mbed library sources
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Revision 501:36015dec7d16, committed 2015-04-07
- Comitter:
- mbed_official
- Date:
- Tue Apr 07 06:45:07 2015 +0100
- Parent:
- 500:04797f1feae2
- Child:
- 502:542898c8d189
- Commit message:
- Synchronized with git revision 40d3a79298f37284b863f90e33e261986340964e
Full URL: https://github.com/mbedmicro/mbed/commit/40d3a79298f37284b863f90e33e261986340964e/
fixes #984: updating to v7.1 of the Nordic SDK.
Changed in this revision
--- a/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.s Tue Mar 31 16:15:13 2015 +0100 +++ b/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.s Tue Apr 07 06:45:07 2015 +0100 @@ -62,7 +62,7 @@ DCD WDT_IRQHandler ;WDT DCD RTC1_IRQHandler ;RTC1 DCD QDEC_IRQHandler ;QDEC - DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP + DCD LPCOMP_IRQHandler ;LPCOMP DCD SWI0_IRQHandler ;SWI0 DCD SWI1_IRQHandler ;SWI1 DCD SWI2_IRQHandler ;SWI2 @@ -85,19 +85,28 @@ ; Reset Handler -NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address -NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask +NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address +NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address +NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask Reset_Handler PROC EXPORT Reset_Handler [WEAK] - IMPORT SystemInit + IMPORT SystemInit IMPORT __main + + MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk + LDR R0, =NRF_POWER_RAMON_ADDRESS LDR R2, [R0] - MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk ORRS R2, R2, R1 STR R2, [R0] - LDR R0, =SystemInit + + LDR R0, =NRF_POWER_RAMONB_ADDRESS + LDR R2, [R0] + ORRS R2, R2, R1 + STR R2, [R0] + + LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 @@ -147,7 +156,7 @@ EXPORT WDT_IRQHandler [WEAK] EXPORT RTC1_IRQHandler [WEAK] EXPORT QDEC_IRQHandler [WEAK] - EXPORT LPCOMP_COMP_IRQHandler [WEAK] + EXPORT LPCOMP_IRQHandler [WEAK] EXPORT SWI0_IRQHandler [WEAK] EXPORT SWI1_IRQHandler [WEAK] EXPORT SWI2_IRQHandler [WEAK] @@ -172,7 +181,7 @@ WDT_IRQHandler RTC1_IRQHandler QDEC_IRQHandler -LPCOMP_COMP_IRQHandler +LPCOMP_IRQHandler SWI0_IRQHandler SWI1_IRQHandler SWI2_IRQHandler
--- a/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h Tue Mar 31 16:15:13 2015 +0100 +++ b/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h Tue Apr 07 06:45:07 2015 +0100 @@ -1,13 +1,13 @@ /* mbed Microcontroller Library - CMSIS * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * + * * A generic CMSIS include header, pulling in LPC407x_8x specifics */ #ifndef MBED_CMSIS_H #define MBED_CMSIS_H -#include "nrf51822.h" +#include "nrf.h" #include "cmsis_nvic.h" #endif
--- a/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h Tue Mar 31 16:15:13 2015 +0100 +++ b/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h Tue Apr 07 06:45:07 2015 +0100 @@ -35,7 +35,7 @@ #define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals #define NVIC_USER_IRQ_OFFSET 16 -#include "nrf51822.h" +#include "nrf51.h" #include "cmsis.h"
--- a/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/compiler_abstraction.h Tue Mar 31 16:15:13 2015 +0100 +++ b/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/compiler_abstraction.h Tue Apr 07 06:45:07 2015 +0100 @@ -1,47 +1,107 @@ -/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. +/* Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * - * The information contained herein is confidential property of Nordic - * Semiconductor ASA.Terms and conditions of usage are described in detail - * in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ - #ifndef _COMPILER_ABSTRACTION_H #define _COMPILER_ABSTRACTION_H /*lint ++flb "Enter library region" */ #if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - #define __current_sp() __get_SP() + + #ifndef __ASM + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #endif + + #ifndef __INLINE + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #endif + + #ifndef __WEAK + #define __WEAK __weak /*!< weak keyword for ARM Compiler */ + #endif + + #define GET_SP() __current_sp() /*!> read current SP function for ARM Compiler */ -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #endif + + #ifndef __INLINE + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #endif + + #ifndef __WEAK + #define __WEAK __weak /*!> define weak function for IAR Compiler */ + #endif + + #define GET_SP() __get_SP() /*!> read current SP function for IAR Compiler */ + +#elif defined ( __GNUC__ ) + + #ifndef __ASM + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #endif + + #ifndef __INLINE + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) /*!< weak keyword for GNU Compiler */ + #endif + + #define GET_SP() gcc_current_sp() /*!> read current SP function for GNU Compiler */ -static __INLINE unsigned int __current_sp(void) - { - register unsigned sp asm("sp"); - return sp; - } - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - + static inline unsigned int gcc_current_sp(void) + { + register unsigned sp asm("sp"); + return sp; + } + +#elif defined ( __TASKING__ ) + + #ifndef __ASM + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #endif + + #ifndef __INLINE + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) /*!< weak keyword for TASKING Compiler */ + #endif + + #define GET_SP() __get_MSP() /*!> read current SP function for TASKING Compiler */ + #endif /*lint --flb "Leave library region" */
--- a/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nordic_global.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,17 +0,0 @@ -#ifndef _NORDIC_GLOBAL_H_ -#define _NORDIC_GLOBAL_H_ - -/* There are no global defines in mbed, so we need to define */ -/* mandatory conditional compilation flags here */ -//#define NRF51 -#ifndef DEBUG_NRF_USER -#define DEBUG_NRF_USER -#endif -#ifndef BLE_STACK_SUPPORT_REQD -#define BLE_STACK_SUPPORT_REQD -#endif -#ifndef BOARD_PCA10001 -#define BOARD_PCA10001 -#endif - -#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h Tue Apr 07 06:45:07 2015 +0100 @@ -0,0 +1,48 @@ +/* Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_H +#define NRF_H + +#ifndef _WIN32 + +/* Family selection for main includes. NRF51 must be selected. */ +#ifdef NRF51 + #include "nrf51.h" + #include "nrf51_bitfields.h" +#else + #error "Device family must be defined. See nrf.h." +#endif /* NRF51 */ + +#include "compiler_abstraction.h" + +#endif /* _WIN32 */ + +#endif /* NRF_H */ +
--- a/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h Tue Mar 31 16:15:13 2015 +0100 +++ b/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h Tue Apr 07 06:45:07 2015 +0100 @@ -1,14 +1,46 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + +/****************************************************************************************************//** + * @file nRF51.h + * + * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for + * nRF51 from Nordic Semiconductor. + * + * @version V522 + * @date 31. October 2014 * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * @note Generated with SVDConv V2.81d + * from CMSIS SVD File 'nRF51.xml' Version 522, + * + * @par Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. * - */ + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + *******************************************************************************************************/ @@ -58,7 +90,7 @@ WDT_IRQn = 16, /*!< 16 WDT */ RTC1_IRQn = 17, /*!< 17 RTC1 */ QDEC_IRQn = 18, /*!< 18 QDEC */ - LPCOMP_COMP_IRQn = 19, /*!< 19 LPCOMP_COMP */ + LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ SWI0_IRQn = 20, /*!< 20 SWI0 */ SWI1_IRQn = 21, /*!< 21 SWI1 */ SWI2_IRQn = 22, /*!< 22 SWI2 */ @@ -77,16 +109,15 @@ /* ================ Processor and Core Peripheral Section ================ */ /* ================================================================================ */ -/* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */ +/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ /** @} */ /* End of group Configuration_of_CMSIS */ -#include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */ -#include "system_nrf51822.h" /*!< nRF51 System */ - +#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ +#include "system_nrf51.h" /*!< nRF51 System */ /* ================================================================================ */ /* ================ Device Specific Peripheral Section ================ */ @@ -125,6 +156,24 @@ } AMLI_RAMPRI_Type; typedef struct { + __IO uint32_t SCK; /*!< Pin select for SCK. */ + __IO uint32_t MOSI; /*!< Pin select for MOSI. */ + __IO uint32_t MISO; /*!< Pin select for MISO. */ +} SPIM_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer. */ + __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */ + __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */ +} SPIM_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer. */ + __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */ + __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */ +} SPIM_TXD_Type; + +typedef struct { __O uint32_t EN; /*!< Enable channel group. */ __O uint32_t DIS; /*!< Disable channel group. */ } PPI_TASKS_CHG_Type; @@ -134,6 +183,15 @@ __IO uint32_t TEP; /*!< Channel task end-point. */ } PPI_CH_Type; +typedef struct { + __I uint32_t PART; /*!< Part code */ + __I uint32_t VARIANT; /*!< Part variant */ + __I uint32_t PACKAGE; /*!< Package option */ + __I uint32_t RAM; /*!< RAM variant */ + __I uint32_t FLASH; /*!< Flash variant */ + __I uint32_t RESERVED[3]; /*!< Reserved */ +} FICR_INFO_Type; + /* ================================================================================ */ /* ================ POWER ================ */ @@ -155,20 +213,26 @@ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ __I uint32_t RESERVED3[61]; __IO uint32_t RESETREAS; /*!< Reset reason. */ - __I uint32_t RESERVED4[63]; + __I uint32_t RESERVED4[9]; + __I uint32_t RAMSTATUS; /*!< Ram status register. */ + __I uint32_t RESERVED5[53]; __O uint32_t SYSTEMOFF; /*!< System off register. */ - __I uint32_t RESERVED5[3]; + __I uint32_t RESERVED6[3]; __IO uint32_t POFCON; /*!< Power failure configuration. */ - __I uint32_t RESERVED6[2]; + __I uint32_t RESERVED7[2]; __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained register. */ - __I uint32_t RESERVED7; + __I uint32_t RESERVED8; __IO uint32_t RAMON; /*!< Ram on/off. */ - __I uint32_t RESERVED8[7]; + __I uint32_t RESERVED9[7]; __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register is a retained register. */ - __I uint32_t RESERVED9[12]; + __I uint32_t RESERVED10[3]; + __IO uint32_t RAMONB; /*!< Ram on/off. */ + __I uint32_t RESERVED11[8]; __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */ + __I uint32_t RESERVED12[291]; + __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */ } NRF_POWER_Type; @@ -193,16 +257,20 @@ __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */ __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */ __I uint32_t RESERVED1; - __IO uint32_t EVENTS_DONE; /*!< Callibration of LFCLK RC oscillator completed. */ - __IO uint32_t EVENTS_CTTO; /*!< Callibration timer timeout. */ + __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */ + __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */ __I uint32_t RESERVED2[124]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[64]; + __I uint32_t RESERVED3[63]; + __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */ __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */ - __I uint32_t RESERVED4[2]; + __I uint32_t RESERVED4; + __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */ __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */ - __I uint32_t RESERVED5[63]; + __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is + triggered. */ + __I uint32_t RESERVED5[62]; __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */ __I uint32_t RESERVED6[7]; __IO uint32_t CTIV; /*!< Calibration timer interval. */ @@ -225,9 +293,10 @@ __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */ __IO uint32_t RLENR0; /*!< Length of RAM region 0. */ __I uint32_t RESERVED1[52]; - __IO uint32_t PROTENSET0; /*!< Protection bit enable set register for low addresses. */ - __IO uint32_t PROTENSET1; /*!< Protection bit enable set register for high addresses. */ - __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug mode. */ + __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */ + __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */ + __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */ + __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */ } NRF_MPU_Type; @@ -299,17 +368,17 @@ __I uint32_t RESERVED1[2]; __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */ __I uint32_t RESERVED2[53]; - __IO uint32_t SHORTS; /*!< Shortcut for the radio. */ + __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */ __I uint32_t RESERVED3[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ __I uint32_t RESERVED4[61]; __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */ - __I uint32_t RESERVED5; + __I uint32_t CD; /*!< Carrier detect. */ __I uint32_t RXMATCH; /*!< Received address. */ __I uint32_t RXCRC; /*!< Received CRC. */ - __IO uint32_t DAI; /*!< Device address match index. */ - __I uint32_t RESERVED6[60]; + __I uint32_t DAI; /*!< Device address match index. */ + __I uint32_t RESERVED5[60]; __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */ __IO uint32_t FREQUENCY; /*!< Frequency. */ __IO uint32_t TXPOWER; /*!< Output power. */ @@ -327,23 +396,23 @@ __IO uint32_t CRCINIT; /*!< CRC initial value. */ __IO uint32_t TEST; /*!< Test features enable register. */ __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */ - __IO uint32_t RSSISAMPLE; /*!< RSSI sample. */ - __I uint32_t RESERVED7; + __I uint32_t RSSISAMPLE; /*!< RSSI sample. */ + __I uint32_t RESERVED6; __I uint32_t STATE; /*!< Current radio state. */ __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */ - __I uint32_t RESERVED8[2]; + __I uint32_t RESERVED7[2]; __IO uint32_t BCC; /*!< Bit counter compare. */ - __I uint32_t RESERVED9[39]; + __I uint32_t RESERVED8[39]; __IO uint32_t DAB[8]; /*!< Device address base segment. */ __IO uint32_t DAP[8]; /*!< Device address prefix. */ __IO uint32_t DACNF; /*!< Device address match configuration. */ - __I uint32_t RESERVED10[56]; + __I uint32_t RESERVED9[56]; __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */ __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */ __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */ __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */ __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */ - __I uint32_t RESERVED11[561]; + __I uint32_t RESERVED10[561]; __IO uint32_t POWER; /*!< Peripheral power control. */ } NRF_RADIO_Type; @@ -375,9 +444,8 @@ __I uint32_t RESERVED4[7]; __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */ __I uint32_t RESERVED5[46]; - __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */ - __I uint32_t RESERVED6[63]; - __IO uint32_t INTEN; /*!< Interrupt enable register. */ + __IO uint32_t SHORTS; /*!< Shortcuts for UART. */ + __I uint32_t RESERVED6[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ __I uint32_t RESERVED7[93]; @@ -390,7 +458,7 @@ __IO uint32_t PSELCTS; /*!< Pin select for CTS. */ __IO uint32_t PSELRXD; /*!< Pin select for RXD. */ __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced. - Once read the character is consummed. If read when no character + Once read the character is consumed. If read when no character available, the UART will stop working. */ __O uint32_t TXD; /*!< TXD register. */ __I uint32_t RESERVED10; @@ -424,7 +492,7 @@ __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */ __IO uint32_t PSELMISO; /*!< Pin select for MISO. */ __I uint32_t RESERVED4; - __IO uint32_t RXD; /*!< RX data. */ + __I uint32_t RXD; /*!< RX data. */ __IO uint32_t TXD; /*!< TX data. */ __I uint32_t RESERVED5; __IO uint32_t FREQUENCY; /*!< SPI frequency */ @@ -462,26 +530,28 @@ __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */ __I uint32_t RESERVED6[4]; __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */ - __I uint32_t RESERVED7[49]; + __I uint32_t RESERVED7[3]; + __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */ + __I uint32_t RESERVED8[45]; __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */ - __I uint32_t RESERVED8[64]; + __I uint32_t RESERVED9[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED9[110]; + __I uint32_t RESERVED10[110]; __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */ - __I uint32_t RESERVED10[14]; + __I uint32_t RESERVED11[14]; __IO uint32_t ENABLE; /*!< Enable two-wire master. */ - __I uint32_t RESERVED11; + __I uint32_t RESERVED12; __IO uint32_t PSELSCL; /*!< Pin select for SCL. */ __IO uint32_t PSELSDA; /*!< Pin select for SDA. */ - __I uint32_t RESERVED12[2]; - __IO uint32_t RXD; /*!< RX data register. */ + __I uint32_t RESERVED13[2]; + __I uint32_t RXD; /*!< RX data register. */ __IO uint32_t TXD; /*!< TX data register. */ - __I uint32_t RESERVED13; + __I uint32_t RESERVED14; __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */ - __I uint32_t RESERVED14[24]; + __I uint32_t RESERVED15[24]; __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */ - __I uint32_t RESERVED15[668]; + __I uint32_t RESERVED16[668]; __IO uint32_t POWER; /*!< Peripheral power control. */ } NRF_TWI_Type; @@ -522,11 +592,11 @@ __I uint32_t RESERVED9[7]; __IO uint32_t RXDPTR; /*!< RX data pointer. */ __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */ - __IO uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */ + __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */ __I uint32_t RESERVED10; __IO uint32_t TXDPTR; /*!< TX data pointer. */ __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */ - __IO uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */ + __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */ __I uint32_t RESERVED11; __IO uint32_t CONFIG; /*!< Configuration register. */ __I uint32_t RESERVED12; @@ -539,6 +609,59 @@ /* ================================================================================ */ +/* ================ SPIM ================ */ +/* ================================================================================ */ + + +/** + * @brief SPI master with easyDMA 1. (SPIM) + */ + +typedef struct { /*!< SPIM Structure */ + __I uint32_t RESERVED0[4]; + __O uint32_t TASKS_START; /*!< Start SPI transaction. */ + __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */ + __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */ + __I uint32_t RESERVED2[56]; + __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */ + __I uint32_t RESERVED4; + __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */ + __I uint32_t RESERVED6[10]; + __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */ + __I uint32_t RESERVED7[44]; + __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */ + __I uint32_t RESERVED8[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED9[125]; + __IO uint32_t ENABLE; /*!< Enable SPIM. */ + __I uint32_t RESERVED10; + SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */ + __I uint32_t RESERVED11; + __I uint32_t RXDDATA; /*!< RXD register. */ + __IO uint32_t TXDDATA; /*!< TXD register. */ + __I uint32_t RESERVED12; + __IO uint32_t FREQUENCY; /*!< SPI frequency. */ + __I uint32_t RESERVED13[3]; + SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */ + __I uint32_t RESERVED14; + SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */ + __I uint32_t RESERVED15; + __IO uint32_t CONFIG; /*!< Configuration register. */ + __I uint32_t RESERVED16[26]; + __IO uint32_t ORC; /*!< Over-read character. */ + __I uint32_t RESERVED17[654]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_SPIM_Type; + + +/* ================================================================================ */ /* ================ GPIOTE ================ */ /* ================================================================================ */ @@ -605,7 +728,8 @@ __O uint32_t TASKS_STOP; /*!< Stop Timer. */ __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */ __O uint32_t TASKS_CLEAR; /*!< Clear timer. */ - __I uint32_t RESERVED0[12]; + __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */ + __I uint32_t RESERVED0[11]; __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */ __I uint32_t RESERVED1[60]; __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ @@ -656,7 +780,7 @@ __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register gives the value of EVTEN. */ __I uint32_t RESERVED4[110]; - __IO uint32_t COUNTER; /*!< Current COUNTER value. */ + __I uint32_t COUNTER; /*!< Current COUNTER value. */ __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */ __I uint32_t RESERVED5[13]; @@ -705,7 +829,7 @@ __I uint32_t RESERVED0[62]; __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */ __I uint32_t RESERVED1[63]; - __IO uint32_t SHORTS; /*!< Shortcut for the RNG. */ + __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */ __I uint32_t RESERVED2[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */ @@ -775,8 +899,8 @@ __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */ __I uint32_t RESERVED5; __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during - resolution. A minimum of 3 bytes must be reserved. */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage + during resolution. A minimum of 3 bytes must be reserved. */ __I uint32_t RESERVED6[697]; __IO uint32_t POWER; /*!< Peripheral power control. */ } NRF_AAR_Type; @@ -802,7 +926,7 @@ __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */ __IO uint32_t EVENTS_ERROR; /*!< Error happened. */ __I uint32_t RESERVED1[61]; - __IO uint32_t SHORTS; /*!< Shortcut for the CCM. */ + __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */ __I uint32_t RESERVED2[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ @@ -811,11 +935,11 @@ __I uint32_t RESERVED4[63]; __IO uint32_t ENABLE; /*!< CCM enable. */ __IO uint32_t MODE; /*!< Operation mode. */ - __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector. */ - __IO uint32_t INPTR; /*!< Pointer to input packet. */ - __IO uint32_t OUTPTR; /*!< Pointer to output packet. */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during - resolution. A minimum of 43 bytes must be reserved. */ + __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */ + __IO uint32_t INPTR; /*!< Pointer to the input packet. */ + __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage + during resolution. A minimum of 43 bytes must be reserved. */ __I uint32_t RESERVED5[697]; __IO uint32_t POWER; /*!< Peripheral power control. */ } NRF_CCM_Type; @@ -871,7 +995,7 @@ ACC register different than zero. */ __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */ __I uint32_t RESERVED1[61]; - __IO uint32_t SHORTS; /*!< Shortcut for the QDEC. */ + __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */ __I uint32_t RESERVED2[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ @@ -904,7 +1028,7 @@ /** - * @brief Wakeup Comparator. (LPCOMP) + * @brief Low power comparator. (LPCOMP) */ typedef struct { /*!< LPCOMP Structure */ @@ -917,7 +1041,7 @@ __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */ __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */ __I uint32_t RESERVED1[60]; - __IO uint32_t SHORTS; /*!< Shortcut for the LPCOMP. */ + __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */ __I uint32_t RESERVED2[64]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ @@ -936,44 +1060,6 @@ /* ================================================================================ */ -/* ================ COMP ================ */ -/* ================================================================================ */ - - -/** - * @brief Comparator. (COMP) - */ - -typedef struct { /*!< COMP Structure */ - __O uint32_t TASKS_START; /*!< Start the comparator. */ - __O uint32_t TASKS_STOP; /*!< Stop the comparator. */ - __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid. */ - __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */ - __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */ - __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */ - __I uint32_t RESERVED1[60]; - __IO uint32_t SHORTS; /*!< Shortcut for the COMP. */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[61]; - __I uint32_t RESULT; /*!< Compare result. */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable the COMP. */ - __IO uint32_t PSEL; /*!< Input pin select. */ - __IO uint32_t REFSEL; /*!< Reference select. */ - __IO uint32_t EXTREFSEL; /*!< External reference select. */ - __I uint32_t RESERVED5[8]; - __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit. */ - __IO uint32_t MODE; /*!< Mode configuration. */ - __I uint32_t RESERVED6[689]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_COMP_Type; - - -/* ================================================================================ */ /* ================ SWI ================ */ /* ================================================================================ */ @@ -1048,7 +1134,13 @@ __I uint32_t PPFC; /*!< Pre-programmed factory code present. */ __I uint32_t RESERVED2; __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */ - __I uint32_t SIZERAMBLOCK[4]; /*!< Size of RAM block in bytes. */ + + union { + __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is + kept for backward compatinility purposes. Use SIZERAMBLOCKS + instead. */ + __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */ + }; __I uint32_t RESERVED3[5]; __I uint32_t CONFIGID; /*!< Configuration identifier. */ __I uint32_t DEVICEID[2]; /*!< Device identifier. */ @@ -1058,9 +1150,12 @@ __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */ __I uint32_t DEVICEADDR[2]; /*!< Device address. */ __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */ - __I uint32_t RESERVED5[15]; + __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit + mode. */ + __I uint32_t RESERVED5[10]; __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit mode. */ + FICR_INFO_Type INFO; /*!< Device info */ } NRF_FICR_Type; @@ -1140,6 +1235,7 @@ #define NRF_SPI1_BASE 0x40004000UL #define NRF_TWI1_BASE 0x40004000UL #define NRF_SPIS1_BASE 0x40004000UL +#define NRF_SPIM1_BASE 0x40004000UL #define NRF_GPIOTE_BASE 0x40006000UL #define NRF_ADC_BASE 0x40007000UL #define NRF_TIMER0_BASE 0x40008000UL @@ -1155,7 +1251,6 @@ #define NRF_RTC1_BASE 0x40011000UL #define NRF_QDEC_BASE 0x40012000UL #define NRF_LPCOMP_BASE 0x40013000UL -#define NRF_COMP_BASE 0x40013000UL #define NRF_SWI_BASE 0x40014000UL #define NRF_NVMC_BASE 0x4001E000UL #define NRF_PPI_BASE 0x4001F000UL @@ -1180,6 +1275,7 @@ #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE) #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) @@ -1195,7 +1291,6 @@ #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) -#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE) #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE) #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) @@ -1214,3 +1309,4 @@ #endif /* nRF51_H */ +
--- a/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51822.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,27 +0,0 @@ -/* mbed Microcontroller Library - - * Copyright (c) 2013 Nordic Semiconductor. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#ifndef NRF_H -#define NRF_H - -#include "nordic_global.h" -#include "compiler_abstraction.h" -#include "nrf51.h" -#include "nrf51_bitfields.h" -#endif /* NRF_H */ -
--- a/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h Tue Mar 31 16:15:13 2015 +0100 +++ b/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h Tue Apr 07 06:45:07 2015 +0100 @@ -1,22 +1,38 @@ -/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. +/* Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ - - #ifndef __NRF51_BITS_H #define __NRF51_BITS_H /*lint ++flb "Enter library region */ -//#include <core_cm0.h> +#include <core_cm0.h> /* Peripheral: AAR */ /* Description: Accelerated Address Resolver. */ @@ -213,124 +229,604 @@ /* Register: AMLI_RAMPRI_CPU0 */ /* Description: Configurable priority configuration register for CPU0. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Register: AMLI_RAMPRI_SPIS1 */ /* Description: Configurable priority configuration register for SPIS1. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Register: AMLI_RAMPRI_RADIO */ /* Description: Configurable priority configuration register for RADIO. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Register: AMLI_RAMPRI_ECB */ /* Description: Configurable priority configuration register for ECB. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Register: AMLI_RAMPRI_CCM */ /* Description: Configurable priority configuration register for CCM. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Register: AMLI_RAMPRI_AAR */ /* Description: Configurable priority configuration register for AAR. */ +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + /* Bits 15..12 : Configuration field for RAM block 3. */ #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 11..8 : Configuration field for RAM block 2. */ #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 7..4 : Configuration field for RAM block 1. */ #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ /* Bits 3..0 : Configuration field for RAM block 0. */ #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ /* Peripheral: CCM */ /* Description: AES CCM Mode Encryption. */ /* Register: CCM_SHORTS */ -/* Description: Shortcut for the CCM. */ - -/* Bit 0 : Short-cut between ENDKSGEN event and CRYPT task. */ +/* Description: Shortcuts for the CCM. */ + +/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */ @@ -486,6 +982,15 @@ #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ +/* Register: CLOCK_HFCLKRUN */ +/* Description: Task HFCLKSTART trigger status. */ + +/* Bit 0 : Task HFCLKSTART trigger status. */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */ + /* Register: CLOCK_HFCLKSTAT */ /* Description: High frequency clock status. */ @@ -501,6 +1006,15 @@ #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */ #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */ +/* Register: CLOCK_LFCLKRUN */ +/* Description: Task LFCLKSTART triggered status. */ + +/* Bit 0 : Task LFCLKSTART triggered status. */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */ + /* Register: CLOCK_LFCLKSTAT */ /* Description: Low frequency clock status. */ @@ -517,6 +1031,16 @@ #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */ #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */ +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ + +/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ + /* Register: CLOCK_LFCLKSRC */ /* Description: Clock source for the LFCLK clock. */ @@ -540,197 +1064,8 @@ /* Bits 7..0 : External Xtal frequency selection. */ #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ -#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used. */ -#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used. */ - - -/* Peripheral: COMP */ -/* Description: Comparator. */ - -/* Register: COMP_SHORTS */ -/* Description: Shortcut for the COMP. */ - -/* Bit 4 : Short-cut between CROSS event and STOP task. */ -#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ -#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ -#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Short-cut between UP event and STOP task. */ -#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ -#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ -#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 2 : Short-cut between DOWN event and STOP task. */ -#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ -#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ -#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 1 : Short-cut between RADY event and STOP task. */ -#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ -#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ -#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Short-cut between READY event and SAMPLE task. */ -#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ -#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ -#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ -#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: COMP_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 3 : Enable interrupt on CROSS event. */ -#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on UP event. */ -#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ -#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ -#define COMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on DOWN event. */ -#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on READY event. */ -#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ -#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define COMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: COMP_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 3 : Disable interrupt on CROSS event. */ -#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on UP event. */ -#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ -#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ -#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on DOWN event. */ -#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on READY event. */ -#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ -#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: COMP_RESULT */ -/* Description: Compare result. */ - -/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ -#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ -#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ -#define COMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */ -#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */ - -/* Register: COMP_ENABLE */ -/* Description: Enable the COMP. */ - -/* Bits 1..0 : Enable or disable COMP. */ -#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define COMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled COMP. */ -#define COMP_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable COMP. */ - -/* Register: COMP_PSEL */ -/* Description: Input pin select. */ - -/* Bits 2..0 : Analog input pin select. */ -#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ -#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ -#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */ -#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */ - -/* Register: COMP_REFSEL */ -/* Description: Reference select. */ - -/* Bits 2..0 : Reference select. */ -#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ -#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define COMP_REFSEL_REFSEL_Int1V5 (0UL) /*!< Use internal 1V5 as reference. */ -#define COMP_REFSEL_REFSEL_Int2V0 (1UL) /*!< Use internal 2V0 as reference. */ -#define COMP_REFSEL_REFSEL_Int2V5 (2UL) /*!< Use internal 2V5 as reference. */ -#define COMP_REFSEL_REFSEL_Supply (4UL) /*!< Use supply as reference. */ -#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< Use external analog reference as reference. */ - -/* Register: COMP_EXTREFSEL */ -/* Description: External reference select. */ - -/* Bit 0 : External analog reference pin selection. */ -#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ -#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */ - -/* Register: COMP_TH */ -/* Description: Threshold configuration for hysteresis unit. */ - -/* Bits 13..8 : VDOWN configuration. */ -#define COMP_TH_THDOWN_Pos (8UL) /*!< Position of THDOWN field. */ -#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ - -/* Bits 5..0 : VUP configuration. */ -#define COMP_TH_THUP_Pos (0UL) /*!< Position of THUP field. */ -#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ - -/* Register: COMP_MODE */ -/* Description: Mode configuration. */ - -/* Bit 8 : Main operation mode. */ -#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ -#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ -#define COMP_MODE_MAIN_Single (0UL) /*!< Single ended mode. */ -#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode. */ - -/* Bits 1..0 : Speed and power mode. */ -#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ -#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ -#define COMP_MODE_SP_Low (0UL) /*!< Low power mode. */ -#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode. */ -#define COMP_MODE_SP_High (2UL) /*!< High speed mode. */ - -/* Register: COMP_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define COMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define COMP_POWER_POWER_Msk (0x1UL << COMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define COMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define COMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ +#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */ +#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */ /* Peripheral: ECB */ @@ -821,6 +1156,66 @@ #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */ #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */ +/* Bit 0 : Override default values for NRF_1Mbit mode. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */ + +/* Register: FICR_INFO_PART */ +/* Description: Part code */ + +/* Bits 31..0 : Part code */ +#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ +#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N51822 (0x51822UL) /*!< nRF51822 */ +#define FICR_INFO_PART_PART_N51422 (0x51422UL) /*!< nRF51422 */ +#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_VARIANT */ +/* Description: Part variant */ + +/* Bits 31..0 : Part variant */ +#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /*!< nRF51-C (XLR3) */ +#define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /*!< nRF51-D (L3) */ +#define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /*!< nRF51-E (XLR3P) */ +#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_PACKAGE */ +/* Description: Package option */ + +/* Bits 31..0 : Package option */ +#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /*!< 48-pin QFN with 31 GPIO */ +#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /*!< nRF51x22 CDxx - WLCSP 56 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /*!< nRF51x22 CExx - WLCSP 62 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /*!< nRF51x22 CFxx - WLCSP 62 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /*!< nRF51x22 CTxx - WLCSP 62 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_RAM */ +/* Description: RAM variant */ + +/* Bits 31..0 : RAM variant */ +#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ +#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ +#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ +#define FICR_INFO_RAM_RAM_K16 (16UL) /*!< 16 kByte RAM. */ +#define FICR_INFO_RAM_RAM_K32 (32UL) /*!< 32 kByte RAM. */ + +/* Register: FICR_INFO_FLASH */ +/* Description: Flash variant */ + +/* Bits 31..0 : Flash variant */ +#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ +#define FICR_INFO_FLASH_FLASH_K128 (128UL) /*!< 128 kByte FLASH. */ +#define FICR_INFO_FLASH_FLASH_K256 (256UL) /*!< 256 kByte FLASH. */ + /* Peripheral: GPIO */ /* Description: General purpose input and output. */ @@ -2477,36 +2872,36 @@ /* Peripheral: LPCOMP */ -/* Description: Wakeup Comparator. */ +/* Description: Low power comparator. */ /* Register: LPCOMP_SHORTS */ -/* Description: Shortcut for the LPCOMP. */ - -/* Bit 4 : Short-cut between CROSS event and STOP task. */ +/* Description: Shortcuts for the LPCOMP. */ + +/* Bit 4 : Shortcut between CROSS event and STOP task. */ #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ -/* Bit 3 : Short-cut between UP event and STOP task. */ +/* Bit 3 : Shortcut between UP event and STOP task. */ #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ -/* Bit 2 : Short-cut between DOWN event and STOP task. */ +/* Bit 2 : Shortcut between DOWN event and STOP task. */ #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ -/* Bit 1 : Short-cut between RADY event and STOP task. */ +/* Bit 1 : Shortcut between RADY event and STOP task. */ #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ -/* Bit 0 : Short-cut between READY event and SAMPLE task. */ +/* Bit 0 : Shortcut between READY event and SAMPLE task. */ #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ @@ -2613,13 +3008,13 @@ /* Bits 2..0 : Reference select. */ #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use analog supply with a 1/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use analog supply with a 2/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use analog supply with a 3/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use analog supply with a 4/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use analog supply with a 5/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use analog supply with a 6/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use analog supply with a 7/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */ #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */ /* Register: LPCOMP_EXTREFSEL */ @@ -2669,11 +3064,11 @@ #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ -/* Bit 19 : LPCOMP_COMP region configuration. */ -#define MPU_PERR0_LPCOMP_COMP_Pos (19UL) /*!< Position of LPCOMP_COMP field. */ -#define MPU_PERR0_LPCOMP_COMP_Msk (0x1UL << MPU_PERR0_LPCOMP_COMP_Pos) /*!< Bit mask of LPCOMP_COMP field. */ -#define MPU_PERR0_LPCOMP_COMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_LPCOMP_COMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ +/* Bit 19 : LPCOMP region configuration. */ +#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */ +#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ /* Bit 18 : QDEC region configuration. */ #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */ @@ -2784,7 +3179,7 @@ #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ /* Register: MPU_PROTENSET0 */ -/* Description: Protection bit enable set register for low addresses. */ +/* Description: Erase and write protection bit enable set register. */ /* Bit 31 : Protection enable for region 31. */ #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */ @@ -3011,7 +3406,7 @@ #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */ /* Register: MPU_PROTENSET1 */ -/* Description: Protection bit enable set register for high addresses. */ +/* Description: Erase and write protection bit enable set register. */ /* Bit 31 : Protection enable for region 63. */ #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */ @@ -3238,7 +3633,7 @@ #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */ /* Register: MPU_DISABLEINDEBUG */ -/* Description: Disable protection mechanism in debug mode. */ +/* Description: Disable erase and write protection mechanism in debug mode. */ /* Bit 0 : Disable protection mechanism in debug mode. */ #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ @@ -3246,6 +3641,14 @@ #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */ #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */ +/* Register: MPU_PROTBLOCKSIZE */ +/* Description: Erase and write protection block size. */ + +/* Bits 1..0 : Erase and write protection block size. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */ + /* Peripheral: NVMC */ /* Description: Non Volatile Memory Controller. */ @@ -3342,6 +3745,33 @@ #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +/* Register: POWER_RAMSTATUS */ +/* Description: Ram status register. */ + +/* Bit 3 : RAM block 3 status. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */ + +/* Bit 2 : RAM block 2 status. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */ + +/* Bit 1 : RAM block 1 status. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */ + +/* Bit 0 : RAM block 0 status. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */ + /* Register: POWER_SYSTEMOFF */ /* Description: System off register. */ @@ -3377,18 +3807,6 @@ /* Register: POWER_RAMON */ /* Description: Ram on/off. */ -/* Bit 19 : RAM block 3 behaviour in OFF mode. */ -#define POWER_RAMON_OFFRAM3_Pos (19UL) /*!< Position of OFFRAM3 field. */ -#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ -#define POWER_RAMON_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */ -#define POWER_RAMON_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */ - -/* Bit 18 : RAM block 2 behaviour in OFF mode. */ -#define POWER_RAMON_OFFRAM2_Pos (18UL) /*!< Position of OFFRAM2 field. */ -#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ -#define POWER_RAMON_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */ -#define POWER_RAMON_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */ - /* Bit 17 : RAM block 1 behaviour in OFF mode. */ #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ @@ -3401,18 +3819,6 @@ #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */ #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */ -/* Bit 3 : RAM block 3 behaviour in ON mode. */ -#define POWER_RAMON_ONRAM3_Pos (3UL) /*!< Position of ONRAM3 field. */ -#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ -#define POWER_RAMON_ONRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in ON mode. */ -#define POWER_RAMON_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */ - -/* Bit 2 : RAM block 2 behaviour in ON mode. */ -#define POWER_RAMON_ONRAM2_Pos (2UL) /*!< Position of ONRAM2 field. */ -#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ -#define POWER_RAMON_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */ -#define POWER_RAMON_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */ - /* Bit 1 : RAM block 1 behaviour in ON mode. */ #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ @@ -3428,12 +3834,39 @@ /* Register: POWER_RESET */ /* Description: Pin reset functionality configuration register. This register is a retained register. */ -/* Bit 0 : Enable pin reset in debug interface mode. */ +/* Bit 0 : Enable or disable pin reset in debug interface mode. */ #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */ #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */ +/* Register: POWER_RAMONB */ +/* Description: Ram on/off. */ + +/* Bit 17 : RAM block 3 behaviour in OFF mode. */ +#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */ +#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */ + +/* Bit 16 : RAM block 2 behaviour in OFF mode. */ +#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */ +#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */ + +/* Bit 1 : RAM block 3 behaviour in ON mode. */ +#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */ +#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */ + +/* Bit 0 : RAM block 2 behaviour in ON mode. */ +#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */ +#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */ + /* Register: POWER_DCDCEN */ /* Description: DCDC converter enable configuration register. */ @@ -3443,6 +3876,21 @@ #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */ #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */ +/* Register: POWER_DCDCFORCE */ +/* Description: DCDC power-up force register. */ + +/* Bit 1 : DCDC power-up force on. */ +#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */ +#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */ +#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */ +#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */ + +/* Bit 0 : DCDC power-up force off. */ +#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ +#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ +#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */ +#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */ + /* Peripheral: PPI */ /* Description: PPI controller. */ @@ -4372,15 +4820,15 @@ /* Description: Rotary decoder. */ /* Register: QDEC_SHORTS */ -/* Description: Shortcut for the QDEC. */ - -/* Bit 1 : Short-cut between SAMPLERDY event and STOP task. */ +/* Description: Shortcuts for the QDEC. */ + +/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ -/* Bit 0 : Short-cut between REPORTRDY event and READCLRACC task. */ +/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */ @@ -4501,9 +4949,9 @@ /* Register: QDEC_LEDPRE */ /* Description: Time LED is switched ON before the sample. */ -/* Bits 7..0 : Period in us the LED in switched on prior to sampling. */ +/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */ #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ -#define QDEC_LEDPRE_LEDPRE_Msk (0xFFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ /* Register: QDEC_ACCDBL */ /* Description: Accumulated double (error) transitions register. */ @@ -4533,7 +4981,7 @@ /* Description: The radio. */ /* Register: RADIO_SHORTS */ -/* Description: Shortcut for the radio. */ +/* Description: Shortcuts for the radio. */ /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ @@ -4724,6 +5172,13 @@ #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */ #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */ +/* Register: RADIO_CD */ +/* Description: Carrier detect. */ + +/* Bit 0 : Carrier detect. */ +#define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */ +#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */ + /* Register: RADIO_RXMATCH */ /* Description: Received address. */ @@ -4741,7 +5196,7 @@ /* Register: RADIO_DAI */ /* Description: Device address match index. */ -/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that got an address match. */ +/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */ #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ @@ -4920,10 +5375,10 @@ /* Description: CRC configuration. */ /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */ -#define RADIO_CRCCNF_SKIP_ADDR_Pos (8UL) /*!< Position of SKIP_ADDR field. */ -#define RADIO_CRCCNF_SKIP_ADDR_Msk (0x1UL << RADIO_CRCCNF_SKIP_ADDR_Pos) /*!< Bit mask of SKIP_ADDR field. */ -#define RADIO_CRCCNF_SKIP_ADDR_Include (0UL) /*!< Include packet address in CRC calculation. */ -#define RADIO_CRCCNF_SKIP_ADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */ /* Bits 1..0 : CRC length. Decision point: START task. */ #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ @@ -4936,9 +5391,9 @@ /* Register: RADIO_CRCPOLY */ /* Description: CRC polynomial. */ -/* Bits 23..1 : CRC polynomial. Decision point: START task. */ -#define RADIO_CRCPOLY_CRCPOLY_Pos (1UL) /*!< Position of CRCPOLY field. */ -#define RADIO_CRCPOLY_CRCPOLY_Msk (0x7FFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ +/* Bits 23..0 : CRC polynomial. Decision point: START task. */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ /* Register: RADIO_CRCINIT */ /* Description: CRC initial value. */ @@ -4951,16 +5406,16 @@ /* Description: Test features enable register. */ /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */ -#define RADIO_TEST_PLL_LOCK_Pos (1UL) /*!< Position of PLL_LOCK field. */ -#define RADIO_TEST_PLL_LOCK_Msk (0x1UL << RADIO_TEST_PLL_LOCK_Pos) /*!< Bit mask of PLL_LOCK field. */ -#define RADIO_TEST_PLL_LOCK_Disabled (0UL) /*!< PLL lock disabled. */ -#define RADIO_TEST_PLL_LOCK_Enabled (1UL) /*!< PLL lock enabled. */ +#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */ +#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */ +#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */ +#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */ /* Bit 0 : Constant carrier. Decision point: TXEN task. */ -#define RADIO_TEST_CONST_CARRIER_Pos (0UL) /*!< Position of CONST_CARRIER field. */ -#define RADIO_TEST_CONST_CARRIER_Msk (0x1UL << RADIO_TEST_CONST_CARRIER_Pos) /*!< Bit mask of CONST_CARRIER field. */ -#define RADIO_TEST_CONST_CARRIER_Disabled (0UL) /*!< Constant carrier disabled. */ -#define RADIO_TEST_CONST_CARRIER_Enabled (1UL) /*!< Constant carrier enabled. */ +#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */ +#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */ +#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */ +#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */ /* Register: RADIO_TIFS */ /* Description: Inter Frame Spacing in microseconds. */ @@ -4995,9 +5450,9 @@ /* Register: RADIO_DATAWHITEIV */ /* Description: Data whitening initial value. */ -/* Bits 5..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */ +/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */ #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ -#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x3FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ /* Register: RADIO_DAP */ /* Description: Device address prefix. */ @@ -5092,28 +5547,28 @@ /* Register: RADIO_OVERRIDE0 */ /* Description: Trim value override register 0. */ -/* Bits 31..0 : Trim value override register 0. */ +/* Bits 31..0 : Trim value override 0. */ #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */ #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */ /* Register: RADIO_OVERRIDE1 */ /* Description: Trim value override register 1. */ -/* Bits 31..0 : Trim value override register 1. */ +/* Bits 31..0 : Trim value override 1. */ #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */ #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */ /* Register: RADIO_OVERRIDE2 */ /* Description: Trim value override register 2. */ -/* Bits 31..0 : Trim value override register 2. */ +/* Bits 31..0 : Trim value override 2. */ #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */ #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */ /* Register: RADIO_OVERRIDE3 */ /* Description: Trim value override register 3. */ -/* Bits 31..0 : Trim value override register 3. */ +/* Bits 31..0 : Trim value override 3. */ #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */ #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */ @@ -5126,7 +5581,7 @@ #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */ #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */ -/* Bits 27..0 : Trim value override register 4. */ +/* Bits 27..0 : Trim value override 4. */ #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */ #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */ @@ -5144,9 +5599,9 @@ /* Description: Random Number Generator. */ /* Register: RNG_SHORTS */ -/* Description: Shortcut for the RNG. */ - -/* Bit 0 : Short-cut between VALRDY event and STOP task. */ +/* Description: Shortcuts for the RNG. */ + +/* Bit 0 : Shortcut between VALRDY event and STOP task. */ #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ @@ -5542,6 +5997,211 @@ #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ +/* Peripheral: SPIM */ +/* Description: SPI master with easyDMA 1. */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcuts for SPIM. */ + +/* Bit 17 : Shortcut between END event and START task. */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: SPIM_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 19 : Enable interrupt on STARTED event. */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 8 : Enable interrupt on ENDTX event. */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 6 : Enable interrupt on END event. */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 4 : Enable interrupt on ENDRX event. */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on STOPPED event. */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: SPIM_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 19 : Disable interrupt on STARTED event. */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 8 : Disable interrupt on ENDTX event. */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 6 : Disable interrupt on END event. */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 4 : Disable interrupt on ENDRX event. */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on STOPPED event. */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM. */ + +/* Bits 3..0 : Enable or disable SPIM. */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */ +#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */ + +/* Register: SPIM_RXDDATA */ +/* Description: RXD register. */ + +/* Bits 7..0 : RX data received. Double buffered. */ +#define SPIM_RXDDATA_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPIM_TXDDATA */ +/* Description: TXD register. */ + +/* Bits 7..0 : TX data to send. Double buffered. */ +#define SPIM_TXDDATA_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency. */ + +/* Bits 31..0 : SPI master data rate. */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 2 : Serial clock (SCK) polarity. */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ + +/* Bit 1 : Serial clock (SCK) phase. */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ + +/* Bit 0 : Bit order. */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ + +/* Register: SPIM_ORC */ +/* Description: Over-read character. */ + +/* Bits 7..0 : Over-read character. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + +/* Register: SPIM_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer. */ + +/* Bits 31..0 : Data pointer. */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of buffer bytes to receive. */ + +/* Bits 7..0 : Maximum number of buffer bytes to receive. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes received in the last transaction. */ + +/* Bits 7..0 : Number of bytes received in the last transaction. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer. */ + +/* Bits 31..0 : Data pointer. */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Maximum number of buffer bytes to send. */ + +/* Bits 7..0 : Maximum number of buffer bytes to send. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes sent in the last transaction. */ + +/* Bits 7..0 : Number of bytes sent in the last transaction. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + /* Peripheral: SPIS */ /* Description: SPI slave 1. */ @@ -5905,6 +6565,13 @@ /* Register: TWI_INTENSET */ /* Description: Interrupt enable set register. */ +/* Bit 18 : Enable interrupt on SUSPENDED event. */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */ + /* Bit 14 : Enable interrupt on BB event. */ #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ @@ -5943,6 +6610,13 @@ /* Register: TWI_INTENCLR */ /* Description: Interrupt enable clear register. */ +/* Bit 18 : Disable interrupt on SUSPENDED event. */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */ + /* Bit 14 : Disable interrupt on BB event. */ #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ @@ -6049,7 +6723,7 @@ /* Description: Universal Asynchronous Receiver/Transmitter. */ /* Register: UART_SHORTS */ -/* Description: Shortcuts for TWI. */ +/* Description: Shortcuts for UART. */ /* Bit 4 : Shortcut between NCTS event and the STOPRX task. */ #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ @@ -6194,7 +6868,7 @@ #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */ /* Register: UART_RXD */ -/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consummed. If read when no character available, the UART will stop working. */ +/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */ /* Bits 7..0 : RX data from previous transfer. Double buffered. */ #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf_delay.h Tue Apr 07 06:45:07 2015 +0100 @@ -0,0 +1,74 @@ +#ifndef _NRF_DELAY_H +#define _NRF_DELAY_H + +// #include "nrf.h" + +/*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */ +#if defined ( __CC_ARM ) +static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us) +{ +loop + SUBS R0, R0, #1 + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + BNE loop + BX LR +} +#elif defined ( __ICCARM__ ) +static void __INLINE nrf_delay_us(uint32_t volatile number_of_us) +{ +__ASM ( +"loop:\n\t" + " SUBS R0, R0, #1\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " NOP\n\t" + " BNE loop\n\t"); +} +#elif defined ( __GNUC__ ) +static void __INLINE nrf_delay_us(uint32_t volatile number_of_us) +{ + do + { + __ASM volatile ( + "NOP\n\t" + "NOP\n\t" + "NOP\n\t" + "NOP\n\t" + "NOP\n\t" + "NOP\n\t" + "NOP\n\t" + "NOP\n\t" + "NOP\n\t" + "NOP\n\t" + "NOP\n\t" + "NOP\n\t" + "NOP\n\t" + "NOP\n\t" + ); + } while (--number_of_us); +} +#endif + +void nrf_delay_ms(uint32_t volatile number_of_ms); + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.c Tue Apr 07 06:45:07 2015 +0100 @@ -0,0 +1,134 @@ +/* Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* NOTE: Template files (including this one) are application specific and therefore expected to + be copied into the application project folder prior to its use! */ + +#include <stdint.h> +#include <stdbool.h> +#include "nrf.h" +#include "system_nrf51.h" + +/*lint ++flb "Enter library region" */ + +#define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */ + +static bool is_manual_peripheral_setup_needed(void); +static bool is_disabled_in_debug_needed(void); + + +#if defined ( __CC_ARM ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; +#elif defined ( __ICCARM__ ) + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK; +#elif defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; +#endif + +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = __SYSTEM_CLOCK; +} + +void SystemInit(void) +{ + /* If desired, switch off the unused RAM to lower consumption by the use of RAMON register. + It can also be done in the application main() function. */ + + /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required + to enable the use of peripherals" found at Product Anomaly document for your device found at + https://www.nordicsemi.com/. The side effect of executing these instructions in the devices + that do not need it is that the new peripherals in the second generation devices (LPCOMP for + example) will not be available. */ + if (is_manual_peripheral_setup_needed()) + { + *(uint32_t volatile *)0x40000504 = 0xC007FFDF; + *(uint32_t volatile *)0x40006C18 = 0x00008000; + } + + /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG + register is incorrect" found at Product Anomaly document four your device found at + https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */ + if (is_disabled_in_debug_needed()) + { + NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos; + } + + // Start the external 32khz crystal oscillator. + +#if defined(TARGET_DELTA_DFCM_NNN40) || defined(TARGET_HRM1017) + NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos); +#else + NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos); +#endif + NRF_CLOCK->EVENTS_LFCLKSTARTED = 0; + NRF_CLOCK->TASKS_LFCLKSTART = 1; + + // Wait for the external oscillator to start up. + while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) { + // Do nothing. + } +} + +static bool is_manual_peripheral_setup_needed(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + } + + return false; +} + +static bool is_disabled_in_debug_needed(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + } + + return false; +} + +/*lint --flb "Leave library region" */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.h Tue Apr 07 06:45:07 2015 +0100 @@ -0,0 +1,68 @@ +/* Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef SYSTEM_NRF51_H +#define SYSTEM_NRF51_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF51_H */
--- a/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.c Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,116 +0,0 @@ -/* mbed Microcontroller Library - - * Copyright (c) 2015 Nordic Semiconductor. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#include <stdint.h> -#include <stdbool.h> -#include "nrf51822.h" -#include "system_nrf51822.h" - -#define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */ - -static bool is_manual_peripheral_setup_needed(void); -static bool is_disabled_in_debug_needed(void); - - -#if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; -#elif defined ( __ICCARM__ ) - __root uint32_t SystemCoreClock = __SYSTEM_CLOCK; -#elif defined ( __GNUC__ ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; -#endif - -void SystemCoreClockUpdate(void) -{ - SystemCoreClock = __SYSTEM_CLOCK; -} - -void SystemInit(void) -{ - /* If desired, switch off the unused RAM to lower consumption by the use of RAMON register. - It can also be done in the application main() function. */ - - // Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required - // to enable the use of peripherals" found at Product Anomaly document for your device found at - // https://www.nordicsemi.com/. The side effect of executing these instructions in the devices - // that do not need it is that the new peripherals in the second generation devices (LPCOMP for - // example) will not be available. - if (is_manual_peripheral_setup_needed()) - { - *(uint32_t volatile *)0x40000504 = 0xC007FFDF; - *(uint32_t volatile *)0x40006C18 = 0x00008000; - } - - // Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG - // register is incorrect" found at Product Anomaly document four your device found at - // https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. - if (is_disabled_in_debug_needed()) - { - NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos; - } - - // Start the external 32khz crystal oscillator. - -#if defined(TARGET_DELTA_DFCM_NNN40) || defined(TARGET_HRM1017) - NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos); -#else - NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos); -#endif - NRF_CLOCK->EVENTS_LFCLKSTARTED = 0; - NRF_CLOCK->TASKS_LFCLKSTART = 1; - - // Wait for the external oscillator to start up. - while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) { - // Do nothing. - } -} - -static bool is_manual_peripheral_setup_needed(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - } - - return false; -} - -static bool is_disabled_in_debug_needed(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - } - - return false; -} -
--- a/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51822.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,58 +0,0 @@ -/* mbed Microcontroller Library - - * Copyright (c) 2013 Nordic Semiconductor. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#ifndef SYSTEM_NRF51_H -#define SYSTEM_NRF51_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <stdint.h> - - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_NRF51_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/crc16/crc16.h Tue Apr 07 06:45:07 2015 +0100 @@ -0,0 +1,52 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup crc_compute CRC compute + * @{ + * @ingroup hci_transport + * + * @brief This module implements the CRC-16 calculation in the blocks. + */ + +#ifndef CRC16_H__ +#define CRC16_H__ + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/**@brief Function for calculating CRC-16 in blocks. + * + * Feed each consecutive data block into this function, along with the current value of p_crc as + * returned by the previous call of this function. The first call of this function should pass NULL + * as the initial value of the crc in p_crc. + * + * @param[in] p_data The input data block for computation. + * @param[in] size The size of the input data block in bytes. + * @param[in] p_crc The previous calculated CRC-16 value or NULL if first call. + * + * @return The updated CRC-16 value, based on the input supplied. + */ +uint16_t crc16_compute(const uint8_t * p_data, uint32_t size, const uint16_t * p_crc); + +#ifdef __cplusplus +} +#endif + + +#endif // CRC16_H__ + +/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/scheduler/app_scheduler.h Tue Apr 07 06:45:07 2015 +0100 @@ -0,0 +1,152 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup app_scheduler Scheduler + * @{ + * @ingroup app_common + * + * @brief The scheduler is used for transferring execution from the interrupt context to the main + * context. + * + * @details See @ref seq_diagrams_sched for sequence diagrams illustrating the flow of events + * when using the Scheduler. + * + * @section app_scheduler_req Requirements: + * + * @subsection main_context_logic Logic in main context: + * + * - Define an event handler for each type of event expected. + * - Initialize the scheduler by calling the APP_SCHED_INIT() macro before entering the + * application main loop. + * - Call app_sched_execute() from the main loop each time the application wakes up because of an + * event (typically when sd_app_evt_wait() returns). + * + * @subsection int_context_logic Logic in interrupt context: + * + * - In the interrupt handler, call app_sched_event_put() + * with the appropriate data and event handler. This will insert an event into the + * scheduler's queue. The app_sched_execute() function will pull this event and call its + * handler in the main context. + * + * @if (SD_S110 && !SD_S310) + * For an example usage of the scheduler, see the implementations of + * @ref ble_sdk_app_hids_mouse and @ref ble_sdk_app_hids_keyboard. + * @endif + * + * @image html scheduler_working.jpg The high level design of the scheduler + */ + +#ifndef APP_SCHEDULER_H__ +#define APP_SCHEDULER_H__ + +#include <stdint.h> +#include "app_error.h" + +#define APP_SCHED_EVENT_HEADER_SIZE 8 /**< Size of app_scheduler.event_header_t (only for use inside APP_SCHED_BUF_SIZE()). */ + +/**@brief Compute number of bytes required to hold the scheduler buffer. + * + * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler. + * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events + * that can be scheduled for execution). + * + * @return Required scheduler buffer size (in bytes). + */ +#define APP_SCHED_BUF_SIZE(EVENT_SIZE, QUEUE_SIZE) \ + (((EVENT_SIZE) + APP_SCHED_EVENT_HEADER_SIZE) * ((QUEUE_SIZE) + 1)) + +/**@brief Scheduler event handler type. */ +typedef void (*app_sched_event_handler_t)(void * p_event_data, uint16_t event_size); + +/**@brief Macro for initializing the event scheduler. + * + * @details It will also handle dimensioning and allocation of the memory buffer required by the + * scheduler, making sure the buffer is correctly aligned. + * + * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler. + * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events + * that can be scheduled for execution). + * + * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it + * several times as long as it is from the same location, e.g. to do a reinitialization). + */ +#define APP_SCHED_INIT(EVENT_SIZE, QUEUE_SIZE) \ + do \ + { \ + static uint32_t APP_SCHED_BUF[CEIL_DIV(APP_SCHED_BUF_SIZE((EVENT_SIZE), (QUEUE_SIZE)), \ + sizeof(uint32_t))]; \ + uint32_t ERR_CODE = app_sched_init((EVENT_SIZE), (QUEUE_SIZE), APP_SCHED_BUF); \ + APP_ERROR_CHECK(ERR_CODE); \ + } while (0) + +/**@brief Function for initializing the Scheduler. + * + * @details It must be called before entering the main loop. + * + * @param[in] max_event_size Maximum size of events to be passed through the scheduler. + * @param[in] queue_size Number of entries in scheduler queue (i.e. the maximum number of + * events that can be scheduled for execution). + * @param[in] p_evt_buffer Pointer to memory buffer for holding the scheduler queue. It must + * be dimensioned using the APP_SCHED_BUFFER_SIZE() macro. The buffer + * must be aligned to a 4 byte boundary. + * + * @note Normally initialization should be done using the APP_SCHED_INIT() macro, as that will both + * allocate the scheduler buffer, and also align the buffer correctly. + * + * @retval NRF_SUCCESS Successful initialization. + * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte + * boundary). + */ +uint32_t app_sched_init(uint16_t max_event_size, uint16_t queue_size, void * p_evt_buffer); + +/**@brief Function for executing all scheduled events. + * + * @details This function must be called from within the main loop. It will execute all events + * scheduled since the last time it was called. + */ +void app_sched_execute(void); + +/**@brief Function for scheduling an event. + * + * @details Puts an event into the event queue. + * + * @param[in] p_event_data Pointer to event data to be scheduled. + * @param[in] event_size Size of event data to be scheduled. + * @param[in] handler Event handler to receive the event. + * + * @return NRF_SUCCESS on success, otherwise an error code. + */ +uint32_t app_sched_event_put(void * p_event_data, + uint16_t event_size, + app_sched_event_handler_t handler); + +#ifdef APP_SCHEDULER_WITH_PAUSE +/**@brief A function to pause the scheduler. + * + * @details When the scheduler is paused events are not pulled from the scheduler queue for + * processing. The function can be called multiple times. To unblock the scheduler the + * function @ref app_sched_resume has to be called the same number of times. + */ +void app_sched_pause(void); + +/**@brief A function to resume a scheduler. + * + * @details To unblock the scheduler this function has to be called the same number of times as + * @ref app_sched_pause function. + */ +void app_sched_resume(void); +#endif +#endif // APP_SCHEDULER_H__ + +/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h Tue Apr 07 06:45:07 2015 +0100 @@ -0,0 +1,84 @@ +/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup app_error Common application error handler + * @{ + * @ingroup app_common + * + * @brief Common application error handler and macros for utilizing a common error handler. + */ + +#ifndef APP_ERROR_H__ +#define APP_ERROR_H__ + +#include <stdint.h> +#include <stdbool.h> +#include "nrf_error.h" + +/**@brief Function for error handling, which is called when an error has occurred. + * + * @param[in] error_code Error code supplied to the handler. + * @param[in] line_num Line number where the handler is called. + * @param[in] p_file_name Pointer to the file name. + */ +void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name); + +/**@brief Macro for calling error handler function. + * + * @param[in] ERR_CODE Error code supplied to the error handler. + */ +#ifdef DEBUG +#define APP_ERROR_HANDLER(ERR_CODE) \ + do \ + { \ + app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); \ + } while (0) +#else +#define APP_ERROR_HANDLER(ERR_CODE) \ + do \ + { \ + app_error_handler((ERR_CODE), 0, 0); \ + } while (0) +#endif +/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS. + * + * @param[in] ERR_CODE Error code supplied to the error handler. + */ +#define APP_ERROR_CHECK(ERR_CODE) \ + do \ + { \ + const uint32_t LOCAL_ERR_CODE = (ERR_CODE); \ + if (LOCAL_ERR_CODE != NRF_SUCCESS) \ + { \ + APP_ERROR_HANDLER(LOCAL_ERR_CODE); \ + } \ + } while (0) + +/**@brief Macro for calling error handler function if supplied boolean value is false. + * + * @param[in] BOOLEAN_VALUE Boolean value to be evaluated. + */ +#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \ + do \ + { \ + const uint32_t LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \ + if (!LOCAL_BOOLEAN_VALUE) \ + { \ + APP_ERROR_HANDLER(0); \ + } \ + } while (0) + +#endif // APP_ERROR_H__ + +/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h Tue Apr 07 06:45:07 2015 +0100 @@ -0,0 +1,232 @@ +/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. + * + * The information contained herein is property of Nordic Semiconductor ASA. + * Terms and conditions of usage are described in detail in NORDIC + * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. NO + * WARRANTY of ANY KIND is provided. This heading must NOT be removed from + * the file. + * + */ + +/** @file + * + * @defgroup app_util Utility Functions and Definitions + * @{ + * @ingroup app_common + * + * @brief Various types and definitions available to all applications. + */ + +#ifndef APP_UTIL_H__ +#define APP_UTIL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include "compiler_abstraction.h" + +enum +{ + UNIT_0_625_MS = 625, /**< Number of microseconds in 0.625 milliseconds. */ + UNIT_1_25_MS = 1250, /**< Number of microseconds in 1.25 milliseconds. */ + UNIT_10_MS = 10000 /**< Number of microseconds in 10 milliseconds. */ +}; + +/**@brief Macro for doing static (i.e. compile time) assertion. + * + * @note If the assertion fails when compiling using Keil, the compiler will report error message + * "error: #94: the size of an array must be greater than zero" (while gcc will list the + * symbol static_assert_failed, making the error message more readable). + * If the supplied expression can not be evaluated at compile time, Keil will report + * "error: #28: expression must have a constant value". + * + * @note The macro is intentionally implemented not using do while(0), allowing it to be used + * outside function blocks (e.g. close to global type- and variable declarations). + * If used in a code block, it must be used before any executable code in this block. + * + * @param[in] EXPR Constant expression to be verified. + */ + +#if defined(__GNUC__) +#define STATIC_ASSERT(EXPR) typedef char __attribute__((unused)) static_assert_failed[(EXPR) ? 1 : -1] +#else +#define STATIC_ASSERT(EXPR) typedef char static_assert_failed[(EXPR) ? 1 : -1] +#endif + + +/**@brief type for holding an encoded (i.e. little endian) 16 bit unsigned integer. */ +typedef uint8_t uint16_le_t[2]; + +/**@brief type for holding an encoded (i.e. little endian) 32 bit unsigned integer. */ +typedef uint8_t uint32_le_t[4]; + +/**@brief Byte array type. */ +typedef struct +{ + uint16_t size; /**< Number of array entries. */ + uint8_t * p_data; /**< Pointer to array entries. */ +} uint8_array_t; + +/**@brief Perform rounded integer division (as opposed to truncating the result). + * + * @param[in] A Numerator. + * @param[in] B Denominator. + * + * @return Rounded (integer) result of dividing A by B. + */ +#define ROUNDED_DIV(A, B) (((A) + ((B) / 2)) / (B)) + +/**@brief Check if the integer provided is a power of two. + * + * @param[in] A Number to be tested. + * + * @return true if value is power of two. + * @return false if value not power of two. + */ +#define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) ) + +/**@brief To convert milliseconds to ticks. + * @param[in] TIME Number of milliseconds to convert. + * @param[in] RESOLUTION Unit to be converted to in [us/ticks]. + */ +#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION)) + + +/**@brief Perform integer division, making sure the result is rounded up. + * + * @details One typical use for this is to compute the number of objects with size B is needed to + * hold A number of bytes. + * + * @param[in] A Numerator. + * @param[in] B Denominator. + * + * @return Integer result of dividing A by B, rounded up. + */ +#define CEIL_DIV(A, B) \ + /*lint -save -e573 */ \ + ((((A) - 1) / (B)) + 1) \ + /*lint -restore */ + +/**@brief Function for encoding a uint16 value. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint16_encode(uint16_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((value & 0x00FF) >> 0); + p_encoded_data[1] = (uint8_t) ((value & 0xFF00) >> 8); + return sizeof(uint16_t); +} + +/**@brief Function for encoding a uint32 value. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint32_encode(uint32_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0); + p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8); + p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16); + p_encoded_data[3] = (uint8_t) ((value & 0xFF000000) >> 24); + return sizeof(uint32_t); +} + +/**@brief Function for decoding a uint16 value. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. + */ +static __INLINE uint16_t uint16_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint16_t)((uint8_t *)p_encoded_data)[0])) | + (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 )); +} + +/**@brief Function for decoding a uint32 value. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. + */ +static __INLINE uint32_t uint32_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) | + (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) | + (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) | + (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 )); +} + +/** @brief Function for converting the input voltage (in milli volts) into percentage of 3.0 Volts. + * + * @details The calculation is based on a linearized version of the battery's discharge + * curve. 3.0V returns 100% battery level. The limit for power failure is 2.1V and + * is considered to be the lower boundary. + * + * The discharge curve for CR2032 is non-linear. In this model it is split into + * 4 linear sections: + * - Section 1: 3.0V - 2.9V = 100% - 42% (58% drop on 100 mV) + * - Section 2: 2.9V - 2.74V = 42% - 18% (24% drop on 160 mV) + * - Section 3: 2.74V - 2.44V = 18% - 6% (12% drop on 300 mV) + * - Section 4: 2.44V - 2.1V = 6% - 0% (6% drop on 340 mV) + * + * These numbers are by no means accurate. Temperature and + * load in the actual application is not accounted for! + * + * @param[in] mvolts The voltage in mV + * + * @return Battery level in percent. +*/ +static __INLINE uint8_t battery_level_in_percent(const uint16_t mvolts) +{ + uint8_t battery_level; + + if (mvolts >= 3000) + { + battery_level = 100; + } + else if (mvolts > 2900) + { + battery_level = 100 - ((3000 - mvolts) * 58) / 100; + } + else if (mvolts > 2740) + { + battery_level = 42 - ((2900 - mvolts) * 24) / 160; + } + else if (mvolts > 2440) + { + battery_level = 18 - ((2740 - mvolts) * 12) / 300; + } + else if (mvolts > 2100) + { + battery_level = 6 - ((2440 - mvolts) * 6) / 340; + } + else + { + battery_level = 0; + } + + return battery_level; +} + +/**@brief Function for checking if a pointer value is aligned to a 4 byte boundary. + * + * @param[in] p Pointer value to be checked. + * + * @return TRUE if pointer is aligned to a 4 byte boundary, FALSE otherwise. + */ +static __INLINE bool is_word_aligned(void * p) +{ + return (((uintptr_t)p & 0x03) == 0); +} + +#endif // APP_UTIL_H__ + +/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_button.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,187 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup app_button Button Handler - * @{ - * @ingroup app_common - * - * @brief Buttons handling module. - * - * @details The button handler uses the @ref app_gpiote to detect that a button has been - * pushed. To handle debouncing, it will start a timer in the GPIOTE event handler. - * The button will only be reported as pushed if the corresponding pin is still active when - * the timer expires. If there is a new GPIOTE event while the timer is running, the timer - * is restarted. - * Use the USE_SCHEDULER parameter of the APP_BUTTON_INIT() macro to select if the - * @ref app_scheduler is to be used or not. - * - * @note The app_button module uses the app_timer module. The user must ensure that the queue in - * app_timer is large enough to hold the app_timer_stop() / app_timer_start() operations - * which will be executed on each event from GPIOTE module (2 operations), as well as other - * app_timer operations queued simultaneously in the application. - * - * @note Even if the scheduler is not used, app_button.h will include app_scheduler.h, so when - * compiling, app_scheduler.h must be available in one of the compiler include paths. - */ - -#ifndef APP_BUTTON_H__ -#define APP_BUTTON_H__ - -#include <stdint.h> -#include <stdbool.h> -#include "app_error.h" -#include "app_scheduler.h" -#include "nrf_gpio.h" - -#define APP_BUTTON_SCHED_EVT_SIZE sizeof(app_button_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */ -#define APP_BUTTON_PUSH 1 /**< Indicates that a button is pushed. */ -#define APP_BUTTON_RELEASE 0 /**< Indicates that a button is released. */ -#define APP_BUTTON_ACTIVE_HIGH 1 /**< Indicates that a button is active high. */ -#define APP_BUTTON_ACTIVE_LOW 0 /**< Indicates that a button is active low. */ - -/**@brief Button event handler type. */ -typedef void (*app_button_handler_t)(uint8_t pin_no, uint8_t button_action); - -/**@brief Type of function for passing events from the Button Handler module to the scheduler. */ -typedef uint32_t (*app_button_evt_schedule_func_t) (app_button_handler_t button_handler, - uint8_t pin_no, - uint8_t button_action); - -/**@brief Button configuration structure. */ -typedef struct -{ - uint8_t pin_no; /**< Pin to be used as a button. */ - uint8_t active_state; /**< APP_BUTTON_ACTIVE_HIGH or APP_BUTTON_ACTIVE_LOW. */ - nrf_gpio_pin_pull_t pull_cfg; /**< Pull-up or -down configuration. */ - app_button_handler_t button_handler; /**< Handler to be called when button is pushed. */ -} app_button_cfg_t; - -/**@brief Pin transition direction struct. */ -typedef struct -{ - uint32_t high_to_low; /**Pin went from high to low */ - uint32_t low_to_high; /**Pin went from low to high */ -} pin_transition_t; - -/**@brief Macro for initializing the Button Handler module. - * - * @details It will initialize the specified pins as buttons, and configure the Button Handler - * module as a GPIOTE user (but it will not enable button detection). It will also connect - * the Button Handler module to the scheduler (if specified). - * - * @param[in] BUTTONS Array of buttons to be used (type app_button_cfg_t, must be - * static!). - * @param[in] BUTTON_COUNT Number of buttons. - * @param[in] DETECTION_DELAY Delay from a GPIOTE event until a button is reported as pushed. - * @param[in] USE_SCHEDULER TRUE if the application is using the event scheduler, - * FALSE otherwise. - */ -/*lint -emacro(506, APP_BUTTON_INIT) */ /* Suppress "Constant value Boolean */ -#define APP_BUTTON_INIT(BUTTONS, BUTTON_COUNT, DETECTION_DELAY, USE_SCHEDULER) \ - do \ - { \ - uint32_t ERR_CODE = app_button_init((BUTTONS), \ - (BUTTON_COUNT), \ - (DETECTION_DELAY), \ - (USE_SCHEDULER) ? app_button_evt_schedule : NULL); \ - APP_ERROR_CHECK(ERR_CODE); \ - } while (0) - -/**@brief Function for initializing the Buttons. - * - * @details This function will initialize the specified pins as buttons, and configure the Button - * Handler module as a GPIOTE user (but it will not enable button detection). - * - * @note Normally initialization should be done using the APP_BUTTON_INIT() macro, as that will take - * care of connecting the Buttons module to the scheduler (if specified). - * - * @note app_button_enable() function must be called in order to enable the button detection. - * - * @param[in] p_buttons Array of buttons to be used (NOTE: Must be static!). - * @param[in] button_count Number of buttons. - * @param[in] detection_delay Delay from a GPIOTE event until a button is reported as pushed. - * @param[in] evt_schedule_func Function for passing button events to the scheduler. Point to - * app_button_evt_schedule() to connect to the scheduler. Set to - * NULL to make the Buttons module call the event handler directly - * from the delayed button push detection timeout handler. - * - * @return NRF_SUCCESS on success, otherwise an error code. - */ -uint32_t app_button_init(app_button_cfg_t * p_buttons, - uint8_t button_count, - uint32_t detection_delay, - app_button_evt_schedule_func_t evt_schedule_func); - -/**@brief Function for enabling button detection. - * - * @retval NRF_ERROR_INVALID_PARAM GPIOTE has to many users. - * @retval NRF_ERROR_INVALID_STATE Button or GPIOTE not initialized. - * @retval NRF_SUCCESS Button detection successfully enabled. - */ -uint32_t app_button_enable(void); - -/**@brief Function for disabling button detection. - * - * @retval NRF_ERROR_INVALID_PARAM GPIOTE has to many users. - * @retval NRF_ERROR_INVALID_STATE Button or GPIOTE not initialized. - * @retval NRF_SUCCESS Button detection successfully enabled. - */ -uint32_t app_button_disable(void); - -/**@brief Function for checking if a button is currently being pushed. - * - * @param[in] pin_no Button pin to be checked. - * @param[out] p_is_pushed Button state. - * - * @retval NRF_SUCCESS State successfully read. - * @retval NRF_ERROR_INVALID_PARAM Invalid pin_no. - */ -uint32_t app_button_is_pushed(uint8_t pin_no, bool * p_is_pushed); - - -// Type and functions for connecting the Buttons module to the scheduler: - -/**@cond NO_DOXYGEN */ -typedef struct -{ - app_button_handler_t button_handler; - uint8_t pin_no; - uint8_t button_action; -} app_button_event_t; - -static __INLINE void app_button_evt_get(void * p_event_data, uint16_t event_size) -{ - app_button_event_t * p_buttons_event = (app_button_event_t *)p_event_data; - - APP_ERROR_CHECK_BOOL(event_size == sizeof(app_button_event_t)); - p_buttons_event->button_handler(p_buttons_event->pin_no, p_buttons_event->button_action); -} - -static __INLINE uint32_t app_button_evt_schedule(app_button_handler_t button_handler, - uint8_t pin_no, - uint8_t button_action) -{ - app_button_event_t buttons_event; - - buttons_event.button_handler = button_handler; - buttons_event.pin_no = pin_no; - buttons_event.button_action = button_action; - - return app_sched_event_put(&buttons_event, sizeof(buttons_event), app_button_evt_get); -} -/**@endcond */ - -#endif // APP_BUTTON_H__ - -/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_error.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,84 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup app_error Common application error handler - * @{ - * @ingroup app_common - * - * @brief Common application error handler and macros for utilizing a common error handler. - */ - -#ifndef APP_ERROR_H__ -#define APP_ERROR_H__ - -#include <stdint.h> -#include <stdbool.h> -#include "nrf_error.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/**@brief Function for error handling, which is called when an error has occurred. - * - * @param[in] error_code Error code supplied to the handler. - * @param[in] line_num Line number where the handler is called. - * @param[in] p_file_name Pointer to the file name. - */ -void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name); - -#ifdef __cplusplus -} -#endif - -/**@brief Macro for calling error handler function. - * - * @param[in] ERR_CODE Error code supplied to the error handler. - */ -#define APP_ERROR_HANDLER(ERR_CODE) \ - do \ - { \ - /* app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); */ \ - } while (0) - -/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS. - * - * @param[in] ERR_CODE Error code supplied to the error handler. - */ -#define APP_ERROR_CHECK(ERR_CODE) \ - do \ - { \ - const uint32_t LOCAL_ERR_CODE = (ERR_CODE); \ - if (LOCAL_ERR_CODE != NRF_SUCCESS) \ - { \ - APP_ERROR_HANDLER(LOCAL_ERR_CODE); \ - } \ - } while (0) - -/**@brief Macro for calling error handler function if supplied boolean value is false. - * - * @param[in] BOOLEAN_VALUE Boolean value to be evaluated. - */ -#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \ - do \ - { \ - const bool LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \ - if (!LOCAL_BOOLEAN_VALUE) \ - { \ - APP_ERROR_HANDLER(0); \ - } \ - } while (0) - -#endif // APP_ERROR_H__ - -/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_fifo.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,83 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup app_fifo FIFO implementation - * @{ - * @ingroup app_common - * - * @brief FIFO implementation. - */ - -#ifndef APP_FIFO_H__ -#define APP_FIFO_H__ - -#include <stdint.h> -#include <stdlib.h> -#include "nrf_error.h" - -/**@brief A FIFO instance structure. Keeps track of which bytes to read and write next. - * Also it keeps the information about which memory is allocated for the buffer - * and its size. This needs to be initialized by app_fifo_init() before use. - */ -typedef struct -{ - uint8_t * p_buf; /**< Pointer to FIFO buffer memory. */ - uint16_t buf_size_mask; /**< Read/write index mask. Also used for size checking. */ - volatile uint32_t read_pos; /**< Next read position in the FIFO buffer. */ - volatile uint32_t write_pos; /**< Next write position in the FIFO buffer. */ -} app_fifo_t; - -/**@brief Function for initializing the FIFO. - * - * @param[out] p_fifo FIFO object. - * @param[in] p_buf FIFO buffer for storing data. The buffer size has to be a power of two. - * @param[in] buf_size Size of the FIFO buffer provided, has to be a power of 2. - * - * @retval NRF_SUCCESS If initialization was successful. - * @retval NRF_ERROR_NULL If a NULL pointer is provided as buffer. - * @retval NRF_ERROR_INVALID_LENGTH If size of buffer provided is not a power of two. - */ -uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size); - -/**@brief Function for adding an element to the FIFO. - * - * @param[in] p_fifo Pointer to the FIFO. - * @param[in] byte Data byte to add to the FIFO. - * - * @retval NRF_SUCCESS If an element has been successfully added to the FIFO. - * @retval NRF_ERROR_NO_MEM If the FIFO is full. - */ -uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte); - -/**@brief Function for getting the next element from the FIFO. - * - * @param[in] p_fifo Pointer to the FIFO. - * @param[out] p_byte Byte fetched from the FIFO. - * - * @retval NRF_SUCCESS If an element was returned. - * @retval NRF_ERROR_NOT_FOUND If there is no more elements in the queue. - */ -uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte); - -/**@brief Function for flushing the FIFO. - * - * @param[in] p_fifo Pointer to the FIFO. - * - * @retval NRF_SUCCESS If the FIFO flushed successfully. - */ -uint32_t app_fifo_flush(app_fifo_t * p_fifo); - -#endif // APP_FIFO_H__ - -/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_gpiote.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,226 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup app_gpiote GPIOTE Handler - * @{ - * @ingroup app_common - * - * @brief GPIOTE handler module. - * - * @details The GPIOTE handler allows several modules ("users") to share the GPIOTE interrupt, - * each user defining a set of pins able to generate events to the user. - * When a GPIOTE interrupt occurs, the GPIOTE interrupt handler will call the event handler - * of each user for which at least one of the pins generated an event. - * - * The GPIOTE users are responsible for configuring all their corresponding pins, except - * the SENSE field, which should be initialized to GPIO_PIN_CNF_SENSE_Disabled. - * The SENSE field will be updated by the GPIOTE module when it is enabled or disabled, - * and also while it is enabled. - * - * The module specifies on which pins events should be generated if the pin(s) goes - * from low->high or high->low or both directions. - * - * @note Even if the application is using the @ref app_scheduler, the GPIOTE event handlers will - * be called directly from the GPIOTE interrupt handler. - * - * @warning If multiple users registers for the same pins the behavior for those pins are undefined. - */ - -#ifndef APP_GPIOTE_H__ -#define APP_GPIOTE_H__ - -#include <stdint.h> -#include <stdbool.h> -// #include "nrf.h" -#include "app_error.h" -#include "app_util.h" - -#ifdef __cpluplus -extern "C" { -#endif - -#define GPIOTE_USER_NODE_SIZE 20 /**< Size of app_gpiote.gpiote_user_t (only for use inside APP_GPIOTE_BUF_SIZE()). */ -#define NO_OF_PINS 32 /**< Number of GPIO pins on the nRF51 chip. */ - -/**@brief Compute number of bytes required to hold the GPIOTE data structures. - * - * @param[in] MAX_USERS Maximum number of GPIOTE users. - * - * @return Required buffer size (in bytes). - */ -#define APP_GPIOTE_BUF_SIZE(MAX_USERS) ((MAX_USERS) * GPIOTE_USER_NODE_SIZE) - -typedef uint8_t app_gpiote_user_id_t; - -/**@brief GPIOTE event handler type. */ -typedef void (*app_gpiote_event_handler_t)(uint32_t event_pins_low_to_high, - uint32_t event_pins_high_to_low); - -/**@brief GPIOTE input event handler type. */ -typedef void (*app_gpiote_input_event_handler_t)(void); - -/**@brief Macro for initializing the GPIOTE module. - * - * @details It will handle dimensioning and allocation of the memory buffer required by the module, - * making sure that the buffer is correctly aligned. - * - * @param[in] MAX_USERS Maximum number of GPIOTE users. - * - * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it - * several times as long as it is from the same location, e.g. to do a reinitialization). - */ -/*lint -emacro(506, APP_GPIOTE_INIT) */ /* Suppress "Constant value Boolean */ -#define APP_GPIOTE_INIT(MAX_USERS) \ - do \ - { \ - static uint32_t app_gpiote_buf[CEIL_DIV(APP_GPIOTE_BUF_SIZE(MAX_USERS), sizeof(uint32_t))];\ - uint32_t ERR_CODE = app_gpiote_init((MAX_USERS), app_gpiote_buf); \ - APP_ERROR_CHECK(ERR_CODE); \ - } while (0) - -/**@brief Function for initializing the GPIOTE module. - * - * @note Normally initialization should be done using the APP_GPIOTE_INIT() macro, as that will - * allocate the buffer needed by the GPIOTE module (including aligning the buffer correctly). - * - * @param[in] max_users Maximum number of GPIOTE users. - * @param[in] p_buffer Pointer to memory buffer for internal use in the app_gpiote - * module. The size of the buffer can be computed using the - * APP_GPIOTE_BUF_SIZE() macro. The buffer must be aligned to - * a 4 byte boundary. - * - * @retval NRF_SUCCESS Successful initialization. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte - * boundary). - */ -uint32_t app_gpiote_init(uint8_t max_users, void * p_buffer); - -/**@brief Function for registering a GPIOTE user. - * - * @param[out] p_user_id Id for the new GPIOTE user. - * @param[in] pins_low_to_high_mask Mask defining which pins will generate events to this user - * when state is changed from low->high. - * @param[in] pins_high_to_low_mask Mask defining which pins will generate events to this user - * when state is changed from high->low. - * @param[in] event_handler Pointer to function to be executed when an event occurs. - * - * @retval NRF_SUCCESS Successful initialization. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte boundary). - * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE - * module. - * @retval NRF_ERROR_NO_MEM Returned if the application tries to register more users - * than defined when the GPIOTE module was initialized in - * @ref app_gpiote_init. - */ -uint32_t app_gpiote_user_register(app_gpiote_user_id_t * p_user_id, - uint32_t pins_low_to_high_mask, - uint32_t pins_high_to_low_mask, - app_gpiote_event_handler_t event_handler); - -/**@brief Function for informing the GPIOTE module that the specified user wants to use the GPIOTE module. - * - * @param[in] user_id Id of user to enable. - * - * @retval NRF_SUCCESS On success. - * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user. - * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE - * module. - */ -uint32_t app_gpiote_user_enable(app_gpiote_user_id_t user_id); - -/**@brief Function for informing the GPIOTE module that the specified user is done using the GPIOTE module. - * - * @param[in] user_id Id of user to enable. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user. - * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE - * module. - */ -uint32_t app_gpiote_user_disable(app_gpiote_user_id_t user_id); - -/**@brief Function for getting the state of the pins which are registered for the specified user. - * - * @param[in] user_id Id of user to check. - * @param[out] p_pins Bit mask corresponding to the pins configured to generate events to - * the specified user. All bits corresponding to pins in the state - * 'high' will have value '1', all others will have value '0'. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_INVALID_PARAM Invalid user_id provided, No a valid user. - * @retval NRF_ERROR_INALID_STATE If @ref app_gpiote_init has not been called on the GPIOTE - * module. - */ -uint32_t app_gpiote_pins_state_get(app_gpiote_user_id_t user_id, uint32_t * p_pins); - -/**@brief Function for registering event handlers for GPIOTE IN events. - * - * @param[in] channel GPIOTE channel [0..3]. - * @param[in] pin Pins associated with GPIOTE channel. Changes on following pins will generate events. - * @param[in] polarity Specify operation on input that shall trigger IN event. - * @param[in] event_handler Event handler invoked on the IN event in the GPIOTE interrupt. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_INVALID_PARAM Invalid channel or pin number. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events. - */ -uint32_t app_gpiote_input_event_handler_register(const uint8_t channel, - const uint32_t pin, - const uint32_t polarity, - app_gpiote_input_event_handler_t event_handler); - -/**@brief Function for unregistering event handlers for GPIOTE IN events. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events. - */ -uint32_t app_gpiote_input_event_handler_unregister(const uint8_t channel); - -/**@brief Function for registering event handler invoked at the end of a GPIOTE interrupt. - * - * @param[in] event_handler Event handler invoked at the end of the GPIOTE interrupt. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events. - */ -uint32_t app_gpiote_end_irq_event_handler_register(app_gpiote_input_event_handler_t event_handler); - -/**@brief Function for unregistering event handler invoked at the end of a GPIOTE interrupt. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support IN events. - */ -uint32_t app_gpiote_end_irq_event_handler_unregister(void); - -/**@brief Function for enabling interrupts in the GPIOTE driver. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support. - */ -uint32_t app_gpiote_enable_interrupts(void); - -/**@brief Function for disabling interrupts in the GPIOTE driver. - * - * @return NRF_SUCCESS On success. - * @retval NRF_ERROR_NOT_SUPPORTED Driver doesn't support. - */ -uint32_t app_gpiote_disable_interrupts(void); - -#ifdef __cpluplus -} -#endif - -#endif // APP_GPIOTE_H__ - -/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_scheduler.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,134 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup app_scheduler Scheduler - * @{ - * @ingroup app_common - * - * @brief The scheduler is used for transferring execution from the interrupt context to the main - * context. - * - * @details See @ref ble_sdk_apps_seq_diagrams for sequence diagrams illustrating the flow of events - * when using the Scheduler. - * - * @section app_scheduler_req Requirements: - * - * @subsection main_context_logic Logic in main context: - * - * - Define an event handler for each type of event expected. - * - Initialize the scheduler by calling the APP_SCHED_INIT() macro before entering the - * application main loop. - * - Call app_sched_execute() from the main loop each time the application wakes up because of an - * event (typically when sd_app_evt_wait() returns). - * - * @subsection int_context_logic Logic in interrupt context: - * - * - In the interrupt handler, call app_sched_event_put() - * with the appropriate data and event handler. This will insert an event into the - * scheduler's queue. The app_sched_execute() function will pull this event and call its - * handler in the main context. - * - * For an example usage of the scheduler, please see the implementations of - * @ref ble_sdk_app_hids_mouse and @ref ble_sdk_app_hids_keyboard. - * - * @image html scheduler_working.jpg The high level design of the scheduler - */ - -#ifndef APP_SCHEDULER_H__ -#define APP_SCHEDULER_H__ - -#include <stdint.h> -#include "app_error.h" - -#define APP_SCHED_EVENT_HEADER_SIZE 8 /**< Size of app_scheduler.event_header_t (only for use inside APP_SCHED_BUF_SIZE()). */ - -/**@brief Compute number of bytes required to hold the scheduler buffer. - * - * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler. - * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events - * that can be scheduled for execution). - * - * @return Required scheduler buffer size (in bytes). - */ -#define APP_SCHED_BUF_SIZE(EVENT_SIZE, QUEUE_SIZE) \ - (((EVENT_SIZE) + APP_SCHED_EVENT_HEADER_SIZE) * ((QUEUE_SIZE) + 1)) - -/**@brief Scheduler event handler type. */ -typedef void (*app_sched_event_handler_t)(void * p_event_data, uint16_t event_size); - -/**@brief Macro for initializing the event scheduler. - * - * @details It will also handle dimensioning and allocation of the memory buffer required by the - * scheduler, making sure the buffer is correctly aligned. - * - * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler. - * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events - * that can be scheduled for execution). - * - * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it - * several times as long as it is from the same location, e.g. to do a reinitialization). - */ -#define APP_SCHED_INIT(EVENT_SIZE, QUEUE_SIZE) \ - do \ - { \ - static uint32_t APP_SCHED_BUF[CEIL_DIV(APP_SCHED_BUF_SIZE((EVENT_SIZE), (QUEUE_SIZE)), \ - sizeof(uint32_t))]; \ - uint32_t ERR_CODE = app_sched_init((EVENT_SIZE), (QUEUE_SIZE), APP_SCHED_BUF); \ - APP_ERROR_CHECK(ERR_CODE); \ - } while (0) - -/**@brief Function for initializing the Scheduler. - * - * @details It must be called before entering the main loop. - * - * @param[in] max_event_size Maximum size of events to be passed through the scheduler. - * @param[in] queue_size Number of entries in scheduler queue (i.e. the maximum number of - * events that can be scheduled for execution). - * @param[in] p_event_buffer Pointer to memory buffer for holding the scheduler queue. It must - * be dimensioned using the APP_SCHED_BUFFER_SIZE() macro. The buffer - * must be aligned to a 4 byte boundary. - * - * @note Normally initialization should be done using the APP_SCHED_INIT() macro, as that will both - * allocate the scheduler buffer, and also align the buffer correctly. - * - * @retval NRF_SUCCESS Successful initialization. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte - * boundary). - */ -uint32_t app_sched_init(uint16_t max_event_size, uint16_t queue_size, void * p_evt_buffer); - -/**@brief Function for executing all scheduled events. - * - * @details This function must be called from within the main loop. It will execute all events - * scheduled since the last time it was called. - */ -void app_sched_execute(void); - -/**@brief Function for scheduling an event. - * - * @details Puts an event into the event queue. - * - * @param[in] p_event_data Pointer to event data to be scheduled. - * @param[in] p_event_size Size of event data to be scheduled. - * @param[in] handler Event handler to receive the event. - * - * @return NRF_SUCCESS on success, otherwise an error code. - */ -uint32_t app_sched_event_put(void * p_event_data, - uint16_t event_size, - app_sched_event_handler_t handler); - -#endif // APP_SCHEDULER_H__ - -/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_timer.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,313 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup app_timer Application Timer - * @{ - * @ingroup app_common - * - * @brief Application timer functionality. - * - * @details It enables the application to create multiple timer instances based on the RTC1 - * peripheral. Checking for timeouts and invokation of user timeout handlers is performed - * in the RTC1 interrupt handler. List handling is done using a software interrupt (SWI0). - * Both interrupt handlers are running in APP_LOW priority level. - * - * @note When calling app_timer_start() or app_timer_stop(), the timer operation is just queued, - * and the software interrupt is triggered. The actual timer start/stop operation is - * executed by the SWI0 interrupt handler. Since the SWI0 interrupt is running in APP_LOW, - * if the application code calling the timer function is running in APP_LOW or APP_HIGH, - * the timer operation will not be performed until the application handler has returned. - * This will be the case e.g. when stopping a timer from a timeout handler when not using - * the scheduler. - * - * @details Use the USE_SCHEDULER parameter of the APP_TIMER_INIT() macro to select if the - * @ref app_scheduler is to be used or not. - * - * @note Even if the scheduler is not used, app_timer.h will include app_scheduler.h, so when - * compiling, app_scheduler.h must be available in one of the compiler include paths. - */ - -#ifndef APP_TIMER_H__ -#define APP_TIMER_H__ - -#include <stdint.h> -#include <stdbool.h> -#include <stdio.h> -#include "app_error.h" -#include "app_util.h" -#include "app_scheduler.h" -#include "compiler_abstraction.h" - -#ifdef __cplusplus -extern "C" { -#endif // #ifdef __cplusplus - -#define APP_TIMER_SCHED_EVT_SIZE sizeof(app_timer_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */ -#define APP_TIMER_CLOCK_FREQ 32768 /**< Clock frequency of the RTC timer used to implement the app timer module. */ -#define APP_TIMER_MIN_TIMEOUT_TICKS 5 /**< Minimum value of the timeout_ticks parameter of app_timer_start(). */ - -#define APP_TIMER_NODE_SIZE 40 /**< Size of app_timer.timer_node_t (only for use inside APP_TIMER_BUF_SIZE()). */ -#define APP_TIMER_USER_OP_SIZE 24 /**< Size of app_timer.timer_user_op_t (only for use inside APP_TIMER_BUF_SIZE()). */ -#define APP_TIMER_USER_SIZE 8 /**< Size of app_timer.timer_user_t (only for use inside APP_TIMER_BUF_SIZE()). */ -#define APP_TIMER_INT_LEVELS 3 /**< Number of interrupt levels from where timer operations may be initiated (only for use inside APP_TIMER_BUF_SIZE()). */ - -#define MAX_RTC_COUNTER_VAL 0x00FFFFFF /**< Maximum value of the RTC counter. */ - -/**@brief Compute number of bytes required to hold the application timer data structures. - * - * @param[in] MAX_TIMERS Maximum number of timers that can be created at any given time. - * @param[in] OP_QUEUE_SIZE Size of queues holding timer operations that are pending execution. - * NOTE: Due to the queue implementation, this size must be one more - * than the size that is actually needed. - * - * @return Required application timer buffer size (in bytes). - */ -#define APP_TIMER_BUF_SIZE(MAX_TIMERS, OP_QUEUE_SIZE) \ - ( \ - ((MAX_TIMERS) * APP_TIMER_NODE_SIZE) \ - + \ - ( \ - APP_TIMER_INT_LEVELS \ - * \ - (APP_TIMER_USER_SIZE + ((OP_QUEUE_SIZE) + 1) * APP_TIMER_USER_OP_SIZE) \ - ) \ - ) - -/**@brief Convert milliseconds to timer ticks. - * - * @note This macro uses 64 bit integer arithmetic, but as long as the macro parameters are - * constants (i.e. defines), the computation will be done by the preprocessor. - * - * @param[in] MS Milliseconds. - * @param[in] PRESCALER Value of the RTC1 PRESCALER register (must be the same value that was - * passed to APP_TIMER_INIT()). - * - * @note When using this macro, it is the responsibility of the developer to ensure that the - * values provided as input result in an output value that is supported by the - * @ref app_timer_start function. For example, when the ticks for 1 ms is needed, the - * maximum possible value of PRESCALER must be 6, when @ref APP_TIMER_CLOCK_FREQ is 32768. - * This will result in a ticks value as 5. Any higher value for PRESCALER will result in a - * ticks value that is not supported by this module. - * - * @return Number of timer ticks. - */ -#define APP_TIMER_TICKS(MS, PRESCALER)\ - ((uint32_t)ROUNDED_DIV((MS) * (uint64_t)APP_TIMER_CLOCK_FREQ, ((PRESCALER) + 1) * 1000)) - -/**@brief Timer id type. */ -typedef uint32_t app_timer_id_t; - -#define TIMER_NULL ((app_timer_id_t)(0 - 1)) /**< Invalid timer id. */ - -/**@brief Application timeout handler type. */ -typedef void (*app_timer_timeout_handler_t)(void * p_context); - -/**@brief Type of function for passing events from the timer module to the scheduler. */ -typedef uint32_t (*app_timer_evt_schedule_func_t) (app_timer_timeout_handler_t timeout_handler, - void * p_context); - -/**@brief Timer modes. */ -typedef enum -{ - APP_TIMER_MODE_SINGLE_SHOT, /**< The timer will expire only once. */ - APP_TIMER_MODE_REPEATED /**< The timer will restart each time it expires. */ -} app_timer_mode_t; - -/**@brief Macro for initializing the application timer module. - * - * @details It will handle dimensioning and allocation of the memory buffer required by the timer, - * making sure that the buffer is correctly aligned. It will also connect the timer module - * to the scheduler (if specified). - * - * @note This module assumes that the LFCLK is already running. If it isn't, the module will - * be non-functional, since the RTC will not run. If you don't use a softdevice, you'll - * have to start the LFCLK manually. See the rtc_example's \ref lfclk_config() function - * for an example of how to do this. If you use a softdevice, the LFCLK is started on - * softdevice init. - * - * - * @param[in] PRESCALER Value of the RTC1 PRESCALER register. This will decide the - * timer tick rate. Set to 0 for no prescaling. - * @param[in] MAX_TIMERS Maximum number of timers that can be created at any given time. - * @param[in] OP_QUEUES_SIZE Size of queues holding timer operations that are pending execution. - * @param[in] USE_SCHEDULER TRUE if the application is using the event scheduler, - * FALSE otherwise. - * - * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it - * several times as long as it is from the same location, e.g. to do a reinitialization). - */ -/*lint -emacro(506, APP_TIMER_INIT) */ /* Suppress "Constant value Boolean */ -#define APP_TIMER_INIT(PRESCALER, MAX_TIMERS, OP_QUEUES_SIZE, USE_SCHEDULER) \ - do \ - { \ - static uint32_t APP_TIMER_BUF[CEIL_DIV(APP_TIMER_BUF_SIZE((MAX_TIMERS), \ - (OP_QUEUES_SIZE) + 1), \ - sizeof(uint32_t))]; \ - uint32_t ERR_CODE = app_timer_init((PRESCALER), \ - (MAX_TIMERS), \ - (OP_QUEUES_SIZE) + 1, \ - APP_TIMER_BUF, \ - (USE_SCHEDULER) ? app_timer_evt_schedule : NULL); \ - APP_ERROR_CHECK(ERR_CODE); \ - } while (0) - -/**@brief Function for initializing the timer module. - * - * @note Normally initialization should be done using the APP_TIMER_INIT() macro, as that will both - * allocate the buffers needed by the timer module (including aligning the buffers correctly, - * and also take care of connecting the timer module to the scheduler (if specified). - * - * @param[in] prescaler Value of the RTC1 PRESCALER register. Set to 0 for no prescaling. - * @param[in] max_timers Maximum number of timers that can be created at any given time. - * @param[in] op_queues_size Size of queues holding timer operations that are pending - * execution. NOTE: Due to the queue implementation, this size must - * be one more than the size that is actually needed. - * @param[in] p_buffer Pointer to memory buffer for internal use in the app_timer - * module. The size of the buffer can be computed using the - * APP_TIMER_BUF_SIZE() macro. The buffer must be aligned to a - * 4 byte boundary. - * @param[in] evt_schedule_func Function for passing timeout events to the scheduler. Point to - * app_timer_evt_schedule() to connect to the scheduler. Set to NULL - * to make the timer module call the timeout handler directly from - * the timer interrupt handler. - * - * @retval NRF_SUCCESS Successful initialization. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte - * boundary or NULL). - */ -uint32_t app_timer_init(uint32_t prescaler, - uint8_t max_timers, - uint8_t op_queues_size, - void * p_buffer, - app_timer_evt_schedule_func_t evt_schedule_func); - -/**@brief Function for creating a timer instance. - * - * @param[out] p_timer_id Id of the newly created timer. - * @param[in] mode Timer mode. - * @param[in] timeout_handler Function to be executed when the timer expires. - * - * @retval NRF_SUCCESS Timer was successfully created. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter. - * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized. - * @retval NRF_ERROR_NO_MEM Maximum number of timers has already been reached. - * - * @note This function does the timer allocation in the caller's context. It is also not protected - * by a critical region. Therefore care must be taken not to call it from several interrupt - * levels simultaneously. - */ -uint32_t app_timer_create(app_timer_id_t * p_timer_id, - app_timer_mode_t mode, - app_timer_timeout_handler_t timeout_handler); - -/**@brief Function for starting a timer. - * - * @param[in] timer_id Id of timer to start. - * @param[in] timeout_ticks Number of ticks (of RTC1, including prescaling) to timeout event - * (minimum 5 ticks). - * @param[in] p_context General purpose pointer. Will be passed to the timeout handler when - * the timer expires. - * - * @retval NRF_SUCCESS Timer was successfully started. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter. - * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized, or timer - * has not been created. - * @retval NRF_ERROR_NO_MEM Timer operations queue was full. - * - * @note The minimum timeout_ticks value is 5. - * @note For multiple active timers, timeouts occurring in close proximity to each other (in the - * range of 1 to 3 ticks) will have a positive jitter of maximum 3 ticks. - * @note When calling this method on a timer which is already running, the second start operation - * will be ignored. - */ -uint32_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context); - -/**@brief Function for stopping the specified timer. - * - * @param[in] timer_id Id of timer to stop. - * - * @retval NRF_SUCCESS Timer was successfully stopped. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter. - * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized, or timer - * has not been created. - * @retval NRF_ERROR_NO_MEM Timer operations queue was full. - */ -uint32_t app_timer_stop(app_timer_id_t timer_id); - -/**@brief Function for stopping all running timers. - * - * @retval NRF_SUCCESS All timers were successfully stopped. - * @retval NRF_ERROR_INVALID_STATE Application timer module has not been initialized. - * @retval NRF_ERROR_NO_MEM Timer operations queue was full. - */ -uint32_t app_timer_stop_all(void); - -/**@brief Function for returning the current value of the RTC1 counter. The - * value includes overflow bits to extend the range to 64-bits. - * - * @param[out] p_ticks Current value of the RTC1 counter. - * - * @retval NRF_SUCCESS Counter was successfully read. - */ -uint32_t app_timer_cnt_get(uint64_t * p_ticks); - -/**@brief Function for computing the difference between two RTC1 counter values. - * - * @param[in] ticks_to Value returned by app_timer_cnt_get(). - * @param[in] ticks_from Value returned by app_timer_cnt_get(). - * @param[out] p_ticks_diff Number of ticks from ticks_from to ticks_to. - * - * @retval NRF_SUCCESS Counter difference was successfully computed. - */ -uint32_t app_timer_cnt_diff_compute(uint32_t ticks_to, - uint32_t ticks_from, - uint32_t * p_ticks_diff); - - -// Type and functions for connecting the timer to the scheduler: - -/**@cond NO_DOXYGEN */ -typedef struct -{ - app_timer_timeout_handler_t timeout_handler; - void * p_context; -} app_timer_event_t; - -static __INLINE void app_timer_evt_get(void * p_event_data, uint16_t event_size) -{ - app_timer_event_t * p_timer_event = (app_timer_event_t *)p_event_data; - - APP_ERROR_CHECK_BOOL(event_size == sizeof(app_timer_event_t)); - p_timer_event->timeout_handler(p_timer_event->p_context); -} - -static __INLINE uint32_t app_timer_evt_schedule(app_timer_timeout_handler_t timeout_handler, - void * p_context) -{ - app_timer_event_t timer_event; - - timer_event.timeout_handler = timeout_handler; - timer_event.p_context = p_context; - - return app_sched_event_put(&timer_event, sizeof(timer_event), app_timer_evt_get); -} -/**@endcond */ - -#ifdef __cplusplus -} -#endif // #ifdef __cplusplus - -#endif // APP_TIMER_H__ - -/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_trace.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,55 +0,0 @@ -#ifndef __DEBUG_H_ -#define __DEBUG_H_ - -#include <stdint.h> -#include <stdio.h> - -/** - * @defgroup app_trace Debug Logger - * @ingroup app_common - * @{ - * @brief Enables debug logs/ trace over UART. - * @details Enables debug logs/ trace over UART. Tracing is enabled only if - * ENABLE_DEBUG_LOG_SUPPORT is defined in the project. - */ -#ifdef ENABLE_DEBUG_LOG_SUPPORT -/** - * @brief Module Initialization. - * - * @details Initializes the module to use UART as trace output. - * - * @warning This function will configure UART using default board configuration (described in @ref nrf51_setups). - * Do not call this function if UART is configured from a higher level in the application. - */ -void app_trace_init(void); - -/** - * @brief Log debug messages. - * - * @details This API logs messages over UART. The module must be initialized before using this API. - * - * @note Though this is currently a macro, it should be used used and treated as function. - */ -#define app_trace_log printf - -/** - * @brief Dump auxiliary byte buffer to the debug trace. - * - * @details This API logs messages over UART. The module must be initialized before using this API. - * - * @param[in] p_buffer Buffer to be dumped on the debug trace. - * @param[in] len Size of the buffer. - */ -void app_trace_dump(uint8_t * p_buffer, uint32_t len); - -#else // ENABLE_DEBUG_LOG_SUPPORT - -#define app_trace_init(...) -#define app_trace_log(...) -#define app_trace_dump(...) - -#endif // ENABLE_DEBUG_LOG_SUPPORT - -/** @} */ - -#endif //__DEBUG_H_
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_uart.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,286 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup app_uart UART module - * @{ - * @ingroup app_common - * - * @brief UART module interface. - */ - -#ifndef APP_UART_H__ -#define APP_UART_H__ - -#include <stdint.h> -#include <stdbool.h> -#include "app_util_platform.h" - -#define UART_PIN_DISCONNECTED 0xFFFFFFFF /**< Value indicating that no pin is connected to this UART register. */ - -/**@brief UART Flow Control modes for the peripheral. - */ -typedef enum -{ - APP_UART_FLOW_CONTROL_DISABLED, /**< UART Hw Flow Control is disabled. */ - APP_UART_FLOW_CONTROL_ENABLED, /**< Standard UART Hw Flow Control is enabled. */ - APP_UART_FLOW_CONTROL_LOW_POWER /**< Specialized UART Hw Flow Control is used. The Low Power setting allows the nRF51 to Power Off the UART module when CTS is in-active, and re-enabling the UART when the CTS signal becomes active. This allows the nRF51 to safe power by only using the UART module when it is needed by the remote site. */ -} app_uart_flow_control_t; - -/**@brief UART communication structure holding configuration settings for the peripheral. - */ -typedef struct -{ - uint8_t rx_pin_no; /**< RX pin number. */ - uint8_t tx_pin_no; /**< TX pin number. */ - uint8_t rts_pin_no; /**< RTS pin number, only used if flow control is enabled. */ - uint8_t cts_pin_no; /**< CTS pin number, only used if flow control is enabled. */ - app_uart_flow_control_t flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */ - bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */ - uint32_t baud_rate; /**< Baud rate configuration. */ -} app_uart_comm_params_t; - -/**@brief UART buffer for transmitting/receiving data. - */ -typedef struct -{ - uint8_t * rx_buf; /**< Pointer to the RX buffer. */ - uint32_t rx_buf_size; /**< Size of the RX buffer. */ - uint8_t * tx_buf; /**< Pointer to the TX buffer. */ - uint32_t tx_buf_size; /**< Size of the TX buffer. */ -} app_uart_buffers_t; - -/**@brief Enumeration describing current state of the UART. - * - * @details The connection state can be fetched by the application using the function call - * @ref app_uart_get_connection_state. - * When hardware flow control is used - * - APP_UART_CONNECTED: Communication is ongoing. - * - APP_UART_DISCONNECTED: No communication is ongoing. - * - * When no hardware flow control is used - * - APP_UART_CONNECTED: Always returned as bytes can always be received/transmitted. - */ -typedef enum -{ - APP_UART_DISCONNECTED, /**< State indicating that the UART is disconnected and cannot receive or transmit bytes. */ - APP_UART_CONNECTED /**< State indicating that the UART is connected and ready to receive or transmit bytes. If flow control is disabled, the state will always be connected. */ -} app_uart_connection_state_t; - -/**@brief Enumeration which defines events used by the UART module upon data reception or error. - * - * @details The event type is used to indicate the type of additional information in the event - * @ref app_uart_evt_t. - */ -typedef enum -{ - APP_UART_DATA_READY, /**< An event indicating that UART data has been received. The data is available in the FIFO and can be fetched using @ref app_uart_get. */ - APP_UART_FIFO_ERROR, /**< An error in the FIFO module used by the app_uart module has occured. The FIFO error code is stored in app_uart_evt_t.data.error_code field. */ - APP_UART_COMMUNICATION_ERROR, /**< An communication error has occured during reception. The error is stored in app_uart_evt_t.data.error_communication field. */ - APP_UART_TX_EMPTY, /**< An event indicating that UART has completed transmission of all available data in the TX FIFO. */ - APP_UART_DATA, /**< An event indicating that UART data has been received, and data is present in data field. This event is only used when no FIFO is configured. */ -} app_uart_evt_type_t; - -/**@brief Struct containing events from the UART module. - * - * @details The app_uart_evt_t is used to notify the application of asynchronous events when data - * are received on the UART peripheral or in case an error occured during data reception. - */ -typedef struct -{ - app_uart_evt_type_t evt_type; /**< Type of event. */ - union - { - uint32_t error_communication; /**< Field used if evt_type is: APP_UART_COMMUNICATION_ERROR. This field contains the value in the ERRORSRC register for the UART peripheral. The UART_ERRORSRC_x defines from @ref nrf51_bitfields.h can be used to parse the error code. See also the nRF51 Series Reference Manual for specification. */ - uint32_t error_code; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */ - uint8_t value; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */ - } data; -} app_uart_evt_t; - -/**@brief Function for handling app_uart event callback. - * - * @details Upon an event in the app_uart module this callback function will be called to notify - * the applicatioon about the event. - * - * @param[in] p_app_uart_event Pointer to UART event. - */ - - -typedef void (* app_uart_event_handler_t) (app_uart_evt_t * p_app_uart_event); - -/**@brief Macro for safe initialization of the UART module in a single user instance when using - * a FIFO together with UART. - * - * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t - * @param[in] RX_BUF_SIZE Size of desired RX buffer, must be a power of 2 or ZERO (No FIFO). - * @param[in] TX_BUF_SIZE Size of desired TX buffer, must be a power of 2 or ZERO (No FIFO). - * @param[in] EVENT_HANDLER Event handler function to be called when an event occurs in the - * UART module. - * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler. - * @param[out] ERR_CODE The return value of the UART initialization function will be - * written to this parameter. - * - * @note Since this macro allocates a buffer and registers the module as a GPIOTE user when flow - * control is enabled, it must only be called once. - */ -#define APP_UART_FIFO_INIT(P_COMM_PARAMS, RX_BUF_SIZE, TX_BUF_SIZE, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \ - do \ - { \ - uint16_t APP_UART_UID = 0; \ - app_uart_buffers_t buffers; \ - static uint8_t rx_buf[RX_BUF_SIZE]; \ - static uint8_t tx_buf[TX_BUF_SIZE]; \ - \ - buffers.rx_buf = rx_buf; \ - buffers.rx_buf_size = sizeof (rx_buf); \ - buffers.tx_buf = tx_buf; \ - buffers.tx_buf_size = sizeof (tx_buf); \ - ERR_CODE = app_uart_init(P_COMM_PARAMS, &buffers, EVT_HANDLER, IRQ_PRIO, &APP_UART_UID); \ - } while (0) - -/**@brief Macro for safe initialization of the UART module in a single user instance. - * - * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t - * @param[in] EVENT_HANDLER Event handler function to be called when an event occurs in the - * UART module. - * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler. - * @param[out] ERR_CODE The return value of the UART initialization function will be - * written to this parameter. - * - * @note Since this macro allocates registers the module as a GPIOTE user when flow control is - * enabled, it must only be called once. - */ -#define APP_UART_INIT(P_COMM_PARAMS, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \ - do \ - { \ - uint16_t APP_UART_UID = 0; \ - ERR_CODE = app_uart_init(P_COMM_PARAMS, NULL, EVT_HANDLER, IRQ_PRIO, &APP_UART_UID); \ - } while (0) - -/**@brief Function for initializing the UART module. Use this initialization when several instances of the UART - * module are needed. - * - * @details This initialization will return a UART user id for the caller. The UART user id must be - * used upon re-initialization of the UART or closing of the module for the user. - * If single instance usage is needed, the APP_UART_INIT() macro should be used instead. - * - * @note Normally single instance initialization should be done using the APP_UART_INIT() or - * APP_UART_INIT_FIFO() macro depending on whether the FIFO should be used by the UART, as - * that will allocate the buffers needed by the UART module (including aligning the buffer - * correctly). - - * @param[in] p_comm_params Pin and communication parameters. - * @param[in] p_buffers RX and TX buffers, NULL is FIFO is not used. - * @param[in] error_handler Function to be called in case of an error. - * @param[in] app_irq_priority Interrupt priority level. - * @param[in,out] p_uart_uid User id for the UART module. The p_uart_uid must be used if - * re-initialization and/or closing of the UART module is needed. - * If the value pointed to by p_uart_uid is zero, this is - * considdered a first time initialization. Otherwise this is - * considered a re-initialization for the user with id *p_uart_uid. - * - * @retval NRF_SUCCESS If successful initialization. - * @retval NRF_ERROR_INVALID_LENGTH If a provided buffer is not a power of two. - * @retval NRF_ERROR_NULL If one of the provided buffers is a NULL pointer. - * - * Those errors are propagated by the UART module to the caller upon registration when Hardware Flow - * Control is enabled. When Hardware Flow Control is not used, those errors cannot occur. - * @retval NRF_ERROR_INVALID_STATE The GPIOTE module is not in a valid state when registering - * the UART module as a user. - * @retval NRF_ERROR_INVALID_PARAM The UART module provides an invalid callback function when - * registering the UART module as a user. - * Or the value pointed to by *p_uart_uid is not a valid - * GPIOTE number. - * @retval NRF_ERROR_NO_MEM GPIOTE module has reached the maximum number of users. - */ -uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params, - app_uart_buffers_t * p_buffers, - app_uart_event_handler_t error_handler, - app_irq_priority_t irq_priority, - uint16_t * p_uart_uid); - -/**@brief Function for getting a byte from the UART. - * - * @details This function will get the next byte from the RX buffer. If the RX buffer is empty - * an error code will be returned and the app_uart module will generate an event upon - * reception of the first byte which is added to the RX buffer. - * - * @param[out] p_byte Pointer to an address where next byte received on the UART will be copied. - * - * @retval NRF_SUCCESS If a byte has been received and pushed to the pointer provided. - * @retval NRF_ERROR_NOT_FOUND If no byte is available in the RX buffer of the app_uart module. - */ -uint32_t app_uart_get(uint8_t * p_byte); - -/**@brief Function for putting a byte on the UART. - * - * @details This call is non-blocking. - * - * @param[in] byte Byte to be transmitted on the UART. - * - * @retval NRF_SUCCESS If the byte was succesfully put on the TX buffer for transmission. - * @retval NRF_ERROR_NO_MEM If no more space is available in the TX buffer. - * NRF_ERROR_NO_MEM may occur if flow control is enabled and CTS signal - * is high for a long period and the buffer fills up. - */ -uint32_t app_uart_put(uint8_t byte); - -/**@brief Function for getting the current state of the UART. - * - * @details If flow control is disabled, the state is assumed to always be APP_UART_CONNECTED. - * - * When using flow control the state will be controlled by the CTS. If CTS is set active - * by the remote side, or the app_uart module is in the process of transmitting a byte, - * app_uart is in APP_UART_CONNECTED state. If CTS is set inactive by remote side app_uart - * will not get into APP_UART_DISCONNECTED state until the last byte in the TXD register - * is fully transmitted. - * - * Internal states in the state machine are mapped to the general connected/disconnected - * states in the following ways: - * - * - UART_ON = CONNECTED - * - UART_READY = CONNECTED - * - UART_WAIT = CONNECTED - * - UART_OFF = DISCONNECTED. - * - * @param[out] p_connection_state Current connection state of the UART. - * - * @retval NRF_SUCCESS The connection state was succesfully retrieved. - */ -uint32_t app_uart_get_connection_state(app_uart_connection_state_t * p_connection_state); - -/**@brief Function for flushing the RX and TX buffers (Only valid if FIFO is used). - * This function does nothing if FIFO is not used. - * - * @retval NRF_SUCCESS Flushing completed (Current implementation will always succeed). - */ -uint32_t app_uart_flush(void); - -/**@brief Function for closing the UART module. - * - * @details This function will close any on-going UART transmissions and disable itself in the - * GPTIO module. - * - * @param[in] app_uart_uid User id for the UART module. The app_uart_uid must be identical to the - * UART id returned on initialization and which is currently in use. - - * @retval NRF_SUCCESS If successfully closed. - * @retval NRF_ERROR_INVALID_PARAM If an invalid user id is provided or the user id differs from - * the current active user. - */ -uint32_t app_uart_close(uint16_t app_uart_id); - - -#endif //APP_UART_H__ - -/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/app_util.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,232 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup app_util Utility Functions and Definitions - * @{ - * @ingroup app_common - * - * @brief Various types and definitions available to all applications. - */ - -#ifndef APP_UTIL_H__ -#define APP_UTIL_H__ - -#include <stdint.h> -#include <stdbool.h> -#include "compiler_abstraction.h" - -enum -{ - UNIT_0_625_MS = 625, /**< Number of microseconds in 0.625 milliseconds. */ - UNIT_1_25_MS = 1250, /**< Number of microseconds in 1.25 milliseconds. */ - UNIT_10_MS = 10000 /**< Number of microseconds in 10 milliseconds. */ -}; - -/**@brief Macro for doing static (i.e. compile time) assertion. - * - * @note If the assertion fails when compiling using Keil, the compiler will report error message - * "error: #94: the size of an array must be greater than zero" (while gcc will list the - * symbol static_assert_failed, making the error message more readable). - * If the supplied expression can not be evaluated at compile time, Keil will report - * "error: #28: expression must have a constant value". - * - * @note The macro is intentionally implemented not using do while(0), allowing it to be used - * outside function blocks (e.g. close to global type- and variable declarations). - * If used in a code block, it must be used before any executable code in this block. - * - * @param[in] EXPR Constant expression to be verified. - */ - -#if defined(__GNUC__) -#define STATIC_ASSERT(EXPR) typedef char __attribute__((unused)) static_assert_failed[(EXPR) ? 1 : -1] -#else -#define STATIC_ASSERT(EXPR) typedef char static_assert_failed[(EXPR) ? 1 : -1] -#endif - - -/**@brief type for holding an encoded (i.e. little endian) 16 bit unsigned integer. */ -typedef uint8_t uint16_le_t[2]; - -/**@brief type for holding an encoded (i.e. little endian) 32 bit unsigned integer. */ -typedef uint8_t uint32_le_t[4]; - -/**@brief Byte array type. */ -typedef struct -{ - uint16_t size; /**< Number of array entries. */ - uint8_t * p_data; /**< Pointer to array entries. */ -} uint8_array_t; - -/**@brief Perform rounded integer division (as opposed to truncating the result). - * - * @param[in] A Numerator. - * @param[in] B Denominator. - * - * @return Rounded (integer) result of dividing A by B. - */ -#define ROUNDED_DIV(A, B) (((A) + ((B) / 2)) / (B)) - -/**@brief Check if the integer provided is a power of two. - * - * @param[in] A Number to be tested. - * - * @return true if value is power of two. - * @return false if value not power of two. - */ -#define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) ) - -/**@brief To convert ticks to millisecond - * @param[in] time Number of millseconds that needs to be converted. - * @param[in] resolution Units to be converted. - */ -#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION)) - - -/**@brief Perform integer division, making sure the result is rounded up. - * - * @details One typical use for this is to compute the number of objects with size B is needed to - * hold A number of bytes. - * - * @param[in] A Numerator. - * @param[in] B Denominator. - * - * @return Integer result of dividing A by B, rounded up. - */ -#define CEIL_DIV(A, B) \ - /*lint -save -e573 */ \ - ((((A) - 1) / (B)) + 1) \ - /*lint -restore */ - -/**@brief Function for encoding a uint16 value. - * - * @param[in] value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t uint16_encode(uint16_t value, uint8_t * p_encoded_data) -{ - p_encoded_data[0] = (uint8_t) ((value & 0x00FF) >> 0); - p_encoded_data[1] = (uint8_t) ((value & 0xFF00) >> 8); - return sizeof(uint16_t); -} - -/**@brief Function for encoding a uint32 value. - * - * @param[in] value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t uint32_encode(uint32_t value, uint8_t * p_encoded_data) -{ - p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0); - p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8); - p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16); - p_encoded_data[3] = (uint8_t) ((value & 0xFF000000) >> 24); - return sizeof(uint32_t); -} - -/**@brief Function for decoding a uint16 value. - * - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * - * @return Decoded value. - */ -static __INLINE uint16_t uint16_decode(const uint8_t * p_encoded_data) -{ - return ( (((uint16_t)((uint8_t *)p_encoded_data)[0])) | - (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 )); -} - -/**@brief Function for decoding a uint32 value. - * - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * - * @return Decoded value. - */ -static __INLINE uint32_t uint32_decode(const uint8_t * p_encoded_data) -{ - return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) | - (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) | - (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) | - (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 )); -} - -/** @brief Function for converting the input voltage (in milli volts) into percentage of 3.0 Volts. - * - * @details The calculation is based on a linearized version of the battery's discharge - * curve. 3.0V returns 100% battery level. The limit for power failure is 2.1V and - * is considered to be the lower boundary. - * - * The discharge curve for CR2032 is non-linear. In this model it is split into - * 4 linear sections: - * - Section 1: 3.0V - 2.9V = 100% - 42% (58% drop on 100 mV) - * - Section 2: 2.9V - 2.74V = 42% - 18% (24% drop on 160 mV) - * - Section 3: 2.74V - 2.44V = 18% - 6% (12% drop on 300 mV) - * - Section 4: 2.44V - 2.1V = 6% - 0% (6% drop on 340 mV) - * - * These numbers are by no means accurate. Temperature and - * load in the actual application is not accounted for! - * - * @param[in] mvolts The voltage in mV - * - * @return Battery level in percent. -*/ -static __INLINE uint8_t battery_level_in_percent(const uint16_t mvolts) -{ - uint8_t battery_level; - - if (mvolts >= 3000) - { - battery_level = 100; - } - else if (mvolts > 2900) - { - battery_level = 100 - ((3000 - mvolts) * 58) / 100; - } - else if (mvolts > 2740) - { - battery_level = 42 - ((2900 - mvolts) * 24) / 160; - } - else if (mvolts > 2440) - { - battery_level = 18 - ((2740 - mvolts) * 12) / 300; - } - else if (mvolts > 2100) - { - battery_level = 6 - ((2440 - mvolts) * 6) / 340; - } - else - { - battery_level = 0; - } - - return battery_level; -} - -/**@brief Function for checking if a pointer value is aligned to a 4 byte boundary. - * - * @param[in] p Pointer value to be checked. - * - * @return TRUE if pointer is aligned to a 4 byte boundary, FALSE otherwise. - */ -static __INLINE bool is_word_aligned(void * p) -{ - return (((uintptr_t)p & 0x03) == 0); -} - -#endif // APP_UTIL_H__ - -/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/crc16.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,52 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup crc_compute CRC compute - * @{ - * @ingroup hci_transport - * - * @brief This module implements the CRC-16 calculation in the blocks. - */ - -#ifndef CRC16_H__ -#define CRC16_H__ - -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/**@brief Function for calculating CRC-16 in blocks. - * - * Feed each consecutive data block into this function, along with the current value of p_crc as - * returned by the previous call of this function. The first call of this function should pass NULL - * as the initial value of the crc in p_crc. - * - * @param[in] p_data The input data block for computation. - * @param[in] size The size of the input data block in bytes. - * @param[in] p_crc The previous calculated CRC-16 value or NULL if first call. - * - * @return The updated CRC-16 value, based on the input supplied. - */ -uint16_t crc16_compute(const uint8_t * p_data, uint32_t size, const uint16_t * p_crc); - -#ifdef __cplusplus -} -#endif - - -#endif // CRC16_H__ - -/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hal_transport.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,227 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup hci_transport HCI Transport - * @{ - * @ingroup app_common - * - * @brief HCI transport module implementation. - * - * This module implements certain specific features from the three-wire UART transport layer, - * defined by the Bluetooth specification version 4.0 [Vol 4] part D. - * - * \par Features supported - * - Transmission and reception of Vendor Specific HCI packet type application packets. - * - Transmission and reception of reliable packets: defined by chapter 6 of the specification. - * - * \par Features not supported - * - Link establishment procedure: defined by chapter 8 of the specification. - * - Low power: defined by chapter 9 of the specification. - * - * \par Implementation specific behaviour - * - As Link establishment procedure is not supported following static link configuration parameters - * are used: - * + TX window size is 1. - * + 16 bit CCITT-CRC must be used. - * + Out of frame software flow control not supported. - * + Parameters specific for resending reliable packets are compile time configurable (clarifed - * later in this document). - * + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for - * transmission within same context which the corresponding application packet was received. - * - * \par Implementation specific limitations - * Current implementation has the following limitations which will have impact to system wide - * behaviour: - * - Delayed acknowledgement scheduling not implemented: - * There exists a possibility that acknowledgement TX packet and application TX packet will collide - * in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX - * pipeline which will trigger the retransmission algorithm within the peer protocol entity. - * - Delayed retransmission scheduling not implemented: - * There exists a possibility that retransmitted application TX packet and acknowledgement TX packet - * will collide in the TX pipeline having the end result that retransmitted application TX packet - * will be excluded from the TX pipeline. - * - Processing of the acknowledgement number from RX application packets: - * Acknowledgement number is not processed from the RX application packets having the end result - * that unnecessary application packet retransmissions can occur. - * - * The application TX packet processing flow is illustrated by the statemachine below. - * - * @image html hci_transport_tx_sm.png "TX - application packet statemachine" - * - * \par Component specific configuration options - * - * The following compile time configuration options are available, and used to configure the - * application TX packet retransmission interval, in order to suite various application specific - * implementations: - * - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits. - * - USED_BAUD_RATE Used uart baudrate. - * - * The following compile time configuration option is available to configure module specific - * behaviour: - * - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets. - */ - -#ifndef HCI_TRANSPORT_H__ -#define HCI_TRANSPORT_H__ - -#include <stdint.h> -#include "nrf_error.h" - -#define HCI_TRANSPORT_PKT_HEADER_SIZE (2) /**< Size of transport packet header */ - -/**@brief Generic event callback function events. */ -typedef enum -{ - HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */ - HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */ -} hci_transport_evt_type_t; - -/**@brief Struct containing events from the Transport layer. - */ -typedef struct -{ - hci_transport_evt_type_t evt_type; /**< Type of event. */ -} hci_transport_evt_t; - -/**@brief Transport layer generic event callback function type. - * - * @param[in] event Transport layer event. - */ -typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event); - -/**@brief TX done event callback function result codes. */ -typedef enum -{ - HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */ - HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */ -} hci_transport_tx_done_result_t; - -/**@brief Transport layer TX done event callback function type. - * - * @param[in] result TX done event result code. - */ -typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result); - -/**@brief Function for registering a generic event handler. - * - * @note Multiple registration requests will overwrite any possible existing registration. - * - * @param[in] event_handler The function to be called by the transport layer upon an event. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler); - -/**@brief Function for registering a handler for TX done event. - * - * @note Multiple registration requests will overwrite any possible existing registration. - * - * @param[in] event_handler The function to be called by the transport layer upon TX done - * event. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler); - -/**@brief Function for opening the transport channel and initializing the transport layer. - * - * @warning Must not be called for a channel which has been allready opened. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred. - */ -uint32_t hci_transport_open(void); - -/**@brief Function for closing the transport channel. - * - * @note Can be called multiple times and also for not opened channel. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_transport_close(void); - -/**@brief Function for allocating tx packet memory. - * - * @param[out] pp_memory Pointer to the packet data. - * - * @retval NRF_SUCCESS Operation success. Memory was allocated. - * @retval NRF_ERROR_NO_MEM Operation failure. No memory available. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory); - -/**@brief Function for freeing tx packet memory. - * - * @note Memory management works in FIFO principle meaning that free order must match the alloc - * order. - * - * @retval NRF_SUCCESS Operation success. Memory was freed. - */ -uint32_t hci_transport_tx_free(void); - -/**@brief Function for writing a packet. - * - * @note Completion of this method does not guarantee that actual peripheral transmission would - * have completed. - * - * @note In case of 0 byte packet length write request, message will consist of only transport - * module specific headers. - * - * @note The buffer provided to this function must be allocated through @ref hci_transport_tx_alloc - * function. - * - * @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue - * and an event will be send upon transmission completion. - * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not - * added to the transmission queue. User should wait for - * a appropriate event prior issuing this operation again. - * @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - * @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open. - * @retval NRF_ERROR_INVALID_ADDR Operation failure. Buffer provided is not allocated through - * hci_transport_tx_alloc function. - */ -uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint16_t length); - -/**@brief Function for extracting received packet. - * - * @note Extracted memory can't be reused by the underlying transport layer untill freed by call to - * hci_transport_rx_pkt_consume(). - * - * @param[out] pp_buffer Pointer to the packet data. - * @param[out] p_length Length of packet data in bytes. - * - * @retval NRF_SUCCESS Operation success. Packet was extracted. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint16_t * p_length); - -/**@brief Function for consuming extracted packet described by p_buffer. - * - * RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer. - * - * @param[in] p_buffer Pointer to the buffer that has been consumed. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume. - * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer. - */ -uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer); - -#endif // HCI_TRANSPORT_H__ - -/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,132 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup memory_pool Memory pool - * @{ - * @ingroup app_common - * - * @brief Memory pool implementation - * - * Memory pool implementation, based on circular buffer data structure, which supports asynchronous - * processing of RX data. The current default implementation supports 1 TX buffer and 4 RX buffers. - * The memory managed by the pool is allocated from static storage instead of heap. The internal - * design of the circular buffer implementing the RX memory layout is illustrated in the picture - * below. - * - * @image html memory_pool.png "Circular buffer design" - * - * The expected call order for the RX APIs is as follows: - * - hci_mem_pool_rx_produce - * - hci_mem_pool_rx_data_size_set - * - hci_mem_pool_rx_extract - * - hci_mem_pool_rx_consume - * - * @warning If the above mentioned expected call order is violated the end result can be undefined. - * - * \par Component specific configuration options - * - * The following compile time configuration options are available to suit various implementations: - * - TX_BUF_SIZE TX buffer size in bytes. - * - RX_BUF_SIZE RX buffer size in bytes. - * - RX_BUF_QUEUE_SIZE RX buffer element size. - */ - -#ifndef HCI_MEM_POOL_H__ -#define HCI_MEM_POOL_H__ - -#include <stdint.h> -#include "nrf_error.h" - -/**@brief Function for opening the module. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_mem_pool_open(void); - -/**@brief Function for closing the module. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_mem_pool_close(void); - -/**@brief Function for allocating requested amount of TX memory. - * - * @param[out] pp_buffer Pointer to the allocated memory. - * - * @retval NRF_SUCCESS Operation success. Memory was allocated. - * @retval NRF_ERROR_NO_MEM Operation failure. No memory available for allocation. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer); - -/**@brief Function for freeing previously allocated TX memory. - * - * @note Memory management follows the FIFO principle meaning that free() order must match the - * alloc(...) order, which is the reason for omitting exact memory block identifier as an - * input parameter. - * - * @retval NRF_SUCCESS Operation success. Memory was freed. - */ -uint32_t hci_mem_pool_tx_free(void); - -/**@brief Function for producing a free RX memory block for usage. - * - * @note Upon produce request amount being 0, NRF_SUCCESS is returned. - * - * @param[in] length Amount, in bytes, of free memory to be produced. - * @param[out] pp_buffer Pointer to the allocated memory. - * - * @retval NRF_SUCCESS Operation success. Free RX memory block produced. - * @retval NRF_ERROR_NO_MEM Operation failure. No suitable memory available for allocation. - * @retval NRF_ERROR_DATA_SIZE Operation failure. Request size exceeds limit. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer); - -/**@brief Function for setting the length of the last produced RX memory block. - * - * @warning If call to this API is omitted the end result is that the following call to - * mem_pool_rx_extract will return incorrect data in the p_length output parameter. - * - * @param[in] length Amount, in bytes, of actual memory used. - * - * @retval NRF_SUCCESS Operation success. Length was set. - */ -uint32_t hci_mem_pool_rx_data_size_set(uint32_t length); - -/**@brief Function for extracting a packet, which has been filled with read data, for further - * processing. - * - * @param[out] pp_buffer Pointer to the packet data. - * @param[out] p_length Length of packet data in bytes. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length); - -/**@brief Function for freeing previously extracted packet, which has been filled with read data. - * - * @param[in] p_buffer Pointer to consumed buffer. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to free. - * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer. - */ -uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer); - -#endif // HCI_MEM_POOL_H__ - -/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_mem_pool_internal.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,32 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup memory_pool_internal Memory Pool Internal - * @{ - * @ingroup memory_pool - * - * @brief Memory pool internal definitions - */ - -#ifndef MEM_POOL_INTERNAL_H__ -#define MEM_POOL_INTERNAL_H__ - -#define TX_BUF_SIZE 600u /**< TX buffer size in bytes. */ -#define RX_BUF_SIZE TX_BUF_SIZE /**< RX buffer size in bytes. */ - -#define RX_BUF_QUEUE_SIZE 4u /**< RX buffer element size. */ - -#endif // MEM_POOL_INTERNAL_H__ - -/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_slip.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,129 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup hci_slip SLIP module - * @{ - * @ingroup app_common - * - * @brief SLIP layer for supporting packet framing in HCI transport. - * - * @details This module implements SLIP packet framing as described in the Bluetooth Core - * Specification 4.0, Volume 4, Part D, Chapter 3 SLIP Layer. - * - * SLIP framing ensures that all packets sent on the UART are framed as: - * <0xC0> SLIP packet 1 <0xC0> <0xC0> SLIP packet 2 <0xC0>. - * - * The SLIP layer uses events to notify the upper layer when data transmission is complete - * and when a SLIP packet is received. - */ - -#ifndef HCI_SLIP_H__ -#define HCI_SLIP_H__ - -#include <stdint.h> - -/**@brief Event types from the SLIP Layer. */ -typedef enum -{ - HCI_SLIP_RX_RDY, /**< An event indicating that an RX packet is ready to be read. */ - HCI_SLIP_TX_DONE, /**< An event indicating write completion of the TX packet provided in the function call \ref hci_slip_write . */ - HCI_SLIP_RX_OVERFLOW, /**< An event indicating that RX data has been discarded due to lack of free RX memory. */ - HCI_SLIP_ERROR, /**< An event indicating that an unrecoverable error has occurred. */ - HCI_SLIP_EVT_TYPE_MAX /**< Enumeration upper bound. */ -} hci_slip_evt_type_t; - -/**@brief Structure containing an event from the SLIP layer. - */ -typedef struct -{ - hci_slip_evt_type_t evt_type; /**< Type of event. */ - const uint8_t * packet; /**< This field contains a pointer to the packet for which the event relates, i.e. SLIP_TX_DONE: the packet transmitted, SLIP_RX_RDY: the packet received, SLIP_RX_OVERFLOW: The packet which overflow/or NULL if no receive buffer is available. */ - uint32_t packet_length; /**< Packet length, i.e. SLIP_TX_DONE: Bytes transmitted, SLIP_RX_RDY: Bytes received, SLIP_RX_OVERFLOW: index at which the packet overflowed. */ -} hci_slip_evt_t; - -/**@brief Function for the SLIP layer event callback. - */ -typedef void (*hci_slip_event_handler_t)(hci_slip_evt_t event); - -/**@brief Function for registering the event handler provided as parameter and this event handler - * will be used by SLIP layer to send events described in \ref hci_slip_evt_type_t. - * - * @note Multiple registration requests will overwrite any existing registration. - * - * @param[in] event_handler This function is called by the SLIP layer upon an event. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_slip_evt_handler_register(hci_slip_event_handler_t event_handler); - -/**@brief Function for opening the SLIP layer. This function must be called before - * \ref hci_slip_write and before any data can be received. - * - * @note Can be called multiple times. - * - * @retval NRF_SUCCESS Operation success. - * - * The SLIP layer module will propagate errors from underlying sub-modules. - * This implementation is using UART module as a physical transmission layer, and hci_slip_open - * executes \ref app_uart_init . For an extended error list, please refer to \ref app_uart_init . - */ -uint32_t hci_slip_open(void); - -/**@brief Function for closing the SLIP layer. After this function is called no data can be - * transmitted or received in this layer. - * - * @note This function can be called multiple times and also for an unopened channel. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_slip_close(void); - -/**@brief Function for writing a packet with SLIP encoding. Packet transmission is confirmed when - * the HCI_SLIP_TX_DONE event is received by the function caller. - * - * @param[in] p_buffer Pointer to the packet to transmit. - * @param[in] length Packet length, in bytes. - * - * @retval NRF_SUCCESS Operation success. Packet was encoded and added to the - * transmission queue and an event will be sent upon transmission - * completion. - * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not - * added to the transmission queue. Application shall wait for - * the \ref HCI_SLIP_TX_DONE event. After HCI_SLIP_TX_DONE this - * function can be executed for transmission of next packet. - * @retval NRF_ERROR_INVALID_ADDR If a NULL pointer is provided. - * @retval NRF_ERROR_INVALID_STATE Operation failure. Module is not open. - */ -uint32_t hci_slip_write(const uint8_t * p_buffer, uint32_t length); - -/**@brief Function for registering a receive buffer. The receive buffer will be used for storage of - * received and SLIP decoded data. - * No data can be received by the SLIP layer until a receive buffer has been registered. - * - * @note The lifetime of the buffer must be valid during complete reception of data. A static - * buffer is recommended. - * - * @warning Multiple registration requests will overwrite any existing registration. - * - * @param[in] p_buffer Pointer to receive buffer. The received and SLIP decoded packet - * will be placed in this buffer. - * @param[in] length Buffer length, in bytes. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_slip_rx_buffer_register(uint8_t * p_buffer, uint32_t length); - -#endif // HCI_SLIP_H__ - -/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/hci_transport.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,220 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup hci_transport HCI Transport - * @{ - * @ingroup app_common - * - * @brief HCI transport module implementation. - * - * This module implements certain specific features from the three-wire UART transport layer, - * defined by the Bluetooth specification version 4.0 [Vol 4] part D. - * - * \par Features supported - * - Transmission and reception of Vendor Specific HCI packet type application packets. - * - Transmission and reception of reliable packets: defined by chapter 6 of the specification. - * - * \par Features not supported - * - Link establishment procedure: defined by chapter 8 of the specification. - * - Low power: defined by chapter 9 of the specification. - * - * \par Implementation specific behaviour - * - As Link establishment procedure is not supported following static link configuration parameters - * are used: - * + TX window size is 1. - * + 16 bit CCITT-CRC must be used. - * + Out of frame software flow control not supported. - * + Parameters specific for resending reliable packets are compile time configurable (clarifed - * later in this document). - * + Acknowledgement packet transmissions are not timeout driven , meaning they are delivered for - * transmission within same context which the corresponding application packet was received. - * - * \par Implementation specific limitations - * Current implementation has the following limitations which will have impact to system wide - * behaviour: - * - Delayed acknowledgement scheduling not implemented: - * There exists a possibility that acknowledgement TX packet and application TX packet will collide - * in the TX pipeline having the end result that acknowledgement packet will be excluded from the TX - * pipeline which will trigger the retransmission algorithm within the peer protocol entity. - * - Delayed retransmission scheduling not implemented: - * There exists a possibility that retransmitted application TX packet and acknowledgement TX packet - * will collide in the TX pipeline having the end result that retransmitted application TX packet - * will be excluded from the TX pipeline. - * - Processing of the acknowledgement number from RX application packets: - * Acknowledgement number is not processed from the RX application packets having the end result - * that unnecessary application packet retransmissions can occur. - * - * The application TX packet processing flow is illustrated by the statemachine below. - * - * @image html hci_transport_tx_sm.png "TX - application packet statemachine" - * - * \par Component specific configuration options - * - * The following compile time configuration options are available, and used to configure the - * application TX packet retransmission interval, in order to suite various application specific - * implementations: - * - MAC_PACKET_SIZE_IN_BITS Maximum size of a single application packet in bits. - * - USED_BAUD_RATE Used uart baudrate. - * - * The following compile time configuration option is available to configure module specific - * behaviour: - * - MAX_RETRY_COUNT Max retransmission retry count for applicaton packets. - */ - -#ifndef HCI_TRANSPORT_H__ -#define HCI_TRANSPORT_H__ - -#include <stdint.h> -#include "nrf_error.h" - -/**@brief Generic event callback function events. */ -typedef enum -{ - HCI_TRANSPORT_RX_RDY, /**< An event indicating that RX packet is ready for read. */ - HCI_TRANSPORT_EVT_TYPE_MAX /**< Enumeration upper bound. */ -} hci_transport_evt_type_t; - -/**@brief Struct containing events from the Transport layer. - */ -typedef struct -{ - hci_transport_evt_type_t evt_type; /**< Type of event. */ -} hci_transport_evt_t; - -/**@brief Transport layer generic event callback function type. - * - * @param[in] event Transport layer event. - */ -typedef void (*hci_transport_event_handler_t)(hci_transport_evt_t event); - -/**@brief TX done event callback function result codes. */ -typedef enum -{ - HCI_TRANSPORT_TX_DONE_SUCCESS, /**< Transmission success, peer transport entity has acknowledged the transmission. */ - HCI_TRANSPORT_TX_DONE_FAILURE /**< Transmission failure. */ -} hci_transport_tx_done_result_t; - -/**@brief Transport layer TX done event callback function type. - * - * @param[in] result TX done event result code. - */ -typedef void (*hci_transport_tx_done_handler_t)(hci_transport_tx_done_result_t result); - -/**@brief Function for registering a generic event handler. - * - * @note Multiple registration requests will overwrite any possible existing registration. - * - * @param[in] event_handler The function to be called by the transport layer upon an event. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_evt_handler_reg(hci_transport_event_handler_t event_handler); - -/**@brief Function for registering a handler for TX done event. - * - * @note Multiple registration requests will overwrite any possible existing registration. - * - * @param[in] event_handler The function to be called by the transport layer upon TX done - * event. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_tx_done_register(hci_transport_tx_done_handler_t event_handler); - -/**@brief Function for opening the transport channel and initializing the transport layer. - * - * @warning Must not be called for a channel which has been allready opened. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_INTERNAL Operation failure. Internal error ocurred. - */ -uint32_t hci_transport_open(void); - -/**@brief Function for closing the transport channel. - * - * @note Can be called multiple times and also for not opened channel. - * - * @retval NRF_SUCCESS Operation success. - */ -uint32_t hci_transport_close(void); - -/**@brief Function for allocating tx packet memory. - * - * @param[out] pp_memory Pointer to the packet data. - * - * @retval NRF_SUCCESS Operation success. Memory was allocated. - * @retval NRF_ERROR_NO_MEM Operation failure. No memory available. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_tx_alloc(uint8_t ** pp_memory); - -/**@brief Function for freeing tx packet memory. - * - * @note Memory management works in FIFO principle meaning that free order must match the alloc - * order. - * - * @retval NRF_SUCCESS Operation success. Memory was freed. - */ -uint32_t hci_transport_tx_free(void); - -/**@brief Function for writing a packet. - * - * @note Completion of this method does not guarantee that actual peripheral transmission would - * have completed. - * - * @note In case of 0 byte packet length write request, message will consist of only transport - * module specific headers. - * - * @retval NRF_SUCCESS Operation success. Packet was added to the transmission queue - * and an event will be send upon transmission completion. - * @retval NRF_ERROR_NO_MEM Operation failure. Transmission queue is full and packet was not - * added to the transmission queue. User should wait for - * a appropriate event prior issuing this operation again. - * @retval NRF_ERROR_DATA_SIZE Operation failure. Packet size exceeds limit. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - * @retval NRF_ERROR_INVALID_STATE Operation failure. Channel is not open. - */ -uint32_t hci_transport_pkt_write(const uint8_t * p_buffer, uint32_t length); - -/**@brief Function for extracting received packet. - * - * @note Extracted memory can't be reused by the underlying transport layer untill freed by call to - * hci_transport_rx_pkt_consume(). - * - * @param[out] pp_buffer Pointer to the packet data. - * @param[out] p_length Length of packet data in bytes. - * - * @retval NRF_SUCCESS Operation success. Packet was extracted. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to extract. - * @retval NRF_ERROR_NULL Operation failure. NULL pointer supplied. - */ -uint32_t hci_transport_rx_pkt_extract(uint8_t ** pp_buffer, uint32_t * p_length); - -/**@brief Function for consuming extracted packet described by p_buffer. - * - * RX memory pointed to by p_buffer is freed and can be reused by the underlying transport layer. - * - * @param[in] p_buffer Pointer to the buffer that has been consumed. - * - * @retval NRF_SUCCESS Operation success. - * @retval NRF_ERROR_NO_MEM Operation failure. No packet available to consume. - * @retval NRF_ERROR_INVALID_ADDR Operation failure. Not a valid pointer. - */ -uint32_t hci_transport_rx_pkt_consume(uint8_t * p_buffer); - -#endif // HCI_TRANSPORT_H__ - -/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/app_common/pstorage.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,381 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup persistent_storage Persistent Storage Interface - * @{ - * @ingroup app_common - * @brief Abstracted flash interface. - * - * @details In order to ensure that the SDK and application be moved to alternate persistent storage - * options other than the default provided with NRF solution, an abstracted interface is provided - * by the module to ensure SDK modules and application can be ported to alternate option with ease. - */ - -#ifndef PSTORAGE_H__ -#define PSTORAGE_H__ - -#ifdef __cplusplus -extern "C" { -#endif /* #ifdef __cplusplus */ - -#include "pstorage_platform.h" - - -/**@defgroup ps_opcode Persistent Storage Access Operation Codes - * @{ - * @brief Persistent Storage Access Operation Codes. These are used to report any error during - * a persistent storage access operation or any general error that may occur in the - * interface. - * - * @details Persistent Storage Access Operation Codes used in error notification callback - * registered with the interface to report any error during an persistent storage access - * operation or any general error that may occur in the interface. - */ -#define PSTORAGE_ERROR_OP_CODE 0x01 /**< General Error Code */ -#define PSTORAGE_STORE_OP_CODE 0x02 /**< Error when Store Operation was requested */ -#define PSTORAGE_LOAD_OP_CODE 0x03 /**< Error when Load Operation was requested */ -#define PSTORAGE_CLEAR_OP_CODE 0x04 /**< Error when Clear Operation was requested */ -#define PSTORAGE_UPDATE_OP_CODE 0x05 /**< Update an already touched storage block */ - -/**@} */ - -/**@defgroup pstorage_data_types Persistent Memory Interface Data Types - * @{ - * @brief Data Types needed for interfacing with persistent memory. - * - * @details Data Types needed for interfacing with persistent memory. - */ - -/**@brief Persistent Storage Error Reporting Callback - * - * @details Persistent Storage Error Reporting Callback that is used by the interface to report - * success or failure of a flash operation. Therefore, for any operations, application - * can know when the procedure was complete. For store operation, since no data copy - * is made, receiving a success or failure notification, indicated by the reason - * parameter of callback is an indication that the resident memory could now be reused - * or freed, as the case may be. - * - * @param[in] handle Identifies module and block for which callback is received. - * @param[in] op_code Identifies the operation for which the event is notified. - * @param[in] result Identifies the result of flash access operation. - * NRF_SUCCESS implies, operation succeeded. - * @param[in] p_data Identifies the application data pointer. In case of store operation, this - * points to the resident source of application memory that application can now - * free or reuse. In case of clear, this is NULL as no application pointer is - * needed for this operation. - * @param[in] data_len Length data application had provided for the operation. - * - */ -typedef void (*pstorage_ntf_cb_t)(pstorage_handle_t * p_handle, - uint8_t op_code, - uint32_t result, - uint8_t * p_data, - uint32_t data_len); - - -typedef struct -{ - pstorage_ntf_cb_t cb; /**< Callback registered with the module to be notified of any error occurring in persistent memory management */ - pstorage_size_t block_size; /**< Desired block size for persistent memory storage, for example, if a module has a table with 10 entries, each entry is size 64 bytes, - * it can request 10 blocks with block size 64 bytes. On the other hand, the module can also request one block of size 640 based on - * how it would like to access or alter memory in persistent memory. - * First option is preferred when single entries that need to be updated often when having no impact on the other entries. - * While second option is preferred when entries of table are not changed on individually but have common point of loading and storing - * data. */ - pstorage_size_t block_count; /** Number of blocks requested by the module, minimum values is 1. */ -} pstorage_module_param_t; - -/**@} */ - -/**@defgroup pstorage_routines Persistent Storage Access Routines - * @{ - * @brief Functions/Interface SDK modules use to persistently store data. - * - * @details Interface for Application & SDK module to load/store information persistently. - * Note: that while implementation of each of the persistent storage access function - * depends on the system and can specific to system/solution, the signature of the - * interface routines should not be altered. - */ - -/**@brief Module Initialization Routine. - * - * @details Initializes module. To be called once before any other APIs of the module are used. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - */ -uint32_t pstorage_init(void); - - -/**@brief Register with persistent storage interface. - * - * @param[in] p_module_param Module registration param. - * @param[out] p_block_id Block identifier to identify persistent memory blocks in case - * registration succeeds. Application is expected to use the block ids - * for subsequent operations on requested persistent memory. Maximum - * registrations permitted is determined by configuration parameter - * PSTORAGE_MAX_APPLICATIONS. - * In case more than one memory blocks are requested, the identifier provided here is - * the base identifier for the first block and to identify subsequent block, - * application shall use \@ref pstorage_block_identifier_get with this base identifier - * and block number. Therefore if 10 blocks of size 64 are requested and application - * wishes to store memory in 6th block, it shall use - * \@ref pstorage_block_identifier_get with based id and provide a block number of 5. - * This way application is only expected to remember the base block identifier. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_NO_MEM in case no more registrations can be supported. - */ -uint32_t pstorage_register(pstorage_module_param_t * p_module_param, - pstorage_handle_t * p_block_id); - - -/** - * @brief Function to get block id with reference to base block identifier provided at time of - * registration. - * - * @details Function to get block id with reference to base block identifier provided at time of - * registration. - * In case more than one memory blocks were requested when registering, the identifier - * provided here is the base identifier for the first block and to identify subsequent - * block, application shall use this routine to get block identifier providing input as - * base identifier and block number. Therefore if 10 blocks of size 64 are requested and - * application wishes to store memory in 6th block, it shall use - * \@ref pstorage_block_identifier_get with based id and provide a block number of 5. - * This way application is only expected to remember the base block identifier. - * - * @param[in] p_base_id Base block id received at the time of registration. - * @param[in] block_num Block Number, with first block numbered zero. - * @param[out] p_block_id Block identifier for the block number requested in case the API succeeds. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - */ -uint32_t pstorage_block_identifier_get(pstorage_handle_t * p_base_id, - pstorage_size_t block_num, - pstorage_handle_t * p_block_id); - - -/**@brief Routine to persistently store data of length 'size' contained in 'p_src' address - * in storage module at 'p_dest' address; Equivalent to Storage Write. - * - * @param[in] p_dest Destination address where data is to be stored persistently. - * @param[in] p_src Source address containing data to be stored. API assumes this to be resident - * memory and no intermediate copy of data is made by the API. - * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned. - * @param[in] offset Offset in bytes to be applied when writing to the block. - * For example, if within a block of 100 bytes, application wishes to - * write 20 bytes at offset of 12, then this field should be set to 12. - * Should be word aligned. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - * - * @warning No copy of the data is made, and hence memory provided for data source to be written - * to flash cannot be freed or reused by the application until this procedure - * is complete. End of this procedure is notified to the application using the - * notification callback registered by the application. - */ -uint32_t pstorage_store(pstorage_handle_t * p_dest, - uint8_t * p_src, - pstorage_size_t size, - pstorage_size_t offset); - -/**@brief Routine to update persistently stored data of length 'size' contained in 'p_src' address - * in storage module at 'p_dest' address. - * - * @param[in] p_dest Destination address where data is to be updated. - * @param[in] p_src Source address containing data to be stored. API assumes this to be resident - * memory and no intermediate copy of data is made by the API. - * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned. - * @param[in] offset Offset in bytes to be applied when writing to the block. - * For example, if within a block of 100 bytes, application wishes to - * write 20 bytes at offset of 12, then this field should be set to 12. - * Should be word aligned. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - * - * @warning No copy of the data is made, and hence memory provided for data source to be written - * to flash cannot be freed or reused by the application until this procedure - * is complete. End of this procedure is notified to the application using the - * notification callback registered by the application. - */ -uint32_t pstorage_update(pstorage_handle_t * p_dest, - uint8_t * p_src, - pstorage_size_t size, - pstorage_size_t offset); - -/**@brief Routine to load persistently stored data of length 'size' from 'p_src' address - * to 'p_dest' address; Equivalent to Storage Read. - * - * @param[in] p_dest Destination address where persistently stored data is to be loaded. - * @param[in] p_src Source from where data is to be loaded from persistent memory. - * @param[in] size Size of data to be loaded from persistent memory expressed in bytes. - * Should be word aligned. - * @param[in] offset Offset in bytes to be applied when loading from the block. - * For example, if within a block of 100 bytes, application wishes to - * load 20 bytes from offset of 12, then this field should be set to 12. - * Should be word aligned. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_dst' is not aligned. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - */ -uint32_t pstorage_load(uint8_t * p_dest, - pstorage_handle_t * p_src, - pstorage_size_t size, - pstorage_size_t offset); - -/**@brief Routine to clear data in persistent memory. - * - * @param[in] p_base_id Base block identifier in persistent memory that needs to cleared; - * Equivalent to an Erase Operation. - * - * @param[in] size Size of data to be cleared from persistent memory expressed in bytes. - * This parameter is to provision for clearing of certain blocks - * of memory, or all memory blocks in a registered module. If the total size - * of the application module is used (blocks * block size) in combination with - * the identifier for the first block in the module, all blocks in the - * module will be erased. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_dst' is not aligned. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - * - * @note Clear operations may take time. This API however, does not block until the clear - * procedure is complete. Application is notified of procedure completion using - * notification callback registered by the application. 'result' parameter of the - * callback suggests if the procedure was successful or not. - */ -uint32_t pstorage_clear(pstorage_handle_t * p_base_id, pstorage_size_t size); - -/** - * @brief API to get status of number of pending operations with the module. - * - * @param[out] p_count Number of storage operations pending with the module, if 0, - * there are no outstanding requests. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - */ -uint32_t pstorage_access_status_get(uint32_t * p_count); - -#ifdef PSTORAGE_RAW_MODE_ENABLE - -/**@brief Function for registering with persistent storage interface. - * - * @param[in] p_module_param Module registration param. - * @param[out] p_block_id Block identifier to identify persistent memory blocks in case - * registration succeeds. Application is expected to use the block ids - * for subsequent operations on requested persistent memory. - * In case more than one memory blocks are requested, the identifier provided here is - * the base identifier for the first block and to identify subsequent block, - * application shall use \@ref pstorage_block_identifier_get with this base identifier - * and block number. Therefore if 10 blocks of size 64 are requested and application - * wishes to store memory in 6th block, it shall use - * \@ref pstorage_block_identifier_get with based id and provide a block number of 5. - * This way application is only expected to remember the base block identifier. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_NO_MEM in case no more registrations can be supported. - */ -uint32_t pstorage_raw_register(pstorage_module_param_t * p_module_param, - pstorage_handle_t * p_block_id); - -/**@brief Raw mode function for persistently storing data of length 'size' contained in 'p_src' - * address in storage module at 'p_dest' address; Equivalent to Storage Write. - * - * @param[in] p_dest Destination address where data is to be stored persistently. - * @param[in] p_src Source address containing data to be stored. API assumes this to be resident - * memory and no intermediate copy of data is made by the API. - * @param[in] size Size of data to be stored expressed in bytes. Should be word aligned. - * @param[in] offset Offset in bytes to be applied when writing to the block. - * For example, if within a block of 100 bytes, application wishes to - * write 20 bytes at offset of 12, then this field should be set to 12. - * Should be word aligned. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_INVALID_ADDR in case data address 'p_src' is not aligned. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - * - * @warning No copy of the data is made, and hence memory provided for data source to be written - * to flash cannot be freed or reused by the application until this procedure - * is complete. End of this procedure is notified to the application using the - * notification callback registered by the application. - */ -uint32_t pstorage_raw_store(pstorage_handle_t * p_dest, - uint8_t * p_src, - pstorage_size_t size, - pstorage_size_t offset); - -/**@brief Function for clearing data in persistent memory in raw mode. - * - * @param[in] p_dest Base block identifier in persistent memory that needs to cleared; - * Equivalent to an Erase Operation. - * @param[in] size Size of data to be cleared from persistent memory expressed in bytes. - * This is currently unused. And a clear would mean clearing all blocks, - * however, this parameter is to provision for clearing of certain blocks - * of memory only and not all if need be. - * - * @retval NRF_SUCCESS on success, else an error code indicating reason for failure. - * @retval NRF_ERROR_INVALID_STATE is returned is API is called without module initialization. - * @retval NRF_ERROR_NULL if NULL parameter has been passed. - * @retval NRF_ERROR_INVALID_PARAM if invalid parameters are passed to the API. - * @retval NRF_ERROR_NO_MEM in case request cannot be processed. - * - * @note Clear operations may take time. This API however, does not block until the clear - * procedure is complete. Application is notified of procedure completion using - * notification callback registered by the application. 'result' parameter of the - * callback suggests if the procedure was successful or not. - */ -uint32_t pstorage_raw_clear(pstorage_handle_t * p_dest, pstorage_size_t size); - -#endif // PSTORAGE_RAW_MODE_ENABLE - -#ifdef __cplusplus -} -#endif /* #ifdef __cplusplus */ - - -/**@} */ -/**@} */ - -#endif // PSTORAGE_H__ -
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/nrf_delay.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,74 +0,0 @@ -#ifndef _NRF_DELAY_H -#define _NRF_DELAY_H - -// #include "nrf.h" - -/*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */ -#if defined ( __CC_ARM ) -static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us) -{ -loop - SUBS R0, R0, #1 - NOP - NOP - NOP - NOP - NOP - NOP - NOP - NOP - NOP - NOP - NOP - NOP - BNE loop - BX LR -} -#elif defined ( __ICCARM__ ) -static void __INLINE nrf_delay_us(uint32_t volatile number_of_us) -{ -__ASM ( -"loop:\n\t" - " SUBS R0, R0, #1\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " BNE loop\n\t"); -} -#elif defined ( __GNUC__ ) -static void __INLINE nrf_delay_us(uint32_t volatile number_of_us) -{ - do - { - __ASM volatile ( - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - ); - } while (--number_of_us); -} -#endif - -void nrf_delay_ms(uint32_t volatile number_of_ms); - -#endif
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nrf-sdk/sd_common/app_util_platform.h Tue Mar 31 16:15:13 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,110 +0,0 @@ -/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/**@file - * - * @defgroup app_util_platform Utility Functions and Definitions (Platform) - * @{ - * @ingroup app_common - * - * @brief Various types and definitions available to all applications when using SoftDevice. - */ - -#ifndef APP_UTIL_PLATFORM_H__ -#define APP_UTIL_PLATFORM_H__ - -#include <stdint.h> -#include "compiler_abstraction.h" -#include "nrf51.h" -#include "app_error.h" - -/**@brief The interrupt priorities available to the application while the SoftDevice is active. */ -typedef enum -{ - APP_IRQ_PRIORITY_HIGH = 1, - APP_IRQ_PRIORITY_LOW = 3 -} app_irq_priority_t; - -#define NRF_APP_PRIORITY_THREAD 4 /**< "Interrupt level" when running in Thread Mode. */ - -/**@cond NO_DOXYGEN */ -#define EXTERNAL_INT_VECTOR_OFFSET 16 -/**@endcond */ - -#define PACKED(TYPE) __packed TYPE - -/**@brief Macro for entering a critical region. - * - * @note Due to implementation details, there must exist one and only one call to - * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located - * in the same scope. - */ -#define CRITICAL_REGION_ENTER() \ - { \ - uint8_t IS_NESTED_CRITICAL_REGION = 0; \ - uint32_t CURRENT_INT_PRI = current_int_priority_get(); \ - if (CURRENT_INT_PRI != APP_IRQ_PRIORITY_HIGH) \ - { \ - uint32_t ERR_CODE = sd_nvic_critical_region_enter(&IS_NESTED_CRITICAL_REGION); \ - if (ERR_CODE == NRF_ERROR_SOFTDEVICE_NOT_ENABLED) \ - { \ - __disable_irq(); \ - } \ - else \ - { \ - APP_ERROR_CHECK(ERR_CODE); \ - } \ - } - -/**@brief Macro for leaving a critical region. - * - * @note Due to implementation details, there must exist one and only one call to - * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located - * in the same scope. - */ -#define CRITICAL_REGION_EXIT() \ - if (CURRENT_INT_PRI != APP_IRQ_PRIORITY_HIGH) \ - { \ - uint32_t ERR_CODE; \ - __enable_irq(); \ - ERR_CODE = sd_nvic_critical_region_exit(IS_NESTED_CRITICAL_REGION); \ - if (ERR_CODE != NRF_ERROR_SOFTDEVICE_NOT_ENABLED) \ - { \ - APP_ERROR_CHECK(ERR_CODE); \ - } \ - } \ - } - -/**@brief Function for finding the current interrupt level. - * - * @return Current interrupt level. - * @retval APP_IRQ_PRIORITY_HIGH We are running in Application High interrupt level. - * @retval APP_IRQ_PRIORITY_LOW We are running in Application Low interrupt level. - * @retval APP_IRQ_PRIORITY_THREAD We are running in Thread Mode. - */ -static __INLINE uint8_t current_int_priority_get(void) -{ - uint32_t isr_vector_num = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); - if (isr_vector_num > 0) - { - int32_t irq_type = ((int32_t)isr_vector_num - EXTERNAL_INT_VECTOR_OFFSET); - return (NVIC_GetPriority((IRQn_Type)irq_type) & 0xFF); - } - else - { - return NRF_APP_PRIORITY_THREAD; - } -} - -#endif // APP_UTIL_PLATFORM_H__ - -/** @} */
--- a/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c Tue Mar 31 16:15:13 2015 +0100 +++ b/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c Tue Apr 07 06:45:07 2015 +0100 @@ -194,10 +194,10 @@ if (enable) { switch (irq) { case RxIrq: - obj->uart->INTEN |= (UART_INTENSET_RXDRDY_Msk); + obj->uart->INTENSET = (UART_INTENSET_RXDRDY_Msk); break; case TxIrq: - obj->uart->INTEN |= (UART_INTENSET_TXDRDY_Msk); + obj->uart->INTENSET = (UART_INTENSET_TXDRDY_Msk); break; } NVIC_SetPriority(irq_n, 3); @@ -209,12 +209,12 @@ int all_disabled = 0; switch (irq) { case RxIrq: - obj->uart->INTEN &= ~(UART_INTENCLR_RXDRDY_Msk); - all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_TXDRDY_Msk)) == 0; + obj->uart->INTENCLR = (UART_INTENCLR_RXDRDY_Msk); + all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_TXDRDY_Msk)) == 0; break; case TxIrq: - obj->uart->INTEN &= ~(UART_INTENCLR_TXDRDY_Msk); - all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_RXDRDY_Msk)) == 0; + obj->uart->INTENCLR = (UART_INTENCLR_TXDRDY_Msk); + all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_RXDRDY_Msk)) == 0; break; }