steven niu
implement LPC1768 GPDMA API
Dependents: LPC1768_DMA_implementation
Currently, only LPC1768 HAL level API have been implemented. You can also find the test code to test the m2p and m2m here http://mbed.org/users/steniu01/code/LPC1768_DMA_implementation/. The target is to implement the user side platform agnostic API to make it more easily to use DMA.
There are still quite a few things undone (list in priority order):
1. Implement user side API to provide platform agnostic user friendly API
2. Tidy up the codes and add more comments
3. Create more test cases
4. Fully test the codes using mbed sdk automated test suits
5. Implement LLI
Revision 0:226ca65983a2, committed 2014-08-14
- Comitter:
- steniu01
- Date:
- Thu Aug 14 01:58:45 2014 +0000
- Child:
- 1:86b13bfcbe46
- Commit message:
- first version
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/LPC1768_dma.c Thu Aug 14 01:58:45 2014 +0000
@@ -0,0 +1,146 @@
+#ifdef TARGET_LPC1768
+#include "mbed.h"
+#include "user_LPC17xx.h"
+
+/**
+ * @brief Initializes the DMAy Channelx according to the specified parameters
+ * in the DMA_InitStruct.
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
+ * for DMA1 to select the DMA Channel.
+ * @note Channel 6 and 7 are available only for STM32F072 devices.
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void DMA_init(LPC_GPDMACH_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+
+ /* clear the pending interrupts on the channel to be used by writing to the DMACIntTCClear and DMACIntErrClear register. */
+ if (DMAy_Channelx == LPC_GPDMACH0){
+ /* Reset interrupt pending bits for DMA1 Channel1 */
+ GPDMA->DMACIntTCClear = 1<<0;
+ GPDMA->DMACIntErrClr = 1<<0;
+ }
+ else if (DMAy_Channelx == LPC_GPDMACH1){
+ /* Reset interrupt pending bits for DMA1 Channel2 */
+ GPDMA->DMACIntTCClear = 1<<1;
+ GPDMA->DMACIntErrClr = 1<<1;
+ }
+ else if (DMAy_Channelx == LPC_GPDMACH2){
+ /* Reset interrupt pending bits for DMA1 Channel3 */
+ GPDMA->DMACIntTCClear = 1<<2;
+ GPDMA->DMACIntErrClr = 1<<2;
+ }
+ else if (DMAy_Channelx= LPC_GPDMACH3){
+ /* Reset interrupt pending bits for DMA1 Channel3 */
+ GPDMA->DMACIntTCClear = 1<<3;
+ GPDMA->DMACIntErrClr = 1<<3;
+ }
+ else if (DMAy_Channelx == LPC_GPDMACH4){
+ /* Reset interrupt pending bits for DMA1 Channel4 */
+ GPDMA->DMACIntTCClear = 1<<4;
+ GPDMA->DMACIntErrClr = 1<<4;
+ }
+ else if (DMAy_Channelx == LPC_GPDMACH5){
+ /* Reset interrupt pending bits for DMA1 Channel5 */
+ GPDMA->DMACIntTCClear = 1<<5;
+ GPDMA->DMACIntErrClr = 1<<5;
+ }
+ else if (DMAy_Channelx == LPC_GPDMACH6){
+ /* Reset interrupt pending bits for DMA1 Channel6 */
+ GPDMA->DMACIntTCClear = 1<<6;
+ GPDMA->DMACIntErrClr = 1<<6;
+ }
+ else if (DMAy_Channelx == DMA1_Channel7) {
+ /* Reset interrupt pending bits for DMA1 Channel7 */
+ GPDMA->DMACIntTCClear = 1<<7;
+ GPDMA->DMACIntErrClr = 1<<7;
+ }
+ }
+
+
+ tmpreg = DMAy_Channelx->DMACControl;
+ //tmpreg &= CControl_CLEAR_MASK; //undo
+
+ DMAy_Channelx->DMACCSrcAddr = DMA_InitStruct->DMA_SrcAddr;
+ DMAy_Channelx->DMACCDestAddr = DMA_InitStruct->DMA_DestAddr;
+ DMAy_Channelx->DMACCLLI = DMA_InitStruct->LLI->next;
+ DMAy_Channelx->DMACCControl| = (DMA_InitStruct->DMA_TransSize<<DMA_CCxControl_TransferSize_Pos) |
+ (DMA_InitStruct->DMA_SrcBurst<<DMA_CCxControl_SBSize_Pos) |
+ (DMA_InitStruct->DMA_DestBurst<<DMA_CCxControl_DBSize_Pos) |
+ (DMA_InitStruct->DMA_SrcWidth<<DMA_CCxControl_SWidth_Pos) |
+ (DMA_InitStruct->DMA_DestWidth<<DMA_CCxControl_DWidth_Pos) |
+ (DMA_InitStruct->DMA_SrcInc<<DMA_CCxControl_SI_Pos) |
+ (DMA_InitStruct->DMA_DestInc<<DMA_CCxControl_DI_Pos) |
+ (DMA_InitStruct->DMA_TermInt<<DMA_CCxControl_I_Pos ) ;
+ DMAy_Channelx->DMACCConfig |= (DMA_InitStruct->DMA_SrcPeripheral<<DMA_CCxConfig_SrcPeripheral_Pos)|
+ (DMA_InitStruct->DMA_DMA_DestPeripheral<<DMA_CCxConfig_DestPeripheral_Pos)|
+ (DMA_InitStruct->DMA_TransferType<< DMA_CCxConfig_TransferType_Pos);
+
+ //DMAy_Channelx->DMACCConfig=;
+
+}
+
+/**
+ * @brief Fills each DMA_InitStruct member with its default value.
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+/*-------------- Reset DMA init structure parameters values ------------------*/
+
+ DMA_InitStruct->DMA_DestAddr=0;
+ DMA_InitStruct->DMA_SrcAddr=0;
+ //DMA_InitStruct->LLI;//undo
+ DMA_InitStruct->DMA_TransSize=0;
+ DMA_InitStruct->DMA_SrcBurst=0;
+ DMA_InitStruct->DMA_DestBurst=0;
+ DMA_InitStruct->DMA_SrcWidth=0;
+ DMA_InitStruct->DMA_DestWidth=0;
+ DMA_InitStruct->DMA_SrcInc=0;
+ DMA_InitStruct->DMA_DestInc=0;
+ DMA_InitStruct->DMA_TermInt=0;
+
+ DMA_InitStruct->DMA_SrcPeripheral=0;
+ DMA_InitStruct->DMA_DestPeripheral=0;
+ DMA_InitStruct->DMA_TransferType=0;
+}
+
+
+
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx.
+ * @param DMAy_Channelx: where y can be 1 to select the DMA and
+ * x can be 1 to 7 for DMA1 to select the DMA Channel.
+ * @note Channel 6 and 7 are available only for STM32F072 devices.
+ * @param NewState: new state of the DMAy Channelx.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DMA_Cmd(LPC_GPDMACH_TypeDef* DMAy_Channelx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ //assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ //assert_param(IS_DMA_CONTROL(cmd));
+
+ if (NewState->DMA_Enable != DISABLE)
+ {
+ /* Enable the selected DMAy Channelx */
+ DMAy_Channelx->CConfig |= 1<<DMA_CCxConfig_E_Pos;
+ }
+ else
+ {
+ /* Disable the selected DMAy Channelx */
+ DMAy_Channelx->CConfig &= (uint16_t)(~1<<DMA_CCxConfig_E_Pos);
+ }
+}
+
+
+
+
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/LPC1768_dma.h Thu Aug 14 01:58:45 2014 +0000
@@ -0,0 +1,60 @@
+#ifdef TARGET_LPC1768
+/**
+ * @brief DMA Init structure definition
+ */
+/*DMA channel control register*/
+#define DMA_CCxControl_TransferSize_Pos 0
+#define DMA_CCxControl_SBSize_Pos 12
+#define DMA_CCxControl_DBSize_Pos 15
+#define DMA_CCxControl_SWidth_Pos 18
+#define DMA_CCxControl_DWidth_Pos 21
+#define DMA_CCxControl_SI_Pos 26
+#define DMA_CCxControl_DI_Pos 27
+#define DMA_CCxControl_I_Pos 31
+
+/*DMA Channel config register*/
+#define DMA_CCxConfig_E_Pos 0
+#define DMA_CCxConfig_SrcPeripheral_Pos 1
+#define DMA_CCxConfig_DestPeripheral_Pos 6
+#define DMA_CCxConfig_TransferType_Pos 11
+#define DMA_CCxConfig_IE_Pos 14
+#define DMA_CCxConfig_ITC_Pos 15
+#define DMA_CCxConfig_L_Pos 16
+#define DMA_CCxConfig_A_Pos 17
+#define DMA_CCxConfig_H_Pos 18
+
+
+
+
+typedef struct
+{
+ uint32_t DMA_DestAddr; /*!< Specifies the destination base address for DMAy Channelx. */
+ uint32_t DMA_SrcAddr; /*!< Specifies the source base address for DMAy Channelx. */
+ DMA_LLI LLI; /*!< Specifies the next linked item */
+ uint32_t DMA_TransSize;/*!< Specifies the source transfer size */
+ uint32_t DMA_SrcBurst; /*!< Specifies the source burst size */
+ uint32_t DMA_DestBurst; /*!< Specifies the destination burst size */
+ uint32_t DMA_SrcWidth; /*!< Specifies the source transfer width */
+ uint32_t DMA_DestWidth; /*!< Specifies the destination transfer width */
+ uint32_t DMA_SrcInc; /*!< Specifies whether the source is incremented or not */
+ uint32_t DMA_DestInc; /*!< Specifies whether the destination is incremented or not */
+ uint32_t DMA_TermInt; /*!< Specifies whether the terminal count interrupt enabled or not */
+
+ /*!< Specifies the features set by channel config register */
+ uint32_t DMA_SrcPeripheral;
+ uint32_t DMA_DestPeripheral;
+ uint32_t DMA_TransferType;
+
+}DMA_InitTypeDef;
+
+typedef struct
+{
+ uint32_t DestAddr;
+ uint32_t SrcAddr;
+ uint32_t next;
+ uint32_t control;
+
+}DMA_LLI;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/user_LPC17xx.h Thu Aug 14 01:58:45 2014 +0000
@@ -0,0 +1,122 @@
+
+/** @defgroup DMA_Exported_Constants
+ * @{
+ */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+ ((PERIPH) == DMA1_Channel2) || \
+ ((PERIPH) == DMA1_Channel3) || \
+ ((PERIPH) == DMA1_Channel4) || \
+ ((PERIPH) == DMA1_Channel5) || \
+ ((PERIPH) == DMA1_Channel6) || \
+ ((PERIPH) == DMA1_Channel7) || \
+ ((PERIPH) == DMA2_Channel1) || \
+ ((PERIPH) == DMA2_Channel2) || \
+ ((PERIPH) == DMA2_Channel3) || \
+ ((PERIPH) == DMA2_Channel4) || \
+ ((PERIPH) == DMA2_Channel5))
+
+/** @defgroup DMA_data_transfer_direction
+ * @{
+ */
+
+#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
+ ((DIR) == DMA_DIR_PeripheralSRC))
+/**
+ * @}
+ */
+
+
+
+/** @defgroup DMA_peripheral_incremented_mode
+ * @{
+ */
+
+#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
+ ((STATE) == DMA_PeripheralInc_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_incremented_mode
+ * @{
+ */
+
+#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
+ ((STATE) == DMA_MemoryInc_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_peripheral_data_size
+ * @{
+ */
+
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+ ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_data_size
+ * @{
+ */
+
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+ ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_circular_normal_mode
+ * @{
+ */
+
+#define DMA_Mode_Circular ((uint32_t)0x00000020)
+#define DMA_Mode_Normal ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_priority_level
+ * @{
+ */
+
+#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
+#define DMA_Priority_High ((uint32_t)0x00002000)
+#define DMA_Priority_Medium ((uint32_t)0x00001000)
+#define DMA_Priority_Low ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+ ((PRIORITY) == DMA_Priority_High) || \
+ ((PRIORITY) == DMA_Priority_Medium) || \
+ ((PRIORITY) == DMA_Priority_Low))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_to_memory
+ * @{
+ */
+
+#define DMA_M2M_Enable ((uint32_t)0x00004000)
+#define DMA_M2M_Disable ((uint32_t)0x00000000)
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
+
+/**
+ * @}
+ */