Revision 6:7b5e59c0e71c, committed 2010-08-22

Comitter:

romilly

Date:

Sun Aug 22 12:41:26 2010 +0000

Parent:

5:cb3c24f94370

Child:

7:53498e24592c

Commit message:

Changed in this revision

--- a/MCP23S17.cpp	Sun Aug 22 12:16:27 2010 +0000
+++ b/MCP23S17.cpp	Sun Aug 22 12:41:26 2010 +0000
@@ -62,4 +62,3 @@
 char MCP23S17::inputB() {
     return _read(GPIOB);
 }
-

--- a/MCP23S17.h	Sun Aug 22 12:16:27 2010 +0000
+++ b/MCP23S17.h	Sun Aug 22 12:41:26 2010 +0000
@@ -46,4 +46,100 @@
     char _writeOpcode;
 };
 
+#endif/* MCP23S17 - drive the Microchip MCP23S17 16-bit Port Extender using SPI
+* Copyright (c) 2010 Romilly Cocking
+* Released under the MIT License: http://mbed.org/license/mit
+*
+* version 0.1
+*/
+#include "mbed.h"
+
+#ifndef  SER23K256_H
+#define  SER23K256_H
+
+// all register addresses assume IOCON.BANK = 0 (POR default)
+
+#define IODIRA   0x00
+#define IODIRB   0x01
+#define GPINTENA 0x04
+#define IOCON    0x0A
+#define GPIOA    0x12
+#define GPIOB    0x13
+#define OLATA    0x14
+#define OLATB    0x15
+
+// Control settings
+
+#define IOCON_BANK  0x80 // Banked registers
+#define IOCON_BYTE_MODE 0x20 // Disables sequential operation. If bank = 0, operations toggle between A and B registers
+#define IOCON_HAEN  0x08 // Hardware address enable
+
+class MCP23S17 {
+public:
+    MCP23S17(SPI& spi, PinName ncs, char writeOpcode);
+    void directionA(char direction);
+    void directionB(char direction);
+    void gpIntEnA(char interruptsEnabledMask);
+    char inputA();
+    char inputB();
+    void outputA(char byte);
+    void outputB(char byte);
+protected:
+    SPI& _spi;
+    DigitalOut _ncs;
+    void _init();
+    void _write(char address, char data);
+    char _read(char address);
+    char _readOpcode;
+    char _writeOpcode;
+};
+
+#endif/* MCP23S17 - drive the Microchip MCP23S17 16-bit Port Extender using SPI
+* Copyright (c) 2010 Romilly Cocking
+* Released under the MIT License: http://mbed.org/license/mit
+*
+* version 0.1
+*/
+#include "mbed.h"
+
+#ifndef  SER23K256_H
+#define  SER23K256_H
+
+// all register addresses assume IOCON.BANK = 0 (POR default)
+
+#define IODIRA   0x00
+#define IODIRB   0x01
+#define GPINTENA 0x04
+#define IOCON    0x0A
+#define GPIOA    0x12
+#define GPIOB    0x13
+#define OLATA    0x14
+#define OLATB    0x15
+
+// Control settings
+
+#define IOCON_BANK  0x80 // Banked registers
+#define IOCON_BYTE_MODE 0x20 // Disables sequential operation. If bank = 0, operations toggle between A and B registers
+#define IOCON_HAEN  0x08 // Hardware address enable
+
+class MCP23S17 {
+public:
+    MCP23S17(SPI& spi, PinName ncs, char writeOpcode);
+    void directionA(char direction);
+    void directionB(char direction);
+    void gpIntEnA(char interruptsEnabledMask);
+    char inputA();
+    char inputB();
+    void outputA(char byte);
+    void outputB(char byte);
+protected:
+    SPI& _spi;
+    DigitalOut _ncs;
+    void _init();
+    void _write(char address, char data);
+    char _read(char address);
+    char _readOpcode;
+    char _writeOpcode;
+};
+
 #endif
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