copy_of_ethernet_api.h

00001 //Copy from mbed HAL
00002 //https://github.com/mbedmicro/mbed/blob/master/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC408X/ethernet_api.c
00003 
00004 #include <string.h>
00005 
00006 #include "ethernet_api.h"
00007 #include "cmsis.h"
00008 #include "mbed_interface.h"
00009 #include "toolchain.h"
00010 //#include "error.h"
00011 
00012 #define NUM_RX_FRAG         3           /* Num.of RX Fragments. */
00013 #define NUM_TX_FRAG         16           /* Num.of TX Fragments. */
00014 #define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */
00015 
00016 #define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
00017 
00018 #define ETHERNET_ADDR_SIZE 6
00019 
00020 PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */
00021    unsigned int Packet;
00022    unsigned int Ctrl;
00023 };
00024 typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
00025 
00026 PACKED struct RX_STAT_TypeDef { /* RX Status struct */
00027    unsigned int Info;
00028    unsigned int HashCRC;
00029 };
00030 typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
00031 
00032 PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */
00033    unsigned int Packet;
00034    unsigned int Ctrl;
00035 };
00036 typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
00037 
00038 PACKED struct TX_STAT_TypeDef { /* TX Status struct */
00039    unsigned int Info;
00040 };
00041 typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
00042 
00043 /* MAC Configuration Register 1 */
00044 #define MAC1_REC_EN 0x00000001 /* Receive Enable */
00045 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
00046 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
00047 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
00048 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
00049 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
00050 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
00051 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
00052 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
00053 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
00054 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
00055 
00056 /* MAC Configuration Register 2 */
00057 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
00058 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
00059 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
00060 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
00061 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
00062 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
00063 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
00064 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
00065 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
00066 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
00067 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
00068 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
00069 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
00070 
00071 /* Back-to-Back Inter-Packet-Gap Register */
00072 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
00073 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
00074 
00075 /* Non Back-to-Back Inter-Packet-Gap Register */
00076 #define IPGR_DEF 0x00000012 /* Recommended value */
00077 
00078 /* Collision Window/Retry Register */
00079 #define CLRT_DEF 0x0000370F /* Default value */
00080 
00081 /* PHY Support Register */
00082 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
00083 //#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
00084 #define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */
00085 
00086 /* Test Register */
00087 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
00088 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */
00089 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
00090 
00091 /* MII Management Configuration Register */
00092 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
00093 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
00094 #define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */
00095 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
00096 
00097 /* MII Management Command Register */
00098 #define MCMD_READ 0x00000001 /* MII Read */
00099 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
00100 
00101 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
00102 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
00103 
00104 /* MII Management Address Register */
00105 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
00106 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
00107 
00108 /* MII Management Indicators Register */
00109 #define MIND_BUSY 0x00000001 /* MII is Busy */
00110 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
00111 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
00112 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
00113 
00114 /* Command Register */
00115 #define CR_RX_EN 0x00000001 /* Enable Receive */
00116 #define CR_TX_EN 0x00000002 /* Enable Transmit */
00117 #define CR_REG_RES 0x00000008 /* Reset Host Registers */
00118 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
00119 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
00120 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
00121 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
00122 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
00123 #define CR_RMII 0x00000200 /* Reduced MII Interface */
00124 #define CR_FULL_DUP 0x00000400 /* Full Duplex */
00125 
00126 /* Status Register */
00127 #define SR_RX_EN 0x00000001 /* Enable Receive */
00128 #define SR_TX_EN 0x00000002 /* Enable Transmit */
00129 
00130 /* Transmit Status Vector 0 Register */
00131 #define TSV0_CRC_ERR 0x00000001 /* CRC error */
00132 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
00133 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
00134 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
00135 #define TSV0_MCAST 0x00000010 /* Multicast Destination */
00136 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
00137 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
00138 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
00139 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
00140 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
00141 #define TSV0_GIANT 0x00000400 /* Giant Frame */
00142 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
00143 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
00144 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
00145 #define TSV0_PAUSE 0x20000000 /* Pause Frame */
00146 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
00147 #define TSV0_VLAN 0x80000000 /* VLAN Frame */
00148 
00149 /* Transmit Status Vector 1 Register */
00150 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
00151 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
00152 
00153 /* Receive Status Vector Register */
00154 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
00155 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
00156 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
00157 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
00158 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
00159 #define RSV_CRC_ERR 0x00100000 /* CRC Error */
00160 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
00161 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
00162 #define RSV_REC_OK 0x00800000 /* Frame Received OK */
00163 #define RSV_MCAST 0x01000000 /* Multicast Frame */
00164 #define RSV_BCAST 0x02000000 /* Broadcast Frame */
00165 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
00166 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
00167 #define RSV_PAUSE 0x10000000 /* Pause Frame */
00168 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
00169 #define RSV_VLAN 0x40000000 /* VLAN Frame */
00170 
00171 /* Flow Control Counter Register */
00172 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
00173 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
00174 
00175 /* Flow Control Status Register */
00176 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
00177 
00178 /* Receive Filter Control Register */
00179 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
00180 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
00181 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
00182 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
00183 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
00184 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
00185 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
00186 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
00187 
00188 /* Receive Filter WoL Status/Clear Registers */
00189 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
00190 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
00191 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
00192 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
00193 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
00194 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
00195 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
00196 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
00197 
00198 /* Interrupt Status/Enable/Clear/Set Registers */
00199 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
00200 #define INT_RX_ERR 0x00000002 /* Receive Error */
00201 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
00202 #define INT_RX_DONE 0x00000008 /* Receive Done */
00203 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
00204 #define INT_TX_ERR 0x00000020 /* Transmit Error */
00205 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
00206 #define INT_TX_DONE 0x00000080 /* Transmit Done */
00207 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
00208 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
00209 
00210 /* Power Down Register */
00211 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
00212 
00213 /* RX Descriptor Control Word */
00214 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */
00215 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
00216 
00217 /* RX Status Hash CRC Word */
00218 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
00219 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
00220 
00221 /* RX Status Information Word */
00222 #define RINFO_SIZE 0x000007FF /* Data size in bytes */
00223 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
00224 #define RINFO_VLAN 0x00080000 /* VLAN Frame */
00225 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
00226 #define RINFO_MCAST 0x00200000 /* Multicast Frame */
00227 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */
00228 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
00229 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
00230 #define RINFO_LEN_ERR 0x02000000 /* Length Error */
00231 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
00232 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
00233 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
00234 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
00235 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
00236 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
00237 
00238 //#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
00239 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
00240 
00241 
00242 /* TX Descriptor Control Word */
00243 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
00244 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
00245 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
00246 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
00247 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
00248 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
00249 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
00250 
00251 /* TX Status Information Word */
00252 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */
00253 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
00254 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
00255 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
00256 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
00257 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
00258 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
00259 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
00260 
00261 /* ENET Device Revision ID */
00262 #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
00263 
00264 /* DP83848C PHY Registers */
00265 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
00266 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
00267 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
00268 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
00269 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
00270 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
00271 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
00272 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
00273 
00274 /* PHY Extended Registers */
00275 #define PHY_REG_STS 0x10 /* Status Register */
00276 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
00277 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
00278 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
00279 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
00280 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
00281 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
00282 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
00283 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
00284 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
00285 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
00286 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
00287 
00288 #define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */
00289 
00290 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
00291 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
00292 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
00293 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
00294 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
00295 
00296 #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
00297 #define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */
00298 
00299 #define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */
00300 
00301 #define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */
00302 #define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */
00303 #define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */
00304 
00305 #define PHY_BMCR_RESET 0x8000 /* PHY Reset */
00306 
00307 #define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */
00308 
00309 #define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */
00310 #define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */