EthDev_LPC17xx.h

00001 /*
00002  * @file:    EthDev_LPC17xx.h
00003  * @purpose: Ethernet Device Definitions for NXP LPC17xx
00004  * @version: V0.01
00005  * @date:    14. May 2009
00006  *----------------------------------------------------------------------------
00007  *
00008  * Copyright (C) 2009 ARM Limited. All rights reserved.
00009  *
00010  * ARM Limited (ARM) is supplying this software for use with Cortex-M3
00011  * processor based microcontrollers.  This file can be freely distributed
00012  * within development tools that are supporting such ARM based processors.
00013  *
00014  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
00015  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
00016  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
00017  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
00018  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
00019  *
00020  */
00021 /*
00022  *  Modified by Kenji Arai August 29th, 2010 for XpressoLPC1768 LAN
00023  *
00024  *  Changed LPC17xx.h then convert all "EMAC" to "LPC_EMAC"
00025  *
00026  *      September 5th, 2010
00027  */
00028 /*
00029  * Modified for MiMic by R.Iizuka. 2011.08.27
00030  * http://nyatla.jp/mimic
00031  */
00032 #ifndef __ETHDEV_LPC17XX_H
00033 #define __ETHDEV_LPC17XX_H
00034 
00035 #include <stdint.h>
00036 #include "NyLPC_stdlib.h"
00037 #include "../NyLPC_IEthernetDevice.h"
00038 
00039 #ifdef __cplusplus
00040 extern "C" {
00041 #endif /* __cplusplus */
00042 
00043 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
00044 #define NUM_RX_FRAG         3           /* Num.of RX Fragments. */
00045 #define NUM_TX_FRAG         16           /* Num.of TX Fragments. */
00046 #define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */
00047 
00048 #define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
00049 
00050 typedef struct {                        /* RX Descriptor struct              */
00051    uint32_t Packet;
00052    uint32_t Ctrl;
00053 } RX_DESC_TypeDef;
00054 
00055 typedef struct {                        /* RX Status struct                  */
00056    uint32_t Info;
00057    uint32_t HashCRC;
00058 } RX_STAT_TypeDef;
00059 
00060 typedef struct {                        /* TX Descriptor struct              */
00061    uint32_t Packet;
00062    uint32_t Ctrl;
00063 } TX_DESC_TypeDef;
00064 
00065 typedef struct {                        /* TX Status struct                  */
00066    uint32_t Info;
00067 } TX_STAT_TypeDef;
00068 
00069 
00070 /* EMAC variables located in AHB SRAM bank 1*/
00071 #define AHB_SRAM_BANK1_BASE  0x2007c000UL
00072 #define RX_DESC_BASE        (AHB_SRAM_BANK1_BASE         )
00073 #define RX_STAT_BASE        (RX_DESC_BASE + NUM_RX_FRAG*(2*4))     /* 2 * uint32_t, see RX_DESC_TypeDef */
00074 #define TX_DESC_BASE        (RX_STAT_BASE + NUM_RX_FRAG*(2*4))     /* 2 * uint32_t, see RX_STAT_TypeDef */
00075 #define TX_STAT_BASE        (TX_DESC_BASE + NUM_TX_FRAG*(2*4))     /* 2 * uint32_t, see TX_DESC_TypeDef */
00076 #define ETH_BUF_BASE        (TX_STAT_BASE + NUM_TX_FRAG*(1*4))     /* 1 * uint32_t, see TX_STAT_TypeDef */
00077 
00078 /**
00079  * 消費メモリ量は、
00080  * descriptor = NUM_RX_FRAG*16+NUM_TX_FRAG*12.
00081  * EthnetBuf=ETH_FRAG_SIZE*NUM_RX_FRAG
00082  */
00083 
00084 /* RX and TX descriptor and status definitions. */
00085 #define RX_DESC_PACKET(i)   (*(unsigned int *)(RX_DESC_BASE   + 8*i))
00086 #define RX_DESC_CTRL(i)     (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
00087 #define RX_STAT_INFO(i)     (*(unsigned int *)(RX_STAT_BASE   + 8*i))
00088 #define RX_STAT_HASHCRC(i)  (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
00089 #define TX_DESC_PACKET(i)   (*(unsigned int *)(TX_DESC_BASE   + 8*i))
00090 #define TX_DESC_CTRL(i)     (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
00091 #define TX_STAT_INFO(i)     (*(unsigned int *)(TX_STAT_BASE   + 4*i))
00092 #define ETH_BUF(i)          ( ETH_BUF_BASE + ETH_FRAG_SIZE*i )
00093 #define ETH_NUM_BUFFERS     ( NUM_TX_FRAG + NUM_RX_FRAG + 1 ) /* There are in fact 2 more buffers than descriptors as the two Tx descriptors use the same buffer to speed up the uip Tx. */
00094 
00095 
00096 /* MAC Configuration Register 1 */
00097 #define MAC1_REC_EN         0x00000001  /* Receive Enable                    */
00098 #define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */
00099 #define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */
00100 #define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */
00101 #define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */
00102 #define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */
00103 #define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */
00104 #define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */
00105 #define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */
00106 #define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */
00107 #define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */
00108 
00109 /* MAC Configuration Register 2 */
00110 #define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */
00111 #define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */
00112 #define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */
00113 #define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */
00114 #define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */
00115 #define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */
00116 #define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */
00117 #define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */
00118 #define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */
00119 #define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */
00120 #define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */
00121 #define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */
00122 #define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */
00123 
00124 /* Back-to-Back Inter-Packet-Gap Register */
00125 #define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */
00126 #define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */
00127 
00128 /* Non Back-to-Back Inter-Packet-Gap Register */
00129 #define IPGR_DEF            0x00000012  /* Recommended value                 */
00130 
00131 /* Collision Window/Retry Register */
00132 #define CLRT_DEF            0x0000370F  /* Default value                     */
00133 
00134 /* PHY Support Register */
00135 #define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */
00136 #define SUPP_RES_RMII       0x00000800  /* Reset Reduced MII Logic           */
00137 
00138 /* Test Register */
00139 #define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */
00140 #define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */
00141 #define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */
00142 
00143 /* MII Management Configuration Register */
00144 #define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */
00145 #define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */
00146 #define MCFG_CLK_SEL        0x0000003C  /* Clock Select Mask                 */
00147 #define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */
00148 
00149 #define MCFG_CLK_DIV4       0x00000000  /* MDC = hclk / 4                    */
00150 #define MCFG_CLK_DIV6       0x00000008  /* MDC = hclk / 6                    */
00151 #define MCFG_CLK_DIV8       0x0000000C  /* MDC = hclk / 8                    */
00152 #define MCFG_CLK_DIV10      0x00000010  /* MDC = hclk / 10                   */
00153 #define MCFG_CLK_DIV14      0x00000014  /* MDC = hclk / 14                   */
00154 #define MCFG_CLK_DIV20      0x00000018  /* MDC = hclk / 20                   */
00155 #define MCFG_CLK_DIV28      0x0000001C  /* MDC = hclk / 28                   */
00156 
00157 /* MII Management Command Register */
00158 #define MCMD_READ           0x00000001  /* MII Read                          */
00159 #define MCMD_SCAN           0x00000002  /* MII Scan continuously             */
00160 
00161 #define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */
00162 #define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */
00163 
00164 /* MII Management Address Register */
00165 #define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */
00166 #define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */
00167 
00168 /* MII Management Indicators Register */
00169 #define MIND_BUSY           0x00000001  /* MII is Busy                       */
00170 #define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */
00171 #define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */
00172 #define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */
00173 
00174 /* Command Register */
00175 #define CR_RX_EN            0x00000001  /* Enable Receive                    */
00176 #define CR_TX_EN            0x00000002  /* Enable Transmit                   */
00177 #define CR_REG_RES          0x00000008  /* Reset Host Registers              */
00178 #define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */
00179 #define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */
00180 #define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */
00181 #define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */
00182 #define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */
00183 #define CR_RMII             0x00000200  /* Reduced MII Interface             */
00184 #define CR_FULL_DUP         0x00000400  /* Full Duplex                       */
00185 
00186 /* Status Register */
00187 #define SR_RX_EN            0x00000001  /* Enable Receive                    */
00188 #define SR_TX_EN            0x00000002  /* Enable Transmit                   */
00189 
00190 /* Transmit Status Vector 0 Register */
00191 #define TSV0_CRC_ERR        0x00000001  /* CRC error                         */
00192 #define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */
00193 #define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */
00194 #define TSV0_DONE           0x00000008  /* Tramsmission Completed            */
00195 #define TSV0_MCAST          0x00000010  /* Multicast Destination             */
00196 #define TSV0_BCAST          0x00000020  /* Broadcast Destination             */
00197 #define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */
00198 #define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */
00199 #define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */
00200 #define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */
00201 #define TSV0_GIANT          0x00000400  /* Giant Frame                       */
00202 #define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */
00203 #define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */
00204 #define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */
00205 #define TSV0_PAUSE          0x20000000  /* Pause Frame                       */
00206 #define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */
00207 #define TSV0_VLAN           0x80000000  /* VLAN Frame                        */
00208 
00209 /* Transmit Status Vector 1 Register */
00210 #define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */
00211 #define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */
00212 
00213 /* Receive Status Vector Register */
00214 #define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */
00215 #define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */
00216 #define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */
00217 #define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */
00218 #define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */
00219 #define RSV_CRC_ERR         0x00100000  /* CRC Error                         */
00220 #define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */
00221 #define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */
00222 #define RSV_REC_OK          0x00800000  /* Frame Received OK                 */
00223 #define RSV_MCAST           0x01000000  /* Multicast Frame                   */
00224 #define RSV_BCAST           0x02000000  /* Broadcast Frame                   */
00225 #define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */
00226 #define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */
00227 #define RSV_PAUSE           0x10000000  /* Pause Frame                       */
00228 #define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */
00229 #define RSV_VLAN            0x40000000  /* VLAN Frame                        */
00230 
00231 /* Flow Control Counter Register */
00232 #define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */
00233 #define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */
00234 
00235 /* Flow Control Status Register */
00236 #define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */
00237 
00238 /* Receive Filter Control Register */
00239 #define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */
00240 #define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */
00241 #define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */
00242 #define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */
00243 #define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/
00244 #define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */
00245 #define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */
00246 #define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */
00247 
00248 /* Receive Filter WoL Status/Clear Registers */
00249 #define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */
00250 #define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */
00251 #define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */
00252 #define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */
00253 #define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */
00254 #define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */
00255 #define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */
00256 #define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */
00257 
00258 /* Interrupt Status/Enable/Clear/Set Registers */
00259 #define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */
00260 #define INT_RX_ERR          0x00000002  /* Receive Error                     */
00261 #define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */
00262 #define INT_RX_DONE         0x00000008  /* Receive Done                      */
00263 #define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */
00264 #define INT_TX_ERR          0x00000020  /* Transmit Error                    */
00265 #define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */
00266 #define INT_TX_DONE         0x00000080  /* Transmit Done                     */
00267 #define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */
00268 #define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */
00269 
00270 /* Power Down Register */
00271 #define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */
00272 
00273 /* RX Descriptor Control Word */
00274 #define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */
00275 #define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */
00276 
00277 /* RX Status Hash CRC Word */
00278 #define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */
00279 #define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */
00280 
00281 /* RX Status Information Word */
00282 #define RINFO_SIZE          0x000007FF  /* Data size in bytes                */
00283 #define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */
00284 #define RINFO_VLAN          0x00080000  /* VLAN Frame                        */
00285 #define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */
00286 #define RINFO_MCAST         0x00200000  /* Multicast Frame                   */
00287 #define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */
00288 #define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */
00289 #define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */
00290 #define RINFO_LEN_ERR       0x02000000  /* Length Error                      */
00291 #define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */
00292 #define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */
00293 #define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */
00294 #define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */
00295 #define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */
00296 #define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
00297 
00298 #define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | \
00299                             RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
00300 
00301 /* TX Descriptor Control Word */
00302 #define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */
00303 #define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */
00304 #define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */
00305 #define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */
00306 #define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */
00307 #define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */
00308 #define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */
00309 
00310 /* TX Status Information Word */
00311 #define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */
00312 #define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */
00313 #define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */
00314 #define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */
00315 #define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */
00316 #define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */
00317 #define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */
00318 #define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
00319 
00320 
00321 
00322 void EthDev_LPC17xx_processTx(void);
00323 void EthDev_LPC17xx_sendTxEthFrame(void* i_buf,unsigned short i_size);
00324 void* EthDev_LPC17xx_getRxEthFrame(unsigned short* o_len_of_data);
00325 void EthDev_LPC17xx_nextRxEthFrame(void);
00326 
00327 void EthDev_LPC17xx_prevTxDescriptor(void);
00328 void EthDev_LPC17xx_prevRxDescriptor(void);
00329 NyLPC_TBool EthDev_LPC17xx_prvWritePHY( long lPhyReg, long lValue );
00330 unsigned short EthDev_LPC17xx_prvReadPHY( unsigned int ucPhyReg, NyLPC_TBool* plStatus );
00331 
00332 
00333 
00334 #ifdef __cplusplus
00335 }
00336 #endif /* __cplusplus */
00337 
00338 #endif
00339 /*----------------------------------------------------------------------------
00340  * end of file
00341  *---------------------------------------------------------------------------*/