Revision 0:f3f80a0695ff, committed 2012-02-17

Comitter:

mio

Date:

Fri Feb 17 13:07:18 2012 +0000

Child:

1:509676f3be32

Commit message:

OV7670+FIFO Cam with SPI QVGA LCD OUTPUT TEST

Changed in this revision

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp	Fri Feb 17 13:07:18 2012 +0000
@@ -0,0 +1,69 @@
+//
+// OV7670 + FIFO AL422B camera board test
+//
+#include "mbed.h"
+#include "spilcd_qvga.h"
+#include "ov7670.h"
+#include <stdlib.h>
+
+//
+// SPILCD LG 
+//
+SPILCD_QVGA lcd(p29, p30, p5, p6, p7) ;
+OV7670 camera(
+    p28,p27,       // SDA,SCL(I2C / SCCB)
+    p21,p22,p20,   // VSYNC,HREF,WEN(FIFO)
+    //p18,p17,p16,p15,p11,p12,p14,p13, // D7-D0
+    Port0,0x07878000,
+    p23,p24,p25) ; // RRST,OE,RCLK
+
+Serial pc(USBTX,USBRX) ;
+Timer t;
+
+#ifdef QQVGA
+# define SIZEX (160)
+# define SIZEY (120)
+#else
+# define SIZEX (320)
+# define SIZEY (240)
+#endif
+
+int main() {
+    int last ;
+    pc.baud(115200) ;
+    camera.Reset() ;
+
+#ifdef QQVGA
+    camera.InitQQVGA565() ;
+#else
+    camera.InitQVGA565() ;
+#endif
+
+    // CAPTURE and SEND LOOP
+    t.start();
+    last = t.read_ms() ;
+    while(1)
+    {
+        camera.CaptureNext() ;
+        while(camera.CaptureDone() == false) ;
+        printf("Caputure %d(ms)\r\n", t.read_ms() - last) ;
+        last = t.read_ms() ;
+        camera.ReadStart() ;
+        lcd.Lcd_SetCursor(0,0);
+        lcd.Lcd_WR_Start();
+        lcd.rsout(1) ;
+        for (int y = 0;y < SIZEY;y++) {
+            lcd.Lcd_SetCursor(y,0);
+            lcd.Lcd_WR_Start();
+            for (int x = 0;x < SIZEX;x++) {
+                lcd.csout(0) ;
+                lcd.DataToWrite(camera.ReadOneWord());
+                lcd.csout(1) ;
+            }
+        }
+        camera.ReadStop() ; 
+        lcd.rsout(0) ;
+        printf("FIFO Read & Lcd Out %d(ms)\r\n", t.read_ms() - last) ;
+        last = t.read_ms() ;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed.bld	Fri Feb 17 13:07:18 2012 +0000
@@ -0,0 +1,1 @@
+http://mbed.org/users/mbed_official/code/mbed/builds/14f4805c468c

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ov7670.h	Fri Feb 17 13:07:18 2012 +0000
@@ -0,0 +1,288 @@
+#include "mbed.h"
+#include "ov7670reg.h"
+
+#define OV7670_WRITE (0x42)
+#define OV7670_READ  (0x43)
+#define OV7670_WRITEWAIT (20)
+#define OV7670_NOACK (0)
+#define OV7670_REGMAX (201)
+#define OV7670_I2CFREQ (50000)
+
+//
+// OV7670 + FIFO AL422B camera board test
+//
+class OV7670 : public Base
+{
+public:
+    I2C camera ;
+    InterruptIn vsync,href;
+    DigitalOut wen ;
+    PortIn data ;
+    DigitalOut rrst,oe,rclk ;
+    volatile int LineCounter ;
+    volatile int LastLines ;
+    volatile bool CaptureReq ;
+    volatile bool Busy ;
+    volatile bool Done ;
+
+    OV7670(
+        PinName sda,// Camera I2C port
+        PinName scl,// Camera I2C port
+        PinName vs, // VSYNC
+        PinName hr, // HREF
+        PinName we, // WEN
+        PortName port, // 8bit bus port
+        int mask, // 0b0000_0M65_4000_0321_L000_0000_0000_0000 = 0x07878000
+        PinName rt, // /RRST
+        PinName o,  // /OE
+        PinName rc  // RCLK      
+        ) : camera(sda,scl),vsync(vs),href(hr),wen(we),data(port,mask),rrst(rt),oe(o),rclk(rc)
+    {
+        camera.stop() ;
+        camera.frequency(OV7670_I2CFREQ) ;
+        vsync.fall(this,&OV7670::VsyncHandler) ;
+        href.rise(this,&OV7670::HrefHandler) ;
+        CaptureReq = false ;
+        Busy = false ;
+        Done = false ;
+        LineCounter = 0 ;
+        rrst = 1 ;
+        oe = 1 ;
+        rclk = 1 ;
+        wen = 0 ;
+    }
+
+    // capture request
+    void CaptureNext(void)
+    {
+        CaptureReq = true ;
+        Busy = true ;
+    }
+    
+    // capture done? (with clear)
+    bool CaptureDone(void)
+    {
+        bool result ;
+        if (Busy) {
+            result = false ;
+        } else {
+            result = Done ;
+            Done = false ;
+        }
+        return result ;
+    }
+
+    // write to camera
+    void WriteReg(int addr,int data)
+    {
+        // WRITE 0x42,ADDR,DATA
+        camera.start() ;
+        camera.write(OV7670_WRITE) ;
+        wait_us(OV7670_WRITEWAIT);
+        camera.write(addr) ;
+        wait_us(OV7670_WRITEWAIT);
+        camera.write(data) ;
+        camera.stop() ;
+    }
+
+    // read from camera
+    int ReadReg(int addr)
+    {
+        int data ;
+
+        // WRITE 0x42,ADDR
+        camera.start() ;
+        camera.write(OV7670_WRITE) ;
+        wait_us(OV7670_WRITEWAIT);
+        camera.write(addr) ;
+        camera.stop() ;
+        wait_us(OV7670_WRITEWAIT);    
+
+        // WRITE 0x43,READ
+        camera.start() ;
+        camera.write(OV7670_READ) ;
+        wait_us(OV7670_WRITEWAIT);
+        data = camera.read(OV7670_NOACK) ;
+        camera.stop() ;
+    
+        return data ;
+    }
+
+    void Reset(void) {    
+        WriteReg(0x12,0x80) ; // RESET CAMERA
+        wait_ms(200) ;
+    }
+    
+    void InitQQVGA565() {
+        // QQVGA RGB565
+        WriteReg(REG_CLKRC,0x80);
+        WriteReg(REG_COM11,0x0A) ;
+        WriteReg(REG_TSLB,0x04);
+        WriteReg(REG_COM7,0x04) ;
+        WriteReg(REG_RGB444, 0x00);
+        WriteReg(REG_COM15, 0xd0);
+        WriteReg(REG_HSTART,0x16) ;
+        WriteReg(REG_HSTOP,0x04) ;
+        WriteReg(REG_HREF,0x24) ;
+        WriteReg(REG_VSTART,0x02) ;
+        WriteReg(REG_VSTOP,0x7a) ;
+        WriteReg(REG_VREF,0x0a) ;
+        WriteReg(REG_COM10,0x02) ;
+        WriteReg(REG_COM3, 0x04);
+        WriteReg(REG_COM14, 0x1a);
+        WriteReg(0x72, 0x22);
+        WriteReg(0x73, 0xf2);
+
+        // COLOR SETTING
+        WriteReg(0x4f,0x80);
+        WriteReg(0x50,0x80);
+        WriteReg(0x51,0x00);
+        WriteReg(0x52,0x22);
+        WriteReg(0x53,0x5e);
+        WriteReg(0x54,0x80);
+        WriteReg(0x56,0x40);
+        WriteReg(0x58,0x9e);
+        WriteReg(0x59,0x88);
+        WriteReg(0x5a,0x88);
+        WriteReg(0x5b,0x44);
+        WriteReg(0x5c,0x67);
+        WriteReg(0x5d,0x49);
+        WriteReg(0x5e,0x0e);
+        WriteReg(0x69,0x00);
+        WriteReg(0x6a,0x40);
+        WriteReg(0x6b,0x0a);
+        WriteReg(0x6c,0x0a);
+        WriteReg(0x6d,0x55);
+        WriteReg(0x6e,0x11);
+        WriteReg(0x6f,0x9f);
+
+        WriteReg(0xb0,0x84);
+    }    
+
+    void InitQVGA565() {
+        // QVGA RGB565
+        WriteReg(REG_CLKRC,0x80);
+        WriteReg(REG_COM11,0x0A) ;
+        WriteReg(REG_TSLB,0x04);
+        WriteReg(REG_COM7,0x04) ;
+        WriteReg(REG_RGB444, 0x00);
+        WriteReg(REG_COM15, 0xd0);
+        WriteReg(REG_HSTART,0x16) ;
+        WriteReg(REG_HSTOP,0x04) ;
+        WriteReg(REG_HREF,0x80) ;
+        WriteReg(REG_VSTART,0x02) ;
+        WriteReg(REG_VSTOP,0x7a) ;
+        WriteReg(REG_VREF,0x0a) ;
+        WriteReg(REG_COM10,0x02) ;
+        WriteReg(REG_COM3, 0x04);
+        WriteReg(REG_COM14, 0x19);
+        WriteReg(0x72, 0x11);
+        WriteReg(0x73, 0xf1);
+
+        // COLOR SETTING
+        WriteReg(0x4f,0x80);
+        WriteReg(0x50,0x80);
+        WriteReg(0x51,0x00);
+        WriteReg(0x52,0x22);
+        WriteReg(0x53,0x5e);
+        WriteReg(0x54,0x80);
+        WriteReg(0x56,0x40);
+        WriteReg(0x58,0x9e);
+        WriteReg(0x59,0x88);
+        WriteReg(0x5a,0x88);
+        WriteReg(0x5b,0x44);
+        WriteReg(0x5c,0x67);
+        WriteReg(0x5d,0x49);
+        WriteReg(0x5e,0x0e);
+        WriteReg(0x69,0x00);
+        WriteReg(0x6a,0x40);
+        WriteReg(0x6b,0x0a);
+        WriteReg(0x6c,0x0a);
+        WriteReg(0x6d,0x55);
+        WriteReg(0x6e,0x11);
+        WriteReg(0x6f,0x9f);
+
+        WriteReg(0xb0,0x84);
+    }    
+
+
+    // vsync handler
+    void VsyncHandler(void)
+    {
+        // Capture Enable
+        if (CaptureReq) {
+            wen = 1 ;
+            Done = false ;
+            CaptureReq = false ;
+        } else {
+            wen = 0 ;
+            if (Busy) {
+                Busy = false ;
+                Done = true ;
+            }
+        }
+
+        // Hline Counter
+        LastLines = LineCounter ;
+        LineCounter = 0 ;
+    }
+    
+    // href handler
+    void HrefHandler(void)
+    {
+        LineCounter++ ;
+    }
+    
+    // Data Read
+    int ReadOneByte(void)
+    {
+        int result ;
+        rclk = 1 ;
+//        wait_us(1) ;
+        result = data ;
+        rclk = 0 ;
+        return result ;
+    }
+
+    // Data Read (PortIn)
+    int ReadOneWord(void)
+    {
+        int r,r1,r2,r3,r4 ;
+        rclk = 1 ;
+        r = data ;
+        rclk = 0 ;
+        r1 = r & 0x07800000 ;
+        r1 = r1 >> (26-7-0) ; // bit26 to bit7
+        r2 = r & 0x00078000 ;
+        r2 = r2 >> (18-3-0) ; // bit18 to bit3        
+        rclk = 1 ;
+        r = data ;        
+        rclk = 0 ;
+        r3 = r & 0x07800000 ;
+        r3 = r3 >> (26-7-8) ; // bit26 to bit7
+        r4 = r & 0x00078000 ;
+        r4 = r4 >> (18-3-8) ; // bit18 to bit3
+        return r4+r3+r2+r1 ;
+    }
+    
+    // Data Start
+    void ReadStart(void)
+    {        
+        rrst = 0 ;
+        oe = 0 ;
+        wait_us(1) ;
+        rclk = 0 ;
+        wait_us(1) ;
+        rclk = 1 ;
+        wait_us(1) ;        
+        rrst = 1 ;
+    }
+    
+    // Data Stop
+    void ReadStop(void)
+    {
+        oe = 1 ;
+        ReadOneByte() ;
+        rclk = 1 ;
+    }
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ov7670reg.h	Fri Feb 17 13:07:18 2012 +0000
@@ -0,0 +1,116 @@
+#define REG_GAIN        0x00    /* Gain lower 8 bits (rest in vref) */
+#define REG_BLUE        0x01    /* blue gain */
+#define REG_RED         0x02    /* red gain */
+#define REG_VREF        0x03    /* Pieces of GAIN, VSTART, VSTOP */
+#define REG_COM1        0x04    /* Control 1 */
+#define COM1_CCIR656    0x40    /* CCIR656 enable */
+#define REG_BAVE        0x05    /* U/B Average level */
+#define REG_GbAVE       0x06    /* Y/Gb Average level */
+#define REG_AECHH       0x07    /* AEC MS 5 bits */
+#define REG_RAVE        0x08    /* V/R Average level */
+#define REG_COM2        0x09    /* Control 2 */
+#define COM2_SSLEEP     0x10    /* Soft sleep mode */
+#define REG_PID         0x0a    /* Product ID MSB */
+#define REG_VER         0x0b    /* Product ID LSB */
+#define REG_COM3        0x0c    /* Control 3 */
+#define COM3_SWAP       0x40    /* Byte swap */
+#define COM3_SCALEEN    0x08    /* Enable scaling */
+#define COM3_DCWEN      0x04    /* Enable downsamp/crop/window */
+#define REG_COM4        0x0d    /* Control 4 */
+#define REG_COM5        0x0e    /* All "reserved" */
+#define REG_COM6        0x0f    /* Control 6 */
+#define REG_AECH        0x10    /* More bits of AEC value */
+#define REG_CLKRC       0x11    /* Clocl control */
+#define CLK_EXT         0x40    /* Use external clock directly */
+#define CLK_SCALE       0x3f    /* Mask for internal clock scale */
+#define REG_COM7        0x12    /* Control 7 */
+#define COM7_RESET      0x80    /* Register reset */
+#define COM7_FMT_MASK   0x38
+#define COM7_FMT_VGA    0x00
+#define COM7_FMT_CIF    0x20    /* CIF format */
+#define COM7_FMT_QVGA   0x10    /* QVGA format */
+#define COM7_FMT_QCIF   0x08    /* QCIF format */
+#define COM7_RGB        0x04    /* bits 0 and 2 - RGB format */
+#define COM7_YUV        0x00    /* YUV */
+#define COM7_BAYER      0x01    /* Bayer format */
+#define COM7_PBAYER     0x05    /* "Processed bayer" */
+#define REG_COM8        0x13    /* Control 8 */
+#define COM8_FASTAEC    0x80    /* Enable fast AGC/AEC */
+#define COM8_AECSTEP    0x40    /* Unlimited AEC step size */
+#define COM8_BFILT      0x20    /* Band filter enable */
+#define COM8_AGC        0x04    /* Auto gain enable */
+#define COM8_AWB        0x02    /* White balance enable */
+#define COM8_AEC        0x01    /* Auto exposure enable */
+#define REG_COM9        0x14    /* Control 9  - gain ceiling */
+#define REG_COM10       0x15    /* Control 10 */
+#define COM10_HSYNC     0x40    /* HSYNC instead of HREF */
+#define COM10_PCLK_HB   0x20    /* Suppress PCLK on horiz blank */
+#define COM10_HREF_REV  0x08    /* Reverse HREF */
+#define COM10_VS_LEAD   0x04    /* VSYNC on clock leading edge */
+#define COM10_VS_NEG    0x02    /* VSYNC negative */
+#define COM10_HS_NEG    0x01    /* HSYNC negative */
+#define REG_HSTART      0x17    /* Horiz start high bits */
+#define REG_HSTOP       0x18    /* Horiz stop high bits */
+#define REG_VSTART      0x19    /* Vert start high bits */
+#define REG_VSTOP       0x1a    /* Vert stop high bits */
+#define REG_PSHFT       0x1b    /* Pixel delay after HREF */
+#define REG_MIDH        0x1c    /* Manuf. ID high */
+#define REG_MIDL        0x1d    /* Manuf. ID low */
+#define REG_MVFP        0x1e    /* Mirror / vflip */
+#define MVFP_MIRROR     0x20    /* Mirror image */
+#define MVFP_FLIP       0x10    /* Vertical flip */
+#define REG_AEW         0x24    /* AGC upper limit */
+#define REG_AEB         0x25    /* AGC lower limit */
+#define REG_VPT         0x26    /* AGC/AEC fast mode op region */
+#define REG_HSYST       0x30    /* HSYNC rising edge delay */
+#define REG_HSYEN       0x31    /* HSYNC falling edge delay */
+#define REG_HREF        0x32    /* HREF pieces */
+#define REG_TSLB        0x3a    /* lots of stuff */
+#define TSLB_YLAST      0x04    /* UYVY or VYUY - see com13 */
+#define REG_COM11       0x3b    /* Control 11 */
+#define COM11_NIGHT     0x80    /* NIght mode enable */
+#define COM11_NMFR      0x60    /* Two bit NM frame rate */
+#define COM11_HZAUTO    0x10    /* Auto detect 50/60 Hz */
+#define COM11_50HZ      0x08    /* Manual 50Hz select */
+#define COM11_EXP       0x02
+#define REG_COM12       0x3c    /* Control 12 */
+#define COM12_HREF      0x80    /* HREF always */
+#define REG_COM13       0x3d    /* Control 13 */
+#define COM13_GAMMA     0x80    /* Gamma enable */
+#define COM13_UVSAT     0x40    /* UV saturation auto adjustment */
+#define COM13_UVSWAP    0x01    /* V before U - w/TSLB */
+#define REG_COM14       0x3e    /* Control 14 */
+#define COM14_DCWEN     0x10    /* DCW/PCLK-scale enable */
+#define REG_EDGE        0x3f    /* Edge enhancement factor */
+#define REG_COM15       0x40    /* Control 15 */
+#define COM15_R10F0     0x00    /* Data range 10 to F0 */
+#define COM15_R01FE     0x80    /*            01 to FE */
+#define COM15_R00FF     0xc0    /*            00 to FF */
+#define COM15_RGB565    0x10    /* RGB565 output */
+#define COM15_RGB555    0x30    /* RGB555 output */
+#define REG_COM16       0x41    /* Control 16 */
+#define COM16_AWBGAIN   0x08    /* AWB gain enable */
+#define REG_COM17       0x42    /* Control 17 */
+#define COM17_AECWIN    0xc0    /* AEC window - must match COM4 */
+#define COM17_CBAR      0x08    /* DSP Color bar */
+#define REG_CMATRIX_BASE 0x4f
+#define CMATRIX_LEN 6
+#define REG_CMATRIX_SIGN 0x58
+#define REG_BRIGHT      0x55    /* Brightness */
+#define REG_CONTRAS     0x56    /* Contrast control */
+#define REG_GFIX        0x69    /* Fix gain control */
+#define REG_REG76       0x76    /* OV's name */
+#define R76_BLKPCOR     0x80    /* Black pixel correction enable */
+#define R76_WHTPCOR     0x40    /* White pixel correction enable */
+#define REG_RGB444      0x8c    /* RGB 444 control */
+#define R444_ENABLE     0x02    /* Turn on RGB444, overrides 5x5 */
+#define R444_RGBX       0x01    /* Empty nibble at end */
+#define REG_HAECC1      0x9f    /* Hist AEC/AGC control 1 */
+#define REG_HAECC2      0xa0    /* Hist AEC/AGC control 2 */
+#define REG_BD50MAX     0xa5    /* 50hz banding step limit */
+#define REG_HAECC3      0xa6    /* Hist AEC/AGC control 3 */
+#define REG_HAECC4      0xa7    /* Hist AEC/AGC control 4 */
+#define REG_HAECC5      0xa8    /* Hist AEC/AGC control 5 */
+#define REG_HAECC6      0xa9    /* Hist AEC/AGC control 6 */
+#define REG_HAECC7      0xaa    /* Hist AEC/AGC control 7 */
+#define REG_BD60MAX     0xab    /* 60hz banding step limit */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/spilcd_qvga.h	Fri Feb 17 13:07:18 2012 +0000
@@ -0,0 +1,226 @@
+//
+// SPILCD_QVGA -- mio
+// This code is based on http://mbed.org/users/Sim/programs/SPILCDsample
+//
+// 2010/06/16 - Now Supports only "LGDP4531" and screen fill test "filltest()" command only (Alpha level).
+//
+
+#ifndef __SPILCD_QVGA_H__
+#define __SPILCD_QVGA_H__
+
+#include "mbed.h"
+
+typedef unsigned int u32 ;
+typedef unsigned short u16 ;
+typedef unsigned char u8 ;
+
+class SPILCD_QVGA {
+private:
+    int rs,rw;
+
+    DigitalOut cs, rst;
+    SPI spi;
+public:
+
+    void reset(u16 data) {
+        rst = data ;
+    }
+
+    void DataToWriteBegin(void) {
+        u8 d ;
+        d = (0x70 | (rs ? 0x02 : 0x00) | (rw ? 0x01 : 0x00)) ;
+        spi.write(d) ;
+// debug
+//        pc.printf("%02X",d) ;
+    }
+
+    u16 DataToWrite16(u16 data) {
+        u8 hiout,loout ;
+        u8 hi,lo ;
+        hiout = (u8)((data & 0xFF00) >> 8) ;
+        hi = spi.write(hiout);
+// debug
+//         pc.printf("%02X",hi) ;
+        loout = ((u8)(data & 0x00FF)) ;
+        lo = spi.write(loout);
+// debug
+//        pc.printf("%02X",lo) ;
+        return (u16)((hi << 8) + lo) ;
+    }
+
+    void DataToWrite(u16 data) {
+        DataToWriteBegin() ;
+        DataToWrite16(data) ;
+    }
+
+    u16 DataToRead(u16 dummy) {
+        rw = 1 ;
+        DataToWriteBegin() ;
+        rw = 0 ;
+        // spi.write(0x00) ; // dummy 1 byte read ??
+        return DataToWrite16(dummy) ;
+    }
+
+    void LCD_WR_REG(u16 Index,u16 CongfigTemp) {
+        csout(0) ;
+        rs = 0 ;
+        DataToWrite(Index);
+        csout(1) ;
+        wait_us(1);
+        csout(0) ;
+        rs = 1 ;
+        DataToWrite(CongfigTemp);
+        csout(1) ;
+    }
+
+    u16 LCD_RD_REG(u16 Index) {
+        u16 result ;
+        csout(0) ;
+        rs = 0 ;
+        DataToWrite(Index);
+        csout(1) ;
+        wait_us(1);
+        csout(0) ;
+        rs = 1 ;
+        result = DataToRead(0x0000);
+        csout(1) ;
+        return result ;
+    }
+
+
+    void Lcd_WR_Start(void) {
+        csout(0) ;
+        rs = 0 ;
+        DataToWrite(0x0022);
+        csout(1) ;
+        wait_us(1);
+        csout(0) ;
+        rs = 1 ;
+    }
+
+    void Lcd_SetCursor(u16 x,u16 y) {
+        LCD_WR_REG(0x20,x);
+        LCD_WR_REG(0x21,y);
+    }
+
+    // boot up sequence
+    void init() {
+        spi.format(8,3); // SPI mode = 3
+        spi.frequency(20000000);
+
+        // reset
+        reset(1);
+        wait_ms(200);
+        reset(0);
+        wait_ms(200);
+        reset(1);
+
+        // initialize sequence
+        DataToWrite16(0xffff);
+        wait_ms(10);
+        LCD_WR_REG(0x0000,0x0001);
+        wait_ms(10);
+
+        u16 id = LCD_RD_REG(0x0000) ;           // CHECK LCD TYPE (ID READ)
+        printf("CHIP ID=%04X\r\n",id) ;
+
+        if (id == 0x4531) {
+            csout(0);
+            DataToWrite16(0x0);
+            DataToWrite16(0x0);
+            csout(1);
+            wait_ms(10);
+            
+            // Setup display
+            LCD_WR_REG(0x10,0x0628);
+            LCD_WR_REG(0x12,0x0006);
+            LCD_WR_REG(0x13,0x0A32);
+            LCD_WR_REG(0x11,0x0040);
+            LCD_WR_REG(0x15,0x0050);
+            LCD_WR_REG(0x12,0x0016);
+            wait_ms(15);
+            LCD_WR_REG(0x10,0x5660);
+            wait_ms(15);
+            LCD_WR_REG(0x13,0x2A4E);
+
+            LCD_WR_REG(0x01,0x0100);
+            LCD_WR_REG(0x02,0x0300);
+            LCD_WR_REG(0x03,0x1038);
+
+            LCD_WR_REG(0x08,0x0202);
+            LCD_WR_REG(0x09,0x0000);
+            LCD_WR_REG(0x0A,0x0000);
+            LCD_WR_REG(0x0C,0x0001); // 16bit , Internal
+
+            LCD_WR_REG(0x30,0x0000);
+            LCD_WR_REG(0x31,0x0402);
+            LCD_WR_REG(0x32,0x0106);
+            LCD_WR_REG(0x33,0x0700);
+            LCD_WR_REG(0x34,0x0104);
+            LCD_WR_REG(0x35,0x0301);
+            LCD_WR_REG(0x36,0x0707);
+            LCD_WR_REG(0x37,0x0305);
+            LCD_WR_REG(0x38,0x0208);
+            LCD_WR_REG(0x39,0x0F0B);
+            wait_ms(15);
+            LCD_WR_REG(0x41,0x0002);
+            LCD_WR_REG(0x60,0x2700);
+            LCD_WR_REG(0x61,0x0001);
+            LCD_WR_REG(0x90,0x0119);
+            LCD_WR_REG(0x92,0x010A);
+            LCD_WR_REG(0x93,0x0004);
+            LCD_WR_REG(0xA0,0x0100);
+            LCD_WR_REG(0x07,0x0001);
+            wait_ms(15);
+            LCD_WR_REG(0x07,0x0021);
+            wait_ms(15);
+            LCD_WR_REG(0x07,0x0023);
+            wait_ms(15);
+            LCD_WR_REG(0x07,0x0033);
+            wait_ms(15);
+            LCD_WR_REG(0x07,0x0133);
+            wait_ms(20);
+            LCD_WR_REG(0xA0,0x0000);
+            wait_ms(20);
+        } else {
+            printf("UNKNOWN LCD\r\n") ;
+        }
+    }
+
+    // constructor
+    SPILCD_QVGA(PinName cs_pin, PinName rst_pin, PinName mosi_pin, PinName miso_pin, PinName sclk_pin)
+            : cs(cs_pin), rst(rst_pin), spi(mosi_pin, miso_pin, sclk_pin) {
+        rw = 0 ;
+        rs = 0 ;
+        init() ;
+    }
+
+    void rsout(u16 data) {
+        rs = data ;
+    }
+
+    void csout(u16 data) {
+        cs = data ;
+    }
+
+    // wipe all screen
+    void filltest(u16 Color) {
+        u16 x,y ;
+        Lcd_SetCursor(0,0);
+        Lcd_WR_Start();
+        rs = 1 ;
+        for (x = 0;x < 240;x++) {
+            for (y = 0;y < 320;y++) {
+//                Lcd_SetCursor(x,y);
+//                LCD_WR_REG(0x22,Color);            
+                csout(0) ;
+                DataToWrite(Color);
+                csout(1) ;
+                Color++ ;
+            }
+        }
+        rs = 0 ;
+    }
+};
+
+#endif