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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Last commit 20 Feb 2019 by 
mbed official
Revision 626:ba773d547214, committed 2015-09-25
- Comitter:
- mbed_official
- Date:
- Fri Sep 25 13:30:09 2015 +0100
- Parent:
- 625:6502bcae5f2c
- Child:
- 627:4fa1328d9c60
- Commit message:
- Synchronized with git revision e8c24ba90dd5507bdb7c1b46dd3aba8cfabb762b
Full URL: https://github.com/mbedmicro/mbed/commit/e8c24ba90dd5507bdb7c1b46dd3aba8cfabb762b/
RZ_A1H - Modify to support NEON for RTOS.
Changed in this revision
--- a/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c Fri Sep 25 12:00:11 2015 +0100
+++ b/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c Fri Sep 25 13:30:09 2015 +0100
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file pl310.c
- * @brief Implementation of pl310 functions
+ * @brief Implementation of PL310 PrimeCell Level 2 Cache Controller functions
* @version
- * @date 11 June 2013
+ * @date 3 December 2014
*
* @note
*
@@ -80,7 +80,7 @@
assoc = 8;
PL310->CLEAN_INV_WAY = (1 << assoc) - 1;
- while(PL310->CLEAN_INV_WAY && ((1 << assoc) - 1)); //poll invalidate
+ while(PL310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
PL310_Sync();
}
--- a/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c Fri Sep 25 12:00:11 2015 +0100
+++ b/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c Fri Sep 25 13:30:09 2015 +0100
@@ -1,14 +1,14 @@
/**************************************************************************//**
* @file system_MBRZA1H.c
* @brief CMSIS Device System Source File for
- * ARMCA9 Device Series
+ * ARM Cortex-A9 Device Series
* @version V1.00
- * @date 19 Sept 2013
+ * @date 09 January 2015
*
* @note
*
******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
+/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -50,9 +50,9 @@
#endif
uint32_t IRQNestLevel;
+unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
-#if defined(__ARMCC_VERSION)
/**
* Initialize the cache.
*
@@ -61,6 +61,7 @@
*
* @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
*/
+#if defined(__ARMCC_VERSION)
#pragma push
#pragma arm
@@ -189,7 +190,7 @@
//Fault Status Register (IFSR/DFSR) definitions
#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup
-#define FSR_INSTRUCTION_CACHE_MAINTAINANCE 0x04 //DFSR only - async/external
+#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external
#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external
#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external
#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external
@@ -223,7 +224,7 @@
//Your code here. Value in DFAR is invalid for some fault statuses.
case FSR_ALIGNMENT_FAULT:
- case FSR_INSTRUCTION_CACHE_MAINTAINANCE:
+ case FSR_INSTRUCTION_CACHE_MAINTENANCE:
case FSR_SYNC_EXT_TTB_WALK_FIRST:
case FSR_SYNC_EXT_TTB_WALK_SECOND:
case FSR_TRANSLATION_FAULT_FIRST:
@@ -278,21 +279,36 @@
}
//returns amount to decrement lr by
-//this will be 0 when we have emulated the instruction and simply want to execute the next instruction
-//this will be 2 when we have performed some maintenance and want to retry the instruction in thumb (state == 2)
-//this will be 4 when we have performed some maintenance and want to retry the instruction in arm (state == 4)
+//this will be 0 when we have emulated the instruction and want to execute the next instruction
+//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
+//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
const unsigned int THUMB = 2;
const unsigned int ARM = 4;
//Lazy VFP/NEON initialisation and switching
- if ((state == ARM && ((opcode & 0x0C000000)) >> 26 == 0x03) ||
- (state == THUMB && ((opcode & 0xEC000000)) >> 26 == 0x3B)) {
- if (((opcode & 0x00000E00) >> 9) == 5) { //fp instruction?
+
+ // (ARM ARM section A7.5) VFP data processing instruction?
+ // (ARM ARM section A7.6) VFP/NEON register load/store instruction?
+ // (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
+ // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
+ if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) ||
+ (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) {
+ if (((opcode & 0x00000E00) >> 9) == 5) {
FPUEnable();
return state;
}
}
+ // (ARM ARM section A7.4) NEON data processing instruction?
+ if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) ||
+ (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) ||
+ // (ARM ARM section A7.7) NEON load/store instruction?
+ (state == ARM && ((opcode >> 24) == 0xF4)) ||
+ (state == THUMB && ((opcode >> 24) == 0xF9))) {
+ FPUEnable();
+ return state;
+ }
+
//Add code here for other Undef cases
while(1);
}
@@ -304,18 +320,22 @@
__asm void FPUEnable(void) {
ARM
- //Permit access to VFP registers by modifying CPACR
+ //Permit access to VFP/NEON, registers by modifying CPACR
MRC p15,0,R1,c1,c0,2
ORR R1,R1,#0x00F00000
MCR p15,0,R1,c1,c0,2
- //Enable VFP
+ //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+ ISB
+
+ //Enable VFP/NEON
VMRS R1,FPEXC
ORR R1,R1,#0x40000000
VMSR FPEXC,R1
- //Initialise VFP registers to 0
+ //Initialise VFP/NEON registers to 0
MOV R2,#0
+ //Initialise D16 registers to 0
VMOV D0, R2,R2
VMOV D1, R2,R2
VMOV D2, R2,R2
@@ -332,7 +352,23 @@
VMOV D13,R2,R2
VMOV D14,R2,R2
VMOV D15,R2,R2
-
+ //Initialise D32 registers to 0
+ VMOV D16,R2,R2
+ VMOV D17,R2,R2
+ VMOV D18,R2,R2
+ VMOV D19,R2,R2
+ VMOV D20,R2,R2
+ VMOV D21,R2,R2
+ VMOV D22,R2,R2
+ VMOV D23,R2,R2
+ VMOV D24,R2,R2
+ VMOV D25,R2,R2
+ VMOV D26,R2,R2
+ VMOV D27,R2,R2
+ VMOV D28,R2,R2
+ VMOV D29,R2,R2
+ VMOV D30,R2,R2
+ VMOV D31,R2,R2
//Initialise FPSCR to a known state
VMRS R2,FPSCR
LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
@@ -344,40 +380,71 @@
#pragma pop
#elif defined(__GNUC__)
-void FPUEnable(void)
-{
- __asm__ __volatile__ (
- ".align 2 \n\t"
- ".arm \n\t"
- "mrc p15,0,r1,c1,c0,2 \n\t"
- "orr r1,r1,#0x00f00000 \n\t"
- "mcr p15,0,r1,c1,c0,2 \n\t"
- "vmrs r1,fpexc \n\t"
- "orr r1,r1,#0x40000000 \n\t"
- "vmsr fpexc,r1 \n\t"
- "mov r2,#0 \n\t"
- "vmov d0, r2,r2 \n\t"
- "vmov d1, r2,r2 \n\t"
- "vmov d2, r2,r2 \n\t"
- "vmov d3, r2,r2 \n\t"
- "vmov d4, r2,r2 \n\t"
- "vmov d5, r2,r2 \n\t"
- "vmov d6, r2,r2 \n\t"
- "vmov d7, r2,r2 \n\t"
- "vmov d8, r2,r2 \n\t"
- "vmov d9, r2,r2 \n\t"
- "vmov d10,r2,r2 \n\t"
- "vmov d11,r2,r2 \n\t"
- "vmov d12,r2,r2 \n\t"
- "vmov d13,r2,r2 \n\t"
- "vmov d14,r2,r2 \n\t"
- "vmov d15,r2,r2 \n\t"
- "vmrs r2,fpscr \n\t"
- "ldr r3,=0x00086060 \n\t"
- "and r2,r2,r3 \n\t"
- "vmsr fpscr,r2 \n\t"
- "bx lr \n\t"
- );
+void FPUEnable(void) {
+ __asm__ (
+ ".ARM;"
+
+ //Permit access to VFP/NEON, registers by modifying CPACR
+ "MRC p15,0,R1,c1,c0,2;"
+ "ORR R1,R1,#0x00F00000;"
+ "MCR p15,0,R1,c1,c0,2;"
+
+ //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+ "ISB;"
+
+ //Enable VFP/NEON
+ "VMRS R1,FPEXC;"
+ "ORR R1,R1,#0x40000000;"
+ "VMSR FPEXC,R1;"
+
+ //Initialise VFP/NEON registers to 0
+ "MOV R2,#0;"
+ //Initialise D16 registers to 0
+ "VMOV D0, R2,R2;"
+ "VMOV D1, R2,R2;"
+ "VMOV D2, R2,R2;"
+ "VMOV D3, R2,R2;"
+ "VMOV D4, R2,R2;"
+ "VMOV D5, R2,R2;"
+ "VMOV D6, R2,R2;"
+ "VMOV D7, R2,R2;"
+ "VMOV D8, R2,R2;"
+ "VMOV D9, R2,R2;"
+ "VMOV D10,R2,R2;"
+ "VMOV D11,R2,R2;"
+ "VMOV D12,R2,R2;"
+ "VMOV D13,R2,R2;"
+ "VMOV D14,R2,R2;"
+ "VMOV D15,R2,R2;"
+ //Initialise D32 registers to 0
+ "VMOV D16,R2,R2;"
+ "VMOV D17,R2,R2;"
+ "VMOV D18,R2,R2;"
+ "VMOV D19,R2,R2;"
+ "VMOV D20,R2,R2;"
+ "VMOV D21,R2,R2;"
+ "VMOV D22,R2,R2;"
+ "VMOV D23,R2,R2;"
+ "VMOV D24,R2,R2;"
+ "VMOV D25,R2,R2;"
+ "VMOV D26,R2,R2;"
+ "VMOV D27,R2,R2;"
+ "VMOV D28,R2,R2;"
+ "VMOV D29,R2,R2;"
+ "VMOV D30,R2,R2;"
+ "VMOV D31,R2,R2;"
+
+ //Initialise FPSCR to a known state
+ "VMRS R2,FPSCR;"
+ "LDR R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+ "AND R2,R2,R3;"
+ "VMSR FPSCR,R2;"
+
+ //"BX LR;"
+ :
+ :
+ :"r1", "r2", "r3");
+ return;
}
#else
#endif
--- a/targets/cmsis/core_caFunc.h Fri Sep 25 12:00:11 2015 +0100
+++ b/targets/cmsis/core_caFunc.h Fri Sep 25 13:30:09 2015 +0100
@@ -2,12 +2,12 @@
* @file core_caFunc.h
* @brief CMSIS Cortex-A Core Function Access Header File
* @version V3.10
- * @date 9 May 2013
+ * @date 30 Oct 2013
*
* @note
*
******************************************************************************/
-/* Copyright (c) 2009 - 2012 ARM LIMITED
+/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -147,8 +147,6 @@
/** \brief Set User Mode
This function changes the processor state to User Mode
-
- \param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_ASM void __set_CPS_USR(void)
{
@@ -253,7 +251,7 @@
This function assigns the given value to the Coprocessor Access Control register.
- \param [in] cpacr Coporcessor Acccess Control value to set
+ \param [in] cpacr Coprocessor Acccess Control value to set
*/
__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
{
@@ -275,7 +273,7 @@
/** \brief Get TTBR0
- This function returns the value of the Configuration Base Address register.
+ This function returns the value of the Translation Table Base Register 0.
\return Translation Table Base Register 0 value
*/
@@ -286,7 +284,7 @@
/** \brief Set TTBR0
- This function assigns the given value to the Coprocessor Access Control register.
+ This function assigns the given value to the Translation Table Base Register 0.
\param [in] ttbr0 Translation Table Base Register 0 value to set
*/
@@ -309,7 +307,7 @@
/** \brief Set DACR
- This function assigns the given value to the Coprocessor Access Control register.
+ This function assigns the given value to the Domain Access Control Register.
\param [in] dacr Domain Access Control Register value to set
*/
@@ -325,7 +323,7 @@
This function assigns the given value to the System Control Register.
- \param [in] sctlr System Control Register, value to set
+ \param [in] sctlr System Control Register value to set
*/
__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
{
@@ -397,9 +395,9 @@
__ISB();
}
-/** \brief Enable MMU
+/** \brief Disable MMU
- Enable MMU
+ Disable MMU
*/
__STATIC_INLINE void __disable_mmu(void) {
// Clear M bit 0 to disable the MMU
@@ -477,8 +475,9 @@
__DMB(); //ensure the ordering of data cache maintenance operations and their effects
}
-/** \brief
- * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
+/** \brief Clean and Invalidate the entire data or unified cache
+
+ Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
*/
#pragma push
#pragma arm
@@ -522,12 +521,12 @@
BNE Dccisw
MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
B cont
-Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
+Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
cont SUBS R9, R9, #1 // Decrement the Way number
BGE Loop3
SUBS R7, R7, #1 // Decrement the Set number
BGE Loop2
-Skip ADD R10, R10, #2 // increment the cache number
+Skip ADD R10, R10, #2 // Increment the cache number
CMP R3, R10
BGT Loop1
@@ -539,9 +538,6 @@
}
#pragma pop
-/** \brief __v7_all_cache - helper function
-
- */
/** \brief Invalidate the whole D$
@@ -577,7 +573,6 @@
#error IAR Compiler support not implemented for Cortex-A
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-
/* GNU gcc specific functions */
#define MODE_USR 0x10
@@ -620,14 +615,12 @@
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
#if 1
- uint32_t result;
-
- __ASM volatile ("mrs %0, apsr" : "=r" (result) );
- return (result);
+ register uint32_t __regAPSR;
+ __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
#else
register uint32_t __regAPSR __ASM("apsr");
+#endif
return(__regAPSR);
-#endif
}
@@ -694,22 +687,49 @@
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
-extern void __set_PSP(uint32_t topOfProcStack);
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __asm__ volatile (
+ ".ARM;"
+ ".eabi_attribute Tag_ABI_align8_preserved,1;"
+
+ "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
+ "MRS R1, CPSR;"
+ "CPS %0;" /* ;no effect in USR mode */
+ "MOV SP, R0;"
+ "MSR CPSR_c, R1;" /* ;no effect in USR mode */
+ "ISB;"
+ //"BX LR;"
+ :
+ : "i"(MODE_SYS)
+ : "r0", "r1");
+ return;
+}
/** \brief Set User Mode
This function changes the processor state to User Mode
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
+{
+ __asm__ volatile (
+ ".ARM;"
- \param [in] topOfProcStack USR/SYS Stack Pointer value to set
- */
-extern void __set_CPS_USR(void);
+ "CPS %0;"
+ //"BX LR;"
+ :
+ : "i"(MODE_USR)
+ : );
+ return;
+}
+
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
-#define __enable_fault_irq __enable_fiq
+#define __enable_fault_irq() __asm__ volatile ("cpsie f")
/** \brief Disable FIQ
@@ -717,7 +737,7 @@
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
-#define __disable_fault_irq __disable_fiq
+#define __disable_fault_irq() __asm__ volatile ("cpsid f")
/** \brief Get FPSCR
@@ -825,7 +845,7 @@
This function assigns the given value to the Coprocessor Access Control register.
- \param [in] cpacr Coporcessor Acccess Control value to set
+ \param [in] cpacr Coprocessor Acccess Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
{
@@ -856,7 +876,7 @@
/** \brief Get TTBR0
- This function returns the value of the Configuration Base Address register.
+ This function returns the value of the Translation Table Base Register 0.
\return Translation Table Base Register 0 value
*/
@@ -872,7 +892,7 @@
/** \brief Set TTBR0
- This function assigns the given value to the Coprocessor Access Control register.
+ This function assigns the given value to the Translation Table Base Register 0.
\param [in] ttbr0 Translation Table Base Register 0 value to set
*/
@@ -904,7 +924,7 @@
/** \brief Set DACR
- This function assigns the given value to the Coprocessor Access Control register.
+ This function assigns the given value to the Domain Access Control Register.
\param [in] dacr Domain Access Control Register value to set
*/
@@ -924,7 +944,7 @@
This function assigns the given value to the System Control Register.
- \param [in] sctlr System Control Register, value to set
+ \param [in] sctlr System Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
{
@@ -1005,9 +1025,9 @@
__ISB();
}
-/** \brief Enable MMU
+/** \brief Disable MMU
- Enable MMU
+ Disable MMU
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
// Clear M bit 0 to disable the MMU
@@ -1109,14 +1129,10 @@
__DMB(); //ensure the ordering of data cache maintenance operations and their effects
}
-/** \brief
- * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
- */
+/** \brief Clean and Invalidate the entire data or unified cache
-/** \brief __v7_all_cache - helper function
-
+ Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
*/
-
extern void __v7_all_cache(uint32_t op);
--- a/targets/cmsis/core_ca_mmu.h Fri Sep 25 12:00:11 2015 +0100
+++ b/targets/cmsis/core_ca_mmu.h Fri Sep 25 13:30:09 2015 +0100
@@ -1,14 +1,13 @@
;/**************************************************************************//**
; * @file core_ca_mmu.h
-; * @brief MMU Startup File for
-; * VE_A9_MP Device Series
+; * @brief MMU Startup File for A9_MP Device Series
; * @version V1.01
-; * @date 25 March 2013
+; * @date 10 Sept 2014
; *
; * @note
; *
; ******************************************************************************/
-;/* Copyright (c) 2012 ARM LIMITED
+;/* Copyright (c) 2012-2014 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
@@ -298,7 +297,7 @@
else if ((priv == RW) && (user == READ)) { ap = 0x2; }
else if ((priv == RW) && (user == RW)) { ap = 0x3; }
else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
- else if ((priv == READ) && (user == READ)) { ap = 0x6; }
+ else if ((priv == READ) && (user == READ)) { ap = 0x7; }
}
else { //Simplified access
@@ -647,7 +646,7 @@
The function creates a section descriptor.
Assumptions:
- - 16MB super sections not suported
+ - 16MB super sections not supported
- TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
- Functions always return 0
