mbed official
mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
Revision 179:b0033dcd6934, committed 2017-12-07
- Comitter:
- AnnaBridge
- Date:
- Thu Dec 07 14:01:42 2017 +0000
- Parent:
- 178:79309dc6340a
- Child:
- 180:96ed750bd169
- Commit message:
- mbed-dev library. Release version 157
Changed in this revision
--- a/mbed.h Thu Nov 23 11:57:25 2017 +0000 +++ b/mbed.h Thu Dec 07 14:01:42 2017 +0000 @@ -16,13 +16,13 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 156 +#define MBED_LIBRARY_VERSION 157 #if MBED_CONF_RTOS_PRESENT // RTOS present, this is valid only for mbed OS 5 #define MBED_MAJOR_VERSION 5 #define MBED_MINOR_VERSION 6 -#define MBED_PATCH_VERSION 5 +#define MBED_PATCH_VERSION 6 #else // mbed 2
--- a/platform/mbed_retarget.cpp Thu Nov 23 11:57:25 2017 +0000
+++ b/platform/mbed_retarget.cpp Thu Dec 07 14:01:42 2017 +0000
@@ -940,7 +940,11 @@
extern "C" WEAK void __iar_file_Mtxlock(__iar_Rmtx *mutex) {}
extern "C" WEAK void __iar_file_Mtxunlock(__iar_Rmtx *mutex) {}
#if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ >= 8000000)
-extern "C" WEAK void *__aeabi_read_tp (void) { return NULL ;}
+#pragma section="__iar_tls$$DATA"
+extern "C" WEAK void *__aeabi_read_tp (void) {
+ // Thread Local storage is not supported, using main thread memory for errno
+ return __section_begin("__iar_tls$$DATA");
+}
#endif
#elif defined(__CC_ARM)
// Do nothing
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/trng_api.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/trng_api.c Thu Dec 07 14:01:42 2017 +0000
@@ -50,6 +50,7 @@
*/
static void trng_get_byte(unsigned char *byte)
{
+ *byte = 0;
size_t bit;
/* 34.5 Steps 3-4-5: poll SR and read from OR when ready */
--- a/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c Thu Dec 07 14:01:42 2017 +0000
@@ -103,8 +103,6 @@
// Schedule wakeup to match semantics of lp_ticker_get_compare_match()
lp_ticker_set_interrupt(wakeup_tick);
-
-
}
timestamp_t lp_ticker_read()
@@ -144,21 +142,13 @@
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t now = lp_ticker_read();
+ uint32_t delta = timestamp - lp_ticker_read();
wakeup_tick = timestamp;
TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- int delta = (int) (timestamp - now);
- if (delta > 0) {
- cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
- lp_ticker_arm_cd();
- } else {
- // NOTE: With lp_ticker_fire_interrupt() introduced, upper layer would handle past event case.
- // This code fragment gets redundant, but it is still kept here for backward-compatible.
- void lp_ticker_fire_interrupt(void);
- lp_ticker_fire_interrupt();
- }
+ cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
+ lp_ticker_arm_cd();
}
void lp_ticker_fire_interrupt(void)
--- a/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c Thu Dec 07 14:01:42 2017 +0000
@@ -25,9 +25,17 @@
/*
* Get Random number generator.
*/
+
+#define PRNG_KEY_SIZE (0x20UL)
+
static volatile int g_PRNG_done;
volatile int g_AES_done;
+/* Implementation that should never be optimized out by the compiler */
+static void trng_zeroize( void *v, size_t n ) {
+ volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
+}
+
void CRYPTO_IRQHandler()
{
if (PRNG_GET_INT_FLAG()) {
@@ -77,21 +85,22 @@
int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
{
(void)obj;
-
- *output_length = 0;
- if (length < 32) {
- unsigned char tmpBuff[32];
+ unsigned char tmpBuff[PRNG_KEY_SIZE];
+ size_t cur_length = 0;
+
+ while (length >= sizeof(tmpBuff)) {
+ trng_get(output);
+ output += sizeof(tmpBuff);
+ cur_length += sizeof(tmpBuff);
+ length -= sizeof(tmpBuff);
+ }
+ if (length > 0) {
trng_get(tmpBuff);
- memcpy(output, &tmpBuff, length);
- *output_length = length;
- } else {
- for (unsigned i = 0; i < (length/32); i++) {
- trng_get(output);
- *output_length += 32;
- output += 32;
- }
+ memcpy(output, tmpBuff, length);
+ cur_length += length;
+ trng_zeroize(tmpBuff, sizeof(tmpBuff));
}
-
+ *output_length = cur_length;
return 0;
}
--- a/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c Thu Dec 07 14:01:42 2017 +0000
@@ -147,16 +147,9 @@
{
TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
- int delta = (int) (timestamp - us_ticker_read());
- if (delta > 0) {
- cd_major_minor_us = delta * US_PER_TICK;
- us_ticker_arm_cd();
- } else {
- // NOTE: With us_ticker_fire_interrupt() introduced, upper layer would handle past event case.
- // This code fragment gets redundant, but it is still kept here for backward-compatible.
- void us_ticker_fire_interrupt(void);
- us_ticker_fire_interrupt();
- }
+ uint32_t delta = timestamp - us_ticker_read();
+ cd_major_minor_us = delta * US_PER_TICK;
+ us_ticker_arm_cd();
}
void us_ticker_fire_interrupt(void)
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c Thu Dec 07 14:01:42 2017 +0000
@@ -30,9 +30,17 @@
/*
* Get Random number generator.
*/
+
+#define PRNG_KEY_SIZE (0x20UL)
+
static volatile int g_PRNG_done;
volatile int g_AES_done;
+/* Implementation that should never be optimized out by the compiler */
+static void trng_zeroize( void *v, size_t n ) {
+ volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
+}
+
void CRYPTO_IRQHandler()
{
if (PRNG_GET_INT_FLAG()) {
@@ -82,21 +90,22 @@
int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
{
(void)obj;
-
- *output_length = 0;
- if (length < 32) {
- unsigned char tmpBuff[32];
+ unsigned char tmpBuff[PRNG_KEY_SIZE];
+ size_t cur_length = 0;
+
+ while (length >= sizeof(tmpBuff)) {
+ trng_get(output);
+ output += sizeof(tmpBuff);
+ cur_length += sizeof(tmpBuff);
+ length -= sizeof(tmpBuff);
+ }
+ if (length > 0) {
trng_get(tmpBuff);
- memcpy(output, &tmpBuff, length);
- *output_length = length;
- } else {
- for (int i = 0; i < (length/32); i++) {
- trng_get(output);
- *output_length += 32;
- output += 32;
- }
+ memcpy(output, tmpBuff, length);
+ cur_length += length;
+ trng_zeroize(tmpBuff, sizeof(tmpBuff));
}
-
+ *output_length = cur_length;
return 0;
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/crc.c Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,234 @@
+/**********************************************************************
+ *
+ * Filename: crc.c
+ *
+ * Description: Slow and fast implementations of the CRC standards.
+ *
+ * Notes: The parameters for each supported CRC standard are
+ * defined in the header file crc.h. The implementations
+ * here should stand up to further additions to that list.
+ *
+ *
+ * Copyright (c) 2000 by Michael Barr. This software is placed into
+ * the public domain and may be used for any purpose. However, this
+ * notice must not be changed or removed and no warranty is either
+ * expressed or implied by its publication or distribution.
+ **********************************************************************/
+
+#include "crc.h"
+
+
+/*
+ * Derive parameters from the standard-specific parameters in crc.h.
+ */
+#define WIDTH (8 * sizeof(crc))
+#define TOPBIT (1 << (WIDTH - 1))
+
+#if (REFLECT_DATA == TRUE)
+#undef REFLECT_DATA
+#define REFLECT_DATA(X) ((unsigned char) reflect((X), 8))
+#else
+#undef REFLECT_DATA
+#define REFLECT_DATA(X) (X)
+#endif
+
+#if (REFLECT_REMAINDER == TRUE)
+#undef REFLECT_REMAINDER
+#define REFLECT_REMAINDER(X) ((crc) reflect((X), WIDTH))
+#else
+#undef REFLECT_REMAINDER
+#define REFLECT_REMAINDER(X) (X)
+#endif
+
+
+/*********************************************************************
+ *
+ * Function: reflect()
+ *
+ * Description: Reorder the bits of a binary sequence, by reflecting
+ * them about the middle position.
+ *
+ * Notes: No checking is done that nBits <= 32.
+ *
+ * Returns: The reflection of the original data.
+ *
+ *********************************************************************/
+static unsigned long
+reflect(unsigned long data, unsigned char nBits)
+{
+ unsigned long reflection = 0x00000000;
+ unsigned char bit;
+
+ /*
+ * Reflect the data about the center bit.
+ */
+ for (bit = 0; bit < nBits; ++bit)
+ {
+ /*
+ * If the LSB bit is set, set the reflection of it.
+ */
+ if (data & 0x01)
+ {
+ reflection |= (1 << ((nBits - 1) - bit));
+ }
+
+ data = (data >> 1);
+ }
+
+ return (reflection);
+
+} /* reflect() */
+
+
+/*********************************************************************
+ *
+ * Function: crcSlow()
+ *
+ * Description: Compute the CRC of a given message.
+ *
+ * Notes:
+ *
+ * Returns: The CRC of the message.
+ *
+ *********************************************************************/
+crc
+crcSlow(unsigned char const message[], int nBytes)
+{
+ crc remainder = INITIAL_REMAINDER;
+ int byte;
+ unsigned char bit;
+
+
+ /*
+ * Perform modulo-2 division, a byte at a time.
+ */
+ for (byte = 0; byte < nBytes; ++byte)
+ {
+ /*
+ * Bring the next byte into the remainder.
+ */
+ remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8));
+
+ /*
+ * Perform modulo-2 division, a bit at a time.
+ */
+ for (bit = 8; bit > 0; --bit)
+ {
+ /*
+ * Try to divide the current data bit.
+ */
+ if (remainder & TOPBIT)
+ {
+ remainder = (remainder << 1) ^ POLYNOMIAL;
+ }
+ else
+ {
+ remainder = (remainder << 1);
+ }
+ }
+ }
+
+ /*
+ * The final remainder is the CRC result.
+ */
+ return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
+
+} /* crcSlow() */
+
+
+crc crcTable[256];
+
+
+/*********************************************************************
+ *
+ * Function: crcInit()
+ *
+ * Description: Populate the partial CRC lookup table.
+ *
+ * Notes: This function must be rerun any time the CRC standard
+ * is changed. If desired, it can be run "offline" and
+ * the table results stored in an embedded system's ROM.
+ *
+ * Returns: None defined.
+ *
+ *********************************************************************/
+void
+crcInit(void)
+{
+ crc remainder;
+ int dividend;
+ unsigned char bit;
+
+
+ /*
+ * Compute the remainder of each possible dividend.
+ */
+ for (dividend = 0; dividend < 256; ++dividend)
+ {
+ /*
+ * Start with the dividend followed by zeros.
+ */
+ remainder = dividend << (WIDTH - 8);
+
+ /*
+ * Perform modulo-2 division, a bit at a time.
+ */
+ for (bit = 8; bit > 0; --bit)
+ {
+ /*
+ * Try to divide the current data bit.
+ */
+ if (remainder & TOPBIT)
+ {
+ remainder = (remainder << 1) ^ POLYNOMIAL;
+ }
+ else
+ {
+ remainder = (remainder << 1);
+ }
+ }
+
+ /*
+ * Store the result into the table.
+ */
+ crcTable[dividend] = remainder;
+ }
+
+} /* crcInit() */
+
+
+/*********************************************************************
+ *
+ * Function: crcFast()
+ *
+ * Description: Compute the CRC of a given message.
+ *
+ * Notes: crcInit() must be called first.
+ *
+ * Returns: The CRC of the message.
+ *
+ *********************************************************************/
+crc
+crcFast(unsigned char const message[], int nBytes)
+{
+ crc remainder = INITIAL_REMAINDER;
+ unsigned char data;
+ int byte;
+
+
+ /*
+ * Divide the message by the polynomial, a byte at a time.
+ */
+ for (byte = 0; byte < nBytes; ++byte)
+ {
+ data = REFLECT_DATA(message[byte]) ^ (remainder >> (WIDTH - 8));
+ remainder = crcTable[data] ^ (remainder << 8);
+ }
+
+ /*
+ * The final remainder is the CRC.
+ */
+ return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
+
+} /* crcFast() */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/crc.h Thu Dec 07 14:01:42 2017 +0000 @@ -0,0 +1,77 @@ +/********************************************************************** + * + * Filename: crc.h + * + * Description: A header file describing the various CRC standards. + * + * Notes: + * + * + * Copyright (c) 2000 by Michael Barr. This software is placed into + * the public domain and may be used for any purpose. However, this + * notice must not be changed or removed and no warranty is either + * expressed or implied by its publication or distribution. + **********************************************************************/ + +#ifndef _crc_h +#define _crc_h + + +#define FALSE 0 +#define TRUE !FALSE + +/* + * Select the CRC standard from the list that follows. + */ +#define CRC16 + + +#if defined(CRC_CCITT) + +typedef unsigned short crc; + +#define CRC_NAME "CRC-CCITT" +#define POLYNOMIAL 0x1021 +#define INITIAL_REMAINDER 0xFFFF +#define FINAL_XOR_VALUE 0x0000 +#define REFLECT_DATA FALSE +#define REFLECT_REMAINDER FALSE +#define CHECK_VALUE 0x29B1 + +#elif defined(CRC16) + +typedef unsigned short crc; + +#define CRC_NAME "CRC-16" +#define POLYNOMIAL 0x8005 +#define INITIAL_REMAINDER 0x0000 +#define FINAL_XOR_VALUE 0x0000 +#define REFLECT_DATA TRUE +#define REFLECT_REMAINDER TRUE +#define CHECK_VALUE 0xBB3D + +#elif defined(CRC32) + +typedef unsigned long crc; + +#define CRC_NAME "CRC-32" +#define POLYNOMIAL 0x04C11DB7 +#define INITIAL_REMAINDER 0xFFFFFFFF +#define FINAL_XOR_VALUE 0xFFFFFFFF +#define REFLECT_DATA TRUE +#define REFLECT_REMAINDER TRUE +#define CHECK_VALUE 0xCBF43926 + +#else + +#error "One of CRC_CCITT, CRC16, or CRC32 must be #define'd." + +#endif + + +void crcInit(void); +crc crcSlow(unsigned char const message[], int nBytes); +crc crcFast(unsigned char const message[], int nBytes); + + +#endif /* _crc_h */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/fsl_phy.c Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_phy.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Defines the timeout macro. */
+#define PHY_TIMEOUT_COUNT 0xFFFFFFU
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the ENET instance from peripheral base address.
+ *
+ * @param base ENET peripheral base address.
+ * @return ENET instance.
+ */
+extern uint32_t ENET_GetInstance(ENET_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to enet clocks for each instance. */
+#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
+extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
+#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
+extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_LPC_ENET_COUNT];
+#endif
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
+{
+ uint32_t reg;
+ uint32_t idReg = 0;
+ uint32_t delay = PHY_TIMEOUT_COUNT;
+ uint32_t instance = ENET_GetInstance(base);
+ bool status = false;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Set SMI first. */
+ CLOCK_EnableClock(s_enetClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
+ ENET_SetSMI(base, srcClock_Hz, false);
+#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
+ ENET_SetSMI(base);
+#endif
+ /* Initialization after PHY stars to work. */
+ while ((idReg != PHY_CONTROL_ID1) && (delay != 0))
+ {
+ PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
+ delay --;
+ }
+
+ if (!delay)
+ {
+ return kStatus_Fail;
+ }
+ delay = PHY_TIMEOUT_COUNT;
+
+ /* Reset PHY and wait until completion. */
+ PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
+ do
+ {
+ PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, ®);
+ } while (delay-- && reg & PHY_BCTL_RESET_MASK);
+
+ if (!delay)
+ {
+ return kStatus_Fail;
+ }
+
+ /* Set the ability. */
+ PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, (PHY_ALL_CAPABLE_MASK | 0x1U));
+
+ /* Start Auto negotiation and wait until auto negotiation completion */
+ PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
+ delay = PHY_TIMEOUT_COUNT;
+ do
+ {
+ PHY_Read(base, phyAddr, PHY_SEPCIAL_CONTROL_REG, ®);
+ delay --;
+ } while (delay && ((reg & PHY_SPECIALCTL_AUTONEGDONE_MASK) == 0));
+
+ if (!delay)
+ {
+ return kStatus_Fail;
+ }
+
+ /* Waiting a moment for phy stable. */
+ for (delay = 0; delay < PHY_TIMEOUT_COUNT; delay++)
+ {
+ __ASM("nop");
+ PHY_GetLinkStatus(base, phyAddr, &status);
+ if (status)
+ {
+ break;
+ }
+ }
+
+ return kStatus_Success;
+}
+
+status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
+{
+#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
+ uint32_t counter;
+
+ /* Clear the SMI interrupt event. */
+ ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+
+ /* Starts a SMI write command. */
+ ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
+
+ /* Wait for SMI complete. */
+ for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
+ {
+ if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
+ {
+ break;
+ }
+ }
+
+ /* Check for timeout. */
+ if (!counter)
+ {
+ return kStatus_PHY_SMIVisitTimeout;
+ }
+
+ /* Clear MII interrupt event. */
+ ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+
+#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
+ ENET_StartSMIWrite(base, phyAddr, phyReg, data);
+ while (ENET_IsSMIBusy(base))
+ ;
+#endif
+ return kStatus_Success;
+}
+
+status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
+{
+#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
+ assert(dataPtr);
+
+ uint32_t counter;
+
+ /* Clear the MII interrupt event. */
+ ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+
+ /* Starts a SMI read command operation. */
+ ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
+
+ /* Wait for MII complete. */
+ for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
+ {
+ if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
+ {
+ break;
+ }
+ }
+
+ /* Check for timeout. */
+ if (!counter)
+ {
+ return kStatus_PHY_SMIVisitTimeout;
+ }
+
+ /* Get data from MII register. */
+ *dataPtr = ENET_ReadSMIData(base);
+
+ /* Clear MII interrupt event. */
+ ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
+ ENET_StartSMIRead(base, phyAddr, phyReg);
+ while (ENET_IsSMIBusy(base))
+ ;
+ *dataPtr = ENET_ReadSMIData(base);
+#endif
+ return kStatus_Success;
+}
+
+status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
+{
+ uint32_t reg;
+ status_t result = kStatus_Success;
+
+ /* Read the basic status register. */
+ result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, ®);
+ if (result == kStatus_Success)
+ {
+ if (reg & PHY_BSTATUS_LINKSTATUS_MASK)
+ {
+ /* link up. */
+ *status = true;
+ }
+ else
+ {
+ *status = false;
+ }
+ }
+ return result;
+}
+
+status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
+{
+ assert(duplex);
+ assert(speed);
+
+ uint32_t reg;
+ status_t result = kStatus_Success;
+
+ /* Read the control two register. */
+ result = PHY_Read(base, phyAddr, PHY_SEPCIAL_CONTROL_REG, ®);
+ if (result == kStatus_Success)
+ {
+ if (reg & PHY_SPECIALCTL_DUPLEX_MASK)
+ {
+ /* Full duplex. */
+ *duplex = kPHY_FullDuplex;
+ }
+ else
+ {
+ /* Half duplex. */
+ *duplex = kPHY_HalfDuplex;
+ }
+
+ if (reg & PHY_SPECIALCTL_100SPEED_MASK)
+ {
+ /* 100M speed. */
+ *speed = kPHY_Speed100M;
+ }
+ else
+ { /* 10M speed. */
+ *speed = kPHY_Speed10M;
+ }
+ }
+ return result;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/fsl_phy.h Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_PHY_H_
+#define _FSL_PHY_H_
+
+#include "fsl_enet.h"
+
+/*!
+ * @addtogroup phy_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief PHY driver version */
+#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+
+/*! @brief Defines the PHY registers. */
+#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
+#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
+#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
+#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
+#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
+#define PHY_SEPCIAL_CONTROL_REG 0x1FU /*!< The PHY control two register. */
+
+#define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/
+
+/*! @brief Defines the mask flag in basic control register. */
+#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
+#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
+#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
+#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */
+#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
+#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
+
+/*!@brief Defines the mask flag of operation mode in special control register*/
+#define PHY_SPECIALCTL_AUTONEGDONE_MASK 0x1000U /*!< The PHY auto-negotiation complete mask. */
+#define PHY_SPECIALCTL_DUPLEX_MASK 0x0010U /*!< The PHY duplex mask. */
+#define PHY_SPECIALCTL_100SPEED_MASK 0x0008U /*!< The PHY speed mask. */
+#define PHY_SPECIALCTL_10SPEED_MASK 0x0004U /*!< The PHY speed mask. */
+#define PHY_SPECIALCTL_SPEEDUPLX_MASK 0x001cU /*!< The PHY speed and duplex mask. */
+
+/*! @brief Defines the mask flag in basic status register. */
+#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
+
+/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
+#define PHY_ALL_CAPABLE_MASK 0x1e0U
+
+/*! @brief Defines the PHY status. */
+enum _phy_status
+{
+ kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 0), /*!< ENET PHY SMI visit timeout. */
+};
+
+/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
+typedef enum _phy_speed {
+ kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
+ kPHY_Speed100M /*!< ENET PHY 100M speed. */
+} phy_speed_t;
+
+/*! @brief Defines the PHY link duplex. */
+typedef enum _phy_duplex {
+ kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
+ kPHY_FullDuplex /*!< ENET PHY full duplex. */
+} phy_duplex_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name PHY Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes PHY.
+ *
+ * This function initialize the SMI interface and initialize PHY.
+ * The SMI is the MII management interface between PHY and MAC, which should be
+ * firstly initialized before any other operation for PHY.
+ *
+ * @param base ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
+ * @retval kStatus_Success PHY initialize success
+ * @retval kStatus_Fail PHY initialize fail
+ */
+status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
+
+/*!
+ * @brief PHY Write function. This function write data over the SMI to
+ * the specified PHY register. This function is called by all PHY interfaces.
+ *
+ * @param base ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register.
+ * @param data The data written to the PHY register.
+ * @retval kStatus_Success PHY write success
+ * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
+ */
+status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
+
+/*!
+ * @brief PHY Read function. This interface read data over the SMI from the
+ * specified PHY register. This function is called by all PHY interfaces.
+ *
+ * @param base ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register.
+ * @param dataPtr The address to store the data read from the PHY register.
+ * @retval kStatus_Success PHY read success
+ * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
+ */
+status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
+
+/*!
+ * @brief Gets the PHY link status.
+ *
+ * @param base ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param status The link up or down status of the PHY.
+ * - true the link is up.
+ * - false the link is down.
+ * @retval kStatus_Success PHY get link status success
+ * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
+ */
+status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
+
+/*!
+ * @brief Gets the PHY link speed and duplex.
+ *
+ * @param base ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param speed The address of PHY link speed.
+ * @param duplex The link duplex of PHY.
+ * @retval kStatus_Success PHY get link speed and duplex success
+ * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
+ */
+status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_PHY_H_ */
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c Thu Dec 07 14:01:42 2017 +0000
@@ -17,6 +17,10 @@
#include "clock_config.h"
#include "fsl_emc.h"
#include "fsl_power.h"
+#include "fsl_flashiap.h"
+
+#define CRC16
+#include "crc.h"
/*******************************************************************************
* Definitions
@@ -37,6 +41,18 @@
#define SDRAM_MODEREG_VALUE (0x23u)
#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/
+uint32_t FLASHIAP_ReadUid(uint32_t *addr)
+{
+ uint32_t command[5], result[5];
+
+ command[0] = kIapCmd_FLASHIAP_ReadUid;
+ iap_entry(command, result);
+
+ memcpy(addr, &result[1], (sizeof(uint32_t) * 4));
+
+ return result[0];
+}
+
// called before main
void mbed_sdk_init()
{
@@ -59,6 +75,38 @@
SYSCON->RTCOSCCTRL |= SYSCON_RTCOSCCTRL_EN_MASK;
}
+// Provide ethernet devices with a semi-unique MAC address from the UUID
+void mbed_mac_address(char *mac)
+{
+ uint16_t MAC[3]; // 3 16 bits words for the MAC
+ uint32_t UID[4];
+
+ // get UID via ISP commands
+ FLASHIAP_ReadUid(UID);
+
+ // generate three CRC16's using different slices of the UUID
+ MAC[0] = crcSlow((const uint8_t *)UID, 8); // most significant half-word
+ MAC[1] = crcSlow((const uint8_t *)UID, 12);
+ MAC[2] = crcSlow((const uint8_t *)UID, 16); // least significant half word
+
+ // The network stack expects an array of 6 bytes
+ // so we copy, and shift and copy from the half-word array to the byte array
+ mac[0] = MAC[0] >> 8;
+ mac[1] = MAC[0];
+ mac[2] = MAC[1] >> 8;
+ mac[3] = MAC[1];
+ mac[4] = MAC[2] >> 8;
+ mac[5] = MAC[2];
+
+ // We want to force bits [1:0] of the most significant byte [0]
+ // to be "10"
+ // http://en.wikipedia.org/wiki/MAC_address
+
+ mac[0] |= 0x02; // force bit 1 to a "1" = "Locally Administered"
+ mac[0] &= 0xFE; // force bit 0 to a "0" = Unicast
+
+}
+
void ADC_ClockPower_Configuration(void)
{
/* SYSCON power. */
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.h Thu Dec 07 14:01:42 2017 +0000
@@ -194,6 +194,123 @@
#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
/* @} */
+/*! @name Alignment variable definition macros */
+/* @{ */
+#if (defined(__ICCARM__))
+/**
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ * http://supp.iar.com/Support/?note=24725
+ */
+_Pragma("diag_suppress=Pm120")
+#define SDK_PRAGMA(x) _Pragma(#x)
+ _Pragma("diag_error=Pm120")
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
+#endif
+#elif defined(__ARMCC_VERSION)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
+#endif
+#elif defined(__GNUC__)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
+#endif
+#else
+#error Toolchain not supported
+#define SDK_ALIGN(var, alignbytes) var
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) var
+#endif
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) var
+#endif
+#endif
+
+/*! Macro to change a value to a given size aligned value */
+#define SDK_SIZEALIGN(var, alignbytes) \
+ ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
+/* @} */
+
+/*! @name Non-cacheable region definition macros */
+/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
+ * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
+ * will be initialized to zero in system startup.
+ */
+/* @{ */
+#if (defined(__ICCARM__))
+#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#endif
+#elif(defined(__ARMCC_VERSION))
+#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+ __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+ __attribute__((section("NonCacheable.init"))) __align(alignbytes) var
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var
+#endif
+#elif(defined(__GNUC__))
+/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ */
+#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+ __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+ __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#endif
+#else
+#error Toolchain not supported.
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
+#endif
+/* @} */
+
/*******************************************************************************
* API
******************************************************************************/
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/analogin_api.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/analogin_api.c Thu Dec 07 14:01:42 2017 +0000
@@ -38,6 +38,13 @@
uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT;
adc_config_t adc_config;
+ uint32_t reg;
+ uint32_t pin_number = pin & 0x1F;
+ uint8_t port_number = pin / 32;
+
+ /* Clear the DIGIMODE bit */
+ reg = IOCON->PIO[port_number][pin_number] & ~IOCON_PIO_DIGIMODE_MASK;
+ IOCON->PIO[port_number][pin_number] = reg;
ADC_ClockPower_Configuration();
@@ -69,6 +76,7 @@
adcConvSeqConfigStruct.interruptMode = kADC_InterruptForEachSequence;
ADC_SetConvSeqAConfig(adc_addrs[instance], &adcConvSeqConfigStruct);
+ ADC_EnableConvSeqA(adc_addrs[instance], true);
ADC_DoSoftwareTriggerConvSeqA(adc_addrs[instance]);
/* Wait for the converter to be done. */
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PinNames.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/PinNames.h Thu Dec 07 14:01:42 2017 +0000
@@ -50,6 +50,7 @@
PIN_OUTPUT
} PinDirection;
+
typedef enum {
PA_0 = (PORT_A<<4|0),
PA_1 = (PORT_A<<4|1),
@@ -158,7 +159,7 @@
PK_5 = (PORT_K<<4|5),
PK_6 = (PORT_K<<4|6),
/* unavailable pins */
-// PK_7 = (PORT_K<<4|7),
+ // PK_7 = (PORT_K<<4|7),
AD_1 = (PORT_V<<4|1),
AD_2 = (PORT_V<<4|2),
@@ -166,34 +167,9 @@
DA_0 = (PORT_U<<4|0),
DA_1 = (PORT_U<<4|1),
-
- // Arduino connector namings
- A0 = AD_2,//A0 and A1 are connected
- A1 = AD_2,
- A2 = AD_3,
-
- D0 = PA_6,
- D1 = PA_7,
- D2 = PA_5,
- D3 = PD_4,
- D4 = PD_5,
- D5 = PA_4,
- D6 = PA_3,
- D7 = PA_2,
- D8 = PB_4,
- D9 = PB_5,
- D10 = PC_0,
- D11 = PC_2,
- D12 = PC_3,
- D13 = PC_1,
- D14 = PB_3,
- D15 = PB_2,
-
- D16 = PA_1,
- D17 = PA_0,
- D18 = PE_5,
-
+ // Not connected
+ NC = (uint32_t)0xFFFFFFFF,
// Generic signals namings
/* LED1~4 are defined as alias of GPIO pins, they are not the LEDs on board*/
@@ -213,8 +189,35 @@
SPI_CS = PC_0,
PWM_OUT = PD_4,
- // Not connected
- NC = (uint32_t)0xFFFFFFFF
+ // Arduino connector namings
+
+ A0 = AD_2,//A0 and A1 are connected
+ A1 = AD_2,
+ A2 = AD_3,
+ A3 = NC,
+ A4 = NC,
+ A5 = NC,
+
+ D0 = PA_6,
+ D1 = PA_7,
+ D2 = PA_5,
+ D3 = PD_4,
+ D4 = PD_5,
+ D5 = PA_4,
+ D6 = PA_3,
+ D7 = PA_2,
+ D8 = PB_4,
+ D9 = PB_5,
+ D10 = PC_0,
+ D11 = PC_2,
+ D12 = PC_3,
+ D13 = PC_1,
+ D14 = PB_3,
+ D15 = PB_2,
+ D16 = PA_1,
+ D17 = PA_0,
+ D18 = PE_5
+
} PinName;
typedef enum {
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a.h Thu Nov 23 11:57:25 2017 +0000 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a.h Thu Dec 07 14:01:42 2017 +0000 @@ -43,8 +43,7 @@ #include "rtl8195a_compiler.h" #include "rtl8195a_platform.h" - - +#include "rtl8195a_crypto.h" #define REG32(reg) (*(volatile uint32_t *)(reg)) #define REG16(reg) (*(volatile uint16_t *)(reg))
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_crypto.h Thu Dec 07 14:01:42 2017 +0000 @@ -0,0 +1,24 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013-2017 Realtek Semiconductor Corp. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_RTL8195A_CRYPTO_H +#define MBED_RTL8195A_CRYPTO_H + +extern _LONG_CALL_ uint32_t crc32_get(uint8_t *buf, int len); + +#endif
--- a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c Thu Dec 07 14:01:42 2017 +0000
@@ -13,7 +13,6 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-#include <stdio.h>
#include <string.h>
#include "mbed_wait_api.h"
@@ -24,61 +23,105 @@
static flash_t flash_obj;
-void OTA_GetImageInfo(imginfo_t *info)
+void OTA_ReadHeader(uint32_t base, imginfo_t *img)
{
- uint32_t ver_hi, ver_lo;
+ uint32_t epoch_hi, epoch_lo;
+
+ if (base != OTA_REGION1_BASE || base != OTA_REGION2_BASE) {
+ return;
+ }
+
+ flash_ext_read_word(&flash_obj, base + OTA_TAG_OFS, &img->tag);
+ flash_ext_read_word(&flash_obj, base + OTA_VER_OFS, &img->ver);
+ flash_ext_read_word(&flash_obj, base + OTA_EPOCH_OFS, &epoch_hi);
+ flash_ext_read_word(&flash_obj, base + OTA_EPOCH_OFS + 4, &epoch_lo);
+ img->timestamp = ((uint64_t)epoch_hi << 32) | (uint64_t) epoch_lo;
- flash_ext_read_word(&flash_obj, info->base + TAG_OFS, &info->tag);
- flash_ext_read_word(&flash_obj, info->base + VER_OFS, &ver_lo);
- flash_ext_read_word(&flash_obj, info->base + VER_OFS + 4, &ver_hi);
+ flash_ext_read_word(&flash_obj, base + OTA_SIZE_OFS, &img->size);
+ flash_ext_stream_read(&flash_obj, base + OTA_HASH_OFS, 32, img->hash);
+ flash_ext_stream_read(&flash_obj, base + OTA_CAMPAIGN_OFS, 16, img->campaign);
+ flash_ext_read_word(&flash_obj, base + OTA_CRC32_OFS, &img->crc32);
+}
+
+bool OTA_CheckHeader(imginfo_t *img)
+{
+ uint8_t *msg;
+ uint32_t crc;
- if (info->tag == TAG_DOWNLOAD) {
- info->ver = ((uint64_t)ver_hi << 32) | (uint64_t) ver_lo;
- } else {
- info->ver = 0;
+ msg = (uint8_t *)img;
+ crc = crc32_get(msg, OTA_CRC32_LEN);
+ if (crc != img->crc32) {
+ return false;
}
+
+ if ((img->tag & OTA_TAG_CHIP_MSK) != (OTA_TAG_ID & OTA_TAG_CHIP_MSK)) {
+ return false;
+ }
+
+ return true;
}
-uint32_t OTA_GetBase(void)
+void OTA_GetImageInfo(uint32_t base, imginfo_t *img)
{
- static uint32_t ota_base = 0;
- imginfo_t region1, region2;
+ OTA_ReadHeader(base, img);
- if (ota_base == OTA_REGION1 || ota_base == OTA_REGION2) {
- return ota_base;
+ if (!OTA_CheckHeader(img)) {
+ img->timestamp = 0;
+ img->valid = false;
}
- region1.base = OTA_REGION1;
- region2.base = OTA_REGION2;
-
- OTA_GetImageInfo(®ion1);
- OTA_GetImageInfo(®ion2);
-
- if (region1.ver >= region2.ver) {
- ota_base = region2.base;
- } else {
- ota_base = region1.base;
- }
- return ota_base;
+ img->valid = true;
}
-uint32_t OTA_MarkUpdateDone(void)
+uint32_t OTA_GetUpdateBase(void)
{
- uint32_t addr = OTA_GetBase() + TAG_OFS;
+ imginfo_t img1, img2;
+
+ OTA_GetImageInfo(OTA_REGION1_BASE, &img1);
+ OTA_GetImageInfo(OTA_REGION2_BASE, &img2);
- return flash_ext_write_word(&flash_obj, addr, TAG_DOWNLOAD);
+ if (img1.valid && img2.valid) {
+ if (img1.timestamp < img2.timestamp) {
+ return OTA_REGION1_BASE;
+ } else {
+ return OTA_REGION2_BASE;
+ }
+ }
+
+ if (img1.valid) {
+ return OTA_REGION2_BASE;
+ }
+
+ return OTA_REGION1_BASE;
}
-uint32_t OTA_UpdateImage(uint32_t offset, uint32_t len, uint8_t *data)
+uint32_t OTA_UpateHeader(uint32_t base, imginfo_t *img)
+{
+ flash_ext_write_word(&flash_obj, base + OTA_TAG_OFS, img->tag);
+ flash_ext_write_word(&flash_obj, base + OTA_VER_OFS, img->ver);
+ flash_ext_write_word(&flash_obj, base + OTA_EPOCH_OFS, img->timestamp >> 32);
+ flash_ext_write_word(&flash_obj, base + OTA_EPOCH_OFS + 4, (img->timestamp << 32) >> 32);
+
+ flash_ext_write_word(&flash_obj, base + OTA_SIZE_OFS, img->size);
+ flash_ext_stream_write(&flash_obj, base + OTA_HASH_OFS, 32, img->hash);
+ flash_ext_stream_write(&flash_obj, base + OTA_CAMPAIGN_OFS, 16, img->campaign);
+ flash_ext_write_word(&flash_obj, base + OTA_CRC32_OFS, img->crc32);
+
+ return 0;
+}
+
+uint32_t OTA_UpdateImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data)
{
uint32_t addr, start, end, count, shift;
uint8_t *pdata = data;
uint8_t buf[FLASH_SECTOR_SIZE];
- start = OTA_GetBase() + offset;
+ start = base + offset;
end = start + len;
- if (data == NULL || start > FLASH_TOP || end > FLASH_TOP) {
+ if (data == NULL ||
+ base != OTA_REGION1_BASE || base != OTA_REGION2_BASE ||
+ start > FLASH_TOP || end > FLASH_TOP) {
return 0;
}
@@ -96,7 +139,6 @@
}
while (addr < end) {
- printf("OTA: update addr=0x%lx, len=%ld\r\n", addr, len);
count = MIN(FLASH_SECTOR_SIZE, end - addr);
flash_ext_erase_sector(&flash_obj, addr);
flash_ext_stream_write(&flash_obj, addr, count, pdata);
@@ -106,19 +148,20 @@
return len;
}
-uint32_t OTA_ReadImage(uint32_t offset, uint32_t len, uint8_t *data)
+uint32_t OTA_ReadImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data)
{
- uint32_t addr, endaddr;
+ uint32_t start, end;
- addr = OTA_GetBase() + offset;
- endaddr = addr + len;
+ start = base + offset;
+ end = start + len;
- if (data == NULL || addr > FLASH_TOP || endaddr > FLASH_TOP) {
+ if (data == NULL ||
+ base != OTA_REGION1_BASE || base != OTA_REGION2_BASE ||
+ start > FLASH_TOP || end > FLASH_TOP) {
return 0;
}
- printf("OTA: read addr=0x%lx\r\n", addr);
- return flash_ext_stream_read(&flash_obj, addr, len, data);
+ return flash_ext_stream_read(&flash_obj, start, len, data);
}
void OTA_ResetTarget(void)
@@ -126,11 +169,7 @@
__RTK_CTRL_WRITE32(0x14, 0x00000021);
wait(1);
- // write SCB->AIRCR
- HAL_WRITE32(0xE000ED00, 0x0C,
- (0x5FA << 16) | // VECTKEY
- (HAL_READ32(0xE000ED00, 0x0C) & (7 << 8)) | // PRIGROUP
- (1 << 2)); // SYSRESETREQ
+ NVIC_SystemReset();
// not reached
while (1);
--- a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,33 +1,75 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2013-2017 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
#ifndef MBED_OTA_API_H
#define MBED_OTA_API_H
-#define FLASH_TOP 0x200000
-#define FLASH_SECTOR_SIZE 0x1000
-#define FLASH_SECTOR_MASK ~(FLASH_SECTOR_SIZE - 1)
-#define OTA_REGION1 0x0b000
-#define OTA_REGION2 0xc0000
-#define TAG_OFS 0xc
-#define VER_OFS 0x10
+#define FLASH_TOP 0x200000
+#define FLASH_SECTOR_SIZE 0x1000
+#define FLASH_SECTOR_MASK ~(FLASH_SECTOR_SIZE - 1)
+
+#define OTA_REGION1_BASE 0x40000
+#define OTA_REGION2_BASE 0x120000
+#define OTA_REGION1_SIZE 0xe0000
+#define OTA_REGION2_SIZE 0xe0000
+#define OTA_REGION_SIZE 0xe0000
+#define OTA_MBED_FS_BASE 0xb000
+
+#define OTA_CRC32_LEN 0x44
+#define OTA_HEADER_LEN 0x48
-#define TAG_DOWNLOAD 0x81950001
-#define TAG_VERIFIED 0x81950003
+#define OTA_HEADER_OFS 0x0
+#define OTA_TAG_OFS 0x0
+#define OTA_VER_OFS 0x4
+#define OTA_EPOCH_OFS 0x8
+#define OTA_SIZE_OFS 0x10
+#define OTA_HASH_OFS 0x14
+#define OTA_CAMPAIGN_OFS 0x34
+#define OTA_CRC32_OFS 0x44
+#define OTA_IMAGE_OFS 0x48
+
+#define OTA_TAG_ID 0x81950001
+#define OTA_VER_ID 0x81950001
+
+#define OTA_TAG_CHIP_MSK 0xFFFF0000
+#define OTA_TAG_INFO_MSK 0x0000FFFF
typedef struct imginfo_s {
- uint32_t base;
uint32_t tag;
- uint64_t ver;
+ uint32_t ver;
+ uint64_t timestamp;
+ uint32_t size;
+ uint8_t hash[32];
+ uint8_t campaign[16];
+ uint32_t crc32;
+ bool valid;
} imginfo_t;
#ifdef __cplusplus
extern "C" {
#endif
-extern void OTA_GetImageInfo(imginfo_t *info);
-extern uint32_t OTA_GetBase(void);
+extern void OTA_GetImageInfo(uint32_t base, imginfo_t *info);
+extern uint32_t OTA_GetUpdateBase(void);
-extern uint32_t OTA_UpdateImage(uint32_t offset, uint32_t len, uint8_t *data);
-extern uint32_t OTA_ReadImage(uint32_t offset, uint32_t len, uint8_t *data);
-extern uint32_t OTA_MarkUpdateDone(void);
+extern uint32_t OTA_UpdateHeader(uint32_t base, imginfo_t *img);
+extern uint32_t OTA_UpdateImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data);
+extern void OTA_ReadHeader(uint32_t base, imginfo_t *img);
+extern uint32_t OTA_ReadImage(uint32_t base, uint32_t offset, uint32_t len, uint8_t *data);
extern void OTA_ResetTarget(void);
#ifdef __cplusplus
@@ -35,4 +77,3 @@
#endif
#endif /* MBED_OTA_API_H */
-
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PeripheralNames.h Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+#define STDIO_UART_TX PB_6
+#define STDIO_UART_RX PB_7
+#define STDIO_UART UART_1
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PeripheralPins.c Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,224 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // SERIAL_TX
+// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // SERIAL_RX
+// {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // SPI_CS
+// {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // SPI_CLK
+// {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // SPI_MISO
+// {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // SPI_MOSI
+// {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // SPI_CLK
+// {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 // SPI_CS
+// {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Push SW 3
+// {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Push SW 4
+// {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 // Slide SW 1
+// {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // Slide SW 2
+// {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // LED-4
+// {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Display LED
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+// {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+// {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+// {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Warning: also on SCL
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+// {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // SERIAL_TX
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // SERIAL_TX
+// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // SERIAL_TX
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // SERIAL_RX
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // SERIAL_RX
+// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // SERIAL_RX
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO
+// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO
+// {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+// {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+
+// {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+// {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO
+// {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO
+// {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+// {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO
+// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+// {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 1, 0)}, // TIM10_CH1
+// {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO
+// {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+// {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+
+// {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+// {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO
+// {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+// {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX
+// {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // WAKE_OUT
+// {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // GPS_EN
+// {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // GPS module SPI
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX
+// {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // MPU9250 SPI MOSI
+// {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // MPU9250 SPI MISO
+// {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // GROVE SDA
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+// {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+// {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+// {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+// {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+// {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+// {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+// {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+// {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+// {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Warning: also on NSS
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+// {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+// {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Warning: also on SCLK
+// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Warning: also on SCLK
+ {NC, NC, 0}
+};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PinNames.h Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,208 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // External IO connector namings
+ A0 = PA_0,
+ A1 = PA_1,
+ VBAT_AD_IN = A0,
+ VBAT_AD_EN = A1,
+ I2C_SCL = PB_10,
+ I2C_SDA = PB_3,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PA_4,
+
+ EXT_PIN_3 = PA_7,
+ EXT_PIN_4 = PA_6,
+ EXT_PIN_5 = PA_5,
+ EXT_PIN_6 = PA_4,
+ EXT_PIN_7 = PA_3,
+ EXT_PIN_8 = PA_2,
+ EXT_PIN_9 = PB_10,
+ EXT_PIN_10 = PB_3,
+ EXT_PIN_13 = PA_0,
+ EXT_PIN_14 = PA_1,
+
+ EXT_I2C_SCL = I2C_SCL,
+ EXT_I2C_SDA = I2C_SDA,
+ EXT_SPI_MOSI = SPI_MOSI,
+ EXT_SPI_MISO = SPI_MISO,
+ EXT_SPI_SCK = SPI_SCK,
+ EXT_SPI_CS = SPI_CS,
+ EXT_SERIAL_TX = PA_2,
+ EXT_SERIAL_RX = PA_3,
+
+ SCM_I2C_SCL = PA_8,
+ SCM_I2C_SDA = PC_9,
+ SCM_SPI_MOSI = PB_15,
+ SCM_SPI_MISO = PB_14,
+ SCM_SPI_SCK = PB_13,
+ SCM_SPI_CS = PB_12,
+ SCM_WAKE_IN = PC_8,
+ SCM_WAKE_OUT = PA_9,
+
+ GPS_INT = PB_5,
+ GPS_1PPS = PB_4,
+ GPS_WAKEUP = PD_2,
+ GPS_EN = PA_11,
+ GPS_SERIAL_TX = PC_6,
+ GPS_SERIAL_RX = PC_7,
+ GPS_SPI_MOSI = PC_12,
+ GPS_SPI_MISO = PC_11,
+ GPS_SPI_SCK = PC_10,
+ GPS_SPI_CS = PA_15,
+
+ LCD_LED = PC_5,
+ LCD_I2C_SCL = PB_8,
+ LCD_I2C_SDA = PB_9,
+ BME280_I2C_SCL = PB_8,
+ BME280_I2C_SDA = PB_9,
+
+ MPU9250_SPI_MOSI = PA_10,
+ MPU9250_SPI_MISO = PA_12,
+ MPU9250_SPI_SCK = PB_0,
+ MPU9250_SPI_CS = PB_1,
+
+ // Generic signals namings
+ LED1 = PC_13,
+ LED2 = PC_15,
+ LED3 = PH_1,
+ LED4 = PC_4,
+ LED_RED = LED1,
+
+ // Standardized button names
+ SW1 = PC_14,
+ SW2 = PH_0,
+ SW3 = PC_0,
+ SW4 = PC_1,
+ SW5 = PC_2,
+ SW6 = PC_3,
+
+ USER_BUTTON = SW1,
+ BUTTON1 = SW1,
+ BUTTON2 = SW2,
+ BUTTON3 = SW3,
+ BUTTON4 = SW4,
+ SLIDE_SW1 = SW5,
+ SLIDE_SW2 = SW6,
+
+ // Serial port pins
+ SERIAL_TX = PB_6,
+ SERIAL_RX = PB_7,
+ USBTX = PB_6,
+ USBRX = PB_7,
+
+ // USB pins
+ // USB_OTG_FS_SOF = PA_8,
+ // USB_OTG_FS_VBUS = PA_9,
+ // USB_OTG_FS_ID = PA_10,
+ // USB_OTG_FS_DM = PA_11,
+ // USB_OTG_FS_DP = PA_12,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/system_clock.c Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,245 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) | CLOCK_SOURCE_USB=1
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) |
+ * | 3- USE_PLL_HSI (internal 16 MHz) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 100 | 96
+ * AHBCLK (MHz) | 100 | 96
+ * APB1CLK (MHz) | 50 | 48
+ * APB2CLK (MHz) | 100 | 96
+ * USB capable | NO | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+* @brief Configures the System clock source, PLL Multiplier and Divider factors,
+* AHB/APBx prescalers and Flash settings
+* @note This function should be called only once the RCC clock configuration
+* is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ while(1) {
+ MBED_ASSERT(1);
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ // Enable HSE oscillator and activate PLL with HSE as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
+#if (CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
+#else /* CLOCK_SOURCE_USB */
+ RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
+#endif /* CLOCK_SOURCE_USB */
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz or 96 MHz (depending on CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (CLOCK_SOURCE_USB=1)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100/96 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100/96 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50/48 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100/96 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
+#if (CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
+#else /* CLOCK_SOURCE_USB */
+ RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
+#endif /* CLOCK_SOURCE_USB */
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz or 96 MHz (depending on CLOCK_SOURCE_USB)
+ RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (CLOCK_SOURCE_USB=1)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l072xz.sct Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32L072CZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
+LR_IROM1 0x08000000 0x30000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x30000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xC0) (0x5000-0xC0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l073xz.sct Thu Nov 23 11:57:25 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2015, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-; this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-; this list of conditions and the following disclaimer in the documentation
-; and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-; may be used to endorse or promote products derived from this software
-; without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L073RZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
-LR_IROM1 0x08000000 0x30000 { ; load region size_region
-
- ER_IROM1 0x08000000 0x30000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
-
- ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
- RW_IRAM1 (0x20000000+0xC0) (0x5000-0xC0) { ; RW data
- .ANY (+RW +ZI)
- }
-
-}
-
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l072xz.sct Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32L072CZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
+LR_IROM1 0x08000000 0x30000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x30000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xC0) (0x5000-0xC0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l073xz.sct Thu Nov 23 11:57:25 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2015, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-; this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-; this list of conditions and the following disclaimer in the documentation
-; and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-; may be used to endorse or promote products derived from this software
-; without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L073RZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
-LR_IROM1 0x08000000 0x30000 { ; load region size_region
-
- ER_IROM1 0x08000000 0x30000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
-
- ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
- RW_IRAM1 (0x20000000+0xC0) (0x5000-0xC0) { ; RW data
- .ANY (+RW +ZI)
- }
-
-}
-
--- a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c Thu Dec 07 14:01:42 2017 +0000
@@ -491,9 +491,11 @@
irq_n = USART2_IRQn;
break;
+#if defined(UART3_BASE)
case 2:
irq_n = USART3_IRQn;
break;
+#endif
#if defined(UART4_BASE)
case 3:
irq_n = UART4_IRQn;
--- a/targets/TARGET_STM/stm_spi_api.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_STM/stm_spi_api.c Thu Dec 07 14:01:42 2017 +0000
@@ -29,6 +29,7 @@
*/
#include "mbed_assert.h"
#include "mbed_error.h"
+#include "mbed_debug.h"
#include "spi_api.h"
#if DEVICE_SPI
@@ -286,6 +287,16 @@
handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
+ if (slave && (handle->Init.Direction == SPI_DIRECTION_1LINE)) {
+ /* SPI slave implemtation in MBED does not support the 3 wires SPI.
+ * (e.g. when MISO is not connected). So we're forcing slave in
+ * 2LINES mode. As MISO is not connected, slave will only read
+ * from master, and cannot write to it. Inform user.
+ */
+ debug("3 wires SPI slave not supported - slave will only read\r\n");
+ handle->Init.Direction = SPI_DIRECTION_2LINES;
+ }
+
init_spi(obj);
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c Thu Dec 07 14:01:42 2017 +0000
@@ -40,10 +40,10 @@
/* Init structure */
obj->adc = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC);
- MBED_ASSERT((int) obj->adc != NC);
+ MBED_ASSERT((unsigned int) obj->adc != NC);
obj->channel = pin_location(pin, PinMap_ADC);
- MBED_ASSERT((int) obj->channel != NC);
+ MBED_ASSERT((unsigned int) obj->channel != NC);
/* Only initialize the ADC once */
if (!adc_initialized) {
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/analogout_api.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/analogout_api.c Thu Dec 07 14:01:42 2017 +0000
@@ -41,11 +41,11 @@
{
/* init in-memory structure */
obj->dac = (DAC_TypeDef *) pinmap_peripheral(pin, PinMap_DAC);
- MBED_ASSERT((int) obj->dac != NC);
+ MBED_ASSERT((unsigned int) obj->dac != NC);
obj->channel = pin_location(pin, PinMap_DAC);
- MBED_ASSERT((int) obj->channel != NC);
-
+ MBED_ASSERT((unsigned int) obj->channel != NC);
+
pin_mode(pin, Disabled);
if (!dac_initialized) {
@@ -78,7 +78,7 @@
DAC_InitChannel_TypeDef initChannel = DAC_INITCHANNEL_DEFAULT;
initChannel.enable = false;
DAC_InitChannel(obj->dac, &initChannel, obj->channel);
-
+
//Check all channels to see if we can disable the DAC completely
if((DAC0->CH0CTRL & DAC_CH0CTRL_EN) == 0 && (DAC0->CH1CTRL & DAC_CH1CTRL_EN) == 0) {
CMU_ClockEnable(cmuClock_DAC0, false);
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h Thu Dec 07 14:01:42 2017 +0000
@@ -41,7 +41,7 @@
PI0 = 8 << 4, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, \
PJ0 = 9 << 4, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, \
PK0 = 10 << 4, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, \
- NC = (int) 0xFFFFFFFF
+ NC = (unsigned int) 0xFFFFFFFFUL
#ifdef __cplusplus
extern "C" {
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/dma_api_HAL.h Thu Nov 23 11:57:25 2017 +0000 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/dma_api_HAL.h Thu Dec 07 14:01:42 2017 +0000 @@ -45,6 +45,7 @@ #define DMA_CAP_2DCOPY (1 << 0) #define DMA_CAP_NONE (0 << 0) +#ifdef DMA_PRESENT #if ( DMA_CHAN_COUNT <= 4 ) #define DMACTRL_CH_CNT 4 #define DMACTRL_ALIGNMENT 256 @@ -60,6 +61,7 @@ #else #error "Unsupported DMA channel count (dma_api.c)." #endif +#endif #ifdef LDMA_PRESENT typedef void (*LDMAx_CBFunc_t)(unsigned int channel, bool primary, void *user);
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt Thu Nov 23 11:57:25 2017 +0000 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt Thu Dec 07 14:01:42 2017 +0000 @@ -1,4 +1,67 @@ ================ Revision history ============================================ +5.3.3 + - em_cmu: 48 MHz HFRCO band selectable for devices that support it. + - em_emu: Added macro guards for BU mode functionality for series 0 devices. + +5.3.2 + - No changes. + +5.3.1 + - em_opamp: Corrected reload of default calibration trims in OPAMP_Enable() + for Series 0. + - em_core: Fixed invalid parameter in CORE_YIELD_CRITICAL and + CORE_YIELD_ATOMIC macros. + +5.3.0 + - em_chip: Updated PLFRCO tuning values. + - em_can: Fixed ID filter mask bug. + - em_gpio: Doc updates. + - em_gpio: Fixed bug in GPIO pin validation to enable PD9 on BGM121 modules. + - em_ldma: Added missing signals for EFM32GG11. + +5.2.2: + - em_emu: Fixed bug in EMU_EM4Init(), The BUBODRSTDIS field was not initialized + as specified in function input parameters. + +5.2.1: + - em_emu: Fixed a problem with handling of DCDC bypass current limiter + that may cause brownout reset. + - em_chip: Added workaround for errata DCDC-E206 for EFR32xG1x devices. + - em_cmu: Fixed handling of HFCLKLE prescaling at frequencies above 64 MHz. + +5.2.0: + - em_cmu: Added flash wait state handling for all devices that can scale down + the voltage. + - em_adc: Fixed bug where ADC SINGLECTRLX register fields VREFSEL, PRSSEL and + FIFOOFACT was not cleared when calling ADC_InitSingle(). + - em_msc: Removed call to SystemCoreClockGet() in MSC_Init. + - em_msc: MSC_WriteWordFast() can now only be used when executing code from + RAM on parts that include a flash write buffer. + - em_emu: Using VMON calibration values to set voltage thresholds when + calling EMU_VmonInit() and EMU_VmonHystInit(). The DI page contains + calibration values for 1.86 V and 2.98 V for each VMON channel. Updated + VMON supported voltage range to 1.62V-3.4V. + - em_emu: Added EMU_Save() and changed EMU_EnterEM2() and EMU_EnterEM3() + to only save the state if the restore parameter is true. + - em_usart: Fixed USART async baudrate calculation for EFM32HG devices. + The extra fractional bits in the CLKDIV register was not used. + - Added support for EFM32GG11B devices. This includes new modules for + Quad SPI (em_qspi) and CAN (em_can). This also includes + changes to other emlib modules in order to support the changes in the + register interface of the new device. + - em_cmu: Added DPLL support. Added support for asynchronous clocks for + ADC, reference clocks for QSPI and SDIO and USB rate clock. Added + functions to support the USHFRCO and clock select for HFXOX2. + - em_gpio: Using single cycle set and clear of DOUT on platforms + where this is supported. + - em_lesense: Added configuration of DACCHnEN and DACSTARTUP bits in + LESENSE->PERCTRL in LESENSE_Init() and init struct. Also changed + default values for LESENSE_AltExDesc_TypeDef and + LESENSE_ChDesc_TypeDef to be disabled by default. + +5.1.3: + - No changes. + 5.1.2: Misc. bugfixes and improvements.
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_acmp.h
* @brief Analog Comparator (ACMP) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -95,8 +95,7 @@
/** Resistor values used for the internal capacative sense resistor. See the
* datasheet for your device for details on each resistor value. */
-typedef enum
-{
+typedef enum {
acmpResistor0 = _ACMP_INPUTSEL_CSRESSEL_RES0, /**< Resistor value 0 */
acmpResistor1 = _ACMP_INPUTSEL_CSRESSEL_RES1, /**< Resistor value 1 */
acmpResistor2 = _ACMP_INPUTSEL_CSRESSEL_RES2, /**< Resistor value 2 */
@@ -111,8 +110,7 @@
/** Hysteresis level. See datasheet for your device for details on each
* level. */
-typedef enum
-{
+typedef enum {
#if defined(_ACMP_CTRL_HYSTSEL_MASK)
acmpHysteresisLevel0 = _ACMP_CTRL_HYSTSEL_HYST0, /**< Hysteresis level 0 */
acmpHysteresisLevel1 = _ACMP_CTRL_HYSTSEL_HYST1, /**< Hysteresis level 1 */
@@ -146,8 +144,7 @@
#if defined(_ACMP_CTRL_WARMTIME_MASK)
/** ACMP warmup time. The delay is measured in HFPERCLK cycles and should
* be at least 10 us. */
-typedef enum
-{
+typedef enum {
/** 4 HFPERCLK cycles warmup */
acmpWarmTime4 = _ACMP_CTRL_WARMTIME_4CYCLES,
/** 8 HFPERCLK cycles warmup */
@@ -171,8 +168,7 @@
/**
* Adjust performance of the ACMP for a given input voltage range
*/
-typedef enum
-{
+typedef enum {
acmpInputRangeFull = _ACMP_CTRL_INPUTRANGE_FULL, /**< Input can be from 0 to Vdd */
acmpInputRangeHigh = _ACMP_CTRL_INPUTRANGE_GTVDDDIV2, /**< Input will always be greater than Vdd/2 */
acmpInputRangeLow = _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 /**< Input will always be less than Vdd/2 */
@@ -183,12 +179,11 @@
/**
* ACMP Power source.
*/
-typedef enum
-{
- acmpPowerSourceAvdd = _ACMP_CTRL_PWRSEL_AVDD, /**< Power the ACMP using the AVDD supply */
- acmpPowerSourceVddVreg = _ACMP_CTRL_PWRSEL_VREGVDD, /**< Power the ACMP using the VREGVDD supply */
- acmpPowerSourceIOVdd0 = _ACMP_CTRL_PWRSEL_IOVDD0, /**< Power the ACMP using the IOVDD/IOVDD0 supply */
- acmpPowerSourceIOVdd1 = _ACMP_CTRL_PWRSEL_IOVDD1, /**< Power the ACMP using the IOVDD1 supply (if part has two I/O voltages) */
+typedef enum {
+ acmpPowerSourceAvdd = _ACMP_CTRL_PWRSEL_AVDD, /**< Power the ACMP using the AVDD supply */
+ acmpPowerSourceVddVreg = _ACMP_CTRL_PWRSEL_VREGVDD, /**< Power the ACMP using the VREGVDD supply */
+ acmpPowerSourceIOVdd0 = _ACMP_CTRL_PWRSEL_IOVDD0, /**< Power the ACMP using the IOVDD/IOVDD0 supply */
+ acmpPowerSourceIOVdd1 = _ACMP_CTRL_PWRSEL_IOVDD1, /**< Power the ACMP using the IOVDD1 supply (if part has two I/O voltages) */
} ACMP_PowerSource_TypeDef;
#endif
@@ -196,8 +191,7 @@
/**
* ACMP accuracy mode.
*/
-typedef enum
-{
+typedef enum {
acmpAccuracyLow = _ACMP_CTRL_ACCURACY_LOW, /**< Low-accuracy mode but consume less current */
acmpAccuracyHigh = _ACMP_CTRL_ACCURACY_HIGH /**< High-accuracy mode but consume more current */
} ACMP_Accuracy_TypeDef;
@@ -206,8 +200,7 @@
#if defined(_ACMP_INPUTSEL_VASEL_MASK)
/** ACMP Input to the VA divider. This enum is used to select the input for
* the VA Divider */
-typedef enum
-{
+typedef enum {
acmpVAInputVDD = _ACMP_INPUTSEL_VASEL_VDD,
acmpVAInputAPORT2YCH0 = _ACMP_INPUTSEL_VASEL_APORT2YCH0,
acmpVAInputAPORT2YCH2 = _ACMP_INPUTSEL_VASEL_APORT2YCH2,
@@ -265,8 +258,7 @@
* ACMP Input to the VB divider. This enum is used to select the input for
* the VB divider.
*/
-typedef enum
-{
+typedef enum {
acmpVBInput1V25 = _ACMP_INPUTSEL_VBSEL_1V25,
acmpVBInput2V5 = _ACMP_INPUTSEL_VBSEL_2V5
} ACMP_VBInput_TypeDef;
@@ -276,8 +268,7 @@
/**
* ACMP Low-Power Input Selection.
*/
-typedef enum
-{
+typedef enum {
acmpVLPInputVADIV = _ACMP_INPUTSEL_VLPSEL_VADIV,
acmpVLPInputVBDIV = _ACMP_INPUTSEL_VLPSEL_VBDIV
} ACMP_VLPInput_Typedef;
@@ -285,8 +276,7 @@
#if defined(_ACMP_INPUTSEL_POSSEL_APORT0XCH0)
/** ACMP Input Selection */
-typedef enum
-{
+typedef enum {
acmpInputAPORT0XCH0 = _ACMP_INPUTSEL_POSSEL_APORT0XCH0,
acmpInputAPORT0XCH1 = _ACMP_INPUTSEL_POSSEL_APORT0XCH1,
acmpInputAPORT0XCH2 = _ACMP_INPUTSEL_POSSEL_APORT0XCH2,
@@ -462,8 +452,7 @@
#else
/** ACMP inputs. Note that scaled VDD and bandgap references can only be used
* as negative inputs. */
-typedef enum
-{
+typedef enum {
/** Channel 0 */
acmpChannel0 = _ACMP_INPUTSEL_NEGSEL_CH0,
/** Channel 1 */
@@ -510,8 +499,7 @@
* used by an external module like LESENSE when it's taking control over
* the ACMP input.
*/
-typedef enum
-{
+typedef enum {
acmpExternalInputAPORT0X = _ACMP_EXTIFCTRL_APORTSEL_APORT0X,
acmpExternalInputAPORT0Y = _ACMP_EXTIFCTRL_APORTSEL_APORT0Y,
acmpExternalInputAPORT1X = _ACMP_EXTIFCTRL_APORTSEL_APORT1X,
@@ -534,8 +522,7 @@
******************************************************************************/
/** Capsense initialization structure. */
-typedef struct
-{
+typedef struct {
/** Full bias current. See the ACMP chapter about bias and response time in
* the reference manual for details. */
bool fullBias;
@@ -607,47 +594,46 @@
/** Default config for capacitive sense mode initialization. */
#if defined(_ACMP_HYSTERESIS0_HYST_MASK)
-#define ACMP_CAPSENSE_INIT_DEFAULT \
-{ \
- false, /* Don't use fullBias to lower power consumption */ \
- 0x20, /* Using biasProg value of 0x20 (32) */ \
- acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 0 */ \
- acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 1 */ \
- acmpResistor5, /* Use internal resistor value 5 */ \
- 0x30, /* VDD level high */ \
- 0x10, /* VDD level low */ \
- true /* Enable after init. */ \
-}
+#define ACMP_CAPSENSE_INIT_DEFAULT \
+ { \
+ false, /* Don't use fullBias to lower power consumption */ \
+ 0x20, /* Using biasProg value of 0x20 (32) */ \
+ acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 0 */ \
+ acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 1 */ \
+ acmpResistor5, /* Use internal resistor value 5 */ \
+ 0x30, /* VDD level high */ \
+ 0x10, /* VDD level low */ \
+ true /* Enable after init. */ \
+ }
#elif defined(_ACMP_CTRL_WARMTIME_MASK)
#define ACMP_CAPSENSE_INIT_DEFAULT \
-{ \
- false, /* fullBias */ \
- false, /* halfBias */ \
- 0x7, /* biasProg */ \
- acmpWarmTime512, /* 512 cycle warmup to be safe */ \
- acmpHysteresisLevel5, \
- acmpResistor3, \
- false, /* low power reference */ \
- 0x3D, /* VDD level */ \
- true /* Enable after init. */ \
-}
+ { \
+ false, /* fullBias */ \
+ false, /* halfBias */ \
+ 0x7, /* biasProg */ \
+ acmpWarmTime512, /* 512 cycle warmup to be safe */ \
+ acmpHysteresisLevel5, \
+ acmpResistor3, \
+ false, /* low power reference */ \
+ 0x3D, /* VDD level */ \
+ true /* Enable after init. */ \
+ }
#else
-#define ACMP_CAPSENSE_INIT_DEFAULT \
-{ \
- false, /* fullBias */ \
- false, /* halfBias */ \
- 0x7, /* biasProg */ \
- acmpHysteresisLevel5, \
- acmpResistor3, \
- false, /* low power reference */ \
- 0x3D, /* VDD level */ \
- true /* Enable after init. */ \
-}
+#define ACMP_CAPSENSE_INIT_DEFAULT \
+ { \
+ false, /* fullBias */ \
+ false, /* halfBias */ \
+ 0x7, /* biasProg */ \
+ acmpHysteresisLevel5, \
+ acmpResistor3, \
+ false, /* low power reference */ \
+ 0x3D, /* VDD level */ \
+ true /* Enable after init. */ \
+ }
#endif
/** ACMP initialization structure. */
-typedef struct
-{
+typedef struct {
/** Full bias current. See the ACMP chapter about bias and response time in
* the reference manual for details. */
bool fullBias;
@@ -731,56 +717,55 @@
/** Default config for ACMP regular initialization. */
#if defined(_ACMP_HYSTERESIS0_HYST_MASK)
#define ACMP_INIT_DEFAULT \
-{ \
- false, /* fullBias */ \
- 0x7, /* biasProg */ \
- false, /* No interrupt on falling edge. */ \
- false, /* No interrupt on rising edge. */ \
- acmpInputRangeFull, /* Input range from 0 to Vdd. */ \
- acmpAccuracyLow, /* Low accuracy, less current usage. */ \
- acmpPowerSourceAvdd, /* Use the AVDD supply. */ \
- acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 0 */ \
- acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 1 */ \
- acmpVLPInputVADIV, /* Use VADIV as the VLP input source. */ \
- false, /* Output 0 when ACMP is inactive. */ \
- true /* Enable after init. */ \
-}
+ { \
+ false, /* fullBias */ \
+ 0x7, /* biasProg */ \
+ false, /* No interrupt on falling edge. */ \
+ false, /* No interrupt on rising edge. */ \
+ acmpInputRangeFull, /* Input range from 0 to Vdd. */ \
+ acmpAccuracyLow, /* Low accuracy, less current usage. */ \
+ acmpPowerSourceAvdd, /* Use the AVDD supply. */ \
+ acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 0 */ \
+ acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 1 */ \
+ acmpVLPInputVADIV, /* Use VADIV as the VLP input source. */ \
+ false, /* Output 0 when ACMP is inactive. */ \
+ true /* Enable after init. */ \
+ }
#elif defined(_ACMP_CTRL_WARMTIME_MASK)
#define ACMP_INIT_DEFAULT \
-{ \
- false, /* fullBias */ \
- false, /* halfBias */ \
- 0x7, /* biasProg */ \
- false, /* No interrupt on falling edge. */ \
- false, /* No interrupt on rising edge. */ \
- acmpWarmTime512, /* 512 cycle warmup to be safe */ \
- acmpHysteresisLevel5, \
- false, /* Disabled emitting inactive value during warmup. */ \
- false, /* low power reference */ \
- 0x3D, /* VDD level */ \
- true /* Enable after init. */ \
-}
+ { \
+ false, /* fullBias */ \
+ false, /* halfBias */ \
+ 0x7, /* biasProg */ \
+ false, /* No interrupt on falling edge. */ \
+ false, /* No interrupt on rising edge. */ \
+ acmpWarmTime512, /* 512 cycle warmup to be safe */ \
+ acmpHysteresisLevel5, \
+ false, /* Disabled emitting inactive value during warmup. */ \
+ false, /* low power reference */ \
+ 0x3D, /* VDD level */ \
+ true /* Enable after init. */ \
+ }
#else
#define ACMP_INIT_DEFAULT \
-{ \
- false, /* fullBias */ \
- false, /* halfBias */ \
- 0x7, /* biasProg */ \
- false, /* No interrupt on falling edge. */ \
- false, /* No interrupt on rising edge. */ \
- acmpHysteresisLevel5, \
- false, /* Disabled emitting inactive value during warmup. */ \
- false, /* low power reference */ \
- 0x3D, /* VDD level */ \
- true /* Enable after init. */ \
-}
+ { \
+ false, /* fullBias */ \
+ false, /* halfBias */ \
+ 0x7, /* biasProg */ \
+ false, /* No interrupt on falling edge. */ \
+ false, /* No interrupt on rising edge. */ \
+ acmpHysteresisLevel5, \
+ false, /* Disabled emitting inactive value during warmup. */ \
+ false, /* low power reference */ \
+ 0x3D, /* VDD level */ \
+ true /* Enable after init. */ \
+ }
#endif
#if defined(_ACMP_INPUTSEL_VASEL_MASK)
/** VA Configuration structure. This struct is used to configure the
* VA voltage input source and it's dividers. */
-typedef struct
-{
+typedef struct {
ACMP_VAInput_TypeDef input; /**< VA voltage input source */
/**
@@ -802,19 +787,18 @@
uint32_t div1;
} ACMP_VAConfig_TypeDef;
-#define ACMP_VACONFIG_DEFAULT \
-{ \
- acmpVAInputVDD, /* Use Vdd as VA voltage input source */ \
- 63, /* No division of the VA source when ACMP output is 0 */ \
- 63, /* No division of the VA source when ACMP output is 1 */ \
-}
+#define ACMP_VACONFIG_DEFAULT \
+ { \
+ acmpVAInputVDD, /* Use Vdd as VA voltage input source */ \
+ 63, /* No division of the VA source when ACMP output is 0 */ \
+ 63, /* No division of the VA source when ACMP output is 1 */ \
+ }
#endif
#if defined(_ACMP_INPUTSEL_VBSEL_MASK)
/** VB Configuration structure. This struct is used to configure the
* VB voltage input source and it's dividers. */
-typedef struct
-{
+typedef struct {
ACMP_VBInput_TypeDef input; /**< VB Voltage input source */
/**
@@ -837,11 +821,11 @@
} ACMP_VBConfig_TypeDef;
#define ACMP_VBCONFIG_DEFAULT \
-{ \
- acmpVBInput1V25, /* Use 1.25 V as VB voltage input source */ \
- 63, /* No division of the VB source when ACMP output is 0 */ \
- 63, /* No division of the VB source when ACMP output is 1 */ \
-}
+ { \
+ acmpVBInput1V25, /* Use 1.25 V as VB voltage input source */ \
+ 63, /* No division of the VB source when ACMP output is 0 */ \
+ 63, /* No division of the VB source when ACMP output is 1 */ \
+ }
#endif
/*******************************************************************************
@@ -883,7 +867,6 @@
acmp->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more ACMP interrupts.
@@ -901,7 +884,6 @@
acmp->IEN &= ~(flags);
}
-
/***************************************************************************//**
* @brief
* Enable one or more ACMP interrupts.
@@ -924,7 +906,6 @@
acmp->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending ACMP interrupt flags.
@@ -945,7 +926,6 @@
return acmp->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending ACMP interrupt flags.
@@ -977,7 +957,6 @@
return acmp->IF & tmp;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending ACMP interrupts from SW.
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_adc.h
* @brief Analog to Digital Converter (ADC) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -34,7 +34,7 @@
#define EM_ADC_H
#include "em_device.h"
-#if defined( ADC_COUNT ) && ( ADC_COUNT > 0 )
+#if defined(ADC_COUNT) && (ADC_COUNT > 0)
#include <stdbool.h>
@@ -57,8 +57,7 @@
******************************************************************************/
/** Acquisition time (in ADC clock cycles). */
-typedef enum
-{
+typedef enum {
adcAcqTime1 = _ADC_SINGLECTRL_AT_1CYCLE, /**< 1 clock cycle. */
adcAcqTime2 = _ADC_SINGLECTRL_AT_2CYCLES, /**< 2 clock cycles. */
adcAcqTime4 = _ADC_SINGLECTRL_AT_4CYCLES, /**< 4 clock cycles. */
@@ -70,10 +69,9 @@
adcAcqTime256 = _ADC_SINGLECTRL_AT_256CYCLES /**< 256 clock cycles. */
} ADC_AcqTime_TypeDef;
-#if defined( _ADC_CTRL_LPFMODE_MASK )
+#if defined(_ADC_CTRL_LPFMODE_MASK)
/** Lowpass filter mode. */
-typedef enum
-{
+typedef enum {
/** No filter or decoupling capacitor. */
adcLPFilterBypass = _ADC_CTRL_LPFMODE_BYPASS,
@@ -86,8 +84,7 @@
#endif
/** Oversample rate select. */
-typedef enum
-{
+typedef enum {
/** 2 samples per conversion result. */
adcOvsRateSel2 = _ADC_CTRL_OVSRSEL_X2,
@@ -125,37 +122,35 @@
adcOvsRateSel4096 = _ADC_CTRL_OVSRSEL_X4096
} ADC_OvsRateSel_TypeDef;
-
/** Peripheral Reflex System signal used to trigger single sample. */
-typedef enum
-{
-#if defined( _ADC_SINGLECTRL_PRSSEL_MASK )
+typedef enum {
+#if defined(_ADC_SINGLECTRL_PRSSEL_MASK)
adcPRSSELCh0 = _ADC_SINGLECTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
adcPRSSELCh1 = _ADC_SINGLECTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
adcPRSSELCh2 = _ADC_SINGLECTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
adcPRSSELCh3 = _ADC_SINGLECTRL_PRSSEL_PRSCH3, /**< PRS channel 3. */
-#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH4 )
+#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH4)
adcPRSSELCh4 = _ADC_SINGLECTRL_PRSSEL_PRSCH4, /**< PRS channel 4. */
#endif
-#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH5 )
+#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH5)
adcPRSSELCh5 = _ADC_SINGLECTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */
#endif
-#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH6 )
+#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH6)
adcPRSSELCh6 = _ADC_SINGLECTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */
#endif
-#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH7 )
+#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH7)
adcPRSSELCh7 = _ADC_SINGLECTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */
#endif
-#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH8 )
+#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH8)
adcPRSSELCh8 = _ADC_SINGLECTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */
#endif
-#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH9 )
+#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH9)
adcPRSSELCh9 = _ADC_SINGLECTRL_PRSSEL_PRSCH9, /**< PRS channel 9. */
#endif
-#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH10 )
+#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH10)
adcPRSSELCh10 = _ADC_SINGLECTRL_PRSSEL_PRSCH10, /**< PRS channel 10. */
#endif
-#if defined( _ADC_SINGLECTRL_PRSSEL_PRSCH11 )
+#if defined(_ADC_SINGLECTRL_PRSSEL_PRSCH11)
adcPRSSELCh11 = _ADC_SINGLECTRL_PRSSEL_PRSCH11, /**< PRS channel 11. */
#endif
#elif defined(_ADC_SINGLECTRLX_PRSSEL_MASK)
@@ -167,11 +162,19 @@
adcPRSSELCh5 = _ADC_SINGLECTRLX_PRSSEL_PRSCH5, /**< PRS channel 5. */
adcPRSSELCh6 = _ADC_SINGLECTRLX_PRSSEL_PRSCH6, /**< PRS channel 6. */
adcPRSSELCh7 = _ADC_SINGLECTRLX_PRSSEL_PRSCH7, /**< PRS channel 7. */
+#if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH8)
adcPRSSELCh8 = _ADC_SINGLECTRLX_PRSSEL_PRSCH8, /**< PRS channel 8. */
+#endif
+#if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH9)
adcPRSSELCh9 = _ADC_SINGLECTRLX_PRSSEL_PRSCH9, /**< PRS channel 9. */
+#endif
+#if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH10)
adcPRSSELCh10 = _ADC_SINGLECTRLX_PRSSEL_PRSCH10, /**< PRS channel 10. */
+#endif
+#if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH11)
adcPRSSELCh11 = _ADC_SINGLECTRLX_PRSSEL_PRSCH11, /**< PRS channel 11. */
-#if defined( _ADC_SINGLECTRLX_PRSSEL_PRSCH12 )
+#endif
+#if defined(_ADC_SINGLECTRLX_PRSSEL_PRSCH12)
adcPRSSELCh12 = _ADC_SINGLECTRLX_PRSSEL_PRSCH12, /**< PRS channel 12. */
adcPRSSELCh13 = _ADC_SINGLECTRLX_PRSSEL_PRSCH13, /**< PRS channel 13. */
adcPRSSELCh14 = _ADC_SINGLECTRLX_PRSSEL_PRSCH14, /**< PRS channel 14. */
@@ -180,14 +183,12 @@
#endif
} ADC_PRSSEL_TypeDef;
-
/** Single and scan mode voltage references. Using unshifted enums and or
in ADC_CTRLX_VREFSEL_REG to select the extension register CTRLX_VREFSEL. */
-#if defined( _ADC_SCANCTRLX_VREFSEL_MASK )
+#if defined(_ADC_SCANCTRLX_VREFSEL_MASK)
#define ADC_CTRLX_VREFSEL_REG 0x80
#endif
-typedef enum
-{
+typedef enum {
/** Internal 1.25V reference. */
adcRef1V25 = _ADC_SINGLECTRL_REF_1V25,
@@ -197,12 +198,12 @@
/** Buffered VDD. */
adcRefVDD = _ADC_SINGLECTRL_REF_VDD,
-#if defined( _ADC_SINGLECTRL_REF_5VDIFF )
+#if defined(_ADC_SINGLECTRL_REF_5VDIFF)
/** Internal differential 5V reference. */
adcRef5VDIFF = _ADC_SINGLECTRL_REF_5VDIFF,
#endif
-#if defined( _ADC_SINGLECTRL_REF_5V )
+#if defined(_ADC_SINGLECTRL_REF_5V)
/** Internal 5V reference. */
adcRef5V = _ADC_SINGLECTRL_REF_5V,
#endif
@@ -216,39 +217,39 @@
/** Unbuffered 2xVDD. */
adcRef2xVDD = _ADC_SINGLECTRL_REF_2XVDD,
-#if defined( _ADC_SINGLECTRLX_VREFSEL_VBGR )
+#if defined(_ADC_SINGLECTRLX_VREFSEL_VBGR)
/** Custom VFS: Internal Bandgap reference */
adcRefVBGR = _ADC_SINGLECTRLX_VREFSEL_VBGR | ADC_CTRLX_VREFSEL_REG,
#endif
-#if defined( _ADC_SINGLECTRLX_VREFSEL_VDDXWATT )
+#if defined(_ADC_SINGLECTRLX_VREFSEL_VDDXWATT)
/** Custom VFS: Scaled AVDD: AVDD * VREFATT */
adcRefVddxAtt = _ADC_SINGLECTRLX_VREFSEL_VDDXWATT | ADC_CTRLX_VREFSEL_REG,
#endif
-#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPWATT )
+#if defined(_ADC_SINGLECTRLX_VREFSEL_VREFPWATT)
/** Custom VFS: Scaled singled ended external reference from pin 6:
VREFP * VREFATT */
adcRefVPxAtt = _ADC_SINGLECTRLX_VREFSEL_VREFPWATT | ADC_CTRLX_VREFSEL_REG,
#endif
-#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFP )
+#if defined(_ADC_SINGLECTRLX_VREFSEL_VREFP)
/** Custom VFS: Raw single ended external reference from pin 6. */
adcRefP = _ADC_SINGLECTRLX_VREFSEL_VREFP | ADC_CTRLX_VREFSEL_REG,
#endif
-#if defined( _ADC_SINGLECTRLX_VREFSEL_VENTROPY )
+#if defined(_ADC_SINGLECTRLX_VREFSEL_VENTROPY)
/** Custom VFS: Special mode for entropy generation */
adcRefVEntropy = _ADC_SINGLECTRLX_VREFSEL_VENTROPY | ADC_CTRLX_VREFSEL_REG,
#endif
-#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT )
+#if defined(_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT)
/** Custom VFS: Scaled differential external Vref from pin 6 and 7:
(VREFP - VREFN) * VREFATT */
adcRefVPNxAtt = _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT | ADC_CTRLX_VREFSEL_REG,
#endif
-#if defined( _ADC_SINGLECTRLX_VREFSEL_VREFPN )
+#if defined(_ADC_SINGLECTRLX_VREFSEL_VREFPN)
/** Custom VFS: Raw differential external Vref from pin 6 and 7:
VREFP - VREFN */
adcRefPN = _ADC_SINGLECTRLX_VREFSEL_VREFPN | ADC_CTRLX_VREFSEL_REG,
@@ -257,26 +258,22 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/* Deprecated enum names */
-#if !defined( _ADC_SINGLECTRL_REF_5VDIFF )
+#if !defined(_ADC_SINGLECTRL_REF_5VDIFF)
#define adcRef5VDIFF adcRef5V
#endif
/** @endcond */
-
/** Sample resolution. */
-typedef enum
-{
+typedef enum {
adcRes12Bit = _ADC_SINGLECTRL_RES_12BIT, /**< 12 bit sampling. */
adcRes8Bit = _ADC_SINGLECTRL_RES_8BIT, /**< 8 bit sampling. */
adcRes6Bit = _ADC_SINGLECTRL_RES_6BIT, /**< 6 bit sampling. */
adcResOVS = _ADC_SINGLECTRL_RES_OVS /**< Oversampling. */
} ADC_Res_TypeDef;
-
-#if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
+#if defined(_ADC_SINGLECTRL_INPUTSEL_MASK)
/** Single sample input selection. */
-typedef enum
-{
+typedef enum {
/* Differential mode disabled */
adcSingleInputCh0 = _ADC_SINGLECTRL_INPUTSEL_CH0, /**< Channel 0. */
adcSingleInputCh1 = _ADC_SINGLECTRL_INPUTSEL_CH1, /**< Channel 1. */
@@ -329,10 +326,9 @@
/** @endcond */
#endif
-#if defined( _ADC_SINGLECTRL_POSSEL_MASK )
+#if defined(_ADC_SINGLECTRL_POSSEL_MASK)
/** Positive input selection for single and scan coversion. */
-typedef enum
-{
+typedef enum {
adcPosSelAPORT0XCH0 = _ADC_SINGLECTRL_POSSEL_APORT0XCH0,
adcPosSelAPORT0XCH1 = _ADC_SINGLECTRL_POSSEL_APORT0XCH1,
adcPosSelAPORT0XCH2 = _ADC_SINGLECTRL_POSSEL_APORT0XCH2,
@@ -494,6 +490,9 @@
adcPosSelAPORT4YCH30 = _ADC_SINGLECTRL_POSSEL_APORT4YCH30,
adcPosSelAPORT4XCH31 = _ADC_SINGLECTRL_POSSEL_APORT4XCH31,
adcPosSelAVDD = _ADC_SINGLECTRL_POSSEL_AVDD,
+#if defined(_ADC_SINGLECTRL_POSSEL_BU)
+ adcPosSelBUVDD = _ADC_SINGLECTRL_POSSEL_BU,
+#endif
adcPosSelDVDD = _ADC_SINGLECTRL_POSSEL_AREG,
adcPosSelPAVDD = _ADC_SINGLECTRL_POSSEL_VREGOUTPA,
adcPosSelDECOUPLE = _ADC_SINGLECTRL_POSSEL_PDBU,
@@ -513,14 +512,11 @@
#define adcPosSelVREGOUTPA adcPosSelPAVDD
#define adcPosSelAREG adcPosSelDVDD
#define adcPosSelPDBU adcPosSelDECOUPLE
-
#endif
-
-#if defined( _ADC_SINGLECTRL_NEGSEL_MASK )
+#if defined(_ADC_SINGLECTRL_NEGSEL_MASK)
/** Negative input selection for single and scan coversion. */
-typedef enum
-{
+typedef enum {
adcNegSelAPORT0XCH0 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH0,
adcNegSelAPORT0XCH1 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH1,
adcNegSelAPORT0XCH2 = _ADC_SINGLECTRL_NEGSEL_APORT0XCH2,
@@ -687,11 +683,9 @@
} ADC_NegSel_TypeDef;
#endif
-
-#if defined( _ADC_SCANINPUTSEL_MASK )
- /* ADC scan input groups */
-typedef enum
-{
+#if defined(_ADC_SCANINPUTSEL_MASK)
+/* ADC scan input groups */
+typedef enum {
adcScanInputGroup0 = 0,
adcScanInputGroup1 = 1,
adcScanInputGroup2 = 2,
@@ -700,18 +694,17 @@
/* Define none selected for ADC_SCANINPUTSEL */
#define ADC_SCANINPUTSEL_GROUP_NONE 0xFFU
-#define ADC_SCANINPUTSEL_NONE ((ADC_SCANINPUTSEL_GROUP_NONE \
- << _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT) \
- | (ADC_SCANINPUTSEL_GROUP_NONE \
- << _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT) \
- | (ADC_SCANINPUTSEL_GROUP_NONE \
- << _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT) \
- | (ADC_SCANINPUTSEL_GROUP_NONE \
+#define ADC_SCANINPUTSEL_NONE ((ADC_SCANINPUTSEL_GROUP_NONE \
+ << _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT) \
+ | (ADC_SCANINPUTSEL_GROUP_NONE \
+ << _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT) \
+ | (ADC_SCANINPUTSEL_GROUP_NONE \
+ << _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT) \
+ | (ADC_SCANINPUTSEL_GROUP_NONE \
<< _ADC_SCANINPUTSEL_INPUT24TO31SEL_SHIFT))
- /* ADC scan alternative negative inputs */
-typedef enum
-{
+/* ADC scan alternative negative inputs */
+typedef enum {
adcScanNegInput1 = 1,
adcScanNegInput3 = 3,
adcScanNegInput5 = 5,
@@ -724,10 +717,8 @@
} ADC_ScanNegInput_TypeDef;
#endif
-
/** ADC Start command. */
-typedef enum
-{
+typedef enum {
/** Start single conversion. */
adcStartSingle = ADC_CMD_SINGLESTART,
@@ -741,30 +732,28 @@
adcStartScanAndSingle = ADC_CMD_SCANSTART | ADC_CMD_SINGLESTART
} ADC_Start_TypeDef;
-
/** Warm-up mode. */
-typedef enum
-{
+typedef enum {
/** ADC shutdown after each conversion. */
adcWarmupNormal = _ADC_CTRL_WARMUPMODE_NORMAL,
-#if defined( _ADC_CTRL_WARMUPMODE_FASTBG )
+#if defined(_ADC_CTRL_WARMUPMODE_FASTBG)
/** Do not warm-up bandgap references. */
adcWarmupFastBG = _ADC_CTRL_WARMUPMODE_FASTBG,
#endif
-#if defined( _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM )
+#if defined(_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM)
/** Reference selected for scan mode kept warm.*/
adcWarmupKeepScanRefWarm = _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM,
#endif
-#if defined( _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY )
+#if defined(_ADC_CTRL_WARMUPMODE_KEEPINSTANDBY)
/** ADC is kept in standby mode between conversion. 1us warmup time needed
before next conversion. */
adcWarmupKeepInStandby = _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY,
#endif
-#if defined( _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC )
+#if defined(_ADC_CTRL_WARMUPMODE_KEEPINSLOWACC)
/** ADC is kept in slow acquisition mode between conversions. 1us warmup
time needed before next conversion. */
adcWarmupKeepInSlowAcq = _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC,
@@ -773,35 +762,30 @@
/** ADC and reference selected for scan mode kept warmup, allowing
continuous conversion. */
adcWarmupKeepADCWarm = _ADC_CTRL_WARMUPMODE_KEEPADCWARM,
-
} ADC_Warmup_TypeDef;
-
-#if defined( _ADC_CTRL_ADCCLKMODE_MASK )
- /** ADC EM2 clock configuration */
-typedef enum
-{
+#if defined(_ADC_CTRL_ADCCLKMODE_MASK)
+/** ADC EM2 clock configuration */
+typedef enum {
adcEm2Disabled = 0,
adcEm2ClockOnDemand = ADC_CTRL_ADCCLKMODE_ASYNC | ADC_CTRL_ASYNCCLKEN_ASNEEDED,
adcEm2ClockAlwaysOn = ADC_CTRL_ADCCLKMODE_ASYNC | ADC_CTRL_ASYNCCLKEN_ALWAYSON,
} ADC_EM2ClockConfig_TypeDef;
#endif
-
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** ADC init structure, common for single conversion and scan sequence. */
-typedef struct
-{
+typedef struct {
/**
* Oversampling rate select. In order to have any effect, oversampling must
* be enabled for single/scan mode.
*/
ADC_OvsRateSel_TypeDef ovsRateSel;
-#if defined( _ADC_CTRL_LPFMODE_MASK )
+#if defined(_ADC_CTRL_LPFMODE_MASK)
/** Lowpass or decoupling capacitor filter to use. */
ADC_LPFilter_TypeDef lpfMode;
#endif
@@ -825,48 +809,45 @@
bool tailgate;
/** ADC EM2 clock configuration */
-#if defined( _ADC_CTRL_ADCCLKMODE_MASK )
+#if defined(_ADC_CTRL_ADCCLKMODE_MASK)
ADC_EM2ClockConfig_TypeDef em2ClockConfig;
#endif
} ADC_Init_TypeDef;
-
/** Default config for ADC init structure. */
-#if defined( _ADC_CTRL_LPFMODE_MASK ) && (!defined( _ADC_CTRL_ADCCLKMODE_MASK ))
-#define ADC_INIT_DEFAULT \
-{ \
- adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
- adcLPFilterBypass, /* No input filter selected. */ \
- adcWarmupNormal, /* ADC shutdown after each conversion. */ \
- _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
- _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
- false /* Do not use tailgate. */ \
-}
-#elif (!defined( _ADC_CTRL_LPFMODE_MASK )) && (!defined( _ADC_CTRL_ADCCLKMODE_MASK ))
-#define ADC_INIT_DEFAULT \
-{ \
- adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
- adcWarmupNormal, /* ADC shutdown after each conversion. */ \
- _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
- _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
- false /* Do not use tailgate. */ \
-}
-#elif (!defined( _ADC_CTRL_LPFMODE_MASK )) && defined( _ADC_CTRL_ADCCLKMODE_MASK )
-#define ADC_INIT_DEFAULT \
-{ \
- adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
- adcWarmupNormal, /* ADC shutdown after each conversion. */ \
- _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
- _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
- false, /* Do not use tailgate. */ \
- adcEm2Disabled /* ADC disabled in EM2 */ \
-}
+#if defined(_ADC_CTRL_LPFMODE_MASK) && (!defined(_ADC_CTRL_ADCCLKMODE_MASK))
+#define ADC_INIT_DEFAULT \
+ { \
+ adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
+ adcLPFilterBypass, /* No input filter selected. */ \
+ adcWarmupNormal, /* ADC shutdown after each conversion. */ \
+ _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
+ _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
+ false /* Do not use tailgate. */ \
+ }
+#elif (!defined(_ADC_CTRL_LPFMODE_MASK)) && (!defined(_ADC_CTRL_ADCCLKMODE_MASK))
+#define ADC_INIT_DEFAULT \
+ { \
+ adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
+ adcWarmupNormal, /* ADC shutdown after each conversion. */ \
+ _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
+ _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
+ false /* Do not use tailgate. */ \
+ }
+#elif (!defined(_ADC_CTRL_LPFMODE_MASK)) && defined(_ADC_CTRL_ADCCLKMODE_MASK)
+#define ADC_INIT_DEFAULT \
+ { \
+ adcOvsRateSel2, /* 2x oversampling (if enabled). */ \
+ adcWarmupNormal, /* ADC shutdown after each conversion. */ \
+ _ADC_CTRL_TIMEBASE_DEFAULT, /* Use HW default value. */ \
+ _ADC_CTRL_PRESC_DEFAULT, /* Use HW default value. */ \
+ false, /* Do not use tailgate. */ \
+ adcEm2Disabled /* ADC disabled in EM2 */ \
+ }
#endif
-
/** Scan input configuration */
-typedef struct
-{
+typedef struct {
/** Input range select to be applied to ADC_SCANINPUTSEL. */
uint32_t scanInputSel;
@@ -877,10 +858,8 @@
uint32_t scanNegSel;
} ADC_InitScanInput_TypeDef;
-
/** Scan sequence init structure. */
-typedef struct
-{
+typedef struct {
/**
* Peripheral reflex system trigger selection. Only applicable if @p prsEnable
* is enabled.
@@ -899,7 +878,7 @@
/** Sample resolution. */
ADC_Res_TypeDef resolution;
-#if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
+#if defined(_ADC_SCANCTRL_INPUTMASK_MASK)
/**
* Scan input selection. If single ended (@p diff is false), use logical
* combination of ADC_SCANCTRL_INPUTMASK_CHx defines. If differential input
@@ -909,7 +888,7 @@
uint32_t input;
#endif
-#if defined( _ADC_SCANINPUTSEL_MASK )
+#if defined(_ADC_SCANINPUTSEL_MASK)
/**
* Scan input configuration. @ref Use ADC_ScanInputClear(), @ref ADC_ScanSingleEndedInputAdd()
* or @ref ADC_ScanDifferentialInputAdd() to update this struct.
@@ -930,11 +909,11 @@
bool rep;
/** When true, DMA is available in EM2 for scan conversion */
-#if defined( _ADC_CTRL_SCANDMAWU_MASK )
+#if defined(_ADC_CTRL_SCANDMAWU_MASK)
bool scanDmaEm2Wu;
#endif
-#if defined( _ADC_SCANCTRLX_FIFOOFACT_MASK )
+#if defined(_ADC_SCANCTRLX_FIFOOFACT_MASK)
/** When true, the FIFO overwrites old data when full. If false, then the FIFO discards new data.
The SINGLEOF IRQ is triggered in both cases. */
bool fifoOverwrite;
@@ -942,47 +921,45 @@
} ADC_InitScan_TypeDef;
/** Default config for ADC scan init structure. */
-#if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
+#if defined(_ADC_SCANCTRL_INPUTMASK_MASK)
#define ADC_INITSCAN_DEFAULT \
-{ \
- adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
- adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
- adcRef1V25, /* 1.25V internal reference. */ \
- adcRes12Bit, /* 12 bit resolution. */ \
- 0, /* No input selected. */ \
- false, /* Single-ended input. */ \
- false, /* PRS disabled. */ \
- false, /* Right adjust. */ \
- false, /* Deactivate conversion after one scan sequence. */ \
-}
+ { \
+ adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
+ adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
+ adcRef1V25, /* 1.25V internal reference. */ \
+ adcRes12Bit, /* 12 bit resolution. */ \
+ 0, /* No input selected. */ \
+ false, /* Single-ended input. */ \
+ false, /* PRS disabled. */ \
+ false, /* Right adjust. */ \
+ false, /* Deactivate conversion after one scan sequence. */ \
+ }
#endif
-#if defined( _ADC_SCANINPUTSEL_MASK )
-#define ADC_INITSCAN_DEFAULT \
-{ \
- adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
- adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
- adcRef1V25, /* 1.25V internal reference. */ \
- adcRes12Bit, /* 12 bit resolution. */ \
- { \
- /* Initialization should match values set by @ref ADC_ScanInputClear() */ \
- ADC_SCANINPUTSEL_NONE, /* Default ADC inputs */ \
- 0, /* Default input mask (all off) */ \
- _ADC_SCANNEGSEL_RESETVALUE,/* Default negative select for positive ternimal */\
- }, \
- false, /* Single-ended input. */ \
- false, /* PRS disabled. */ \
- false, /* Right adjust. */ \
- false, /* Deactivate conversion after one scan sequence. */ \
- false, /* No EM2 DMA wakeup from scan FIFO DVL */ \
- false /* Discard new data on full FIFO. */ \
-}
+#if defined(_ADC_SCANINPUTSEL_MASK)
+#define ADC_INITSCAN_DEFAULT \
+ { \
+ adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
+ adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
+ adcRef1V25, /* 1.25V internal reference. */ \
+ adcRes12Bit, /* 12 bit resolution. */ \
+ { \
+ /* Initialization should match values set by @ref ADC_ScanInputClear() */ \
+ ADC_SCANINPUTSEL_NONE, /* Default ADC inputs */ \
+ 0, /* Default input mask (all off) */ \
+ _ADC_SCANNEGSEL_RESETVALUE,/* Default negative select for positive ternimal */ \
+ }, \
+ false, /* Single-ended input. */ \
+ false, /* PRS disabled. */ \
+ false, /* Right adjust. */ \
+ false, /* Deactivate conversion after one scan sequence. */ \
+ false, /* No EM2 DMA wakeup from scan FIFO DVL */ \
+ false /* Discard new data on full FIFO. */ \
+ }
#endif
-
/** Single conversion init structure. */
-typedef struct
-{
+typedef struct {
/**
* Peripheral reflex system trigger selection. Only applicable if @p prsEnable
* is enabled.
@@ -1001,7 +978,7 @@
/** Sample resolution. */
ADC_Res_TypeDef resolution;
-#if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
+#if defined(_ADC_SINGLECTRL_INPUTSEL_MASK)
/**
* Sample input selection, use single ended or differential input according
* to setting of @p diff.
@@ -1009,12 +986,12 @@
ADC_SingleInput_TypeDef input;
#endif
-#if defined( _ADC_SINGLECTRL_POSSEL_MASK )
+#if defined(_ADC_SINGLECTRL_POSSEL_MASK)
/** Select positive input for for single channel conversion mode. */
ADC_PosSel_TypeDef posSel;
#endif
-#if defined( _ADC_SINGLECTRL_NEGSEL_MASK )
+#if defined(_ADC_SINGLECTRL_NEGSEL_MASK)
/** Select negative input for single channel conversion mode. Negative input is grounded
for single ended (non-differential) converison. */
ADC_NegSel_TypeDef negSel;
@@ -1032,12 +1009,12 @@
/** Select if continuous conversion until explicit stop. */
bool rep;
-#if defined( _ADC_CTRL_SINGLEDMAWU_MASK )
+#if defined(_ADC_CTRL_SINGLEDMAWU_MASK)
/** When true, DMA is available in EM2 for single conversion */
bool singleDmaEm2Wu;
#endif
-#if defined( _ADC_SINGLECTRLX_FIFOOFACT_MASK )
+#if defined(_ADC_SINGLECTRLX_FIFOOFACT_MASK)
/** When true, the FIFO overwrites old data when full. If false, then the FIFO discards new data.
The SCANOF IRQ is triggered in both cases. */
bool fifoOverwrite;
@@ -1045,35 +1022,35 @@
} ADC_InitSingle_TypeDef;
/** Default config for ADC single conversion init structure. */
-#if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
+#if defined(_ADC_SINGLECTRL_INPUTSEL_MASK)
#define ADC_INITSINGLE_DEFAULT \
-{ \
- adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
- adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
- adcRef1V25, /* 1.25V internal reference. */ \
- adcRes12Bit, /* 12 bit resolution. */ \
- adcSingleInpCh0, /* CH0 input selected. */ \
- false, /* Single ended input. */ \
- false, /* PRS disabled. */ \
- false, /* Right adjust. */ \
- false /* Deactivate conversion after one scan sequence. */ \
-}
+ { \
+ adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
+ adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
+ adcRef1V25, /* 1.25V internal reference. */ \
+ adcRes12Bit, /* 12 bit resolution. */ \
+ adcSingleInpCh0, /* CH0 input selected. */ \
+ false, /* Single ended input. */ \
+ false, /* PRS disabled. */ \
+ false, /* Right adjust. */ \
+ false /* Deactivate conversion after one scan sequence. */ \
+ }
#else
#define ADC_INITSINGLE_DEFAULT \
-{ \
- adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
- adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
- adcRef1V25, /* 1.25V internal reference. */ \
- adcRes12Bit, /* 12 bit resolution. */ \
- adcPosSelAPORT0XCH0, /* Select node BUS0XCH0 as posSel */ \
- adcNegSelVSS, /* Select VSS as negSel */ \
- false, /* Single ended input. */ \
- false, /* PRS disabled. */ \
- false, /* Right adjust. */ \
- false, /* Deactivate conversion after one scan sequence. */ \
- false, /* No EM2 DMA wakeup from single FIFO DVL */ \
- false /* Discard new data on full FIFO. */ \
-}
+ { \
+ adcPRSSELCh0, /* PRS ch0 (if enabled). */ \
+ adcAcqTime1, /* 1 ADC_CLK cycle acquisition time. */ \
+ adcRef1V25, /* 1.25V internal reference. */ \
+ adcRes12Bit, /* 12 bit resolution. */ \
+ adcPosSelAPORT0XCH0, /* Select node BUS0XCH0 as posSel */ \
+ adcNegSelVSS, /* Select VSS as negSel */ \
+ false, /* Single ended input. */ \
+ false, /* PRS disabled. */ \
+ false, /* Right adjust. */ \
+ false, /* Deactivate conversion after one scan sequence. */ \
+ false, /* No EM2 DMA wakeup from single FIFO DVL */ \
+ false /* Discard new data on full FIFO. */ \
+ }
#endif
/*******************************************************************************
@@ -1098,7 +1075,6 @@
return adc->SINGLEDATA;
}
-
/***************************************************************************//**
* @brief
* Peek single conversion result.
@@ -1117,7 +1093,6 @@
return adc->SINGLEDATAP;
}
-
/***************************************************************************//**
* @brief
* Get scan result.
@@ -1136,7 +1111,6 @@
return adc->SCANDATA;
}
-
/***************************************************************************//**
* @brief
* Peek scan result.
@@ -1155,8 +1129,7 @@
return adc->SCANDATAP;
}
-
-#if defined( _ADC_SCANDATAX_MASK )
+#if defined(_ADC_SCANDATAX_MASK)
uint32_t ADC_DataIdScanGet(ADC_TypeDef *adc, uint32_t *scanId);
#endif
@@ -1164,7 +1137,7 @@
void ADC_Reset(ADC_TypeDef *adc);
void ADC_InitScan(ADC_TypeDef *adc, const ADC_InitScan_TypeDef *init);
-#if defined( _ADC_SCANINPUTSEL_MASK )
+#if defined(_ADC_SCANINPUTSEL_MASK)
void ADC_ScanInputClear(ADC_InitScan_TypeDef *scanInit);
uint32_t ADC_ScanSingleEndedInputAdd(ADC_InitScan_TypeDef *scanInit,
ADC_ScanInputGroup_TypeDef inputGroup,
@@ -1179,7 +1152,6 @@
uint8_t ADC_TimebaseCalc(uint32_t hfperFreq);
uint8_t ADC_PrescaleCalc(uint32_t adcFreq, uint32_t hfperFreq);
-
/***************************************************************************//**
* @brief
* Clear one or more pending ADC interrupts.
@@ -1196,7 +1168,6 @@
adc->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more ADC interrupts.
@@ -1213,7 +1184,6 @@
adc->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more ADC interrupts.
@@ -1235,7 +1205,6 @@
adc->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending ADC interrupt flags.
@@ -1255,7 +1224,6 @@
return adc->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending ADC interrupt flags.
@@ -1287,7 +1255,6 @@
return adc->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending ADC interrupts from SW.
@@ -1304,7 +1271,6 @@
adc->IFS = flags;
}
-
/***************************************************************************//**
* @brief
* Start scan sequence and/or single conversion.
@@ -1320,7 +1286,6 @@
adc->CMD = (uint32_t)cmd;
}
-
/** @} (end addtogroup ADC) */
/** @} (end addtogroup emlib) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_aes.h
* @brief Advanced encryption standard (AES) accelerator peripheral API.
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -126,7 +126,7 @@
const uint8_t *iv,
bool encrypt);
-#if defined( AES_CTRL_AES256 )
+#if defined(AES_CTRL_AES256)
void AES_CBC256(uint8_t *out,
const uint8_t *in,
unsigned int len,
@@ -142,7 +142,7 @@
const uint8_t *iv,
bool encrypt);
-#if defined( AES_CTRL_AES256 )
+#if defined(AES_CTRL_AES256)
void AES_CFB256(uint8_t *out,
const uint8_t *in,
unsigned int len,
@@ -158,7 +158,7 @@
uint8_t *ctr,
AES_CtrFuncPtr_TypeDef ctrFunc);
-#if defined( AES_CTRL_AES256 )
+#if defined(AES_CTRL_AES256)
void AES_CTR256(uint8_t *out,
const uint8_t *in,
unsigned int len,
@@ -171,7 +171,7 @@
void AES_DecryptKey128(uint8_t *out, const uint8_t *in);
-#if defined( AES_CTRL_AES256 )
+#if defined(AES_CTRL_AES256)
void AES_DecryptKey256(uint8_t *out, const uint8_t *in);
#endif
@@ -181,7 +181,7 @@
const uint8_t *key,
bool encrypt);
-#if defined( AES_CTRL_AES256 )
+#if defined(AES_CTRL_AES256)
void AES_ECB256(uint8_t *out,
const uint8_t *in,
unsigned int len,
@@ -202,7 +202,6 @@
AES->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more AES interrupts.
@@ -216,7 +215,6 @@
AES->IEN &= ~(flags);
}
-
/***************************************************************************//**
* @brief
* Enable one or more AES interrupts.
@@ -235,7 +233,6 @@
AES->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending AES interrupt flags.
@@ -252,7 +249,6 @@
return AES->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending AES interrupt flags.
@@ -275,7 +271,6 @@
return AES->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending AES interrupts from SW.
@@ -289,14 +284,13 @@
AES->IFS = flags;
}
-
void AES_OFB128(uint8_t *out,
const uint8_t *in,
unsigned int len,
const uint8_t *key,
const uint8_t *iv);
-#if defined( AES_CTRL_AES256 )
+#if defined(AES_CTRL_AES256)
void AES_OFB256(uint8_t *out,
const uint8_t *in,
unsigned int len,
@@ -304,7 +298,6 @@
const uint8_t *iv);
#endif
-
/** @} (end addtogroup AES) */
/** @} (end addtogroup emlib) */
@@ -314,5 +307,3 @@
#endif /* defined(AES_COUNT) && (AES_COUNT > 0) */
#endif /* EM_AES_H */
-
-
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h Thu Nov 23 11:57:25 2017 +0000 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h Thu Dec 07 14:01:42 2017 +0000 @@ -1,9 +1,9 @@ /***************************************************************************//** * @file em_assert.h * @brief Emlib peripheral API "assert" implementation. - * @version 5.1.2 + * @version 5.3.3 ******************************************************************************* - * @section License + * # License * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b> ******************************************************************************* * @@ -44,8 +44,8 @@ #if defined(DOXY_DOC_ONLY) /** @brief Included for documentation purposes only. This define is not present by default. - * @ref DEBUG_EFM should be defined from the compiler to enable the default internal - * assert handler. */ + * @ref DEBUG_EFM should be defined from the compiler to enable the default internal + * assert handler. */ #define DEBUG_EFM /** @endcond */ #endif
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_burtc.h
* @brief Backup Real Time Counter (BURTC) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -73,8 +73,7 @@
******************************************************************************/
/** BURTC clock selection */
-typedef enum
-{
+typedef enum {
/** Ultra low frequency (1 kHz) clock */
burtcClkSelULFRCO = BURTC_CTRL_CLKSEL_ULFRCO,
/** Low frequency RC oscillator */
@@ -83,10 +82,8 @@
burtcClkSelLFXO = BURTC_CTRL_CLKSEL_LFXO
} BURTC_ClkSel_TypeDef;
-
/** BURTC mode of operation */
-typedef enum
-{
+typedef enum {
/** Disable BURTC */
burtcModeDisable = BURTC_CTRL_MODE_DISABLE,
/** Enable and start BURTC counter in EM0 to EM2 */
@@ -98,8 +95,7 @@
} BURTC_Mode_TypeDef;
/** BURTC low power mode */
-typedef enum
-{
+typedef enum {
/** Low Power Mode is disabled */
burtcLPDisable = BURTC_LPMODE_LPMODE_DISABLE,
/** Low Power Mode is always enabled */
@@ -113,8 +109,7 @@
******************************************************************************/
/** BURTC initialization structure. */
-typedef struct
-{
+typedef struct {
bool enable; /**< Enable BURTC after initialization (starts counter) */
BURTC_Mode_TypeDef mode; /**< Configure energy mode operation */
@@ -131,18 +126,18 @@
} BURTC_Init_TypeDef;
/** Default configuration for BURTC init structure */
-#define BURTC_INIT_DEFAULT \
-{ \
- true, \
- burtcModeEM2, \
- false, \
- burtcClkSelULFRCO, \
- burtcClkDiv_1, \
- 0, \
- true, \
- false, \
- burtcLPDisable, \
-}
+#define BURTC_INIT_DEFAULT \
+ { \
+ true, \
+ burtcModeEM2, \
+ false, \
+ burtcClkSelULFRCO, \
+ burtcClkDiv_1, \
+ 0, \
+ true, \
+ false, \
+ burtcLPDisable, \
+ }
/*******************************************************************************
***************************** PROTOTYPES **********************************
@@ -162,7 +157,6 @@
BURTC->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more BURTC interrupts.
@@ -177,7 +171,6 @@
BURTC->IEN &= ~(flags);
}
-
/***************************************************************************//**
* @brief
* Enable one or more BURTC interrupts.
@@ -197,7 +190,6 @@
BURTC->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending BURTC interrupt flags.
@@ -214,7 +206,6 @@
return(BURTC->IF);
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending BURTC interrupt flags.
@@ -238,7 +229,6 @@
return BURTC->IF & tmp;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending BURTC interrupts from SW.
@@ -253,7 +243,6 @@
BURTC->IFS = flags;
}
-
/***************************************************************************//**
* @brief
* Status of BURTC RAM, timestamp and LP Mode
@@ -265,7 +254,6 @@
return BURTC->STATUS;
}
-
/***************************************************************************//**
* @brief
* Clear and reset BURTC status register
@@ -275,7 +263,6 @@
BURTC->CMD = BURTC_CMD_CLRSTATUS;
}
-
/***************************************************************************//**
* @brief
* Enable or Disable BURTC peripheral reset and start counter
@@ -289,17 +276,13 @@
&& ((BURTC->CTRL & _BURTC_CTRL_MODE_MASK)
!= BURTC_CTRL_MODE_DISABLE))
|| (enable == false));
- if (enable)
- {
+ if (enable) {
BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);
- }
- else
- {
+ } else {
BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1);
}
}
-
/***************************************************************************//**
* @brief Get BURTC counter
*
@@ -311,7 +294,6 @@
return BURTC->CNT;
}
-
/***************************************************************************//**
* @brief Get BURTC timestamp for entering BU
*
@@ -323,7 +305,6 @@
return BURTC->TIMESTAMP;
}
-
/***************************************************************************//**
* @brief Freeze register updates until enabled
* @param[in] enable If true, registers are not updated until enabled again.
@@ -333,7 +314,6 @@
BUS_RegBitWrite(&BURTC->FREEZE, _BURTC_FREEZE_REGFREEZE_SHIFT, enable);
}
-
/***************************************************************************//**
* @brief Shut down power to rentention register bank.
* @param[in] enable
@@ -347,7 +327,6 @@
BUS_RegBitWrite(&BURTC->POWERDOWN, _BURTC_POWERDOWN_RAM_SHIFT, enable);
}
-
/***************************************************************************//**
* @brief
* Set a value in one of the retention registers
@@ -364,7 +343,6 @@
BURTC->RET[num].REG = data;
}
-
/***************************************************************************//**
* @brief
* Read a value from one of the retention registers
@@ -379,7 +357,6 @@
return BURTC->RET[num].REG;
}
-
/***************************************************************************//**
* @brief
* Lock BURTC registers, will protect from writing new config settings
@@ -389,7 +366,6 @@
BURTC->LOCK = BURTC_LOCK_LOCKKEY_LOCK;
}
-
/***************************************************************************//**
* @brief
* Unlock BURTC registers, enable write access to change configuration
@@ -399,7 +375,6 @@
BURTC->LOCK = BURTC_LOCK_LOCKKEY_UNLOCK;
}
-
void BURTC_Reset(void);
void BURTC_Init(const BURTC_Init_TypeDef *burtcInit);
void BURTC_CounterReset(void);
@@ -407,7 +382,6 @@
uint32_t BURTC_CompareGet(unsigned int comp);
uint32_t BURTC_ClockFreqGet(void);
-
/** @} (end addtogroup BURTC) */
/** @} (end addtogroup emlib) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_bus.h
* @brief RAM and peripheral bit-field set and clear API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -76,7 +76,7 @@
unsigned int bit,
unsigned int val)
{
-#if defined( BITBAND_RAM_BASE )
+#if defined(BITBAND_RAM_BASE)
uint32_t aliasAddr =
BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * 32) + (bit * 4);
@@ -89,7 +89,6 @@
#endif
}
-
/***************************************************************************//**
* @brief
* Perform a single-bit read operation on a 32-bit word in RAM
@@ -114,7 +113,7 @@
__STATIC_INLINE unsigned int BUS_RamBitRead(volatile const uint32_t *addr,
unsigned int bit)
{
-#if defined( BITBAND_RAM_BASE )
+#if defined(BITBAND_RAM_BASE)
uint32_t aliasAddr =
BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * 32) + (bit * 4);
@@ -124,7 +123,6 @@
#endif
}
-
/***************************************************************************//**
* @brief
* Perform a single-bit write operation on a peripheral register
@@ -149,7 +147,7 @@
unsigned int bit,
unsigned int val)
{
-#if defined( BITBAND_PER_BASE )
+#if defined(BITBAND_PER_BASE)
uint32_t aliasAddr =
BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * 32) + (bit * 4);
@@ -162,7 +160,6 @@
#endif
}
-
/***************************************************************************//**
* @brief
* Perform a single-bit read operation on a peripheral register
@@ -187,7 +184,7 @@
__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr,
unsigned int bit)
{
-#if defined( BITBAND_PER_BASE )
+#if defined(BITBAND_PER_BASE)
uint32_t aliasAddr =
BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * 32) + (bit * 4);
@@ -197,7 +194,6 @@
#endif
}
-
/***************************************************************************//**
* @brief
* Perform a masked set operation on peripheral register address.
@@ -221,7 +217,7 @@
__STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr,
uint32_t mask)
{
-#if defined( PER_BITSET_MEM_BASE )
+#if defined(PER_BITSET_MEM_BASE)
uint32_t aliasAddr = PER_BITSET_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE);
*(volatile uint32_t *)aliasAddr = mask;
#else
@@ -229,7 +225,6 @@
#endif
}
-
/***************************************************************************//**
* @brief
* Perform a masked clear operation on peripheral register address.
@@ -253,7 +248,7 @@
__STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr,
uint32_t mask)
{
-#if defined( PER_BITCLR_MEM_BASE )
+#if defined(PER_BITCLR_MEM_BASE)
uint32_t aliasAddr = PER_BITCLR_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE);
*(volatile uint32_t *)aliasAddr = mask;
#else
@@ -261,7 +256,6 @@
#endif
}
-
/***************************************************************************//**
* @brief
* Perform peripheral register masked clear and value write.
@@ -289,7 +283,7 @@
uint32_t mask,
uint32_t val)
{
-#if defined( PER_BITCLR_MEM_BASE )
+#if defined(PER_BITCLR_MEM_BASE)
BUS_RegMaskedClear(addr, mask);
BUS_RegMaskedSet(addr, val);
#else
@@ -297,7 +291,6 @@
#endif
}
-
/***************************************************************************//**
* @brief
* Perform a peripheral register masked read
@@ -321,7 +314,6 @@
return *addr & mask;
}
-
/** @} (end addtogroup BUS) */
/** @} (end addtogroup emlib) */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_can.h Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,596 @@
+/***************************************************************************//**
+ * @file em_can.h
+ * @brief Controller Area Network API
+ * @version 5.3.3
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#ifndef EM_CAN_H
+#define EM_CAN_H
+
+#include "em_bus.h"
+#include "em_device.h"
+#include <stdbool.h>
+
+#if defined(CAN_COUNT) && (CAN_COUNT > 0)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+ * @addtogroup emlib
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup CAN
+ * @{
+ ******************************************************************************/
+
+/*******************************************************************************
+ ******************************* DEFINES ***********************************
+ ******************************************************************************/
+
+/*******************************************************************************
+ ******************************** ENUMS ************************************
+ ******************************************************************************/
+
+/** CAN Status codes */
+typedef enum {
+ /** No error occurred during last CAN bus event. */
+ canErrorNoError = CAN_STATUS_LEC_NONE,
+
+ /**
+ * More than 5 equal bits in a sequence have occurred in a part of a received
+ * message where this is not allowed.
+ */
+ canErrorStuff = CAN_STATUS_LEC_STUFF,
+
+ /** A fixed format part of a received frame has the wrong format. */
+ canErrorForm = CAN_STATUS_LEC_FORM,
+
+ /** The message this CAN Core transmitted was not acknowledged by another node. */
+ canErrorAck = CAN_STATUS_LEC_ACK,
+
+ /** Wrong monitored bus value : dominant when the module wanted to send a recessive. */
+ canErrorBit1 = CAN_STATUS_LEC_BIT1,
+
+ /** Wrong monitored bus value : recessive when the module intended to send a dominant. */
+ canErrorBit0 = CAN_STATUS_LEC_BIT0,
+
+ /** CRC check sum incorrect. */
+ canErrorCrc = CAN_STATUS_LEC_CRC,
+
+ /** Unused. No new error since the cpu wrote this value */
+ canErrorUnused = CAN_STATUS_LEC_UNUSED
+} CAN_ErrorCode_TypeDef;
+
+/** CAN peripheral mode */
+typedef enum {
+ /** CAN peripheral in Normal mode : ready to send and receive messages */
+ canModeNormal,
+
+ /** CAN peripheral in Basic mode : no use of the RAM */
+ canModeBasic,
+
+ /**
+ * CAN peripheral in Loopback mode : input from the CAN bus is disregarded
+ * and comes from TX instead
+ */
+ canModeLoopBack,
+
+ /**
+ * CAN peripheral in SilentLoopback mode : input from the CAN bus is
+ * disregarded and comes from TX instead ; no output on the CAN bus
+ */
+ canModeSilentLoopBack,
+
+ /** CAN peripheral in Silent mode : no output on the CAN bus. If required to
+ * send a dominant bit, it's rerouted internally so that the CAN module
+ * monitors it but the CAN bus stays recessive.
+ */
+ canModeSilent
+} CAN_Mode_TypeDef;
+
+/*******************************************************************************
+ ******************************* STRUCTS ***********************************
+ ******************************************************************************/
+
+/** CAN Message Object TypeDef structure. LSBs is used */
+typedef struct {
+ /** Message number of this Message Object, [1 - 32] */
+ uint8_t msgNum;
+
+ /** Id extended if true, standard if false */
+ bool extended;
+
+ /**
+ * Id of the message, with 11 bits (standard) or 28 bits (extended).
+ * LSBs are used for both of them
+ */
+ uint32_t id;
+
+ /** Data Length Code [0 - 8] */
+ uint8_t dlc;
+
+ /** Pointer to the data, [0 - 8] bytes */
+ uint8_t data[8];
+
+ /** Mask for id filtering */
+ uint32_t mask;
+
+ /** Enable the use of 'extended' value for filtering */
+ bool extendedMask;
+
+ /** Enable the use of 'direction' value for filtering */
+ bool directionMask;
+} CAN_MessageObject_TypeDef;
+
+/** CAN initialization structure. */
+typedef struct {
+ /** true to set the CAN Device in normal mode after init */
+ bool enable;
+
+ /** True to reset messages during initialization */
+ bool resetMessages;
+
+ /** Default bitrate */
+ uint32_t bitrate;
+
+ /** Default Propagation Time Segment */
+ uint8_t propagationTimeSegment;
+
+ /** Default Phase Buffer Segment 1 */
+ uint8_t phaseBufferSegment1;
+
+ /** Default Phase Buffer Segment 2 */
+ uint8_t phaseBufferSegment2;
+
+ /** Default Synchronisation Jump Width */
+ uint8_t synchronisationJumpWidth;
+} CAN_Init_TypeDef;
+
+/**
+ * Default initialization of CAN_Init_TypeDef. The total duration of a bit with
+ * these default parameters is 10 tq (time quantum : tq = brp/fsys, brp being
+ * the baudrate prescaler and being set according to the wanted bitrate, fsys
+ * beeing the CAN Device frequency).
+ */
+#define CAN_INIT_DEFAULT \
+ { \
+ true, /** Set the CAN Device in normal mode after init */ \
+ true, /** Reset messages during initialization */ \
+ 100000, /** Set bitrate to 100 000 */ \
+ 1, /** Set the Propagation Time Segment to 1 */ \
+ 4, /** Set the Phase Buffer Segment 1 to 4 */ \
+ 4, /** Set the Phase Buffer Segment 2 to 4 */ \
+ 1 /** Set the Synchronization Jump Width to 1 */ \
+ }
+
+/*******************************************************************************
+ ***************************** PROTOTYPES **********************************
+ ******************************************************************************/
+
+void CAN_Init(CAN_TypeDef *can, const CAN_Init_TypeDef *init);
+
+uint32_t CAN_GetClockFrequency(CAN_TypeDef *can);
+
+bool CAN_MessageLost(CAN_TypeDef *can, uint8_t interface, uint8_t msgNum);
+
+void CAN_SetRoute(CAN_TypeDef *can,
+ bool active,
+ uint16_t pinRxLoc,
+ uint16_t pinTxLoc);
+
+void CAN_SetBitTiming(CAN_TypeDef *can,
+ uint32_t bitrate,
+ uint16_t propagationTimeSegment,
+ uint16_t phaseBufferSegment1,
+ uint16_t phaseBufferSegment2,
+ uint16_t synchronisationJumpWidth);
+
+void CAN_SetMode(CAN_TypeDef *can, CAN_Mode_TypeDef mode);
+
+void CAN_SetIdAndFilter(CAN_TypeDef *can,
+ uint8_t interface,
+ bool useMask,
+ const CAN_MessageObject_TypeDef *message,
+ bool wait);
+
+void CAN_ConfigureMessageObject(CAN_TypeDef *can,
+ uint8_t interface,
+ uint8_t msgNum,
+ bool valid,
+ bool tx,
+ bool remoteTransfer,
+ bool endOfBuffer,
+ bool wait);
+
+void CAN_SendMessage(CAN_TypeDef *can,
+ uint8_t interface,
+ const CAN_MessageObject_TypeDef *message,
+ bool wait);
+
+void CAN_ReadMessage(CAN_TypeDef *can,
+ uint8_t interface,
+ CAN_MessageObject_TypeDef *message);
+
+void CAN_AbortSendMessage(CAN_TypeDef *can,
+ uint8_t interface,
+ uint8_t msgNum,
+ bool wait);
+
+void CAN_ResetMessages(CAN_TypeDef *can, uint8_t interface);
+
+void CAN_Reset(CAN_TypeDef *can);
+
+void CAN_WriteData(CAN_TypeDef *can,
+ uint8_t interface,
+ const CAN_MessageObject_TypeDef *message);
+
+void CAN_SendRequest(CAN_TypeDef *can,
+ uint8_t interface,
+ uint8_t msgNum,
+ bool wait);
+
+/***************************************************************************//**
+ * @brief
+ * Enable the Host Controller to send messages.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] enable
+ * true to enable CAN device, false to disable it. If the CAN device is
+ * enabled, it goes in normal mode (the default working mode).
+ ******************************************************************************/
+__STATIC_INLINE void CAN_Enable(CAN_TypeDef *can, bool enable)
+{
+ BUS_RegBitWrite(&can->CTRL, _CAN_CTRL_INIT_SHIFT, (enable ? 0 : 1));
+}
+
+/***************************************************************************//**
+ * @brief
+ * Gives the communication capabilities state.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @return
+ * true if the Host Controller can send messages, false otherwise.
+ ******************************************************************************/
+__STATIC_INLINE bool CAN_IsEnabled(CAN_TypeDef *can)
+{
+ return (can->CTRL & _CAN_CTRL_INIT_MASK) == 0;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Waiting function.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] interface
+ * Indicate which Message Interface Register to use.
+ *
+ ******************************************************************************/
+__STATIC_INLINE void CAN_ReadyWait(CAN_TypeDef *can,
+ uint8_t interface)
+{
+ while ((_CAN_MIR_CMDREQ_BUSY_MASK & can->MIR[interface].CMDREQ) != 0) {
+ }
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get the last error code and clear its register.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @return
+ * return Last error code.
+ ******************************************************************************/
+__STATIC_INLINE CAN_ErrorCode_TypeDef CAN_GetLastErrorCode(CAN_TypeDef *can)
+{
+ CAN_ErrorCode_TypeDef errorCode = (CAN_ErrorCode_TypeDef)
+ (can->STATUS & _CAN_STATUS_LEC_MASK);
+ can->STATUS |= ~_CAN_STATUS_LEC_MASK;
+ return errorCode;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Indicates which messages objects have received new data.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @return
+ * State of MESSAGEDATA register indicating which messages objects have received
+ * new data.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CAN_HasNewdata(CAN_TypeDef *can)
+{
+ return can->MESSAGEDATA;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Clear one or more pending CAN status interrupts.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] flags
+ * Pending CAN status interrupt source(s) to clear.
+ ******************************************************************************/
+__STATIC_INLINE void CAN_StatusIntClear(CAN_TypeDef *can, uint32_t flags)
+{
+ can->IF1IFC = flags;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Disable CAN status interrupts.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] flags
+ * CAN status interrupt source(s) to disable.
+ ******************************************************************************/
+__STATIC_INLINE void CAN_StatusIntDisable(CAN_TypeDef *can, uint32_t flags)
+{
+ can->IF1IEN &= ~flags;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Enable CAN status interrupts.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] flags
+ * CAN status interrupt source(s) to enable.
+ ******************************************************************************/
+__STATIC_INLINE void CAN_StatusIntEnable(CAN_TypeDef *can, uint32_t flags)
+{
+ can->IF1IEN |= flags;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get pending CAN status interrupt flags.
+ *
+ * @note
+ * The event bits are not cleared by the use of this function.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @return
+ * CAN interrupt source(s) pending.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CAN_StatusIntGet(CAN_TypeDef *can)
+{
+ return can->IF1IF;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get pending and enabled CAN status interrupt flags.
+ *
+ * @note
+ * The event bits are not cleared by the use of this function.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @return
+ * CAN interrupt source(s) pending and enabled.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CAN_StatusIntGetEnabled(CAN_TypeDef *can)
+{
+ uint32_t ien;
+
+ ien = can->IF1IEN;
+ return can->IF1IF & ien;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Set one or more CAN status interrupts.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] flags
+ * CAN status interrupt source(s) to set to pending.
+ ******************************************************************************/
+__STATIC_INLINE void CAN_StatusIntSet(CAN_TypeDef *can, uint32_t flags)
+{
+ can->IF1IFS = flags;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get CAN status.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @return
+ * Value of CAN register STATUS.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CAN_StatusGet(CAN_TypeDef *can)
+{
+ return can->STATUS & ~_CAN_STATUS_LEC_MASK;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Clear CAN status.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] flags
+ * CAN status bits to clear.
+ ******************************************************************************/
+__STATIC_INLINE void CAN_StatusClear(CAN_TypeDef *can, uint32_t flags)
+{
+ can->STATUS &= ~flags;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get the error count.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @return
+ * Error count.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CAN_GetErrorCount(CAN_TypeDef *can)
+{
+ return can->ERRCNT;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Clear one or more pending CAN message interrupts.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] flags
+ * Pending CAN message interrupt source(s) to clear.
+ ******************************************************************************/
+__STATIC_INLINE void CAN_MessageIntClear(CAN_TypeDef *can, uint32_t flags)
+{
+ can->IF0IFC = flags;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Disable CAN message interrupts.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] flags
+ * CAN message interrupt source(s) to disable.
+ ******************************************************************************/
+__STATIC_INLINE void CAN_MessageIntDisable(CAN_TypeDef *can, uint32_t flags)
+{
+ can->IF0IEN &= ~flags;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Enable CAN message interrupts.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] flags
+ * CAN message interrupt source(s) to enable.
+ ******************************************************************************/
+__STATIC_INLINE void CAN_MessageIntEnable(CAN_TypeDef *can, uint32_t flags)
+{
+ can->IF0IEN |= flags;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get pending CAN message interrupt flags.
+ *
+ * @note
+ * The event bits are not cleared by the use of this function.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @return
+ * CAN message interrupt source(s) pending.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CAN_MessageIntGet(CAN_TypeDef *can)
+{
+ return can->IF0IF;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get CAN message interrupt flags that are pending and enabled.
+ *
+ * @note
+ * The event bits are not cleared by the use of this function.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @return
+ * CAN message interrupt source(s) pending and enabled.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t CAN_MessageIntGetEnabled(CAN_TypeDef *can)
+{
+ uint32_t ien;
+
+ ien = can->IF0IEN;
+ return can->IF0IF & ien;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Set one or more CAN message interrupts.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] flags
+ * CAN message interrupt source(s) to set to pending.
+ ******************************************************************************/
+__STATIC_INLINE void CAN_MessageIntSet(CAN_TypeDef *can, uint32_t flags)
+{
+ can->IF0IFS = flags;
+}
+
+/** @} (end addtogroup CAN) */
+/** @} (end addtogroup emlib) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* defined(CAN_COUNT) && (CAN_COUNT > 0) */
+#endif /* EM_CAN_H */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_chip.h
* @brief Chip Initialization API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -76,8 +76,7 @@
rev = *(volatile uint32_t *)(0x0FE081FC);
/* Engineering Sample calibration setup */
- if ((rev >> 24) == 0)
- {
+ if ((rev >> 24) == 0) {
reg = (volatile uint32_t *)0x400CA00C;
*reg &= ~(0x70UL);
/* DREG */
@@ -85,8 +84,7 @@
*reg &= ~(0xE0000000UL);
*reg |= ~(7UL << 25);
}
- if ((rev >> 24) <= 3)
- {
+ if ((rev >> 24) <= 3) {
/* DREG */
reg = (volatile uint32_t *)0x400C6020;
*reg &= ~(0x00001F80UL);
@@ -104,12 +102,10 @@
}
SYSTEM_ChipRevisionGet(&chipRev);
- if (chipRev.major == 0x01)
- {
+ if (chipRev.major == 0x01) {
/* Rev A errata handling for EM2/3. Must enable DMA clock in order for EM2/3 */
/* to work. This will be fixed in later chip revisions, so only do for rev A. */
- if (chipRev.minor == 00)
- {
+ if (chipRev.minor == 00) {
reg = (volatile uint32_t *)0x400C8040;
*reg |= 0x2;
}
@@ -117,16 +113,14 @@
/* Rev A+B errata handling for I2C when using EM2/3. USART0 clock must be enabled */
/* after waking up from EM2/EM3 in order for I2C to work. This will be fixed in */
/* later chip revisions, so only do for rev A+B. */
- if (chipRev.minor <= 0x01)
- {
+ if (chipRev.minor <= 0x01) {
reg = (volatile uint32_t *)0x400C8044;
*reg |= 0x1;
}
}
/* Ensure correct ADC/DAC calibration value */
rev = *(volatile uint32_t *)0x0FE081F0;
- if (rev < 0x4C8ABA00)
- {
+ if (rev < 0x4C8ABA00) {
uint32_t cal;
/* Enable ADC/DAC clocks */
@@ -134,17 +128,17 @@
*reg |= (1 << 14 | 1 << 11);
/* Retrive calibration values */
- cal = ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) >>
- 8) << 24;
+ cal = ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL)
+ >> 8) << 24;
- cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) >>
- 0) << 16;
+ cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL)
+ >> 0) << 16;
- cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) >>
- 8) << 8;
+ cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL)
+ >> 8) << 8;
- cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) >>
- 0) << 0;
+ cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL)
+ >> 0) << 0;
/* ADC0->CAL = 1.25 reference */
reg = (volatile uint32_t *)0x40002034UL;
@@ -172,11 +166,10 @@
prodRev = SYSTEM_GetProdRev();
SYSTEM_ChipRevisionGet(&chipRev);
- if ((prodRev >= 16) && (chipRev.minor >= 3))
- {
+ if ((prodRev >= 16) && (chipRev.minor >= 3)) {
/* This fixes an issue with the LFXO on high temperatures. */
*(volatile uint32_t*)0x400C80C0 =
- ( *(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4);
+ (*(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4);
}
#endif
@@ -185,8 +178,7 @@
uint8_t prodRev;
prodRev = SYSTEM_GetProdRev();
- if (prodRev <= 129)
- {
+ if (prodRev <= 129) {
/* This fixes a mistaken internal connection between PC0 and PC4 */
/* This disables an internal pulldown on PC4 */
*(volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0);
@@ -198,14 +190,14 @@
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
/****************************
- * Fixes for errata GPIO_E201 (slewrate) and
- * HFXO high temperature oscillator startup robustness fix */
+ * Fixes for errata GPIO_E201 (slewrate) and
+ * HFXO high temperature oscillator startup robustness fix */
uint32_t port;
uint32_t clkEn;
uint8_t prodRev;
const uint32_t setVal = (0x5 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT)
- | (0x5 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
+ | (0x5 << _GPIO_P_CTRL_SLEWRATE_SHIFT);
const uint32_t resetVal = _GPIO_P_CTRL_RESETVALUE
& ~(_GPIO_P_CTRL_SLEWRATE_MASK
| _GPIO_P_CTRL_SLEWRATEALT_MASK);
@@ -215,8 +207,7 @@
SYSTEM_ChipRevisionGet(&chipRev);
/* This errata is fixed in hardware from PRODREV 0x8F. */
- if (prodRev < 0x8F)
- {
+ if (prodRev < 0x8F) {
/* Fixes for errata GPIO_E201 (slewrate) */
/* Save HFBUSCLK enable state and enable GPIO clock. */
@@ -224,8 +215,7 @@
CMU->HFBUSCLKEN0 = clkEn | CMU_HFBUSCLKEN0_GPIO;
/* Update slewrate */
- for(port = 0; port <= GPIO_PORT_MAX; port++)
- {
+ for (port = 0; port <= GPIO_PORT_MAX; port++) {
GPIO->P[port].CTRL = setVal | resetVal;
}
@@ -234,19 +224,25 @@
}
/* This errata is fixed in hardware from PRODREV 0x90. */
- if (prodRev < 0x90)
- {
+ if (prodRev < 0x90) {
/* HFXO high temperature oscillator startup robustness fix */
CMU->HFXOSTARTUPCTRL =
- (CMU->HFXOSTARTUPCTRL & ~_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK)
- | (0x20 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT);
+ (CMU->HFXOSTARTUPCTRL & ~_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK)
+ | (0x20 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT);
}
- if (chipRev.major == 0x01)
- {
+ if (chipRev.major == 0x01) {
/* Fix for errata EMU_E210 - Potential Power-Down When Entering EM2 */
*(volatile uint32_t *)(EMU_BASE + 0x164) |= 0x4;
}
+
+#if defined(_EFR_DEVICE)
+ /****************************
+ * Fix for errata DCDC_E206
+ * Disable bypass limit enabled temporarily in SystemInit() errata
+ * workaround. */
+ BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0);
+#endif
#endif
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
@@ -254,28 +250,33 @@
uint8_t prodRev = SYSTEM_GetProdRev();
/* EM2 current fixes for early samples */
- if (prodRev == 0)
- {
+ if (prodRev == 0) {
*(volatile uint32_t *)(EMU_BASE + 0x190) = 0x0000ADE8UL;
*(volatile uint32_t *)(EMU_BASE + 0x198) |= (0x1 << 2);
*(volatile uint32_t *)(EMU_BASE + 0x190) = 0x0;
}
- if (prodRev < 2)
- {
+ if (prodRev < 2) {
*(volatile uint32_t *)(EMU_BASE + 0x164) |= (0x1 << 13);
}
/* Set optimal LFRCOCTRL VREFUPDATE and enable duty cycling of vref */
CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~_CMU_LFRCOCTRL_VREFUPDATE_MASK)
- | CMU_LFRCOCTRL_VREFUPDATE_64CYCLES
- | CMU_LFRCOCTRL_ENVREF;
+ | CMU_LFRCOCTRL_VREFUPDATE_64CYCLES
+ | CMU_LFRCOCTRL_ENVREF;
#endif
#if defined(_EFR_DEVICE) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 84)
MSC->CTRL |= 0x1 << 8;
#endif
-
+ /* Set validated PLFRCO trims for production revision < 5. Overwriting registers
+ for all production revisions is safe. */
+#if defined(_SILICON_LABS_32B_SERIES_1) && defined(_CMU_STATUS_PLFRCOENS_MASK)
+ *(volatile uint32_t *)(CMU_BASE + 0x28C) = 0x258;
+ *(volatile uint32_t *)(CMU_BASE + 0x290) = 0x55D4A;
+ *(volatile uint32_t *)(CMU_BASE + 0x2FC) = 0x16E228;
+ *(volatile uint32_t *)(CMU_BASE + 0x294) = 0x1E0;
+#endif
}
/** @} (end addtogroup CHIP) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_cmu.h
* @brief Clock management unit (CMU) API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -33,7 +33,7 @@
#define EM_CMU_H
#include "em_device.h"
-#if defined( CMU_PRESENT )
+#if defined(CMU_PRESENT)
#include <stdbool.h>
#include "em_assert.h"
@@ -64,6 +64,11 @@
#define CMU_LFECLKSEL_REG 5
#define CMU_DBGCLKSEL_REG 6
#define CMU_USBCCLKSEL_REG 7
+#define CMU_ADC0ASYNCSEL_REG 8
+#define CMU_ADC1ASYNCSEL_REG 9
+#define CMU_SDIOREFSEL_REG 10
+#define CMU_QSPI0REFSEL_REG 11
+#define CMU_USBRCLKSEL_REG 12
#define CMU_SEL_REG_POS 0
#define CMU_SEL_REG_MASK 0xf
@@ -82,6 +87,7 @@
#define CMU_LFAPRESC0_REG 6
#define CMU_LFBPRESC0_REG 7
#define CMU_LFEPRESC0_REG 8
+#define CMU_ADCASYNCDIV_REG 9
#define CMU_PRESC_REG_POS 4
#define CMU_DIV_REG_POS CMU_PRESC_REG_POS
@@ -100,6 +106,11 @@
#define CMU_LFCCLKEN0_EN_REG 8
#define CMU_LFECLKEN0_EN_REG 9
#define CMU_PCNT_EN_REG 10
+#define CMU_SDIOREF_EN_REG 11
+#define CMU_QSPI0REF_EN_REG 12
+#define CMU_QSPI1REF_EN_REG 13
+#define CMU_HFPERCLKEN1_EN_REG 14
+#define CMU_USBRCLK_EN_REG 15
#define CMU_EN_REG_POS 8
#define CMU_EN_REG_MASK 0xf
@@ -131,14 +142,27 @@
#define CMU_LCD_CLK_BRANCH 20
#define CMU_LESENSE_CLK_BRANCH 21
#define CMU_CSEN_LF_CLK_BRANCH 22
+#define CMU_ADC0ASYNC_CLK_BRANCH 23
+#define CMU_ADC1ASYNC_CLK_BRANCH 24
+#define CMU_SDIOREF_CLK_BRANCH 25
+#define CMU_QSPI0REF_CLK_BRANCH 26
+#define CMU_USBR_CLK_BRANCH 27
#define CMU_CLK_BRANCH_POS 17
#define CMU_CLK_BRANCH_MASK 0x1f
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
/* Max clock frequency for VSCALE voltages */
#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000
#endif
+
+#if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK)
+#define USBC_CLOCK_PRESENT
+#endif
+#if defined(USB_PRESENT) && defined(_CMU_USBCTRL_MASK)
+#define USBR_CLOCK_PRESENT
+#endif
+
/** @endcond */
/*******************************************************************************
@@ -166,45 +190,42 @@
/** Clock divider configuration */
typedef uint32_t CMU_ClkDiv_TypeDef;
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
/** Clockprescaler configuration */
typedef uint32_t CMU_ClkPresc_TypeDef;
#endif
-#if defined( _CMU_HFRCOCTRL_BAND_MASK )
+#if defined(_CMU_HFRCOCTRL_BAND_MASK)
/** High frequency system RCO bands */
-typedef enum
-{
+typedef enum {
cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ, /**< 1MHz HFRCO band */
cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ, /**< 7MHz HFRCO band */
cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ, /**< 11MHz HFRCO band */
cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ, /**< 14MHz HFRCO band */
cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ, /**< 21MHz HFRCO band */
-#if defined( CMU_HFRCOCTRL_BAND_28MHZ )
+#if defined(CMU_HFRCOCTRL_BAND_28MHZ)
cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ, /**< 28MHz HFRCO band */
#endif
} CMU_HFRCOBand_TypeDef;
#endif /* _CMU_HFRCOCTRL_BAND_MASK */
-#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
+#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK)
/** AUX High frequency RCO bands */
-typedef enum
-{
+typedef enum {
cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ, /**< 1MHz RC band */
cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ, /**< 7MHz RC band */
cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ, /**< 11MHz RC band */
cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ, /**< 14MHz RC band */
cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ, /**< 21MHz RC band */
-#if defined( CMU_AUXHFRCOCTRL_BAND_28MHZ )
+#if defined(CMU_AUXHFRCOCTRL_BAND_28MHZ)
cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ, /**< 28MHz RC band */
#endif
} CMU_AUXHFRCOBand_TypeDef;
#endif
-#if defined( _CMU_USHFRCOCONF_BAND_MASK )
+#if defined(_CMU_USHFRCOCONF_BAND_MASK)
/** USB High frequency RC bands. */
-typedef enum
-{
+typedef enum {
/** 24MHz RC band. */
cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ,
/** 48MHz RC band. */
@@ -212,10 +233,22 @@
} CMU_USHFRCOBand_TypeDef;
#endif
-#if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
+#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK)
+/** High USHFRCO bands */
+typedef enum {
+ cmuUSHFRCOFreq_16M0Hz = 16000000U, /**< 16MHz RC band */
+ cmuUSHFRCOFreq_32M0Hz = 32000000U, /**< 32MHz RC band */
+ cmuUSHFRCOFreq_48M0Hz = 48000000U, /**< 48MHz RC band */
+ cmuUSHFRCOFreq_50M0Hz = 50000000U, /**< 50MHz RC band */
+ cmuUSHFRCOFreq_UserDefined = 0,
+} CMU_USHFRCOFreq_TypeDef;
+#define CMU_USHFRCO_MIN cmuUSHFRCOFreq_16M0Hz
+#define CMU_USHFRCO_MAX cmuUSHFRCOFreq_50M0Hz
+#endif
+
+#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
/** High frequency system RCO bands */
-typedef enum
-{
+typedef enum {
cmuHFRCOFreq_1M0Hz = 1000000U, /**< 1MHz RC band */
cmuHFRCOFreq_2M0Hz = 2000000U, /**< 2MHz RC band */
cmuHFRCOFreq_4M0Hz = 4000000U, /**< 4MHz RC band */
@@ -226,16 +259,37 @@
cmuHFRCOFreq_26M0Hz = 26000000U, /**< 26MHz RC band */
cmuHFRCOFreq_32M0Hz = 32000000U, /**< 32MHz RC band */
cmuHFRCOFreq_38M0Hz = 38000000U, /**< 38MHz RC band */
+#if defined(_DEVINFO_HFRCOCAL13_MASK)
+ cmuHFRCOFreq_48M0Hz = 48000000U, /**< 48MHz RC band */
+#endif
+#if defined(_DEVINFO_HFRCOCAL14_MASK)
+ cmuHFRCOFreq_56M0Hz = 56000000U, /**< 56MHz RC band */
+#endif
+#if defined(_DEVINFO_HFRCOCAL15_MASK)
+ cmuHFRCOFreq_64M0Hz = 64000000U, /**< 64MHz RC band */
+#endif
+#if defined(_DEVINFO_HFRCOCAL16_MASK)
+ cmuHFRCOFreq_72M0Hz = 72000000U, /**< 72MHz RC band */
+#endif
cmuHFRCOFreq_UserDefined = 0,
} CMU_HFRCOFreq_TypeDef;
#define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz
+#if defined(_DEVINFO_HFRCOCAL16_MASK)
+#define CMU_HFRCO_MAX cmuHFRCOFreq_72M0Hz
+#elif defined(_DEVINFO_HFRCOCAL15_MASK)
+#define CMU_HFRCO_MAX cmuHFRCOFreq_64M0Hz
+#elif defined(_DEVINFO_HFRCOCAL14_MASK)
+#define CMU_HFRCO_MAX cmuHFRCOFreq_56M0Hz
+#elif defined(_DEVINFO_HFRCOCAL13_MASK)
+#define CMU_HFRCO_MAX cmuHFRCOFreq_48M0Hz
+#else
#define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz
#endif
+#endif
-#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
+#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
/** AUX High frequency RCO bands */
-typedef enum
-{
+typedef enum {
cmuAUXHFRCOFreq_1M0Hz = 1000000U, /**< 1MHz RC band */
cmuAUXHFRCOFreq_2M0Hz = 2000000U, /**< 2MHz RC band */
cmuAUXHFRCOFreq_4M0Hz = 4000000U, /**< 4MHz RC band */
@@ -246,23 +300,29 @@
cmuAUXHFRCOFreq_26M0Hz = 26000000U, /**< 26MHz RC band */
cmuAUXHFRCOFreq_32M0Hz = 32000000U, /**< 32MHz RC band */
cmuAUXHFRCOFreq_38M0Hz = 38000000U, /**< 38MHz RC band */
+#if defined(_DEVINFO_AUXHFRCOCAL14_MASK)
+ cmuAUXHFRCOFreq_48M0Hz = 48000000U, /**< 48MHz RC band */
+ cmuAUXHFRCOFreq_50M0Hz = 50000000U, /**< 50MHz RC band */
+#endif
cmuAUXHFRCOFreq_UserDefined = 0,
} CMU_AUXHFRCOFreq_TypeDef;
#define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz
+#if defined(_DEVINFO_AUXHFRCOCAL14_MASK)
+#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_50M0Hz
+#else
#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz
#endif
+#endif
-
/** Clock points in CMU. Please refer to CMU overview in reference manual. */
-typedef enum
-{
+typedef enum {
/*******************/
/* HF clock branch */
/*******************/
/** High frequency clock */
-#if defined( _CMU_CTRL_HFCLKDIV_MASK ) \
- || defined( _CMU_HFPRESC_MASK )
+#if defined(_CMU_CTRL_HFCLKDIV_MASK) \
+ || defined(_CMU_HFPRESC_MASK)
cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS)
| (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
| (CMU_NO_EN_REG << CMU_EN_REG_POS)
@@ -290,7 +350,7 @@
| (0 << CMU_EN_BIT_POS)
| (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),
-#if defined( _CMU_HFEXPPRESC_MASK )
+#if defined(_CMU_HFEXPPRESC_MASK)
/**********************/
/* HF export sub-branch */
/**********************/
@@ -303,10 +363,10 @@
| (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( _CMU_HFBUSCLKEN0_MASK )
+#if defined(_CMU_HFBUSCLKEN0_MASK)
/**********************************/
- /* HF bus clock sub-branch */
- /**********************************/
+/* HF bus clock sub-branch */
+/**********************************/
/** High frequency bus clock. */
cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
@@ -315,7 +375,7 @@
| (0 << CMU_EN_BIT_POS)
| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
-#if defined( CMU_HFBUSCLKEN0_CRYPTO )
+#if defined(CMU_HFBUSCLKEN0_CRYPTO)
/** Cryptography accelerator clock. */
cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -324,7 +384,7 @@
| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFBUSCLKEN0_CRYPTO0 )
+#if defined(CMU_HFBUSCLKEN0_CRYPTO0)
/** Cryptography accelerator 0 clock. */
cmuClock_CRYPTO0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -333,7 +393,7 @@
| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFBUSCLKEN0_CRYPTO1 )
+#if defined(CMU_HFBUSCLKEN0_CRYPTO1)
/** Cryptography accelerator 1 clock. */
cmuClock_CRYPTO1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -342,7 +402,7 @@
| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFBUSCLKEN0_LDMA )
+#if defined(CMU_HFBUSCLKEN0_LDMA)
/** Direct memory access controller clock. */
cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -351,7 +411,16 @@
| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFBUSCLKEN0_GPCRC )
+#if defined(CMU_HFBUSCLKEN0_QSPI0)
+ /** Quad SPI clock. */
+ cmuClock_QSPI0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFBUSCLKEN0_QSPI0_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(CMU_HFBUSCLKEN0_GPCRC)
/** General purpose cyclic redundancy checksum clock. */
cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -360,7 +429,7 @@
| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFBUSCLKEN0_GPIO )
+#if defined(CMU_HFBUSCLKEN0_GPIO)
/** General purpose input/output clock. */
cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -376,7 +445,7 @@
| (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
-#if defined( CMU_HFBUSCLKEN0_PRS )
+#if defined(CMU_HFBUSCLKEN0_PRS)
/** Peripheral reflex system clock. */
cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -391,7 +460,7 @@
/**********************************/
/** High frequency peripheral clock */
-#if defined( _CMU_HFPRESC_MASK )
+#if defined(_CMU_HFPRESC_MASK)
cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
@@ -405,7 +474,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_USART0 )
+#if defined(CMU_HFPERCLKEN0_USART0)
/** Universal sync/async receiver/transmitter 0 clock. */
cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -414,7 +483,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_USARTRF0 )
+#if defined(CMU_HFPERCLKEN0_USARTRF0)
/** Universal sync/async receiver/transmitter 0 clock. */
cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -423,7 +492,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_USARTRF1 )
+#if defined(CMU_HFPERCLKEN0_USARTRF1)
/** Universal sync/async receiver/transmitter 0 clock. */
cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -432,7 +501,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_USART1 )
+#if defined(CMU_HFPERCLKEN0_USART1)
/** Universal sync/async receiver/transmitter 1 clock. */
cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -441,7 +510,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_USART2 )
+#if defined(CMU_HFPERCLKEN0_USART2)
/** Universal sync/async receiver/transmitter 2 clock. */
cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -450,7 +519,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_USART3 )
+#if defined(CMU_HFPERCLKEN0_USART3)
/** Universal sync/async receiver/transmitter 3 clock. */
cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -459,7 +528,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_USART4 )
+#if defined(CMU_HFPERCLKEN0_USART4)
/** Universal sync/async receiver/transmitter 4 clock. */
cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -468,7 +537,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_USART5 )
+#if defined(CMU_HFPERCLKEN0_USART5)
/** Universal sync/async receiver/transmitter 5 clock. */
cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -477,26 +546,39 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-
-#if defined( CMU_HFPERCLKEN0_UART0 )
+#if defined(CMU_HFPERCLKEN0_UART0)
/** Universal async receiver/transmitter 0 clock. */
cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#elif defined(_CMU_HFPERCLKEN1_UART0_MASK)
+ /** Universal async receiver/transmitter 0 clock. */
+ cmuClock_UART0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN1_UART0_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_UART1 )
+#if defined(CMU_HFPERCLKEN0_UART1)
/** Universal async receiver/transmitter 1 clock. */
cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#elif defined(_CMU_HFPERCLKEN1_UART1_MASK)
+ /** Universal async receiver/transmitter 1 clock. */
+ cmuClock_UART1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN1_UART1_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_TIMER0 )
+#if defined(CMU_HFPERCLKEN0_TIMER0)
/** Timer 0 clock. */
cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -505,7 +587,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_TIMER1 )
+#if defined(CMU_HFPERCLKEN0_TIMER1)
/** Timer 1 clock. */
cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -514,7 +596,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_TIMER2 )
+#if defined(CMU_HFPERCLKEN0_TIMER2)
/** Timer 2 clock. */
cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -523,7 +605,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_TIMER3 )
+#if defined(CMU_HFPERCLKEN0_TIMER3)
/** Timer 3 clock. */
cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -532,25 +614,84 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_WTIMER0 )
- /** Wide Timer 0 clock. */
- cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+#if defined(CMU_HFPERCLKEN0_TIMER4)
+ /** Timer 4 clock. */
+ cmuClock_TIMER4 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
- | (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS)
+ | (_CMU_HFPERCLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(CMU_HFPERCLKEN0_TIMER5)
+ /** Timer 5 clock. */
+ cmuClock_TIMER5 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(CMU_HFPERCLKEN0_TIMER6)
+ /** Timer 6 clock. */
+ cmuClock_TIMER6 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_WTIMER1 )
+#if defined(CMU_HFPERCLKEN0_WTIMER0)
+ /** Wide Timer 0 clock. */
+ cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#elif defined(CMU_HFPERCLKEN1_WTIMER0)
+ /** Wide Timer 0 clock. */
+ cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN1_WTIMER0_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(CMU_HFPERCLKEN0_WTIMER1)
+ /** Wide Timer 1 clock. */
+ cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#elif defined(CMU_HFPERCLKEN1_WTIMER1)
/** Wide Timer 1 clock. */
cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
- | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
- | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
- | (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS)
- | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN1_WTIMER1_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_CRYOTIMER )
+#if defined(CMU_HFPERCLKEN1_WTIMER2)
+ /** Wide Timer 2 clock. */
+ cmuClock_WTIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN1_WTIMER2_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(CMU_HFPERCLKEN1_WTIMER3)
+ /** Wide Timer 3 clock. */
+ cmuClock_WTIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN1_WTIMER3_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(CMU_HFPERCLKEN0_CRYOTIMER)
/** CRYOtimer clock. */
cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -559,7 +700,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_ACMP0 )
+#if defined(CMU_HFPERCLKEN0_ACMP0)
/** Analog comparator 0 clock. */
cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -568,7 +709,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_ACMP1 )
+#if defined(CMU_HFPERCLKEN0_ACMP1)
/** Analog comparator 1 clock. */
cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -577,7 +718,25 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_PRS )
+#if defined(CMU_HFPERCLKEN0_ACMP2)
+ /** Analog comparator 2 clock. */
+ cmuClock_ACMP2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN0_ACMP2_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(CMU_HFPERCLKEN0_ACMP3)
+ /** Analog comparator 3 clock. */
+ cmuClock_ACMP3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN0_ACMP3_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(CMU_HFPERCLKEN0_PRS)
/** Peripheral reflex system clock. */
cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -586,7 +745,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_DAC0 )
+#if defined(CMU_HFPERCLKEN0_DAC0)
/** Digital to analog converter 0 clock. */
cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -595,16 +754,23 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_VDAC0 )
+#if defined(CMU_HFPERCLKEN0_VDAC0)
/** Voltage digital to analog converter 0 clock. */
cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
- | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
- | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
- | (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS)
- | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#elif defined(CMU_HFPERCLKEN1_VDAC0)
+ /** Voltage digital to analog converter 0 clock. */
+ cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_IDAC0 )
+#if defined(CMU_HFPERCLKEN0_IDAC0)
/** Current digital to analog converter 0 clock. */
cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -613,7 +779,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_GPIO )
+#if defined(CMU_HFPERCLKEN0_GPIO)
/** General purpose input/output clock. */
cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -622,7 +788,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_VCMP )
+#if defined(CMU_HFPERCLKEN0_VCMP)
/** Voltage comparator clock. */
cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -631,7 +797,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_ADC0 )
+#if defined(CMU_HFPERCLKEN0_ADC0)
/** Analog to digital converter 0 clock. */
cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -640,7 +806,16 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_I2C0 )
+#if defined(CMU_HFPERCLKEN0_ADC1)
+ /** Analog to digital converter 1 clock. */
+ cmuClock_ADC1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN0_ADC1_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(CMU_HFPERCLKEN0_I2C0)
/** I2C 0 clock. */
cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -649,7 +824,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_I2C1 )
+#if defined(CMU_HFPERCLKEN0_I2C1)
/** I2C 1 clock. */
cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -658,7 +833,7 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_I2C2 )
+#if defined(CMU_HFPERCLKEN0_I2C2)
/** I2C 2 clock. */
cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -667,21 +842,46 @@
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_CSEN )
+#if defined(CMU_HFPERCLKEN0_CSEN)
+ /** Capacitive Sense HF clock */
+ cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#elif defined(CMU_HFPERCLKEN1_CSEN)
/** Capacitive Sense HF clock */
cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN1_CSEN_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(CMU_HFPERCLKEN0_TRNG0)
+ /** True random number generator clock */
+ cmuClock_TRNG0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
- | (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS)
+ | (_CMU_HFPERCLKEN0_TRNG0_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFPERCLKEN0_TRNG0 )
- /** True random number generator clock */
- cmuClock_TRNG0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+#if defined(_CMU_HFPERCLKEN1_CAN0_MASK)
+ /** Controller Area Network 0 clock. */
+ cmuClock_CAN0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
- | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
- | (_CMU_HFPERCLKEN0_TRNG0_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN1_CAN0_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(_CMU_HFPERCLKEN1_CAN1_MASK)
+ /** Controller Area Network 1 clock. */
+ cmuClock_CAN1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFPERCLKEN1_CAN1_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
@@ -696,7 +896,7 @@
| (0 << CMU_EN_BIT_POS)
| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
-#if defined( CMU_HFCORECLKEN0_AES )
+#if defined(CMU_HFCORECLKEN0_AES)
/** Advanced encryption standard accelerator clock. */
cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -705,7 +905,7 @@
| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFCORECLKEN0_DMA )
+#if defined(CMU_HFCORECLKEN0_DMA)
/** Direct memory access controller clock. */
cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -714,7 +914,7 @@
| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFCORECLKEN0_LE )
+#if defined(CMU_HFCORECLKEN0_LE)
/** Low energy clock divided down from HFCORECLK. */
cmuClock_HFLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -723,32 +923,71 @@
| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFCORECLKEN0_EBI )
+#if defined(CMU_HFCORECLKEN0_EBI)
/** External bus interface clock. */
cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#elif defined(_CMU_HFBUSCLKEN0_EBI_MASK)
+ /** External bus interface clock. */
+ cmuClock_EBI = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFBUSCLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFCORECLKEN0_USBC )
+#if defined(_CMU_HFBUSCLKEN0_ETH_MASK)
+ /** Ethernet clock. */
+ cmuClock_ETH = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFBUSCLKEN0_ETH_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(_CMU_HFBUSCLKEN0_SDIO_MASK)
+ /** SDIO clock. */
+ cmuClock_SDIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFBUSCLKEN0_SDIO_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(USBC_CLOCK_PRESENT)
/** USB Core clock. */
cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS)
| (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
-
+#endif
+#if defined (USBR_CLOCK_PRESENT)
+ /** USB Rate clock. */
+ cmuClock_USBR = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_USBRCLKSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_USBRCLK_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_USBCTRL_USBCLKEN_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_HFCORECLKEN0_USB )
+#if defined(CMU_HFCORECLKEN0_USB)
/** USB clock. */
cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
| (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#elif defined(CMU_HFBUSCLKEN0_USB)
+ /** USB clock. */
+ cmuClock_USB = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_HFBUSCLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
/***************/
@@ -762,7 +1001,7 @@
| (0 << CMU_EN_BIT_POS)
| (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
-#if defined( CMU_LFACLKEN0_RTC )
+#if defined(CMU_LFACLKEN0_RTC)
/** Real time counter clock. */
cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -771,7 +1010,7 @@
| (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_LFACLKEN0_LETIMER0 )
+#if defined(CMU_LFACLKEN0_LETIMER0)
/** Low energy timer 0 clock. */
cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -780,7 +1019,16 @@
| (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_LFACLKEN0_LCD )
+#if defined(CMU_LFACLKEN0_LETIMER1)
+ /** Low energy timer 1 clock. */
+ cmuClock_LETIMER1 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
+ | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_LFACLKEN0_LETIMER1_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(CMU_LFACLKEN0_LCD)
/** Liquid crystal display, pre FDIV clock. */
cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -797,7 +1045,7 @@
| (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_PCNTCTRL_PCNT0CLKEN )
+#if defined(CMU_PCNTCTRL_PCNT0CLKEN)
/** Pulse counter 0 clock. */
cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -806,7 +1054,7 @@
| (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_PCNTCTRL_PCNT1CLKEN )
+#if defined(CMU_PCNTCTRL_PCNT1CLKEN)
/** Pulse counter 1 clock. */
cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -815,7 +1063,7 @@
| (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_PCNTCTRL_PCNT2CLKEN )
+#if defined(CMU_PCNTCTRL_PCNT2CLKEN)
/** Pulse counter 2 clock. */
cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -823,7 +1071,7 @@
| (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS)
| (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_LFACLKEN0_LESENSE )
+#if defined(CMU_LFACLKEN0_LESENSE)
/** LESENSE clock. */
cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -843,7 +1091,7 @@
| (0 << CMU_EN_BIT_POS)
| (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
-#if defined( CMU_LFBCLKEN0_LEUART0 )
+#if defined(CMU_LFBCLKEN0_LEUART0)
/** Low energy universal asynchronous receiver/transmitter 0 clock. */
cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -852,7 +1100,7 @@
| (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_LFBCLKEN0_CSEN )
+#if defined(CMU_LFBCLKEN0_CSEN)
/** Capacitive Sense LF clock. */
cmuClock_CSEN_LF = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -861,7 +1109,7 @@
| (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_LFBCLKEN0_LEUART1 )
+#if defined(CMU_LFBCLKEN0_LEUART1)
/** Low energy universal asynchronous receiver/transmitter 1 clock. */
cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -870,7 +1118,7 @@
| (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( CMU_LFBCLKEN0_SYSTICK )
+#if defined(CMU_LFBCLKEN0_SYSTICK)
/** Cortex SYSTICK LF clock. */
cmuClock_SYSTICK = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
@@ -879,7 +1127,7 @@
| (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
-#if defined( _CMU_LFCCLKEN0_MASK )
+#if defined(_CMU_LFCCLKEN0_MASK)
/***************/
/* LF C branch */
/***************/
@@ -891,30 +1139,37 @@
| (0 << CMU_EN_BIT_POS)
| (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
-#if defined( CMU_LFCCLKEN0_USBLE )
+#if defined(CMU_LFCCLKEN0_USBLE)
/** USB LE clock. */
cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
| (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
| (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
| (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS)
| (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#elif defined(CMU_LFCCLKEN0_USB)
+ /** USB LE clock. */
+ cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_LFCCLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
#endif
#endif
-#if defined( _CMU_LFECLKEN0_MASK )
+#if defined(_CMU_LFECLKEN0_MASK)
/***************/
/* LF E branch */
/***************/
- /** Low frequency A clock */
+ /** Low frequency E clock */
cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
| (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS)
| (CMU_NO_EN_REG << CMU_EN_REG_POS)
| (0 << CMU_EN_BIT_POS)
| (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
- /** Real time counter and calendar clock. */
-#if defined ( CMU_LFECLKEN0_RTCC )
+ /** Real-time counter and calendar clock. */
+#if defined (CMU_LFECLKEN0_RTCC)
cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS)
| (CMU_NOSEL_REG << CMU_SEL_REG_POS)
| (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS)
@@ -923,6 +1178,45 @@
#endif
#endif
+ /**********************************/
+ /* Asynchronous peripheral clocks */
+ /**********************************/
+
+#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK)
+ /** ADC0 asynchronous clock. */
+ cmuClock_ADC0ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS)
+ | (CMU_ADC0ASYNCSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_NO_EN_REG << CMU_EN_REG_POS)
+ | (0 << CMU_EN_BIT_POS)
+ | (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK)
+ /** ADC1 asynchronous clock. */
+ cmuClock_ADC1ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS)
+ | (CMU_ADC1ASYNCSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_NO_EN_REG << CMU_EN_REG_POS)
+ | (0 << CMU_EN_BIT_POS)
+ | (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(_CMU_SDIOCTRL_SDIOCLKDIS_MASK)
+ /** SDIO reference clock. */
+ cmuClock_SDIOREF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_SDIOREFSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_SDIOREF_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_SDIOCTRL_SDIOCLKDIS_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
+
+#if defined(_CMU_QSPICTRL_QSPI0CLKDIS_MASK)
+ /** QSPI0 reference clock. */
+ cmuClock_QSPI0REF = (CMU_NODIV_REG << CMU_DIV_REG_POS)
+ | (CMU_QSPI0REFSEL_REG << CMU_SEL_REG_POS)
+ | (CMU_QSPI0REF_EN_REG << CMU_EN_REG_POS)
+ | (_CMU_QSPICTRL_QSPI0CLKDIS_SHIFT << CMU_EN_BIT_POS)
+ | (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
+#endif
} CMU_Clock_TypeDef;
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
@@ -930,37 +1224,33 @@
#define cmuClock_CORELE cmuClock_HFLE
/** @endcond */
-
/** Oscillator types. */
-typedef enum
-{
+typedef enum {
cmuOsc_LFXO, /**< Low frequency crystal oscillator. */
cmuOsc_LFRCO, /**< Low frequency RC oscillator. */
cmuOsc_HFXO, /**< High frequency crystal oscillator. */
cmuOsc_HFRCO, /**< High frequency RC oscillator. */
cmuOsc_AUXHFRCO, /**< Auxiliary high frequency RC oscillator. */
-#if defined( _CMU_STATUS_USHFRCOENS_MASK )
+#if defined(_CMU_STATUS_USHFRCOENS_MASK)
cmuOsc_USHFRCO, /**< USB high frequency RC oscillator */
#endif
-#if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
+#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO)
cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */
#endif
-#if defined( _CMU_STATUS_PLFRCOENS_MASK )
+#if defined(_CMU_STATUS_PLFRCOENS_MASK)
cmuOsc_PLFRCO, /**< Precision Low Frequency Oscillator. */
#endif
} CMU_Osc_TypeDef;
/** Oscillator modes. */
-typedef enum
-{
+typedef enum {
cmuOscMode_Crystal, /**< Crystal oscillator. */
cmuOscMode_AcCoupled, /**< AC coupled buffer. */
cmuOscMode_External, /**< External digital clock. */
} CMU_OscMode_TypeDef;
/** Selectable clock sources. */
-typedef enum
-{
+typedef enum {
cmuSelect_Error, /**< Usage error. */
cmuSelect_Disabled, /**< Clock selector disabled. */
cmuSelect_LFXO, /**< Low frequency crystal oscillator. */
@@ -969,62 +1259,87 @@
cmuSelect_HFRCO, /**< High frequency RC oscillator. */
cmuSelect_HFCLKLE, /**< High frequency LE clock divided by 2 or 4. */
cmuSelect_AUXHFRCO, /**< Auxilliary clock source can be used for debug clock */
+ cmuSelect_HFSRCCLK, /**< High frequency source clock */
cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on
Tiny Gecko and for USBC (not used on Gecko) */
-#if defined( CMU_STATUS_USHFRCOENS )
+#if defined(CMU_STATUS_USHFRCOENS)
cmuSelect_USHFRCO, /**< USB high frequency RC oscillator */
#endif
-#if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )
- cmuSelect_USHFRCODIV2, /**< USB high frequency RC oscillator */
+#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2)
+ cmuSelect_USHFRCODIV2, /**< USB high frequency RC oscillator / 2 */
#endif
-#if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
+#if defined(CMU_HFXOCTRL_HFXOX2EN)
+ cmuSelect_HFXOX2, /**< High frequency crystal oscillator x 2. */
+#endif
+#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO)
cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */
#endif
-#if defined( _CMU_STATUS_PLFRCOENS_MASK )
+#if defined(_CMU_STATUS_PLFRCOENS_MASK)
cmuSelect_PLFRCO, /**< Precision Low Frequency Oscillator. */
#endif
} CMU_Select_TypeDef;
-#if defined( CMU_HFCORECLKEN0_LE )
+#if defined(CMU_HFCORECLKEN0_LE)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/* Deprecated CMU_Select_TypeDef member */
#define cmuSelect_CORELEDIV2 cmuSelect_HFCLKLE
/** @endcond */
#endif
-#if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
+#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK)
/** HFXO tuning modes */
-typedef enum
-{
+typedef enum {
cmuHFXOTuningMode_Auto = 0,
+ cmuHFXOTuningMode_PeakDetectCommand = CMU_CMD_HFXOPEAKDETSTART, /**< Run peak detect optimization only */
+#if defined(CMU_CMD_HFXOSHUNTOPTSTART)
cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART, /**< Run shunt current optimization only */
cmuHFXOTuningMode_PeakShuntCommand = CMU_CMD_HFXOPEAKDETSTART /**< Run peak and shunt current optimization */
| CMU_CMD_HFXOSHUNTOPTSTART,
+#endif
} CMU_HFXOTuningMode_TypeDef;
#endif
-#if defined( _CMU_CTRL_LFXOBOOST_MASK )
+#if defined(_CMU_CTRL_LFXOBOOST_MASK)
/** LFXO Boost values. */
-typedef enum
-{
+typedef enum {
cmuLfxoBoost70 = 0x0,
cmuLfxoBoost100 = 0x2,
-#if defined( _EMU_AUXCTRL_REDLFXOBOOST_MASK )
+#if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK)
cmuLfxoBoost70Reduced = 0x1,
cmuLfxoBoost100Reduced = 0x3,
#endif
} CMU_LFXOBoost_TypeDef;
#endif
+#if defined(CMU_OSCENCMD_DPLLEN)
+/** DPLL reference clock selector. */
+typedef enum {
+ cmuDPLLClkSel_Hfxo = _CMU_DPLLCTRL_REFSEL_HFXO, /**< HFXO is DPLL reference clock. */
+ cmuDPLLClkSel_Lfxo = _CMU_DPLLCTRL_REFSEL_LFXO, /**< LFXO is DPLL reference clock. */
+ cmuDPLLClkSel_Clkin0 = _CMU_DPLLCTRL_REFSEL_CLKIN0 /**< CLKIN0 is DPLL reference clock. */
+} CMU_DPLLClkSel_TypeDef;
+
+/** DPLL reference clock edge detect selector. */
+typedef enum {
+ cmuDPLLEdgeSel_Fall = _CMU_DPLLCTRL_EDGESEL_FALL, /**< Detect falling edge of reference clock. */
+ cmuDPLLEdgeSel_Rise = _CMU_DPLLCTRL_EDGESEL_RISE /**< Detect rising edge of reference clock. */
+} CMU_DPLLEdgeSel_TypeDef;
+
+/** DPLL lock mode selector. */
+typedef enum {
+ cmuDPLLLockMode_Freq = _CMU_DPLLCTRL_MODE_FREQLL, /**< Frequency lock mode. */
+ cmuDPLLLockMode_Phase = _CMU_DPLLCTRL_MODE_PHASELL /**< Phase lock mode. */
+} CMU_DPLLLockMode_TypeDef;
+#endif // CMU_OSCENCMD_DPLLEN
+
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** LFXO initialization structure. Init values should be obtained from a configuration tool,
app note or xtal datasheet */
-typedef struct
-{
-#if defined( _CMU_LFXOCTRL_MASK )
+typedef struct {
+#if defined(_CMU_LFXOCTRL_MASK)
uint8_t ctune; /**< CTUNE (load capacitance) value */
uint8_t gain; /**< Gain / max startup margin */
#else
@@ -1034,15 +1349,15 @@
CMU_OscMode_TypeDef mode; /**< Oscillator mode */
} CMU_LFXOInit_TypeDef;
-#if defined( _CMU_LFXOCTRL_MASK )
+#if defined(_CMU_LFXOCTRL_MASK)
/** Default LFXO initialization values for platform 2 devices which contain a
* separate LFXOCTRL register. */
-#define CMU_LFXOINIT_DEFAULT \
- { \
- _CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \
- _CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \
- _CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32k cycles */ \
- cmuOscMode_Crystal, /* Crystal oscillator */ \
+#define CMU_LFXOINIT_DEFAULT \
+ { \
+ _CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \
+ _CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \
+ _CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32k cycles */ \
+ cmuOscMode_Crystal, /* Crystal oscillator */ \
}
#define CMU_LFXOINIT_EXTERNAL_CLOCK \
{ \
@@ -1053,25 +1368,32 @@
}
#else
/** Default LFXO initialization values for platform 1 devices. */
-#define CMU_LFXOINIT_DEFAULT \
- { \
- cmuLfxoBoost70, \
- _CMU_CTRL_LFXOTIMEOUT_DEFAULT, \
- cmuOscMode_Crystal, \
+#define CMU_LFXOINIT_DEFAULT \
+ { \
+ cmuLfxoBoost70, \
+ _CMU_CTRL_LFXOTIMEOUT_DEFAULT, \
+ cmuOscMode_Crystal, \
}
-#define CMU_LFXOINIT_EXTERNAL_CLOCK \
- { \
- cmuLfxoBoost70, \
- _CMU_CTRL_LFXOTIMEOUT_8CYCLES, \
- cmuOscMode_External, \
+#define CMU_LFXOINIT_EXTERNAL_CLOCK \
+ { \
+ cmuLfxoBoost70, \
+ _CMU_CTRL_LFXOTIMEOUT_8CYCLES, \
+ cmuOscMode_External, \
}
#endif
/** HFXO initialization structure. Init values should be obtained from a configuration tool,
app note or xtal datasheet */
-typedef struct
-{
-#if defined( _CMU_HFXOCTRL_MASK )
+typedef struct {
+#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100)
+ uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */
+ uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */
+ uint16_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */
+ uint16_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */
+ uint8_t timeoutPeakDetect; /**< Timeout - peak detection */
+ uint8_t timeoutSteady; /**< Timeout - steady-state */
+ uint8_t timeoutStartup; /**< Timeout - startup */
+#elif defined(_CMU_HFXOCTRL_MASK)
bool lowPowerMode; /**< Enable low-power mode */
bool autoStartEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
bool autoSelEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */
@@ -1094,105 +1416,159 @@
CMU_OscMode_TypeDef mode; /**< Oscillator mode */
} CMU_HFXOInit_TypeDef;
-#if defined( _CMU_HFXOCTRL_MASK )
+#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100)
+#define CMU_HFXOINIT_DEFAULT \
+ { \
+ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
+ _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
+ _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \
+ _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \
+ _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \
+ _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \
+ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
+ cmuOscMode_Crystal, \
+ }
+#define CMU_HFXOINIT_EXTERNAL_CLOCK \
+ { \
+ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
+ _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
+ _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \
+ _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \
+ _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \
+ _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \
+ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
+ cmuOscMode_External, \
+ }
+#elif defined(_CMU_HFXOCTRL_MASK)
/**
* Default HFXO initialization values for Platform 2 devices which contain a
* separate HFXOCTRL register.
*/
-#if defined( _EFR_DEVICE )
-#define CMU_HFXOINIT_DEFAULT \
-{ \
- false, /* Low-noise mode for EFR32 */ \
- false, /* @deprecated no longer in use */ \
- false, /* @deprecated no longer in use */ \
- false, /* @deprecated no longer in use */ \
- _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
- _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
- _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
- 0x20, /* Matching errata fix in CHIP_Init() */ \
- 0x7, /* Recommended steady-state XO core bias current */ \
- 0x6, /* Recommended peak detection threshold */ \
- _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
- 0xA, /* Recommended peak detection timeout */ \
- 0x4, /* Recommended steady timeout */ \
- _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
- cmuOscMode_Crystal, \
-}
+#if defined(_EFR_DEVICE)
+#define CMU_HFXOINIT_DEFAULT \
+ { \
+ false, /* Low-noise mode for EFR32 */ \
+ false, /* @deprecated no longer in use */ \
+ false, /* @deprecated no longer in use */ \
+ false, /* @deprecated no longer in use */ \
+ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
+ _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
+ 0xA, /* Default Shunt steady-state current */ \
+ 0x20, /* Matching errata fix in @ref CHIP_Init() */ \
+ 0x7, /* Recommended steady-state XO core bias current */ \
+ 0x6, /* Recommended peak detection threshold */ \
+ 0x2, /* Recommended shunt optimization timeout */ \
+ 0xA, /* Recommended peak detection timeout */ \
+ 0x4, /* Recommended steady timeout */ \
+ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
+ cmuOscMode_Crystal, \
+ }
#else /* EFM32 device */
-#define CMU_HFXOINIT_DEFAULT \
-{ \
- true, /* Low-power mode for EFM32 */ \
- false, /* @deprecated no longer in use */ \
- false, /* @deprecated no longer in use */ \
- false, /* @deprecated no longer in use */ \
- _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
- _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
- _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
- 0x20, /* Matching errata fix in CHIP_Init() */ \
- 0x7, /* Recommended steady-state osc core bias current */ \
- 0x6, /* Recommended peak detection threshold */ \
- _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
- 0xA, /* Recommended peak detection timeout */ \
- 0x4, /* Recommended steady timeout */ \
- _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
- cmuOscMode_Crystal, \
-}
+#define CMU_HFXOINIT_DEFAULT \
+ { \
+ true, /* Low-power mode for EFM32 */ \
+ false, /* @deprecated no longer in use */ \
+ false, /* @deprecated no longer in use */ \
+ false, /* @deprecated no longer in use */ \
+ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
+ _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
+ 0xA, /* Default shunt steady-state current */ \
+ 0x20, /* Matching errata fix in @ref CHIP_Init() */ \
+ 0x7, /* Recommended steady-state osc core bias current */ \
+ 0x6, /* Recommended peak detection threshold */ \
+ 0x2, /* Recommended shunt optimization timeout */ \
+ 0xA, /* Recommended peak detection timeout */ \
+ 0x4, /* Recommended steady timeout */ \
+ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
+ cmuOscMode_Crystal, \
+ }
#endif /* _EFR_DEVICE */
-#define CMU_HFXOINIT_EXTERNAL_CLOCK \
-{ \
- true, /* Low-power mode */ \
- false, /* @deprecated no longer in use */ \
- false, /* @deprecated no longer in use */ \
- false, /* @deprecated no longer in use */ \
- 0, /* Startup CTUNE=0 recommended for external clock */ \
- 0, /* Steady CTUNE=0 recommended for external clock */ \
- _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
- 0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \
- 0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \
- 0x6, /* Recommended peak detection threshold */ \
- _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
- 0x0, /* Peak-detect not recommended for external clock usage */ \
- _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \
- _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \
- cmuOscMode_External, \
-}
+#define CMU_HFXOINIT_EXTERNAL_CLOCK \
+ { \
+ true, /* Low-power mode */ \
+ false, /* @deprecated no longer in use */ \
+ false, /* @deprecated no longer in use */ \
+ false, /* @deprecated no longer in use */ \
+ 0, /* Startup CTUNE=0 recommended for external clock */ \
+ 0, /* Steady CTUNE=0 recommended for external clock */ \
+ 0xA, /* Default shunt steady-state current */ \
+ 0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \
+ 0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \
+ 0x6, /* Recommended peak detection threshold */ \
+ 0x2, /* Recommended shunt optimization timeout */ \
+ 0x0, /* Peak-detect not recommended for external clock usage */ \
+ _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \
+ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \
+ cmuOscMode_External, \
+ }
#else /* _CMU_HFXOCTRL_MASK */
/**
* Default HFXO initialization values for Platform 1 devices.
*/
-#define CMU_HFXOINIT_DEFAULT \
-{ \
- _CMU_CTRL_HFXOBOOST_DEFAULT, /* 100% HFXO boost */ \
- _CMU_CTRL_HFXOTIMEOUT_DEFAULT, /* 16k startup delay */ \
- false, /* Disable glitch detector */ \
- cmuOscMode_Crystal, /* Crystal oscillator */ \
-}
-#define CMU_HFXOINIT_EXTERNAL_CLOCK \
-{ \
- 0, /* Minimal HFXO boost, 50% */ \
- _CMU_CTRL_HFXOTIMEOUT_8CYCLES, /* Minimal startup delay, 8 cycles */ \
- false, /* Disable glitch detector */ \
- cmuOscMode_External, /* External digital clock */ \
-}
+#define CMU_HFXOINIT_DEFAULT \
+ { \
+ _CMU_CTRL_HFXOBOOST_DEFAULT, /* 100% HFXO boost */ \
+ _CMU_CTRL_HFXOTIMEOUT_DEFAULT, /* 16k startup delay */ \
+ false, /* Disable glitch detector */ \
+ cmuOscMode_Crystal, /* Crystal oscillator */ \
+ }
+#define CMU_HFXOINIT_EXTERNAL_CLOCK \
+ { \
+ 0, /* Minimal HFXO boost, 50% */ \
+ _CMU_CTRL_HFXOTIMEOUT_8CYCLES, /* Minimal startup delay, 8 cycles */ \
+ false, /* Disable glitch detector */ \
+ cmuOscMode_External, /* External digital clock */ \
+ }
#endif /* _CMU_HFXOCTRL_MASK */
+#if defined(CMU_OSCENCMD_DPLLEN)
+/** DPLL initialization structure. Frequency will be Fref*(N+1)/(M+1). */
+typedef struct {
+ uint32_t frequency; /**< PLL frequency value, max 40 MHz. */
+ uint16_t n; /**< Factor N. 32 <= N <= 4095 */
+ uint16_t m; /**< Factor M. M <= 4095 */
+ uint8_t ssInterval; /**< Spread spectrum update interval. */
+ uint8_t ssAmplitude; /**< Spread spectrum amplitude. */
+ CMU_DPLLClkSel_TypeDef refClk; /**< Reference clock selector. */
+ CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */
+ CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */
+ bool autoRecover; /**< Enable automatic lock recovery. */
+} CMU_DPLLInit_TypeDef;
+
+/**
+ * DPLL initialization values for 39,998,805 Hz using LFXO as reference
+ * clock, M=2 and N=3661.
+ */
+#define CMU_DPLL_LFXO_TO_40MHZ \
+ { \
+ 39998805, /* Target frequency. */ \
+ 3661, /* Factor N. */ \
+ 2, /* Factor M. */ \
+ 0, /* No spread spectrum clocking. */ \
+ 0, /* No spread spectrum clocking. */ \
+ cmuDPLLClkSel_Lfxo, /* Select LFXO as reference clock. */ \
+ cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
+ cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
+ true /* Enable automatic lock recovery. */ \
+ }
+#endif // CMU_OSCENCMD_DPLLEN
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
-#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
+#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK)
CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void);
void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band);
-#elif defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
+#elif defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void);
void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq);
#endif
uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
-#if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
+#if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK)
void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
CMU_Osc_TypeDef upSel);
#endif
@@ -1203,20 +1579,24 @@
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, uint32_t presc);
uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock);
#endif
void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
+
+#if defined(CMU_OSCENCMD_DPLLEN)
+bool CMU_DPLLLock(CMU_DPLLInit_TypeDef *init);
+#endif
void CMU_FreezeEnable(bool enable);
-#if defined( _CMU_HFRCOCTRL_BAND_MASK )
+#if defined(_CMU_HFRCOCTRL_BAND_MASK)
CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);
void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);
-#elif defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
+#elif defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void);
void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq);
#endif
@@ -1224,7 +1604,12 @@
uint32_t CMU_HFRCOStartupDelayGet(void);
void CMU_HFRCOStartupDelaySet(uint32_t delay);
-#if defined( _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK )
+#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK)
+CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void);
+void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq);
+#endif
+
+#if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK)
void CMU_HFXOAutostartEnable(uint32_t userSel,
bool enEM0EM1Start,
bool enEM0EM1StartSel);
@@ -1232,7 +1617,6 @@
void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit);
-
uint32_t CMU_LCDClkFDIVGet(void);
void CMU_LCDClkFDIVSet(uint32_t div);
void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit);
@@ -1241,23 +1625,24 @@
uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
-#if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
+#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK)
bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode);
bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc,
CMU_HFXOTuningMode_TypeDef mode,
bool wait);
#endif
+void CMU_UpdateWaitStates(uint32_t freq, int vscale);
bool CMU_PCNTClockExternalGet(unsigned int instance);
void CMU_PCNTClockExternalSet(unsigned int instance, bool external);
-#if defined( _CMU_USHFRCOCONF_BAND_MASK )
+#if defined(_CMU_USHFRCOCONF_BAND_MASK)
CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void);
void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);
#endif
-
+void CMU_UpdateWaitStates(uint32_t freq, int vscale);
-#if defined( CMU_CALCTRL_CONT )
+#if defined(CMU_CALCTRL_CONT)
/***************************************************************************//**
* @brief
* Configures continuous calibration mode
@@ -1271,21 +1656,19 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Starts calibration
* @note
- * This call is usually invoked after CMU_CalibrateConfig() and possibly
- * CMU_CalibrateCont()
+ * This call is usually invoked after @ref CMU_CalibrateConfig() and possibly
+ * @ref CMU_CalibrateCont()
******************************************************************************/
__STATIC_INLINE void CMU_CalibrateStart(void)
{
CMU->CMD = CMU_CMD_CALSTART;
}
-
-#if defined( CMU_CMD_CALSTOP )
+#if defined(CMU_CMD_CALSTOP)
/***************************************************************************//**
* @brief
* Stop the calibration counters
@@ -1296,7 +1679,6 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Convert dividend to logarithmic value. Only works for even
@@ -1321,6 +1703,18 @@
return log2;
}
+#if defined(CMU_OSCENCMD_DPLLEN)
+/***************************************************************************//**
+ * @brief
+ * Unlock the DPLL.
+ * @note
+ * The HFRCO is not turned off.
+ ******************************************************************************/
+__STATIC_INLINE void CMU_DPLLUnlock(void)
+{
+ CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS;
+}
+#endif
/***************************************************************************//**
* @brief
@@ -1334,7 +1728,6 @@
CMU->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more CMU interrupts.
@@ -1347,14 +1740,13 @@
CMU->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more CMU interrupts.
*
* @note
* Depending on the use, a pending interrupt may already be set prior to
- * enabling the interrupt. Consider using CMU_IntClear() prior to enabling
+ * enabling the interrupt. Consider using @ref CMU_IntClear() prior to enabling
* if such a pending interrupt should be ignored.
*
* @param[in] flags
@@ -1365,7 +1757,6 @@
CMU->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending CMU interrupts.
@@ -1378,7 +1769,6 @@
return CMU->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending CMU interrupt flags.
@@ -1403,7 +1793,6 @@
return CMU->IF & ien;
}
-
/**************************************************************************//**
* @brief
* Set one or more pending CMU interrupts.
@@ -1416,7 +1805,6 @@
CMU->IFS = flags;
}
-
/***************************************************************************//**
* @brief
* Lock the CMU in order to protect some of its registers against unintended
@@ -1435,7 +1823,6 @@
CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
}
-
/***************************************************************************//**
* @brief
* Convert logarithm of 2 prescaler to division factor.
@@ -1451,8 +1838,7 @@
return 1 << log2;
}
-
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
/***************************************************************************//**
* @brief
* Convert prescaler dividend to logarithmic value. Only works for even
@@ -1481,7 +1867,6 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Unlock the CMU so that writing to locked registers again is possible.
@@ -1491,8 +1876,7 @@
CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
}
-
-#if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
+#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
/***************************************************************************//**
* @brief
* Get current HFRCO frequency.
@@ -1508,7 +1892,6 @@
return CMU_HFRCOBandGet();
}
-
/***************************************************************************//**
* @brief
* Set HFRCO calibration for the selected target frequency
@@ -1525,8 +1908,7 @@
}
#endif
-
-#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
+#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
/***************************************************************************//**
* @brief
* Get current AUXHFRCO frequency.
@@ -1542,7 +1924,6 @@
return CMU_AUXHFRCOBandGet();
}
-
/***************************************************************************//**
* @brief
* Set AUXHFRCO calibration for the selected target frequency
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_common.h
* @brief General purpose utilities.
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -116,7 +116,7 @@
#if defined(__ICCARM__)
/** @brief IAR Embedded Workbench: Macros for handling aligned structs. */
-#define SL_ALIGN(X) _Pragma(STRINGIZE(data_alignment=X))
+#define SL_ALIGN(X) _Pragma(STRINGIZE(data_alignment = X))
/** @brief IAR Embedded Workbench: Macros for handling weak symbols. */
#define SL_WEAK __weak
@@ -124,9 +124,11 @@
/** @brief IAR Embedded Workbench: Macro for handling non-returning functions. */
#define SL_NORETURN __noreturn
+/* *INDENT-OFF* */
/** IAR Embedded Workbench: Macro for handling section placement */
#define SL_ATTRIBUTE_SECTION(X) @ X
#endif
+/* *INDENT-ON* */
#define SL_ATTRIBUTE_ALIGN(X)
@@ -134,10 +136,10 @@
/* GCC compilers */
/** @brief Macro for getting minimum value. No sideeffects, a and b are evaluated once only. */
-#define SL_MIN(a, b) __extension__({__typeof__(a) _a = (a); __typeof__(b) _b = (b); _a < _b ? _a : _b;})
+#define SL_MIN(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a < _b ? _a : _b; })
/** @brief Macro for getting maximum value. No sideeffects, a and b are evaluated once only. */
-#define SL_MAX(a, b) __extension__({__typeof__(a) _a = (a); __typeof__(b) _b = (b); _a > _b ? _a : _b;})
+#define SL_MAX(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a > _b ? _a : _b; })
/** @brief GCC style macro for handling packed structs. */
#define SL_ATTRIBUTE_PACKED __attribute__ ((packed))
@@ -198,18 +200,63 @@
#else
uint32_t zeros;
- for(zeros=0; (zeros<32) && ((value&0x1) == 0); zeros++, value>>=1);
+ for (zeros = 0; (zeros < 32) && ((value & 0x1) == 0); zeros++, value >>= 1) {
+ ;
+ }
return zeros;
#endif
}
-
/* Deprecated function. New code should use @ref SL_CTZ. */
__STATIC_INLINE uint32_t EFM32_CTZ(uint32_t value)
{
return SL_CTZ(value);
}
+/***************************************************************************//**
+ * @brief
+ * Reverse the bits. Use the RBIT instruction if available, else process.
+ *
+ * @param[in] value
+ * Data value to reverse.
+ *
+ * @return
+ * Reversed value.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t SL_RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if (__CORTEX_M >= 0x03U)
+ result = __RBIT(value);
+#else
+ int32_t s = 4 * 8 - 1;
+
+ result = value;
+ for (value >>= 1U; value; value >>= 1U) {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s;
+#endif
+ return result;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Reverse the bits. Use the RBIT instruction if available, else process.
+ *
+ * @param[in] value
+ * 16-bit data value to reverse.
+ *
+ * @return
+ * 16-bit reversed value.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t SL_RBIT16(uint32_t value)
+{
+ return SL_RBIT(value) >> 16;
+}
/** @} (end addtogroup COMMON) */
/** @} (end addtogroup emlib) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_core.h
* @brief Core interrupt handling API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -92,14 +92,14 @@
/** Convenience macro for implementing a CRITICAL section. */
#define CORE_CRITICAL_SECTION(yourcode) \
-{ \
- CORE_DECLARE_IRQ_STATE; \
- CORE_ENTER_CRITICAL(); \
{ \
- yourcode \
- } \
- CORE_EXIT_CRITICAL(); \
-}
+ CORE_DECLARE_IRQ_STATE; \
+ CORE_ENTER_CRITICAL(); \
+ { \
+ yourcode \
+ } \
+ CORE_EXIT_CRITICAL(); \
+ }
/** Enter CRITICAL section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in
* scope. */
@@ -110,7 +110,7 @@
#define CORE_EXIT_CRITICAL() CORE_ExitCritical(irqState)
/** CRITICAL style yield. */
-#define CORE_YIELD_CRITICAL() CORE_YieldCritical(void)
+#define CORE_YIELD_CRITICAL() CORE_YieldCritical()
//
// ATOMIC section macro API.
@@ -124,14 +124,14 @@
/** Convenience macro for implementing an ATOMIC section. */
#define CORE_ATOMIC_SECTION(yourcode) \
-{ \
- CORE_DECLARE_IRQ_STATE; \
- CORE_ENTER_ATOMIC(); \
{ \
- yourcode \
- } \
- CORE_EXIT_ATOMIC(); \
-}
+ CORE_DECLARE_IRQ_STATE; \
+ CORE_ENTER_ATOMIC(); \
+ { \
+ yourcode \
+ } \
+ CORE_EXIT_ATOMIC(); \
+ }
/** Enter ATOMIC section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in
* scope. */
@@ -142,7 +142,7 @@
#define CORE_EXIT_ATOMIC() CORE_ExitAtomic(irqState)
/** ATOMIC style yield. */
-#define CORE_YIELD_ATOMIC() CORE_YieldAtomic(void)
+#define CORE_YIELD_ATOMIC() CORE_YieldAtomic()
//
// NVIC mask section macro API.
@@ -160,7 +160,7 @@
/** Allocate storage for and zero initialize NVIC interrupt mask.
* @param[in] x
* The storage variable name to use.*/
-#define CORE_DECLARE_NVIC_ZEROMASK(x) CORE_nvicMask_t x = {{0}}
+#define CORE_DECLARE_NVIC_ZEROMASK(x) CORE_nvicMask_t x = { { 0 } }
/** NVIC mask style interrupt disable.
* @param[in] mask
@@ -177,21 +177,21 @@
* Mask specifying which NVIC interrupts to disable within the section.
* @param[in] yourcode
* The code for the section. */
-#define CORE_NVIC_SECTION(mask, yourcode) \
-{ \
- CORE_DECLARE_NVIC_STATE; \
- CORE_ENTER_NVIC(mask); \
- { \
- yourcode \
- } \
- CORE_EXIT_NVIC(); \
-}
+#define CORE_NVIC_SECTION(mask, yourcode) \
+ { \
+ CORE_DECLARE_NVIC_STATE; \
+ CORE_ENTER_NVIC(mask); \
+ { \
+ yourcode \
+ } \
+ CORE_EXIT_NVIC(); \
+ }
/** Enter NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist
* in scope.
* @param[in] disable
* Mask specifying which NVIC interrupts to disable within the section. */
-#define CORE_ENTER_NVIC(disable) CORE_EnterNvicMask(&nvicState,disable)
+#define CORE_ENTER_NVIC(disable) CORE_EnterNvicMask(&nvicState, disable)
/** Exit NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist
* in scope. */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_cryotimer.h
* @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -116,8 +116,7 @@
******************************************************************************/
/** Prescaler selection. */
-typedef enum
-{
+typedef enum {
cryotimerPresc_1 = _CRYOTIMER_CTRL_PRESC_DIV1, /**< Divide clock by 1. */
cryotimerPresc_2 = _CRYOTIMER_CTRL_PRESC_DIV2, /**< Divide clock by 2. */
cryotimerPresc_4 = _CRYOTIMER_CTRL_PRESC_DIV4, /**< Divide clock by 4. */
@@ -129,16 +128,14 @@
} CRYOTIMER_Presc_TypeDef;
/** Low frequency oscillator selection. */
-typedef enum
-{
+typedef enum {
cryotimerOscLFRCO = _CRYOTIMER_CTRL_OSCSEL_LFRCO, /**< Select Low Frequency RC Oscillator. */
cryotimerOscLFXO = _CRYOTIMER_CTRL_OSCSEL_LFXO, /**< Select Low Frequency Crystal Oscillator. */
cryotimerOscULFRCO = _CRYOTIMER_CTRL_OSCSEL_ULFRCO, /**< Select Ultra Low Frequency RC Oscillator. */
} CRYOTIMER_Osc_TypeDef;
/** Period selection value */
-typedef enum
-{
+typedef enum {
cryotimerPeriod_1 = 0, /**< Wakeup event after every Pre-scaled clock cycle. */
cryotimerPeriod_2 = 1, /**< Wakeup event after 2 Pre-scaled clock cycles. */
cryotimerPeriod_4 = 2, /**< Wakeup event after 4 Pre-scaled clock cycles. */
@@ -179,8 +176,7 @@
******************************************************************************/
/** CRYOTIMER initialization structure. */
-typedef struct
-{
+typedef struct {
/** Enable/disable counting when initialization is completed. */
bool enable;
@@ -205,15 +201,15 @@
******************************************************************************/
/** Default CRYOTIMER init structure. */
-#define CRYOTIMER_INIT_DEFAULT \
-{ \
- true, /* Start counting when init done. */ \
- false, /* Disable CRYOTIMER during debug halt. */ \
- false, /* Disable EM4 wakeup. */ \
- cryotimerOscLFRCO, /* Select Low Frequency RC Oscillator. */ \
- cryotimerPresc_1, /* LF Oscillator frequency undivided. */ \
- cryotimerPeriod_4096m, /* Wakeup event after 4096M pre-scaled clock cycles. */ \
-}
+#define CRYOTIMER_INIT_DEFAULT \
+ { \
+ true, /* Start counting when init done. */ \
+ false, /* Disable CRYOTIMER during debug halt. */ \
+ false, /* Disable EM4 wakeup. */ \
+ cryotimerOscLFRCO, /* Select Low Frequency RC Oscillator. */ \
+ cryotimerPresc_1, /* LF Oscillator frequency undivided. */ \
+ cryotimerPeriod_4096m, /* Wakeup event after 4096M pre-scaled clock cycles. */ \
+ }
/*******************************************************************************
***************************** PROTOTYPES **********************************
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_crypto.h
* @brief Cryptography accelerator peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -187,37 +187,46 @@
* @{
******************************************************************************/
- /*******************************************************************************
+/*******************************************************************************
****************************** DEFINES ***********************************
******************************************************************************/
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+/** Default CRYPTO instance for deprecated AES functions. */
+#if !defined(DEFAULT_CRYPTO)
+#if defined(CRYPTO)
+#define DEFAULT_CRYPTO CRYPTO
+#elif defined(CRYPTO0)
+#define DEFAULT_CRYPTO CRYPTO0
+#endif
+#endif
+
/** Data sizes used by CRYPTO operations. */
#define CRYPTO_DATA_SIZE_IN_BITS (128)
-#define CRYPTO_DATA_SIZE_IN_BYTES (CRYPTO_DATA_SIZE_IN_BITS/8)
-#define CRYPTO_DATA_SIZE_IN_32BIT_WORDS (CRYPTO_DATA_SIZE_IN_BYTES/sizeof(uint32_t))
+#define CRYPTO_DATA_SIZE_IN_BYTES (CRYPTO_DATA_SIZE_IN_BITS / 8)
+#define CRYPTO_DATA_SIZE_IN_32BIT_WORDS (CRYPTO_DATA_SIZE_IN_BYTES / sizeof(uint32_t))
#define CRYPTO_KEYBUF_SIZE_IN_BITS (256)
-#define CRYPTO_KEYBUF_SIZE_IN_BYTES (CRYPTO_DDATA_SIZE_IN_BITS/8)
-#define CRYPTO_KEYBUF_SIZE_IN_32BIT_WORDS (CRYPTO_DDATA_SIZE_IN_BYTES/sizeof(uint32_t))
+#define CRYPTO_KEYBUF_SIZE_IN_BYTES (CRYPTO_DDATA_SIZE_IN_BITS / 8)
+#define CRYPTO_KEYBUF_SIZE_IN_32BIT_WORDS (CRYPTO_DDATA_SIZE_IN_BYTES / sizeof(uint32_t))
#define CRYPTO_DDATA_SIZE_IN_BITS (256)
-#define CRYPTO_DDATA_SIZE_IN_BYTES (CRYPTO_DDATA_SIZE_IN_BITS/8)
-#define CRYPTO_DDATA_SIZE_IN_32BIT_WORDS (CRYPTO_DDATA_SIZE_IN_BYTES/sizeof(uint32_t))
+#define CRYPTO_DDATA_SIZE_IN_BYTES (CRYPTO_DDATA_SIZE_IN_BITS / 8)
+#define CRYPTO_DDATA_SIZE_IN_32BIT_WORDS (CRYPTO_DDATA_SIZE_IN_BYTES / sizeof(uint32_t))
#define CRYPTO_QDATA_SIZE_IN_BITS (512)
-#define CRYPTO_QDATA_SIZE_IN_BYTES (CRYPTO_QDATA_SIZE_IN_BITS/8)
-#define CRYPTO_QDATA_SIZE_IN_32BIT_WORDS (CRYPTO_QDATA_SIZE_IN_BYTES/sizeof(uint32_t))
+#define CRYPTO_QDATA_SIZE_IN_BYTES (CRYPTO_QDATA_SIZE_IN_BITS / 8)
+#define CRYPTO_QDATA_SIZE_IN_32BIT_WORDS (CRYPTO_QDATA_SIZE_IN_BYTES / sizeof(uint32_t))
#define CRYPTO_DATA260_SIZE_IN_32BIT_WORDS (9)
/** SHA-1 digest sizes */
#define CRYPTO_SHA1_DIGEST_SIZE_IN_BITS (160)
-#define CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES (CRYPTO_SHA1_DIGEST_SIZE_IN_BITS/8)
+#define CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES (CRYPTO_SHA1_DIGEST_SIZE_IN_BITS / 8)
/** SHA-256 digest sizes */
#define CRYPTO_SHA256_DIGEST_SIZE_IN_BITS (256)
-#define CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES (CRYPTO_SHA256_DIGEST_SIZE_IN_BITS/8)
+#define CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES (CRYPTO_SHA256_DIGEST_SIZE_IN_BITS / 8)
/**
* Read and write all 260 bits of DDATA0 when in 260 bit mode.
@@ -233,89 +242,89 @@
* Use these macros in order for faster execution than the function API.
*/
#define CRYPTO_SEQ_LOAD_1(crypto, a1) { \
- crypto->SEQ0 = a1 | (CRYPTO_CMD_INSTR_END<<8);}
+ crypto->SEQ0 = a1 | (CRYPTO_CMD_INSTR_END << 8); }
#define CRYPTO_SEQ_LOAD_2(crypto, a1, a2) { \
- crypto->SEQ0 = a1 | (a2<<8) | (CRYPTO_CMD_INSTR_END<<16);}
+ crypto->SEQ0 = a1 | (a2 << 8) | (CRYPTO_CMD_INSTR_END << 16); }
#define CRYPTO_SEQ_LOAD_3(crypto, a1, a2, a3) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (CRYPTO_CMD_INSTR_END<<24);}
-#define CRYPTO_SEQ_LOAD_4(crypto, a1, a2, a3, a4) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = CRYPTO_CMD_INSTR_END;}
-#define CRYPTO_SEQ_LOAD_5(crypto, a1, a2, a3, a4, a5) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (CRYPTO_CMD_INSTR_END<<8);}
-#define CRYPTO_SEQ_LOAD_6(crypto, a1, a2, a3, a4, a5, a6) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (CRYPTO_CMD_INSTR_END<<16);}
-#define CRYPTO_SEQ_LOAD_7(crypto, a1, a2, a3, a4, a5, a6, a7) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (CRYPTO_CMD_INSTR_END<<24);}
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (CRYPTO_CMD_INSTR_END << 24); }
+#define CRYPTO_SEQ_LOAD_4(crypto, a1, a2, a3, a4) { \
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = CRYPTO_CMD_INSTR_END; }
+#define CRYPTO_SEQ_LOAD_5(crypto, a1, a2, a3, a4, a5) { \
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (CRYPTO_CMD_INSTR_END << 8); }
+#define CRYPTO_SEQ_LOAD_6(crypto, a1, a2, a3, a4, a5, a6) { \
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (CRYPTO_CMD_INSTR_END << 16); }
+#define CRYPTO_SEQ_LOAD_7(crypto, a1, a2, a3, a4, a5, a6, a7) { \
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (CRYPTO_CMD_INSTR_END << 24); }
#define CRYPTO_SEQ_LOAD_8(crypto, a1, a2, a3, a4, a5, a6, a7, a8) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = CRYPTO_CMD_INSTR_END;}
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = CRYPTO_CMD_INSTR_END; }
#define CRYPTO_SEQ_LOAD_9(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (CRYPTO_CMD_INSTR_END<<8);}
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (CRYPTO_CMD_INSTR_END << 8); }
#define CRYPTO_SEQ_LOAD_10(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (CRYPTO_CMD_INSTR_END<<16);}
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (CRYPTO_CMD_INSTR_END << 16); }
#define CRYPTO_SEQ_LOAD_11(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (CRYPTO_CMD_INSTR_END<<24);}
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (CRYPTO_CMD_INSTR_END << 24); }
#define CRYPTO_SEQ_LOAD_12(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = CRYPTO_CMD_INSTR_END;}
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = CRYPTO_CMD_INSTR_END; }
#define CRYPTO_SEQ_LOAD_13(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (CRYPTO_CMD_INSTR_END<<8);}
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (CRYPTO_CMD_INSTR_END << 8); }
#define CRYPTO_SEQ_LOAD_14(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (a14<<8) | (CRYPTO_CMD_INSTR_END<<16);}
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (a14 << 8) | (CRYPTO_CMD_INSTR_END << 16); }
#define CRYPTO_SEQ_LOAD_15(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (CRYPTO_CMD_INSTR_END<<24);}
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (CRYPTO_CMD_INSTR_END << 24); }
#define CRYPTO_SEQ_LOAD_16(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
- crypto->SEQ4 = CRYPTO_CMD_INSTR_END;}
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
+ crypto->SEQ4 = CRYPTO_CMD_INSTR_END; }
#define CRYPTO_SEQ_LOAD_17(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
- crypto->SEQ4 = a17 | (CRYPTO_CMD_INSTR_END<<8);}
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
+ crypto->SEQ4 = a17 | (CRYPTO_CMD_INSTR_END << 8); }
#define CRYPTO_SEQ_LOAD_18(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
- crypto->SEQ4 = a17 | (a18<<8) | (CRYPTO_CMD_INSTR_END<<16);}
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
+ crypto->SEQ4 = a17 | (a18 << 8) | (CRYPTO_CMD_INSTR_END << 16); }
#define CRYPTO_SEQ_LOAD_19(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
- crypto->SEQ4 = a17 | (a18<<8) | (a19<<16) | (CRYPTO_CMD_INSTR_END<<24);}
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
+ crypto->SEQ4 = a17 | (a18 << 8) | (a19 << 16) | (CRYPTO_CMD_INSTR_END << 24); }
#define CRYPTO_SEQ_LOAD_20(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
- crypto->SEQ4 = a17 | (a18<<8) | (a19<<16) | (a20<<24);}
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
+ crypto->SEQ4 = a17 | (a18 << 8) | (a19 << 16) | (a20 << 24); }
/** @endcond */
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
@@ -324,91 +333,91 @@
* 1-20). E.g. @ref CRYPTO_EXECUTE_19.
* Use these macros in order for faster execution than the function API.
*/
-#define CRYPTO_EXECUTE_1(crypto, a1) { \
- crypto->SEQ0 = a1 | (CRYPTO_CMD_INSTR_EXEC<<8); }
-#define CRYPTO_EXECUTE_2(crypto, a1, a2) { \
- crypto->SEQ0 = a1 | (a2<<8) | (CRYPTO_CMD_INSTR_EXEC<<16); }
-#define CRYPTO_EXECUTE_3(crypto, a1, a2, a3) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }
-#define CRYPTO_EXECUTE_4(crypto, a1, a2, a3, a4) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
+#define CRYPTO_EXECUTE_1(crypto, a1) { \
+ crypto->SEQ0 = a1 | (CRYPTO_CMD_INSTR_EXEC << 8); }
+#define CRYPTO_EXECUTE_2(crypto, a1, a2) { \
+ crypto->SEQ0 = a1 | (a2 << 8) | (CRYPTO_CMD_INSTR_EXEC << 16); }
+#define CRYPTO_EXECUTE_3(crypto, a1, a2, a3) { \
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (CRYPTO_CMD_INSTR_EXEC << 24); }
+#define CRYPTO_EXECUTE_4(crypto, a1, a2, a3, a4) { \
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
crypto->SEQ1 = CRYPTO_CMD_INSTR_EXEC; }
-#define CRYPTO_EXECUTE_5(crypto, a1, a2, a3, a4, a5) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (CRYPTO_CMD_INSTR_EXEC<<8); }
-#define CRYPTO_EXECUTE_6(crypto, a1, a2, a3, a4, a5, a6) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (CRYPTO_CMD_INSTR_EXEC<<16); }
-#define CRYPTO_EXECUTE_7(crypto, a1, a2, a3, a4, a5, a6, a7) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }
-#define CRYPTO_EXECUTE_8(crypto, a1, a2, a3, a4, a5, a6, a7, a8) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
+#define CRYPTO_EXECUTE_5(crypto, a1, a2, a3, a4, a5) { \
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (CRYPTO_CMD_INSTR_EXEC << 8); }
+#define CRYPTO_EXECUTE_6(crypto, a1, a2, a3, a4, a5, a6) { \
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (CRYPTO_CMD_INSTR_EXEC << 16); }
+#define CRYPTO_EXECUTE_7(crypto, a1, a2, a3, a4, a5, a6, a7) { \
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (CRYPTO_CMD_INSTR_EXEC << 24); }
+#define CRYPTO_EXECUTE_8(crypto, a1, a2, a3, a4, a5, a6, a7, a8) { \
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
crypto->SEQ2 = CRYPTO_CMD_INSTR_EXEC; }
-#define CRYPTO_EXECUTE_9(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (CRYPTO_CMD_INSTR_EXEC<<8); }
-#define CRYPTO_EXECUTE_10(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (CRYPTO_CMD_INSTR_EXEC<<16); }
+#define CRYPTO_EXECUTE_9(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9) { \
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (CRYPTO_CMD_INSTR_EXEC << 8); }
+#define CRYPTO_EXECUTE_10(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10) { \
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (CRYPTO_CMD_INSTR_EXEC << 16); }
#define CRYPTO_EXECUTE_11(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (CRYPTO_CMD_INSTR_EXEC << 24); }
#define CRYPTO_EXECUTE_12(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
crypto->SEQ3 = CRYPTO_CMD_INSTR_EXEC; }
#define CRYPTO_EXECUTE_13(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (CRYPTO_CMD_INSTR_EXEC<<8); }
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (CRYPTO_CMD_INSTR_EXEC << 8); }
#define CRYPTO_EXECUTE_14(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (a14<<8) | (CRYPTO_CMD_INSTR_EXEC<<16); }
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (a14 << 8) | (CRYPTO_CMD_INSTR_EXEC << 16); }
#define CRYPTO_EXECUTE_15(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (CRYPTO_CMD_INSTR_EXEC << 24); }
#define CRYPTO_EXECUTE_16(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
crypto->SEQ4 = CRYPTO_CMD_INSTR_EXEC; }
#define CRYPTO_EXECUTE_17(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
- crypto->SEQ4 = a17 | (CRYPTO_CMD_INSTR_EXEC<<8); }
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
+ crypto->SEQ4 = a17 | (CRYPTO_CMD_INSTR_EXEC << 8); }
#define CRYPTO_EXECUTE_18(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
- crypto->SEQ4 = a17 | (a18<<8) | (CRYPTO_CMD_INSTR_EXEC<<16); }
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
+ crypto->SEQ4 = a17 | (a18 << 8) | (CRYPTO_CMD_INSTR_EXEC << 16); }
#define CRYPTO_EXECUTE_19(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
- crypto->SEQ4 = a17 | (a18<<8) | (a19<<16) | (CRYPTO_CMD_INSTR_EXEC<<24); }
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
+ crypto->SEQ4 = a17 | (a18 << 8) | (a19 << 16) | (CRYPTO_CMD_INSTR_EXEC << 24); }
#define CRYPTO_EXECUTE_20(crypto, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20) { \
- crypto->SEQ0 = a1 | (a2<<8) | (a3<<16) | (a4<<24); \
- crypto->SEQ1 = a5 | (a6<<8) | (a7<<16) | (a8<<24); \
- crypto->SEQ2 = a9 | (a10<<8) | (a11<<16) | (a12<<24); \
- crypto->SEQ3 = a13 | (a14<<8) | (a15<<16) | (a16<<24); \
- crypto->SEQ4 = a17 | (a18<<8) | (a19<<16) | (a20<<24); \
- CRYPTO_InstructionSequenceExecute();}
+ crypto->SEQ0 = a1 | (a2 << 8) | (a3 << 16) | (a4 << 24); \
+ crypto->SEQ1 = a5 | (a6 << 8) | (a7 << 16) | (a8 << 24); \
+ crypto->SEQ2 = a9 | (a10 << 8) | (a11 << 16) | (a12 << 24); \
+ crypto->SEQ3 = a13 | (a14 << 8) | (a15 << 16) | (a16 << 24); \
+ crypto->SEQ4 = a17 | (a18 << 8) | (a19 << 16) | (a20 << 24); \
+ CRYPTO_InstructionSequenceExecute(); }
/** @endcond */
/*******************************************************************************
@@ -478,8 +487,7 @@
typedef volatile uint32_t* CRYPTO_QDataReg_TypeDef;
/** CRYPTO modulus identifiers. */
-typedef enum
-{
+typedef enum {
cryptoModulusBin256 = CRYPTO_WAC_MODULUS_BIN256, /**< Generic 256 bit modulus 2^256 */
cryptoModulusBin128 = CRYPTO_WAC_MODULUS_BIN128, /**< Generic 128 bit modulus 2^128 */
cryptoModulusGcmBin128 = CRYPTO_WAC_MODULUS_GCMBIN128, /**< GCM 128 bit modulus = 2^128 + 2^7 + 2^2 + 2 + 1 */
@@ -498,8 +506,7 @@
} CRYPTO_ModulusId_TypeDef;
/** CRYPTO multiplication widths for wide arithmetic operations. */
-typedef enum
-{
+typedef enum {
cryptoMulOperand256Bits = CRYPTO_WAC_MULWIDTH_MUL256, /**< 256 bits operands */
cryptoMulOperand128Bits = CRYPTO_WAC_MULWIDTH_MUL128, /**< 128 bits operands */
cryptoMulOperandModulusBits = CRYPTO_WAC_MULWIDTH_MULMOD /**< MUL operand width
@@ -508,16 +515,14 @@
} CRYPTO_MulOperandWidth_TypeDef;
/** CRYPTO result widths for MUL operations. */
-typedef enum
-{
+typedef enum {
cryptoResult128Bits = CRYPTO_WAC_RESULTWIDTH_128BIT, /**< Multiplication result width is 128 bits*/
cryptoResult256Bits = CRYPTO_WAC_RESULTWIDTH_256BIT, /**< Multiplication result width is 256 bits*/
cryptoResult260Bits = CRYPTO_WAC_RESULTWIDTH_260BIT /**< Multiplication result width is 260 bits*/
} CRYPTO_ResultWidth_TypeDef;
/** CRYPTO result widths for MUL operations. */
-typedef enum
-{
+typedef enum {
cryptoInc1byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH1, /**< inc width is 1 byte*/
cryptoInc2byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH2, /**< inc width is 2 byte*/
cryptoInc3byte = CRYPTO_CTRL_INCWIDTH_INCWIDTH3, /**< inc width is 3 byte*/
@@ -525,8 +530,7 @@
} CRYPTO_IncWidth_TypeDef;
/** CRYPTO key width. */
-typedef enum
-{
+typedef enum {
cryptoKey128Bits = 8, /**< Key width is 128 bits*/
cryptoKey256Bits = 16, /**< Key width is 256 bits*/
} CRYPTO_KeyWidth_TypeDef;
@@ -549,14 +553,14 @@
initialize the instruction sequence with this default value set, and fill
in the desired operations from step 1. The first END instruction marks
the end of the sequence. */
-#define CRYPTO_INSTRUCTIONSEQUENSE_DEFAULT \
- {CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
- CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
- CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
- CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
- CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
- CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
- CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END}
+#define CRYPTO_INSTRUCTIONSEQUENSE_DEFAULT \
+ { CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
+ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
+ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
+ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
+ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
+ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END, \
+ CRYPTO_CMD_INSTR_END, CRYPTO_CMD_INSTR_END }
/** SHA-1 Digest type. */
typedef uint8_t CRYPTO_SHA1_Digest_TypeDef[CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES];
@@ -861,15 +865,12 @@
CRYPTO_KeyBuf_TypeDef val,
CRYPTO_KeyWidth_TypeDef keyWidth)
{
- if (keyWidth == cryptoKey256Bits)
- {
+ if (keyWidth == cryptoKey256Bits) {
/* Set AES-256 mode */
BUS_RegBitWrite(&crypto->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES256);
/* Load key in KEYBUF register (= DDATA4) */
CRYPTO_DDataWrite(&crypto->DDATA4, (uint32_t *)val);
- }
- else
- {
+ } else {
/* Set AES-128 mode */
BUS_RegBitWrite(&crypto->CTRL, _CRYPTO_CTRL_AES_SHIFT, _CRYPTO_CTRL_AES_AES128);
CRYPTO_BurstToCrypto(&crypto->KEYBUF, &val[0]);
@@ -915,7 +916,7 @@
__STATIC_INLINE bool CRYPTO_CarryIsSet(CRYPTO_TypeDef *crypto)
{
return (crypto->DSTATUS & _CRYPTO_DSTATUS_CARRY_MASK)
- >> _CRYPTO_DSTATUS_CARRY_SHIFT;
+ >> _CRYPTO_DSTATUS_CARRY_SHIFT;
}
/***************************************************************************//**
@@ -935,7 +936,7 @@
__STATIC_INLINE uint8_t CRYPTO_DData0_4LSBitsRead(CRYPTO_TypeDef *crypto)
{
return (crypto->DSTATUS & _CRYPTO_DSTATUS_DDATA0LSBS_MASK)
- >> _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT;
+ >> _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT;
}
/***************************************************************************//**
@@ -959,7 +960,7 @@
{
CRYPTO_DDataRead(&crypto->DDATA0, val);
val[8] = (crypto->DSTATUS & _CRYPTO_DSTATUS_DDATA0MSBS_MASK)
- >> _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT;
+ >> _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT;
}
/***************************************************************************//**
@@ -1004,7 +1005,7 @@
__STATIC_INLINE bool CRYPTO_DData1_MSBitRead(CRYPTO_TypeDef *crypto)
{
return (crypto->DSTATUS & _CRYPTO_DSTATUS_DDATA1MSB_MASK)
- >> _CRYPTO_DSTATUS_DDATA1MSB_SHIFT;
+ >> _CRYPTO_DSTATUS_DDATA1MSB_SHIFT;
}
/***************************************************************************//**
@@ -1336,13 +1337,13 @@
* @ref CRYPTO_AES_CBC128 instead.
******************************************************************************/
__STATIC_INLINE void AES_CBC128(uint8_t * out,
- const uint8_t * in,
- unsigned int len,
- const uint8_t * key,
- const uint8_t * iv,
- bool encrypt)
+ const uint8_t * in,
+ unsigned int len,
+ const uint8_t * key,
+ const uint8_t * iv,
+ bool encrypt)
{
- CRYPTO_AES_CBC128(CRYPTO, out, in, len, key, iv, encrypt);
+ CRYPTO_AES_CBC128(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt);
}
/***************************************************************************//**
@@ -1355,13 +1356,13 @@
* @ref CRYPTO_AES_CBC256 instead.
******************************************************************************/
__STATIC_INLINE void AES_CBC256(uint8_t * out,
- const uint8_t * in,
- unsigned int len,
- const uint8_t * key,
- const uint8_t * iv,
- bool encrypt)
+ const uint8_t * in,
+ unsigned int len,
+ const uint8_t * key,
+ const uint8_t * iv,
+ bool encrypt)
{
- CRYPTO_AES_CBC256(CRYPTO, out, in, len, key, iv, encrypt);
+ CRYPTO_AES_CBC256(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt);
}
/***************************************************************************//**
@@ -1373,13 +1374,13 @@
* @ref CRYPTO_AES_CFB128 instead.
******************************************************************************/
__STATIC_INLINE void AES_CFB128(uint8_t * out,
- const uint8_t * in,
- unsigned int len,
- const uint8_t * key,
- const uint8_t * iv,
- bool encrypt)
+ const uint8_t * in,
+ unsigned int len,
+ const uint8_t * key,
+ const uint8_t * iv,
+ bool encrypt)
{
- CRYPTO_AES_CFB128(CRYPTO, out, in, len, key, iv, encrypt);
+ CRYPTO_AES_CFB128(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt);
}
/***************************************************************************//**
@@ -1391,13 +1392,13 @@
* @ref CRYPTO_AES_CFB256 instead.
******************************************************************************/
__STATIC_INLINE void AES_CFB256(uint8_t * out,
- const uint8_t * in,
- unsigned int len,
- const uint8_t * key,
- const uint8_t * iv,
- bool encrypt)
+ const uint8_t * in,
+ unsigned int len,
+ const uint8_t * key,
+ const uint8_t * iv,
+ bool encrypt)
{
- CRYPTO_AES_CFB256(CRYPTO, out, in, len, key, iv, encrypt);
+ CRYPTO_AES_CFB256(DEFAULT_CRYPTO, out, in, len, key, iv, encrypt);
}
/***************************************************************************//**
@@ -1409,13 +1410,13 @@
* @ref CRYPTO_AES_CTR128 instead.
******************************************************************************/
__STATIC_INLINE void AES_CTR128(uint8_t * out,
- const uint8_t * in,
- unsigned int len,
- const uint8_t * key,
- uint8_t * ctr,
- CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)
+ const uint8_t * in,
+ unsigned int len,
+ const uint8_t * key,
+ uint8_t * ctr,
+ CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)
{
- CRYPTO_AES_CTR128(CRYPTO, out, in, len, key, ctr, ctrFunc);
+ CRYPTO_AES_CTR128(DEFAULT_CRYPTO, out, in, len, key, ctr, ctrFunc);
}
/***************************************************************************//**
@@ -1427,13 +1428,13 @@
* @ref CRYPTO_AES_CTR256 instead.
******************************************************************************/
__STATIC_INLINE void AES_CTR256(uint8_t * out,
- const uint8_t * in,
- unsigned int len,
- const uint8_t * key,
- uint8_t * ctr,
- CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)
+ const uint8_t * in,
+ unsigned int len,
+ const uint8_t * key,
+ uint8_t * ctr,
+ CRYPTO_AES_CtrFuncPtr_TypeDef ctrFunc)
{
- CRYPTO_AES_CTR256(CRYPTO, out, in, len, key, ctr, ctrFunc);
+ CRYPTO_AES_CTR256(DEFAULT_CRYPTO, out, in, len, key, ctr, ctrFunc);
}
/***************************************************************************//**
@@ -1460,7 +1461,7 @@
******************************************************************************/
__STATIC_INLINE void AES_DecryptKey128(uint8_t * out, const uint8_t * in)
{
- CRYPTO_AES_DecryptKey128(CRYPTO, out, in);
+ CRYPTO_AES_DecryptKey128(DEFAULT_CRYPTO, out, in);
}
/***************************************************************************//**
@@ -1474,7 +1475,7 @@
******************************************************************************/
__STATIC_INLINE void AES_DecryptKey256(uint8_t * out, const uint8_t * in)
{
- CRYPTO_AES_DecryptKey256(CRYPTO, out, in);
+ CRYPTO_AES_DecryptKey256(DEFAULT_CRYPTO, out, in);
}
/***************************************************************************//**
@@ -1492,7 +1493,7 @@
const uint8_t * key,
bool encrypt)
{
- CRYPTO_AES_ECB128(CRYPTO, out, in, len, key, encrypt);
+ CRYPTO_AES_ECB128(DEFAULT_CRYPTO, out, in, len, key, encrypt);
}
/***************************************************************************//**
@@ -1510,7 +1511,7 @@
const uint8_t * key,
bool encrypt)
{
- CRYPTO_AES_ECB256(CRYPTO, out, in, len, key, encrypt);
+ CRYPTO_AES_ECB256(DEFAULT_CRYPTO, out, in, len, key, encrypt);
}
/***************************************************************************//**
@@ -1527,7 +1528,7 @@
const uint8_t * key,
const uint8_t * iv)
{
- CRYPTO_AES_OFB128(CRYPTO, out, in, len, key, iv);
+ CRYPTO_AES_OFB128(DEFAULT_CRYPTO, out, in, len, key, iv);
}
/***************************************************************************//**
@@ -1544,7 +1545,7 @@
const uint8_t * key,
const uint8_t * iv)
{
- CRYPTO_AES_OFB256(CRYPTO, out, in, len, key, iv);
+ CRYPTO_AES_OFB256(DEFAULT_CRYPTO, out, in, len, key, iv);
}
#ifdef __cplusplus
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_csen.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_csen.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_csen.h
* @brief Capacitive Sense Module (CSEN) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -34,7 +34,7 @@
#define EM_CSEN_H
#include "em_device.h"
-#if defined( CSEN_COUNT ) && ( CSEN_COUNT > 0 )
+#if defined(CSEN_COUNT) && (CSEN_COUNT > 0)
#include <stdbool.h>
#include "em_bus.h"
@@ -53,24 +53,24 @@
* @brief Capacitive Sense (CSEN) Peripheral API
*
* @details
- * This module provides functions for controlling the capacitive sense
- * peripheral of Silicon Labs 32-bit MCUs and SoCs. The CSEN includes a
- * capacitance-to-digital circuit that measures capacitance on selected
- * inputs. Measurements are performed using either a successive approximation
+ * This module provides functions for controlling the capacitive sense
+ * peripheral of Silicon Labs 32-bit MCUs and SoCs. The CSEN includes a
+ * capacitance-to-digital circuit that measures capacitance on selected
+ * inputs. Measurements are performed using either a successive approximation
* register (SAR) or a delta modulator (DM) analog to digital converter.
*
- * The CSEN can be configured to measure capacitance on a single port pin
- * or to automatically measure multiple port pins in succession using scan
- * mode. Also several port pins can be shorted together to measure the
+ * The CSEN can be configured to measure capacitance on a single port pin
+ * or to automatically measure multiple port pins in succession using scan
+ * mode. Also several port pins can be shorted together to measure the
* combined capacitance.
*
- * The CSEN includes an accumulator which can be configured to average
- * multiple conversions on the selected input. Additionally, an exponential
- * moving average (EMA) calculator is included to provide data smoothing.
- * A comparator is also included and can be used to terminate a continuous
+ * The CSEN includes an accumulator which can be configured to average
+ * multiple conversions on the selected input. Additionally, an exponential
+ * moving average (EMA) calculator is included to provide data smoothing.
+ * A comparator is also included and can be used to terminate a continuous
* conversion when the configured threshold condition is met.
*
- * The following example shows how to intialize and start a single
+ * The following example shows how to intialize and start a single
* conversion on one input:
*
* @include em_csen_single.c
@@ -83,8 +83,7 @@
******************************************************************************/
/** Comparator Mode. Selects the operation of the digital comparator. */
-typedef enum
-{
+typedef enum {
/** Comparator is disabled. */
csenCmpModeDisabled = 0,
@@ -98,10 +97,8 @@
csenCmpModeEMAWindow = CSEN_CTRL_EMACMPEN,
} CSEN_CmpMode_TypeDef;
-
/** Converter Select. Determines the converter operational mode. */
-typedef enum
-{
+typedef enum {
/** Successive Approximation (SAR) converter. */
csenConvSelSAR = CSEN_CTRL_CONVSEL_SAR,
@@ -115,10 +112,8 @@
csenConvSelDMChop = CSEN_CTRL_CONVSEL_DM | CSEN_CTRL_CHOPEN_ENABLE,
} CSEN_ConvSel_TypeDef;
-
/** Sample Mode. Determines how inputs are sampled for a conversion. */
-typedef enum
-{
+typedef enum {
/** Convert multiple inputs shorted together and stop. */
csenSampleModeBonded = CSEN_CTRL_CM_SGL | CSEN_CTRL_MCEN_ENABLE,
@@ -138,19 +133,15 @@
csenSampleModeContScan = CSEN_CTRL_CM_CONTSCAN,
} CSEN_SampleMode_TypeDef;
-
/** Start Trigger Select. */
-typedef enum
-{
+typedef enum {
csenTrigSelPRS = _CSEN_CTRL_STM_PRS, /**< PRS system. */
csenTrigSelTimer = _CSEN_CTRL_STM_TIMER, /**< CSEN PC timer. */
csenTrigSelStart = _CSEN_CTRL_STM_START, /**< Start bit. */
} CSEN_TrigSel_TypeDef;
-
/** Accumulator Mode Select. */
-typedef enum
-{
+typedef enum {
csenAccMode1 = _CSEN_CTRL_ACU_ACC1, /**< Accumulate 1 sample. */
csenAccMode2 = _CSEN_CTRL_ACU_ACC2, /**< Accumulate 2 samples. */
csenAccMode4 = _CSEN_CTRL_ACU_ACC4, /**< Accumulate 4 samples. */
@@ -160,31 +151,25 @@
csenAccMode64 = _CSEN_CTRL_ACU_ACC64, /**< Accumulate 64 samples. */
} CSEN_AccMode_TypeDef;
-
/** Successive Approximation (SAR) Conversion Resolution. */
-typedef enum
-{
+typedef enum {
csenSARRes10 = _CSEN_CTRL_SARCR_CLK10, /**< 10-bit resolution. */
csenSARRes12 = _CSEN_CTRL_SARCR_CLK12, /**< 12-bit resolution. */
csenSARRes14 = _CSEN_CTRL_SARCR_CLK14, /**< 14-bit resolution. */
csenSARRes16 = _CSEN_CTRL_SARCR_CLK16, /**< 16-bit resolution. */
} CSEN_SARRes_TypeDef;
-
/** Delta Modulator (DM) Conversion Resolution. */
-typedef enum
-{
+typedef enum {
csenDMRes10 = _CSEN_DMCFG_CRMODE_DM10, /**< 10-bit resolution. */
csenDMRes12 = _CSEN_DMCFG_CRMODE_DM12, /**< 12-bit resolution. */
csenDMRes14 = _CSEN_DMCFG_CRMODE_DM14, /**< 14-bit resolution. */
csenDMRes16 = _CSEN_DMCFG_CRMODE_DM16, /**< 16-bit resolution. */
} CSEN_DMRes_TypeDef;
-
-/** Period counter clock pre-scaler. See the reference manual for source clock
+/** Period counter clock pre-scaler. See the reference manual for source clock
* information. */
-typedef enum
-{
+typedef enum {
csenPCPrescaleDiv1 = _CSEN_TIMCTRL_PCPRESC_DIV1, /**< Divide by 1. */
csenPCPrescaleDiv2 = _CSEN_TIMCTRL_PCPRESC_DIV2, /**< Divide by 2. */
csenPCPrescaleDiv4 = _CSEN_TIMCTRL_PCPRESC_DIV4, /**< Divide by 4. */
@@ -195,10 +180,8 @@
csenPCPrescaleDiv128 = _CSEN_TIMCTRL_PCPRESC_DIV128, /**< Divide by 128. */
} CSEN_PCPrescale_TypeDef;
-
/** Exponential Moving Average sample weight. */
-typedef enum
-{
+typedef enum {
csenEMASampleW1 = _CSEN_EMACTRL_EMASAMPLE_W1, /**< Weight 1. */
csenEMASampleW2 = _CSEN_EMACTRL_EMASAMPLE_W2, /**< Weight 2. */
csenEMASampleW4 = _CSEN_EMACTRL_EMASAMPLE_W4, /**< Weight 4. */
@@ -208,10 +191,8 @@
csenEMASampleW64 = _CSEN_EMACTRL_EMASAMPLE_W64, /**< Weight 64. */
} CSEN_EMASample_TypeDef;
-
/** Reset Phase Timing Select (units are microseconds). */
-typedef enum
-{
+typedef enum {
csenResetPhaseSel0 = 0, /**< Reset phase time = 0.75 usec. */
csenResetPhaseSel1 = 1, /**< Reset phase time = 1.00 usec. */
csenResetPhaseSel2 = 2, /**< Reset phase time = 1.20 usec. */
@@ -222,10 +203,8 @@
csenResetPhaseSel7 = 7, /**< Reset phase time = 12.0 usec. */
} CSEN_ResetPhaseSel_TypeDef;
-
/** Drive Strength Select. Scales the output current. */
-typedef enum
-{
+typedef enum {
csenDriveSelFull = 0, /**< Drive strength = fully on. */
csenDriveSel1 = 1, /**< Drive strength = 1/8 full scale. */
csenDriveSel2 = 2, /**< Drive strength = 1/4 full scale. */
@@ -236,10 +215,8 @@
csenDriveSel7 = 7, /**< Drive strength = 7/8 full scale. */
} CSEN_DriveSel_TypeDef;
-
/** Gain Select. See reference manual for information on each setting. */
-typedef enum
-{
+typedef enum {
csenGainSel1X = 0, /**< Gain = 1x. */
csenGainSel2X = 1, /**< Gain = 2x. */
csenGainSel3X = 2, /**< Gain = 3x. */
@@ -250,10 +227,8 @@
csenGainSel8X = 7, /**< Gain = 8x. */
} CSEN_GainSel_TypeDef;
-
/** Peripheral Reflex System signal used to trigger conversion. */
-typedef enum
-{
+typedef enum {
csenPRSSELCh0 = _CSEN_PRSSEL_PRSSEL_PRSCH0, /**< PRS channel 0. */
csenPRSSELCh1 = _CSEN_PRSSEL_PRSSEL_PRSCH1, /**< PRS channel 1. */
csenPRSSELCh2 = _CSEN_PRSSEL_PRSSEL_PRSCH2, /**< PRS channel 2. */
@@ -262,16 +237,22 @@
csenPRSSELCh5 = _CSEN_PRSSEL_PRSSEL_PRSCH5, /**< PRS channel 5. */
csenPRSSELCh6 = _CSEN_PRSSEL_PRSSEL_PRSCH6, /**< PRS channel 6. */
csenPRSSELCh7 = _CSEN_PRSSEL_PRSSEL_PRSCH7, /**< PRS channel 7. */
+#if defined(_CSEN_PRSSEL_PRSSEL_PRSCH8)
csenPRSSELCh8 = _CSEN_PRSSEL_PRSSEL_PRSCH8, /**< PRS channel 8. */
+#endif
+#if defined(_CSEN_PRSSEL_PRSSEL_PRSCH9)
csenPRSSELCh9 = _CSEN_PRSSEL_PRSSEL_PRSCH9, /**< PRS channel 9. */
+#endif
+#if defined(_CSEN_PRSSEL_PRSSEL_PRSCH10)
csenPRSSELCh10 = _CSEN_PRSSEL_PRSSEL_PRSCH10, /**< PRS channel 10. */
+#endif
+#if defined(_CSEN_PRSSEL_PRSSEL_PRSCH11)
csenPRSSELCh11 = _CSEN_PRSSEL_PRSSEL_PRSCH11, /**< PRS channel 11. */
+#endif
} CSEN_PRSSel_TypeDef;
-
/** APORT channel to CSEN input selection. */
-typedef enum
-{
+typedef enum {
csenInputSelDefault = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT,
csenInputSelAPORT1CH0TO7 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7,
csenInputSelAPORT1CH8TO15 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15,
@@ -283,10 +264,8 @@
csenInputSelAPORT3CH24TO31 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31,
} CSEN_InputSel_TypeDef;
-
/** APORT channel to CSEN single input selection. */
-typedef enum
-{
+typedef enum {
csenSingleSelDefault = _CSEN_SINGLECTRL_SINGLESEL_DEFAULT,
csenSingleSelAPORT1XCH0 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0,
csenSingleSelAPORT1YCH1 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1,
@@ -354,14 +333,12 @@
csenSingleSelAPORT3YCH31 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31,
} CSEN_SingleSel_TypeDef;
-
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** CSEN init structure, common for all measurement modes. */
-typedef struct
-{
+typedef struct {
/** Requests system charge pump high accuracy mode. */
bool cpAccuracyHi;
@@ -394,29 +371,27 @@
CSEN_InputSel_TypeDef input56To63;
} CSEN_Init_TypeDef;
-#define CSEN_INIT_DEFAULT \
-{ \
- false, /* Charge pump low accuracy mode. */ \
- false, /* Use external kelvin connection. */ \
- false, /* Disable keep warm. */ \
- 0, /* 0+3 cycle warmup time. */ \
- 0, /* Period counter reload. */ \
- csenPCPrescaleDiv1, /* Period counter prescale. */ \
- csenPRSSELCh0, /* PRS channel 0. */ \
- csenInputSelAPORT1CH0TO7, /* input0To7 -> aport1ch0to7 */ \
- csenInputSelAPORT1CH8TO15, /* input8To15 -> aport1ch8to15 */ \
- csenInputSelAPORT1CH16TO23, /* input16To23 -> aport1ch16to23 */ \
- csenInputSelAPORT1CH24TO31, /* input24To31 -> aport1ch24to31 */ \
- csenInputSelAPORT3CH0TO7, /* input32To39 -> aport3ch0to7 */ \
- csenInputSelAPORT3CH8TO15, /* input40To47 -> aport3ch8to15 */ \
- csenInputSelAPORT3CH16TO23, /* input48To55 -> aport3ch16to23 */ \
- csenInputSelAPORT3CH24TO31, /* input56To63 -> aport3ch24to31 */ \
-}
-
+#define CSEN_INIT_DEFAULT \
+ { \
+ false, /* Charge pump low accuracy mode. */ \
+ false, /* Use external kelvin connection. */ \
+ false, /* Disable keep warm. */ \
+ 0, /* 0+3 cycle warmup time. */ \
+ 0, /* Period counter reload. */ \
+ csenPCPrescaleDiv1, /* Period counter prescale. */ \
+ csenPRSSELCh0, /* PRS channel 0. */ \
+ csenInputSelAPORT1CH0TO7, /* input0To7 -> aport1ch0to7 */ \
+ csenInputSelAPORT1CH8TO15, /* input8To15 -> aport1ch8to15 */ \
+ csenInputSelAPORT1CH16TO23, /* input16To23 -> aport1ch16to23 */ \
+ csenInputSelAPORT1CH24TO31, /* input24To31 -> aport1ch24to31 */ \
+ csenInputSelAPORT3CH0TO7, /* input32To39 -> aport3ch0to7 */ \
+ csenInputSelAPORT3CH8TO15, /* input40To47 -> aport3ch8to15 */ \
+ csenInputSelAPORT3CH16TO23, /* input48To55 -> aport3ch16to23 */ \
+ csenInputSelAPORT3CH24TO31, /* input56To63 -> aport3ch24to31 */ \
+ }
/** Measurement mode init structure. */
-typedef struct
-{
+typedef struct {
/** Selects the conversion sample mode. */
CSEN_SampleMode_TypeDef sampleMode;
@@ -444,11 +419,11 @@
/** Selects an APORT channel for a single conversion. */
CSEN_SingleSel_TypeDef singleSel;
- /**
- * Mask selects inputs 0 to 31. Effect depends on @p sampleMode. If sample
- * mode is bonded, then mask selects inputs to short together. If sample
- * mode is scan, then mask selects which inputs will be scanned. If sample
- * mode is single and auto-ground is on (@p autoGnd is true), mask selects
+ /**
+ * Mask selects inputs 0 to 31. Effect depends on @p sampleMode. If sample
+ * mode is bonded, then mask selects inputs to short together. If sample
+ * mode is scan, then mask selects which inputs will be scanned. If sample
+ * mode is single and auto-ground is on (@p autoGnd is true), mask selects
* which pins are grounded.
*/
uint32_t inputMask0;
@@ -467,61 +442,60 @@
/** Selects the Delta Modulation (DM) converter resolution. */
CSEN_DMRes_TypeDef dmRes;
-
- /** Sets the number of DM iterations (comparisons) per cycle. Only applies
- * to the Delta Modulation converter. */
+
+ /** Sets the number of DM iterations (comparisons) per cycle. Only applies
+ * to the Delta Modulation converter. */
uint8_t dmIterPerCycle;
-
- /** Sets number of DM converter cycles. Only applies to the
- * Delta Modulation converter. */
+
+ /** Sets number of DM converter cycles. Only applies to the
+ * Delta Modulation converter. */
uint8_t dmCycles;
- /** Sets the DM converter initial delta value. Only applies to the
- * Delta Modulation converter. */
+ /** Sets the DM converter initial delta value. Only applies to the
+ * Delta Modulation converter. */
uint8_t dmDelta;
- /** Disable DM automatic delta size reduction per cycle. Only applies to the
- * Delta Modulation converter. */
+ /** Disable DM automatic delta size reduction per cycle. Only applies to the
+ * Delta Modulation converter. */
bool dmFixedDelta;
- /** Selects the reset phase timing. Most measurements should use the default
- * value. See reference manual for details on when to adjust. */
+ /** Selects the reset phase timing. Most measurements should use the default
+ * value. See reference manual for details on when to adjust. */
CSEN_ResetPhaseSel_TypeDef resetPhase;
- /** Selects the output drive strength. Most measurements should use the
- * default value. See reference manual for details on when to adjust. */
+ /** Selects the output drive strength. Most measurements should use the
+ * default value. See reference manual for details on when to adjust. */
CSEN_DriveSel_TypeDef driveSel;
/** Selects the converter gain. */
CSEN_GainSel_TypeDef gainSel;
} CSEN_InitMode_TypeDef;
-#define CSEN_INITMODE_DEFAULT \
-{ \
- csenSampleModeSingle, /* Sample one input and stop. */ \
- csenTrigSelStart, /* Use start bit to trigger. */ \
- false, /* Disable DMA. */ \
- false, /* Average the accumulated result. */ \
- csenAccMode1, /* Accumulate 1 sample. */ \
- csenEMASampleW1, /* Disable the EMA. */ \
- csenCmpModeDisabled, /* Disable the comparator. */ \
- 0, /* Comparator threshold not used. */ \
- csenSingleSelDefault, /* Disconnect the single input. */ \
- 0, /* Disable inputs 0 to 31. */ \
- 0, /* Disable inputs 32 to 63. */ \
- false, /* Do not ground inactive inputs. */ \
- csenConvSelSAR, /* Use the SAR converter. */ \
- csenSARRes10, /* Set SAR resolution to 10 bits. */ \
- csenDMRes10, /* Set DM resolution to 10 bits. */ \
- 0, /* Set DM conv/cycle to default. */ \
- 0, /* Set DM cycles to default. */ \
- 0, /* Set DM initial delta to default. */ \
- false, /* Use DM auto delta reduction. */ \
- csenResetPhaseSel0, /* Use shortest reset phase time. */ \
- csenDriveSelFull, /* Use full output current. */ \
- csenGainSel8X, /* Use highest converter gain. */ \
-}
-
+#define CSEN_INITMODE_DEFAULT \
+ { \
+ csenSampleModeSingle, /* Sample one input and stop. */ \
+ csenTrigSelStart, /* Use start bit to trigger. */ \
+ false, /* Disable DMA. */ \
+ false, /* Average the accumulated result. */ \
+ csenAccMode1, /* Accumulate 1 sample. */ \
+ csenEMASampleW1, /* Disable the EMA. */ \
+ csenCmpModeDisabled, /* Disable the comparator. */ \
+ 0, /* Comparator threshold not used. */ \
+ csenSingleSelDefault, /* Disconnect the single input. */ \
+ 0, /* Disable inputs 0 to 31. */ \
+ 0, /* Disable inputs 32 to 63. */ \
+ false, /* Do not ground inactive inputs. */ \
+ csenConvSelSAR, /* Use the SAR converter. */ \
+ csenSARRes10, /* Set SAR resolution to 10 bits. */ \
+ csenDMRes10, /* Set DM resolution to 10 bits. */ \
+ 0, /* Set DM conv/cycle to default. */ \
+ 0, /* Set DM cycles to default. */ \
+ 0, /* Set DM initial delta to default. */ \
+ false, /* Use DM auto delta reduction. */ \
+ csenResetPhaseSel0, /* Use shortest reset phase time. */ \
+ csenDriveSelFull, /* Use full output current. */ \
+ csenGainSel8X, /* Use highest converter gain. */ \
+ }
/*******************************************************************************
***************************** PROTOTYPES **********************************
@@ -532,8 +506,8 @@
* Get last conversion result.
*
* @note
- * Check conversion busy flag before calling this function. In addition,
- * the result width and format depend on the parameters passed to the
+ * Check conversion busy flag before calling this function. In addition,
+ * the result width and format depend on the parameters passed to the
* @ref CSEN_InitMode() function.
*
* @param[in] csen
@@ -612,7 +586,6 @@
void CSEN_InitMode(CSEN_TypeDef *csen, const CSEN_InitMode_TypeDef *init);
void CSEN_Reset(CSEN_TypeDef *csen);
-
/***************************************************************************//**
* @brief
* Clear one or more pending CSEN interrupts.
@@ -629,7 +602,6 @@
csen->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more CSEN interrupts.
@@ -646,7 +618,6 @@
csen->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more CSEN interrupts.
@@ -668,7 +639,6 @@
csen->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending CSEN interrupt flags.
@@ -688,7 +658,6 @@
return csen->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending CSEN interrupt flags.
@@ -720,7 +689,6 @@
return csen->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending CSEN interrupts from SW.
@@ -737,7 +705,6 @@
csen->IFS = flags;
}
-
/***************************************************************************//**
* @brief
* Return CSEN conversion busy status.
@@ -753,7 +720,6 @@
return (bool)(csen->STATUS & _CSEN_STATUS_CSENBUSY_MASK);
}
-
/***************************************************************************//**
* @brief
* Start scan sequence and/or single conversion.
@@ -766,7 +732,6 @@
csen->CMD = CSEN_CMD_START;
}
-
/** @} (end addtogroup CSEN) */
/** @} (end addtogroup emlib) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_dac.h
* @brief Digital to Analog Converter (DAC) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -44,7 +44,6 @@
extern "C" {
#endif
-
/***************************************************************************//**
* @addtogroup emlib
* @{
@@ -67,83 +66,73 @@
******************************************************************************/
/** Conversion mode. */
-typedef enum
-{
+typedef enum {
dacConvModeContinuous = _DAC_CTRL_CONVMODE_CONTINUOUS, /**< Continuous mode. */
dacConvModeSampleHold = _DAC_CTRL_CONVMODE_SAMPLEHOLD, /**< Sample/hold mode. */
dacConvModeSampleOff = _DAC_CTRL_CONVMODE_SAMPLEOFF /**< Sample/shut off mode. */
} DAC_ConvMode_TypeDef;
/** Output mode. */
-typedef enum
-{
+typedef enum {
dacOutputDisable = _DAC_CTRL_OUTMODE_DISABLE, /**< Output to pin and ADC disabled. */
dacOutputPin = _DAC_CTRL_OUTMODE_PIN, /**< Output to pin only. */
dacOutputADC = _DAC_CTRL_OUTMODE_ADC, /**< Output to ADC only */
dacOutputPinADC = _DAC_CTRL_OUTMODE_PINADC /**< Output to pin and ADC. */
} DAC_Output_TypeDef;
-
/** Peripheral Reflex System signal used to trigger single sample. */
-typedef enum
-{
+typedef enum {
dacPRSSELCh0 = _DAC_CH0CTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
dacPRSSELCh1 = _DAC_CH0CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
dacPRSSELCh2 = _DAC_CH0CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
dacPRSSELCh3 = _DAC_CH0CTRL_PRSSEL_PRSCH3, /**< PRS channel 3. */
-#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH4 )
+#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH4)
dacPRSSELCh4 = _DAC_CH0CTRL_PRSSEL_PRSCH4, /**< PRS channel 4. */
#endif
-#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH5 )
+#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH5)
dacPRSSELCh5 = _DAC_CH0CTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */
#endif
-#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH6 )
+#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH6)
dacPRSSELCh6 = _DAC_CH0CTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */
#endif
-#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH7 )
+#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH7)
dacPRSSELCh7 = _DAC_CH0CTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */
#endif
-#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH8 )
+#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH8)
dacPRSSELCh8 = _DAC_CH0CTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */
#endif
-#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH9 )
+#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH9)
dacPRSSELCh9 = _DAC_CH0CTRL_PRSSEL_PRSCH9, /**< PRS channel 9. */
#endif
-#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH10 )
+#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH10)
dacPRSSELCh10 = _DAC_CH0CTRL_PRSSEL_PRSCH10, /**< PRS channel 10. */
#endif
-#if defined( _DAC_CH0CTRL_PRSSEL_PRSCH11 )
+#if defined(_DAC_CH0CTRL_PRSSEL_PRSCH11)
dacPRSSELCh11 = _DAC_CH0CTRL_PRSSEL_PRSCH11, /**< PRS channel 11. */
#endif
} DAC_PRSSEL_TypeDef;
-
/** Reference voltage for DAC. */
-typedef enum
-{
+typedef enum {
dacRef1V25 = _DAC_CTRL_REFSEL_1V25, /**< Internal 1.25V bandgap reference. */
dacRef2V5 = _DAC_CTRL_REFSEL_2V5, /**< Internal 2.5V bandgap reference. */
dacRefVDD = _DAC_CTRL_REFSEL_VDD /**< VDD reference. */
} DAC_Ref_TypeDef;
-
/** Refresh interval. */
-typedef enum
-{
+typedef enum {
dacRefresh8 = _DAC_CTRL_REFRSEL_8CYCLES, /**< Refresh every 8 prescaled cycles. */
dacRefresh16 = _DAC_CTRL_REFRSEL_16CYCLES, /**< Refresh every 16 prescaled cycles. */
dacRefresh32 = _DAC_CTRL_REFRSEL_32CYCLES, /**< Refresh every 32 prescaled cycles. */
dacRefresh64 = _DAC_CTRL_REFRSEL_64CYCLES /**< Refresh every 64 prescaled cycles. */
} DAC_Refresh_TypeDef;
-
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** DAC init structure, common for both channels. */
-typedef struct
-{
+typedef struct {
/** Refresh interval. Only used if REFREN bit set for a DAC channel. */
DAC_Refresh_TypeDef refresh;
@@ -180,23 +169,21 @@
/** Default config for DAC init structure. */
#define DAC_INIT_DEFAULT \
-{ \
- dacRefresh8, /* Refresh every 8 prescaled cycles. */ \
- dacRef1V25, /* 1.25V internal reference. */ \
- dacOutputPin, /* Output to pin only. */ \
- dacConvModeContinuous, /* Continuous mode. */ \
- 0, /* No prescaling. */ \
- false, /* Do not enable low pass filter. */ \
- false, /* Do not reset prescaler on ch0 start. */ \
- false, /* DAC output enable always on. */ \
- false, /* Disable sine mode. */ \
- false /* Single ended mode. */ \
-}
-
+ { \
+ dacRefresh8, /* Refresh every 8 prescaled cycles. */ \
+ dacRef1V25, /* 1.25V internal reference. */ \
+ dacOutputPin, /* Output to pin only. */ \
+ dacConvModeContinuous, /* Continuous mode. */ \
+ 0, /* No prescaling. */ \
+ false, /* Do not enable low pass filter. */ \
+ false, /* Do not reset prescaler on ch0 start. */ \
+ false, /* DAC output enable always on. */ \
+ false, /* Disable sine mode. */ \
+ false /* Single ended mode. */ \
+ }
/** DAC channel init structure. */
-typedef struct
-{
+typedef struct {
/** Enable channel. */
bool enable;
@@ -221,13 +208,12 @@
/** Default config for DAC channel init structure. */
#define DAC_INITCHANNEL_DEFAULT \
-{ \
- false, /* Leave channel disabled when init done. */ \
- false, /* Disable PRS triggering. */ \
- false, /* Channel not refreshed automatically. */ \
- dacPRSSELCh0 /* Select PRS ch0 (if PRS triggering enabled). */ \
-}
-
+ { \
+ false, /* Leave channel disabled when init done. */ \
+ false, /* Disable PRS triggering. */ \
+ false, /* Channel not refreshed automatically. */ \
+ dacPRSSELCh0 /* Select PRS ch0 (if PRS triggering enabled). */ \
+ }
/*******************************************************************************
***************************** PROTOTYPES **********************************
@@ -256,14 +242,13 @@
* @param[in] value
* Value to write to the channel 0 output register CH0DATA.
******************************************************************************/
-__STATIC_INLINE void DAC_Channel0OutputSet( DAC_TypeDef *dac,
- uint32_t value )
+__STATIC_INLINE void DAC_Channel0OutputSet(DAC_TypeDef *dac,
+ uint32_t value)
{
- EFM_ASSERT(value<=_DAC_CH0DATA_MASK);
+ EFM_ASSERT(value <= _DAC_CH0DATA_MASK);
dac->CH0DATA = value;
}
-
/***************************************************************************//**
* @brief
* Set the output signal of DAC channel 1 to a given value.
@@ -278,14 +263,13 @@
* @param[in] value
* Value to write to the channel 1 output register CH1DATA.
******************************************************************************/
-__STATIC_INLINE void DAC_Channel1OutputSet( DAC_TypeDef *dac,
- uint32_t value )
+__STATIC_INLINE void DAC_Channel1OutputSet(DAC_TypeDef *dac,
+ uint32_t value)
{
- EFM_ASSERT(value<=_DAC_CH1DATA_MASK);
+ EFM_ASSERT(value <= _DAC_CH1DATA_MASK);
dac->CH1DATA = value;
}
-
/***************************************************************************//**
* @brief
* Clear one or more pending DAC interrupts.
@@ -302,7 +286,6 @@
dac->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more DAC interrupts.
@@ -319,7 +302,6 @@
dac->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more DAC interrupts.
@@ -341,7 +323,6 @@
dac->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending DAC interrupt flags.
@@ -361,7 +342,6 @@
return dac->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending DAC interrupt flags.
@@ -393,7 +373,6 @@
return dac->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending DAC interrupts from SW.
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_dbg.h
* @brief Debug (DBG) API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -30,14 +30,13 @@
*
******************************************************************************/
-
#ifndef EM_DBG_H
#define EM_DBG_H
#include <stdbool.h>
#include "em_device.h"
-#if defined( CoreDebug_DHCSR_C_DEBUGEN_Msk )
+#if defined(CoreDebug_DHCSR_C_DEBUGEN_Msk)
#ifdef __cplusplus
extern "C" {
@@ -57,7 +56,7 @@
***************************** PROTOTYPES **********************************
******************************************************************************/
-#if defined( GPIO_ROUTE_SWCLKPEN ) || defined( GPIO_ROUTEPEN_SWCLKTCKPEN )
+#if defined(GPIO_ROUTE_SWCLKPEN) || defined(GPIO_ROUTEPEN_SWCLKTCKPEN)
/***************************************************************************//**
* @brief
* Check if a debugger is connected (and debug session activated)
@@ -76,8 +75,7 @@
}
#endif
-
-#if defined( GPIO_ROUTE_SWOPEN ) || defined( GPIO_ROUTEPEN_SWVPEN )
+#if defined(GPIO_ROUTE_SWOPEN) || defined(GPIO_ROUTEPEN_SWVPEN)
void DBG_SWOEnable(unsigned int location);
#endif
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_dma.h
* @brief Direct memory access (DMA) API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -34,7 +34,7 @@
#define EM_DMA_H
#include "em_device.h"
-#if defined( DMA_PRESENT )
+#if defined(DMA_PRESENT)
#include <stdio.h>
#include <stdbool.h>
@@ -61,27 +61,22 @@
* Amount source/destination address should be incremented for each data
* transfer.
*/
-typedef enum
-{
+typedef enum {
dmaDataInc1 = _DMA_CTRL_SRC_INC_BYTE, /**< Increment address 1 byte. */
dmaDataInc2 = _DMA_CTRL_SRC_INC_HALFWORD, /**< Increment address 2 bytes. */
dmaDataInc4 = _DMA_CTRL_SRC_INC_WORD, /**< Increment address 4 bytes. */
dmaDataIncNone = _DMA_CTRL_SRC_INC_NONE /**< Do not increment address. */
} DMA_DataInc_TypeDef;
-
/** Data sizes (in number of bytes) to be read/written by DMA transfer. */
-typedef enum
-{
+typedef enum {
dmaDataSize1 = _DMA_CTRL_SRC_SIZE_BYTE, /**< 1 byte DMA transfer size. */
dmaDataSize2 = _DMA_CTRL_SRC_SIZE_HALFWORD, /**< 2 byte DMA transfer size. */
dmaDataSize4 = _DMA_CTRL_SRC_SIZE_WORD /**< 4 byte DMA transfer size. */
} DMA_DataSize_TypeDef;
-
/** Type of DMA transfer. */
-typedef enum
-{
+typedef enum {
/** Basic DMA cycle. */
dmaCycleCtrlBasic = _DMA_CTRL_CYCLE_CTRL_BASIC,
/** Auto-request DMA cycle. */
@@ -94,10 +89,8 @@
dmaCycleCtrlPerScatterGather = _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER
} DMA_CycleCtrl_TypeDef;
-
/** Number of transfers before controller does new arbitration. */
-typedef enum
-{
+typedef enum {
dmaArbitrate1 = _DMA_CTRL_R_POWER_1, /**< Arbitrate after 1 DMA transfer. */
dmaArbitrate2 = _DMA_CTRL_R_POWER_2, /**< Arbitrate after 2 DMA transfers. */
dmaArbitrate4 = _DMA_CTRL_R_POWER_4, /**< Arbitrate after 4 DMA transfers. */
@@ -111,7 +104,6 @@
dmaArbitrate1024 = _DMA_CTRL_R_POWER_1024 /**< Arbitrate after 1024 DMA transfers. */
} DMA_ArbiterConfig_TypeDef;
-
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
@@ -134,7 +126,6 @@
*/
typedef void (*DMA_FuncPtr_TypeDef)(unsigned int channel, bool primary, void *user);
-
/**
* @brief
* Callback structure that can be used to define DMA complete actions.
@@ -145,8 +136,7 @@
* handled by one common callback, using the provided 'primary' parameter
* with the callback function.
*/
-typedef struct
-{
+typedef struct {
/**
* Pointer to callback function to invoke when DMA transfer cycle done.
* Notice that this function is invoked in interrupt context, and therefore
@@ -165,10 +155,8 @@
uint8_t primary;
} DMA_CB_TypeDef;
-
/** Configuration structure for a channel. */
-typedef struct
-{
+typedef struct {
/**
* Select if channel priority is in the high or default priority group
* with respect to arbitration. Within a priority group, lower numbered
@@ -208,13 +196,11 @@
DMA_CB_TypeDef *cb;
} DMA_CfgChannel_TypeDef;
-
/**
* Configuration structure for primary or alternate descriptor
* (not used for scatter-gather DMA cycles).
*/
-typedef struct
-{
+typedef struct {
/** Destination increment size for each DMA transfer */
DMA_DataInc_TypeDef dstInc;
@@ -242,13 +228,11 @@
uint8_t hprot;
} DMA_CfgDescr_TypeDef;
-
-#if defined( _DMA_LOOP0_MASK ) && defined( _DMA_LOOP1_MASK )
+#if defined(_DMA_LOOP0_MASK) && defined(_DMA_LOOP1_MASK)
/**
* Configuration structure for loop mode
*/
-typedef struct
-{
+typedef struct {
/** Enable repeated loop */
bool enable;
/** Width of transfer, reload value for nMinus1 */
@@ -256,13 +240,11 @@
} DMA_CfgLoop_TypeDef;
#endif
-
-#if defined( _DMA_RECT0_MASK )
+#if defined(_DMA_RECT0_MASK)
/**
* Configuration structure for rectangular copy
*/
-typedef struct
-{
+typedef struct {
/** DMA channel destination stride (width of destination image, distance between lines) */
uint16_t dstStride;
/** DMA channel source stride (width of source image, distance between lines) */
@@ -272,10 +254,8 @@
} DMA_CfgRect_TypeDef;
#endif
-
/** Configuration structure for alternate scatter-gather descriptor. */
-typedef struct
-{
+typedef struct {
/** Pointer to location to transfer data from. */
void *src;
@@ -320,10 +300,8 @@
bool peripheral;
} DMA_CfgDescrSGAlt_TypeDef;
-
/** DMA init structure */
-typedef struct
-{
+typedef struct {
/**
* HPROT signal state when accessing the primary/alternate
* descriptors. Normally set to 0 if protection is not an issue.
@@ -352,7 +330,6 @@
DMA_DESCRIPTOR_TypeDef *controlBlock;
} DMA_Init_TypeDef;
-
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@@ -384,15 +361,15 @@
void DMA_CfgDescr(unsigned int channel,
bool primary,
DMA_CfgDescr_TypeDef *cfg);
-#if defined( _DMA_LOOP0_MASK ) && defined( _DMA_LOOP1_MASK )
+#if defined(_DMA_LOOP0_MASK) && defined(_DMA_LOOP1_MASK)
void DMA_CfgLoop(unsigned int channel, DMA_CfgLoop_TypeDef *cfg);
#endif
-#if defined( _DMA_RECT0_MASK )
+#if defined(_DMA_RECT0_MASK)
void DMA_CfgRect(unsigned int channel, DMA_CfgRect_TypeDef *cfg);
#endif
-#if defined( _DMA_LOOP0_MASK ) && defined( _DMA_LOOP1_MASK )
+#if defined(_DMA_LOOP0_MASK) && defined(_DMA_LOOP1_MASK)
/***************************************************************************//**
* @brief
* Clear Loop configuration for channel
@@ -403,8 +380,7 @@
__STATIC_INLINE void DMA_ResetLoop(unsigned int channel)
{
/* Clean loop copy operation */
- switch(channel)
- {
+ switch (channel) {
case 0:
DMA->LOOP0 = _DMA_LOOP0_RESETVALUE;
break;
@@ -417,8 +393,7 @@
}
#endif
-
-#if defined( _DMA_RECT0_MASK )
+#if defined(_DMA_RECT0_MASK)
/***************************************************************************//**
* @brief
* Clear Rect/2D DMA configuration for channel
@@ -464,7 +439,6 @@
DMA->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more DMA interrupts.
@@ -478,7 +452,6 @@
DMA->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more DMA interrupts.
@@ -497,7 +470,6 @@
DMA->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending DMA interrupt flags.
@@ -514,7 +486,6 @@
return DMA->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending DMA interrupt flags.
@@ -537,7 +508,6 @@
return DMA->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending DMA interrupts
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_ebi.h
* @brief External Bus Iterface (EBI) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -82,28 +82,88 @@
#define EBI_CS2 (uint32_t)(1 << 3) /**< EBI chip select line 2 */
#define EBI_CS3 (uint32_t)(1 << 4) /**< EBI chip select line 3 */
+#if defined(_EBI_ROUTE_MASK) && defined(_EBI_ROUTE_APEN_MASK)
+#define EBI_GENERIC_ALB_A0 EBI_ROUTE_ALB_A0
+#define EBI_GENERIC_ALB_A8 EBI_ROUTE_ALB_A8
+#define EBI_GENERIC_ALB_A16 EBI_ROUTE_ALB_A16
+#define EBI_GENERIC_ALB_A24 EBI_ROUTE_ALB_A24
+#define EBI_GENERIC_APEN_A0 EBI_ROUTE_APEN_A0
+#define EBI_GENERIC_APEN_A5 EBI_ROUTE_APEN_A5
+#define EBI_GENERIC_APEN_A6 EBI_ROUTE_APEN_A6
+#define EBI_GENERIC_APEN_A7 EBI_ROUTE_APEN_A7
+#define EBI_GENERIC_APEN_A8 EBI_ROUTE_APEN_A8
+#define EBI_GENERIC_APEN_A9 EBI_ROUTE_APEN_A9
+#define EBI_GENERIC_APEN_A10 EBI_ROUTE_APEN_A10
+#define EBI_GENERIC_APEN_A11 EBI_ROUTE_APEN_A11
+#define EBI_GENERIC_APEN_A12 EBI_ROUTE_APEN_A12
+#define EBI_GENERIC_APEN_A13 EBI_ROUTE_APEN_A13
+#define EBI_GENERIC_APEN_A14 EBI_ROUTE_APEN_A14
+#define EBI_GENERIC_APEN_A15 EBI_ROUTE_APEN_A15
+#define EBI_GENERIC_APEN_A16 EBI_ROUTE_APEN_A16
+#define EBI_GENERIC_APEN_A17 EBI_ROUTE_APEN_A17
+#define EBI_GENERIC_APEN_A18 EBI_ROUTE_APEN_A18
+#define EBI_GENERIC_APEN_A19 EBI_ROUTE_APEN_A19
+#define EBI_GENERIC_APEN_A20 EBI_ROUTE_APEN_A20
+#define EBI_GENERIC_APEN_A21 EBI_ROUTE_APEN_A21
+#define EBI_GENERIC_APEN_A22 EBI_ROUTE_APEN_A22
+#define EBI_GENERIC_APEN_A23 EBI_ROUTE_APEN_A23
+#define EBI_GENERIC_APEN_A24 EBI_ROUTE_APEN_A24
+#define EBI_GENERIC_APEN_A25 EBI_ROUTE_APEN_A25
+#define EBI_GENERIC_APEN_A26 EBI_ROUTE_APEN_A26
+#define EBI_GENERIC_APEN_A27 EBI_ROUTE_APEN_A27
+#define EBI_GENERIC_APEN_A28 EBI_ROUTE_APEN_A28
+#elif defined(_EBI_ROUTEPEN_MASK)
+#define EBI_GENERIC_ALB_A0 EBI_ROUTEPEN_ALB_A0
+#define EBI_GENERIC_ALB_A8 EBI_ROUTEPEN_ALB_A8
+#define EBI_GENERIC_ALB_A16 EBI_ROUTEPEN_ALB_A16
+#define EBI_GENERIC_ALB_A24 EBI_ROUTEPEN_ALB_A24
+#define EBI_GENERIC_APEN_A0 EBI_ROUTEPEN_APEN_A0
+#define EBI_GENERIC_APEN_A5 EBI_ROUTEPEN_APEN_A5
+#define EBI_GENERIC_APEN_A6 EBI_ROUTEPEN_APEN_A6
+#define EBI_GENERIC_APEN_A7 EBI_ROUTEPEN_APEN_A7
+#define EBI_GENERIC_APEN_A8 EBI_ROUTEPEN_APEN_A8
+#define EBI_GENERIC_APEN_A9 EBI_ROUTEPEN_APEN_A9
+#define EBI_GENERIC_APEN_A10 EBI_ROUTEPEN_APEN_A10
+#define EBI_GENERIC_APEN_A11 EBI_ROUTEPEN_APEN_A11
+#define EBI_GENERIC_APEN_A12 EBI_ROUTEPEN_APEN_A12
+#define EBI_GENERIC_APEN_A13 EBI_ROUTEPEN_APEN_A13
+#define EBI_GENERIC_APEN_A14 EBI_ROUTEPEN_APEN_A14
+#define EBI_GENERIC_APEN_A15 EBI_ROUTEPEN_APEN_A15
+#define EBI_GENERIC_APEN_A16 EBI_ROUTEPEN_APEN_A16
+#define EBI_GENERIC_APEN_A17 EBI_ROUTEPEN_APEN_A17
+#define EBI_GENERIC_APEN_A18 EBI_ROUTEPEN_APEN_A18
+#define EBI_GENERIC_APEN_A19 EBI_ROUTEPEN_APEN_A19
+#define EBI_GENERIC_APEN_A20 EBI_ROUTEPEN_APEN_A20
+#define EBI_GENERIC_APEN_A21 EBI_ROUTEPEN_APEN_A21
+#define EBI_GENERIC_APEN_A22 EBI_ROUTEPEN_APEN_A22
+#define EBI_GENERIC_APEN_A23 EBI_ROUTEPEN_APEN_A23
+#define EBI_GENERIC_APEN_A24 EBI_ROUTEPEN_APEN_A24
+#define EBI_GENERIC_APEN_A25 EBI_ROUTEPEN_APEN_A25
+#define EBI_GENERIC_APEN_A26 EBI_ROUTEPEN_APEN_A26
+#define EBI_GENERIC_APEN_A27 EBI_ROUTEPEN_APEN_A27
+#define EBI_GENERIC_APEN_A28 EBI_ROUTEPEN_APEN_A28
+#endif
+
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** EBI Mode of operation */
-typedef enum
-{
+typedef enum {
/** 8 data bits, 8 address bits */
ebiModeD8A8 = EBI_CTRL_MODE_D8A8,
/** 16 data bits, 16 address bits, using address latch enable */
ebiModeD16A16ALE = EBI_CTRL_MODE_D16A16ALE,
/** 8 data bits, 24 address bits, using address latch enable */
ebiModeD8A24ALE = EBI_CTRL_MODE_D8A24ALE,
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(EBI_CTRL_MODE_D16)
/** Mode D16 */
ebiModeD16 = EBI_CTRL_MODE_D16,
#endif
} EBI_Mode_TypeDef;
/** EBI Polarity configuration */
-typedef enum
-{
+typedef enum {
/** Active Low */
ebiActiveLow = 0,
/** Active High */
@@ -111,8 +171,7 @@
} EBI_Polarity_TypeDef;
/** EBI Pin Line types */
-typedef enum
-{
+typedef enum {
/** Address Ready line */
ebiLineARDY,
/** Address Latch Enable line */
@@ -123,11 +182,11 @@
ebiLineRE,
/** Chip Select line */
ebiLineCS,
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(_EBI_POLARITY_BLPOL_MASK)
/** BL line */
ebiLineBL,
#endif
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(_EBI_TFTPOLARITY_MASK)
/** TFT VSYNC line */
ebiLineTFTVSync,
/** TFT HSYNC line */
@@ -141,75 +200,75 @@
#endif
} EBI_Line_TypeDef;
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if !defined(_EFM32_GECKO_FAMILY)
/** Address Pin Enable, lower limit - lower range of pins to enable */
-typedef enum
-{
+typedef enum {
/** Adress lines EBI_A[0] and upwards are enabled by APEN */
- ebiALowA0 = EBI_ROUTE_ALB_A0,
+ ebiALowA0 = EBI_GENERIC_ALB_A0,
/** Adress lines EBI_A[8] and upwards are enabled by APEN */
- ebiALowA8 = EBI_ROUTE_ALB_A8,
+ ebiALowA8 = EBI_GENERIC_ALB_A8,
/** Adress lines EBI_A[16] and upwards are enabled by APEN */
- ebiALowA16 = EBI_ROUTE_ALB_A16,
+ ebiALowA16 = EBI_GENERIC_ALB_A16,
/** Adress lines EBI_A[24] and upwards are enabled by APEN */
- ebiALowA24 = EBI_ROUTE_ALB_A24,
+ ebiALowA24 = EBI_GENERIC_ALB_A24,
} EBI_ALow_TypeDef;
/** Adress Pin Enable, high limit - higher limit of pins to enable */
-typedef enum
-{
+typedef enum {
/** All EBI_A pins are disabled */
- ebiAHighA0 = EBI_ROUTE_APEN_A0,
+ ebiAHighA0 = EBI_GENERIC_APEN_A0,
/** All EBI_A[4:ALow] are enabled */
- ebiAHighA5 = EBI_ROUTE_APEN_A5,
+ ebiAHighA5 = EBI_GENERIC_APEN_A5,
/** All EBI_A[5:ALow] are enabled */
- ebiAHighA6 = EBI_ROUTE_APEN_A6,
+ ebiAHighA6 = EBI_GENERIC_APEN_A6,
/** All EBI_A[6:ALow] are enabled */
- ebiAHighA7 = EBI_ROUTE_APEN_A7,
+ ebiAHighA7 = EBI_GENERIC_APEN_A7,
/** All EBI_A[7:ALow] are enabled */
- ebiAHighA8 = EBI_ROUTE_APEN_A8,
+ ebiAHighA8 = EBI_GENERIC_APEN_A8,
/** All EBI_A[8:ALow] are enabled */
- ebiAHighA9 = EBI_ROUTE_APEN_A9,
+ ebiAHighA9 = EBI_GENERIC_APEN_A9,
/** All EBI_A[9:ALow] are enabled */
- ebiAHighA10 = EBI_ROUTE_APEN_A10,
+ ebiAHighA10 = EBI_GENERIC_APEN_A10,
/** All EBI_A[10:ALow] are enabled */
- ebiAHighA11 = EBI_ROUTE_APEN_A11,
+ ebiAHighA11 = EBI_GENERIC_APEN_A11,
/** All EBI_A[11:ALow] are enabled */
- ebiAHighA12 = EBI_ROUTE_APEN_A12,
+ ebiAHighA12 = EBI_GENERIC_APEN_A12,
/** All EBI_A[12:ALow] are enabled */
- ebiAHighA13 = EBI_ROUTE_APEN_A13,
+ ebiAHighA13 = EBI_GENERIC_APEN_A13,
/** All EBI_A[13:ALow] are enabled */
- ebiAHighA14 = EBI_ROUTE_APEN_A14,
+ ebiAHighA14 = EBI_GENERIC_APEN_A14,
/** All EBI_A[14:ALow] are enabled */
- ebiAHighA15 = EBI_ROUTE_APEN_A15,
+ ebiAHighA15 = EBI_GENERIC_APEN_A15,
/** All EBI_A[15:ALow] are enabled */
- ebiAHighA16 = EBI_ROUTE_APEN_A16,
+ ebiAHighA16 = EBI_GENERIC_APEN_A16,
/** All EBI_A[16:ALow] are enabled */
- ebiAHighA17 = EBI_ROUTE_APEN_A17,
+ ebiAHighA17 = EBI_GENERIC_APEN_A17,
/** All EBI_A[17:ALow] are enabled */
- ebiAHighA18 = EBI_ROUTE_APEN_A18,
+ ebiAHighA18 = EBI_GENERIC_APEN_A18,
/** All EBI_A[18:ALow] are enabled */
- ebiAHighA19 = EBI_ROUTE_APEN_A19,
+ ebiAHighA19 = EBI_GENERIC_APEN_A19,
/** All EBI_A[19:ALow] are enabled */
- ebiAHighA20 = EBI_ROUTE_APEN_A20,
+ ebiAHighA20 = EBI_GENERIC_APEN_A20,
/** All EBI_A[20:ALow] are enabled */
- ebiAHighA21 = EBI_ROUTE_APEN_A21,
+ ebiAHighA21 = EBI_GENERIC_APEN_A21,
/** All EBI_A[21:ALow] are enabled */
- ebiAHighA22 = EBI_ROUTE_APEN_A22,
+ ebiAHighA22 = EBI_GENERIC_APEN_A22,
/** All EBI_A[22:ALow] are enabled */
- ebiAHighA23 = EBI_ROUTE_APEN_A23,
+ ebiAHighA23 = EBI_GENERIC_APEN_A23,
/** All EBI_A[23:ALow] are enabled */
- ebiAHighA24 = EBI_ROUTE_APEN_A24,
+ ebiAHighA24 = EBI_GENERIC_APEN_A24,
/** All EBI_A[24:ALow] are enabled */
- ebiAHighA25 = EBI_ROUTE_APEN_A25,
+ ebiAHighA25 = EBI_GENERIC_APEN_A25,
/** All EBI_A[25:ALow] are enabled */
- ebiAHighA26 = EBI_ROUTE_APEN_A26,
+ ebiAHighA26 = EBI_GENERIC_APEN_A26,
/** All EBI_A[26:ALow] are enabled */
- ebiAHighA27 = EBI_ROUTE_APEN_A27,
+ ebiAHighA27 = EBI_GENERIC_APEN_A27,
/** All EBI_A[27:ALow] are enabled */
- ebiAHighA28 = EBI_ROUTE_APEN_A28,
+ ebiAHighA28 = EBI_GENERIC_APEN_A28,
} EBI_AHigh_TypeDef;
+#endif
+#if defined(_EBI_ROUTE_LOCATION_MASK)
/** EBI I/O Alternate Pin Location */
typedef enum {
/** EBI PIN I/O Location 0 */
@@ -221,11 +280,11 @@
} EBI_Location_TypeDef;
#endif
+#if defined(_EBI_TFTCTRL_MASK)
/* TFT support */
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+
/** EBI TFT Graphics Bank Select */
-typedef enum
-{
+typedef enum {
/** Memory BANK0 contains frame buffer */
ebiTFTBank0 = EBI_TFTCTRL_BANKSEL_BANK0,
/** Memory BANK1 contains frame buffer */
@@ -237,8 +296,7 @@
} EBI_TFTBank_TypeDef;
/** Masking and Alpha blending source color*/
-typedef enum
-{
+typedef enum {
/** Use memory as source color for masking/alpha blending */
ebiTFTColorSrcMem = EBI_TFTCTRL_COLOR1SRC_MEM,
/** Use PIXEL1 register as source color for masking/alpha blending */
@@ -246,8 +304,7 @@
} EBI_TFTColorSrc_TypeDef;
/** Bus Data Interleave Mode */
-typedef enum
-{
+typedef enum {
/** Unlimited interleaved accesses per EBI_DCLK period. Can cause jitter */
ebiTFTInterleaveUnlimited = EBI_TFTCTRL_INTERLEAVE_UNLIMITED,
/** Allow 1 interleaved access per EBI_DCLK period */
@@ -257,8 +314,7 @@
} EBI_TFTInterleave_TypeDef;
/** Control frame base pointer copy */
-typedef enum
-{
+typedef enum {
/** Trigger update of frame buffer pointer on vertical sync */
ebiTFTFrameBufTriggerVSync = EBI_TFTCTRL_FBCTRIG_VSYNC,
/** Trigger update of frame buffer pointer on horizontal sync */
@@ -266,8 +322,7 @@
} EBI_TFTFrameBufTrigger_TypeDef;
/** Control of mask and alpha blending mode */
-typedef enum
-{
+typedef enum {
/** Masking and blending are disabled */
ebiTFTMBDisabled = EBI_TFTCTRL_MASKBLEND_DISABLED,
/** Internal masking */
@@ -275,18 +330,30 @@
/** Internal alpha blending */
ebiTFTMBIAlpha = EBI_TFTCTRL_MASKBLEND_IALPHA,
/** Internal masking and alpha blending are enabled */
+#if defined(EBI_TFTCTRL_MASKBLEND_IMASKIALPHA)
ebiTFTMBIMaskAlpha = EBI_TFTCTRL_MASKBLEND_IMASKIALPHA,
+#else
+ ebiTFTMBIMaskAlpha = EBI_TFTCTRL_MASKBLEND_IMASKALPHA,
+#endif
+#if defined(EBI_TFTCTRL_MASKBLEND_EMASK)
/** External masking */
ebiTFTMBEMask = EBI_TFTCTRL_MASKBLEND_EMASK,
/** External alpha blending */
ebiTFTMBEAlpha = EBI_TFTCTRL_MASKBLEND_EALPHA,
/** External masking and alpha blending */
ebiTFTMBEMaskAlpha = EBI_TFTCTRL_MASKBLEND_EMASKEALPHA,
+#else
+ /** External masking */
+ ebiTFTMBEMask = EBI_TFTCTRL_MASKBLEND_EFBMASK,
+ /** External alpha blending */
+ ebiTFTMBEAlpha = EBI_TFTCTRL_MASKBLEND_EFBALPHA,
+ /** External masking and alpha blending */
+ ebiTFTMBEMaskAlpha = EBI_TFTCTRL_MASKBLEND_EFBMASKALPHA,
+#endif
} EBI_TFTMaskBlend_TypeDef;
/** TFT Direct Drive mode */
-typedef enum
-{
+typedef enum {
/** Disabled */
ebiTFTDDModeDisabled = EBI_TFTCTRL_DD_DISABLED,
/** Direct Drive from internal memory */
@@ -296,23 +363,21 @@
} EBI_TFTDDMode_TypeDef;
/** TFT Data Increment Width */
-typedef enum
-{
+typedef enum {
/** Pixel increments are 1 byte at a time */
ebiTFTWidthByte = EBI_TFTCTRL_WIDTH_BYTE,
/** Pixel increments are 2 bytes (half word) */
ebiTFTWidthHalfWord = EBI_TFTCTRL_WIDTH_HALFWORD,
} EBI_TFTWidth_TypeDef;
-#endif
+#endif // _EBI_TFTCTRL_MASK
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** EBI Initialization structure */
-typedef struct
-{
+typedef struct {
/** EBI operation mode, data and address limits */
EBI_Mode_TypeDef mode;
/** Address Ready pin polarity, active high or low */
@@ -325,8 +390,8 @@
EBI_Polarity_TypeDef rePolarity;
/** Chip Select pin polarity, active high or low */
EBI_Polarity_TypeDef csPolarity;
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
- /** Byte Lane pin polaritym, active high or low */
+#if !defined(_EFM32_GECKO_FAMILY)
+ /** Byte Lane pin polarity, active high or low */
EBI_Polarity_TypeDef blPolarity;
/** Flag to enable or disable Byte Lane support */
bool blEnable;
@@ -345,7 +410,7 @@
int addrSetupCycles;
/** Number of cycles address is driven onto the ADDRDAT bus before ALE is asserted */
int addrHoldCycles;
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if !defined(_EFM32_GECKO_FAMILY)
/** Enable or disables half cycle duration of the ALE strobe in the last address setup cycle */
bool addrHalfALE;
#endif
@@ -355,7 +420,7 @@
int readStrobeCycles;
/** Number of cycles CSn is held active after REn is deasserted */
int readHoldCycles;
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if !defined(_EFM32_GECKO_FAMILY)
/** Enable or disable page mode reads */
bool readPageMode;
/** Enables or disable prefetching from sequential addresses */
@@ -369,7 +434,7 @@
int writeStrobeCycles;
/** Number of cycles CSn is held active after WEn is deasserted */
int writeHoldCycles;
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if !defined(_EFM32_GECKO_FAMILY)
/** Enable or disable the write buffer */
bool writeBufferDisable;
/** Enables or disables half cycle duration of the WEn signal in the last strobe cycle */
@@ -378,6 +443,8 @@
EBI_ALow_TypeDef aLow;
/** High address pin limit to enable */
EBI_AHigh_TypeDef aHigh;
+#endif
+#if defined(_EBI_ROUTE_LOCATION_MASK)
/** Pin Location */
EBI_Location_TypeDef location;
#endif
@@ -386,71 +453,104 @@
} EBI_Init_TypeDef;
/** Default config for EBI init structures */
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(_SILICON_LABS_32B_SERIES_1)
#define EBI_INIT_DEFAULT \
-{ \
- ebiModeD8A8, /* 8 bit address, 8 bit data */ \
- ebiActiveLow, /* ARDY polarity */ \
- ebiActiveLow, /* ALE polarity */ \
- ebiActiveLow, /* WE polarity */ \
- ebiActiveLow, /* RE polarity */ \
- ebiActiveLow, /* CS polarity */ \
- ebiActiveLow, /* BL polarity */ \
- false, /* enable BL */ \
- false, /* enable NOIDLE */ \
- false, /* enable ARDY */ \
- false, /* don't disable ARDY timeout */ \
- EBI_BANK0, /* enable bank 0 */ \
- EBI_CS0, /* enable chip select 0 */ \
- 0, /* addr setup cycles */ \
- 1, /* addr hold cycles */ \
- false, /* do not enable half cycle ALE strobe */ \
- 0, /* read setup cycles */ \
- 0, /* read strobe cycles */ \
- 0, /* read hold cycles */ \
- false, /* disable page mode */ \
- false, /* disable prefetch */ \
- false, /* do not enable half cycle REn strobe */ \
- 0, /* write setup cycles */ \
- 0, /* write strobe cycles */ \
- 1, /* write hold cycles */ \
- false, /* do not disable the write buffer */ \
- false, /* do not enable halc cycle WEn strobe */ \
- ebiALowA0, /* ALB - Low bound, address lines */ \
- ebiAHighA0, /* APEN - High bound, address lines */ \
- ebiLocation0, /* Use Location 0 */ \
- true, /* enable EBI */ \
-}
+ { \
+ ebiModeD8A8, /* 8 bit address, 8 bit data */ \
+ ebiActiveLow, /* ARDY polarity */ \
+ ebiActiveLow, /* ALE polarity */ \
+ ebiActiveLow, /* WE polarity */ \
+ ebiActiveLow, /* RE polarity */ \
+ ebiActiveLow, /* CS polarity */ \
+ ebiActiveLow, /* BL polarity */ \
+ false, /* enable BL */ \
+ false, /* enable NOIDLE */ \
+ false, /* enable ARDY */ \
+ false, /* don't disable ARDY timeout */ \
+ EBI_BANK0, /* enable bank 0 */ \
+ EBI_CS0, /* enable chip select 0 */ \
+ 0, /* addr setup cycles */ \
+ 1, /* addr hold cycles */ \
+ false, /* do not enable half cycle ALE strobe */ \
+ 0, /* read setup cycles */ \
+ 0, /* read strobe cycles */ \
+ 0, /* read hold cycles */ \
+ false, /* disable page mode */ \
+ false, /* disable prefetch */ \
+ false, /* do not enable half cycle REn strobe */ \
+ 0, /* write setup cycles */ \
+ 0, /* write strobe cycles */ \
+ 1, /* write hold cycles */ \
+ false, /* do not disable the write buffer */ \
+ false, /* do not enable halc cycle WEn strobe */ \
+ ebiALowA0, /* ALB - Low bound, address lines */ \
+ ebiAHighA0, /* APEN - High bound, address lines */ \
+ true, /* enable EBI */ \
+ }
+#elif !defined(_EFM32_GECKO_FAMILY)
+#define EBI_INIT_DEFAULT \
+ { \
+ ebiModeD8A8, /* 8 bit address, 8 bit data */ \
+ ebiActiveLow, /* ARDY polarity */ \
+ ebiActiveLow, /* ALE polarity */ \
+ ebiActiveLow, /* WE polarity */ \
+ ebiActiveLow, /* RE polarity */ \
+ ebiActiveLow, /* CS polarity */ \
+ ebiActiveLow, /* BL polarity */ \
+ false, /* enable BL */ \
+ false, /* enable NOIDLE */ \
+ false, /* enable ARDY */ \
+ false, /* don't disable ARDY timeout */ \
+ EBI_BANK0, /* enable bank 0 */ \
+ EBI_CS0, /* enable chip select 0 */ \
+ 0, /* addr setup cycles */ \
+ 1, /* addr hold cycles */ \
+ false, /* do not enable half cycle ALE strobe */ \
+ 0, /* read setup cycles */ \
+ 0, /* read strobe cycles */ \
+ 0, /* read hold cycles */ \
+ false, /* disable page mode */ \
+ false, /* disable prefetch */ \
+ false, /* do not enable half cycle REn strobe */ \
+ 0, /* write setup cycles */ \
+ 0, /* write strobe cycles */ \
+ 1, /* write hold cycles */ \
+ false, /* do not disable the write buffer */ \
+ false, /* do not enable halc cycle WEn strobe */ \
+ ebiALowA0, /* ALB - Low bound, address lines */ \
+ ebiAHighA0, /* APEN - High bound, address lines */ \
+ ebiLocation0, /* Use Location 0 */ \
+ true, /* enable EBI */ \
+ }
#else
#define EBI_INIT_DEFAULT \
-{ \
- ebiModeD8A8, /* 8 bit address, 8 bit data */ \
- ebiActiveLow, /* ARDY polarity */ \
- ebiActiveLow, /* ALE polarity */ \
- ebiActiveLow, /* WE polarity */ \
- ebiActiveLow, /* RE polarity */ \
- ebiActiveLow, /* CS polarity */ \
- false, /* enable ARDY */ \
- false, /* don't disable ARDY timeout */ \
- EBI_BANK0, /* enable bank 0 */ \
- EBI_CS0, /* enable chip select 0 */ \
- 0, /* addr setup cycles */ \
- 1, /* addr hold cycles */ \
- 0, /* read setup cycles */ \
- 0, /* read strobe cycles */ \
- 0, /* read hold cycles */ \
- 0, /* write setup cycles */ \
- 0, /* write strobe cycles */ \
- 1, /* write hold cycles */ \
- true, /* enable EBI */ \
-}
+ { \
+ ebiModeD8A8, /* 8 bit address, 8 bit data */ \
+ ebiActiveLow, /* ARDY polarity */ \
+ ebiActiveLow, /* ALE polarity */ \
+ ebiActiveLow, /* WE polarity */ \
+ ebiActiveLow, /* RE polarity */ \
+ ebiActiveLow, /* CS polarity */ \
+ false, /* enable ARDY */ \
+ false, /* don't disable ARDY timeout */ \
+ EBI_BANK0, /* enable bank 0 */ \
+ EBI_CS0, /* enable chip select 0 */ \
+ 0, /* addr setup cycles */ \
+ 1, /* addr hold cycles */ \
+ 0, /* read setup cycles */ \
+ 0, /* read strobe cycles */ \
+ 0, /* read hold cycles */ \
+ 0, /* write setup cycles */ \
+ 0, /* write strobe cycles */ \
+ 1, /* write hold cycles */ \
+ true, /* enable EBI */ \
+ }
#endif
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(_EBI_TFTCTRL_MASK)
/** TFT Initialization structure */
-typedef struct
-{
+typedef struct {
/** External memory bank for driving display */
EBI_TFTBank_TypeDef bank;
/** Width */
@@ -507,36 +607,36 @@
/** Default configuration for EBI TFT init structure */
#define EBI_TFTINIT_DEFAULT \
-{ \
- ebiTFTBank0, /* Select EBI Bank 0 */ \
- ebiTFTWidthHalfWord, /* Select 2-byte increments */ \
- ebiTFTColorSrcMem, /* Use memory as source for mask/blending */ \
- ebiTFTInterleaveUnlimited, /* Unlimited interleaved accesses */ \
- ebiTFTFrameBufTriggerVSync, /* VSYNC as frame buffer update trigger */ \
- false, /* Drive DCLK from negative edge of internal clock */ \
- ebiTFTMBDisabled, /* No masking and alpha blending enabled */ \
- ebiTFTDDModeExternal, /* Drive from external memory */ \
- ebiActiveLow, /* CS Active Low polarity */ \
- ebiActiveLow, /* DCLK Active Low polarity */ \
- ebiActiveLow, /* DATAEN Active Low polarity */ \
- ebiActiveLow, /* HSYNC Active Low polarity */ \
- ebiActiveLow, /* VSYNC Active Low polarity */ \
- 320, /* Horizontal size in pixels */ \
- 1, /* Horizontal Front Porch */ \
- 29, /* Horizontal Back Porch */ \
- 2, /* Horizontal Synchronization Pulse Width */ \
- 240, /* Vertical size in pixels */ \
- 1, /* Vertical Front Porch */ \
- 4, /* Vertical Back Porch */ \
- 2, /* Vertical Synchronization Pulse Width */ \
- 0x0000, /* Address offset to EBI memory base */ \
- 5, /* DCLK Period */ \
- 2, /* DCLK Start */ \
- 1, /* DCLK Setup cycles */ \
- 1, /* DCLK Hold cycles */ \
-}
+ { \
+ ebiTFTBank0, /* Select EBI Bank 0 */ \
+ ebiTFTWidthHalfWord, /* Select 2-byte increments */ \
+ ebiTFTColorSrcMem, /* Use memory as source for mask/blending */ \
+ ebiTFTInterleaveUnlimited, /* Unlimited interleaved accesses */ \
+ ebiTFTFrameBufTriggerVSync, /* VSYNC as frame buffer update trigger */ \
+ false, /* Drive DCLK from negative edge of internal clock */ \
+ ebiTFTMBDisabled, /* No masking and alpha blending enabled */ \
+ ebiTFTDDModeExternal, /* Drive from external memory */ \
+ ebiActiveLow, /* CS Active Low polarity */ \
+ ebiActiveLow, /* DCLK Active Low polarity */ \
+ ebiActiveLow, /* DATAEN Active Low polarity */ \
+ ebiActiveLow, /* HSYNC Active Low polarity */ \
+ ebiActiveLow, /* VSYNC Active Low polarity */ \
+ 320, /* Horizontal size in pixels */ \
+ 1, /* Horizontal Front Porch */ \
+ 29, /* Horizontal Back Porch */ \
+ 2, /* Horizontal Synchronization Pulse Width */ \
+ 240, /* Vertical size in pixels */ \
+ 1, /* Vertical Front Porch */ \
+ 4, /* Vertical Back Porch */ \
+ 2, /* Vertical Synchronization Pulse Width */ \
+ 0x0000, /* Address offset to EBI memory base */ \
+ 5, /* DCLK Period */ \
+ 2, /* DCLK Start */ \
+ 1, /* DCLK Setup cycles */ \
+ 1, /* DCLK Hold cycles */ \
+ }
+#endif
-#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@@ -546,7 +646,7 @@
uint32_t EBI_BankAddress(uint32_t bank);
void EBI_BankEnable(uint32_t banks, bool enable);
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(_EBI_TFTCTRL_MASK)
void EBI_TFTInit(const EBI_TFTInit_TypeDef *ebiTFTInit);
void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical);
void EBI_TFTHPorchSet(int front, int back, int pulseWidth);
@@ -554,7 +654,7 @@
void EBI_TFTTimingSet(int dclkPeriod, int start, int setup, int hold);
#endif
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if !defined(_EFM32_GECKO_FAMILY)
/* This functionality is only available on devices with independent timing support */
void EBI_BankReadTimingSet(uint32_t bank, int setupCycles, int strobeCycles, int holdCycles);
void EBI_BankReadTimingConfig(uint32_t bank, bool pageMode, bool prefetch, bool halfRE);
@@ -568,7 +668,9 @@
void EBI_BankPolaritySet(uint32_t bank, EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity);
void EBI_BankByteLaneEnable(uint32_t bank, bool enable);
void EBI_AltMapEnable(bool enable);
+#endif
+#if defined(_EBI_TFTCTRL_MASK)
/***************************************************************************//**
* @brief
* Enable or disable TFT Direct Drive
@@ -581,7 +683,6 @@
EBI->TFTCTRL = (EBI->TFTCTRL & ~(_EBI_TFTCTRL_DD_MASK)) | (uint32_t) mode;
}
-
/***************************************************************************//**
* @brief
* Configure frame buffer pointer
@@ -594,7 +695,6 @@
EBI->TFTFRAMEBASE = (uint32_t) address;
}
-
/***************************************************************************//**
* @brief Set TFT Pixel Color 0 or 1
*
@@ -607,17 +707,14 @@
{
EFM_ASSERT(pixel == 0 || pixel == 1);
- if (pixel == 0)
- {
+ if (pixel == 0) {
EBI->TFTPIXEL0 = color;
}
- if (pixel == 1)
- {
+ if (pixel == 1) {
EBI->TFTPIXEL1 = color;
}
}
-
/***************************************************************************//**
* @brief Masking and Blending Mode Set
*
@@ -626,10 +723,9 @@
******************************************************************************/
__STATIC_INLINE void EBI_TFTMaskBlendMode(EBI_TFTMaskBlend_TypeDef maskBlend)
{
- EBI->TFTCTRL = (EBI->TFTCTRL & (~_EBI_TFTCTRL_MASKBLEND_MASK))|maskBlend;
+ EBI->TFTCTRL = (EBI->TFTCTRL & (~_EBI_TFTCTRL_MASKBLEND_MASK)) | maskBlend;
}
-
/***************************************************************************//**
* @brief Set TFT Alpha Blending Factor
*
@@ -641,7 +737,6 @@
EBI->TFTALPHA = alpha;
}
-
/***************************************************************************//**
* @brief Set TFT mask value
* Data accesses that matches this value are suppressed
@@ -652,7 +747,6 @@
EBI->TFTMASK = mask;
}
-
/***************************************************************************//**
* @brief Get current vertical position counter
* @return
@@ -663,7 +757,6 @@
return((EBI->TFTSTATUS & _EBI_TFTSTATUS_VCNT_MASK) >> _EBI_TFTSTATUS_VCNT_SHIFT);
}
-
/***************************************************************************//**
* @brief Get current horizontal position counter
* @return
@@ -674,7 +767,6 @@
return((EBI->TFTSTATUS & _EBI_TFTSTATUS_HCNT_MASK) >> _EBI_TFTSTATUS_HCNT_SHIFT);
}
-
/***************************************************************************//**
* @brief Set Frame Buffer Trigger
*
@@ -687,10 +779,9 @@
******************************************************************************/
__STATIC_INLINE void EBI_TFTFBTriggerSet(EBI_TFTFrameBufTrigger_TypeDef sync)
{
- EBI->TFTCTRL = ((EBI->TFTCTRL & ~_EBI_TFTCTRL_FBCTRIG_MASK)|sync);
+ EBI->TFTCTRL = ((EBI->TFTCTRL & ~_EBI_TFTCTRL_FBCTRIG_MASK) | sync);
}
-
/***************************************************************************//**
* @brief Set horizontal TFT stride value in number of bytes
*
@@ -702,11 +793,12 @@
{
EFM_ASSERT(nbytes < 0x1000);
- EBI->TFTSTRIDE = (EBI->TFTSTRIDE & ~(_EBI_TFTSTRIDE_HSTRIDE_MASK))|
- (nbytes<<_EBI_TFTSTRIDE_HSTRIDE_SHIFT);
+ EBI->TFTSTRIDE = (EBI->TFTSTRIDE & ~(_EBI_TFTSTRIDE_HSTRIDE_MASK))
+ | (nbytes << _EBI_TFTSTRIDE_HSTRIDE_SHIFT);
}
+#endif // _EBI_TFTCTRL_MASK
-
+#if defined(_EBI_IF_MASK)
/***************************************************************************//**
* @brief
* Clear one or more pending EBI interrupts.
@@ -719,7 +811,6 @@
EBI->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending EBI interrupts.
@@ -733,7 +824,6 @@
EBI->IFS = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more EBI interrupts.
@@ -747,7 +837,6 @@
EBI->IEN &= ~(flags);
}
-
/***************************************************************************//**
* @brief
* Enable one or more EBI interrupts.
@@ -761,7 +850,6 @@
EBI->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending EBI interrupt flags.
@@ -778,7 +866,6 @@
return EBI->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending EBI interrupt flags.
@@ -800,8 +887,9 @@
ien = EBI->IEN;
return EBI->IF & ien;
}
+#endif // _EBI_IF_MASK
-
+#if defined(_EBI_CMD_MASK)
/***************************************************************************//**
* @brief
* Start ECC generator on NAND flash transfers.
@@ -811,7 +899,6 @@
EBI->CMD = EBI_CMD_ECCSTART | EBI_CMD_ECCCLEAR;
}
-
/***************************************************************************//**
* @brief
* Stop NAND flash ECC generator and return generated ECC.
@@ -819,12 +906,12 @@
* @return
* The generated ECC.
******************************************************************************/
-__STATIC_INLINE uint32_t EBI_StopNandEccGen( void )
+__STATIC_INLINE uint32_t EBI_StopNandEccGen(void)
{
EBI->CMD = EBI_CMD_ECCSTOP;
return EBI->ECCPARITY;
}
-#endif
+#endif // _EBI_CMD_MASK
void EBI_ChipSelectEnable(uint32_t banks, bool enable);
void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles);
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_emu.h
* @brief Energy management unit (EMU) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -34,7 +34,7 @@
#define EM_EMU_H
#include "em_device.h"
-#if defined( EMU_PRESENT )
+#if defined(EMU_PRESENT)
#include <stdbool.h>
#include "em_bus.h"
@@ -57,10 +57,9 @@
******************************** ENUMS ************************************
******************************************************************************/
-#if defined( _EMU_EM4CONF_OSC_MASK )
+#if defined(_EMU_EM4CONF_OSC_MASK)
/** EM4 duty oscillator */
-typedef enum
-{
+typedef enum {
/** Select ULFRCO as duty oscillator in EM4 */
emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO,
/** Select LFXO as duty oscillator in EM4 */
@@ -70,10 +69,9 @@
} EMU_EM4Osc_TypeDef;
#endif
-#if defined( _EMU_BUCTRL_PROBE_MASK )
+#if defined(_EMU_BUCTRL_PROBE_MASK)
/** Backup Power Voltage Probe types */
-typedef enum
-{
+typedef enum {
/** Disable voltage probe */
emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE,
/** Connect probe to VDD_DREG */
@@ -85,10 +83,9 @@
} EMU_Probe_TypeDef;
#endif
-#if defined( _EMU_PWRCONF_PWRRES_MASK )
+#if defined(_EMU_PWRCONF_PWRRES_MASK)
/** Backup Power Domain resistor selection */
-typedef enum
-{
+typedef enum {
/** Main power and backup power connected with RES0 series resistance */
emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0,
/** Main power and backup power connected with RES1 series resistance */
@@ -100,10 +97,9 @@
} EMU_Resistor_TypeDef;
#endif
-#if defined( BU_PRESENT )
+#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
/** Backup Power Domain power connection */
-typedef enum
-{
+typedef enum {
/** No connection between main and backup power */
emuPower_None = EMU_BUINACT_PWRCON_NONE,
/** Main power and backup power connected through diode,
@@ -118,18 +114,16 @@
#endif
/** BOD threshold setting selector, active or inactive mode */
-typedef enum
-{
+typedef enum {
/** Configure BOD threshold for active mode */
emuBODMode_Active,
/** Configure BOD threshold for inactive mode */
emuBODMode_Inactive,
} EMU_BODMode_TypeDef;
-#if defined( _EMU_EM4CTRL_EM4STATE_MASK )
+#if defined(_EMU_EM4CTRL_EM4STATE_MASK)
/** EM4 modes */
-typedef enum
-{
+typedef enum {
/** EM4 Hibernate */
emuEM4Hibernate = EMU_EM4CTRL_EM4STATE_EM4H,
/** EM4 Shutoff */
@@ -137,32 +131,27 @@
} EMU_EM4State_TypeDef;
#endif
-
-#if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
-typedef enum
-{
+#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK)
+typedef enum {
/** No Retention: Pads enter reset state when entering EM4 */
emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE,
/** Retention through EM4: Pads enter reset state when exiting EM4 */
emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT,
- /** Retention through EM4 and wakeup: call EMU_UnlatchPinRetention() to
+ /** Retention through EM4 and wakeup: call @ref EMU_UnlatchPinRetention() to
release pins from retention after EM4 wakeup */
emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH,
} EMU_EM4PinRetention_TypeDef;
#endif
/** Power configurations. DCDC-to-DVDD is currently the only supported mode. */
-typedef enum
-{
+typedef enum {
/** DCDC is connected to DVDD */
emuPowerConfig_DcdcToDvdd,
} EMU_PowerConfig_TypeDef;
-
-#if defined( _EMU_DCDCCTRL_MASK )
+#if defined(_EMU_DCDCCTRL_MASK)
/** DCDC operating modes */
-typedef enum
-{
+typedef enum {
/** DCDC regulator bypass */
emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS,
/** DCDC low-noise mode */
@@ -174,10 +163,9 @@
} EMU_DcdcMode_TypeDef;
#endif
-#if defined( _EMU_DCDCCTRL_MASK )
+#if defined(_EMU_DCDCCTRL_MASK)
/** DCDC conduction modes */
-typedef enum
-{
+typedef enum {
/** DCDC Low-Noise Continuous Conduction Mode (CCM). EFR32 interference minimization
features are available in this mode. */
emuDcdcConductionMode_ContinuousLN,
@@ -187,10 +175,9 @@
} EMU_DcdcConductionMode_TypeDef;
#endif
-#if defined( _EMU_PWRCTRL_MASK )
+#if defined(_EMU_PWRCTRL_MASK)
/** DCDC to DVDD mode analog peripheral power supply select */
-typedef enum
-{
+typedef enum {
/** Select AVDD as analog power supply. Typically lower noise, but less energy efficient. */
emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD,
/** Select DCDC (DVDD) as analog power supply. Typically more energy efficient, but more noise. */
@@ -198,7 +185,7 @@
} EMU_DcdcAnaPeripheralPower_TypeDef;
#endif
-#if defined( _EMU_DCDCMISCCTRL_MASK )
+#if defined(_EMU_DCDCMISCCTRL_MASK)
/** DCDC Forced CCM and reverse current limiter control. Positive values have unit mA. */
typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef;
@@ -209,11 +196,9 @@
#define emuDcdcLnFastTransient 160
#endif
-
-#if defined( _EMU_DCDCCTRL_MASK )
+#if defined(_EMU_DCDCCTRL_MASK)
/** DCDC Low-noise RCO band select */
-typedef enum
-{
+typedef enum {
/** Set RCO to 3MHz */
emuDcdcLnRcoBand_3MHz = 0,
/** Set RCO to 4MHz */
@@ -245,11 +230,9 @@
/** @endcond */
#endif
-
-#if defined( _EMU_DCDCCTRL_MASK )
+#if defined(_EMU_DCDCCTRL_MASK)
/** DCDC Low Noise Compensator Control register. */
-typedef enum
-{
+typedef enum {
/** DCDC capacitor is 1uF. */
emuDcdcLnCompCtrl_1u0F,
/** DCDC capacitor is 4.7uF. */
@@ -257,32 +240,34 @@
} EMU_DcdcLnCompCtrl_TypeDef;
#endif
-
-#if defined( EMU_STATUS_VMONRDY )
+#if defined(EMU_STATUS_VMONRDY)
/** VMON channels */
-typedef enum
-{
+typedef enum {
emuVmonChannel_AVDD,
emuVmonChannel_ALTAVDD,
emuVmonChannel_DVDD,
- emuVmonChannel_IOVDD0
+ emuVmonChannel_IOVDD0,
+#if defined(_EMU_VMONIO1CTRL_EN_MASK)
+ emuVmonChannel_IOVDD1,
+#endif
+#if defined(_EMU_VMONBUVDDCTRL_EN_MASK)
+ emuVmonChannel_BUVDD,
+#endif
} EMU_VmonChannel_TypeDef;
#endif /* EMU_STATUS_VMONRDY */
-#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
/** Bias mode configurations */
-typedef enum
-{
+typedef enum {
emuBiasMode_1KHz,
emuBiasMode_4KHz,
emuBiasMode_Continuous
} EMU_BiasMode_TypeDef;
#endif
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
/** Supported EM0/1 Voltage Scaling Levels */
-typedef enum
-{
+typedef enum {
/** High-performance voltage level. HF clock can be set to any frequency. */
emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2,
/** Low-power optimized voltage level. The HF clock must be limited
@@ -294,27 +279,25 @@
} EMU_VScaleEM01_TypeDef;
#endif
-#if defined( _EMU_CTRL_EM23VSCALE_MASK )
+#if defined(_EMU_CTRL_EM23VSCALE_MASK)
/** Supported EM2/3 Voltage Scaling Levels */
-typedef enum
-{
+typedef enum {
/** Fast-wakeup voltage level. */
emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2,
/** Low-power optimized voltage level. Using this voltage level in EM2 and 3
- adds 20-25us to wakeup time if the EM0 and 1 voltage must be scaled
+ adds approximately 30us to wakeup time if the EM0 and 1 voltage must be scaled
up to @ref emuVScaleEM01_HighPerformance on EM2 or 3 exit. */
emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0,
} EMU_VScaleEM23_TypeDef;
#endif
-#if defined( _EMU_CTRL_EM4HVSCALE_MASK )
+#if defined(_EMU_CTRL_EM4HVSCALE_MASK)
/** Supported EM4H Voltage Scaling Levels */
-typedef enum
-{
+typedef enum {
/** Fast-wakeup voltage level. */
emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2,
/** Low-power optimized voltage level. Using this voltage level in EM4H
- adds 20-25us to wakeup time if the EM0 and 1 voltage must be scaled
+ adds approximately 30us to wakeup time if the EM0 and 1 voltage must be scaled
up to @ref emuVScaleEM01_HighPerformance on EM4H exit. */
emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0,
} EMU_VScaleEM4H_TypeDef;
@@ -322,43 +305,116 @@
#if defined(_EMU_EM23PERNORETAINCTRL_MASK)
/** Peripheral EM2 and 3 retention control */
-typedef enum
-{
- emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /* Select LEUART0 retention control */
- emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /* Select CSEN retention control */
- emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /* Select LESENSE0 retention control */
- emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /* Select LETIMER0 retention control */
- emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /* Select ADC0 retention control */
- emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /* Select IDAC0 retention control */
- emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK, /* Select DAC0 retention control */
- emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select I2C1 retention control */
- emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /* Select I2C0 retention control */
- emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /* Select ACMP1 retention control */
- emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /* Select ACMP0 retention control */
-#if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK )
- emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /* Select PCNT2 retention control */
- emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /* Select PCNT1 retention control */
+typedef enum {
+#if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK)
+ emuPeripheralRetention_USB = _EMU_EM23PERNORETAINCTRL_USBDIS_MASK, /* Select USB retention control */
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK)
+ emuPeripheralRetention_RTC = _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK, /* Select RTC retention control */
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK)
+ emuPeripheralRetention_ACMP3 = _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK, /* Select ACMP3 retention control */
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK)
+ emuPeripheralRetention_ACMP2 = _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK, /* Select ACMP2 retention control */
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK)
+ emuPeripheralRetention_ADC1 = _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK, /* Select ADC1 retention control */
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK)
+ emuPeripheralRetention_I2C2 = _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK, /* Select I2C2 retention control */
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK)
+ emuPeripheralRetention_LETIMER1 = _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK, /* Select LETIMER1 retention control */
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK)
+ emuPeripheralRetention_LCD = _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK, /* Select LCD retention control */
#endif
- emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /* Select PCNT0 retention control */
+#if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK)
+ emuPeripheralRetention_LEUART1 = _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK, /* Select LEUART1 retention control */
+#endif
+ emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /* Select LEUART0 retention control */
+#if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK)
+ emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /* Select CSEN retention control */
+#endif
+ emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /* Select LESENSE0 retention control */
+#if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK)
+ emuPeripheralRetention_WDOG1 = _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK, /* Select WDOG1 retention control */
+#endif
+ emuPeripheralRetention_WDOG0 = _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK, /* Select WDOG0 retention control */
+ emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /* Select LETIMER0 retention control */
+ emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /* Select ADC0 retention control */
+#if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK)
+ emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /* Select IDAC0 retention control */
+#endif
+ emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK, /* Select DAC0 retention control */
+#if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK)
+ emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select I2C1 retention control */
+#endif
+ emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /* Select I2C0 retention control */
+ emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /* Select ACMP1 retention control */
+ emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /* Select ACMP0 retention control */
+#if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK)
+ emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /* Select PCNT2 retention control */
+ emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /* Select PCNT1 retention control */
+#endif
+ emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /* Select PCNT0 retention control */
emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK
- | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK
- | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK
- | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK
- | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/* Select all peripherals in domain 1 */
+ | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK
+ | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK
+ | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK
+ | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/* Select all peripherals in domain 1 */
emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK
- | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK
- | _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK
- | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK
- | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK
-#if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK )
- | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK
- | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK
+#if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK)
+ | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK
+#endif
+ | _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK
+#if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK)
+ | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK
+#endif
+ | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK
+#if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK)
+ | _EMU_EM23PERNORETAINCTRL_USBDIS_MASK
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK)
+ | _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK)
+ | _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK)
+ | _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK)
+ | _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK
#endif
- | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK
- | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select all peripherals in domain 2 */
- emuPeripheralRetention_ALL = emuPeripheralRetention_D1
- | emuPeripheralRetention_D2, /* Select all peripherals with retention control */
+#if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK)
+ | _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK)
+ | _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK)
+ | _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK)
+ | _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK)
+ | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK
+ | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK
+#endif
+#if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK)
+ | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK /* Select all peripherals in domain 2 */
+#endif
+ | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK,
+ emuPeripheralRetention_ALL = emuPeripheralRetention_D1
+ | emuPeripheralRetention_D2
+#if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK)
+ | emuPeripheralRetention_WDOG1
+#endif
+ | emuPeripheralRetention_WDOG0, /* Select all peripherals with retention control */
} EMU_PeripheralRetention_TypeDef;
#endif
@@ -366,59 +422,56 @@
******************************* STRUCTS ***********************************
******************************************************************************/
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
/** EM0 and 1 initialization structure. Voltage scaling is applied when
the core clock frequency is changed from @ref CMU. EM0 an 1 emuVScaleEM01_HighPerformance
is always enabled. */
-typedef struct
-{
+typedef struct {
bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status */
} EMU_EM01Init_TypeDef;
#endif
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
/** Default initialization of EM0 and 1 configuration */
-#define EMU_EM01INIT_DEFAULT \
-{ \
- false /** Do not scale down in EM0/1 */ \
-}
+#define EMU_EM01INIT_DEFAULT \
+ { \
+ false /** Do not scale down in EM0/1 */ \
+ }
#endif
/** EM2 and 3 initialization structure */
-typedef struct
-{
+typedef struct {
bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3 */
-#if defined( _EMU_CTRL_EM23VSCALE_MASK )
+#if defined(_EMU_CTRL_EM23VSCALE_MASK)
EMU_VScaleEM23_TypeDef vScaleEM23Voltage; /**< EM2/3 voltage scaling level */
#endif
} EMU_EM23Init_TypeDef;
/** Default initialization of EM2 and 3 configuration */
-#if defined( _EMU_CTRL_EM4HVSCALE_MASK )
+#if defined(_EMU_CTRL_EM4HVSCALE_MASK)
#define EMU_EM23INIT_DEFAULT \
-{ \
- false, /* Reduced voltage regulator drive strength in EM2/3 */ \
- emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3 */ \
-}
+ { \
+ false, /* Reduced voltage regulator drive strength in EM2/3 */ \
+ emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3 */ \
+ }
#else
#define EMU_EM23INIT_DEFAULT \
-{ \
- false, /* Reduced voltage regulator drive strength in EM2/3 */ \
-}
+ { \
+ false, /* Reduced voltage regulator drive strength in EM2/3 */ \
+ }
#endif
-#if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
+#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK)
/** EM4 initialization structure */
-typedef struct
-{
-#if defined( _EMU_EM4CONF_MASK )
+typedef struct {
+#if defined(_EMU_EM4CONF_MASK)
/* Init parameters for platforms with EMU->EM4CONF register (Series 0) */
bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator */
bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4 */
EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator */
bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt */
bool vreg; /**< Enable EM4 voltage regulator */
-#elif defined( _EMU_EM4CTRL_MASK )
+#elif defined(_EMU_EM4CTRL_MASK)
/* Init parameters for platforms with EMU->EM4CTRL register (Series 1) */
bool retainLfxo; /**< Disable the LFXO upon EM4 entry */
bool retainLfrco; /**< Disable the LFRCO upon EM4 entry */
@@ -426,51 +479,50 @@
EMU_EM4State_TypeDef em4State; /**< Hibernate or shutoff EM4 state */
EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode */
#endif
-#if defined( _EMU_CTRL_EM4HVSCALE_MASK )
+#if defined(_EMU_CTRL_EM4HVSCALE_MASK)
EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;/**< EM4H voltage scaling level */
#endif
} EMU_EM4Init_TypeDef;
#endif
-#if defined( _EMU_EM4CONF_MASK )
+#if defined(_EMU_EM4CONF_MASK)
/** Default initialization of EM4 configuration (Series 0) */
-#define EMU_EM4INIT_DEFAULT \
-{ \
- false, /* Dont't lock configuration after it's been set */ \
- false, /* No reset will be asserted due to BOD in EM4 */ \
- emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator */ \
- true, /* Wake up on EM4 BURTC interrupt */ \
- true, /* Enable VREG */ \
-}
+#define EMU_EM4INIT_DEFAULT \
+ { \
+ false, /* Dont't lock configuration after it's been set */ \
+ false, /* No reset will be asserted due to BOD in EM4 */ \
+ emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator */ \
+ true, /* Wake up on EM4 BURTC interrupt */ \
+ true, /* Enable VREG */ \
+ }
-#elif defined( _EMU_CTRL_EM4HVSCALE_MASK )
+#elif defined(_EMU_CTRL_EM4HVSCALE_MASK)
/** Default initialization of EM4 configuration (Series 1 with VSCALE) */
-#define EMU_EM4INIT_DEFAULT \
-{ \
- false, /* Retain LFXO configuration upon EM4 entry */ \
- false, /* Retain LFRCO configuration upon EM4 entry */ \
- false, /* Retain ULFRCO configuration upon EM4 entry */ \
- emuEM4Shutoff, /* Use EM4 shutoff state */ \
- emuPinRetentionDisable, /* Do not retain pins in EM4 */ \
- emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H */ \
-}
+#define EMU_EM4INIT_DEFAULT \
+ { \
+ false, /* Retain LFXO configuration upon EM4 entry */ \
+ false, /* Retain LFRCO configuration upon EM4 entry */ \
+ false, /* Retain ULFRCO configuration upon EM4 entry */ \
+ emuEM4Shutoff, /* Use EM4 shutoff state */ \
+ emuPinRetentionDisable, /* Do not retain pins in EM4 */ \
+ emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H */ \
+ }
-#elif defined( _EMU_EM4CTRL_MASK )
+#elif defined(_EMU_EM4CTRL_MASK)
/** Default initialization of EM4 configuration (Series 1 without VSCALE) */
-#define EMU_EM4INIT_DEFAULT \
-{ \
- false, /* Retain LFXO configuration upon EM4 entry */ \
- false, /* Retain LFRCO configuration upon EM4 entry */ \
- false, /* Retain ULFRCO configuration upon EM4 entry */ \
- emuEM4Shutoff, /* Use EM4 shutoff state */ \
- emuPinRetentionDisable, /* Do not retain pins in EM4 */ \
-}
+#define EMU_EM4INIT_DEFAULT \
+ { \
+ false, /* Retain LFXO configuration upon EM4 entry */ \
+ false, /* Retain LFRCO configuration upon EM4 entry */ \
+ false, /* Retain ULFRCO configuration upon EM4 entry */ \
+ emuEM4Shutoff, /* Use EM4 shutoff state */ \
+ emuPinRetentionDisable, /* Do not retain pins in EM4 */ \
+ }
#endif
-#if defined( BU_PRESENT )
+#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
/** Backup Power Domain Initialization structure */
-typedef struct
-{
+typedef struct {
/* Backup Power Domain power configuration */
/** Voltage probe select, selects ADC voltage */
@@ -498,27 +550,26 @@
} EMU_BUPDInit_TypeDef;
/** Default Backup Power Domain configuration */
-#define EMU_BUPDINIT_DEFAULT \
-{ \
- emuProbe_Disable, /* Do not enable voltage probe */ \
- false, /* Disable BOD calibration mode */ \
- false, /* Disable BU_STAT pin for backup mode indication */ \
- \
- emuRes_Res0, /* RES0 series resistance between main and backup power */ \
- false, /* Don't enable strong switch */ \
- false, /* Don't enable medium switch */ \
- false, /* Don't enable weak switch */ \
- \
- emuPower_None, /* No connection between main and backup power (inactive mode) */ \
- emuPower_None, /* No connection between main and backup power (active mode) */ \
- true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset */ \
-}
+#define EMU_BUPDINIT_DEFAULT \
+ { \
+ emuProbe_Disable, /* Do not enable voltage probe */ \
+ false, /* Disable BOD calibration mode */ \
+ false, /* Disable BU_STAT pin for backup mode indication */ \
+ \
+ emuRes_Res0, /* RES0 series resistance between main and backup power */ \
+ false, /* Don't enable strong switch */ \
+ false, /* Don't enable medium switch */ \
+ false, /* Don't enable weak switch */ \
+ \
+ emuPower_None, /* No connection between main and backup power (inactive mode) */ \
+ emuPower_None, /* No connection between main and backup power (active mode) */ \
+ true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset */ \
+ }
#endif
-#if defined( _EMU_DCDCCTRL_MASK )
+#if defined(_EMU_DCDCCTRL_MASK)
/** DCDC initialization structure */
-typedef struct
-{
+typedef struct {
EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration.
@ref emuPowerConfig_DcdcToDvdd is currently the only supported mode. */
EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0/1 */
@@ -546,76 +597,75 @@
} EMU_DCDCInit_TypeDef;
/** Default DCDC initialization */
-#if defined( _EFM_DEVICE )
+#if defined(_EFM_DEVICE)
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
-#define EMU_DCDCINIT_DEFAULT \
-{ \
- emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \
- emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \
- 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \
- 5, /* Nominal EM0/1 load current of less than 5mA */ \
- 10, /* Nominal EM2/3/4 load current less than 10uA */ \
- 200, /* Maximum average current of 200mA
- (assume strong battery or other power source) */ \
- emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \
- emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \
- emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \
-}
+#define EMU_DCDCINIT_DEFAULT \
+ { \
+ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \
+ emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \
+ 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \
+ 5, /* Nominal EM0/1 load current of less than 5mA */ \
+ 10, /* Nominal EM2/3/4 load current less than 10uA */ \
+ 200, /* Maximum average current of 200mA
+ (assume strong battery or other power source) */ \
+ emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \
+ emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \
+ emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \
+ }
#else
-#define EMU_DCDCINIT_DEFAULT \
-{ \
- emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \
- emuDcdcMode_LowPower, /* Low-power mode in EM0 */ \
- 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \
- 5, /* Nominal EM0/1 load current of less than 5mA */ \
- 10, /* Nominal EM2/3/4 load current less than 10uA */ \
- 200, /* Maximum average current of 200mA
- (assume strong battery or other power source) */ \
- emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \
- emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \
- emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \
-}
+#define EMU_DCDCINIT_DEFAULT \
+ { \
+ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \
+ emuDcdcMode_LowPower, /* Low-power mode in EM0 */ \
+ 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \
+ 5, /* Nominal EM0/1 load current of less than 5mA */ \
+ 10, /* Nominal EM2/3/4 load current less than 10uA */ \
+ 200, /* Maximum average current of 200mA
+ (assume strong battery or other power source) */ \
+ emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply) */ \
+ emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \
+ emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \
+ }
#endif
#else /* EFR32 device */
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
-#define EMU_DCDCINIT_DEFAULT \
-{ \
- emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \
- emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \
- 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \
- 15, /* Nominal EM0/1 load current of less than 15mA */ \
- 10, /* Nominal EM2/3/4 load current less than 10uA */ \
- 200, /* Maximum average current of 200mA
- (assume strong battery or other power source) */ \
- emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \
- 160, /* Maximum reverse current of 160mA */ \
- emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \
-}
+#define EMU_DCDCINIT_DEFAULT \
+ { \
+ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \
+ emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \
+ 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \
+ 15, /* Nominal EM0/1 load current of less than 15mA */ \
+ 10, /* Nominal EM2/3/4 load current less than 10uA */ \
+ 200, /* Maximum average current of 200mA
+ (assume strong battery or other power source) */ \
+ emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \
+ 160, /* Maximum reverse current of 160mA */ \
+ emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \
+ }
#else
-#define EMU_DCDCINIT_DEFAULT \
-{ \
- emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \
- emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \
- 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \
- 15, /* Nominal EM0/1 load current of less than 15mA */ \
- 10, /* Nominal EM2/3/4 load current less than 10uA */ \
- 200, /* Maximum average current of 200mA
- (assume strong battery or other power source) */ \
- emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \
- 160, /* Maximum reverse current of 160mA */ \
- emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \
-}
+#define EMU_DCDCINIT_DEFAULT \
+ { \
+ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \
+ emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \
+ 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \
+ 15, /* Nominal EM0/1 load current of less than 15mA */ \
+ 10, /* Nominal EM2/3/4 load current less than 10uA */ \
+ 200, /* Maximum average current of 200mA
+ (assume strong battery or other power source) */ \
+ emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \
+ 160, /* Maximum reverse current of 160mA */ \
+ emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \
+ }
#endif
#endif
#endif
-#if defined( EMU_STATUS_VMONRDY )
+#if defined(EMU_STATUS_VMONRDY)
/** VMON initialization structure */
-typedef struct
-{
+typedef struct {
EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure */
- int threshold; /**< Trigger threshold (mV) */
+ int threshold; /**< Trigger threshold (mV). Supported range is 1620 mV to 3400 mV */
bool riseWakeup; /**< Wake up from EM4H on rising edge */
bool fallWakeup; /**< Wake up from EM4H on falling edge */
bool enable; /**< Enable VMON channel */
@@ -624,18 +674,17 @@
/** Default VMON initialization structure */
#define EMU_VMONINIT_DEFAULT \
-{ \
- emuVmonChannel_AVDD, /* AVDD VMON channel */ \
- 3200, /* 3.2 V threshold */ \
- false, /* Don't wake from EM4H on rising edge */ \
- false, /* Don't wake from EM4H on falling edge */ \
- true, /* Enable VMON channel */ \
- false /* Don't disable IO0 retention */ \
-}
+ { \
+ emuVmonChannel_AVDD, /* AVDD VMON channel */ \
+ 3200, /* 3.2 V threshold */ \
+ false, /* Don't wake from EM4H on rising edge */ \
+ false, /* Don't wake from EM4H on falling edge */ \
+ true, /* Enable VMON channel */ \
+ false /* Don't disable IO0 retention */ \
+ }
/** VMON Hysteresis initialization structure */
-typedef struct
-{
+typedef struct {
EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure */
int riseThreshold; /**< Rising threshold (mV) */
int fallThreshold; /**< Falling threshold (mV) */
@@ -646,32 +695,33 @@
/** Default VMON Hysteresis initialization structure */
#define EMU_VMONHYSTINIT_DEFAULT \
-{ \
- emuVmonChannel_AVDD, /* AVDD VMON channel */ \
- 3200, /* 3.2 V rise threshold */ \
- 3200, /* 3.2 V fall threshold */ \
- false, /* Don't wake from EM4H on rising edge */ \
- false, /* Don't wake from EM4H on falling edge */ \
- true /* Enable VMON channel */ \
-}
+ { \
+ emuVmonChannel_AVDD, /* AVDD VMON channel */ \
+ 3200, /* 3.2 V rise threshold */ \
+ 3200, /* 3.2 V fall threshold */ \
+ false, /* Don't wake from EM4H on rising edge */ \
+ false, /* Don't wake from EM4H on falling edge */ \
+ true /* Enable VMON channel */ \
+ }
#endif /* EMU_STATUS_VMONRDY */
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init);
#endif
void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init);
-#if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
+#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK)
void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init);
#endif
void EMU_EnterEM2(bool restore);
void EMU_EnterEM3(bool restore);
+void EMU_Save(void);
void EMU_Restore(void);
void EMU_EnterEM4(void);
-#if defined( _EMU_EM4CTRL_MASK )
+#if defined(_EMU_EM4CTRL_MASK)
void EMU_EnterEM4H(void);
void EMU_EnterEM4S(void);
#endif
@@ -681,16 +731,16 @@
void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable);
#endif
void EMU_UpdateOscConfig(void);
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait);
void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait);
#endif
-#if defined( BU_PRESENT )
+#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit);
void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value);
void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value);
#endif
-#if defined( _EMU_DCDCCTRL_MASK )
+#if defined(_EMU_DCDCCTRL_MASK)
bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit);
void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode);
void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet);
@@ -699,7 +749,7 @@
void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band);
bool EMU_DCDCPowerOff(void);
#endif
-#if defined( EMU_STATUS_VMONRDY )
+#if defined(EMU_STATUS_VMONRDY)
void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit);
void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit);
void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable);
@@ -717,19 +767,18 @@
__WFI();
}
-
-#if defined( _EMU_STATUS_VSCALE_MASK )
+#if defined(_EMU_STATUS_VSCALE_MASK)
/***************************************************************************//**
* @brief
* Wait for voltage scaling to complete
******************************************************************************/
__STATIC_INLINE void EMU_VScaleWait(void)
{
- while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT));
+ while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT)) ;
}
#endif
-#if defined( _EMU_STATUS_VSCALE_MASK )
+#if defined(_EMU_STATUS_VSCALE_MASK)
/***************************************************************************//**
* @brief
* Get current voltage scaling level
@@ -745,7 +794,7 @@
}
#endif
-#if defined( _EMU_STATUS_VMONRDY_MASK )
+#if defined(_EMU_STATUS_VMONRDY_MASK)
/***************************************************************************//**
* @brief
* Get the status of the voltage monitor (VMON).
@@ -760,7 +809,7 @@
}
#endif /* _EMU_STATUS_VMONRDY_MASK */
-#if defined( _EMU_IF_MASK )
+#if defined(_EMU_IF_MASK)
/***************************************************************************//**
* @brief
* Clear one or more pending EMU interrupts.
@@ -774,7 +823,6 @@
EMU->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more EMU interrupts.
@@ -788,14 +836,13 @@
EMU->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more EMU interrupts.
*
* @note
* Depending on the use, a pending interrupt may already be set prior to
- * enabling the interrupt. Consider using EMU_IntClear() prior to enabling
+ * enabling the interrupt. Consider using @ref EMU_IntClear() prior to enabling
* if such a pending interrupt should be ignored.
*
* @param[in] flags
@@ -807,7 +854,6 @@
EMU->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending EMU interrupt flags.
@@ -824,7 +870,6 @@
return EMU->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending EMU interrupt flags.
@@ -847,7 +892,6 @@
return EMU->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending EMU interrupts
@@ -862,8 +906,7 @@
}
#endif /* _EMU_IF_MASK */
-
-#if defined( _EMU_EM4CONF_LOCKCONF_MASK )
+#if defined(_EMU_EM4CONF_LOCKCONF_MASK)
/***************************************************************************//**
* @brief
* Enable or disable EM4 lock configuration
@@ -876,19 +919,19 @@
}
#endif
-#if defined( _EMU_STATUS_BURDY_MASK )
+#if defined(_EMU_STATUS_BURDY_MASK)
/***************************************************************************//**
* @brief
* Halts until backup power functionality is ready
******************************************************************************/
__STATIC_INLINE void EMU_BUReady(void)
{
- while(!(EMU->STATUS & EMU_STATUS_BURDY))
+ while (!(EMU->STATUS & EMU_STATUS_BURDY))
;
}
#endif
-#if defined( _EMU_ROUTE_BUVINPEN_MASK )
+#if defined(_EMU_ROUTE_BUVINPEN_MASK)
/***************************************************************************//**
* @brief
* Disable BU_VIN support
@@ -918,7 +961,6 @@
EMU->LOCK = EMU_LOCK_LOCKKEY_LOCK;
}
-
/***************************************************************************//**
* @brief
* Unlock the EMU so that writing to locked registers again is possible.
@@ -928,8 +970,7 @@
EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK;
}
-
-#if defined( _EMU_PWRLOCK_MASK )
+#if defined(_EMU_PWRLOCK_MASK)
/***************************************************************************//**
* @brief
* Lock the EMU regulator control registers in order to protect against
@@ -940,7 +981,6 @@
EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK;
}
-
/***************************************************************************//**
* @brief
* Unlock the EMU power control registers so that writing to
@@ -952,7 +992,6 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Block entering EM2 or higher number energy modes.
@@ -971,7 +1010,7 @@
BUS_RegBitWrite(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 0U);
}
-#if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
+#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK)
/***************************************************************************//**
* @brief
* When EM4 pin retention is set to emuPinRetentionLatch, then pins are retained
@@ -986,7 +1025,7 @@
}
#endif
-#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode);
#endif
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file
* @brief General Purpose Cyclic Redundancy Check (GPCRC) API.
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -99,8 +99,7 @@
******************************************************************************/
/** CRC initialization structure. */
-typedef struct
-{
+typedef struct {
/**
* CRC polynomial value. The GPCRC support either a fixed 32-bit polynomial
* or a user configurable 16 bit polynomial. The fixed 32-bit polynomial
@@ -159,16 +158,16 @@
} GPCRC_Init_TypeDef;
/** Default configuration for GPCRC_Init_TypeDef structure. */
-#define GPCRC_INIT_DEFAULT \
-{ \
- 0x04C11DB7UL, /* CRC32 Polynomial value. */ \
- 0x00000000UL, /* Initialization value. */ \
- false, /* Byte order is normal. */ \
- false, /* Bit order is not reversed on output. */ \
- false, /* Disable byte mode. */ \
- false, /* Disable automatic init on data read. */ \
- true, /* Enable GPCRC. */ \
-}
+#define GPCRC_INIT_DEFAULT \
+ { \
+ 0x04C11DB7UL, /* CRC32 Polynomial value. */ \
+ 0x00000000UL, /* Initialization value. */ \
+ false, /* Byte order is normal. */ \
+ false, /* Bit order is not reversed on output. */ \
+ false, /* Disable byte mode. */ \
+ false, /* Disable automatic init on data read. */ \
+ true, /* Enable GPCRC. */ \
+ }
/*******************************************************************************
****************************** PROTOTYPES *********************************
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_gpio.h
* @brief General Purpose IO (GPIO) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -30,7 +30,6 @@
*
******************************************************************************/
-
#ifndef EM_GPIO_H
#define EM_GPIO_H
@@ -60,7 +59,8 @@
******************************************************************************/
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-#if defined( _EFM32_TINY_FAMILY ) || defined( _EFM32_ZERO_FAMILY )
+#if defined(_SILICON_LABS_32B_SERIES_0) \
+ && defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY)
#define _GPIO_PORT_A_PIN_COUNT 14
#define _GPIO_PORT_B_PIN_COUNT 10
@@ -86,7 +86,7 @@
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
-#elif defined( _EFM32_HAPPY_FAMILY )
+#elif defined(_EFM32_HAPPY_FAMILY)
#define _GPIO_PORT_A_PIN_COUNT 6
#define _GPIO_PORT_B_PIN_COUNT 5
@@ -112,8 +112,8 @@
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
-#elif defined( _EFM32_GIANT_FAMILY ) \
- || defined( _EFM32_WONDER_FAMILY )
+#elif defined(_SILICON_LABS_32B_SERIES_0) \
+ && (defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY))
#define _GPIO_PORT_A_PIN_COUNT 16
#define _GPIO_PORT_B_PIN_COUNT 16
@@ -139,7 +139,7 @@
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
-#elif defined( _EFM32_GECKO_FAMILY )
+#elif defined(_EFM32_GECKO_FAMILY)
#define _GPIO_PORT_A_PIN_COUNT 16
#define _GPIO_PORT_B_PIN_COUNT 16
@@ -165,33 +165,7 @@
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
-#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) && defined( _EFR_DEVICE )
-
-#define _GPIO_PORT_A_PIN_COUNT 6
-#define _GPIO_PORT_B_PIN_COUNT 5
-#define _GPIO_PORT_C_PIN_COUNT 6
-#define _GPIO_PORT_D_PIN_COUNT 6
-#define _GPIO_PORT_E_PIN_COUNT 0
-#define _GPIO_PORT_F_PIN_COUNT 8
-#define _GPIO_PORT_G_PIN_COUNT 0
-#define _GPIO_PORT_H_PIN_COUNT 0
-#define _GPIO_PORT_I_PIN_COUNT 0
-#define _GPIO_PORT_J_PIN_COUNT 0
-#define _GPIO_PORT_K_PIN_COUNT 0
-
-#define _GPIO_PORT_A_PIN_MASK 0x003F
-#define _GPIO_PORT_B_PIN_MASK 0xF800
-#define _GPIO_PORT_C_PIN_MASK 0x0FC0
-#define _GPIO_PORT_D_PIN_MASK 0xFC00
-#define _GPIO_PORT_E_PIN_MASK 0x0000
-#define _GPIO_PORT_F_PIN_MASK 0x00FF
-#define _GPIO_PORT_G_PIN_MASK 0x0000
-#define _GPIO_PORT_H_PIN_MASK 0x0000
-#define _GPIO_PORT_I_PIN_MASK 0x0000
-#define _GPIO_PORT_J_PIN_MASK 0x0000
-#define _GPIO_PORT_K_PIN_MASK 0x0000
-
-#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) && defined( _EFM_DEVICE )
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE)
#define _GPIO_PORT_A_PIN_COUNT 6
#define _GPIO_PORT_B_PIN_COUNT 5
@@ -217,7 +191,33 @@
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
-#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_84 )
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFM_DEVICE)
+
+#define _GPIO_PORT_A_PIN_COUNT 6
+#define _GPIO_PORT_B_PIN_COUNT 5
+#define _GPIO_PORT_C_PIN_COUNT 6
+#define _GPIO_PORT_D_PIN_COUNT 7
+#define _GPIO_PORT_E_PIN_COUNT 0
+#define _GPIO_PORT_F_PIN_COUNT 8
+#define _GPIO_PORT_G_PIN_COUNT 0
+#define _GPIO_PORT_H_PIN_COUNT 0
+#define _GPIO_PORT_I_PIN_COUNT 0
+#define _GPIO_PORT_J_PIN_COUNT 0
+#define _GPIO_PORT_K_PIN_COUNT 0
+
+#define _GPIO_PORT_A_PIN_MASK 0x003F
+#define _GPIO_PORT_B_PIN_MASK 0xF800
+#define _GPIO_PORT_C_PIN_MASK 0x0FC0
+#define _GPIO_PORT_D_PIN_MASK 0xFE00
+#define _GPIO_PORT_E_PIN_MASK 0x0000
+#define _GPIO_PORT_F_PIN_MASK 0x00FF
+#define _GPIO_PORT_G_PIN_MASK 0x0000
+#define _GPIO_PORT_H_PIN_MASK 0x0000
+#define _GPIO_PORT_I_PIN_MASK 0x0000
+#define _GPIO_PORT_J_PIN_MASK 0x0000
+#define _GPIO_PORT_K_PIN_MASK 0x0000
+
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
#define _GPIO_PORT_A_PIN_COUNT 10
#define _GPIO_PORT_B_PIN_COUNT 10
@@ -243,7 +243,59 @@
#define _GPIO_PORT_J_PIN_MASK 0xC000
#define _GPIO_PORT_K_PIN_MASK 0x0007
-#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_89 )
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
+
+#define _GPIO_PORT_A_PIN_COUNT 6
+#define _GPIO_PORT_B_PIN_COUNT 5
+#define _GPIO_PORT_C_PIN_COUNT 6
+#define _GPIO_PORT_D_PIN_COUNT 6
+#define _GPIO_PORT_E_PIN_COUNT 0
+#define _GPIO_PORT_F_PIN_COUNT 8
+#define _GPIO_PORT_G_PIN_COUNT 0
+#define _GPIO_PORT_H_PIN_COUNT 0
+#define _GPIO_PORT_I_PIN_COUNT 0
+#define _GPIO_PORT_J_PIN_COUNT 0
+#define _GPIO_PORT_K_PIN_COUNT 0
+
+#define _GPIO_PORT_A_PIN_MASK 0x003F
+#define _GPIO_PORT_B_PIN_MASK 0xF800
+#define _GPIO_PORT_C_PIN_MASK 0x0FC0
+#define _GPIO_PORT_D_PIN_MASK 0xFC00
+#define _GPIO_PORT_E_PIN_MASK 0x0000
+#define _GPIO_PORT_F_PIN_MASK 0x00FF
+#define _GPIO_PORT_G_PIN_MASK 0x0000
+#define _GPIO_PORT_H_PIN_MASK 0x0000
+#define _GPIO_PORT_I_PIN_MASK 0x0000
+#define _GPIO_PORT_J_PIN_MASK 0x0000
+#define _GPIO_PORT_K_PIN_MASK 0x0000
+
+#elif defined(_SILICON_LABS_32B_SERIES_1) && defined(_EFM32_GIANT_FAMILY)
+
+#define _GPIO_PORT_A_PIN_COUNT 16
+#define _GPIO_PORT_B_PIN_COUNT 16
+#define _GPIO_PORT_C_PIN_COUNT 16
+#define _GPIO_PORT_D_PIN_COUNT 16
+#define _GPIO_PORT_E_PIN_COUNT 16
+#define _GPIO_PORT_F_PIN_COUNT 16
+#define _GPIO_PORT_G_PIN_COUNT 16
+#define _GPIO_PORT_H_PIN_COUNT 16
+#define _GPIO_PORT_I_PIN_COUNT 16
+#define _GPIO_PORT_J_PIN_COUNT 0
+#define _GPIO_PORT_K_PIN_COUNT 0
+
+#define _GPIO_PORT_A_PIN_MASK 0xFFFF
+#define _GPIO_PORT_B_PIN_MASK 0xFFFF
+#define _GPIO_PORT_C_PIN_MASK 0xFFFF
+#define _GPIO_PORT_D_PIN_MASK 0xFFFF
+#define _GPIO_PORT_E_PIN_MASK 0xFFFF
+#define _GPIO_PORT_F_PIN_MASK 0xFFFF
+#define _GPIO_PORT_G_PIN_MASK 0xFFFF
+#define _GPIO_PORT_H_PIN_MASK 0xFFFF
+#define _GPIO_PORT_I_PIN_MASK 0xFFFF
+#define _GPIO_PORT_J_PIN_MASK 0x0000
+#define _GPIO_PORT_K_PIN_MASK 0x0000
+
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
#define _GPIO_PORT_A_PIN_COUNT 6
#define _GPIO_PORT_B_PIN_COUNT 5
@@ -269,46 +321,72 @@
#define _GPIO_PORT_J_PIN_MASK 0x0000
#define _GPIO_PORT_K_PIN_MASK 0x0000
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
+
+#define _GPIO_PORT_A_PIN_COUNT 14
+#define _GPIO_PORT_B_PIN_COUNT 10
+#define _GPIO_PORT_C_PIN_COUNT 16
+#define _GPIO_PORT_D_PIN_COUNT 9
+#define _GPIO_PORT_E_PIN_COUNT 12
+#define _GPIO_PORT_F_PIN_COUNT 6
+#define _GPIO_PORT_G_PIN_COUNT 0
+#define _GPIO_PORT_H_PIN_COUNT 0
+#define _GPIO_PORT_I_PIN_COUNT 0
+#define _GPIO_PORT_J_PIN_COUNT 0
+#define _GPIO_PORT_K_PIN_COUNT 0
+
+#define _GPIO_PORT_A_PIN_MASK 0xF77F
+#define _GPIO_PORT_B_PIN_MASK 0x79F8
+#define _GPIO_PORT_C_PIN_MASK 0xFFFF
+#define _GPIO_PORT_D_PIN_MASK 0x01FF
+#define _GPIO_PORT_E_PIN_MASK 0xFFF0
+#define _GPIO_PORT_F_PIN_MASK 0x003F
+#define _GPIO_PORT_G_PIN_MASK 0x0000
+#define _GPIO_PORT_H_PIN_MASK 0x0000
+#define _GPIO_PORT_I_PIN_MASK 0x0000
+#define _GPIO_PORT_J_PIN_MASK 0x0000
+#define _GPIO_PORT_K_PIN_MASK 0x0000
+
#else
#warning "Port and pin masks are not defined for this family."
#endif
-#define _GPIO_PORT_SIZE(port) ( \
- (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \
- (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \
- (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \
- (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \
- (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \
- (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \
- (port) == 6 ? _GPIO_PORT_G_PIN_COUNT : \
- (port) == 7 ? _GPIO_PORT_H_PIN_COUNT : \
- (port) == 8 ? _GPIO_PORT_I_PIN_COUNT : \
- (port) == 9 ? _GPIO_PORT_J_PIN_COUNT : \
- (port) == 10 ? _GPIO_PORT_K_PIN_COUNT : \
- 0)
+#define _GPIO_PORT_SIZE(port) ( \
+ (port) == 0 ? _GPIO_PORT_A_PIN_COUNT \
+ : (port) == 1 ? _GPIO_PORT_B_PIN_COUNT \
+ : (port) == 2 ? _GPIO_PORT_C_PIN_COUNT \
+ : (port) == 3 ? _GPIO_PORT_D_PIN_COUNT \
+ : (port) == 4 ? _GPIO_PORT_E_PIN_COUNT \
+ : (port) == 5 ? _GPIO_PORT_F_PIN_COUNT \
+ : (port) == 6 ? _GPIO_PORT_G_PIN_COUNT \
+ : (port) == 7 ? _GPIO_PORT_H_PIN_COUNT \
+ : (port) == 8 ? _GPIO_PORT_I_PIN_COUNT \
+ : (port) == 9 ? _GPIO_PORT_J_PIN_COUNT \
+ : (port) == 10 ? _GPIO_PORT_K_PIN_COUNT \
+ : 0)
-#define _GPIO_PORT_MASK(port) ( \
- (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \
- (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \
- (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \
- (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \
- (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \
- (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \
- (port) == 6 ? _GPIO_PORT_G_PIN_MASK : \
- (port) == 7 ? _GPIO_PORT_H_PIN_MASK : \
- (port) == 8 ? _GPIO_PORT_I_PIN_MASK : \
- (port) == 9 ? _GPIO_PORT_J_PIN_MASK : \
- (port) == 10 ? _GPIO_PORT_K_PIN_MASK : \
- 0)
+#define _GPIO_PORT_MASK(port) ( \
+ (port) == 0 ? _GPIO_PORT_A_PIN_MASK \
+ : (port) == 1 ? _GPIO_PORT_B_PIN_MASK \
+ : (port) == 2 ? _GPIO_PORT_C_PIN_MASK \
+ : (port) == 3 ? _GPIO_PORT_D_PIN_MASK \
+ : (port) == 4 ? _GPIO_PORT_E_PIN_MASK \
+ : (port) == 5 ? _GPIO_PORT_F_PIN_MASK \
+ : (port) == 6 ? _GPIO_PORT_G_PIN_MASK \
+ : (port) == 7 ? _GPIO_PORT_H_PIN_MASK \
+ : (port) == 8 ? _GPIO_PORT_I_PIN_MASK \
+ : (port) == 9 ? _GPIO_PORT_J_PIN_MASK \
+ : (port) == 10 ? _GPIO_PORT_K_PIN_MASK \
+ : 0)
/** Validation of port and pin */
-#define GPIO_PORT_VALID(port) ( _GPIO_PORT_MASK(port) )
-#define GPIO_PORT_PIN_VALID(port, pin) ((( _GPIO_PORT_MASK(port)) >> (pin)) & 0x1 )
+#define GPIO_PORT_VALID(port) (_GPIO_PORT_MASK(port) )
+#define GPIO_PORT_PIN_VALID(port, pin) (((_GPIO_PORT_MASK(port)) >> (pin)) & 0x1)
#if defined(_GPIO_EXTIPINSELL_MASK)
/** Validation of interrupt number and pin */
-#define GPIO_INTNO_PIN_VALID(intNo, pin) \
- ((intNo & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) \
+#define GPIO_INTNO_PIN_VALID(intNo, pin) \
+ ((intNo & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) \
== (pin & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK))
#endif
@@ -316,17 +394,17 @@
#define GPIO_PIN_MAX 15
/** Highest GPIO port number */
-#if ( _GPIO_PORT_K_PIN_COUNT > 0 )
+#if (_GPIO_PORT_K_PIN_COUNT > 0)
#define GPIO_PORT_MAX 10
-#elif ( _GPIO_PORT_J_PIN_COUNT > 0 )
+#elif (_GPIO_PORT_J_PIN_COUNT > 0)
#define GPIO_PORT_MAX 9
-#elif ( _GPIO_PORT_I_PIN_COUNT > 0 )
+#elif (_GPIO_PORT_I_PIN_COUNT > 0)
#define GPIO_PORT_MAX 8
-#elif ( _GPIO_PORT_H_PIN_COUNT > 0 )
+#elif (_GPIO_PORT_H_PIN_COUNT > 0)
#define GPIO_PORT_MAX 7
-#elif ( _GPIO_PORT_G_PIN_COUNT > 0 )
+#elif (_GPIO_PORT_G_PIN_COUNT > 0)
#define GPIO_PORT_MAX 6
-#elif ( _GPIO_PORT_F_PIN_COUNT > 0 )
+#elif (_GPIO_PORT_F_PIN_COUNT > 0)
#define GPIO_PORT_MAX 5
#else
#error "Max GPIO port number is undefined for this part."
@@ -342,47 +420,45 @@
******************************************************************************/
/** GPIO ports ids. */
-typedef enum
-{
-#if ( _GPIO_PORT_A_PIN_COUNT > 0 )
+typedef enum {
+#if (_GPIO_PORT_A_PIN_COUNT > 0)
gpioPortA = 0,
#endif
-#if ( _GPIO_PORT_B_PIN_COUNT > 0 )
+#if (_GPIO_PORT_B_PIN_COUNT > 0)
gpioPortB = 1,
#endif
-#if ( _GPIO_PORT_C_PIN_COUNT > 0 )
+#if (_GPIO_PORT_C_PIN_COUNT > 0)
gpioPortC = 2,
#endif
-#if ( _GPIO_PORT_D_PIN_COUNT > 0 )
+#if (_GPIO_PORT_D_PIN_COUNT > 0)
gpioPortD = 3,
#endif
-#if ( _GPIO_PORT_E_PIN_COUNT > 0 )
+#if (_GPIO_PORT_E_PIN_COUNT > 0)
gpioPortE = 4,
#endif
-#if ( _GPIO_PORT_F_PIN_COUNT > 0 )
+#if (_GPIO_PORT_F_PIN_COUNT > 0)
gpioPortF = 5,
#endif
-#if ( _GPIO_PORT_G_PIN_COUNT > 0 )
+#if (_GPIO_PORT_G_PIN_COUNT > 0)
gpioPortG = 6,
#endif
-#if ( _GPIO_PORT_H_PIN_COUNT > 0 )
+#if (_GPIO_PORT_H_PIN_COUNT > 0)
gpioPortH = 7,
#endif
-#if ( _GPIO_PORT_I_PIN_COUNT > 0 )
+#if (_GPIO_PORT_I_PIN_COUNT > 0)
gpioPortI = 8,
#endif
-#if ( _GPIO_PORT_J_PIN_COUNT > 0 )
+#if (_GPIO_PORT_J_PIN_COUNT > 0)
gpioPortJ = 9,
#endif
-#if ( _GPIO_PORT_K_PIN_COUNT > 0 )
+#if (_GPIO_PORT_K_PIN_COUNT > 0)
gpioPortK = 10,
#endif
} GPIO_Port_TypeDef;
-#if defined( _GPIO_P_CTRL_DRIVEMODE_MASK )
+#if defined(_GPIO_P_CTRL_DRIVEMODE_MASK)
/** GPIO drive mode. */
-typedef enum
-{
+typedef enum {
/** Default 6mA */
gpioDriveModeStandard = GPIO_P_CTRL_DRIVEMODE_STANDARD,
/** 0.5 mA */
@@ -394,17 +470,16 @@
} GPIO_DriveMode_TypeDef;
#endif
-#if defined( _GPIO_P_CTRL_DRIVESTRENGTH_MASK ) && defined( _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK )
+#if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK) && defined(_GPIO_P_CTRL_DRIVESTRENGTHALT_MASK)
/** GPIO drive strength. */
-typedef enum
-{
+typedef enum {
/** GPIO weak 1mA and alternate function weak 1mA */
gpioDriveStrengthWeakAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK,
/** GPIO weak 1mA and alternate function strong 10mA */
gpioDriveStrengthWeakAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG,
- /** GPIO strong 10mA and alternate function weak 1mA */
+ /** GPIO strong 10mA and alternate function weak 1mA */
gpioDriveStrengthStrongAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK,
/** GPIO strong 10mA and alternate function strong 10mA */
@@ -418,8 +493,7 @@
/** Pin mode. For more details on each mode, please refer to the
* reference manual. */
-typedef enum
-{
+typedef enum {
/** Input disabled. Pullup if DOUT is set. */
gpioModeDisabled = _GPIO_P_MODEL_MODE0_DISABLED,
/** Input enabled. Filter if DOUT is set */
@@ -430,11 +504,11 @@
gpioModeInputPullFilter = _GPIO_P_MODEL_MODE0_INPUTPULLFILTER,
/** Push-pull output */
gpioModePushPull = _GPIO_P_MODEL_MODE0_PUSHPULL,
-#if defined( _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE )
+#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLDRIVE)
/** Push-pull output with drive-strength set by DRIVEMODE */
gpioModePushPullDrive = _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE,
#endif
-#if defined( _GPIO_P_MODEL_MODE0_PUSHPULLALT )
+#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLALT)
/** Push-pull using alternate control */
gpioModePushPullAlternate = _GPIO_P_MODEL_MODE0_PUSHPULLALT,
#endif
@@ -450,7 +524,7 @@
gpioModeWiredAndPullUp = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP,
/** Open-drain output with filter and pullup */
gpioModeWiredAndPullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER,
-#if defined( _GPIO_P_MODEL_MODE0_WIREDANDDRIVE )
+#if defined(_GPIO_P_MODEL_MODE0_WIREDANDDRIVE)
/** Open-drain output with drive-strength set by DRIVEMODE */
gpioModeWiredAndDrive = _GPIO_P_MODEL_MODE0_WIREDANDDRIVE,
/** Open-drain output with filter and drive-strength set by DRIVEMODE */
@@ -460,7 +534,7 @@
/** Open-drain output with filter, pullup and drive-strength set by DRIVEMODE */
gpioModeWiredAndDrivePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER
#endif
-#if defined( _GPIO_P_MODEL_MODE0_WIREDANDALT )
+#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALT)
/** Open-drain output using alternate control */
gpioModeWiredAndAlternate = _GPIO_P_MODEL_MODE0_WIREDANDALT,
/** Open-drain output using alternate control with filter */
@@ -492,9 +566,9 @@
******************************************************************************/
__STATIC_INLINE void GPIO_DbgSWDClkEnable(bool enable)
{
-#if defined( _GPIO_ROUTE_SWCLKPEN_MASK )
+#if defined(_GPIO_ROUTE_SWCLKPEN_MASK)
BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, enable);
-#elif defined( _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK )
+#elif defined(_GPIO_ROUTEPEN_SWCLKTCKPEN_MASK)
BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT, enable);
#else
#warning "ROUTE enable for SWCLK pin is not defined."
@@ -515,16 +589,16 @@
******************************************************************************/
__STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable)
{
-#if defined( _GPIO_ROUTE_SWDIOPEN_MASK )
+#if defined(_GPIO_ROUTE_SWDIOPEN_MASK)
BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, enable);
-#elif defined( _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK )
+#elif defined(_GPIO_ROUTEPEN_SWDIOTMSPEN_MASK)
BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT, enable);
#else
#warning "ROUTE enable for SWDIO pin is not defined."
#endif
}
-#if defined( _GPIO_ROUTE_SWOPEN_MASK ) || defined( _GPIO_ROUTEPEN_SWVPEN_MASK )
+#if defined(_GPIO_ROUTE_SWOPEN_MASK) || defined(_GPIO_ROUTEPEN_SWVPEN_MASK)
/***************************************************************************//**
* @brief
* Enable/Disable serial wire output pin.
@@ -532,7 +606,7 @@
* @note
* Enabling this pin is not sufficient to fully enable serial wire output
* which is also dependent on issues outside the GPIO module. Please refer to
- * DBG_SWOEnable().
+ * @ref DBG_SWOEnable().
*
* @param[in] enable
* @li false - disable serial wire viewer pin (default after reset).
@@ -540,9 +614,9 @@
******************************************************************************/
__STATIC_INLINE void GPIO_DbgSWOEnable(bool enable)
{
-#if defined( _GPIO_ROUTE_SWOPEN_MASK )
+#if defined(_GPIO_ROUTE_SWOPEN_MASK)
BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, enable);
-#elif defined( _GPIO_ROUTEPEN_SWVPEN_MASK )
+#elif defined(_GPIO_ROUTEPEN_SWVPEN_MASK)
BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWVPEN_SHIFT, enable);
#else
#warning "ROUTE enable for SWO/SWV pin is not defined."
@@ -554,11 +628,11 @@
void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode);
#endif
-#if defined( _GPIO_P_CTRL_DRIVESTRENGTH_MASK )
+#if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK)
void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, GPIO_DriveStrength_TypeDef strength);
#endif
-# if defined( _GPIO_EM4WUEN_MASK )
+# if defined(_GPIO_EM4WUEN_MASK)
/**************************************************************************//**
* @brief
* Disable GPIO pin wake-up from EM4.
@@ -575,11 +649,11 @@
}
#endif
-# if defined( _GPIO_EM4WUEN_MASK )
+# if defined(_GPIO_EM4WUEN_MASK)
void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask);
#endif
-#if defined( _GPIO_EM4WUCAUSE_MASK ) || defined( _GPIO_IF_EM4WU_MASK )
+#if defined(_GPIO_EM4WUCAUSE_MASK) || defined(_GPIO_IF_EM4WU_MASK)
/**************************************************************************//**
* @brief
* Check which GPIO pin(s) that caused a wake-up from EM4.
@@ -590,7 +664,7 @@
*****************************************************************************/
__STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void)
{
-#if defined( _GPIO_EM4WUCAUSE_MASK )
+#if defined(_GPIO_EM4WUCAUSE_MASK)
return GPIO->EM4WUCAUSE & _GPIO_EM4WUCAUSE_MASK;
#else
return GPIO->IF & _GPIO_IF_EM4WU_MASK;
@@ -598,14 +672,14 @@
}
#endif
-#if defined( GPIO_CTRL_EM4RET ) || defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
+#if defined(GPIO_CTRL_EM4RET) || defined(_EMU_EM4CTRL_EM4IORETMODE_MASK)
/**************************************************************************//**
* @brief
* Enable GPIO pin retention of output enable, output value, pull enable and
* pull direction in EM4.
*
* @note
- * For platform 2 parts, EMU_EM4Init() and EMU_UnlatchPinRetention() offers
+ * For platform 2 parts, @ref EMU_EM4Init() and @ref EMU_UnlatchPinRetention() offers
* more pin retention features. This function implements the EM4EXIT retention
* mode on platform 2.
*
@@ -615,18 +689,15 @@
*****************************************************************************/
__STATIC_INLINE void GPIO_EM4SetPinRetention(bool enable)
{
- if (enable)
- {
-#if defined( GPIO_CTRL_EM4RET )
+ if (enable) {
+#if defined(GPIO_CTRL_EM4RET)
GPIO->CTRL |= GPIO_CTRL_EM4RET;
#else
EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK)
| EMU_EM4CTRL_EM4IORETMODE_EM4EXIT;
#endif
- }
- else
- {
-#if defined( GPIO_CTRL_EM4RET )
+ } else {
+#if defined(GPIO_CTRL_EM4RET)
GPIO->CTRL &= ~GPIO_CTRL_EM4RET;
#else
EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK)
@@ -694,7 +765,7 @@
*
* @note
* Depending on the use, a pending interrupt may already be set prior to
- * enabling the interrupt. Consider using GPIO_IntClear() prior to enabling
+ * enabling the interrupt. Consider using @ref GPIO_IntClear() prior to enabling
* if such a pending interrupt should be ignored.
*
* @param[in] flags
@@ -811,10 +882,10 @@
__STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin)
{
EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
-#if defined( _GPIO_P_DOUTCLR_MASK )
+#if defined(_GPIO_P_DOUTCLR_MASK)
GPIO->P[port].DOUTCLR = 1 << pin;
#else
- BUS_RegBitWrite(&GPIO->P[port].DOUT, pin, 0);
+ BUS_RegMaskedClear(&GPIO->P[port].DOUT, 1 << pin);
#endif
}
@@ -856,10 +927,10 @@
__STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin)
{
EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
-#if defined( _GPIO_P_DOUTSET_MASK )
+#if defined(_GPIO_P_DOUTSET_MASK)
GPIO->P[port].DOUTSET = 1 << pin;
#else
- BUS_RegBitWrite(&GPIO->P[port].DOUT, pin, 1);
+ BUS_RegMaskedSet(&GPIO->P[port].DOUT, 1 << pin);
#endif
}
@@ -917,7 +988,7 @@
__STATIC_INLINE void GPIO_PortOutClear(GPIO_Port_TypeDef port, uint32_t pins)
{
EFM_ASSERT(GPIO_PORT_VALID(port));
-#if defined( _GPIO_P_DOUTCLR_MASK )
+#if defined(_GPIO_P_DOUTCLR_MASK)
GPIO->P[port].DOUTCLR = pins;
#else
BUS_RegMaskedClear(&GPIO->P[port].DOUT, pins);
@@ -959,7 +1030,7 @@
__STATIC_INLINE void GPIO_PortOutSet(GPIO_Port_TypeDef port, uint32_t pins)
{
EFM_ASSERT(GPIO_PORT_VALID(port));
-#if defined( _GPIO_P_DOUTSET_MASK )
+#if defined(_GPIO_P_DOUTSET_MASK)
GPIO->P[port].DOUTSET = pins;
#else
BUS_RegMaskedSet(&GPIO->P[port].DOUT, pins);
@@ -1067,7 +1138,7 @@
*
* @details
* If reconfiguring a GPIO interrupt that is already enabled, it is generally
- * recommended to disable it first, see GPIO_Disable().
+ * recommended to disable it first, see @ref GPIO_Disable().
*
* The actual GPIO interrupt handler must be in place before enabling the
* interrupt.
@@ -1099,7 +1170,7 @@
*
* @param[in] enable
* Set to true if interrupt shall be enabled after configuration completed,
- * false to leave disabled. See GPIO_IntDisable() and GPIO_IntEnable().
+ * false to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable().
******************************************************************************/
__STATIC_INLINE void GPIO_IntConfig(GPIO_Port_TypeDef port,
unsigned int pin,
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_i2c.h
* @brief Inter-intergrated circuit (I2C) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -68,15 +68,15 @@
* @note
* Due to chip characteristics, the max value is somewhat reduced.
*/
-#if defined(_SILICON_LABS_32B_SERIES_0) \
- && (defined(_EFM32_GECKO_FAMILY) \
- || defined(_EFM32_TINY_FAMILY) \
- || defined(_EFM32_ZERO_FAMILY) \
- || defined(_EFM32_HAPPY_FAMILY))
+#if defined(_SILICON_LABS_32B_SERIES_0) \
+ && (defined(_EFM32_GECKO_FAMILY) \
+ || defined(_EFM32_TINY_FAMILY) \
+ || defined(_EFM32_ZERO_FAMILY) \
+ || defined(_EFM32_HAPPY_FAMILY))
#define I2C_FREQ_STANDARD_MAX 93000
-#elif defined(_SILICON_LABS_32B_SERIES_0) \
- && (defined(_EFM32_GIANT_FAMILY) \
- || defined(_EFM32_WONDER_FAMILY))
+#elif defined(_SILICON_LABS_32B_SERIES_0) \
+ && (defined(_EFM32_GIANT_FAMILY) \
+ || defined(_EFM32_WONDER_FAMILY))
#define I2C_FREQ_STANDARD_MAX 92000
#elif defined(_SILICON_LABS_32B_SERIES_1)
// None of the chips on this platform has been characterized on this parameter.
@@ -98,7 +98,6 @@
*/
#define I2C_FREQ_FAST_MAX 392157
-
/**
* @brief
* Fast mode+ max frequency assuming using 11:6 ratio for Nlow:Nhigh.
@@ -111,7 +110,6 @@
*/
#define I2C_FREQ_FASTPLUS_MAX 987167
-
/**
* @brief
* Indicate plain write sequence: S+ADDR(W)+DATA0+P.
@@ -161,23 +159,19 @@
/** Use 10 bit address. */
#define I2C_FLAG_10BIT_ADDR 0x0010
-
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** Clock low to high ratio settings. */
-typedef enum
-{
+typedef enum {
i2cClockHLRStandard = _I2C_CTRL_CLHR_STANDARD, /**< Ratio is 4:4 */
i2cClockHLRAsymetric = _I2C_CTRL_CLHR_ASYMMETRIC, /**< Ratio is 6:3 */
i2cClockHLRFast = _I2C_CTRL_CLHR_FAST /**< Ratio is 11:3 */
} I2C_ClockHLR_TypeDef;
-
/** Return codes for single master mode transfer function. */
-typedef enum
-{
+typedef enum {
/* In progress code (>0) */
i2cTransferInProgress = 1, /**< Transfer in progress. */
@@ -192,14 +186,12 @@
i2cTransferSwFault = -5 /**< SW fault. */
} I2C_TransferReturn_TypeDef;
-
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** I2C initialization structure. */
-typedef struct
-{
+typedef struct {
/** Enable I2C peripheral when init completed. */
bool enable;
@@ -225,15 +217,14 @@
/** Suggested default config for I2C init structure. */
#define I2C_INIT_DEFAULT \
-{ \
- true, /* Enable when init done */ \
- true, /* Set to master mode */ \
- 0, /* Use currently configured reference clock */ \
- I2C_FREQ_STANDARD_MAX, /* Set to standard rate assuring being */ \
- /* within I2C spec */ \
- i2cClockHLRStandard /* Set to use 4:4 low/high duty cycle */ \
-}
-
+ { \
+ true, /* Enable when init done */ \
+ true, /* Set to master mode */ \
+ 0, /* Use currently configured reference clock */ \
+ I2C_FREQ_STANDARD_MAX, /* Set to standard rate assuring being */ \
+ /* within I2C spec */ \
+ i2cClockHLRStandard /* Set to use 4:4 low/high duty cycle */ \
+ }
/**
* @brief
@@ -249,8 +240,7 @@
* @li #I2C_FLAG_WRITE_WRITE - data written from buf[0].data and
* buf[1].data
*/
-typedef struct
-{
+typedef struct {
/**
* @brief
* Address to use after (repeated) start.
@@ -268,8 +258,7 @@
* Buffers used to hold data to send from or receive into depending
* on sequence type.
*/
- struct
- {
+ struct {
/** Buffer used for data to transmit/receive, must be @p len long. */
uint8_t *data;
@@ -284,7 +273,6 @@
} buf[2];
} I2C_TransferSeq_TypeDef;
-
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@@ -313,7 +301,6 @@
i2c->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more I2C interrupts.
@@ -330,7 +317,6 @@
i2c->IEN &= ~(flags);
}
-
/***************************************************************************//**
* @brief
* Enable one or more I2C interrupts.
@@ -352,7 +338,6 @@
i2c->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending I2C interrupt flags.
@@ -372,7 +357,6 @@
return i2c->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending I2C interrupt flags.
@@ -398,7 +382,6 @@
return i2c->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending I2C interrupts from SW.
@@ -439,7 +422,6 @@
return ((uint8_t)(i2c->SADDR));
}
-
/***************************************************************************//**
* @brief
* Set slave address to use for I2C peripheral (when operating in slave mode).
@@ -462,7 +444,6 @@
i2c->SADDR = (uint32_t)addr & 0xfe;
}
-
/***************************************************************************//**
* @brief
* Get slave address mask used for I2C peripheral (when operating in slave
@@ -491,7 +472,6 @@
return ((uint8_t)(i2c->SADDRMASK));
}
-
/***************************************************************************//**
* @brief
* Set slave address mask used for I2C peripheral (when operating in slave
@@ -520,7 +500,6 @@
i2c->SADDRMASK = (uint32_t)mask & 0xfe;
}
-
I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c);
I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c,
I2C_TransferSeq_TypeDef *seq);
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_idac.h
* @brief Current Digital to Analog Converter (IDAC) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -90,9 +90,8 @@
******************************************************************************/
/** Output mode. */
-typedef enum
-{
-#if defined( _IDAC_CTRL_OUTMODE_MASK )
+typedef enum {
+#if defined(_IDAC_CTRL_OUTMODE_MASK)
idacOutputPin = IDAC_CTRL_OUTMODE_PIN, /**< Output to IDAC OUT pin */
idacOutputADC = IDAC_CTRL_OUTMODE_ADC /**< Output to ADC */
#elif ( _IDAC_CTRL_APORTOUTSEL_MASK )
@@ -131,20 +130,18 @@
#endif
} IDAC_OutMode_TypeDef;
-
/** Selects which Peripheral Reflex System (PRS) signal to use when
PRS is set to control the IDAC output. */
-typedef enum
-{
+typedef enum {
idacPRSSELCh0 = IDAC_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
idacPRSSELCh1 = IDAC_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
idacPRSSELCh2 = IDAC_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
idacPRSSELCh3 = IDAC_CTRL_PRSSEL_PRSCH3, /**< PRS channel 3. */
-#if defined( IDAC_CTRL_PRSSEL_PRSCH4 )
+#if defined(IDAC_CTRL_PRSSEL_PRSCH4)
idacPRSSELCh4 = IDAC_CTRL_PRSSEL_PRSCH4, /**< PRS channel 4. */
idacPRSSELCh5 = IDAC_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */
#endif
-#if defined( IDAC_CTRL_PRSSEL_PRSCH6 )
+#if defined(IDAC_CTRL_PRSSEL_PRSCH6)
idacPRSSELCh6 = IDAC_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */
idacPRSSELCh7 = IDAC_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */
idacPRSSELCh8 = IDAC_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */
@@ -154,10 +151,8 @@
#endif
} IDAC_PRSSEL_TypeDef;
-
/** Selects which current range to use. */
-typedef enum
-{
+typedef enum {
idacCurrentRange0 = IDAC_CURPROG_RANGESEL_RANGE0, /**< current range 0. */
idacCurrentRange1 = IDAC_CURPROG_RANGESEL_RANGE1, /**< current range 1. */
idacCurrentRange2 = IDAC_CURPROG_RANGESEL_RANGE2, /**< current range 2. */
@@ -169,8 +164,7 @@
******************************************************************************/
/** IDAC init structure, common for both channels. */
-typedef struct
-{
+typedef struct {
/** Enable IDAC. */
bool enable;
@@ -192,36 +186,33 @@
/** Enable/disable current sink mode. */
bool sinkEnable;
-
} IDAC_Init_TypeDef;
/** Default config for IDAC init structure. */
-#if defined( _IDAC_CTRL_OUTMODE_MASK )
+#if defined(_IDAC_CTRL_OUTMODE_MASK)
#define IDAC_INIT_DEFAULT \
-{ \
- false, /**< Leave IDAC disabled when init done. */ \
- idacOutputPin, /**< Output to IDAC output pin. */ \
- false, /**< Disable PRS triggering. */ \
- idacPRSSELCh0, /**< Select PRS ch0 (if PRS triggering enabled). */ \
- false /**< Disable current sink mode. */ \
-}
-#elif ( _IDAC_CTRL_APORTOUTSEL_MASK )
+ { \
+ false, /**< Leave IDAC disabled when init done. */ \
+ idacOutputPin, /**< Output to IDAC output pin. */ \
+ false, /**< Disable PRS triggering. */ \
+ idacPRSSELCh0, /**< Select PRS ch0 (if PRS triggering enabled). */ \
+ false /**< Disable current sink mode. */ \
+ }
+#elif (_IDAC_CTRL_APORTOUTSEL_MASK)
#define IDAC_INIT_DEFAULT \
-{ \
- false, /**< Leave IDAC disabled when init done. */ \
- idacOutputAPORT1XCH0, /**< Output to APORT. */ \
- false, /**< Disable PRS triggering. */ \
- idacPRSSELCh0, /**< Select PRS ch0 (if PRS triggering enabled). */ \
- false /**< Disable current sink mode. */ \
-}
+ { \
+ false, /**< Leave IDAC disabled when init done. */ \
+ idacOutputAPORT1XCH0, /**< Output to APORT. */ \
+ false, /**< Disable PRS triggering. */ \
+ idacPRSSELCh0, /**< Select PRS ch0 (if PRS triggering enabled). */ \
+ false /**< Disable current sink mode. */ \
+ }
#endif
-
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
-
void IDAC_Init(IDAC_TypeDef *idac, const IDAC_Init_TypeDef *init);
void IDAC_Enable(IDAC_TypeDef *idac, bool enable);
void IDAC_Reset(IDAC_TypeDef *idac);
@@ -230,8 +221,7 @@
void IDAC_StepSet(IDAC_TypeDef *idac, const uint32_t step);
void IDAC_OutEnable(IDAC_TypeDef *idac, bool enable);
-
-#if defined( _IDAC_IEN_MASK )
+#if defined(_IDAC_IEN_MASK)
/***************************************************************************//**
* @brief
* Clear one or more pending IDAC interrupts.
@@ -248,7 +238,6 @@
idac->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more IDAC interrupts.
@@ -265,7 +254,6 @@
idac->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more IDAC interrupts.
@@ -287,7 +275,6 @@
idac->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending IDAC interrupt flags.
@@ -307,7 +294,6 @@
return idac->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending IDAC interrupt flags.
@@ -339,7 +325,6 @@
return idac->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending IDAC interrupts from SW.
@@ -357,7 +342,6 @@
}
#endif
-
/** @} (end addtogroup IDAC) */
/** @} (end addtogroup emlib) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h Thu Nov 23 11:57:25 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,132 +0,0 @@
-/***************************************************************************//**
- * @file em_int.h
- * @brief Interrupt enable/disable unit API
- * @version 5.1.2
- *******************************************************************************
- * @section License
- * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
- *******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
- * obligation to support this Software. Silicon Labs is providing the
- * Software "AS IS", with no express or implied warranties of any kind,
- * including, but not limited to, any implied warranties of merchantability
- * or fitness for any particular purpose or warranties against infringement
- * of any proprietary rights of a third party.
- *
- * Silicon Labs will not be liable for any consequential, incidental, or
- * special damages, or any other relief, or for any claim by any third party,
- * arising from your use of this Software.
- *
- ******************************************************************************/
-
-#ifndef EM_INT_H
-#define EM_INT_H
-
-#include "em_device.h"
-
-extern uint32_t INT_LockCnt;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-#ifndef UINT32_MAX
-#define UINT32_MAX ((uint32_t)(0xFFFFFFFF))
-#endif
-
-#warning "The INT module is deprecated and marked for removal in a later release. Please use the new CORE module instead. See \"Porting from em_int\" in the CORE documentation for instructions."
-
-/** @endcond */
-
-/***************************************************************************//**
- * @addtogroup emlib
- * @{
- ******************************************************************************/
-
-/***************************************************************************//**
- * @addtogroup INT
- * @{
- ******************************************************************************/
-
-/***************************************************************************//**
- * @brief
- * Disable interrupts.
- *
- * @deprecated
- * This function is deprecated and marked for removal in a later release.
- * Please use the new CORE module instead.
- *
- * @details
- * Disable interrupts and increment lock level counter.
- *
- * @return
- * The resulting interrupt disable nesting level.
- *
- ******************************************************************************/
-__STATIC_INLINE uint32_t INT_Disable(void)
-{
- __disable_irq();
- if (INT_LockCnt < UINT32_MAX)
- {
- INT_LockCnt++;
- }
-
- return INT_LockCnt;
-}
-
-/***************************************************************************//**
- * @brief
- * Enable interrupts.
- *
- * @deprecated
- * This function is deprecated and marked for removal in a later release.
- * Please use the new CORE module instead.
- *
- * @return
- * The resulting interrupt disable nesting level.
- *
- * @details
- * Decrement interrupt lock level counter and enable interrupts if counter
- * reached zero.
- *
- ******************************************************************************/
-__STATIC_INLINE uint32_t INT_Enable(void)
-{
- uint32_t retVal;
-
- if (INT_LockCnt > 0)
- {
- INT_LockCnt--;
- retVal = INT_LockCnt;
- if (retVal == 0)
- {
- __enable_irq();
- }
- return retVal;
- }
- else
- {
- return 0;
- }
-}
-
-/** @} (end addtogroup INT) */
-/** @} (end addtogroup emlib) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* EM_INT_H */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_lcd.h
* @brief Liquid Crystal Display (LCD) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -54,12 +54,18 @@
******************************************************************************/
/*******************************************************************************
+ ******************************** DEFINES **********************************
+ ******************************************************************************/
+
+#define LCD_DEFAULT_FRAME_RATE_DIV 4
+#define LCD_DEFAULT_CONTRAST 15
+
+/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** MUX setting */
-typedef enum
-{
+typedef enum {
/** Static (segments can be multiplexed with LCD_COM[0]) */
lcdMuxStatic = LCD_DISPCTRL_MUX_STATIC,
/** Duplex / 1/2 Duty cycle (segments can be multiplexed with LCD_COM[0:1]) */
@@ -73,12 +79,24 @@
lcdMuxSextaplex = LCD_DISPCTRL_MUXE_MUXE | LCD_DISPCTRL_MUX_DUPLEX,
/** Octaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */
lcdMuxOctaplex = LCD_DISPCTRL_MUXE_MUXE | LCD_DISPCTRL_MUX_QUADRUPLEX
+#elif defined(LCD_DISPCTRL_MUX_SEXTAPLEX)
+ /** Sextaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */
+ lcdMuxSextaplex = LCD_DISPCTRL_MUX_SEXTAPLEX,
+ /** Octaplex / 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */
+ lcdMuxOctaplex = LCD_DISPCTRL_MUX_OCTAPLEX,
#endif
} LCD_Mux_TypeDef;
+/** Wave type */
+typedef enum {
+ /** Low power optimized waveform output */
+ lcdWaveLowPower = LCD_DISPCTRL_WAVE_LOWPOWER,
+ /** Regular waveform output */
+ lcdWaveNormal = LCD_DISPCTRL_WAVE_NORMAL
+} LCD_Wave_TypeDef;
+
/** Bias setting */
-typedef enum
-{
+typedef enum {
/** Static (2 levels) */
lcdBiasStatic = LCD_DISPCTRL_BIAS_STATIC,
/** 1/2 Bias (3 levels) */
@@ -91,36 +109,29 @@
#endif
} LCD_Bias_TypeDef;
-/** Wave type */
-typedef enum
-{
- /** Low power optimized waveform output */
- lcdWaveLowPower = LCD_DISPCTRL_WAVE_LOWPOWER,
- /** Regular waveform output */
- lcdWaveNormal = LCD_DISPCTRL_WAVE_NORMAL
-} LCD_Wave_TypeDef;
-
+#if defined(_SILICON_LABS_32B_SERIES_0)
/** VLCD Voltage Source */
-typedef enum
-{
+typedef enum {
/** VLCD Powered by VDD */
lcdVLCDSelVDD = LCD_DISPCTRL_VLCDSEL_VDD,
/** VLCD Powered by external VDD / Voltage Boost */
lcdVLCDSelVExtBoost = LCD_DISPCTRL_VLCDSEL_VEXTBOOST
} LCD_VLCDSel_TypeDef;
+#endif
/** Contrast Configuration */
-typedef enum
-{
+#if defined(_SILICON_LABS_32B_SERIES_0)
+typedef enum {
/** Contrast is adjusted relative to VDD (VLCD) */
lcdConConfVLCD = LCD_DISPCTRL_CONCONF_VLCD,
/** Contrast is adjusted relative to Ground */
lcdConConfGND = LCD_DISPCTRL_CONCONF_GND
} LCD_ConConf_TypeDef;
+#endif
+#if defined(_SILICON_LABS_32B_SERIES_0)
/** Voltage Boost Level - Datasheets document setting for each part number */
-typedef enum
-{
+typedef enum {
lcdVBoostLevel0 = LCD_DISPCTRL_VBLEV_LEVEL0, /**< Voltage boost LEVEL0 */
lcdVBoostLevel1 = LCD_DISPCTRL_VBLEV_LEVEL1, /**< Voltage boost LEVEL1 */
lcdVBoostLevel2 = LCD_DISPCTRL_VBLEV_LEVEL2, /**< Voltage boost LEVEL2 */
@@ -130,10 +141,19 @@
lcdVBoostLevel6 = LCD_DISPCTRL_VBLEV_LEVEL6, /**< Voltage boost LEVEL6 */
lcdVBoostLevel7 = LCD_DISPCTRL_VBLEV_LEVEL7 /**< Voltage boost LEVEL7 */
} LCD_VBoostLevel_TypeDef;
+#endif
+
+#if defined(_SILICON_LABS_32B_SERIES_1)
+/** Mode */
+typedef enum {
+ lcdModeNoExtCap = LCD_DISPCTRL_MODE_NOEXTCAP, /**< No external capacitor */
+ lcdModeStepDown = LCD_DISPCTRL_MODE_STEPDOWN, /**< External cap with resistor string */
+ lcdModeCpIntOsc = LCD_DISPCTRL_MODE_CPINTOSC, /**< External cap and internal oscillator */
+} LCD_Mode_Typedef;
+#endif
/** Frame Counter Clock Prescaler, FC-CLK = FrameRate (Hz) / this factor */
-typedef enum
-{
+typedef enum {
/** Prescale Div 1 */
lcdFCPrescDiv1 = LCD_BACTRL_FCPRESC_DIV1,
/** Prescale Div 2 */
@@ -144,9 +164,9 @@
lcdFCPrescDiv8 = LCD_BACTRL_FCPRESC_DIV8
} LCD_FCPreScale_TypeDef;
+#if defined(_SILICON_LABS_32B_SERIES_0)
/** Segment selection */
-typedef enum
-{
+typedef enum {
/** Select segment lines 0 to 3 */
lcdSegment0_3 = (1 << 0),
/** Select segment lines 4 to 7 */
@@ -175,10 +195,10 @@
lcdSegmentAll = (0x03ff)
#endif
} LCD_SegmentRange_TypeDef;
+#endif
/** Update Data Control */
-typedef enum
-{
+typedef enum {
/** Regular update, data transfer done immediately */
lcdUpdateCtrlRegular = LCD_CTRL_UDCTRL_REGULAR,
/** Data transfer done at Frame Counter event */
@@ -188,8 +208,7 @@
} LCD_UpdateCtrl_TypeDef;
/** Animation Shift operation; none, left or right */
-typedef enum
-{
+typedef enum {
/** No shift */
lcdAnimShiftNone = _LCD_BACTRL_AREGASC_NOSHIFT,
/** Shift segment bits left */
@@ -199,22 +218,19 @@
} LCD_AnimShift_TypeDef;
/** Animation Logic Control, how AReg and BReg should be combined */
-typedef enum
-{
+typedef enum {
/** Use bitwise logic AND to mix animation register A (AREGA) and B (AREGB) */
lcdAnimLogicAnd = LCD_BACTRL_ALOGSEL_AND,
/** Use bitwise logic OR to mix animation register A (AREGA) and B (AREGB) */
lcdAnimLogicOr = LCD_BACTRL_ALOGSEL_OR
} LCD_AnimLogic_TypeDef;
-
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** LCD Animation Configuration */
-typedef struct
-{
+typedef struct {
/** Enable Animation at end of initialization */
bool enable;
/** Initial Animation Register A Value */
@@ -234,8 +250,7 @@
} LCD_AnimInit_TypeDef;
/** LCD Frame Control Initialization */
-typedef struct
-{
+typedef struct {
/** Enable at end */
bool enable;
/** Frame Counter top value */
@@ -245,8 +260,7 @@
} LCD_FrameCountInit_TypeDef;
/** LCD Controller Initialization structure */
-typedef struct
-{
+typedef struct {
/** Enable controller at end of initialization */
bool enable;
/** Mux configuration */
@@ -255,46 +269,81 @@
LCD_Bias_TypeDef bias;
/** Wave configuration */
LCD_Wave_TypeDef wave;
+#if defined(_SILICON_LABS_32B_SERIES_0)
/** VLCD Select */
LCD_VLCDSel_TypeDef vlcd;
/** Contrast Configuration */
LCD_ConConf_TypeDef contrast;
+#endif
+#if defined(_SILICON_LABS_32B_SERIES_1)
+ /** Mode */
+ LCD_Mode_Typedef mode;
+ uint8_t chgrDst;
+ uint8_t frameRateDivider;
+ int contrastLevel;
+#endif
} LCD_Init_TypeDef;
/** Default config for LCD init structure, enables 160 segments */
+#if defined(_SILICON_LABS_32B_SERIES_0)
#define LCD_INIT_DEFAULT \
-{ \
- true, \
- lcdMuxQuadruplex, \
- lcdBiasOneThird, \
- lcdWaveLowPower, \
- lcdVLCDSelVDD, \
- lcdConConfVLCD \
-}
+ { \
+ true, \
+ lcdMuxQuadruplex, \
+ lcdBiasOneThird, \
+ lcdWaveLowPower, \
+ lcdVLCDSelVDD, \
+ lcdConConfVLCD, \
+ }
+#endif
+
+#if defined(_SILICON_LABS_32B_SERIES_1)
+#define LCD_INIT_DEFAULT \
+ { \
+ true, \
+ lcdMuxQuadruplex, \
+ lcdBiasOneThird, \
+ lcdWaveLowPower, \
+ lcdModeNoExtCap, \
+ 0, \
+ LCD_DEFAULT_FRAME_RATE_DIV, \
+ LCD_DEFAULT_CONTRAST \
+ }
+#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
void LCD_Init(const LCD_Init_TypeDef *lcdInit);
+#if defined(_SILICON_LABS_32B_SERIES_0)
void LCD_VLCDSelect(LCD_VLCDSel_TypeDef vlcd);
+#endif
void LCD_UpdateCtrl(LCD_UpdateCtrl_TypeDef ud);
void LCD_FrameCountInit(const LCD_FrameCountInit_TypeDef *fcInit);
void LCD_AnimInit(const LCD_AnimInit_TypeDef *animInit);
+#if defined(_SILICON_LABS_32B_SERIES_0)
void LCD_SegmentRangeEnable(LCD_SegmentRange_TypeDef segment, bool enable);
+#endif
void LCD_SegmentSet(int com, int bit, bool enable);
void LCD_SegmentSetLow(int com, uint32_t mask, uint32_t bits);
#if defined(_LCD_SEGD0H_MASK)
void LCD_SegmentSetHigh(int com, uint32_t mask, uint32_t bits);
#endif
void LCD_ContrastSet(int level);
+void LCD_BiasSet(LCD_Bias_TypeDef bias);
+#if defined(_SILICON_LABS_32B_SERIES_0)
void LCD_VBoostSet(LCD_VBoostLevel_TypeDef vboost);
-
+#endif
#if defined(LCD_CTRL_DSC)
void LCD_BiasSegmentSet(int segment, int biasLevel);
void LCD_BiasComSet(int com, int biasLevel);
#endif
+#if defined(_SILICON_LABS_32B_SERIES_1)
+void LCD_ModeSet(LCD_Mode_Typedef mode);
+void LCD_ChargeRedistributionCyclesSet(uint8_t cycles);
+#endif
/***************************************************************************//**
* @brief
@@ -307,17 +356,13 @@
******************************************************************************/
__STATIC_INLINE void LCD_Enable(bool enable)
{
- if (enable)
- {
+ if (enable) {
LCD->CTRL |= LCD_CTRL_EN;
- }
- else
- {
+ } else {
LCD->CTRL &= ~LCD_CTRL_EN;
}
}
-
/***************************************************************************//**
* @brief
* Enables or disables LCD Animation feature
@@ -327,17 +372,13 @@
******************************************************************************/
__STATIC_INLINE void LCD_AnimEnable(bool enable)
{
- if (enable)
- {
+ if (enable) {
LCD->BACTRL |= LCD_BACTRL_AEN;
- }
- else
- {
+ } else {
LCD->BACTRL &= ~LCD_BACTRL_AEN;
}
}
-
/***************************************************************************//**
* @brief
* Enables or disables LCD blink
@@ -347,17 +388,13 @@
******************************************************************************/
__STATIC_INLINE void LCD_BlinkEnable(bool enable)
{
- if (enable)
- {
+ if (enable) {
LCD->BACTRL |= LCD_BACTRL_BLINKEN;
- }
- else
- {
+ } else {
LCD->BACTRL &= ~LCD_BACTRL_BLINKEN;
}
}
-
/***************************************************************************//**
* @brief
* Disables all segments, while keeping segment state
@@ -367,17 +404,13 @@
******************************************************************************/
__STATIC_INLINE void LCD_BlankEnable(bool enable)
{
- if (enable)
- {
+ if (enable) {
LCD->BACTRL |= LCD_BACTRL_BLANK;
- }
- else
- {
+ } else {
LCD->BACTRL &= ~LCD_BACTRL_BLANK;
}
}
-
/***************************************************************************//**
* @brief
* Enables or disables LCD Frame Control
@@ -387,17 +420,13 @@
******************************************************************************/
__STATIC_INLINE void LCD_FrameCountEnable(bool enable)
{
- if (enable)
- {
+ if (enable) {
LCD->BACTRL |= LCD_BACTRL_FCEN;
- }
- else
- {
+ } else {
LCD->BACTRL &= ~LCD_BACTRL_FCEN;
}
}
-
/***************************************************************************//**
* @brief
* Returns current animation state
@@ -410,7 +439,6 @@
return (int)(LCD->STATUS & _LCD_STATUS_ASTATE_MASK) >> _LCD_STATUS_ASTATE_SHIFT;
}
-
/***************************************************************************//**
* @brief
* Returns current blink state
@@ -423,7 +451,6 @@
return (int)(LCD->STATUS & _LCD_STATUS_BLINK_MASK) >> _LCD_STATUS_BLINK_SHIFT;
}
-
/***************************************************************************//**
* @brief
* When set, LCD registers will not be updated until cleared,
@@ -434,17 +461,13 @@
******************************************************************************/
__STATIC_INLINE void LCD_FreezeEnable(bool enable)
{
- if (enable)
- {
+ if (enable) {
LCD->FREEZE = LCD_FREEZE_REGFREEZE_FREEZE;
- }
- else
- {
+ } else {
LCD->FREEZE = LCD_FREEZE_REGFREEZE_UPDATE;
}
}
-
/***************************************************************************//**
* @brief
* Returns SYNCBUSY bits, indicating which registers have pending updates
@@ -457,7 +480,6 @@
return LCD->SYNCBUSY;
}
-
/***************************************************************************//**
* @brief
* Polls LCD SYNCBUSY flags, until flag has been cleared
@@ -471,7 +493,6 @@
;
}
-
/***************************************************************************//**
* @brief
* Get pending LCD interrupt flags
@@ -485,7 +506,6 @@
return LCD->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending LCD interrupt flags.
@@ -516,7 +536,6 @@
return LCD->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending LCD interrupts from SW.
@@ -531,7 +550,6 @@
LCD->IFS = flags;
}
-
/***************************************************************************//**
* @brief
* Enable LCD interrupts
@@ -546,7 +564,6 @@
LCD->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Disable LCD interrupts
@@ -561,7 +578,6 @@
LCD->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Clear one or more interrupt flags
@@ -576,7 +592,6 @@
LCD->IFC = flags;
}
-
#if defined(LCD_CTRL_DSC)
/***************************************************************************//**
* @brief
@@ -589,12 +604,9 @@
******************************************************************************/
__STATIC_INLINE void LCD_DSCEnable(bool enable)
{
- if (enable)
- {
+ if (enable) {
LCD->CTRL |= LCD_CTRL_DSC;
- }
- else
- {
+ } else {
LCD->CTRL &= ~LCD_CTRL_DSC;
}
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_ldma.h
* @brief Direct memory access (LDMA) API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -35,7 +35,7 @@
#include "em_device.h"
-#if defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
+#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1)
#include <stdbool.h>
@@ -43,7 +43,6 @@
extern "C" {
#endif
-
/***************************************************************************//**
* @addtogroup emlib
* @{
@@ -132,8 +131,7 @@
* This value controls the number of unit data transfers per arbitration
* cycle, providing a means to balance DMA channels' load on the controller.
*/
-typedef enum
-{
+typedef enum {
ldmaCtrlBlockSizeUnit1 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1, /**< One transfer per arbitration. */
ldmaCtrlBlockSizeUnit2 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT2, /**< Two transfers per arbitration. */
ldmaCtrlBlockSizeUnit3 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT3, /**< Three transfers per arbitration. */
@@ -151,23 +149,20 @@
} LDMA_CtrlBlockSize_t;
/** DMA structure type. */
-typedef enum
-{
+typedef enum {
ldmaCtrlStructTypeXfer = _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER, /**< TRANSFER transfer type. */
ldmaCtrlStructTypeSync = _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE, /**< SYNCHRONIZE transfer type. */
ldmaCtrlStructTypeWrite = _LDMA_CH_CTRL_STRUCTTYPE_WRITE /**< WRITE transfer type. */
} LDMA_CtrlStructType_t;
/** DMA transfer block or cycle selector. */
-typedef enum
-{
+typedef enum {
ldmaCtrlReqModeBlock = _LDMA_CH_CTRL_REQMODE_BLOCK, /**< Each DMA request trigger transfer of one block. */
ldmaCtrlReqModeAll = _LDMA_CH_CTRL_REQMODE_ALL /**< A DMA request trigger transfer of a complete cycle. */
} LDMA_CtrlReqMode_t;
/** Source address increment unit size. */
-typedef enum
-{
+typedef enum {
ldmaCtrlSrcIncOne = _LDMA_CH_CTRL_SRCINC_ONE, /**< Increment source address by one unit data size. */
ldmaCtrlSrcIncTwo = _LDMA_CH_CTRL_SRCINC_TWO, /**< Increment source address by two unit data sizes. */
ldmaCtrlSrcIncFour = _LDMA_CH_CTRL_SRCINC_FOUR, /**< Increment source address by four unit data sizes. */
@@ -175,16 +170,14 @@
} LDMA_CtrlSrcInc_t;
/** DMA transfer unit size. */
-typedef enum
-{
+typedef enum {
ldmaCtrlSizeByte = _LDMA_CH_CTRL_SIZE_BYTE, /**< Each unit transfer is a byte. */
ldmaCtrlSizeHalf = _LDMA_CH_CTRL_SIZE_HALFWORD, /**< Each unit transfer is a half-word. */
ldmaCtrlSizeWord = _LDMA_CH_CTRL_SIZE_WORD /**< Each unit transfer is a word. */
} LDMA_CtrlSize_t;
/** Destination address increment unit size. */
-typedef enum
-{
+typedef enum {
ldmaCtrlDstIncOne = _LDMA_CH_CTRL_DSTINC_ONE, /**< Increment destination address by one unit data size. */
ldmaCtrlDstIncTwo = _LDMA_CH_CTRL_DSTINC_TWO, /**< Increment destination address by two unit data sizes. */
ldmaCtrlDstIncFour = _LDMA_CH_CTRL_DSTINC_FOUR, /**< Increment destination address by four unit data sizes. */
@@ -192,29 +185,25 @@
} LDMA_CtrlDstInc_t;
/** Source addressing mode. */
-typedef enum
-{
+typedef enum {
ldmaCtrlSrcAddrModeAbs = _LDMA_CH_CTRL_SRCMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */
ldmaCtrlSrcAddrModeRel = _LDMA_CH_CTRL_SRCMODE_RELATIVE /**< Address fetched from a linked structure is relative. */
} LDMA_CtrlSrcAddrMode_t;
/** Destination addressing mode. */
-typedef enum
-{
+typedef enum {
ldmaCtrlDstAddrModeAbs = _LDMA_CH_CTRL_DSTMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */
ldmaCtrlDstAddrModeRel = _LDMA_CH_CTRL_DSTMODE_RELATIVE /**< Address fetched from a linked structure is relative. */
} LDMA_CtrlDstAddrMode_t;
/** DMA linkload address mode. */
-typedef enum
-{
+typedef enum {
ldmaLinkModeAbs = _LDMA_CH_LINK_LINKMODE_ABSOLUTE, /**< Link address is an absolute address value. */
ldmaLinkModeRel = _LDMA_CH_LINK_LINKMODE_RELATIVE /**< Link address is a two's complement releative address. */
} LDMA_LinkMode_t;
/** Insert extra arbitration slots to increase channel arbitration priority. */
-typedef enum
-{
+typedef enum {
ldmaCfgArbSlotsAs1 = _LDMA_CH_CFG_ARBSLOTS_ONE, /**< One arbitration slot selected. */
ldmaCfgArbSlotsAs2 = _LDMA_CH_CFG_ARBSLOTS_TWO, /**< Two arbitration slots selected. */
ldmaCfgArbSlotsAs4 = _LDMA_CH_CFG_ARBSLOTS_FOUR, /**< Four arbitration slots selected. */
@@ -222,22 +211,19 @@
} LDMA_CfgArbSlots_t;
/** Source address increment sign. */
-typedef enum
-{
+typedef enum {
ldmaCfgSrcIncSignPos = _LDMA_CH_CFG_SRCINCSIGN_POSITIVE, /**< Increment source address. */
ldmaCfgSrcIncSignNeg = _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE /**< Decrement source address. */
} LDMA_CfgSrcIncSign_t;
/** Destination address increment sign. */
-typedef enum
-{
+typedef enum {
ldmaCfgDstIncSignPos = _LDMA_CH_CFG_DSTINCSIGN_POSITIVE, /**< Increment destination address. */
ldmaCfgDstIncSignNeg = _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE /**< Decrement destination address. */
} LDMA_CfgDstIncSign_t;
/** Peripherals that can trigger LDMA transfers. */
-typedef enum
-{
+typedef enum {
ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering.
#if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN)
ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SCAN.
@@ -245,19 +231,25 @@
#if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE)
ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SINGLE.
#endif
- #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD )
+ #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SCAN)
+ ldmaPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trig on ADC1_SCAN.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE)
+ ldmaPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trig on ADC1_SINGLE.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD)
ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0RD.
#endif
- #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR )
+ #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR)
ldmaPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0WR.
#endif
- #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR )
+ #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR)
ldmaPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0XWR.
#endif
- #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD )
+ #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD)
ldmaPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1RD.
#endif
- #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR )
+ #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR)
ldmaPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1WR.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD)
@@ -296,6 +288,24 @@
#if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA)
ldmaPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_DATA.
#endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY)
+ ldmaPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXL0EMPTY.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY)
+ ldmaPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXL1EMPTY.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL)
+ ldmaPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXLFULL.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY)
+ ldmaPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_DDEMPTY.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_EBIVSYNC)
+ ldmaPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_VSYNC.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_EBIHSYNC)
+ ldmaPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_HSYNC.
+ #endif
#if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV)
ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_RXDATAV.
#endif
@@ -308,6 +318,12 @@
#if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL)
ldmaPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_TXBL.
#endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV)
+ ldmaPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trig on I2C2_RXDATAV.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2TXBL)
+ ldmaPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trig on I2C2_TXBL.
+ #endif
#if defined(LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV)
ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trig on LESENSE_BUFDATAV.
#endif
@@ -320,6 +336,15 @@
#if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY)
ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXEMPTY.
#endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV)
+ ldmaPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_RXDATAV.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL)
+ ldmaPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_TXBL.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY)
+ ldmaPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_TXEMPTY.
+ #endif
#if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA)
ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trig on MSC_WDATA.
#endif
@@ -356,6 +381,84 @@
#if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF)
ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_UFOF.
#endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC0)
+ ldmaPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC0.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC1)
+ ldmaPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC1.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC2)
+ ldmaPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC2.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF)
+ ldmaPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_UFOF.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC0)
+ ldmaPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC0.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC1)
+ ldmaPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC1.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC2)
+ ldmaPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC2.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF)
+ ldmaPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_UFOF.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC0)
+ ldmaPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC0.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC1)
+ ldmaPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC1.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC2)
+ ldmaPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC2.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF)
+ ldmaPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_UFOF.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC0)
+ ldmaPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC0.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC1)
+ ldmaPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC1.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC2)
+ ldmaPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC2.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF)
+ ldmaPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_UFOF.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC0)
+ ldmaPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC0.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC1)
+ ldmaPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC1.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC2)
+ ldmaPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC2.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF)
+ ldmaPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_UFOF.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV)
+ ldmaPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_RXDATAV.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXBL)
+ ldmaPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_TXBL.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY)
+ ldmaPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_TXEMPTY.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV)
+ ldmaPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_RXDATAV.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXBL)
+ ldmaPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_TXBL.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY)
+ ldmaPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_TXEMPTY.
+ #endif
#if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV)
ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_RXDATAV.
#endif
@@ -404,6 +507,30 @@
#if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY)
ldmaPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXEMPTY.
#endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV)
+ ldmaPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_RXDATAV.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT)
+ ldmaPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_RXDATAVRIGHT.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBL)
+ ldmaPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXBL.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT)
+ ldmaPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXBLRIGHT.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY)
+ ldmaPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXEMPTY.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV)
+ ldmaPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_RXDATAV.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBL)
+ ldmaPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXBL.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY)
+ ldmaPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXEMPTY.
+ #endif
#if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0)
ldmaPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH0.
#endif
@@ -435,11 +562,34 @@
ldmaPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC3.
#endif
#if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF)
- ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1 ///< Trig on WTIMER1_UFOF.
+ ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_UFOF.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0)
+ ldmaPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC0.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1)
+ ldmaPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC1.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2)
+ ldmaPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC2.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF)
+ ldmaPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_UFOF.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0)
+ ldmaPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC0.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1)
+ ldmaPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC1.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2)
+ ldmaPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC2.
+ #endif
+ #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF)
+ ldmaPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_UFOF.
#endif
} LDMA_PeripheralSignal_t;
-
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
@@ -453,14 +603,12 @@
* given DMA channel. The three descriptor types are XFER, SYNC and WRI.
* Refer to the reference manual for further information.
*/
-typedef union
-{
+typedef union {
/**
* TRANSFER DMA descriptor, this is the only descriptor type which can be
* used to start a DMA transfer.
*/
- struct
- {
+ struct {
uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */
uint32_t reserved0 : 1;
uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
@@ -474,8 +622,8 @@
uint32_t srcInc : 2; /**< Source address increment unit size. */
uint32_t size : 2; /**< DMA transfer unit size. */
uint32_t dstInc : 2; /**< Destination address increment unit size. */
- uint32_t srcAddrMode: 1; /**< Source addressing mode. */
- uint32_t dstAddrMode: 1; /**< Destination addressing mode. */
+ uint32_t srcAddrMode : 1; /**< Source addressing mode. */
+ uint32_t dstAddrMode : 1; /**< Destination addressing mode. */
uint32_t srcAddr; /**< DMA source address. */
uint32_t dstAddr; /**< DMA destination address. */
@@ -486,10 +634,9 @@
} xfer;
/** SYNCHRONIZE DMA descriptor, used for intra channel transfer
- * syncronization.
- */
- struct
- {
+ * syncronization.
+ */
+ struct {
uint32_t structType : 2; /**< Set to 1 to select SYNC descriptor type. */
uint32_t reserved0 : 1;
uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
@@ -503,8 +650,8 @@
uint32_t srcInc : 2; /**< Source address increment unit size. */
uint32_t size : 2; /**< DMA transfer unit size. */
uint32_t dstInc : 2; /**< Destination address increment unit size. */
- uint32_t srcAddrMode: 1; /**< Source addressing mode. */
- uint32_t dstAddrMode: 1; /**< Destination addressing mode. */
+ uint32_t srcAddrMode : 1; /**< Source addressing mode. */
+ uint32_t dstAddrMode : 1; /**< Destination addressing mode. */
uint32_t syncSet : 8; /**< Set bits in LDMA_CTRL.SYNCTRIG register. */
uint32_t syncClr : 8; /**< Clear bits in LDMA_CTRL.SYNCTRIG register*/
@@ -519,8 +666,7 @@
} sync;
/** WRITE DMA descriptor, used for write immediate operations. */
- struct
- {
+ struct {
uint32_t structType : 2; /**< Set to 2 to select WRITE descriptor type.*/
uint32_t reserved0 : 1;
uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
@@ -534,8 +680,8 @@
uint32_t srcInc : 2; /**< Source address increment unit size. */
uint32_t size : 2; /**< DMA transfer unit size. */
uint32_t dstInc : 2; /**< Destination address increment unit size. */
- uint32_t srcAddrMode: 1; /**< Source addressing mode. */
- uint32_t dstAddrMode: 1; /**< Destination addressing mode. */
+ uint32_t srcAddrMode : 1; /**< Source addressing mode. */
+ uint32_t dstAddrMode : 1; /**< Destination addressing mode. */
uint32_t immVal; /**< Data to be written at dstAddr. */
uint32_t dstAddr; /**< DMA write destination address. */
@@ -547,8 +693,7 @@
} LDMA_Descriptor_t;
/** @brief LDMA initialization configuration structure. */
-typedef struct
-{
+typedef struct {
uint8_t ldmaInitCtrlNumFixed; /**< Arbitration mode separator.*/
uint8_t ldmaInitCtrlSyncPrsClrEn; /**< PRS Synctrig clear enable. */
uint8_t ldmaInitCtrlSyncPrsSetEn; /**< PRS Synctrig set enable. */
@@ -561,8 +706,7 @@
* @details
* This struct configures all aspects of a DMA transfer.
*/
-typedef struct
-{
+typedef struct {
uint32_t ldmaReqSel; /**< Selects DMA trigger source. */
uint8_t ldmaCtrlSyncPrsClrOff; /**< PRS Synctrig clear enables to clear. */
uint8_t ldmaCtrlSyncPrsClrOn; /**< PRS Synctrig clear enables to set. */
@@ -576,65 +720,63 @@
uint8_t ldmaLoopCnt; /**< Counter for looped transfers. */
} LDMA_TransferCfg_t;
-
/*******************************************************************************
************************** STRUCT INITIALIZERS ****************************
******************************************************************************/
-
/** @brief Default DMA initialization structure. */
-#define LDMA_INIT_DEFAULT \
-{ \
- .ldmaInitCtrlNumFixed = _LDMA_CTRL_NUMFIXED_DEFAULT, /* Fixed priority arbitration. */ \
- .ldmaInitCtrlSyncPrsClrEn = 0, /* No PRS Synctrig clear enable*/ \
- .ldmaInitCtrlSyncPrsSetEn = 0, /* No PRS Synctrig set enable. */ \
- .ldmaInitIrqPriority = 3 /* IRQ priority level 3. */ \
-}
+#define LDMA_INIT_DEFAULT \
+ { \
+ .ldmaInitCtrlNumFixed = _LDMA_CTRL_NUMFIXED_DEFAULT,/* Fixed priority arbitration.*/ \
+ .ldmaInitCtrlSyncPrsClrEn = 0, /* No PRS Synctrig clear enable*/ \
+ .ldmaInitCtrlSyncPrsSetEn = 0, /* No PRS Synctrig set enable. */ \
+ .ldmaInitIrqPriority = 3 /* IRQ priority level 3. */ \
+ }
/**
* @brief
* Generic DMA transfer configuration for memory to memory transfers.
*/
-#define LDMA_TRANSFER_CFG_MEMORY() \
-{ \
- 0, 0, 0, 0, 0, \
- false, false, ldmaCfgArbSlotsAs1, \
- ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \
-}
+#define LDMA_TRANSFER_CFG_MEMORY() \
+ { \
+ 0, 0, 0, 0, 0, \
+ false, false, ldmaCfgArbSlotsAs1, \
+ ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \
+ }
/**
* @brief
* Generic DMA transfer configuration for looped memory to memory transfers.
*/
#define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \
-{ \
- 0, 0, 0, 0, 0, \
- false, false, ldmaCfgArbSlotsAs1, \
- ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \
- loopCnt \
-}
+ { \
+ 0, 0, 0, 0, 0, \
+ false, false, ldmaCfgArbSlotsAs1, \
+ ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \
+ loopCnt \
+ }
/**
* @brief
* Generic DMA transfer configuration for memory to/from peripheral transfers.
*/
-#define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \
-{ \
- signal, 0, 0, 0, 0, \
- false, false, ldmaCfgArbSlotsAs1, \
- ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \
-}
+#define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \
+ { \
+ signal, 0, 0, 0, 0, \
+ false, false, ldmaCfgArbSlotsAs1, \
+ ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \
+ }
/**
* @brief
* Generic DMA transfer configuration for looped memory to/from peripheral transfers.
*/
-#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \
-{ \
- signal, 0, 0, 0, 0, \
- false, false, ldmaCfgArbSlotsAs1, \
- ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt \
-}
+#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \
+ { \
+ signal, 0, 0, 0, 0, \
+ false, false, ldmaCfgArbSlotsAs1, \
+ ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt \
+ }
/**
* @brief
@@ -643,31 +785,31 @@
* @param[in] dest Destination data address.
* @param[in] count Number of words to transfer.
*/
-#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD(src, dest, count) \
-{ \
- .xfer = \
- { \
- .structType = ldmaCtrlStructTypeXfer, \
- .structReq = 1, \
- .xferCnt = ( count ) - 1, \
- .byteSwap = 0, \
- .blockSize = ldmaCtrlBlockSizeUnit1, \
- .doneIfs = 1, \
- .reqMode = ldmaCtrlReqModeAll, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = ldmaCtrlSrcIncOne, \
- .size = ldmaCtrlSizeWord, \
- .dstInc = ldmaCtrlDstIncOne, \
- .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
- .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
- .srcAddr = (uint32_t)(src), \
- .dstAddr = (uint32_t)(dest), \
- .linkMode = 0, \
- .link = 0, \
- .linkAddr = 0 \
- } \
-}
+#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD(src, dest, count) \
+ { \
+ .xfer = \
+ { \
+ .structType = ldmaCtrlStructTypeXfer, \
+ .structReq = 1, \
+ .xferCnt = (count) - 1, \
+ .byteSwap = 0, \
+ .blockSize = ldmaCtrlBlockSizeUnit1, \
+ .doneIfs = 1, \
+ .reqMode = ldmaCtrlReqModeAll, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = ldmaCtrlSrcIncOne, \
+ .size = ldmaCtrlSizeWord, \
+ .dstInc = ldmaCtrlDstIncOne, \
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
+ .srcAddr = (uint32_t)(src), \
+ .dstAddr = (uint32_t)(dest), \
+ .linkMode = 0, \
+ .link = 0, \
+ .linkAddr = 0 \
+ } \
+ }
/**
* @brief
@@ -676,31 +818,31 @@
* @param[in] dest Destination data address.
* @param[in] count Number of half-words to transfer.
*/
-#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF(src, dest, count) \
-{ \
- .xfer = \
- { \
- .structType = ldmaCtrlStructTypeXfer, \
- .structReq = 1, \
- .xferCnt = ( count ) - 1, \
- .byteSwap = 0, \
- .blockSize = ldmaCtrlBlockSizeUnit1, \
- .doneIfs = 1, \
- .reqMode = ldmaCtrlReqModeAll, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = ldmaCtrlSrcIncOne, \
- .size = ldmaCtrlSizeHalf, \
- .dstInc = ldmaCtrlDstIncOne, \
- .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
- .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
- .srcAddr = (uint32_t)(src), \
- .dstAddr = (uint32_t)(dest), \
- .linkMode = 0, \
- .link = 0, \
- .linkAddr = 0 \
- } \
-}
+#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF(src, dest, count) \
+ { \
+ .xfer = \
+ { \
+ .structType = ldmaCtrlStructTypeXfer, \
+ .structReq = 1, \
+ .xferCnt = (count) - 1, \
+ .byteSwap = 0, \
+ .blockSize = ldmaCtrlBlockSizeUnit1, \
+ .doneIfs = 1, \
+ .reqMode = ldmaCtrlReqModeAll, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = ldmaCtrlSrcIncOne, \
+ .size = ldmaCtrlSizeHalf, \
+ .dstInc = ldmaCtrlDstIncOne, \
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
+ .srcAddr = (uint32_t)(src), \
+ .dstAddr = (uint32_t)(dest), \
+ .linkMode = 0, \
+ .link = 0, \
+ .linkAddr = 0 \
+ } \
+ }
/**
* @brief
@@ -709,31 +851,31 @@
* @param[in] dest Destination data address.
* @param[in] count Number of bytes to transfer.
*/
-#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE(src, dest, count) \
-{ \
- .xfer = \
- { \
- .structType = ldmaCtrlStructTypeXfer, \
- .structReq = 1, \
- .xferCnt = (count) - 1, \
- .byteSwap = 0, \
- .blockSize = ldmaCtrlBlockSizeUnit1, \
- .doneIfs = 1, \
- .reqMode = ldmaCtrlReqModeAll, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = ldmaCtrlSrcIncOne, \
- .size = ldmaCtrlSizeByte, \
- .dstInc = ldmaCtrlDstIncOne, \
- .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
- .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
- .srcAddr = (uint32_t)(src), \
- .dstAddr = (uint32_t)(dest), \
- .linkMode = 0, \
- .link = 0, \
- .linkAddr = 0 \
- } \
-}
+#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE(src, dest, count) \
+ { \
+ .xfer = \
+ { \
+ .structType = ldmaCtrlStructTypeXfer, \
+ .structReq = 1, \
+ .xferCnt = (count) - 1, \
+ .byteSwap = 0, \
+ .blockSize = ldmaCtrlBlockSizeUnit1, \
+ .doneIfs = 1, \
+ .reqMode = ldmaCtrlReqModeAll, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = ldmaCtrlSrcIncOne, \
+ .size = ldmaCtrlSizeByte, \
+ .dstInc = ldmaCtrlDstIncOne, \
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
+ .srcAddr = (uint32_t)(src), \
+ .dstAddr = (uint32_t)(dest), \
+ .linkMode = 0, \
+ .link = 0, \
+ .linkAddr = 0 \
+ } \
+ }
/**
* @brief
@@ -747,31 +889,31 @@
* @param[in] dest Destination data address.
* @param[in] count Number of words to transfer.
*/
-#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD(src, dest, count) \
-{ \
- .xfer = \
- { \
- .structType = ldmaCtrlStructTypeXfer, \
- .structReq = 1, \
- .xferCnt = (count) - 1, \
- .byteSwap = 0, \
- .blockSize = ldmaCtrlBlockSizeUnit1, \
- .doneIfs = 0, \
- .reqMode = ldmaCtrlReqModeAll, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = ldmaCtrlSrcIncOne, \
- .size = ldmaCtrlSizeWord, \
- .dstInc = ldmaCtrlDstIncOne, \
- .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
- .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
- .srcAddr = (uint32_t)(src), \
- .dstAddr = (uint32_t)(dest), \
- .linkMode = ldmaLinkModeAbs, \
- .link = 1, \
- .linkAddr = 0 /* Must be set runtime ! */ \
- } \
-}
+#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD(src, dest, count) \
+ { \
+ .xfer = \
+ { \
+ .structType = ldmaCtrlStructTypeXfer, \
+ .structReq = 1, \
+ .xferCnt = (count) - 1, \
+ .byteSwap = 0, \
+ .blockSize = ldmaCtrlBlockSizeUnit1, \
+ .doneIfs = 0, \
+ .reqMode = ldmaCtrlReqModeAll, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = ldmaCtrlSrcIncOne, \
+ .size = ldmaCtrlSizeWord, \
+ .dstInc = ldmaCtrlDstIncOne, \
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
+ .srcAddr = (uint32_t)(src), \
+ .dstAddr = (uint32_t)(dest), \
+ .linkMode = ldmaLinkModeAbs, \
+ .link = 1, \
+ .linkAddr = 0 /* Must be set runtime ! */ \
+ } \
+ }
/**
* @brief
@@ -785,31 +927,31 @@
* @param[in] dest Destination data address.
* @param[in] count Number of half-words to transfer.
*/
-#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF(src, dest, count) \
-{ \
- .xfer = \
- { \
- .structType = ldmaCtrlStructTypeXfer, \
- .structReq = 1, \
- .xferCnt = (count) - 1, \
- .byteSwap = 0, \
- .blockSize = ldmaCtrlBlockSizeUnit1, \
- .doneIfs = 0, \
- .reqMode = ldmaCtrlReqModeAll, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = ldmaCtrlSrcIncOne, \
- .size = ldmaCtrlSizeHalf, \
- .dstInc = ldmaCtrlDstIncOne, \
- .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
- .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
- .srcAddr = (uint32_t)(src), \
- .dstAddr = (uint32_t)(dest), \
- .linkMode = ldmaLinkModeAbs, \
- .link = 1, \
- .linkAddr = 0 /* Must be set runtime ! */ \
- } \
-}
+#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF(src, dest, count) \
+ { \
+ .xfer = \
+ { \
+ .structType = ldmaCtrlStructTypeXfer, \
+ .structReq = 1, \
+ .xferCnt = (count) - 1, \
+ .byteSwap = 0, \
+ .blockSize = ldmaCtrlBlockSizeUnit1, \
+ .doneIfs = 0, \
+ .reqMode = ldmaCtrlReqModeAll, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = ldmaCtrlSrcIncOne, \
+ .size = ldmaCtrlSizeHalf, \
+ .dstInc = ldmaCtrlDstIncOne, \
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
+ .srcAddr = (uint32_t)(src), \
+ .dstAddr = (uint32_t)(dest), \
+ .linkMode = ldmaLinkModeAbs, \
+ .link = 1, \
+ .linkAddr = 0 /* Must be set runtime ! */ \
+ } \
+ }
/**
* @brief
@@ -823,31 +965,31 @@
* @param[in] dest Destination data address.
* @param[in] count Number of bytes to transfer.
*/
-#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE(src, dest, count) \
-{ \
- .xfer = \
- { \
- .structType = ldmaCtrlStructTypeXfer, \
- .structReq = 1, \
- .xferCnt = (count) - 1, \
- .byteSwap = 0, \
- .blockSize = ldmaCtrlBlockSizeUnit1, \
- .doneIfs = 0, \
- .reqMode = ldmaCtrlReqModeAll, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = ldmaCtrlSrcIncOne, \
- .size = ldmaCtrlSizeByte, \
- .dstInc = ldmaCtrlDstIncOne, \
- .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
- .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
- .srcAddr = (uint32_t)(src), \
- .dstAddr = (uint32_t)(dest), \
- .linkMode = ldmaLinkModeAbs, \
- .link = 1, \
- .linkAddr = 0 /* Must be set runtime ! */ \
- } \
-}
+#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE(src, dest, count) \
+ { \
+ .xfer = \
+ { \
+ .structType = ldmaCtrlStructTypeXfer, \
+ .structReq = 1, \
+ .xferCnt = (count) - 1, \
+ .byteSwap = 0, \
+ .blockSize = ldmaCtrlBlockSizeUnit1, \
+ .doneIfs = 0, \
+ .reqMode = ldmaCtrlReqModeAll, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = ldmaCtrlSrcIncOne, \
+ .size = ldmaCtrlSizeByte, \
+ .dstInc = ldmaCtrlDstIncOne, \
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
+ .srcAddr = (uint32_t)(src), \
+ .dstAddr = (uint32_t)(dest), \
+ .linkMode = ldmaLinkModeAbs, \
+ .link = 1, \
+ .linkAddr = 0 /* Must be set runtime ! */ \
+ } \
+ }
/**
* @brief
@@ -867,31 +1009,31 @@
* 0=one this descriptor,
* -1=one descriptor back in memory.
*/
-#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD(src, dest, count, linkjmp) \
-{ \
- .xfer = \
- { \
- .structType = ldmaCtrlStructTypeXfer, \
- .structReq = 1, \
- .xferCnt = (count) - 1, \
- .byteSwap = 0, \
- .blockSize = ldmaCtrlBlockSizeUnit1, \
- .doneIfs = 0, \
- .reqMode = ldmaCtrlReqModeAll, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = ldmaCtrlSrcIncOne, \
- .size = ldmaCtrlSizeWord, \
- .dstInc = ldmaCtrlDstIncOne, \
- .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
- .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
- .srcAddr = (uint32_t)(src), \
- .dstAddr = (uint32_t)(dest), \
- .linkMode = ldmaLinkModeRel, \
- .link = 1, \
- .linkAddr = (linkjmp) * 4 \
- } \
-}
+#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD(src, dest, count, linkjmp) \
+ { \
+ .xfer = \
+ { \
+ .structType = ldmaCtrlStructTypeXfer, \
+ .structReq = 1, \
+ .xferCnt = (count) - 1, \
+ .byteSwap = 0, \
+ .blockSize = ldmaCtrlBlockSizeUnit1, \
+ .doneIfs = 0, \
+ .reqMode = ldmaCtrlReqModeAll, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = ldmaCtrlSrcIncOne, \
+ .size = ldmaCtrlSizeWord, \
+ .dstInc = ldmaCtrlDstIncOne, \
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
+ .srcAddr = (uint32_t)(src), \
+ .dstAddr = (uint32_t)(dest), \
+ .linkMode = ldmaLinkModeRel, \
+ .link = 1, \
+ .linkAddr = (linkjmp) * 4 \
+ } \
+ }
/**
* @brief
@@ -911,31 +1053,31 @@
* 0=one this descriptor,
* -1=one descriptor back in memory.
*/
-#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF(src, dest, count, linkjmp) \
-{ \
- .xfer = \
- { \
- .structType = ldmaCtrlStructTypeXfer, \
- .structReq = 1, \
- .xferCnt = (count) - 1, \
- .byteSwap = 0, \
- .blockSize = ldmaCtrlBlockSizeUnit1, \
- .doneIfs = 0, \
- .reqMode = ldmaCtrlReqModeAll, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = ldmaCtrlSrcIncOne, \
- .size = ldmaCtrlSizeHalf, \
- .dstInc = ldmaCtrlDstIncOne, \
- .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
- .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
- .srcAddr = (uint32_t)(src), \
- .dstAddr = (uint32_t)(dest), \
- .linkMode = ldmaLinkModeRel, \
- .link = 1, \
- .linkAddr = (linkjmp) * 4 \
- } \
-}
+#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF(src, dest, count, linkjmp) \
+ { \
+ .xfer = \
+ { \
+ .structType = ldmaCtrlStructTypeXfer, \
+ .structReq = 1, \
+ .xferCnt = (count) - 1, \
+ .byteSwap = 0, \
+ .blockSize = ldmaCtrlBlockSizeUnit1, \
+ .doneIfs = 0, \
+ .reqMode = ldmaCtrlReqModeAll, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = ldmaCtrlSrcIncOne, \
+ .size = ldmaCtrlSizeHalf, \
+ .dstInc = ldmaCtrlDstIncOne, \
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
+ .srcAddr = (uint32_t)(src), \
+ .dstAddr = (uint32_t)(dest), \
+ .linkMode = ldmaLinkModeRel, \
+ .link = 1, \
+ .linkAddr = (linkjmp) * 4 \
+ } \
+ }
/**
* @brief
@@ -955,31 +1097,31 @@
* 0=one this descriptor,
* -1=one descriptor back in memory.
*/
-#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE(src, dest, count, linkjmp) \
-{ \
- .xfer = \
- { \
- .structType = ldmaCtrlStructTypeXfer, \
- .structReq = 1, \
- .xferCnt = (count) - 1, \
- .byteSwap = 0, \
- .blockSize = ldmaCtrlBlockSizeUnit1, \
- .doneIfs = 0, \
- .reqMode = ldmaCtrlReqModeAll, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = ldmaCtrlSrcIncOne, \
- .size = ldmaCtrlSizeByte, \
- .dstInc = ldmaCtrlDstIncOne, \
- .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
- .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
- .srcAddr = (uint32_t)(src), \
- .dstAddr = (uint32_t)(dest), \
- .linkMode = ldmaLinkModeRel, \
- .link = 1, \
- .linkAddr = (linkjmp) * 4 \
- } \
-}
+#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE(src, dest, count, linkjmp) \
+ { \
+ .xfer = \
+ { \
+ .structType = ldmaCtrlStructTypeXfer, \
+ .structReq = 1, \
+ .xferCnt = (count) - 1, \
+ .byteSwap = 0, \
+ .blockSize = ldmaCtrlBlockSizeUnit1, \
+ .doneIfs = 0, \
+ .reqMode = ldmaCtrlReqModeAll, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = ldmaCtrlSrcIncOne, \
+ .size = ldmaCtrlSizeByte, \
+ .dstInc = ldmaCtrlDstIncOne, \
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
+ .srcAddr = (uint32_t)(src), \
+ .dstAddr = (uint32_t)(dest), \
+ .linkMode = ldmaLinkModeRel, \
+ .link = 1, \
+ .linkAddr = (linkjmp) * 4 \
+ } \
+ }
/**
* @brief
@@ -988,31 +1130,31 @@
* @param[in] dest Destination data address.
* @param[in] count Number of bytes to transfer.
*/
-#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(src, dest, count) \
-{ \
- .xfer = \
- { \
- .structType = ldmaCtrlStructTypeXfer, \
- .structReq = 0, \
- .xferCnt = (count) - 1, \
- .byteSwap = 0, \
- .blockSize = ldmaCtrlBlockSizeUnit1, \
- .doneIfs = 1, \
- .reqMode = ldmaCtrlReqModeBlock, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = ldmaCtrlSrcIncNone, \
- .size = ldmaCtrlSizeByte, \
- .dstInc = ldmaCtrlDstIncOne, \
- .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
- .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
- .srcAddr = (uint32_t)(src), \
- .dstAddr = (uint32_t)(dest), \
- .linkMode = 0, \
- .link = 0, \
- .linkAddr = 0 \
- } \
-}
+#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(src, dest, count) \
+ { \
+ .xfer = \
+ { \
+ .structType = ldmaCtrlStructTypeXfer, \
+ .structReq = 0, \
+ .xferCnt = (count) - 1, \
+ .byteSwap = 0, \
+ .blockSize = ldmaCtrlBlockSizeUnit1, \
+ .doneIfs = 1, \
+ .reqMode = ldmaCtrlReqModeBlock, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = ldmaCtrlSrcIncNone, \
+ .size = ldmaCtrlSizeByte, \
+ .dstInc = ldmaCtrlDstIncOne, \
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
+ .srcAddr = (uint32_t)(src), \
+ .dstAddr = (uint32_t)(dest), \
+ .linkMode = 0, \
+ .link = 0, \
+ .linkAddr = 0 \
+ } \
+ }
/**
* @brief
@@ -1021,31 +1163,31 @@
* @param[in] dest Peripheral data destination register address.
* @param[in] count Number of bytes to transfer.
*/
-#define LDMA_DESCRIPTOR_SINGLE_P2P_BYTE(src, dest, count) \
-{ \
- .xfer = \
- { \
- .structType = ldmaCtrlStructTypeXfer, \
- .structReq = 0, \
- .xferCnt = (count) - 1, \
- .byteSwap = 0, \
- .blockSize = ldmaCtrlBlockSizeUnit1, \
- .doneIfs = 1, \
- .reqMode = ldmaCtrlReqModeBlock, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = ldmaCtrlSrcIncNone, \
- .size = ldmaCtrlSizeByte, \
- .dstInc = ldmaCtrlDstIncNone, \
- .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
- .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
- .srcAddr = (uint32_t)(src), \
- .dstAddr = (uint32_t)(dest), \
- .linkMode = 0, \
- .link = 0, \
- .linkAddr = 0 \
- } \
-}
+#define LDMA_DESCRIPTOR_SINGLE_P2P_BYTE(src, dest, count) \
+ { \
+ .xfer = \
+ { \
+ .structType = ldmaCtrlStructTypeXfer, \
+ .structReq = 0, \
+ .xferCnt = (count) - 1, \
+ .byteSwap = 0, \
+ .blockSize = ldmaCtrlBlockSizeUnit1, \
+ .doneIfs = 1, \
+ .reqMode = ldmaCtrlReqModeBlock, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = ldmaCtrlSrcIncNone, \
+ .size = ldmaCtrlSizeByte, \
+ .dstInc = ldmaCtrlDstIncNone, \
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
+ .srcAddr = (uint32_t)(src), \
+ .dstAddr = (uint32_t)(dest), \
+ .linkMode = 0, \
+ .link = 0, \
+ .linkAddr = 0 \
+ } \
+ }
/**
* @brief
@@ -1054,31 +1196,31 @@
* @param[in] dest Peripheral data register destination address.
* @param[in] count Number of bytes to transfer.
*/
-#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(src, dest, count) \
-{ \
- .xfer = \
- { \
- .structType = ldmaCtrlStructTypeXfer, \
- .structReq = 0, \
- .xferCnt = (count) - 1, \
- .byteSwap = 0, \
- .blockSize = ldmaCtrlBlockSizeUnit1, \
- .doneIfs = 1, \
- .reqMode = ldmaCtrlReqModeBlock, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = ldmaCtrlSrcIncOne, \
- .size = ldmaCtrlSizeByte, \
- .dstInc = ldmaCtrlDstIncNone, \
- .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
- .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
- .srcAddr = (uint32_t)(src), \
- .dstAddr = (uint32_t)(dest), \
- .linkMode = 0, \
- .link = 0, \
- .linkAddr = 0 \
- } \
-}
+#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(src, dest, count) \
+ { \
+ .xfer = \
+ { \
+ .structType = ldmaCtrlStructTypeXfer, \
+ .structReq = 0, \
+ .xferCnt = (count) - 1, \
+ .byteSwap = 0, \
+ .blockSize = ldmaCtrlBlockSizeUnit1, \
+ .doneIfs = 1, \
+ .reqMode = ldmaCtrlReqModeBlock, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = ldmaCtrlSrcIncOne, \
+ .size = ldmaCtrlSizeByte, \
+ .dstInc = ldmaCtrlDstIncNone, \
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
+ .srcAddr = (uint32_t)(src), \
+ .dstAddr = (uint32_t)(dest), \
+ .linkMode = 0, \
+ .link = 0, \
+ .linkAddr = 0 \
+ } \
+ }
/**
* @brief
@@ -1092,31 +1234,31 @@
* 0=one this descriptor,
* -1=one descriptor back in memory.
*/
-#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(src, dest, count, linkjmp) \
-{ \
- .xfer = \
- { \
- .structType = ldmaCtrlStructTypeXfer, \
- .structReq = 0, \
- .xferCnt = (count) - 1, \
- .byteSwap = 0, \
- .blockSize = ldmaCtrlBlockSizeUnit1, \
- .doneIfs = 1, \
- .reqMode = ldmaCtrlReqModeBlock, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = ldmaCtrlSrcIncNone, \
- .size = ldmaCtrlSizeByte, \
- .dstInc = ldmaCtrlDstIncOne, \
- .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
- .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
- .srcAddr = (uint32_t)(src), \
- .dstAddr = (uint32_t)(dest), \
- .linkMode = ldmaLinkModeRel, \
- .link = 1, \
- .linkAddr = (linkjmp) * 4 \
- } \
-}
+#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(src, dest, count, linkjmp) \
+ { \
+ .xfer = \
+ { \
+ .structType = ldmaCtrlStructTypeXfer, \
+ .structReq = 0, \
+ .xferCnt = (count) - 1, \
+ .byteSwap = 0, \
+ .blockSize = ldmaCtrlBlockSizeUnit1, \
+ .doneIfs = 1, \
+ .reqMode = ldmaCtrlReqModeBlock, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = ldmaCtrlSrcIncNone, \
+ .size = ldmaCtrlSizeByte, \
+ .dstInc = ldmaCtrlDstIncOne, \
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
+ .srcAddr = (uint32_t)(src), \
+ .dstAddr = (uint32_t)(dest), \
+ .linkMode = ldmaLinkModeRel, \
+ .link = 1, \
+ .linkAddr = (linkjmp) * 4 \
+ } \
+ }
/**
* @brief
@@ -1130,31 +1272,31 @@
* 0=one this descriptor,
* -1=one descriptor back in memory.
*/
-#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE(src, dest, count, linkjmp) \
-{ \
- .xfer = \
- { \
- .structType = ldmaCtrlStructTypeXfer, \
- .structReq = 0, \
- .xferCnt = (count) - 1, \
- .byteSwap = 0, \
- .blockSize = ldmaCtrlBlockSizeUnit1, \
- .doneIfs = 1, \
- .reqMode = ldmaCtrlReqModeBlock, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = ldmaCtrlSrcIncOne, \
- .size = ldmaCtrlSizeByte, \
- .dstInc = ldmaCtrlDstIncNone, \
- .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
- .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
- .srcAddr = (uint32_t)(src), \
- .dstAddr = (uint32_t)(dest), \
- .linkMode = ldmaLinkModeRel, \
- .link = 1, \
- .linkAddr = (linkjmp) * 4 \
- } \
-}
+#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE(src, dest, count, linkjmp) \
+ { \
+ .xfer = \
+ { \
+ .structType = ldmaCtrlStructTypeXfer, \
+ .structReq = 0, \
+ .xferCnt = (count) - 1, \
+ .byteSwap = 0, \
+ .blockSize = ldmaCtrlBlockSizeUnit1, \
+ .doneIfs = 1, \
+ .reqMode = ldmaCtrlReqModeBlock, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = ldmaCtrlSrcIncOne, \
+ .size = ldmaCtrlSizeByte, \
+ .dstInc = ldmaCtrlDstIncNone, \
+ .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
+ .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
+ .srcAddr = (uint32_t)(src), \
+ .dstAddr = (uint32_t)(dest), \
+ .linkMode = ldmaLinkModeRel, \
+ .link = 1, \
+ .linkAddr = (linkjmp) * 4 \
+ } \
+ }
/**
* @brief
@@ -1162,31 +1304,31 @@
* @param[in] value Immediate value to write.
* @param[in] address Write sddress.
*/
-#define LDMA_DESCRIPTOR_SINGLE_WRITE(value, address) \
-{ \
- .wri = \
- { \
- .structType = ldmaCtrlStructTypeWrite, \
- .structReq = 1, \
- .xferCnt = 0, \
- .byteSwap = 0, \
- .blockSize = 0, \
- .doneIfs = 1, \
- .reqMode = 0, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = 0, \
- .size = 0, \
- .dstInc = 0, \
- .srcAddrMode = 0, \
- .dstAddrMode = 0, \
- .immVal = (value), \
- .dstAddr = (uint32_t)(address), \
- .linkMode = 0, \
- .link = 0, \
- .linkAddr = 0 \
- } \
-}
+#define LDMA_DESCRIPTOR_SINGLE_WRITE(value, address) \
+ { \
+ .wri = \
+ { \
+ .structType = ldmaCtrlStructTypeWrite, \
+ .structReq = 1, \
+ .xferCnt = 0, \
+ .byteSwap = 0, \
+ .blockSize = 0, \
+ .doneIfs = 1, \
+ .reqMode = 0, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = 0, \
+ .size = 0, \
+ .dstInc = 0, \
+ .srcAddrMode = 0, \
+ .dstAddrMode = 0, \
+ .immVal = (value), \
+ .dstAddr = (uint32_t)(address), \
+ .linkMode = 0, \
+ .link = 0, \
+ .linkAddr = 0 \
+ } \
+ }
/**
* @brief
@@ -1199,31 +1341,31 @@
* @param[in] value Immediate value to write.
* @param[in] address Write sddress.
*/
-#define LDMA_DESCRIPTOR_LINKABS_WRITE(value, address) \
-{ \
- .wri = \
- { \
- .structType = ldmaCtrlStructTypeWrite, \
- .structReq = 1, \
- .xferCnt = 0, \
- .byteSwap = 0, \
- .blockSize = 0, \
- .doneIfs = 0, \
- .reqMode = 0, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = 0, \
- .size = 0, \
- .dstInc = 0, \
- .srcAddrMode = 0, \
- .dstAddrMode = 0, \
- .immVal = (value), \
- .dstAddr = (uint32_t)(address), \
- .linkMode = ldmaLinkModeAbs, \
- .link = 1, \
- .linkAddr = 0 /* Must be set runtime ! */ \
- } \
-}
+#define LDMA_DESCRIPTOR_LINKABS_WRITE(value, address) \
+ { \
+ .wri = \
+ { \
+ .structType = ldmaCtrlStructTypeWrite, \
+ .structReq = 1, \
+ .xferCnt = 0, \
+ .byteSwap = 0, \
+ .blockSize = 0, \
+ .doneIfs = 0, \
+ .reqMode = 0, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = 0, \
+ .size = 0, \
+ .dstInc = 0, \
+ .srcAddrMode = 0, \
+ .dstAddrMode = 0, \
+ .immVal = (value), \
+ .dstAddr = (uint32_t)(address), \
+ .linkMode = ldmaLinkModeAbs, \
+ .link = 1, \
+ .linkAddr = 0 /* Must be set runtime ! */ \
+ } \
+ }
/**
* @brief
@@ -1236,31 +1378,31 @@
* 0=one this descriptor,
* -1=one descriptor back in memory.
*/
-#define LDMA_DESCRIPTOR_LINKREL_WRITE(value, address, linkjmp) \
-{ \
- .wri = \
- { \
- .structType = ldmaCtrlStructTypeWrite, \
- .structReq = 1, \
- .xferCnt = 0, \
- .byteSwap = 0, \
- .blockSize = 0, \
- .doneIfs = 0, \
- .reqMode = 0, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = 0, \
- .size = 0, \
- .dstInc = 0, \
- .srcAddrMode = 0, \
- .dstAddrMode = 0, \
- .immVal = (value), \
- .dstAddr = (uint32_t)(address), \
- .linkMode = ldmaLinkModeRel, \
- .link = 1, \
- .linkAddr = (linkjmp) * 4 \
- } \
-}
+#define LDMA_DESCRIPTOR_LINKREL_WRITE(value, address, linkjmp) \
+ { \
+ .wri = \
+ { \
+ .structType = ldmaCtrlStructTypeWrite, \
+ .structReq = 1, \
+ .xferCnt = 0, \
+ .byteSwap = 0, \
+ .blockSize = 0, \
+ .doneIfs = 0, \
+ .reqMode = 0, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = 0, \
+ .size = 0, \
+ .dstInc = 0, \
+ .srcAddrMode = 0, \
+ .dstAddrMode = 0, \
+ .immVal = (value), \
+ .dstAddr = (uint32_t)(address), \
+ .linkMode = ldmaLinkModeRel, \
+ .link = 1, \
+ .linkAddr = (linkjmp) * 4 \
+ } \
+ }
/**
* @brief
@@ -1270,33 +1412,33 @@
* @param[in] matchValue Sync pattern to match.
* @param[in] matchEnable Sync pattern bits to enable for match.
*/
-#define LDMA_DESCRIPTOR_SINGLE_SYNC(set, clr, matchValue, matchEnable) \
-{ \
- .sync = \
- { \
- .structType = ldmaCtrlStructTypeSync, \
- .structReq = 1, \
- .xferCnt = 0, \
- .byteSwap = 0, \
- .blockSize = 0, \
- .doneIfs = 1, \
- .reqMode = 0, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = 0, \
- .size = 0, \
- .dstInc = 0, \
- .srcAddrMode = 0, \
- .dstAddrMode = 0, \
- .syncSet = (set), \
- .syncClr = (clr), \
- .matchVal = (matchValue), \
- .matchEn = (matchEnable), \
- .linkMode = 0, \
- .link = 0, \
- .linkAddr = 0 \
- } \
-}
+#define LDMA_DESCRIPTOR_SINGLE_SYNC(set, clr, matchValue, matchEnable) \
+ { \
+ .sync = \
+ { \
+ .structType = ldmaCtrlStructTypeSync, \
+ .structReq = 1, \
+ .xferCnt = 0, \
+ .byteSwap = 0, \
+ .blockSize = 0, \
+ .doneIfs = 1, \
+ .reqMode = 0, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = 0, \
+ .size = 0, \
+ .dstInc = 0, \
+ .srcAddrMode = 0, \
+ .dstAddrMode = 0, \
+ .syncSet = (set), \
+ .syncClr = (clr), \
+ .matchVal = (matchValue), \
+ .matchEn = (matchEnable), \
+ .linkMode = 0, \
+ .link = 0, \
+ .linkAddr = 0 \
+ } \
+ }
/**
* @brief
@@ -1311,33 +1453,33 @@
* @param[in] matchValue Sync pattern to match.
* @param[in] matchEnable Sync pattern bits to enable for match.
*/
-#define LDMA_DESCRIPTOR_LINKABS_SYNC(set, clr, matchValue, matchEnable) \
-{ \
- .sync = \
- { \
- .structType = ldmaCtrlStructTypeSync, \
- .structReq = 1, \
- .xferCnt = 0, \
- .byteSwap = 0, \
- .blockSize = 0, \
- .doneIfs = 0, \
- .reqMode = 0, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = 0, \
- .size = 0, \
- .dstInc = 0, \
- .srcAddrMode = 0, \
- .dstAddrMode = 0, \
- .syncSet = (set), \
- .syncClr = (clr), \
- .matchVal = (matchValue), \
- .matchEn = (matchEnable), \
- .linkMode = ldmaLinkModeAbs, \
- .link = 1, \
- .linkAddr = 0 /* Must be set runtime ! */ \
- } \
-}
+#define LDMA_DESCRIPTOR_LINKABS_SYNC(set, clr, matchValue, matchEnable) \
+ { \
+ .sync = \
+ { \
+ .structType = ldmaCtrlStructTypeSync, \
+ .structReq = 1, \
+ .xferCnt = 0, \
+ .byteSwap = 0, \
+ .blockSize = 0, \
+ .doneIfs = 0, \
+ .reqMode = 0, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = 0, \
+ .size = 0, \
+ .dstInc = 0, \
+ .srcAddrMode = 0, \
+ .dstAddrMode = 0, \
+ .syncSet = (set), \
+ .syncClr = (clr), \
+ .matchVal = (matchValue), \
+ .matchEn = (matchEnable), \
+ .linkMode = ldmaLinkModeAbs, \
+ .link = 1, \
+ .linkAddr = 0 /* Must be set runtime ! */ \
+ } \
+ }
/**
* @brief
@@ -1353,32 +1495,32 @@
* -1=one descriptor back in memory.
*/
#define LDMA_DESCRIPTOR_LINKREL_SYNC(set, clr, matchValue, matchEnable, linkjmp) \
-{ \
- .sync = \
{ \
- .structType = ldmaCtrlStructTypeSync, \
- .structReq = 1, \
- .xferCnt = 0, \
- .byteSwap = 0, \
- .blockSize = 0, \
- .doneIfs = 0, \
- .reqMode = 0, \
- .decLoopCnt = 0, \
- .ignoreSrec = 0, \
- .srcInc = 0, \
- .size = 0, \
- .dstInc = 0, \
- .srcAddrMode = 0, \
- .dstAddrMode = 0, \
- .syncSet = (set), \
- .syncClr = (clr), \
- .matchVal = (matchValue), \
- .matchEn = (matchEnable), \
- .linkMode = ldmaLinkModeRel, \
- .link = 1, \
- .linkAddr = (linkjmp) * 4 \
- } \
-}
+ .sync = \
+ { \
+ .structType = ldmaCtrlStructTypeSync, \
+ .structReq = 1, \
+ .xferCnt = 0, \
+ .byteSwap = 0, \
+ .blockSize = 0, \
+ .doneIfs = 0, \
+ .reqMode = 0, \
+ .decLoopCnt = 0, \
+ .ignoreSrec = 0, \
+ .srcInc = 0, \
+ .size = 0, \
+ .dstInc = 0, \
+ .srcAddrMode = 0, \
+ .dstAddrMode = 0, \
+ .syncSet = (set), \
+ .syncClr = (clr), \
+ .matchVal = (matchValue), \
+ .matchEn = (matchEnable), \
+ .linkMode = ldmaLinkModeRel, \
+ .link = 1, \
+ .linkAddr = (linkjmp) * 4 \
+ } \
+ }
/*******************************************************************************
***************************** PROTOTYPES **********************************
@@ -1394,7 +1536,6 @@
bool LDMA_TransferDone(int ch);
uint32_t LDMA_TransferRemainingCount(int ch);
-
/***************************************************************************//**
* @brief
* Clear one or more pending LDMA interrupts.
@@ -1409,7 +1550,6 @@
LDMA->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more LDMA interrupts.
@@ -1424,7 +1564,6 @@
LDMA->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more LDMA interrupts.
@@ -1444,7 +1583,6 @@
LDMA->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending LDMA interrupt flags.
@@ -1462,7 +1600,6 @@
return LDMA->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending LDMA interrupt flags.
@@ -1485,7 +1622,6 @@
return LDMA->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending LDMA interrupts
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_lesense.h
* @brief Low Energy Sensor (LESENSE) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -43,7 +43,6 @@
extern "C" {
#endif
-
/***************************************************************************//**
* @addtogroup emlib
* @{
@@ -68,8 +67,7 @@
* counter.
* Note: these enumeration values are being used for different clock division
* related configuration parameters (hfPresc, lfPresc, pcPresc). */
-typedef enum
-{
+typedef enum {
lesenseClkDiv_1 = 0, /**< Divide clock by 1. */
lesenseClkDiv_2 = 1, /**< Divide clock by 2. */
lesenseClkDiv_4 = 2, /**< Divide clock by 4. */
@@ -80,10 +78,8 @@
lesenseClkDiv_128 = 7 /**< Divide clock by 128. */
} LESENSE_ClkPresc_TypeDef;
-
/** Scan modes. */
-typedef enum
-{
+typedef enum {
/** New scan is started each time the period counter overflows. */
lesenseScanStartPeriodic = LESENSE_CTRL_SCANMODE_PERIODIC,
@@ -94,46 +90,42 @@
lesenseScanStartPRS = LESENSE_CTRL_SCANMODE_PRS
} LESENSE_ScanMode_TypeDef;
-
/** PRS sources.
* Note: these enumeration values are being used for different PRS related
* configuration parameters. */
-typedef enum
-{
+typedef enum {
lesensePRSCh0 = 0, /**< PRS channel 0. */
lesensePRSCh1 = 1, /**< PRS channel 1. */
lesensePRSCh2 = 2, /**< PRS channel 2. */
lesensePRSCh3 = 3, /**< PRS channel 3. */
-#if defined( LESENSE_CTRL_PRSSEL_PRSCH4 )
+#if defined(LESENSE_CTRL_PRSSEL_PRSCH4)
lesensePRSCh4 = 4, /**< PRS channel 4. */
#endif
-#if defined( LESENSE_CTRL_PRSSEL_PRSCH5 )
+#if defined(LESENSE_CTRL_PRSSEL_PRSCH5)
lesensePRSCh5 = 5, /**< PRS channel 5. */
#endif
-#if defined( LESENSE_CTRL_PRSSEL_PRSCH6 )
+#if defined(LESENSE_CTRL_PRSSEL_PRSCH6)
lesensePRSCh6 = 6, /**< PRS channel 6. */
#endif
-#if defined( LESENSE_CTRL_PRSSEL_PRSCH7 )
+#if defined(LESENSE_CTRL_PRSSEL_PRSCH7)
lesensePRSCh7 = 7, /**< PRS channel 7. */
#endif
-#if defined( LESENSE_CTRL_PRSSEL_PRSCH8 )
+#if defined(LESENSE_CTRL_PRSSEL_PRSCH8)
lesensePRSCh8 = 8, /**< PRS channel 8. */
#endif
-#if defined( LESENSE_CTRL_PRSSEL_PRSCH9 )
+#if defined(LESENSE_CTRL_PRSSEL_PRSCH9)
lesensePRSCh9 = 9, /**< PRS channel 9. */
#endif
-#if defined( LESENSE_CTRL_PRSSEL_PRSCH10 )
+#if defined(LESENSE_CTRL_PRSSEL_PRSCH10)
lesensePRSCh10 = 10, /**< PRS channel 10.*/
#endif
-#if defined( LESENSE_CTRL_PRSSEL_PRSCH11 )
+#if defined(LESENSE_CTRL_PRSSEL_PRSCH11)
lesensePRSCh11 = 11, /**< PRS channel 11.*/
#endif
} LESENSE_PRSSel_TypeDef;
-
/** Locations of the alternate excitation function. */
-typedef enum
-{
+typedef enum {
/** Alternate excitation is mapped to the LES_ALTEX pins. */
lesenseAltExMapALTEX = _LESENSE_CTRL_ALTEXMAP_ALTEX,
@@ -149,10 +141,8 @@
#endif
} LESENSE_AltExMap_TypeDef;
-
/** Result buffer interrupt and DMA trigger levels. */
-typedef enum
-{
+typedef enum {
/** DMA and interrupt flags are set when result buffer is halffull. */
lesenseBufTrigHalf = LESENSE_CTRL_BUFIDL_HALFFULL,
@@ -160,10 +150,8 @@
lesenseBufTrigFull = LESENSE_CTRL_BUFIDL_FULL
} LESENSE_BufTrigLevel_TypeDef;
-
/** Modes of operation for DMA wakeup from EM2. */
-typedef enum
-{
+typedef enum {
/** No DMA wakeup from EM2. */
lesenseDMAWakeUpDisable = LESENSE_CTRL_DMAWU_DISABLE,
@@ -176,10 +164,8 @@
lesenseDMAWakeUpBufLevel = LESENSE_CTRL_DMAWU_BUFLEVEL
} LESENSE_DMAWakeUp_TypeDef;
-
/** Bias modes. */
-typedef enum
-{
+typedef enum {
/** Duty cycle bias module between low power and high accuracy mode. */
lesenseBiasModeDutyCycle = LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE,
@@ -190,10 +176,8 @@
lesenseBiasModeDontTouch = LESENSE_BIASCTRL_BIASMODE_DONTTOUCH
} LESENSE_BiasMode_TypeDef;
-
/** Scan configuration. */
-typedef enum
-{
+typedef enum {
/** The channel configuration registers (CHx_CONF) used are directly mapped to
* the channel number. */
lesenseScanConfDirMap = LESENSE_CTRL_SCANCONF_DIRMAP,
@@ -211,10 +195,8 @@
lesenseScanConfDecDef = LESENSE_CTRL_SCANCONF_DECDEF
} LESENSE_ScanConfSel_TypeDef;
-
/** DAC CHx data control configuration. */
-typedef enum
-{
+typedef enum {
/** DAC channel x data is defined by DAC_CHxDATA register.
* Note: this value could be used for both DAC Ch0 and Ch1. */
lesenseDACIfData = _LESENSE_PERCTRL_DACCH0DATA_DACDATA,
@@ -234,8 +216,7 @@
#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK)
/** DAC channel x conversion mode configuration. */
-typedef enum
-{
+typedef enum {
/** LESENSE doesn't control DAC channel x.
* Note: this value could be used for both DAC Ch0 and Ch1. */
lesenseDACConvModeDisable = _LESENSE_PERCTRL_DACCH0CONV_DISABLE,
@@ -256,8 +237,7 @@
#if defined(_LESENSE_PERCTRL_DACCH0OUT_MASK)
/** DAC channel x output mode configuration. */
-typedef enum
-{
+typedef enum {
/** DAC CHx output to pin and ACMP/ADC disabled.
* Note: this value could be used for both DAC Ch0 and Ch1. */
lesenseDACOutModeDisable = _LESENSE_PERCTRL_DACCH0OUT_DISABLE,
@@ -276,11 +256,9 @@
} LESENSE_ControlDACOut_TypeDef;
#endif
-
#if defined(_LESENSE_PERCTRL_DACREF_MASK)
/** DAC reference configuration. */
-typedef enum
-{
+typedef enum {
/** DAC uses VDD reference. */
lesenseDACRefVdd = LESENSE_PERCTRL_DACREF_VDD,
@@ -289,10 +267,8 @@
} LESENSE_DACRef_TypeDef;
#endif
-
/** ACMPx control configuration. */
-typedef enum
-{
+typedef enum {
/** LESENSE does not control the ACMPx.
* Note: this value could be used for both ACMP0 and ACMP1. */
lesenseACMPModeDisable = _LESENSE_PERCTRL_ACMP0MODE_DISABLE,
@@ -306,10 +282,8 @@
lesenseACMPModeMuxThres = _LESENSE_PERCTRL_ACMP0MODE_MUXTHRES
} LESENSE_ControlACMP_TypeDef;
-
/** Warm up modes. ACMP and DAC duty cycle mode configuration. */
-typedef enum
-{
+typedef enum {
/** ACMPs and DACs are shut down when LESENSE is idle. */
lesenseWarmupModeNormal = LESENSE_PERCTRL_WARMUPMODE_NORMAL,
@@ -323,10 +297,8 @@
lesenseWarmupModeKeepWarm = LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM
} LESENSE_WarmupMode_TypeDef;
-
/** Decoder input source configuration. */
-typedef enum
-{
+typedef enum {
/** The SENSORSTATE register is used as input to the decoder. */
lesenseDecInputSensorSt = LESENSE_DECCTRL_INPUT_SENSORSTATE,
@@ -334,15 +306,13 @@
lesenseDecInputPRS = LESENSE_DECCTRL_INPUT_PRS
} LESENSE_DecInput_TypeDef;
-
/** Compare source selection for sensor sampling. */
-typedef enum
-{
+typedef enum {
/** Counter output will be used in comparison. */
lesenseSampleModeCounter = 0x0 << _LESENSE_CH_INTERACT_SAMPLE_SHIFT,
- /** ACMP output will be used in comparison. */
- lesenseSampleModeACMP = LESENSE_CH_INTERACT_SAMPLE_ACMP,
+ /** ACMP output will be used in comparison. */
+ lesenseSampleModeACMP = LESENSE_CH_INTERACT_SAMPLE_ACMP,
#if defined(LESENSE_CH_INTERACT_SAMPLE_ADC)
/** ADC output will be used in comparison. */
@@ -353,10 +323,8 @@
#endif
} LESENSE_ChSampleMode_TypeDef;
-
/** Interrupt generation setup for CHx interrupt flag. */
-typedef enum
-{
+typedef enum {
/** No interrupt is generated. */
lesenseSetIntNone = LESENSE_CH_INTERACT_SETIF_NONE,
@@ -370,10 +338,8 @@
lesenseSetIntNegEdge = LESENSE_CH_INTERACT_SETIF_NEGEDGE
} LESENSE_ChIntMode_TypeDef;
-
/** Channel pin mode for the excitation phase of the scan sequence. */
-typedef enum
-{
+typedef enum {
/** Channel pin is disabled. */
lesenseChPinExDis = LESENSE_CH_INTERACT_EXMODE_DISABLE,
@@ -387,10 +353,8 @@
lesenseChPinExDACOut = LESENSE_CH_INTERACT_EXMODE_DACOUT
} LESENSE_ChPinExMode_TypeDef;
-
/** Channel pin mode for the idle phase of the scan sequence. */
-typedef enum
-{
+typedef enum {
/** Channel pin is disabled in idle phase.
* Note: this value could be used for all channels. */
lesenseChPinIdleDis = _LESENSE_IDLECONF_CH0_DISABLE,
@@ -418,10 +382,8 @@
#endif
} LESENSE_ChPinIdleMode_TypeDef;
-
/** Clock used for excitation and sample delay timing. */
-typedef enum
-{
+typedef enum {
/** LFACLK (LF clock) is used. */
lesenseClkLF = _LESENSE_CH_INTERACT_EXCLK_LFACLK,
@@ -429,10 +391,8 @@
lesenseClkHF = _LESENSE_CH_INTERACT_EXCLK_AUXHFRCO
} LESENSE_ChClk_TypeDef;
-
/** Compare modes for counter comparison. */
-typedef enum
-{
+typedef enum {
/** Comparison evaluates to 1 if the sensor data is less than the counter
* threshold, or if the ACMP output is 0. */
lesenseCompModeLess = LESENSE_CH_EVAL_COMP_LESS,
@@ -442,11 +402,9 @@
lesenseCompModeGreaterOrEq = LESENSE_CH_EVAL_COMP_GE
} LESENSE_ChCompMode_TypeDef;
-
#if defined(_LESENSE_CH_EVAL_MODE_MASK)
/** Sensor evaluation modes. */
-typedef enum
-{
+typedef enum {
/** Threshold comparison evaluation mode. In this mode the sensor data
* is compared to the configured threshold value. Two possible comparison
* operators can be used on the sensor data, either >= (GE) or < (LT).
@@ -469,10 +427,8 @@
} LESENSE_ChEvalMode_TypeDef;
#endif
-
/** Idle phase configuration of alternate excitation channels. */
-typedef enum
-{
+typedef enum {
/** ALTEX output is disabled in idle phase.
* Note: this value could be used for all alternate excitation channels. */
lesenseAltExPinIdleDis = _LESENSE_ALTEXCONF_IDLECONF0_DISABLE,
@@ -486,10 +442,8 @@
lesenseAltExPinIdleLow = _LESENSE_ALTEXCONF_IDLECONF0_LOW
} LESENSE_AltExPinIdle_TypeDef;
-
/** Transition action modes. */
-typedef enum
-{
+typedef enum {
/** No PRS pulses generated (if PRSCOUNT == 0).
* Do not count (if PRSCOUNT == 1). */
lesenseTransActNone = LESENSE_ST_TCONFA_PRSACT_NONE,
@@ -528,14 +482,12 @@
lesenseTransActDownAndPRS2 = LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2
} LESENSE_StTransAct_TypeDef;
-
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** Core control (LESENSE_CTRL) descriptor structure. */
-typedef struct
-{
+typedef struct {
/** Select scan start mode to control how the scan start is being triggered.*/
LESENSE_ScanMode_TypeDef scanStart;
@@ -577,24 +529,23 @@
/** Default configuration for LESENSE_CtrlDesc_TypeDef structure. */
#define LESENSE_CORECTRL_DESC_DEFAULT \
-{ \
- lesenseScanStartPeriodic, /* Start new scan each time the period counter overflows. */ \
- lesensePRSCh0, /* Default PRS channel is selected. */ \
- lesenseScanConfDirMap, /* Direct mapping SCANCONF register usage strategy. */ \
- false, /* Don't invert ACMP0 output. */ \
- false, /* Don't invert ACMP1 output. */ \
- false, /* Disable dual sampling. */ \
- true, /* Store scan result after each scan. */ \
- true, /* Overwrite result buffer register even if it is full. */ \
- lesenseBufTrigHalf, /* Trigger interrupt and DMA request if result buffer is half full. */ \
- lesenseDMAWakeUpDisable, /* Don't wake up on DMA from EM2. */ \
- lesenseBiasModeDontTouch, /* Don't touch bias configuration. */ \
- true /* Keep LESENSE running in debug mode. */ \
-}
+ { \
+ lesenseScanStartPeriodic,/* Start new scan each time the period counter overflows. */ \
+ lesensePRSCh0, /* Default PRS channel is selected. */ \
+ lesenseScanConfDirMap, /* Direct mapping SCANCONF register usage strategy. */ \
+ false, /* Don't invert ACMP0 output. */ \
+ false, /* Don't invert ACMP1 output. */ \
+ false, /* Disable dual sampling. */ \
+ true, /* Store scan result after each scan. */ \
+ true, /* Overwrite result buffer register even if it is full. */ \
+ lesenseBufTrigHalf, /* Trigger interrupt and DMA request if result buffer is half full. */ \
+ lesenseDMAWakeUpDisable, /* Don't wake up on DMA from EM2. */ \
+ lesenseBiasModeDontTouch,/* Don't touch bias configuration. */ \
+ true /* Keep LESENSE running in debug mode. */ \
+ }
/** LESENSE timing control descriptor structure. */
-typedef struct
-{
+typedef struct {
/** Set the number of LFACLK cycles to delay sensor interaction on
* each channel. Valid range: 0-3 (2 bit). */
uint8_t startDelay;
@@ -607,23 +558,23 @@
} LESENSE_TimeCtrlDesc_TypeDef;
/** Default configuration for LESENSE_TimeCtrlDesc_TypeDef structure. */
-#define LESENSE_TIMECTRL_DESC_DEFAULT \
-{ \
- 0U, /* No sensor interaction delay. */ \
- false /* Don't delay the AUXHFRCO startup. */ \
-}
-
+#define LESENSE_TIMECTRL_DESC_DEFAULT \
+ { \
+ 0U, /* No sensor interaction delay. */ \
+ false /* Don't delay the AUXHFRCO startup. */ \
+ }
/** LESENSE peripheral control descriptor structure. */
-typedef struct
-{
+typedef struct {
/** Configure DAC channel 0 data control. */
LESENSE_ControlDACData_TypeDef dacCh0Data;
#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK)
/** Configure how LESENSE controls conversion on DAC channel 0. */
LESENSE_ControlDACConv_TypeDef dacCh0ConvMode;
+#endif
+#if defined(_LESENSE_PERCTRL_DACCH0OUT_MASK)
/** Configure how LESENSE controls output on DAC channel 0. */
LESENSE_ControlDACOut_TypeDef dacCh0OutMode;
#endif
@@ -634,7 +585,9 @@
#if defined(_LESENSE_PERCTRL_DACCH1CONV_MASK)
/** Configure how LESENSE controls conversion on DAC channel 1. */
LESENSE_ControlDACConv_TypeDef dacCh1ConvMode;
+#endif
+#if defined(_LESENSE_PERCTRL_DACCH1OUT_MASK)
/** Configure how LESENSE controls output on DAC channel 1. */
LESENSE_ControlDACOut_TypeDef dacCh1OutMode;
#endif
@@ -665,39 +618,57 @@
* set to false the DAC is enabled before every channel measurement. */
bool dacScan;
#endif
+
+#if defined(_LESENSE_PERCTRL_DACSTARTUP_MASK)
+ /** When set to true the DAC is started a half clock cycle before sensor
+ * interaction starts. When set to false, a full clock cycle is used. */
+ bool dacStartupHalf;
+#endif
+
+#if defined(_LESENSE_PERCTRL_DACCH0EN_MASK)
+ /** When set to true, LESENSE controls DAC channel 0. */
+ bool dacCh0En;
+#endif
+
+#if defined(_LESENSE_PERCTRL_DACCH1EN_MASK)
+ /** When set to true, LESENSE controls DAC channel 1. */
+ bool dacCh1En;
+#endif
} LESENSE_PerCtrlDesc_TypeDef;
/** Default configuration for LESENSE_PerCtrl_TypeDef structure. */
#if defined(_SILICON_LABS_32B_SERIES_0)
-#define LESENSE_PERCTRL_DESC_DEFAULT \
-{ \
- lesenseDACIfData, /* DAC channel 0 data is defined by DAC_CH0DATA register */ \
- lesenseDACConvModeDisable, /* LESENSE does not control DAC CH0. */ \
- lesenseDACOutModeDisable, /* DAC channel 0 output to pin disabled. */ \
- lesenseDACIfData, /* DAC channel 1 data is defined by DAC_CH1DATA register */ \
- lesenseDACConvModeDisable, /* LESENSE does not control DAC CH1. */ \
- lesenseDACOutModeDisable, /* DAC channel 1 output to pin disabled. */ \
- 0U, /* DAC prescaling factor of 1 (0+1). */ \
- lesenseDACRefVdd, /* DAC uses VDD reference. */ \
- lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP0. */ \
- lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP1. */ \
- lesenseWarmupModeKeepWarm, /* Keep both ACMPs and the DAC powered up when LESENSE is idle. */ \
-}
+#define LESENSE_PERCTRL_DESC_DEFAULT \
+ { \
+ lesenseDACIfData, /* DAC channel 0 data is defined by DAC_CH0DATA register */ \
+ lesenseDACConvModeDisable,/* LESENSE does not control DAC CH0. */ \
+ lesenseDACOutModeDisable, /* DAC channel 0 output to pin disabled. */ \
+ lesenseDACIfData, /* DAC channel 1 data is defined by DAC_CH1DATA register */ \
+ lesenseDACConvModeDisable,/* LESENSE does not control DAC CH1. */ \
+ lesenseDACOutModeDisable, /* DAC channel 1 output to pin disabled. */ \
+ 0U, /* DAC prescaling factor of 1 (0+1). */ \
+ lesenseDACRefVdd, /* DAC uses VDD reference. */ \
+ lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP0. */ \
+ lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP1. */ \
+ lesenseWarmupModeKeepWarm /* Keep both ACMPs and the DAC powered up when LESENSE is idle. */ \
+ }
#else
#define LESENSE_PERCTRL_DESC_DEFAULT \
-{ \
- lesenseDACIfData, /* DAC channel 0 data is defined by DAC_CH0DATA register. */ \
- lesenseDACIfData, /* DAC channel 1 data is defined by DAC_CH1DATA register. */ \
- lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP0. */ \
- lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP1. */ \
- lesenseWarmupModeKeepWarm, /* Keep both ACMPs and the DAC powered up when LESENSE is idle. */ \
- false, /* DAC is enable for before every channel measurement. */ \
-}
+ { \
+ lesenseDACIfData, /* DAC channel 0 data is defined by DAC_CH0DATA register. */ \
+ lesenseDACIfData, /* DAC channel 1 data is defined by DAC_CH1DATA register. */ \
+ lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP0. */ \
+ lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP1. */ \
+ lesenseWarmupModeKeepWarm,/* Keep both ACMPs and the DAC powered up when LESENSE is idle. */ \
+ false, /* DAC is enabled for before every channel measurement. */ \
+ false, /* DAC is enabled a full clock cycle before sensor interaction */ \
+ false, /* LESENSE does not control DAC channel 0. */ \
+ false /* LESENSE does not control DAC channel 1. */ \
+ }
#endif
/** LESENSE decoder control descriptor structure. */
-typedef struct
-{
+typedef struct {
/** Select the input to the LESENSE decoder. */
LESENSE_DecInput_TypeDef decInput;
@@ -746,27 +717,25 @@
} LESENSE_DecCtrlDesc_TypeDef;
/** Default configuration for LESENSE_PerCtrl_TypeDef structure. */
-#define LESENSE_DECCTRL_DESC_DEFAULT \
-{ \
- lesenseDecInputSensorSt, /* The SENSORSTATE register is used as input to the decoder. */ \
- 0U, /* State 0 is the initial state of the decoder. */ \
- false, /* Disable check of current state. */ \
- true, /* Enable channel x % 16 interrupt on state x change. */ \
- true, /* Enable decoder hysteresis on PRS0 output. */ \
- true, /* Enable decoder hysteresis on PRS1 output. */ \
- true, /* Enable decoder hysteresis on PRS2 output. */ \
- true, /* Enable decoder hysteresis on PRS3 output. */ \
- false, /* Disable count mode on decoder PRS channels 0 and 1*/ \
- lesensePRSCh0, /* PRS Channel 0 as input for bit 0 of the LESENSE decoder. */ \
- lesensePRSCh1, /* PRS Channel 1 as input for bit 1 of the LESENSE decoder. */ \
- lesensePRSCh2, /* PRS Channel 2 as input for bit 2 of the LESENSE decoder. */ \
- lesensePRSCh3, /* PRS Channel 3 as input for bit 3 of the LESENSE decoder. */ \
-}
-
+#define LESENSE_DECCTRL_DESC_DEFAULT \
+ { \
+ lesenseDecInputSensorSt, /* The SENSORSTATE register is used as input to the decoder. */ \
+ 0U, /* State 0 is the initial state of the decoder. */ \
+ false, /* Disable check of current state. */ \
+ true, /* Enable channel x % 16 interrupt on state x change. */ \
+ true, /* Enable decoder hysteresis on PRS0 output. */ \
+ true, /* Enable decoder hysteresis on PRS1 output. */ \
+ true, /* Enable decoder hysteresis on PRS2 output. */ \
+ true, /* Enable decoder hysteresis on PRS3 output. */ \
+ false, /* Disable count mode on decoder PRS channels 0 and 1*/ \
+ lesensePRSCh0, /* PRS Channel 0 as input for bit 0 of the LESENSE decoder. */ \
+ lesensePRSCh1, /* PRS Channel 1 as input for bit 1 of the LESENSE decoder. */ \
+ lesensePRSCh2, /* PRS Channel 2 as input for bit 2 of the LESENSE decoder. */ \
+ lesensePRSCh3, /* PRS Channel 3 as input for bit 3 of the LESENSE decoder. */ \
+ }
/** LESENSE module initialization structure. */
-typedef struct
-{
+typedef struct {
/** LESENSE core configuration parameters. */
LESENSE_CoreCtrlDesc_TypeDef coreCtrl;
@@ -781,18 +750,16 @@
} LESENSE_Init_TypeDef;
/** Default configuration for LESENSE_Init_TypeDef structure. */
-#define LESENSE_INIT_DEFAULT \
-{ \
- .coreCtrl = LESENSE_CORECTRL_DESC_DEFAULT, /* Default core control parameters. */ \
- .timeCtrl = LESENSE_TIMECTRL_DESC_DEFAULT, /* Default time control parameters. */ \
- .perCtrl = LESENSE_PERCTRL_DESC_DEFAULT, /* Default peripheral control parameters. */ \
- .decCtrl = LESENSE_DECCTRL_DESC_DEFAULT /* Default decoder control parameters. */ \
-}
-
+#define LESENSE_INIT_DEFAULT \
+ { \
+ .coreCtrl = LESENSE_CORECTRL_DESC_DEFAULT, /* Default core control parameters. */ \
+ .timeCtrl = LESENSE_TIMECTRL_DESC_DEFAULT, /* Default time control parameters. */ \
+ .perCtrl = LESENSE_PERCTRL_DESC_DEFAULT, /* Default peripheral control parameters. */ \
+ .decCtrl = LESENSE_DECCTRL_DESC_DEFAULT /* Default decoder control parameters. */ \
+ }
/** Channel descriptor structure. */
-typedef struct
-{
+typedef struct {
/** Set to enable scan channel CHx. */
bool enaScanCh;
@@ -873,117 +840,109 @@
/** Select sensor evaluation mode. */
LESENSE_ChEvalMode_TypeDef evalMode;
#endif
-
} LESENSE_ChDesc_TypeDef;
-
/** Configuration structure for all scan channels. */
-typedef struct
-{
+typedef struct {
/** Channel descriptor for all LESENSE channels. */
LESENSE_ChDesc_TypeDef Ch[LESENSE_NUM_CHANNELS];
} LESENSE_ChAll_TypeDef;
/** Default configuration for scan channel. */
#if defined(_LESENSE_CH_EVAL_MODE_MASK)
-#define LESENSE_CH_CONF_DEFAULT \
-{ \
- true, /* Enable scan channel. */ \
- true, /* Enable the assigned pin on scan channel. */ \
- true, /* Enable interrupts on channel. */ \
- lesenseChPinExHigh, /* Channel pin is high during the excitation period. */ \
- lesenseChPinIdleLow, /* Channel pin is low during the idle period. */ \
- false, /* Don't use alternate excitation pins for excitation. */ \
- false, /* Disabled to shift results from this channel to the decoder register. */ \
- false, /* Disabled to invert the scan result bit. */ \
- false, /* Disabled to store counter value in the result buffer. */ \
- lesenseClkLF, /* Use the LF clock for excitation timing. */ \
- lesenseClkLF, /* Use the LF clock for sample timing. */ \
- 0x03U, /* Excitation time is set to 3(+1) excitation clock cycles. */ \
- 0x09U, /* Sample delay is set to 9(+1) sample clock cycles. */ \
- 0x06U, /* Measure delay is set to 6 excitation clock cycles.*/ \
- 0x00U, /* ACMP threshold has been set to 0. */ \
- lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \
- lesenseSetIntNone, /* No interrupt is generated by the channel. */ \
- 0xFFU, /* Counter threshold has bee set to 0xFF. */ \
- lesenseCompModeLess, /* Compare mode has been set to trigger interrupt on "less". */ \
- lesenseEvalModeThreshold /* Compare mode has been set to trigger interrupt on "less". */ \
-}
+#define LESENSE_CH_CONF_DEFAULT \
+ { \
+ false, /* Disable scan channel. */ \
+ false, /* Disable the assigned pin on scan channel. */ \
+ false, /* Disable interrupts on channel. */ \
+ lesenseChPinExDis, /* Channel pin is disabled during the excitation period. */ \
+ lesenseChPinIdleDis, /* Channel pin is disabled during the idle period. */ \
+ false, /* Don't use alternate excitation pins for excitation. */ \
+ false, /* Disabled to shift results from this channel to the decoder register. */ \
+ false, /* Disabled to invert the scan result bit. */ \
+ false, /* Disabled to store counter value in the result buffer. */ \
+ lesenseClkLF, /* Use the LF clock for excitation timing. */ \
+ lesenseClkLF, /* Use the LF clock for sample timing. */ \
+ 0x00U, /* Excitation time is set to 0(+1) excitation clock cycles. */ \
+ 0x00U, /* Sample delay is set to 0(+1) sample clock cycles. */ \
+ 0x00U, /* Measure delay is set to 0 excitation clock cycles.*/ \
+ 0x00U, /* ACMP threshold has been set to 0. */ \
+ lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \
+ lesenseSetIntNone, /* No interrupt is generated by the channel. */ \
+ 0x00U, /* Counter threshold has bee set to 0x00. */ \
+ lesenseCompModeLess, /* Compare mode has been set to trigger interrupt on "less". */ \
+ lesenseEvalModeThreshold /* Eval mode has been set to trigger interrupt on threshold. */ \
+ }
#else
-#define LESENSE_CH_CONF_DEFAULT \
-{ \
- true, /* Enable scan channel. */ \
- true, /* Enable the assigned pin on scan channel. */ \
- true, /* Enable interrupts on channel. */ \
- lesenseChPinExHigh, /* Channel pin is high during the excitation period. */ \
- lesenseChPinIdleLow, /* Channel pin is low during the idle period. */ \
- false, /* Don't use alternate excitation pins for excitation. */ \
- false, /* Disabled to shift results from this channel to the decoder register. */ \
- false, /* Disabled to invert the scan result bit. */ \
- false, /* Disabled to store counter value in the result buffer. */ \
- lesenseClkLF, /* Use the LF clock for excitation timing. */ \
- lesenseClkLF, /* Use the LF clock for sample timing. */ \
- 0x03U, /* Excitation time is set to 3(+1) excitation clock cycles. */ \
- 0x09U, /* Sample delay is set to 9(+1) sample clock cycles. */ \
- 0x06U, /* Measure delay is set to 6 excitation clock cycles.*/ \
- 0x00U, /* ACMP threshold has been set to 0. */ \
- lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \
- lesenseSetIntNone, /* No interrupt is generated by the channel. */ \
- 0xFFU, /* Counter threshold has bee set to 0xFF. */ \
- lesenseCompModeLess /* Compare mode has been set to trigger interrupt on "less". */ \
-}
+#define LESENSE_CH_CONF_DEFAULT \
+ { \
+ false, /* Disable scan channel. */ \
+ false, /* Disable the assigned pin on scan channel. */ \
+ false, /* Disable interrupts on channel. */ \
+ lesenseChPinExDis, /* Channel pin is disabled during the excitation period. */ \
+ lesenseChPinIdleDis, /* Channel pin is disabled during the idle period. */ \
+ false, /* Don't use alternate excitation pins for excitation. */ \
+ false, /* Disabled to shift results from this channel to the decoder register. */ \
+ false, /* Disabled to invert the scan result bit. */ \
+ false, /* Disabled to store counter value in the result buffer. */ \
+ lesenseClkLF, /* Use the LF clock for excitation timing. */ \
+ lesenseClkLF, /* Use the LF clock for sample timing. */ \
+ 0x00U, /* Excitation time is set to 0(+1) excitation clock cycles. */ \
+ 0x00U, /* Sample delay is set to 0(+1) sample clock cycles. */ \
+ 0x00U, /* Measure delay is set to 0 excitation clock cycles.*/ \
+ 0x00U, /* ACMP threshold has been set to 0. */ \
+ lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \
+ lesenseSetIntNone, /* No interrupt is generated by the channel. */ \
+ 0x00U, /* Counter threshold has bee set to 0x00. */ \
+ lesenseCompModeLess /* Compare mode has been set to trigger interrupt on "less". */ \
+ }
#endif
-
/** Default configuration for all sensor channels. */
-#define LESENSE_SCAN_CONF_DEFAULT \
-{ \
- { \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 0. */ \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 1. */ \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 2. */ \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 3. */ \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 4. */ \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 5. */ \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 6. */ \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 7. */ \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 8. */ \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 9. */ \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 10. */ \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 11. */ \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 12. */ \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 13. */ \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 14. */ \
- LESENSE_CH_CONF_DEFAULT, /* Scan channel 15. */ \
- } \
-}
-
+#define LESENSE_SCAN_CONF_DEFAULT \
+ { \
+ { \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 0. */ \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 1. */ \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 2. */ \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 3. */ \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 4. */ \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 5. */ \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 6. */ \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 7. */ \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 8. */ \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 9. */ \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 10. */ \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 11. */ \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 12. */ \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 13. */ \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 14. */ \
+ LESENSE_CH_CONF_DEFAULT, /* Scan channel 15. */ \
+ } \
+ }
/** Alternate excitation descriptor structure. */
-typedef struct
-{
+typedef struct {
/** Configure alternate excitation pins. If set, the corresponding alternate
* excitation pin/signal is enabled. */
bool enablePin;
/** Configure idle phase setup of alternate excitation pins.
- The idleConf parameter is not valid when altExMap==lesenseAltExMapACMP. */
+ The idleConf parameter is not valid when altExMap==lesenseAltExMapACMP. */
LESENSE_AltExPinIdle_TypeDef idleConf;
/** Configure how to control the external alternate excitation pins. Only
- * applies if altExMap has been set to lesenseAltExMapALTEX.
- * If true, the excitation happens on the corresponding alternate excitation
- * pin during the excitation periods of all enabled channels.
- * If false, the excitation happens on the corresponding alternate excitation
- * pin ONLY during the excitation period of the corresponding channel.
- * The alwaysEx parameter is not valid when altExMap==lesenseAltExMapACMP. */
+ * applies if altExMap has been set to lesenseAltExMapALTEX.
+ * If true, the excitation happens on the corresponding alternate excitation
+ * pin during the excitation periods of all enabled channels.
+ * If false, the excitation happens on the corresponding alternate excitation
+ * pin ONLY during the excitation period of the corresponding channel.
+ * The alwaysEx parameter is not valid when altExMap==lesenseAltExMapACMP. */
bool alwaysEx;
} LESENSE_AltExDesc_TypeDef;
-
/** Configuration structure for alternate excitation. */
-typedef struct
-{
+typedef struct {
/** Select alternate excitation mapping. */
LESENSE_AltExMap_TypeDef altExMap;
@@ -1000,70 +959,67 @@
* LESENSE_AltExDesc_TypeDef structure for details regarding which parameters
* are valid. */
LESENSE_AltExDesc_TypeDef AltEx[16];
-
} LESENSE_ConfAltEx_TypeDef;
-
/** Default configuration for alternate excitation channel. */
-#define LESENSE_ALTEX_CH_CONF_DEFAULT \
-{ \
- true, /* Alternate excitation enabled.*/ \
- lesenseAltExPinIdleDis,/* Alternate excitation pin is disabled in idle. */ \
- false /* Excite only for corresponding channel. */ \
-}
+#define LESENSE_ALTEX_CH_CONF_DEFAULT \
+ { \
+ false, /* Alternate excitation disabled.*/ \
+ lesenseAltExPinIdleDis,/* Alternate excitation pin is disabled in idle. */ \
+ false /* Excite only for corresponding channel. */ \
+ }
/** Default configuration for all alternate excitation channels. */
#if defined(_LESENSE_CTRL_ALTEXMAP_ACMP)
-#define LESENSE_ALTEX_CONF_DEFAULT \
-{ \
- lesenseAltExMapACMP, \
- { \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 0. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 1. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 2. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 3. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 4. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 5. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 6. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 7. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 8. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 9. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 10. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 11. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 12. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 13. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 14. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT /* Alternate excitation channel 15. */ \
- } \
-}
+#define LESENSE_ALTEX_CONF_DEFAULT \
+ { \
+ lesenseAltExMapACMP, \
+ { \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 0. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 1. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 2. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 3. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 4. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 5. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 6. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 7. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 8. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 9. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 10. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 11. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 12. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 13. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 14. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT /* Alternate excitation channel 15. */ \
+ } \
+ }
#else
-#define LESENSE_ALTEX_CONF_DEFAULT \
-{ \
- lesenseAltExMapCH, \
- { \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 0. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 1. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 2. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 3. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 4. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 5. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 6. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 7. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 8. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 9. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 10. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 11. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 12. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 13. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 14. */ \
- LESENSE_ALTEX_CH_CONF_DEFAULT /* Alternate excitation channel 15. */ \
- } \
-}
+#define LESENSE_ALTEX_CONF_DEFAULT \
+ { \
+ lesenseAltExMapCH, \
+ { \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 0. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 1. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 2. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 3. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 4. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 5. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 6. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 7. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 8. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 9. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 10. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 11. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 12. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 13. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 14. */ \
+ LESENSE_ALTEX_CH_CONF_DEFAULT /* Alternate excitation channel 15. */ \
+ } \
+ }
#endif
/** Decoder state condition descriptor structure. */
-typedef struct
-{
+typedef struct {
/** Configure compare value. State transition is triggered when sensor state
* equals to this value. Valid range: 0-15 (4 bits). */
uint8_t compVal;
@@ -1086,19 +1042,17 @@
} LESENSE_DecStCond_TypeDef;
/** Default configuration for decoder state condition. */
-#define LESENSE_ST_CONF_DEFAULT \
-{ \
- 0x0FU, /* Compare value set to 0x0F. */ \
- 0x00U, /* All decoder inputs masked. */ \
- 0U, /* Next state is state 0. */ \
- lesenseTransActNone, /* No PRS action performed on compare match. */ \
- false /* No interrupt triggered on compare match. */ \
-}
-
+#define LESENSE_ST_CONF_DEFAULT \
+ { \
+ 0x0FU, /* Compare value set to 0x0F. */ \
+ 0x00U, /* All decoder inputs masked. */ \
+ 0U, /* Next state is state 0. */ \
+ lesenseTransActNone, /* No PRS action performed on compare match. */ \
+ false /* No interrupt triggered on compare match. */ \
+ }
/** Decoder state x configuration structure. */
-typedef struct
-{
+typedef struct {
/** If enabled, the state descriptor pair in the next location will also be
* evaluated. */
bool chainDesc;
@@ -1112,75 +1066,73 @@
LESENSE_DecStCond_TypeDef confB;
} LESENSE_DecStDesc_TypeDef;
-
/** Configuration structure for the decoder. */
-typedef struct
-{
+typedef struct {
/** Descriptor of the 16 or 32 decoder states depending on the device. */
LESENSE_DecStDesc_TypeDef St[LESENSE_NUM_DECODER_STATES];
} LESENSE_DecStAll_TypeDef;
/** Default configuration for all decoder states. */
#if defined(_SILICON_LABS_32B_SERIES_0)
-#define LESENSE_DECODER_CONF_DEFAULT \
-{ /* chain | Descriptor A | Descriptor B */ \
- { \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 0. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 1. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 2. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 3. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 4. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 5. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 6. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 7. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 8. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 9. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 10. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 11. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 12. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 13. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 14. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT } /* Decoder state 15. */ \
- } \
-}
+#define LESENSE_DECODER_CONF_DEFAULT \
+ { /* chain | Descriptor A | Descriptor B */ \
+ { \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 0. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 1. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 2. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 3. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 4. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 5. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 6. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 7. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 8. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 9. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 10. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 11. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 12. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 13. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 14. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT } /* Decoder state 15. */ \
+ } \
+ }
#else
-#define LESENSE_DECODER_CONF_DEFAULT \
-{ /* chain | Descriptor A | Descriptor B */ \
- { \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 0. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 1. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 2. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 3. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 4. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 5. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 6. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 7. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 8. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 9. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 10. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 11. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 12. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 13. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 14. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 15. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 16. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 17. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 18. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 19. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 20. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 21. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 22. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 23. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 24. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 25. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 26. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 27. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 28. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 29. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 30. */ \
- { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT } /* Decoder state 31. */ \
- } \
-}
+#define LESENSE_DECODER_CONF_DEFAULT \
+ { /* chain | Descriptor A | Descriptor B */ \
+ { \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 0. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 1. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 2. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 3. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 4. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 5. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 6. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 7. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 8. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 9. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 10. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 11. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 12. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 13. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 14. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 15. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 16. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 17. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 18. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 19. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 20. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 21. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 22. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 23. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 24. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 25. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 26. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 27. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 28. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 29. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 30. */ \
+ { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT } /* Decoder state 31. */ \
+ } \
+ }
#endif
/*******************************************************************************
@@ -1236,7 +1188,6 @@
void LESENSE_DecoderStart(void);
void LESENSE_ResultBufferClear(void);
-
/***************************************************************************//**
* @brief
* Stop LESENSE decoder.
@@ -1251,7 +1202,6 @@
LESENSE->DECCTRL |= LESENSE_DECCTRL_DISABLE;
}
-
/***************************************************************************//**
* @brief
* Get the current status of LESENSE.
@@ -1271,7 +1221,6 @@
return LESENSE->STATUS;
}
-
/***************************************************************************//**
* @brief
* Wait until the status of LESENSE is equal to what requested.
@@ -1298,7 +1247,6 @@
;
}
-
/***************************************************************************//**
* @brief
* Get the currently active channel index.
@@ -1312,7 +1260,6 @@
return LESENSE->CURCH;
}
-
/***************************************************************************//**
* @brief
* Get the latest scan comparison result (1 bit / channel).
@@ -1329,7 +1276,6 @@
return LESENSE->SCANRES & _LESENSE_SCANRES_SCANRES_MASK;
}
-
/***************************************************************************//**
* @brief
* Get the oldest unread data from the result buffer.
@@ -1348,7 +1294,6 @@
return LESENSE->BUFDATA;
}
-
/***************************************************************************//**
* @brief
* Get data from the result data buffer.
@@ -1383,7 +1328,6 @@
return LESENSE->SENSORSTATE;
}
-
#if defined(LESENSE_POWERDOWN_RAM)
/***************************************************************************//**
* @brief
@@ -1404,7 +1348,6 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Clear one or more pending LESENSE interrupts.
@@ -1419,7 +1362,6 @@
LESENSE->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more LESENSE interrupts.
@@ -1434,7 +1376,6 @@
LESENSE->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more LESENSE interrupts.
@@ -1449,7 +1390,6 @@
LESENSE->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending LESENSE interrupts from SW.
@@ -1464,7 +1404,6 @@
LESENSE->IFS = flags;
}
-
/***************************************************************************//**
* @brief
* Get pending LESENSE interrupt flags.
@@ -1481,7 +1420,6 @@
return LESENSE->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending LESENSE interrupt flags.
@@ -1512,7 +1450,6 @@
return LESENSE->IF & tmp;
}
-
/** @} (end addtogroup LESENSE) */
/** @} (end addtogroup emlib) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_letimer.h
* @brief Low Energy Timer (LETIMER) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -56,8 +56,7 @@
******************************************************************************/
/** Repeat mode. */
-typedef enum
-{
+typedef enum {
/** Count until stopped by SW. */
letimerRepeatFree = _LETIMER_CTRL_REPMODE_FREE,
/** Count REP0 times. */
@@ -74,10 +73,8 @@
letimerRepeatDouble = _LETIMER_CTRL_REPMODE_DOUBLE
} LETIMER_RepeatMode_TypeDef;
-
/** Underflow action on output. */
-typedef enum
-{
+typedef enum {
/** No output action. */
letimerUFOANone = _LETIMER_CTRL_UFOA0_NONE,
/** Toggle output when counter underflows. */
@@ -93,8 +90,7 @@
******************************************************************************/
/** LETIMER initialization structure. */
-typedef struct
-{
+typedef struct {
bool enable; /**< Start counting when init completed. */
bool debugRun; /**< Counter shall keep running during debug halt. */
#if defined(LETIMER_CTRL_RTCC0TEN)
@@ -113,32 +109,32 @@
/** Default config for LETIMER init structure. */
#if defined(LETIMER_CTRL_RTCC0TEN)
#define LETIMER_INIT_DEFAULT \
-{ \
- true, /* Enable timer when init complete. */ \
- false, /* Stop counter during debug halt. */ \
- false, /* Do not start counting on RTC COMP0 match. */ \
- false, /* Do not start counting on RTC COMP1 match. */ \
- false, /* Do not load COMP0 into CNT on underflow. */ \
- false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \
- 0, /* Idle value 0 for output 0. */ \
- 0, /* Idle value 0 for output 1. */ \
- letimerUFOANone, /* No action on underflow on output 0. */ \
- letimerUFOANone, /* No action on underflow on output 1. */ \
- letimerRepeatFree /* Count until stopped by SW. */ \
-}
+ { \
+ true, /* Enable timer when init complete. */ \
+ false, /* Stop counter during debug halt. */ \
+ false, /* Do not start counting on RTC COMP0 match. */ \
+ false, /* Do not start counting on RTC COMP1 match. */ \
+ false, /* Do not load COMP0 into CNT on underflow. */ \
+ false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \
+ 0, /* Idle value 0 for output 0. */ \
+ 0, /* Idle value 0 for output 1. */ \
+ letimerUFOANone, /* No action on underflow on output 0. */ \
+ letimerUFOANone, /* No action on underflow on output 1. */ \
+ letimerRepeatFree /* Count until stopped by SW. */ \
+ }
#else
#define LETIMER_INIT_DEFAULT \
-{ \
- true, /* Enable timer when init complete. */ \
- false, /* Stop counter during debug halt. */ \
- false, /* Do not load COMP0 into CNT on underflow. */ \
- false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \
- 0, /* Idle value 0 for output 0. */ \
- 0, /* Idle value 0 for output 1. */ \
- letimerUFOANone, /* No action on underflow on output 0. */ \
- letimerUFOANone, /* No action on underflow on output 1. */ \
- letimerRepeatFree /* Count until stopped by SW. */ \
-}
+ { \
+ true, /* Enable timer when init complete. */ \
+ false, /* Stop counter during debug halt. */ \
+ false, /* Do not load COMP0 into CNT on underflow. */ \
+ false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \
+ 0, /* Idle value 0 for output 0. */ \
+ 0, /* Idle value 0 for output 1. */ \
+ letimerUFOANone, /* No action on underflow on output 0. */ \
+ letimerUFOANone, /* No action on underflow on output 1. */ \
+ letimerRepeatFree /* Count until stopped by SW. */ \
+ }
#endif
/*******************************************************************************
@@ -150,7 +146,6 @@
unsigned int comp,
uint32_t value);
-
/***************************************************************************//**
* @brief
* Get LETIMER counter value.
@@ -166,14 +161,12 @@
return(letimer->CNT);
}
-
void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable);
#if defined(_LETIMER_FREEZE_MASK)
void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable);
#endif
void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init);
-
/***************************************************************************//**
* @brief
* Clear one or more pending LETIMER interrupts.
@@ -191,7 +184,6 @@
letimer->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more LETIMER interrupts.
@@ -208,7 +200,6 @@
letimer->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more LETIMER interrupts.
@@ -230,7 +221,6 @@
letimer->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending LETIMER interrupt flags.
@@ -250,7 +240,6 @@
return letimer->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending LETIMER interrupt flags.
@@ -276,7 +265,6 @@
{
uint32_t ien;
-
/* Store flags in temporary variable in order to define explicit order
* of volatile accesses. */
ien = letimer->IEN;
@@ -285,7 +273,6 @@
return letimer->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending LETIMER interrupts from SW.
@@ -302,14 +289,12 @@
letimer->IFS = flags;
}
-
uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep);
void LETIMER_RepeatSet(LETIMER_TypeDef *letimer,
unsigned int rep,
uint32_t value);
void LETIMER_Reset(LETIMER_TypeDef *letimer);
-
/** @} (end addtogroup LETIMER) */
/** @} (end addtogroup emlib) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h Thu Dec 07 14:01:42 2017 +0000
@@ -2,9 +2,9 @@
* @file em_leuart.h
* @brief Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
* peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -58,16 +58,13 @@
******************************************************************************/
/** Databit selection. */
-typedef enum
-{
+typedef enum {
leuartDatabits8 = LEUART_CTRL_DATABITS_EIGHT, /**< 8 databits. */
leuartDatabits9 = LEUART_CTRL_DATABITS_NINE /**< 9 databits. */
} LEUART_Databits_TypeDef;
-
/** Enable selection. */
-typedef enum
-{
+typedef enum {
/** Disable both receiver and transmitter. */
leuartDisable = 0x0,
@@ -81,31 +78,25 @@
leuartEnable = (LEUART_CMD_RXEN | LEUART_CMD_TXEN)
} LEUART_Enable_TypeDef;
-
/** Parity selection. */
-typedef enum
-{
+typedef enum {
leuartNoParity = LEUART_CTRL_PARITY_NONE, /**< No parity. */
leuartEvenParity = LEUART_CTRL_PARITY_EVEN, /**< Even parity. */
leuartOddParity = LEUART_CTRL_PARITY_ODD /**< Odd parity. */
} LEUART_Parity_TypeDef;
-
/** Stopbits selection. */
-typedef enum
-{
+typedef enum {
leuartStopbits1 = LEUART_CTRL_STOPBITS_ONE, /**< 1 stopbits. */
leuartStopbits2 = LEUART_CTRL_STOPBITS_TWO /**< 2 stopbits. */
} LEUART_Stopbits_TypeDef;
-
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** Init structure. */
-typedef struct
-{
+typedef struct {
/** Specifies whether TX and/or RX shall be enabled when init completed. */
LEUART_Enable_TypeDef enable;
@@ -130,15 +121,14 @@
/** Default config for LEUART init structure. */
#define LEUART_INIT_DEFAULT \
-{ \
- leuartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 9600, /* 9600 bits/s. */ \
- leuartDatabits8, /* 8 databits. */ \
- leuartNoParity, /* No parity. */ \
- leuartStopbits1 /* 1 stopbit. */ \
-}
-
+ { \
+ leuartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 9600, /* 9600 bits/s. */ \
+ leuartDatabits8, /* 8 databits. */ \
+ leuartNoParity, /* No parity. */ \
+ leuartStopbits1 /* 1 stopbit. */ \
+ }
/*******************************************************************************
***************************** PROTOTYPES **********************************
@@ -171,7 +161,6 @@
leuart->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more LEUART interrupts.
@@ -188,7 +177,6 @@
leuart->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more LEUART interrupts.
@@ -210,7 +198,6 @@
leuart->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending LEUART interrupt flags.
@@ -230,7 +217,6 @@
return leuart->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending LEUART interrupt flags.
@@ -262,7 +248,6 @@
return leuart->IF & tmp;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending LEUART interrupts from SW.
@@ -279,7 +264,6 @@
leuart->IFS = flags;
}
-
/***************************************************************************//**
* @brief
* Get LEUART STATUS register.
@@ -302,7 +286,6 @@
void LEUART_Tx(LEUART_TypeDef *leuart, uint8_t data);
void LEUART_TxExt(LEUART_TypeDef *leuart, uint16_t data);
-
/***************************************************************************//**
* @brief
* Receive one 8 bit frame, (or part of a 9 bit frame).
@@ -336,7 +319,6 @@
return (uint8_t)leuart->RXDATA;
}
-
/***************************************************************************//**
* @brief
* Receive one 8-9 bit frame, with extended information.
@@ -370,7 +352,6 @@
return (uint16_t)leuart->RXDATAX;
}
-
/** @} (end addtogroup LEUART) */
/** @} (end addtogroup emlib) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_mpu.h
* @brief Memory protection unit (MPU) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -71,8 +71,7 @@
/**
* Size of an MPU region.
*/
-typedef enum
-{
+typedef enum {
mpuRegionSize32b = 4, /**< 32 byte region size. */
mpuRegionSize64b = 5, /**< 64 byte region size. */
mpuRegionSize128b = 6, /**< 128 byte region size. */
@@ -106,8 +105,7 @@
/**
* MPU region access permission attributes.
*/
-typedef enum
-{
+typedef enum {
mpuRegionNoAccess = 0, /**< No access what so ever. */
mpuRegionApPRw = 1, /**< Priviledged state R/W only. */
mpuRegionApPRwURo = 2, /**< Priviledged state R/W, User state R only. */
@@ -116,19 +114,17 @@
mpuRegionApPRo_URo = 6 /**< R only in Priviledged and User state. */
} MPU_RegionAp_TypeDef;
-
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** MPU Region init structure. */
-typedef struct
-{
+typedef struct {
bool regionEnable; /**< MPU region enable. */
uint8_t regionNo; /**< MPU region number. */
uint32_t baseAddress; /**< Region baseaddress. */
MPU_RegionSize_TypeDef size; /**< Memory region size. */
- MPU_RegionAp_TypeDef accessPermission; /**< Memory access permissions. */
+ MPU_RegionAp_TypeDef accessPermission; /**< Memory access permissions. */
bool disableExec; /**< Disable execution. */
bool shareable; /**< Memory shareable attribute. */
bool cacheable; /**< Memory cacheable attribute. */
@@ -138,64 +134,59 @@
} MPU_RegionInit_TypeDef;
/** Default configuration of MPU region init structure for flash memory. */
-#define MPU_INIT_FLASH_DEFAULT \
-{ \
- true, /* Enable MPU region. */ \
- 0, /* MPU Region number. */ \
- FLASH_MEM_BASE, /* Flash base address. */ \
- mpuRegionSize1Mb, /* Size - Set to max. */ \
- mpuRegionApFullAccess, /* Access permissions. */ \
- false, /* Execution allowed. */ \
- false, /* Not shareable. */ \
- true, /* Cacheable. */ \
- false, /* Not bufferable. */ \
- 0, /* No subregions. */ \
- 0 /* No TEX attributes. */ \
-}
-
+#define MPU_INIT_FLASH_DEFAULT \
+ { \
+ true, /* Enable MPU region. */ \
+ 0, /* MPU Region number. */ \
+ FLASH_MEM_BASE, /* Flash base address. */ \
+ mpuRegionSize1Mb, /* Size - Set to max. */ \
+ mpuRegionApFullAccess, /* Access permissions. */ \
+ false, /* Execution allowed. */ \
+ false, /* Not shareable. */ \
+ true, /* Cacheable. */ \
+ false, /* Not bufferable. */ \
+ 0, /* No subregions. */ \
+ 0 /* No TEX attributes. */ \
+ }
/** Default configuration of MPU region init structure for sram memory. */
-#define MPU_INIT_SRAM_DEFAULT \
-{ \
- true, /* Enable MPU region. */ \
- 1, /* MPU Region number. */ \
- RAM_MEM_BASE, /* SRAM base address. */ \
- mpuRegionSize128Kb, /* Size - Set to max. */ \
- mpuRegionApFullAccess, /* Access permissions. */ \
- false, /* Execution allowed. */ \
- true, /* Shareable. */ \
- true, /* Cacheable. */ \
- false, /* Not bufferable. */ \
- 0, /* No subregions. */ \
- 0 /* No TEX attributes. */ \
-}
-
+#define MPU_INIT_SRAM_DEFAULT \
+ { \
+ true, /* Enable MPU region. */ \
+ 1, /* MPU Region number. */ \
+ RAM_MEM_BASE, /* SRAM base address. */ \
+ mpuRegionSize128Kb, /* Size - Set to max. */ \
+ mpuRegionApFullAccess, /* Access permissions. */ \
+ false, /* Execution allowed. */ \
+ true, /* Shareable. */ \
+ true, /* Cacheable. */ \
+ false, /* Not bufferable. */ \
+ 0, /* No subregions. */ \
+ 0 /* No TEX attributes. */ \
+ }
/** Default configuration of MPU region init structure for onchip peripherals.*/
-#define MPU_INIT_PERIPHERAL_DEFAULT \
-{ \
- true, /* Enable MPU region. */ \
- 0, /* MPU Region number. */ \
- 0, /* Region base address. */ \
- mpuRegionSize32b, /* Size - Set to minimum */ \
- mpuRegionApFullAccess, /* Access permissions. */ \
- true, /* Execution not allowed. */ \
- true, /* Shareable. */ \
- false, /* Not cacheable. */ \
- true, /* Bufferable. */ \
- 0, /* No subregions. */ \
- 0 /* No TEX attributes. */ \
-}
-
+#define MPU_INIT_PERIPHERAL_DEFAULT \
+ { \
+ true, /* Enable MPU region. */ \
+ 0, /* MPU Region number. */ \
+ 0, /* Region base address. */ \
+ mpuRegionSize32b, /* Size - Set to minimum */ \
+ mpuRegionApFullAccess, /* Access permissions. */ \
+ true, /* Execution not allowed. */ \
+ true, /* Shareable. */ \
+ false, /* Not cacheable. */ \
+ true, /* Bufferable. */ \
+ 0, /* No subregions. */ \
+ 0 /* No TEX attributes. */ \
+ }
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
-
void MPU_ConfigureRegion(const MPU_RegionInit_TypeDef *init);
-
/***************************************************************************//**
* @brief
* Disable the MPU
@@ -204,11 +195,12 @@
******************************************************************************/
__STATIC_INLINE void MPU_Disable(void)
{
+#if defined(SCB_SHCSR_MEMFAULTENA_Msk)
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; /* Disable fault exceptions */
+#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; /* Disable the MPU */
}
-
/***************************************************************************//**
* @brief
* Enable the MPU
@@ -225,10 +217,11 @@
| MPU_CTRL_ENABLE_Msk)));
MPU->CTRL = flags | MPU_CTRL_ENABLE_Msk; /* Enable the MPU */
+#if defined(SCB_SHCSR_MEMFAULTENA_Msk)
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; /* Enable fault exceptions */
+#endif
}
-
/** @} (end addtogroup MPU) */
/** @} (end addtogroup emlib) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_msc.h
* @brief Flash controller (MSC) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -130,8 +130,7 @@
******************************************************************************/
/** Return codes for writing/erasing the flash */
-typedef enum
-{
+typedef enum {
mscReturnOk = 0, /**< Flash write/erase successful. */
mscReturnInvalidAddr = -1, /**< Invalid address. Write to an address that is not flash. */
mscReturnLocked = -2, /**< Flash address is locked. */
@@ -139,11 +138,9 @@
mscReturnUnaligned = -4 /**< Unaligned access to flash. */
} MSC_Status_TypeDef;
-
-#if defined( _MSC_READCTRL_BUSSTRATEGY_MASK )
+#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK)
/** Strategy for prioritized bus access */
-typedef enum
-{
+typedef enum {
mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses */
mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses */
mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses */
@@ -152,8 +149,7 @@
#endif
/** Code execution configuration */
-typedef struct
-{
+typedef struct {
bool scbtEn; /**< Enable Suppressed Conditional Branch Target Prefetch */
bool prefetchEn; /**< Enable MSC prefetching */
bool ifcDis; /**< Disable instruction cache */
@@ -163,15 +159,15 @@
} MSC_ExecConfig_TypeDef;
/** Default MSC ExecConfig initialization */
-#define MSC_EXECCONFIG_DEFAULT \
-{ \
- false, \
- true, \
- false, \
- false, \
- false, \
- false, \
-}
+#define MSC_EXECCONFIG_DEFAULT \
+ { \
+ false, \
+ true, \
+ false, \
+ false, \
+ false, \
+ false, \
+ }
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/* Deprecated type names */
@@ -179,7 +175,6 @@
#define msc_Return_TypeDef MSC_Status_TypeDef
/** @endcond */
-
/***************************************************************************//**
* @brief
* Clear one or more pending MSC interrupts.
@@ -206,7 +201,6 @@
MSC->IEN &= ~(flags);
}
-
/***************************************************************************//**
* @brief
* Enable one or more MSC interrupts.
@@ -225,7 +219,6 @@
MSC->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending MSC interrupt flags.
@@ -242,7 +235,6 @@
return(MSC->IF);
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending MSC interrupt flags.
@@ -265,7 +257,6 @@
return MSC->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending MSC interrupts from SW.
@@ -279,8 +270,7 @@
MSC->IFS = flags;
}
-
-#if defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF )
+#if defined(MSC_IF_CHOF) && defined(MSC_IF_CMOF)
/***************************************************************************//**
* @brief
* Starts measuring cache hit ratio.
@@ -294,14 +284,13 @@
MSC->IFC = MSC_IF_CHOF | MSC_IF_CMOF;
/* Start performance counters */
-#if defined( _MSC_CACHECMD_MASK )
+#if defined(_MSC_CACHECMD_MASK)
MSC->CACHECMD = MSC_CACHECMD_STARTPC;
#else
MSC->CMD = MSC_CMD_STARTPC;
#endif
}
-
/***************************************************************************//**
* @brief
* Stops measuring the hit rate.
@@ -321,13 +310,11 @@
* {
* uint32_t flags;
* flags = MSC->IF;
- * if (flags & MSC_IF_CHOF)
- * {
+ * if (flags & MSC_IF_CHOF) {
* MSC->IFC = MSC_IF_CHOF;
* hitOverflows++;
* }
- * if (flags & MSC_IF_CMOF)
- * {
+ * if (flags & MSC_IF_CMOF) {
* MSC->IFC = MSC_IF_CMOF;
* missOverflows++;
* }
@@ -354,15 +341,14 @@
int32_t total;
int32_t hits;
/* Stop the counter before computing the hit-rate */
-#if defined( _MSC_CACHECMD_MASK )
+#if defined(_MSC_CACHECMD_MASK)
MSC->CACHECMD = MSC_CACHECMD_STOPPC;
#else
MSC->CMD = MSC_CMD_STOPPC;
#endif
/* Check for overflows in performance counters */
- if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF))
- {
+ if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF)) {
return -2;
}
@@ -370,29 +356,26 @@
total = MSC->CACHEMISSES + hits;
/* To avoid a division by zero. */
- if (total == 0)
- {
+ if (total == 0) {
return -1;
}
return (hits * 100) / total;
}
-
/***************************************************************************//**
* @brief
* Flush the contents of the instruction cache.
******************************************************************************/
__STATIC_INLINE void MSC_FlushCache(void)
{
-#if defined( _MSC_CACHECMD_MASK )
+#if defined(_MSC_CACHECMD_MASK)
MSC->CACHECMD = MSC_CACHECMD_INVCACHE;
#else
MSC->CMD = MSC_CMD_INVCACHE;
#endif
}
-
/***************************************************************************//**
* @brief
* Enable or disable instruction cache functionality
@@ -404,8 +387,7 @@
BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, !enable);
}
-
-#if defined( MSC_READCTRL_ICCDIS )
+#if defined(MSC_READCTRL_ICCDIS)
/***************************************************************************//**
* @brief
* Enable or disable instruction cache functionality in IRQs
@@ -418,7 +400,6 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Enable or disable instruction cache flushing when writing to flash
@@ -431,8 +412,7 @@
}
#endif /* defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF ) */
-
-#if defined( _MSC_READCTRL_BUSSTRATEGY_MASK )
+#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK)
/***************************************************************************//**
* @brief
* Configure which unit should get priority on system bus.
@@ -445,7 +425,6 @@
}
#endif
-
/*******************************************************************************
************************* PROTOTYPES **************************************
******************************************************************************/
@@ -468,24 +447,25 @@
#endif
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
- MSC_WriteWord(uint32_t *address,
- void const *data,
- uint32_t numBytes);
+MSC_WriteWord(uint32_t *address,
+ void const *data,
+ uint32_t numBytes);
-#if !defined( _EFM32_GECKO_FAMILY )
+#if !defined(_EFM32_GECKO_FAMILY)
+#if !defined (EM_MSC_RUN_FROM_FLASH) || (_SILICON_LABS_GECKO_INTERNAL_SDID < 84)
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
- MSC_WriteWordFast(uint32_t *address,
- void const *data,
- uint32_t numBytes);
-
+MSC_WriteWordFast(uint32_t *address,
+ void const *data,
+ uint32_t numBytes);
+#endif
#endif
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
- MSC_ErasePage(uint32_t *startAddress);
+MSC_ErasePage(uint32_t *startAddress);
-#if defined( _MSC_MASSLOCK_MASK )
+#if defined(_MSC_MASSLOCK_MASK)
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
- MSC_MassErase(void);
+MSC_MassErase(void);
#endif
/** @} (end addtogroup MSC) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,41 +1,41 @@
/**************************************************************************//**
- * @file em_opamp.h
- * @brief Operational Amplifier (OPAMP) peripheral API
- * @version 5.1.2
- ******************************************************************************
- * @section License
- * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
- *******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
- * obligation to support this Software. Silicon Labs is providing the
- * Software "AS IS", with no express or implied warranties of any kind,
- * including, but not limited to, any implied warranties of merchantability
- * or fitness for any particular purpose or warranties against infringement
- * of any proprietary rights of a third party.
- *
- * Silicon Labs will not be liable for any consequential, incidental, or
- * special damages, or any other relief, or for any claim by any third party,
- * arising from your use of this Software.
- *
- ******************************************************************************/
+* @file em_opamp.h
+* @brief Operational Amplifier (OPAMP) peripheral API
+* @version 5.3.3
+******************************************************************************
+* # License
+* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
+*******************************************************************************
+*
+* Permission is granted to anyone to use this software for any purpose,
+* including commercial applications, and to alter it and redistribute it
+* freely, subject to the following restrictions:
+*
+* 1. The origin of this software must not be misrepresented; you must not
+* claim that you wrote the original software.
+* 2. Altered source versions must be plainly marked as such, and must not be
+* misrepresented as being the original software.
+* 3. This notice may not be removed or altered from any source distribution.
+*
+* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+* obligation to support this Software. Silicon Labs is providing the
+* Software "AS IS", with no express or implied warranties of any kind,
+* including, but not limited to, any implied warranties of merchantability
+* or fitness for any particular purpose or warranties against infringement
+* of any proprietary rights of a third party.
+*
+* Silicon Labs will not be liable for any consequential, incidental, or
+* special damages, or any other relief, or for any claim by any third party,
+* arising from your use of this Software.
+*
+******************************************************************************/
#ifndef EM_OPAMP_H
#define EM_OPAMP_H
#include "em_device.h"
#if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \
- || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0)))
+ || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0)))
#ifdef __cplusplus
extern "C" {
@@ -66,7 +66,13 @@
#if defined(_SILICON_LABS_32B_SERIES_0)
#define DAC_OPA_VALID(opa) ((opa) <= OPA2)
#elif defined(_SILICON_LABS_32B_SERIES_1)
+#if defined(VDAC_STATUS_OPA2ENS)
#define VDAC_OPA_VALID(opa) ((opa) <= OPA2)
+#elif defined(VDAC_STATUS_OPA1ENS)
+#define VDAC_OPA_VALID(opa) ((opa) <= OPA1)
+#else
+#define VDAC_OPA_VALID(opa) ((opa) = OPA0)
+#endif
#endif
/** @endcond */
@@ -76,16 +82,20 @@
******************************************************************************/
/** OPAMP selector values. */
-typedef enum
-{
+typedef enum {
+#if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA0ENS)
OPA0 = 0, /**< Select OPA0. */
+#endif
+#if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA1ENS)
OPA1 = 1, /**< Select OPA1. */
+#endif
+#if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA2ENS)
OPA2 = 2 /**< Select OPA2. */
+#endif
} OPAMP_TypeDef;
/** OPAMP negative terminal input selection values. */
-typedef enum
-{
+typedef enum {
#if defined(_SILICON_LABS_32B_SERIES_0)
opaNegSelDisable = DAC_OPA0MUX_NEGSEL_DISABLE, /**< Input disabled. */
opaNegSelUnityGain = DAC_OPA0MUX_NEGSEL_UG, /**< Unity gain feedback path. */
@@ -164,8 +174,7 @@
} OPAMP_NegSel_TypeDef;
/** OPAMP positive terminal input selection values. */
-typedef enum
-{
+typedef enum {
#if defined(_SILICON_LABS_32B_SERIES_0)
opaPosSelDisable = DAC_OPA0MUX_POSSEL_DISABLE, /**< Input disabled. */
opaPosSelDac = DAC_OPA0MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */
@@ -246,8 +255,7 @@
} OPAMP_PosSel_TypeDef;
/** OPAMP output terminal selection values. */
-typedef enum
-{
+typedef enum {
#if defined(_SILICON_LABS_32B_SERIES_0)
opaOutModeDisable = DAC_OPA0MUX_OUTMODE_DISABLE, /**< OPA output disabled. */
opaOutModeMain = DAC_OPA0MUX_OUTMODE_MAIN, /**< Main output to pin enabled. */
@@ -326,8 +334,7 @@
} OPAMP_OutMode_TypeDef;
/** OPAMP gain values. */
-typedef enum
-{
+typedef enum {
#if defined(_SILICON_LABS_32B_SERIES_0)
opaResSelDefault = DAC_OPA0MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */
opaResSelR2eq0_33R1 = DAC_OPA0MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */
@@ -352,8 +359,7 @@
} OPAMP_ResSel_TypeDef;
/** OPAMP resistor ladder input selector values. */
-typedef enum
-{
+typedef enum {
#if defined(_SILICON_LABS_32B_SERIES_0)
opaResInMuxDisable = DAC_OPA0MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */
opaResInMuxOpaIn = DAC_OPA0MUX_RESINMUX_OPA0INP, /**< Input from OPAx. */
@@ -374,8 +380,7 @@
} OPAMP_ResInMux_TypeDef;
#if defined(_SILICON_LABS_32B_SERIES_1)
-typedef enum
-{
+typedef enum {
opaPrsModeDefault = VDAC_OPA_CTRL_PRSMODE_DEFAULT, /**< Default value when PRS is not the trigger. */
opaPrsModePulsed = VDAC_OPA_CTRL_PRSMODE_PULSED, /**< PRS trigger is a pulse that starts the OPAMP
warmup sequence. The end of the warmup sequence
@@ -385,8 +390,7 @@
sequence is controlled by the edge of the pulse. */
} OPAMP_PrsMode_TypeDef;
-typedef enum
-{
+typedef enum {
opaPrsSelDefault = VDAC_OPA_CTRL_PRSSEL_DEFAULT, /**< Default value when PRS is not the trigger. */
opaPrsSelCh0 = VDAC_OPA_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0 triggers OPAMP. */
opaPrsSelCh1 = VDAC_OPA_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1 triggers OPAMP. */
@@ -396,28 +400,27 @@
opaPrsSelCh5 = VDAC_OPA_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5 triggers OPAMP. */
opaPrsSelCh6 = VDAC_OPA_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6 triggers OPAMP. */
opaPrsSelCh7 = VDAC_OPA_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7 triggers OPAMP. */
+#if defined(VDAC_OPA_CTRL_PRSSEL_PRSCH8)
opaPrsSelCh8 = VDAC_OPA_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8 triggers OPAMP. */
opaPrsSelCh9 = VDAC_OPA_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9 triggers OPAMP. */
opaPrsSelCh10 = VDAC_OPA_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10 triggers OPAMP. */
opaPrsSelCh11 = VDAC_OPA_CTRL_PRSSEL_PRSCH11, /**< PRS channel 11 triggers OPAMP. */
+#endif
} OPAMP_PrsSel_TypeDef;
-typedef enum
-{
+typedef enum {
opaPrsOutDefault = VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT, /**< Default value. */
opaPrsOutWarm = VDAC_OPA_CTRL_PRSOUTMODE_WARM, /**< Warm status available on PRS. */
opaPrsOutOutValid = VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID, /**< Outvalid status available on PRS. */
} OPAMP_PrsOut_TypeDef;
-typedef enum
-{
+typedef enum {
opaOutScaleDefault = VDAC_OPA_CTRL_OUTSCALE_DEFAULT, /**< Default OPAM output drive strength. */
opaOutScaleFull = VDAC_OPA_CTRL_OUTSCALE_FULL, /**< OPAMP uses full output drive strength. */
opaOutSacleHalf = VDAC_OPA_CTRL_OUTSCALE_HALF, /**< OPAMP uses half output drive strength. */
} OPAMP_OutScale_Typedef;
-typedef enum
-{
+typedef enum {
opaDrvStrDefault = VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT, /**< Default value. */
opaDrvStrLowerAccLowStr = (0 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Lower accuracy with low drive stregth. */
opaDrvStrLowAccLowStr = (1 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Low accuracy with low drive stregth. */
@@ -431,8 +434,7 @@
******************************************************************************/
/** OPAMP init structure. */
-typedef struct
-{
+typedef struct {
OPAMP_NegSel_TypeDef negSel; /**< Select input source for negative terminal. */
OPAMP_PosSel_TypeDef posSel; /**< Select input source for positive terminal. */
OPAMP_OutMode_TypeDef outMode; /**< Output terminal connection. */
@@ -523,826 +525,826 @@
#if defined(_SILICON_LABS_32B_SERIES_0)
/** Configuration of OPA0/1 in unity gain voltage follower mode. */
#define OPA_INIT_UNITY_GAIN \
-{ \
- opaNegSelUnityGain, /* Unity gain. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelDefault, /* Resistor ladder is not used. */ \
- opaResInMuxDisable, /* Resistor ladder disabled. */ \
- 0, /* No alternate outputs enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- false, /* No nextout output enabled. */ \
- false, /* Neg pad disabled. */ \
- true, /* Pos pad enabled, used as signal input. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelUnityGain, /* Unity gain. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelDefault, /* Resistor ladder is not used. */ \
+ opaResInMuxDisable, /* Resistor ladder disabled. */ \
+ 0, /* No alternate outputs enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ false, /* No nextout output enabled. */ \
+ false, /* Neg pad disabled. */ \
+ true, /* Pos pad enabled, used as signal input. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA2 in unity gain voltage follower mode. */
#define OPA_INIT_UNITY_GAIN_OPA2 \
-{ \
- opaNegSelUnityGain, /* Unity gain. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelDefault, /* Resistor ladder is not used. */ \
- opaResInMuxDisable, /* Resistor ladder disabled. */ \
- DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- false, /* No nextout output enabled. */ \
- false, /* Neg pad disabled. */ \
- true, /* Pos pad enabled, used as signal input. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelUnityGain, /* Unity gain. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelDefault, /* Resistor ladder is not used. */ \
+ opaResInMuxDisable, /* Resistor ladder disabled. */ \
+ DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ false, /* No nextout output enabled. */ \
+ false, /* Neg pad disabled. */ \
+ true, /* Pos pad enabled, used as signal input. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA0/1 in non-inverting amplifier mode. */
#define OPA_INIT_NON_INVERTING \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- 0, /* No alternate outputs enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- false, /* No nextout output enabled. */ \
- true, /* Neg pad enabled, used as signal ground. */ \
- true, /* Pos pad enabled, used as signal input. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ 0, /* No alternate outputs enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ false, /* No nextout output enabled. */ \
+ true, /* Neg pad enabled, used as signal ground. */ \
+ true, /* Pos pad enabled, used as signal input. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA2 in non-inverting amplifier mode. */
#define OPA_INIT_NON_INVERTING_OPA2 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- false, /* No nextout output enabled. */ \
- true, /* Neg pad enabled, used as signal ground. */ \
- true, /* Pos pad enabled, used as signal input. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ false, /* No nextout output enabled. */ \
+ true, /* Neg pad enabled, used as signal ground. */ \
+ true, /* Pos pad enabled, used as signal input. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA0/1 in inverting amplifier mode. */
#define OPA_INIT_INVERTING \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- 0, /* No alternate outputs enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- false, /* No nextout output enabled. */ \
- true, /* Neg pad enabled, used as signal input. */ \
- true, /* Pos pad enabled, used as signal ground. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ 0, /* No alternate outputs enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ false, /* No nextout output enabled. */ \
+ true, /* Neg pad enabled, used as signal input. */ \
+ true, /* Pos pad enabled, used as signal ground. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA2 in inverting amplifier mode. */
#define OPA_INIT_INVERTING_OPA2 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- false, /* No nextout output enabled. */ \
- true, /* Neg pad enabled, used as signal input. */ \
- true, /* Pos pad enabled, used as signal ground. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ false, /* No nextout output enabled. */ \
+ true, /* Neg pad enabled, used as signal input. */ \
+ true, /* Pos pad enabled, used as signal ground. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA0 in cascaded non-inverting amplifier mode. */
#define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeAll, /* Both main and alternate outputs. */ \
- opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- 0, /* No alternate outputs enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- true, /* Pass output to next stage (OPA1). */ \
- true, /* Neg pad enabled, used as signal ground. */ \
- true, /* Pos pad enabled, used as signal input. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeAll, /* Both main and alternate outputs. */ \
+ opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ 0, /* No alternate outputs enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ true, /* Pass output to next stage (OPA1). */ \
+ true, /* Neg pad enabled, used as signal ground. */ \
+ true, /* Pos pad enabled, used as signal input. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA1 in cascaded non-inverting amplifier mode. */
#define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelOpaIn, /* Pos input from OPA0 output. */ \
- opaOutModeAll, /* Both main and alternate outputs. */ \
- opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- 0, /* No alternate outputs enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- true, /* Pass output to next stage (OPA2). */ \
- true, /* Neg pad enabled, used as signal ground. */ \
- false, /* Pos pad disabled. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelOpaIn, /* Pos input from OPA0 output. */ \
+ opaOutModeAll, /* Both main and alternate outputs. */ \
+ opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ 0, /* No alternate outputs enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ true, /* Pass output to next stage (OPA2). */ \
+ true, /* Neg pad enabled, used as signal ground. */ \
+ false, /* Pos pad disabled. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA2 in cascaded non-inverting amplifier mode. */
#define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelOpaIn, /* Pos input from OPA1 output. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- false, /* No nextout output enabled. */ \
- true, /* Neg pad enabled, used as signal ground. */ \
- false, /* Pos pad disabled. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelOpaIn, /* Pos input from OPA1 output. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ false, /* No nextout output enabled. */ \
+ true, /* Neg pad enabled, used as signal ground. */ \
+ false, /* Pos pad disabled. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA0 in cascaded inverting amplifier mode. */
#define OPA_INIT_CASCADED_INVERTING_OPA0 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeAll, /* Both main and alternate outputs. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- 0, /* No alternate outputs enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- true, /* Pass output to next stage (OPA1). */ \
- true, /* Neg pad enabled, used as signal input. */ \
- true, /* Pos pad enabled, used as signal ground. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeAll, /* Both main and alternate outputs. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ 0, /* No alternate outputs enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ true, /* Pass output to next stage (OPA1). */ \
+ true, /* Neg pad enabled, used as signal input. */ \
+ true, /* Pos pad enabled, used as signal ground. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA1 in cascaded inverting amplifier mode. */
#define OPA_INIT_CASCADED_INVERTING_OPA1 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeAll, /* Both main and alternate outputs. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
- 0, /* No alternate outputs enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- true, /* Pass output to next stage (OPA2). */ \
- false, /* Neg pad disabled. */ \
- true, /* Pos pad enabled, used as signal ground. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeAll, /* Both main and alternate outputs. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
+ 0, /* No alternate outputs enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ true, /* Pass output to next stage (OPA2). */ \
+ false, /* Neg pad disabled. */ \
+ true, /* Pos pad enabled, used as signal ground. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA2 in cascaded inverting amplifier mode. */
#define OPA_INIT_CASCADED_INVERTING_OPA2 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
- DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- false, /* No nextout output enabled. */ \
- false, /* Neg pad disabled. */ \
- true, /* Pos pad enabled, used as signal ground. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
+ DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ false, /* No nextout output enabled. */ \
+ false, /* Neg pad disabled. */ \
+ true, /* Pos pad enabled, used as signal ground. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA0 in two-opamp differential driver mode. */
#define OPA_INIT_DIFF_DRIVER_OPA0 \
-{ \
- opaNegSelUnityGain, /* Unity gain. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeAll, /* Both main and alternate outputs. */ \
- opaResSelDefault, /* Resistor ladder is not used. */ \
- opaResInMuxDisable, /* Resistor ladder disabled. */ \
- 0, /* No alternate outputs enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- true, /* Pass output to next stage (OPA1). */ \
- false, /* Neg pad disabled. */ \
- true, /* Pos pad enabled, used as signal input. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelUnityGain, /* Unity gain. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeAll, /* Both main and alternate outputs. */ \
+ opaResSelDefault, /* Resistor ladder is not used. */ \
+ opaResInMuxDisable, /* Resistor ladder disabled. */ \
+ 0, /* No alternate outputs enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ true, /* Pass output to next stage (OPA1). */ \
+ false, /* Neg pad disabled. */ \
+ true, /* Pos pad enabled, used as signal input. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA1 in two-opamp differential driver mode. */
#define OPA_INIT_DIFF_DRIVER_OPA1 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
- 0, /* No alternate outputs enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- false, /* No nextout output enabled. */ \
- false, /* Neg pad disabled. */ \
- true, /* Pos pad enabled, used as signal ground. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
+ 0, /* No alternate outputs enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ false, /* No nextout output enabled. */ \
+ false, /* Neg pad disabled. */ \
+ true, /* Pos pad enabled, used as signal ground. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA0 in three-opamp differential receiver mode. */
#define OPA_INIT_DIFF_RECEIVER_OPA0 \
-{ \
- opaNegSelUnityGain, /* Unity gain. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeAll, /* Both main and alternate outputs. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- 0, /* No alternate outputs enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- true, /* Pass output to next stage (OPA2). */ \
- true, /* Neg pad enabled, used as signal ground. */ \
- true, /* Pos pad enabled, used as signal input. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelUnityGain, /* Unity gain. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeAll, /* Both main and alternate outputs. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ 0, /* No alternate outputs enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ true, /* Pass output to next stage (OPA2). */ \
+ true, /* Neg pad enabled, used as signal ground. */ \
+ true, /* Pos pad enabled, used as signal input. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA1 in three-opamp differential receiver mode. */
#define OPA_INIT_DIFF_RECEIVER_OPA1 \
-{ \
- opaNegSelUnityGain, /* Unity gain. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeAll, /* Both main and alternate outputs. */ \
- opaResSelDefault, /* Resistor ladder is not used. */ \
- opaResInMuxDisable, /* Disable resistor ladder. */ \
- 0, /* No alternate outputs enabled. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- true, /* Pass output to next stage (OPA2). */ \
- false, /* Neg pad disabled. */ \
- true, /* Pos pad enabled, used as signal input. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelUnityGain, /* Unity gain. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeAll, /* Both main and alternate outputs. */ \
+ opaResSelDefault, /* Resistor ladder is not used. */ \
+ opaResInMuxDisable, /* Disable resistor ladder. */ \
+ 0, /* No alternate outputs enabled. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ true, /* Pass output to next stage (OPA2). */ \
+ false, /* Neg pad disabled. */ \
+ true, /* Pos pad enabled, used as signal input. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA2 in three-opamp differential receiver mode. */
#define OPA_INIT_DIFF_RECEIVER_OPA2 \
-{ \
- opaNegSelResTap, /* Input from resistor ladder tap. */ \
- opaPosSelResTapOpa0, /* Input from OPA0 resistor ladder tap. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
- DAC_OPA0MUX_OUTPEN_OUT0, /* Enable alternate output 0. */ \
- _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
- _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
- false, /* No low pass filter on pos pad. */ \
- false, /* No low pass filter on neg pad. */ \
- false, /* No nextout output enabled. */ \
- false, /* Neg pad disabled. */ \
- false, /* Pos pad disabled. */ \
- false, /* No shorting of inputs. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use factory calibrated opamp offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Input from resistor ladder tap. */ \
+ opaPosSelResTapOpa0, /* Input from OPA0 resistor ladder tap. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
+ DAC_OPA0MUX_OUTPEN_OUT0, /* Enable alternate output 0. */ \
+ _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
+ _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
+ false, /* No low pass filter on pos pad. */ \
+ false, /* No low pass filter on neg pad. */ \
+ false, /* No nextout output enabled. */ \
+ false, /* Neg pad disabled. */ \
+ false, /* Pos pad disabled. */ \
+ false, /* No shorting of inputs. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use factory calibrated opamp offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
#elif defined(_SILICON_LABS_32B_SERIES_1)
/** Configuration of OPA in unity gain voltage follower mode. */
#define OPA_INIT_UNITY_GAIN \
-{ \
- opaNegSelUnityGain, /* Unity gain. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelDefault, /* Resistor ladder is not used. */ \
- opaResInMuxDisable, /* Resistor ladder disabled. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelUnityGain, /* Unity gain. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelDefault, /* Resistor ladder is not used. */ \
+ opaResInMuxDisable, /* Resistor ladder disabled. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA in non-inverting amplifier mode. */
#define OPA_INIT_NON_INVERTING \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA in inverting amplifier mode. */
#define OPA_INIT_INVERTING \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA0 in cascaded non-inverting amplifier mode. */
#define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA1 in cascaded non-inverting amplifier mode. */
#define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelOpaIn, /* Pos input from OPA0 output. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelOpaIn, /* Pos input from OPA0 output. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA2 in cascaded non-inverting amplifier mode. */
#define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelOpaIn, /* Pos input from OPA1 output. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelOpaIn, /* Pos input from OPA1 output. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA0 in cascaded inverting amplifier mode. */
#define OPA_INIT_CASCADED_INVERTING_OPA0 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA1 in cascaded inverting amplifier mode. */
#define OPA_INIT_CASCADED_INVERTING_OPA1 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA2 in cascaded inverting amplifier mode. */
#define OPA_INIT_CASCADED_INVERTING_OPA2 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA0 in two-opamp differential driver mode. */
#define OPA_INIT_DIFF_DRIVER_OPA0 \
-{ \
- opaNegSelUnityGain, /* Unity gain. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelDefault, /* Resistor ladder is not used. */ \
- opaResInMuxDisable, /* Resistor ladder disabled. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelUnityGain, /* Unity gain. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelDefault, /* Resistor ladder is not used. */ \
+ opaResInMuxDisable, /* Resistor ladder disabled. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA1 in two-opamp differential driver mode. */
#define OPA_INIT_DIFF_DRIVER_OPA1 \
-{ \
- opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA0 in three-opamp differential receiver mode. */
#define OPA_INIT_DIFF_RECEIVER_OPA0 \
-{ \
- opaNegSelUnityGain, /* Unity gain. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelUnityGain, /* Unity gain. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA1 in three-opamp differential receiver mode. */
#define OPA_INIT_DIFF_RECEIVER_OPA1 \
-{ \
- opaNegSelUnityGain, /* Unity gain. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelDefault, /* Resistor ladder is not used. */ \
- opaResInMuxDisable, /* Disable resistor ladder. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelUnityGain, /* Unity gain. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelDefault, /* Resistor ladder is not used. */ \
+ opaResInMuxDisable, /* Disable resistor ladder. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA2 in three-opamp differential receiver mode. */
#define OPA_INIT_DIFF_RECEIVER_OPA2 \
-{ \
- opaNegSelResTap, /* Input from resistor ladder tap. */ \
- opaPosSelResTap, /* Input from OPA0 resistor ladder tap. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Input from resistor ladder tap. */ \
+ opaPosSelResTap, /* Input from OPA0 resistor ladder tap. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA0 in two-opamp instrumentation amplifier mode. */
#define OPA_INIT_INSTR_AMP_OPA0 \
-{ \
- opaNegSelResTap, /* Input from resistor ladder tap. */ \
- opaPosSelPosPad, /* Pos input from pad. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelResTap, /* Input from resistor ladder tap. */ \
+ opaPosSelPosPad, /* Pos input from pad. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
/** Configuration of OPA1 in two-opamp instrumentation amplifier mode. */
#define OPA_INIT_INSTR_AMP_OPA1 \
-{ \
- opaNegSelNegPad, /* Neg input from pad. */ \
- opaPosSelResTap, /* Input from resistor ladder tap. */ \
- opaOutModeMain, /* Main output enabled. */ \
- opaResSelR2eqR1, /* R2 = R1 */ \
- opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \
- 0, /* No alternate outputs enabled. */ \
- opaDrvStrDefault, /* Default opamp operation mode. */ \
- false, /* Disable 3x gain setting. */ \
- false, /* Use full output drive strength. */ \
- false, /* Disable unity-gain bandwidth scaling. */ \
- false, /* Opamp triggered by OPAxEN. */ \
- opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
- opaPrsOutDefault, /* Default PRS output setting. */ \
- false, /* Bus mastering enabled on APORTX. */ \
- false, /* Bus mastering enabled on APORTY. */ \
- 3, /* 3us settle time with default DrvStr. */ \
- 0, /* No startup delay. */ \
- false, /* Rail-to-rail input enabled. */ \
- true, /* Use calibrated inverting offset. */ \
- 0, /* Opamp offset value (not used). */ \
- true, /* Use calibrated non-inverting offset. */ \
- 0 /* Opamp offset value (not used). */ \
-}
+ { \
+ opaNegSelNegPad, /* Neg input from pad. */ \
+ opaPosSelResTap, /* Input from resistor ladder tap. */ \
+ opaOutModeMain, /* Main output enabled. */ \
+ opaResSelR2eqR1, /* R2 = R1 */ \
+ opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \
+ 0, /* No alternate outputs enabled. */ \
+ opaDrvStrDefault, /* Default opamp operation mode. */ \
+ false, /* Disable 3x gain setting. */ \
+ false, /* Use full output drive strength. */ \
+ false, /* Disable unity-gain bandwidth scaling. */ \
+ false, /* Opamp triggered by OPAxEN. */ \
+ opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
+ opaPrsOutDefault, /* Default PRS output setting. */ \
+ false, /* Bus mastering enabled on APORTX. */ \
+ false, /* Bus mastering enabled on APORTY. */ \
+ 3, /* 3us settle time with default DrvStr. */ \
+ 0, /* No startup delay. */ \
+ false, /* Rail-to-rail input enabled. */ \
+ true, /* Use calibrated inverting offset. */ \
+ 0, /* Opamp offset value (not used). */ \
+ true, /* Use calibrated non-inverting offset. */ \
+ 0 /* Opamp offset value (not used). */ \
+ }
#endif /* defined(_SILICON_LABS_32B_SERIES_0) */
@@ -1366,5 +1368,5 @@
#endif
#endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1))
- || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */
+ || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */
#endif /* EM_OPAMP_H */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_pcnt.h
* @brief Pulse Counter (PCNT) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -72,14 +72,12 @@
#define PCNT2_CNT_SIZE (8) /* PCNT2 counter is 8 bits. */
#endif
-
/*******************************************************************************
******************************** ENUMS ************************************
******************************************************************************/
/** Mode selection. */
-typedef enum
-{
+typedef enum {
/** Disable pulse counter. */
pcntModeDisable = _PCNT_CTRL_MODE_DISABLE,
@@ -104,13 +102,11 @@
#endif
} PCNT_Mode_TypeDef;
-
#if defined(_PCNT_CTRL_CNTEV_MASK)
/** Counter event selection.
* Note: unshifted values are being used for enumeration because multiple
* configuration structure members use this type definition. */
-typedef enum
-{
+typedef enum {
/** Counts up on up-count and down on down-count events. */
pcntCntEventBoth = _PCNT_CTRL_CNTEV_BOTH,
@@ -125,11 +121,9 @@
} PCNT_CntEvent_TypeDef;
#endif
-
#if defined(_PCNT_INPUT_MASK)
/** PRS sources for @p s0PRS and @p s1PRS. */
-typedef enum
-{
+typedef enum {
pcntPRSCh0 = 0, /**< PRS channel 0. */
pcntPRSCh1 = 1, /**< PRS channel 1. */
pcntPRSCh2 = 2, /**< PRS channel 2. */
@@ -160,23 +154,19 @@
#endif
} PCNT_PRSSel_TypeDef;
-
/** PRS inputs of PCNT. */
-typedef enum
-{
+typedef enum {
pcntPRSInputS0 = 0, /** PRS input 0. */
pcntPRSInputS1 = 1 /** PRS input 1. */
} PCNT_PRSInput_TypeDef;
#endif
-
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** Init structure. */
-typedef struct
-{
+typedef struct {
/** Mode to operate in. */
PCNT_Mode_TypeDef mode;
@@ -235,37 +225,36 @@
#if !defined(PCNT_CTRL_HYST)
/** Default config for PCNT init structure. */
#define PCNT_INIT_DEFAULT \
-{ \
- pcntModeDisable, /* Disabled by default. */ \
- _PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \
- _PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \
- false, /* Use positive edge. */ \
- false, /* Up-counting. */ \
- false /* Filter disabled. */ \
-}
+ { \
+ pcntModeDisable, /* Disabled by default. */ \
+ _PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \
+ _PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \
+ false, /* Use positive edge. */ \
+ false, /* Up-counting. */ \
+ false /* Filter disabled. */ \
+ }
#else
/** Default config for PCNT init structure. */
#define PCNT_INIT_DEFAULT \
-{ \
- pcntModeDisable, /* Disabled by default. */ \
- _PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \
- _PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \
- false, /* Use positive edge. */ \
- false, /* Up-counting. */ \
- false, /* Filter disabled. */ \
- false, /* Hysteresis disabled. */ \
- true, /* Counter direction is given by CNTDIR. */ \
- pcntCntEventUp, /* Regular counter counts up on upcount events. */ \
- pcntCntEventNone, /* Auxiliary counter doesn't respond to events. */ \
- pcntPRSCh0, /* PRS channel 0 selected as S0IN. */ \
- pcntPRSCh0 /* PRS channel 0 selected as S1IN. */ \
-}
+ { \
+ pcntModeDisable, /* Disabled by default. */ \
+ _PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \
+ _PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \
+ false, /* Use positive edge. */ \
+ false, /* Up-counting. */ \
+ false, /* Filter disabled. */ \
+ false, /* Hysteresis disabled. */ \
+ true, /* Counter direction is given by CNTDIR. */ \
+ pcntCntEventUp, /* Regular counter counts up on upcount events. */ \
+ pcntCntEventNone, /* Auxiliary counter doesn't respond to events. */ \
+ pcntPRSCh0, /* PRS channel 0 selected as S0IN. */ \
+ pcntPRSCh0 /* PRS channel 0 selected as S1IN. */ \
+ }
#endif
#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)
/** Filter initialization structure */
-typedef struct
-{
+typedef struct {
/** Used only in OVSINGLE and OVSQUAD1X-4X modes. To use this, enable the filter through
* setting filter to true during PCNT_Init(). Filter length = (filtLen + 5) LFACLK cycles. */
uint8_t filtLen;
@@ -278,18 +267,17 @@
/** Default config for PCNT init structure. */
#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)
-#define PCNT_FILTER_DEFAULT \
-{ \
- 0, /* Default length is 5 LFACLK cycles */ \
- false /* No flutter removal */ \
-}
+#define PCNT_FILTER_DEFAULT \
+ { \
+ 0, /* Default length is 5 LFACLK cycles */ \
+ false /* No flutter removal */ \
+ }
#endif
#if defined(PCNT_CTRL_TCCMODE_DEFAULT)
/** Modes for Triggered Compare and Clear module */
-typedef enum
-{
+typedef enum {
/** Triggered compare and clear not enabled. */
tccModeDisabled = _PCNT_CTRL_TCCMODE_DISABLED,
@@ -301,8 +289,7 @@
} PCNT_TCCMode_TypeDef;
/** Prescaler values for LFA compare and clear events. Only has effect when TCC mode is LFA. */
-typedef enum
-{
+typedef enum {
/** Compare and clear event each LFA cycle. */
tccPrescDiv1 = _PCNT_CTRL_TCCPRESC_DIV1,
@@ -317,8 +304,7 @@
} PCNT_TCCPresc_Typedef;
/** Compare modes for TCC module */
-typedef enum
-{
+typedef enum {
/** Compare match if PCNT_CNT is less than, or equal to PCNT_TOP. */
tccCompLTOE = _PCNT_CTRL_TCCCOMP_LTOE,
@@ -331,8 +317,7 @@
} PCNT_TCCComp_Typedef;
/** TCC initialization structure */
-typedef struct
-{
+typedef struct {
/** Mode to operate in. */
PCNT_TCCMode_TypeDef mode;
@@ -355,15 +340,15 @@
bool prsGateEnable;
} PCNT_TCC_TypeDef;
-#define PCNT_TCC_DEFAULT \
-{ \
- tccModeDisabled, /* Disabled by default */ \
- tccPrescDiv1, /* Do not prescale LFA clock in LFA mode */ \
- tccCompLTOE, /* Clear when CNT <= TOP */ \
- pcntPRSCh0, /* Select PRS channel 0 as input to TCC */ \
- false, /* PRS polarity is rising edge, and gate when 1 */ \
- false /* Do not gate the PCNT counter input */ \
-}
+#define PCNT_TCC_DEFAULT \
+ { \
+ tccModeDisabled, /* Disabled by default */ \
+ tccPrescDiv1, /* Do not prescale LFA clock in LFA mode */ \
+ tccCompLTOE, /* Clear when CNT <= TOP */ \
+ pcntPRSCh0, /* Select PRS channel 0 as input to TCC */ \
+ false, /* PRS polarity is rising edge, and gate when 1 */ \
+ false /* Do not gate the PCNT counter input */ \
+ }
#endif
/* defined(PCNT_CTRL_TCCMODE_DEFAULT) */
@@ -547,7 +532,6 @@
{
uint32_t ien;
-
/* Store pcnt->IEN in temporary variable in order to define explicit order
* of volatile accesses. */
ien = pcnt->IEN;
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_prs.h
* @brief Peripheral Reflex System (PRS) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -55,8 +55,7 @@
******************************************************************************/
/** Edge detection type. */
-typedef enum
-{
+typedef enum {
prsEdgeOff = PRS_CH_CTRL_EDSEL_OFF, /**< Leave signal as is. */
prsEdgePos = PRS_CH_CTRL_EDSEL_POSEDGE, /**< Generate pules on positive edge. */
prsEdgeNeg = PRS_CH_CTRL_EDSEL_NEGEDGE, /**< Generate pules on negative edge. */
@@ -88,7 +87,6 @@
PRS->SWLEVEL = (PRS->SWLEVEL & ~mask) | (level & mask);
}
-
/***************************************************************************//**
* @brief
* Trigger a high pulse (one HFPERCLK) for one or more channels.
@@ -113,7 +111,7 @@
uint32_t signal,
PRS_Edge_TypeDef edge);
-#if defined( PRS_CH_CTRL_ASYNC )
+#if defined(PRS_CH_CTRL_ASYNC)
void PRS_SourceAsyncSignalSet(unsigned int ch,
uint32_t source,
uint32_t signal);
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_qspi.h Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,345 @@
+/***************************************************************************//**
+ * @file em_qspi.h
+ * @brief QSPI Octal-SPI Flash Controller API
+ * @version 5.3.3
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#ifndef EM_QSPI_H
+#define EM_QSPI_H
+
+#include "em_device.h"
+#if defined(QSPI_COUNT) && (QSPI_COUNT > 0)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "em_bus.h"
+#include <stdbool.h>
+
+/***************************************************************************//**
+ * @addtogroup emlib
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup QSPI
+ * @{
+ ******************************************************************************/
+
+/*******************************************************************************
+ ******************************* DEFINES ***********************************
+ ******************************************************************************/
+
+/*******************************************************************************
+ ******************************** ENUMS ************************************
+ ******************************************************************************/
+
+/** Transfer type. */
+typedef enum {
+ /** Single IO mode. DQ0 used for output and DQ1 as input. */
+ qspiTransferSingle = 0,
+
+ /** Dual I/O transfer. DQ0 and DQ1 are used as both inputs and outputs. */
+ qspiTransferDual = 1,
+
+ /** Quad I/O transfer. DQ0, DQ1, DQ2 and DQ3 are used as both inputs and outputs. */
+ qspiTransferQuad = 2,
+
+ /** Octal I/O transfer. DQ[7:0] are used as both inputs and outputs. */
+ qspiTransferOctal = 3
+} QSPI_TransferType_TypeDef;
+
+/*******************************************************************************
+ ******************************* STRUCTS ***********************************
+ ******************************************************************************/
+
+/** QSPI Device Read Instruction Configuration structure. */
+typedef struct {
+ /** Read opcode in non-xip mode. */
+ uint8_t opCode;
+
+ /** Number of dummy read clock cycles. */
+ uint8_t dummyCycles;
+
+ /** Transfer type used for address. */
+ QSPI_TransferType_TypeDef addrTransfer;
+
+ /** Transfer type used for data. */
+ QSPI_TransferType_TypeDef dataTransfer;
+
+ /** Transfer type used for instruction. */
+ QSPI_TransferType_TypeDef instTransfer;
+} QSPI_ReadConfig_TypeDef;
+
+/** Default read configuration structure. */
+#define QSPI_READCONFIG_DEFAULT \
+ { \
+ 0x03, /* 0x03 is the standard read opcode. */ \
+ 0, /* 0 dummy cycles. */ \
+ qspiTransferSingle, /* Single I/O mode. */ \
+ qspiTransferSingle, /* Single I/O mode. */ \
+ qspiTransferSingle, /* Single I/O mode. */ \
+ }
+
+/** QSPI Device Write Instruction Configuration structure. */
+typedef struct {
+ /** Write opcode. */
+ uint8_t opCode;
+
+ /** Number of dummy read clock cycles. */
+ uint8_t dummyCycles;
+
+ /** Transfer type used for address. */
+ QSPI_TransferType_TypeDef addrTransfer;
+
+ /** Transfer type used for data. */
+ QSPI_TransferType_TypeDef dataTransfer;
+
+ /**
+ * @brief
+ * Enable/disable automatic issuing of WEL (Write Enable Latch)
+ * command before a write operation.
+ *
+ * @details
+ * When writing to a flash device the write enable latch (WEL)
+ * within the flash device itself must be high before a write sequence can be
+ * issued. The QSPI peripheral can automatically issue the write enable latch
+ * command before triggering a write sequence. The command used for enabling
+ * the write enable latch is WREN (0x06) and is common between devices. */
+ bool autoWEL;
+} QSPI_WriteConfig_TypeDef;
+
+/** Default write configuration structure. */
+#define QSPI_WRITECONFIG_DEFAULT \
+ { \
+ 0x02, /* 0x02 is the standard write opcode. */ \
+ 0, /* 0 dummy cycles. */ \
+ qspiTransferSingle, /* Single I/O mode. */ \
+ qspiTransferSingle, /* Single I/O mode. */ \
+ true, /* Send WEL command automatically. */ \
+ }
+
+/** QSPI Device Delay Configuration structure. */
+typedef struct {
+ /** The minimal delay to keep the chip select line de-asserted between
+ * two transactions. */
+ uint8_t deassert;
+
+ /** Delay between one chip select being de-activated and the
+ * activation of another. */
+ uint8_t deviceSwitch;
+
+ /** Delay between last bit and chip select de-assert. */
+ uint8_t lastBit;
+
+ /** Delay chip select assert and first bit in a transaction. */
+ uint8_t firstBit;
+} QSPI_DelayConfig_TypeDef;
+
+/** Defines command to be executed using STIG mechanism. */
+typedef struct {
+ /** command op-code */
+ uint8_t cmdOpcode;
+ /** Number of Read Data Bytes */
+ uint16_t readDataSize;
+ /** Number of Address Bytes */
+ uint8_t addrSize;
+ /** Number of Write Data Bytes */
+ uint8_t writeDataSize;
+ /** Number of dummy cycles */
+ uint8_t dummyCycles;
+ /** Mode Bit Configuration register are sent following the address bytes. */
+ bool modeBitEnable;
+ /** flash command address */
+ uint32_t address;
+ /** buffer for read data */
+ void * readBuffer;
+ /** buffer with data to write */
+ void * writeBuffer;
+} QSPI_StigCmd_TypeDef;
+
+/** QSPI initialization structure. */
+typedef struct {
+ /** Enable/disable Quad SPI when initialization is completed. */
+ bool enable;
+
+ /**
+ * Master mode baude rate divisor. Values can be even numbers in the range
+ * [2-32] inclusive. */
+ uint8_t divisor;
+} QSPI_Init_TypeDef;
+
+/** Default configuration for QSPI_Init_TypeDef structure. */
+#define QSPI_INIT_DEFAULT \
+ { \
+ true, /* Enable Quad SPI. */ \
+ 32, /* Divide QSPI clock by 32. */ \
+ }
+
+/*******************************************************************************
+ ****************************** PROTOTYPES *********************************
+ ******************************************************************************/
+
+void QSPI_Init(QSPI_TypeDef * qspi, const QSPI_Init_TypeDef * init);
+void QSPI_ReadConfig(QSPI_TypeDef * qspi, const QSPI_ReadConfig_TypeDef * config);
+void QSPI_WriteConfig(QSPI_TypeDef * qspi, const QSPI_WriteConfig_TypeDef * config);
+void QSPI_ExecStigCmd(QSPI_TypeDef * qspi, const QSPI_StigCmd_TypeDef * stigCmd);
+
+/***************************************************************************//**
+ * @brief
+ * Wait for the QSPI to go into idle state.
+ *
+ * @param[in] qspi
+ * Pointer to QSPI peripheral register block.
+ ******************************************************************************/
+__STATIC_INLINE void QSPI_WaitForIdle(QSPI_TypeDef * qspi)
+{
+ while ((qspi->CONFIG & _QSPI_CONFIG_IDLE_MASK) == 0)
+ ;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get the fill level of the write partition of the QSPI internal SRAM.
+ *
+ * @param[in] qspi
+ * Pointer to QSPI peripheral register block.
+ *
+ * @return
+ * SRAM fill level of the write partition. The value is the number of 4 byte
+ * words in the write partition.
+ ******************************************************************************/
+__STATIC_INLINE uint16_t QSPI_GetWriteLevel(QSPI_TypeDef * qspi)
+{
+ return (qspi->SRAMFILL & _QSPI_SRAMFILL_SRAMFILLINDACWRITE_MASK)
+ >> _QSPI_SRAMFILL_SRAMFILLINDACWRITE_SHIFT;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get the fill level of the read partition of the QSPI internal SRAM.
+ *
+ * @param[in] qspi
+ * Pointer to QSPI peripheral register block.
+ *
+ * @return
+ * SRAM fill level of the read partition. The value is the number of 4 byte
+ * words in the read partition.
+ ******************************************************************************/
+__STATIC_INLINE uint16_t QSPI_GetReadLevel(QSPI_TypeDef * qspi)
+{
+ return (qspi->SRAMFILL & _QSPI_SRAMFILL_SRAMFILLINDACREAD_MASK)
+ >> _QSPI_SRAMFILL_SRAMFILLINDACREAD_SHIFT;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Enable/disable Quad SPI.
+ *
+ * @param[in] qspi
+ * Pointer to QSPI peripheral register block.
+ *
+ * @param[in] enable
+ * true to enable quad spi, false to disable quad spi.
+ ******************************************************************************/
+__STATIC_INLINE void QSPI_Enable(QSPI_TypeDef * qspi, bool enable)
+{
+ BUS_RegBitWrite(&qspi->CONFIG, _QSPI_CONFIG_ENBSPI_SHIFT, enable ? 1 : 0);
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get the current interrupt flags.
+ *
+ * @param[in] qspi
+ * Pointer to QSPI peripheral register block.
+ *
+ * @return
+ * This functions returns the current interrupt flags that are set.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t QSPI_IntGet(QSPI_TypeDef * qspi)
+{
+ return qspi->IRQSTATUS;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Clear interrupt flags
+ *
+ * @param[in] qspi
+ * Pointer to QSPI peripheral register block.
+ *
+ * @param[in] flags
+ * The interrupt flags to clear.
+ ******************************************************************************/
+__STATIC_INLINE void QSPI_IntClear(QSPI_TypeDef * qspi, uint32_t flags)
+{
+ qspi->IRQSTATUS = flags;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Enable interrupts.
+ *
+ * @param[in] qspi
+ * Pointer to QSPI peripheral register block.
+ *
+ * @param[in] flags
+ * The interrupt flags to enable.
+ ******************************************************************************/
+__STATIC_INLINE void QSPI_IntEnable(QSPI_TypeDef * qspi, uint32_t flags)
+{
+ qspi->IRQMASK = flags & (~_QSPI_IRQMASK_MASK);
+}
+
+/***************************************************************************//**
+ * @brief
+ * Disable interrupts.
+ *
+ * @param[in] qspi
+ * Pointer to QSPI peripheral register block.
+ *
+ * @param[in] flags
+ * The interrupt flags to disable.
+ ******************************************************************************/
+__STATIC_INLINE void QSPI_IntDisable(QSPI_TypeDef * qspi, uint32_t flags)
+{
+ qspi->IRQMASK = ~flags & (~_QSPI_IRQMASK_MASK);
+}
+
+/** @} (end addtogroup QSPI) */
+/** @} (end addtogroup emlib) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* defined(QSPI_COUNT) && (QSPI_COUNT > 0) */
+#endif /* EM_QSPI_H */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_ramfunc.h
* @brief RAM code support.
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -37,6 +37,7 @@
extern "C" {
#endif
+/* *INDENT-OFF* */
/***************************************************************************//**
* @addtogroup emlib
* @{
@@ -61,6 +62,11 @@
guarantee no calls to standard libraries with GCC.
Read more at https://gcc.gnu.org/onlinedocs/gcc-5.3.0/gcc/Standards.html
+ @warning
+ Keil/ARM uVision users must add a section named "ram_code" in their linker
+ scatter file. This section must be in RAM memory. Look in the MCU SDK for
+ example scatter files (ram_code.sct).
+
@n @section ramfunc_usage Usage
In your .h file:
@@ -87,10 +93,10 @@
SL_RAMFUNC_DEFINITION_END
@endverbatim
+ ******************************************************************************/
+/* *INDENT-ON* */
- ******************************************************************************/
-
- /*******************************************************************************
+/*******************************************************************************
****************************** DEFINES ***********************************
******************************************************************************/
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_rmu.h
* @brief Reset Management Unit (RMU) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -58,8 +58,7 @@
******************************************************************************/
/** RMU reset modes */
-typedef enum
-{
+typedef enum {
#if defined(_RMU_CTRL_PINRMODE_MASK)
rmuResetModeDisabled = _RMU_CTRL_PINRMODE_DISABLED,
rmuResetModeLimited = _RMU_CTRL_PINRMODE_LIMITED,
@@ -72,8 +71,7 @@
} RMU_ResetMode_TypeDef;
/** RMU controlled peripheral reset control and reset source control */
-typedef enum
-{
+typedef enum {
#if defined(RMU_CTRL_BURSTEN)
rmuResetBU = _RMU_CTRL_BURSTEN_MASK, /**< Reset control over Backup Power domain select */
#endif
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_rtc.h
* @brief Real Time Counter (RTC) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -57,8 +57,7 @@
******************************************************************************/
/** RTC initialization structure. */
-typedef struct
-{
+typedef struct {
bool enable; /**< Start counting when init completed. */
bool debugRun; /**< Counter shall keep running during debug halt. */
bool comp0Top; /**< Use compare register 0 as max count value. */
@@ -66,12 +65,11 @@
/** Suggested default config for RTC init structure. */
#define RTC_INIT_DEFAULT \
-{ \
- true, /* Start counting when init done */ \
- false, /* Disable updating during debug halt */ \
- true /* Restart counting from 0 when reaching COMP0 */ \
-}
-
+ { \
+ true, /* Start counting when init done */ \
+ false, /* Disable updating during debug halt */ \
+ true /* Restart counting from 0 when reaching COMP0 */ \
+ }
/*******************************************************************************
***************************** PROTOTYPES **********************************
@@ -108,7 +106,9 @@
void RTC_CounterReset(void);
void RTC_Enable(bool enable);
+#if defined(_RTC_FREEZE_MASK)
void RTC_FreezeEnable(bool enable);
+#endif
void RTC_Init(const RTC_Init_TypeDef *init);
/***************************************************************************//**
@@ -125,7 +125,6 @@
RTC->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more RTC interrupts.
@@ -140,7 +139,6 @@
RTC->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more RTC interrupts.
@@ -160,7 +158,6 @@
RTC->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending RTC interrupt flags.
@@ -177,7 +174,6 @@
return RTC->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending RTC interrupt flags.
@@ -200,7 +196,6 @@
return RTC->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending RTC interrupts from SW.
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file
* @brief Real Time Counter (RTCC) peripheral API.
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -34,7 +34,7 @@
#define EM_RTCC_H
#include "em_device.h"
-#if defined( RTCC_COUNT ) && ( RTCC_COUNT == 1 )
+#if defined(RTCC_COUNT) && (RTCC_COUNT == 1)
#include <stdbool.h>
#include "em_assert.h"
@@ -54,8 +54,8 @@
******************************************************************************/
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \
- || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \
+ || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
/* Enable fix for errata "RTCC_E203 - Potential Stability Issue with RTCC
* Registers". */
#define ERRATA_FIX_RTCC_E203
@@ -73,19 +73,17 @@
******************************************************************************/
/** Operational mode of the counter. */
-typedef enum
-{
+typedef enum {
/** Normal counter mode. The counter is incremented by 1 for each tick. */
- rtccCntModeNormal = _RTCC_CTRL_CNTTICK_PRESC,
+ rtccCntModeNormal = _RTCC_CTRL_CNTMODE_NORMAL,
/** Calendar mode. Refer to the RTCC chapter of the Reference Manual for more
* details on the calendar mode. */
- rtccCntModeCalendar = _RTCC_CTRL_CNTTICK_CCV0MATCH
+ rtccCntModeCalendar = _RTCC_CTRL_CNTMODE_CALENDAR
} RTCC_CntMode_TypeDef;
/** Counter prescaler selection. */
-typedef enum
-{
+typedef enum {
rtccCntPresc_1 = _RTCC_CTRL_CNTPRESC_DIV1, /**< Divide clock by 1. */
rtccCntPresc_2 = _RTCC_CTRL_CNTPRESC_DIV2, /**< Divide clock by 2. */
rtccCntPresc_4 = _RTCC_CTRL_CNTPRESC_DIV4, /**< Divide clock by 4. */
@@ -104,10 +102,8 @@
rtccCntPresc_32768 = _RTCC_CTRL_CNTPRESC_DIV32768 /**< Divide clock by 32768. */
} RTCC_CntPresc_TypeDef;
-
/** Prescaler mode of the RTCC counter. */
-typedef enum
-{
+typedef enum {
/** CNT register ticks according to the prescaler value. */
rtccCntTickPresc = _RTCC_CTRL_CNTTICK_PRESC,
@@ -116,28 +112,23 @@
rtccCntTickCCV0Match = _RTCC_CTRL_CNTTICK_CCV0MATCH
} RTCC_PrescMode_TypeDef;
-
/** Capture/Compare channel mode. */
-typedef enum
-{
+typedef enum {
rtccCapComChModeOff = _RTCC_CC_CTRL_MODE_OFF, /**< Capture/Compare channel turned off. */
rtccCapComChModeCapture = _RTCC_CC_CTRL_MODE_INPUTCAPTURE, /**< Capture mode. */
rtccCapComChModeCompare = _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Compare mode. */
} RTCC_CapComChMode_TypeDef;
/** Compare match output action mode. */
-typedef enum
-{
+typedef enum {
rtccCompMatchOutActionPulse = _RTCC_CC_CTRL_CMOA_PULSE, /**< Generate a pulse. */
rtccCompMatchOutActionToggle = _RTCC_CC_CTRL_CMOA_TOGGLE, /**< Toggle output. */
rtccCompMatchOutActionClear = _RTCC_CC_CTRL_CMOA_CLEAR, /**< Clear output. */
rtccCompMatchOutActionSet = _RTCC_CC_CTRL_CMOA_SET /**< Set output. */
} RTCC_CompMatchOutAction_TypeDef;
-
/** PRS input sources. */
-typedef enum
-{
+typedef enum {
rtccPRSCh0 = _RTCC_CC_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
rtccPRSCh1 = _RTCC_CC_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
rtccPRSCh2 = _RTCC_CC_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
@@ -146,26 +137,30 @@
rtccPRSCh5 = _RTCC_CC_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5. */
rtccPRSCh6 = _RTCC_CC_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6. */
rtccPRSCh7 = _RTCC_CC_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7. */
+#if defined(_RTCC_CC_CTRL_PRSSEL_PRSCH8)
rtccPRSCh8 = _RTCC_CC_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8. */
+#endif
+#if defined(_RTCC_CC_CTRL_PRSSEL_PRSCH9)
rtccPRSCh9 = _RTCC_CC_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9. */
+#endif
+#if defined(_RTCC_CC_CTRL_PRSSEL_PRSCH10)
rtccPRSCh10 = _RTCC_CC_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10. */
+#endif
+#if defined(_RTCC_CC_CTRL_PRSSEL_PRSCH11)
rtccPRSCh11 = _RTCC_CC_CTRL_PRSSEL_PRSCH11 /**< PRS channel 11. */
+#endif
} RTCC_PRSSel_TypeDef;
-
/** Input edge select. */
-typedef enum
-{
+typedef enum {
rtccInEdgeRising = _RTCC_CC_CTRL_ICEDGE_RISING, /**< Rising edges detected. */
rtccInEdgeFalling = _RTCC_CC_CTRL_ICEDGE_FALLING, /**< Falling edges detected. */
rtccInEdgeBoth = _RTCC_CC_CTRL_ICEDGE_BOTH, /**< Both edges detected. */
rtccInEdgeNone = _RTCC_CC_CTRL_ICEDGE_NONE /**< No edge detection, signal is left as is. */
} RTCC_InEdgeSel_TypeDef;
-
/** Capture/Compare channel compare mode. */
-typedef enum
-{
+typedef enum {
/** CCVx is compared with the CNT register. */
rtccCompBaseCnt = _RTCC_CC_CTRL_COMPBASE_CNT,
@@ -173,9 +168,8 @@
rtccCompBasePreCnt = _RTCC_CC_CTRL_COMPBASE_PRECNT
} RTCC_CompBase_TypeDef;
- /** Day compare mode. */
-typedef enum
-{
+/** Day compare mode. */
+typedef enum {
rtccDayCompareModeMonth = _RTCC_CC_CTRL_DAYCC_MONTH, /**< Day of month is selected for Capture/Compare. */
rtccDayCompareModeWeek = _RTCC_CC_CTRL_DAYCC_WEEK /**< Day of week is selected for Capture/Compare. */
} RTCC_DayCompareMode_TypeDef;
@@ -185,8 +179,7 @@
******************************************************************************/
/** RTCC initialization structure. */
-typedef struct
-{
+typedef struct {
/** Enable/disable counting when initialization is completed. */
bool enable;
@@ -224,10 +217,8 @@
bool disLeapYearCorr;
} RTCC_Init_TypeDef;
-
/** RTCC capture/compare channel configuration structure. */
-typedef struct
-{
+typedef struct {
/** Select the mode of the Capture/Compare channel. */
RTCC_CapComChMode_TypeDef chMode;
@@ -251,7 +242,6 @@
RTCC_DayCompareMode_TypeDef dayCompMode;
} RTCC_CCChConf_TypeDef;
-
/*******************************************************************************
******************************* DEFINES ***********************************
******************************************************************************/
@@ -259,59 +249,59 @@
/** Default RTCC init structure. */
#if defined(_RTCC_CTRL_BUMODETSEN_MASK)
#define RTCC_INIT_DEFAULT \
-{ \
- true, /* Start counting when init done. */ \
- false, /* Disable RTCC during debug halt. */ \
- false, /* Disable precounter wrap on ch. 0 CCV value. */ \
- false, /* Disable counter wrap on ch. 1 CCV value. */ \
- rtccCntPresc_32, /* 977 us per tick. */ \
- rtccCntTickPresc, /* Counter increments according to prescaler value. */ \
- false, /* No RTCC storage on backup mode entry. */ \
- false, /* No RTCC oscillator failure detection. */ \
- rtccCntModeNormal, /* Normal RTCC mode. */ \
- false, /* No leap year correction. */ \
-}
+ { \
+ true, /* Start counting when init done. */ \
+ false, /* Disable RTCC during debug halt. */ \
+ false, /* Disable precounter wrap on ch. 0 CCV value. */ \
+ false, /* Disable counter wrap on ch. 1 CCV value. */ \
+ rtccCntPresc_32, /* 977 us per tick. */ \
+ rtccCntTickPresc, /* Counter increments according to prescaler value.*/ \
+ false, /* No RTCC storage on backup mode entry. */ \
+ false, /* No RTCC oscillator failure detection. */ \
+ rtccCntModeNormal, /* Normal RTCC mode. */ \
+ false, /* No leap year correction. */ \
+ }
#else
#define RTCC_INIT_DEFAULT \
-{ \
- true, /* Start counting when init done. */ \
- false, /* Disable RTCC during debug halt. */ \
- false, /* Disable precounter wrap on ch. 0 CCV value. */ \
- false, /* Disable counter wrap on ch. 1 CCV value. */ \
- rtccCntPresc_32, /* 977 us per tick. */ \
- rtccCntTickPresc, /* Counter increments according to prescaler value. */ \
- false, /* No RTCC oscillator failure detection. */ \
- rtccCntModeNormal, /* Normal RTCC mode. */ \
- false, /* No leap year correction. */ \
-}
+ { \
+ true, /* Start counting when init done. */ \
+ false, /* Disable RTCC during debug halt. */ \
+ false, /* Disable precounter wrap on ch. 0 CCV value. */ \
+ false, /* Disable counter wrap on ch. 1 CCV value. */ \
+ rtccCntPresc_32, /* 977 us per tick. */ \
+ rtccCntTickPresc, /* Counter increments according to prescaler value.*/ \
+ false, /* No RTCC oscillator failure detection. */ \
+ rtccCntModeNormal, /* Normal RTCC mode. */ \
+ false, /* No leap year correction. */ \
+ }
#endif
/** Default RTCC channel output compare init structure. */
-#define RTCC_CH_INIT_COMPARE_DEFAULT \
-{ \
- rtccCapComChModeCompare, /* Select output compare mode. */ \
- rtccCompMatchOutActionPulse, /* Create pulse on compare match. */ \
- rtccPRSCh0, /* PRS channel 0 (not used). */ \
- rtccInEdgeNone, /* No edge detection. */ \
- rtccCompBaseCnt, /* Counter comparison base. */ \
- 0, /* No compare mask bits set. */ \
- rtccDayCompareModeMonth /* Don't care */ \
-}
+#define RTCC_CH_INIT_COMPARE_DEFAULT \
+ { \
+ rtccCapComChModeCompare, /* Select output compare mode. */ \
+ rtccCompMatchOutActionPulse, /* Create pulse on compare match.*/ \
+ rtccPRSCh0, /* PRS channel 0 (not used). */ \
+ rtccInEdgeNone, /* No edge detection. */ \
+ rtccCompBaseCnt, /* Counter comparison base. */ \
+ 0, /* No compare mask bits set. */ \
+ rtccDayCompareModeMonth /* Don't care */ \
+ }
/** Default RTCC channel input capture init structure. */
-#define RTCC_CH_INIT_CAPTURE_DEFAULT \
-{ \
- rtccCapComChModeCapture, /* Select input capture mode. */ \
- rtccCompMatchOutActionPulse, /* Create pulse on capture. */ \
- rtccPRSCh0, /* PRS channel 0. */ \
- rtccInEdgeRising, /* Rising edge detection. */ \
- rtccCompBaseCnt, /* Don't care. */ \
- 0, /* Don't care. */ \
- rtccDayCompareModeMonth /* Don't care */ \
-}
+#define RTCC_CH_INIT_CAPTURE_DEFAULT \
+ { \
+ rtccCapComChModeCapture, /* Select input capture mode. */ \
+ rtccCompMatchOutActionPulse, /* Create pulse on capture. */ \
+ rtccPRSCh0, /* PRS channel 0. */ \
+ rtccInEdgeRising, /* Rising edge detection. */ \
+ rtccCompBaseCnt, /* Don't care. */ \
+ 0, /* Don't care. */ \
+ rtccDayCompareModeMonth /* Don't care */ \
+ }
/** Validation of valid RTCC channel for assert statements. */
-#define RTCC_CH_VALID( ch ) ( ( ch ) < 3 )
+#define RTCC_CH_VALID(ch) ( (ch) < 3)
/*******************************************************************************
***************************** PROTOTYPES **********************************
@@ -327,10 +317,10 @@
* @return
* Capture/compare register value.
******************************************************************************/
-__STATIC_INLINE uint32_t RTCC_ChannelCCVGet( int ch )
+__STATIC_INLINE uint32_t RTCC_ChannelCCVGet(int ch)
{
- EFM_ASSERT( RTCC_CH_VALID( ch ) );
- return RTCC->CC[ ch ].CCV;
+ EFM_ASSERT(RTCC_CH_VALID(ch) );
+ return RTCC->CC[ch].CCV;
}
/***************************************************************************//**
@@ -343,10 +333,10 @@
* @param[in] value
* CCV value.
******************************************************************************/
-__STATIC_INLINE void RTCC_ChannelCCVSet( int ch, uint32_t value )
+__STATIC_INLINE void RTCC_ChannelCCVSet(int ch, uint32_t value)
{
- EFM_ASSERT( RTCC_CH_VALID( ch ) );
- RTCC->CC[ ch ].CCV = value;
+ EFM_ASSERT(RTCC_CH_VALID(ch) );
+ RTCC->CC[ch].CCV = value;
}
/***************************************************************************//**
@@ -359,10 +349,10 @@
* @return
* DATE register value.
******************************************************************************/
-__STATIC_INLINE uint32_t RTCC_ChannelDateGet( int ch )
+__STATIC_INLINE uint32_t RTCC_ChannelDateGet(int ch)
{
- EFM_ASSERT( RTCC_CH_VALID( ch ) );
- return RTCC->CC[ ch ].DATE;
+ EFM_ASSERT(RTCC_CH_VALID(ch) );
+ return RTCC->CC[ch].DATE;
}
/***************************************************************************//**
@@ -375,13 +365,13 @@
* @param[in] date
* DATE value.
******************************************************************************/
-__STATIC_INLINE void RTCC_ChannelDateSet( int ch, uint32_t date )
+__STATIC_INLINE void RTCC_ChannelDateSet(int ch, uint32_t date)
{
- EFM_ASSERT( RTCC_CH_VALID( ch ) );
- RTCC->CC[ ch ].DATE = date;
+ EFM_ASSERT(RTCC_CH_VALID(ch) );
+ RTCC->CC[ch].DATE = date;
}
-void RTCC_ChannelInit( int ch, RTCC_CCChConf_TypeDef const *confPtr );
+void RTCC_ChannelInit(int ch, RTCC_CCChConf_TypeDef const *confPtr);
/***************************************************************************//**
* @brief
@@ -393,10 +383,10 @@
* @return
* TIME register value.
******************************************************************************/
-__STATIC_INLINE uint32_t RTCC_ChannelTimeGet( int ch )
+__STATIC_INLINE uint32_t RTCC_ChannelTimeGet(int ch)
{
- EFM_ASSERT( RTCC_CH_VALID( ch ) );
- return RTCC->CC[ ch ].TIME;
+ EFM_ASSERT(RTCC_CH_VALID(ch) );
+ return RTCC->CC[ch].TIME;
}
/***************************************************************************//**
@@ -409,10 +399,10 @@
* @param[in] time
* TIME value.
******************************************************************************/
-__STATIC_INLINE void RTCC_ChannelTimeSet( int ch, uint32_t time )
+__STATIC_INLINE void RTCC_ChannelTimeSet(int ch, uint32_t time)
{
- EFM_ASSERT( RTCC_CH_VALID( ch ) );
- RTCC->CC[ ch ].TIME = time;
+ EFM_ASSERT(RTCC_CH_VALID(ch) );
+ RTCC->CC[ch].TIME = time;
}
/***************************************************************************//**
@@ -422,7 +412,7 @@
* @return
* CNT/PRECNT register value.
******************************************************************************/
-__STATIC_INLINE uint32_t RTCC_CombinedCounterGet( void )
+__STATIC_INLINE uint32_t RTCC_CombinedCounterGet(void)
{
return RTCC->COMBCNT;
}
@@ -434,7 +424,7 @@
* @return
* Current RTCC counter value.
******************************************************************************/
-__STATIC_INLINE uint32_t RTCC_CounterGet( void )
+__STATIC_INLINE uint32_t RTCC_CounterGet(void)
{
return RTCC->CNT;
}
@@ -446,7 +436,7 @@
* @param[in] value
* CNT value.
******************************************************************************/
-__STATIC_INLINE void RTCC_CounterSet( uint32_t value )
+__STATIC_INLINE void RTCC_CounterSet(uint32_t value)
{
RTCC->CNT = value;
}
@@ -458,7 +448,7 @@
* @return
* Current DATE register value.
******************************************************************************/
-__STATIC_INLINE uint32_t RTCC_DateGet( void )
+__STATIC_INLINE uint32_t RTCC_DateGet(void)
{
return RTCC->DATE;
}
@@ -470,7 +460,7 @@
* @param[in] date
* DATE value.
******************************************************************************/
-__STATIC_INLINE void RTCC_DateSet( uint32_t date )
+__STATIC_INLINE void RTCC_DateSet(uint32_t date)
{
RTCC->DATE = date;
}
@@ -482,21 +472,18 @@
* @param[in] enable
* True to enable EM4 wakeup, false to disable.
******************************************************************************/
-__STATIC_INLINE void RTCC_EM4WakeupEnable( bool enable )
+__STATIC_INLINE void RTCC_EM4WakeupEnable(bool enable)
{
- if ( enable )
- {
+ if ( enable ) {
RTCC->EM4WUEN = RTCC_EM4WUEN_EM4WU;
- }
- else
- {
+ } else {
RTCC->EM4WUEN = 0;
}
}
-void RTCC_Enable( bool enable );
+void RTCC_Enable(bool enable);
-void RTCC_Init( const RTCC_Init_TypeDef *init );
+void RTCC_Init(const RTCC_Init_TypeDef *init);
/***************************************************************************//**
* @brief
@@ -506,7 +493,7 @@
* RTCC interrupt sources to clear. Use a set of interrupt flags OR-ed
* together to clear multiple interrupt sources.
******************************************************************************/
-__STATIC_INLINE void RTCC_IntClear( uint32_t flags )
+__STATIC_INLINE void RTCC_IntClear(uint32_t flags)
{
RTCC->IFC = flags;
}
@@ -519,7 +506,7 @@
* RTCC interrupt sources to disable. Use a set of interrupt flags OR-ed
* together to disable multiple interrupt.
******************************************************************************/
-__STATIC_INLINE void RTCC_IntDisable( uint32_t flags )
+__STATIC_INLINE void RTCC_IntDisable(uint32_t flags)
{
RTCC->IEN &= ~flags;
}
@@ -537,7 +524,7 @@
* RTCC interrupt sources to enable. Use a set of interrupt flags OR-ed
* together to set multiple interrupt.
******************************************************************************/
-__STATIC_INLINE void RTCC_IntEnable( uint32_t flags )
+__STATIC_INLINE void RTCC_IntEnable(uint32_t flags)
{
RTCC->IEN |= flags;
}
@@ -553,7 +540,7 @@
* Pending RTCC interrupt sources. Returns a set of interrupt flags OR-ed
* together for the interrupt sources set.
******************************************************************************/
-__STATIC_INLINE uint32_t RTCC_IntGet( void )
+__STATIC_INLINE uint32_t RTCC_IntGet(void)
{
return RTCC->IF;
}
@@ -569,7 +556,7 @@
* Pending and enabled RTCC interrupt sources. Returns a set of interrupt
* flags OR-ed together for the interrupt sources set.
******************************************************************************/
-__STATIC_INLINE uint32_t RTCC_IntGetEnabled( void )
+__STATIC_INLINE uint32_t RTCC_IntGetEnabled(void)
{
uint32_t tmp;
@@ -587,7 +574,7 @@
* RTCC interrupt sources to set to pending. Use a set of interrupt flags
* (RTCC_IFS_nnn).
******************************************************************************/
-__STATIC_INLINE void RTCC_IntSet( uint32_t flags )
+__STATIC_INLINE void RTCC_IntSet(uint32_t flags)
{
RTCC->IFS = flags;
}
@@ -601,15 +588,14 @@
* RTCC_TIME, RTCC_DATE, RTCC_IEN, RTCC_POWERDOWN and RTCC_CCx_XXX registers
* can not be written to.
******************************************************************************/
-__STATIC_INLINE void RTCC_Lock( void )
+__STATIC_INLINE void RTCC_Lock(void)
{
#if defined(ERRATA_FIX_RTCC_E203)
/* RTCC_E203 - Potential Stability Issue with RTCC Registers
* RTCC_LOCK register must be modified while RTCC clock is disabled. */
uint32_t lfeReg = CMU->LFECLKEN0;
bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED);
- if (cmuLocked)
- {
+ if (cmuLocked) {
CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
}
CMU->LFECLKEN0 = 0x0;
@@ -618,8 +604,7 @@
#if defined(ERRATA_FIX_RTCC_E203)
/* Restore clock state after RTCC_E203 fix. */
CMU->LFECLKEN0 = lfeReg;
- if (cmuLocked)
- {
+ if (cmuLocked) {
CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
}
#endif
@@ -632,7 +617,7 @@
* @return
* Current RTCC pre-counter value.
******************************************************************************/
-__STATIC_INLINE uint32_t RTCC_PreCounterGet( void )
+__STATIC_INLINE uint32_t RTCC_PreCounterGet(void)
{
return RTCC->PRECNT;
}
@@ -644,12 +629,12 @@
* @param[in] preCntVal
* RTCC pre-counter value to be set.
******************************************************************************/
-__STATIC_INLINE void RTCC_PreCounterSet( uint32_t preCntVal )
+__STATIC_INLINE void RTCC_PreCounterSet(uint32_t preCntVal)
{
RTCC->PRECNT = preCntVal;
}
-void RTCC_Reset( void );
+void RTCC_Reset(void);
/***************************************************************************//**
* @brief
@@ -658,7 +643,7 @@
* @note
* Once retention ram is powered down, it cannot be powered up again.
******************************************************************************/
-__STATIC_INLINE void RTCC_RetentionRamPowerDown( void )
+__STATIC_INLINE void RTCC_RetentionRamPowerDown(void)
{
#if !defined(ERRATA_FIX_RTCC_E204)
/* Devices that are affected by RTCC_E204 should always keep the RTCC
@@ -667,7 +652,7 @@
#endif
}
-void RTCC_StatusClear( void );
+void RTCC_StatusClear(void);
/***************************************************************************//**
* @brief
@@ -676,10 +661,9 @@
* @return
* Current STATUS register value.
******************************************************************************/
-__STATIC_INLINE uint32_t RTCC_StatusGet( void )
+__STATIC_INLINE uint32_t RTCC_StatusGet(void)
{
- while ( RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD )
- {
+ while ( RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD ) {
// Wait for syncronization.
}
return RTCC->STATUS;
@@ -692,7 +676,7 @@
* @return
* Current TIME register value.
******************************************************************************/
-__STATIC_INLINE uint32_t RTCC_TimeGet( void )
+__STATIC_INLINE uint32_t RTCC_TimeGet(void)
{
return RTCC->TIME;
}
@@ -704,7 +688,7 @@
* @param[in] time
* TIME value.
******************************************************************************/
-__STATIC_INLINE void RTCC_TimeSet( uint32_t time )
+__STATIC_INLINE void RTCC_TimeSet(uint32_t time)
{
RTCC->TIME = time;
}
@@ -718,15 +702,14 @@
* RTCC_TIME, RTCC_DATE, RTCC_IEN, RTCC_POWERDOWN and RTCC_CCx_XXX registers
* can not be written to.
******************************************************************************/
-__STATIC_INLINE void RTCC_Unlock( void )
+__STATIC_INLINE void RTCC_Unlock(void)
{
#if defined(ERRATA_FIX_RTCC_E203)
/* RTCC_E203 - Potential Stability Issue with RTCC Registers
* RTCC_LOCK register must be modified while RTCC clock is disabled. */
uint32_t lfeReg = CMU->LFECLKEN0;
bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED);
- if (cmuLocked)
- {
+ if (cmuLocked) {
CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
}
CMU->LFECLKEN0 = 0x0;
@@ -735,8 +718,7 @@
#if defined(ERRATA_FIX_RTCC_E203)
/* Restore clock state after RTCC_E203 fix. */
CMU->LFECLKEN0 = lfeReg;
- if (cmuLocked)
- {
+ if (cmuLocked) {
CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
}
#endif
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_smu.h
* @brief Security Management Unit (SMU) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -77,7 +77,6 @@
/** SMU peripheral identifiers. */
typedef enum {
-
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
@@ -127,8 +126,12 @@
smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1 */
+#if defined(_SMU_PPUPATD0_CSEN_SHIFT)
smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
+#endif
+#if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
+#endif
smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
@@ -136,7 +139,9 @@
smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
+#if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
+#endif
smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */
smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
@@ -156,6 +161,167 @@
smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
+#if defined(_SMU_PPUPATD0_ACMP0_SHIFT)
+ smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
+#endif
+#if defined(_SMU_PPUPATD0_ACMP1_SHIFT)
+ smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
+#endif
+ smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
+ smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
+ smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
+ smuPeripheralCRYPTO = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
+#if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
+ smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
+#endif
+ smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
+ smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
+ smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
+ smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
+ smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
+ smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
+#if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
+ smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
+#endif
+ smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */
+ smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
+#if defined(_SMU_PPUPATD0_LESENSE_SHIFT)
+ smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
+#endif
+ smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
+ smuPeripheralLEUART = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
+#if defined(_SMU_PPUPATD0_PCNT0_SHIFT)
+ smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
+#endif
+ smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
+ smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
+ smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
+ smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
+ smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
+ smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
+ smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
+ smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
+ smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
+ smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
+ smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
+
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
+ smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
+ smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
+ smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2 */
+ smuPeripheralACMP3 = _SMU_PPUPATD0_ACMP3_SHIFT, /**< SMU peripheral identifier for ACMP3 */
+ smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
+ smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1 */
+ smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0 */
+ smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1 */
+ smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
+ smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
+ smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
+ smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
+ smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
+ smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
+ smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI */
+ smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
+#if defined(_SMU_PPUPATD0_ETH_SHIFT)
+ smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH */
+#endif
+ smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
+ smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
+ smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
+ smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
+ smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
+ smuPeripheralI2C2 = _SMU_PPUPATD0_I2C2_SHIFT, /**< SMU peripheral identifier for I2C2 */
+ smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
+ smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC */
+#if defined(_SMU_PPUPATD0_LCD_SHIFT)
+ smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD */
+#endif
+ smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
+ smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
+ smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
+ smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1 */
+ smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
+ smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1 */
+ smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
+ smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1 */
+ smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2 */
+#if defined(_SMU_PPUPATD1_QSPI0_SHIFT)
+ smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0 */
+#endif
+ smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
+ smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC */
+ smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
+#if defined(_SMU_PPUPATD1_SDIO_SHIFT)
+ smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO */
+#endif
+ smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
+ smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
+ smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
+ smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2 */
+ smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3 */
+ smuPeripheralTIMER4 = 32 + _SMU_PPUPATD1_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4 */
+ smuPeripheralTIMER5 = 32 + _SMU_PPUPATD1_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5 */
+ smuPeripheralTIMER6 = 32 + _SMU_PPUPATD1_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6 */
+ smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
+ smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0 */
+ smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1 */
+ smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
+ smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
+ smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
+ smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3 */
+ smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4 */
+ smuPeripheralUSART5 = 32 + _SMU_PPUPATD1_USART5_SHIFT, /**< SMU peripheral identifier for USART5 */
+#if defined(_SMU_PPUPATD1_USB_SHIFT)
+ smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB */
+#endif
+ smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
+ smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
+ smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
+ smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1 */
+ smuPeripheralWTIMER2 = 32 + _SMU_PPUPATD1_WTIMER2_SHIFT, /**< SMU peripheral identifier for WTIMER2 */
+ smuPeripheralWTIMER3 = 32 + _SMU_PPUPATD1_WTIMER3_SHIFT, /**< SMU peripheral identifier for WTIMER3 */
+
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
+ smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
+ smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
+ smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
+ smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0 */
+ smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
+ smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
+ smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
+ smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
+ smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
+ smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
+ smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
+ smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
+ smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
+ smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
+ smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
+ smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC */
+#if defined(_SMU_PPUPATD0_LCD_SHIFT)
+ smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD */
+#endif
+ smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
+ smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
+ smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
+ smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
+ smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
+ smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
+ smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
+ smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
+ smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
+ smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER0 */
+ smuPeripheralTRNG0 = _SMU_PPUPATD0_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
+ smuPeripheralUART0 = _SMU_PPUPATD0_UART0_SHIFT, /**< SMU peripheral identifier for UART0 */
+ smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
+ smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
+ smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
+ smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3 */
+ smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
+ smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
+ smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1 */
+
#else
#error "No peripherals defined for SMU for this device configuration."
#endif
@@ -164,7 +330,6 @@
/** SMU peripheral privileged access enablers. */
typedef struct {
-
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
@@ -262,6 +427,154 @@
bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
+ bool privilegedACMP0 : 1; /**< Privileged access enabler for */
+ bool privilegedACMP1 : 1; /**< Privileged access enabler for */
+ bool privilegedADC0 : 1; /**< Privileged access enabler for */
+ bool privilegedReserved0 : 1;
+ bool privilegedReserved1 : 1;
+ bool privilegedCMU : 1; /**< Privileged access enabler for */
+ bool privilegedReserved2 : 1;
+ bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for */
+ bool privilegedCRYPTO : 1; /**< Privileged access enabler for */
+ bool privilegedVDAC0 : 1; /**< Privileged access enabler for */
+ bool privilegedPRS : 1; /**< Privileged access enabler for */
+ bool privilegedEMU : 1; /**< Privileged access enabler for */
+ bool privilegedFPUEH : 1; /**< Privileged access enabler for */
+ bool privilegedReserved3 : 1;
+ bool privilegedGPCRC : 1; /**< Privileged access enabler for */
+ bool privilegedGPIO : 1; /**< Privileged access enabler for */
+ bool privilegedI2C0 : 1; /**< Privileged access enabler for */
+ bool privilegedIDAC0 : 1; /**< Privileged access enabler for */
+ bool privilegedMSC : 1; /**< Privileged access enabler for */
+ bool privilegedLDMA : 1; /**< Privileged access enabler for */
+ bool privilegedLESENSE : 1; /**< Privileged access enabler for */
+ bool privilegedLETIMER0 : 1; /**< Privileged access enabler for */
+ bool privilegedLEUART : 1; /**< Privileged access enabler for */
+ bool privilegedReserved4 : 1;
+ bool privilegedPCNT0 : 1; /**< Privileged access enabler for */
+ bool privilegedReserved5 : 1;
+ bool privilegedReserved6 : 1;
+ bool privilegedReserved7 : 1;
+ bool privilegedReserved8 : 1;
+ bool privilegedRMU : 1; /**< Privileged access enabler for */
+ bool privilegedRTCC : 1; /**< Privileged access enabler for */
+ bool privilegedSMU : 1; /**< Privileged access enabler for */
+
+ bool privilegedReserved9 : 1;
+ bool privilegedTIMER0 : 1; /**< Privileged access enabler for */
+ bool privilegedTIMER1 : 1; /**< Privileged access enabler for */
+ bool privilegedTRNG0 : 1; /**< Privileged access enabler for */
+ bool privilegedUSART0 : 1; /**< Privileged access enabler for */
+ bool privilegedUSART1 : 1; /**< Privileged access enabler for */
+ bool privilegedWDOG0 : 1; /**< Privileged access enabler for */
+ bool privilegedWDOG1 : 1; /**< Privileged access enabler for */
+ bool privilegedWTIMER0 : 1; /**< Privileged access enabler for */
+
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
+ bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
+ bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
+ bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2 */
+ bool privilegedACMP3 : 1; /**< Privileged access enabler for ACMP3 */
+ bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */
+ bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1 */
+ bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0 */
+ bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1 */
+ bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
+ bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */
+ bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */
+ bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */
+ bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
+ bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
+ bool privilegedEBI : 1; /**< Privileged access enabler for EBI */
+ bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
+ bool privilegedETH : 1; /**< Privileged access enabler for ETH */
+ bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH */
+ bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
+ bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
+ bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
+ bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
+ bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2 */
+ bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0 */
+ bool privilegedMSC : 1; /**< Privileged access enabler for MAC */
+ bool privilegedLCD : 1; /**< Privileged access enabler for LCD */
+ bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
+ bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
+ bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
+ bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1 */
+ bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */
+ bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1 */
+ bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */
+ bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1 */
+ bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2 */
+ bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0 */
+ bool privilegedRMU : 1; /**< Privileged access enabler for RMU */
+ bool privilegedRTC : 1; /**< Privileged access enabler for RTC */
+ bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
+ bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO */
+ bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
+ bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
+ bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
+ bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
+ bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
+ bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */
+ bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */
+ bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */
+ bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */
+ bool privilegedUART0 : 1; /**< Privileged access enabler for UART0 */
+ bool privilegedUART1 : 1; /**< Privileged access enabler for UART1 */
+ bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
+ bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
+ bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
+ bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3 */
+ bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4 */
+ bool privilegedUSART5 : 1; /**< Privileged access enabler for USART5 */
+ bool privilegedUSB : 1; /**< Privileged access enabler for USB */
+ bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
+ bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
+ bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
+ bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1 */
+ bool privilegedWTIMER2 : 1; /**< Privileged access enabler for WTIMER2 */
+ bool privilegedWTIMER3 : 1; /**< Privileged access enabler for WTIMER3 */
+
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
+ bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
+ bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
+ bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */
+ bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0 */
+ bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
+ bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */
+ bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */
+ bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */
+ bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
+ bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
+ bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
+ bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
+ bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
+ bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
+ bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
+ bool privilegedMSC : 1; /**< Privileged access enabler for MAC */
+ bool privilegedLCD : 1; /**< Privileged access enabler for LCD */
+ bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
+ bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
+ bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
+ bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */
+ bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */
+ bool privilegedRMU : 1; /**< Privileged access enabler for RMU */
+ bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
+ bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
+ bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
+ bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
+ bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */
+ bool privilegedUART0 : 1; /**< Privileged access enabler for UART0 */
+ bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
+ bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
+ bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
+ bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3 */
+ bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
+ bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
+ bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1 */
+
#else
#error "No peripherals defined for SMU for this device configuration"
#endif
@@ -280,13 +593,11 @@
bool enable; /**< SMU enable flag, when set SMU_Init() will enable SMU.*/
} SMU_Init_TypeDef;
-#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID > 80)
/** Default SMU initialization struct settings. */
-#define SMU_INIT_DEFAULT { \
- {{0}}, /* No peripherals acsess protected. */ \
- true /* Enable SMU.*/ \
+#define SMU_INIT_DEFAULT { \
+ { { 0 } }, /* No peripherals acsess protected. */ \
+ true /* Enable SMU.*/ \
}
-#endif
/*******************************************************************************
***************************** PROTOTYPES **********************************
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_system.h
* @brief System API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -61,18 +61,23 @@
******************************************************************************/
/** Family identifiers. */
-typedef enum
-{
+typedef enum {
/* New style family #defines */
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32G)
systemPartFamilyEfm32Gecko = _DEVINFO_PART_DEVICE_FAMILY_EFM32G, /**< EFM32 Gecko Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG)
- systemPartFamilyEfm32Giant = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG, /**< EFM32 Giant Gecko Device Family */
+ systemPartFamilyEfm32Giant = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG, /**< EFM32 Giant Gecko Series 0 Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B)
+ systemPartFamilyEfm32Giant11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B, /**< EFM32 Giant Gecko Series 1 Config 1 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG)
systemPartFamilyEfm32Tiny = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG, /**< EFM32 Tiny Gecko Device Family */
#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B)
+ systemPartFamilyEfm32Tiny11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B, /**< EFM32 Tiny Gecko 11 Device Family */
+#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32LG)
systemPartFamilyEfm32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EFM32LG, /**< EFM32 Leopard Gecko Device Family */
#endif
@@ -92,16 +97,16 @@
systemPartFamilyEfm32Jade1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B, /**< EFM32 Jade Gecko Series 1 Config 1 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B)
- systemPartFamilyEfm32Pearl12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B, /**< EFM32 Pearl Gecko Series 1 Config 2 Basic Device Family */
+ systemPartFamilyEfm32Pearl12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B, /**< EFM32 Pearl Gecko Series 1 Config 2 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B)
- systemPartFamilyEfm32Jade12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B, /**< EFM32 Jade Gecko Series 1 Config 2 Basic Device Family */
+ systemPartFamilyEfm32Jade12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B, /**< EFM32 Jade Gecko Series 1 Config 2 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B)
- systemPartFamilyEfm32Pearl13B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B, /**< EFM32 Pearl Gecko Series 1 Config 3 Basic Device Family */
+ systemPartFamilyEfm32Pearl13B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B, /**< EFM32 Pearl Gecko Series 1 Config 3 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B)
- systemPartFamilyEfm32Jade13B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B, /**< EFM32 Jade Gecko Series 1 Config 3 Basic Device Family */
+ systemPartFamilyEfm32Jade13B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B, /**< EFM32 Jade Gecko Series 1 Config 3 Basic Device Family */
#endif
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32WG)
systemPartFamilyEzr32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EZR32WG, /**< EZR32 Wonder Device Family */
@@ -196,8 +201,33 @@
#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V)
systemPartFamilyFlex13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V, /**< EFR32 Flex Gecko Series 1 Config 3 Value Device Family */
#endif
-
-
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P)
+ systemPartFamilyMighty14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P, /**< EFR32 Mighty Gecko Series 1 Config 4 Premium Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B)
+ systemPartFamilyMighty14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B, /**< EFR32 Mighty Gecko Series 1 Config 4 Basic Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V)
+ systemPartFamilyMighty14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V, /**< EFR32 Mighty Gecko Series 1 Config 4 Value Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P)
+ systemPartFamilyBlue14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14P, /**< EFR32 Blue Gecko Series 1 Config 4 Premium Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B)
+ systemPartFamilyBlue14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14B, /**< EFR32 Blue Gecko Series 1 Config 4 Basic Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V)
+ systemPartFamilyBlue14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG14V, /**< EFR32 Blue Gecko Series 1 Config 4 Value Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P)
+ systemPartFamilyFlex14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P, /**< EFR32 Flex Gecko Series 1 Config 4 Premium Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B)
+ systemPartFamilyFlex14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B, /**< EFR32 Flex Gecko Series 1 Config 4 Basic Device Family */
+#endif
+#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V)
+ systemPartFamilyFlex14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V, /**< EFR32 Flex Gecko Series 1 Config 4 Value Device Family */
+#endif
/* Deprecated family #defines */
#if defined(_DEVINFO_PART_DEVICE_FAMILY_G)
@@ -226,14 +256,12 @@
on unprogrammed parts. */
} SYSTEM_PartFamily_TypeDef;
-
/*******************************************************************************
******************************* STRUCTS ***********************************
******************************************************************************/
/** Chip revision details */
-typedef struct
-{
+typedef struct {
uint8_t minor; /**< Minor revision number */
uint8_t major; /**< Major revision number */
uint8_t family;/**< Device family number */
@@ -241,8 +269,7 @@
#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1)
/** Floating point coprocessor access modes. */
-typedef enum
-{
+typedef enum {
fpuAccessDenied = (0x0 << 20), /**< Access denied, any attempted access generates a NOCP UsageFault. */
fpuAccessPrivilegedOnly = (0x5 << 20), /**< Privileged access only, an unprivileged access generates a NOCP UsageFault. */
fpuAccessReserved = (0xA << 20), /**< Reserved. */
@@ -251,8 +278,7 @@
#endif
/** DEVINFO calibration address/value pair */
-typedef struct
-{
+typedef struct {
uint32_t address; /**< Peripheral calibration register address */
uint32_t calValue; /**< Calibration value for register at address */
}
@@ -324,14 +350,13 @@
#if defined(_EFM32_GECKO_FAMILY)
/* Early Gecko devices had a bug where SRAM and Flash size were swapped. */
- if (SYSTEM_GetProdRev() < 5)
- {
+ if (SYSTEM_GetProdRev() < 5) {
sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK)
- >> _DEVINFO_MSIZE_FLASH_SHIFT;
+ >> _DEVINFO_MSIZE_FLASH_SHIFT;
}
#endif
sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK)
- >> _DEVINFO_MSIZE_SRAM_SHIFT;
+ >> _DEVINFO_MSIZE_SRAM_SHIFT;
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE)
/* Do not include EFR32xG1 RAMH */
@@ -357,8 +382,7 @@
{
#if defined(_EFM32_GECKO_FAMILY)
/* Early Gecko devices had a bug where SRAM and Flash size were swapped. */
- if (SYSTEM_GetProdRev() < 5)
- {
+ if (SYSTEM_GetProdRev() < 5) {
return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK)
>> _DEVINFO_MSIZE_SRAM_SHIFT;
}
@@ -367,7 +391,6 @@
>> _DEVINFO_MSIZE_FLASH_SHIFT;
}
-
/***************************************************************************//**
* @brief
* Get the flash page size in bytes.
@@ -384,19 +407,19 @@
{
uint32_t tmp;
+#if defined(_SILICON_LABS_32B_SERIES_0)
#if defined(_EFM32_GIANT_FAMILY)
- if (SYSTEM_GetProdRev() < 18)
- {
+ if (SYSTEM_GetProdRev() < 18) {
/* Early Giant/Leopard devices did not have MEMINFO in DEVINFO. */
return FLASH_PAGE_SIZE;
}
#elif defined(_EFM32_ZERO_FAMILY)
- if (SYSTEM_GetProdRev() < 24)
- {
+ if (SYSTEM_GetProdRev() < 24) {
/* Early Zero devices have an incorrect DEVINFO flash page size */
return FLASH_PAGE_SIZE;
}
#endif
+#endif
tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK)
>> _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT;
@@ -404,8 +427,7 @@
return 1 << ((tmp + 10) & 0xFF);
}
-
-#if defined( _DEVINFO_DEVINFOREV_DEVINFOREV_MASK )
+#if defined(_DEVINFO_DEVINFOREV_DEVINFOREV_MASK)
/***************************************************************************//**
* @brief
* Get DEVINFO revision.
@@ -416,11 +438,10 @@
__STATIC_INLINE uint8_t SYSTEM_GetDevinfoRev(void)
{
return (DEVINFO->DEVINFOREV & _DEVINFO_DEVINFOREV_DEVINFOREV_MASK)
- >> _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT;
+ >> _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT;
}
#endif
-
/***************************************************************************//**
* @brief
* Get part number of the MCU.
@@ -455,7 +476,6 @@
>> _DEVINFO_PART_DEVICE_FAMILY_SHIFT);
}
-
/***************************************************************************//**
* @brief
* Get the calibration temperature (in degrees Celsius).
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_timer.h
* @brief Timer/counter (TIMER) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -78,18 +78,15 @@
******************************************************************************/
/** Timer compare/capture mode. */
-typedef enum
-{
+typedef enum {
timerCCModeOff = _TIMER_CC_CTRL_MODE_OFF, /**< Channel turned off. */
timerCCModeCapture = _TIMER_CC_CTRL_MODE_INPUTCAPTURE, /**< Input capture. */
timerCCModeCompare = _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Output compare. */
timerCCModePWM = _TIMER_CC_CTRL_MODE_PWM /**< Pulse-Width modulation. */
} TIMER_CCMode_TypeDef;
-
/** Clock select. */
-typedef enum
-{
+typedef enum {
/** Prescaled HFPER clock. */
timerClkSelHFPerClk = _TIMER_CTRL_CLKSEL_PRESCHFPERCLK,
@@ -103,10 +100,8 @@
timerClkSelCascade = _TIMER_CTRL_CLKSEL_TIMEROUF
} TIMER_ClkSel_TypeDef;
-
/** Input capture edge select. */
-typedef enum
-{
+typedef enum {
/** Rising edges detected. */
timerEdgeRising = _TIMER_CC_CTRL_ICEDGE_RISING,
@@ -120,10 +115,8 @@
timerEdgeNone = _TIMER_CC_CTRL_ICEDGE_NONE
} TIMER_Edge_TypeDef;
-
/** Input capture event control. */
-typedef enum
-{
+typedef enum {
/** PRS output pulse, interrupt flag and DMA request set on every capture. */
timerEventEveryEdge = _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE,
/** PRS output pulse, interrupt flag and DMA request set on every second capture. */
@@ -140,10 +133,8 @@
timerEventFalling = _TIMER_CC_CTRL_ICEVCTRL_FALLING
} TIMER_Event_TypeDef;
-
/** Input edge action. */
-typedef enum
-{
+typedef enum {
/** No action taken. */
timerInputActionNone = _TIMER_CTRL_FALLA_NONE,
@@ -157,20 +148,16 @@
timerInputActionReloadStart = _TIMER_CTRL_FALLA_RELOADSTART
} TIMER_InputAction_TypeDef;
-
/** Timer mode. */
-typedef enum
-{
+typedef enum {
timerModeUp = _TIMER_CTRL_MODE_UP, /**< Up-counting. */
timerModeDown = _TIMER_CTRL_MODE_DOWN, /**< Down-counting. */
timerModeUpDown = _TIMER_CTRL_MODE_UPDOWN, /**< Up/down-counting. */
timerModeQDec = _TIMER_CTRL_MODE_QDEC /**< Quadrature decoder. */
} TIMER_Mode_TypeDef;
-
/** Compare/capture output action. */
-typedef enum
-{
+typedef enum {
/** No action. */
timerOutputActionNone = _TIMER_CC_CTRL_CUFOA_NONE,
@@ -184,10 +171,8 @@
timerOutputActionSet = _TIMER_CC_CTRL_CUFOA_SET
} TIMER_OutputAction_TypeDef;
-
/** Prescaler. */
-typedef enum
-{
+typedef enum {
timerPrescale1 = _TIMER_CTRL_PRESC_DIV1, /**< Divide by 1. */
timerPrescale2 = _TIMER_CTRL_PRESC_DIV2, /**< Divide by 2. */
timerPrescale4 = _TIMER_CTRL_PRESC_DIV4, /**< Divide by 4. */
@@ -201,10 +186,8 @@
timerPrescale1024 = _TIMER_CTRL_PRESC_DIV1024 /**< Divide by 1024. */
} TIMER_Prescale_TypeDef;
-
/** Peripheral Reflex System signal. */
-typedef enum
-{
+typedef enum {
timerPRSSELCh0 = _TIMER_CC_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0. */
timerPRSSELCh1 = _TIMER_CC_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1. */
timerPRSSELCh2 = _TIMER_CC_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2. */
@@ -237,8 +220,7 @@
#if defined(_TIMER_DTFC_DTFA_NONE)
/** DT (Dead Time) Fault Actions. */
-typedef enum
-{
+typedef enum {
timerDtiFaultActionNone = _TIMER_DTFC_DTFA_NONE, /**< No action on fault. */
timerDtiFaultActionInactive = _TIMER_DTFC_DTFA_INACTIVE, /**< Set outputs inactive. */
timerDtiFaultActionClear = _TIMER_DTFC_DTFA_CLEAR, /**< Clear outputs. */
@@ -251,8 +233,7 @@
******************************************************************************/
/** TIMER initialization structure. */
-typedef struct
-{
+typedef struct {
/** Start counting when init completed. */
bool enable;
@@ -299,41 +280,40 @@
/** Default config for TIMER init structure. */
#if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI)
#define TIMER_INIT_DEFAULT \
-{ \
- true, /* Enable timer when init complete. */ \
- false, /* Stop counter during debug halt. */ \
- timerPrescale1, /* No prescaling. */ \
- timerClkSelHFPerClk, /* Select HFPER clock. */ \
- false, /* Not 2x count mode. */ \
- false, /* No ATI. */ \
- timerInputActionNone, /* No action on falling input edge. */ \
- timerInputActionNone, /* No action on rising input edge. */ \
- timerModeUp, /* Up-counting. */ \
- false, /* Do not clear DMA requests when DMA channel is active. */ \
- false, /* Select X2 quadrature decode mode (if used). */ \
- false, /* Disable one shot. */ \
- false /* Not started/stopped/reloaded by other timers. */ \
-}
+ { \
+ true, /* Enable timer when init complete. */ \
+ false, /* Stop counter during debug halt. */ \
+ timerPrescale1, /* No prescaling. */ \
+ timerClkSelHFPerClk, /* Select HFPER clock. */ \
+ false, /* Not 2x count mode. */ \
+ false, /* No ATI. */ \
+ timerInputActionNone, /* No action on falling input edge. */ \
+ timerInputActionNone, /* No action on rising input edge. */ \
+ timerModeUp, /* Up-counting. */ \
+ false, /* Do not clear DMA requests when DMA channel is active. */ \
+ false, /* Select X2 quadrature decode mode (if used). */ \
+ false, /* Disable one shot. */ \
+ false /* Not started/stopped/reloaded by other timers. */ \
+ }
#else
#define TIMER_INIT_DEFAULT \
-{ \
- true, /* Enable timer when init complete. */ \
- false, /* Stop counter during debug halt. */ \
- timerPrescale1, /* No prescaling. */ \
- timerClkSelHFPerClk, /* Select HFPER clock. */ \
- timerInputActionNone, /* No action on falling input edge. */ \
- timerInputActionNone, /* No action on rising input edge. */ \
- timerModeUp, /* Up-counting. */ \
- false, /* Do not clear DMA requests when DMA channel is active. */ \
- false, /* Select X2 quadrature decode mode (if used). */ \
- false, /* Disable one shot. */ \
- false /* Not started/stopped/reloaded by other timers. */ \
-}
+ { \
+ true, /* Enable timer when init complete. */ \
+ false, /* Stop counter during debug halt. */ \
+ timerPrescale1, /* No prescaling. */ \
+ timerClkSelHFPerClk, /* Select HFPER clock. */ \
+ timerInputActionNone, /* No action on falling input edge. */ \
+ timerInputActionNone, /* No action on rising input edge. */ \
+ timerModeUp, /* Up-counting. */ \
+ false, /* Do not clear DMA requests when DMA channel is active. */ \
+ false, /* Select X2 quadrature decode mode (if used). */ \
+ false, /* Disable one shot. */ \
+ false /* Not started/stopped/reloaded by other timers. */ \
+ }
#endif
/** TIMER compare/capture initialization structure. */
-typedef struct
-{
+typedef struct {
/** Input capture event control. */
TIMER_Event_TypeDef eventCtrl;
@@ -379,24 +359,23 @@
/** Default config for TIMER compare/capture init structure. */
#define TIMER_INITCC_DEFAULT \
-{ \
- timerEventEveryEdge, /* Event on every capture. */ \
- timerEdgeRising, /* Input capture edge on rising edge. */ \
- timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
- timerOutputActionNone, /* No action on underflow. */ \
- timerOutputActionNone, /* No action on overflow. */ \
- timerOutputActionNone, /* No action on match. */ \
- timerCCModeOff, /* Disable compare/capture channel. */ \
- false, /* Disable filter. */ \
- false, /* Select TIMERnCCx input. */ \
- false, /* Clear output when counter disabled. */ \
- false /* Do not invert output. */ \
-}
+ { \
+ timerEventEveryEdge, /* Event on every capture. */ \
+ timerEdgeRising, /* Input capture edge on rising edge. */ \
+ timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
+ timerOutputActionNone, /* No action on underflow. */ \
+ timerOutputActionNone, /* No action on overflow. */ \
+ timerOutputActionNone, /* No action on match. */ \
+ timerCCModeOff, /* Disable compare/capture channel. */ \
+ false, /* Disable filter. */ \
+ false, /* Select TIMERnCCx input. */ \
+ false, /* Clear output when counter disabled. */ \
+ false /* Do not invert output. */ \
+ }
#if defined(_TIMER_DTCTRL_MASK)
/** TIMER Dead Time Insertion (DTI) initialization structure. */
-typedef struct
-{
+typedef struct {
/** Enable DTI or leave it disabled until @ref TIMER_EnableDTI() is called */
bool enable;
@@ -451,39 +430,35 @@
/** Fault Action */
TIMER_DtiFaultAction_TypeDef faultAction;
-
} TIMER_InitDTI_TypeDef;
-
- /** Default config for TIMER DTI init structure. */
-#define TIMER_INITDTI_DEFAULT \
-{ \
- true, /* Enable the DTI. */ \
- false, /* CC[0|1|2] outputs are active high. */ \
- false, /* CDTI[0|1|2] outputs are not inverted. */ \
- false, /* No auto restart when debugger exits. */ \
- false, /* No PRS source selected. */ \
- timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
- timerPrescale1, /* No prescaling. */ \
- 0, /* No rise time. */ \
- 0, /* No fall time. */ \
- TIMER_DTOGEN_DTOGCC0EN|TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0 */\
- true, /* Enable core lockup as fault source */ \
- true, /* Enable debugger as fault source */ \
- false, /* Disable PRS fault source 0 */ \
- timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
- false, /* Disable PRS fault source 1 */ \
- timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
- timerDtiFaultActionInactive, /* No fault action. */ \
-}
+/** Default config for TIMER DTI init structure. */
+#define TIMER_INITDTI_DEFAULT \
+ { \
+ true, /* Enable the DTI. */ \
+ false, /* CC[0|1|2] outputs are active high. */ \
+ false, /* CDTI[0|1|2] outputs are not inverted. */ \
+ false, /* No auto restart when debugger exits. */ \
+ false, /* No PRS source selected. */ \
+ timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
+ timerPrescale1, /* No prescaling. */ \
+ 0, /* No rise time. */ \
+ 0, /* No fall time. */ \
+ TIMER_DTOGEN_DTOGCC0EN | TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0 */ \
+ true, /* Enable core lockup as fault source */ \
+ true, /* Enable debugger as fault source */ \
+ false, /* Disable PRS fault source 0 */ \
+ timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
+ false, /* Disable PRS fault source 1 */ \
+ timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
+ timerDtiFaultActionInactive, /* No fault action. */ \
+ }
#endif /* _TIMER_DTCTRL_MASK */
-
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
-
/***************************************************************************//**
* @brief
* Validate the TIMER register block pointer
@@ -506,13 +481,28 @@
#if defined(TIMER3)
|| (ref == TIMER3)
#endif
+#if defined(TIMER4)
+ || (ref == TIMER4)
+#endif
+#if defined(TIMER5)
+ || (ref == TIMER5)
+#endif
+#if defined(TIMER6)
+ || (ref == TIMER6)
+#endif
#if defined(WTIMER0)
|| (ref == WTIMER0)
#endif
#if defined(WTIMER1)
|| (ref == WTIMER1)
#endif
- ;
+#if defined(WTIMER2)
+ || (ref == WTIMER2)
+#endif
+#if defined(WTIMER3)
+ || (ref == WTIMER3)
+#endif
+ ;
}
/***************************************************************************//**
@@ -533,8 +523,13 @@
#if defined(WTIMER1)
|| (ref == WTIMER1)
#endif
- )
- {
+#if defined(WTIMER2)
+ || (ref == WTIMER2)
+#endif
+#if defined(WTIMER3)
+ || (ref == WTIMER3)
+#endif
+ ) {
return 0xFFFFFFFFUL;
}
#else
@@ -562,7 +557,6 @@
return timer->CC[ch].CCV;
}
-
/***************************************************************************//**
* @brief
* Set compare value buffer for compare/capture channel when operating in
@@ -590,7 +584,6 @@
timer->CC[ch].CCVB = val;
}
-
/***************************************************************************//**
* @brief
* Set compare value for compare/capture channel when operating in compare
@@ -613,7 +606,6 @@
timer->CC[ch].CCV = val;
}
-
/***************************************************************************//**
* @brief
* Get TIMER counter value.
@@ -629,7 +621,6 @@
return timer->CNT;
}
-
/***************************************************************************//**
* @brief
* Set TIMER counter value.
@@ -646,7 +637,6 @@
timer->CNT = val;
}
-
/***************************************************************************//**
* @brief
* Start/stop TIMER.
@@ -661,17 +651,13 @@
{
EFM_ASSERT(TIMER_REF_VALID(timer));
- if (enable)
- {
+ if (enable) {
timer->CMD = TIMER_CMD_START;
- }
- else
- {
+ } else {
timer->CMD = TIMER_CMD_STOP;
}
}
-
void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init);
void TIMER_InitCC(TIMER_TypeDef *timer,
unsigned int ch,
@@ -694,17 +680,13 @@
{
EFM_ASSERT(TIMER0 == timer);
- if (enable)
- {
+ if (enable) {
timer->DTCTRL |= TIMER_DTCTRL_DTEN;
- }
- else
- {
+ } else {
timer->DTCTRL &= ~TIMER_DTCTRL_DTEN;
}
}
-
/***************************************************************************//**
* @brief
* Get DTI fault source flags status.
@@ -725,7 +707,6 @@
return timer->DTFAULT;
}
-
/***************************************************************************//**
* @brief
* Clear DTI fault source flags.
@@ -745,7 +726,6 @@
}
#endif /* _TIMER_DTCTRL_MASK */
-
/***************************************************************************//**
* @brief
* Clear one or more pending TIMER interrupts.
@@ -762,7 +742,6 @@
timer->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more TIMER interrupts.
@@ -779,7 +758,6 @@
timer->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more TIMER interrupts.
@@ -801,7 +779,6 @@
timer->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending TIMER interrupt flags.
@@ -821,7 +798,6 @@
return timer->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending TIMER interrupt flags.
@@ -853,7 +829,6 @@
return timer->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending TIMER interrupts from SW.
@@ -918,7 +893,6 @@
timer->TOPB = val;
}
-
/***************************************************************************//**
* @brief
* Get top value setting for timer.
@@ -934,7 +908,6 @@
return timer->TOP;
}
-
/***************************************************************************//**
* @brief
* Set top value for timer.
@@ -951,7 +924,6 @@
timer->TOP = val;
}
-
#if defined(TIMER_DTLOCK_LOCKKEY_UNLOCK)
/***************************************************************************//**
* @brief
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h Thu Dec 07 14:01:42 2017 +0000
@@ -2,9 +2,9 @@
* @file em_usart.h
* @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART)
* peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -31,7 +31,6 @@
*
******************************************************************************/
-
#ifndef EM_USART_H
#define EM_USART_H
@@ -102,8 +101,7 @@
******************************************************************************/
/** Databit selection. */
-typedef enum
-{
+typedef enum {
usartDatabits4 = USART_FRAME_DATABITS_FOUR, /**< 4 databits (not available for UART). */
usartDatabits5 = USART_FRAME_DATABITS_FIVE, /**< 5 databits (not available for UART). */
usartDatabits6 = USART_FRAME_DATABITS_SIX, /**< 6 databits (not available for UART). */
@@ -119,10 +117,8 @@
usartDatabits16 = USART_FRAME_DATABITS_SIXTEEN /**< 16 databits (not available for UART). */
} USART_Databits_TypeDef;
-
/** Enable selection. */
-typedef enum
-{
+typedef enum {
/** Disable both receiver and transmitter. */
usartDisable = 0x0,
@@ -136,39 +132,40 @@
usartEnable = (USART_CMD_RXEN | USART_CMD_TXEN)
} USART_Enable_TypeDef;
-
/** Oversampling selection, used for asynchronous operation. */
-typedef enum
-{
+typedef enum {
usartOVS16 = USART_CTRL_OVS_X16, /**< 16x oversampling (normal). */
usartOVS8 = USART_CTRL_OVS_X8, /**< 8x oversampling. */
usartOVS6 = USART_CTRL_OVS_X6, /**< 6x oversampling. */
usartOVS4 = USART_CTRL_OVS_X4 /**< 4x oversampling. */
} USART_OVS_TypeDef;
-
/** Parity selection, mainly used for asynchronous operation. */
-typedef enum
-{
+typedef enum {
usartNoParity = USART_FRAME_PARITY_NONE, /**< No parity. */
usartEvenParity = USART_FRAME_PARITY_EVEN, /**< Even parity. */
usartOddParity = USART_FRAME_PARITY_ODD /**< Odd parity. */
} USART_Parity_TypeDef;
-
/** Stopbits selection, used for asynchronous operation. */
-typedef enum
-{
+typedef enum {
usartStopbits0p5 = USART_FRAME_STOPBITS_HALF, /**< 0.5 stopbits. */
usartStopbits1 = USART_FRAME_STOPBITS_ONE, /**< 1 stopbits. */
usartStopbits1p5 = USART_FRAME_STOPBITS_ONEANDAHALF, /**< 1.5 stopbits. */
usartStopbits2 = USART_FRAME_STOPBITS_TWO /**< 2 stopbits. */
} USART_Stopbits_TypeDef;
+#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
+typedef enum {
+ usartHwFlowControlNone = 0,
+ usartHwFlowControlCts = USART_ROUTEPEN_CTSPEN,
+ usartHwFlowControlRts = USART_ROUTEPEN_RTSPEN,
+ usartHwFlowControlCtsAndRts = USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN,
+} USART_HwFlowControl_TypeDef;
+#endif
/** Clock polarity/phase mode. */
-typedef enum
-{
+typedef enum {
/** Clock idle low, sample on rising edge. */
usartClockMode0 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLELEADING,
@@ -182,10 +179,8 @@
usartClockMode3 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLETRAILING
} USART_ClockMode_TypeDef;
-
/** Pulse width selection for IrDA mode. */
-typedef enum
-{
+typedef enum {
/** IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 */
usartIrDAPwONE = USART_IRCTRL_IRPW_ONE,
@@ -199,10 +194,8 @@
usartIrDAPwFOUR = USART_IRCTRL_IRPW_FOUR
} USART_IrDAPw_Typedef;
-
/** PRS channel selection for IrDA mode. */
-typedef enum
-{
+typedef enum {
usartIrDAPrsCh0 = USART_IRCTRL_IRPRSSEL_PRSCH0, /**< PRS channel 0 */
usartIrDAPrsCh1 = USART_IRCTRL_IRPRSSEL_PRSCH1, /**< PRS channel 1 */
usartIrDAPrsCh2 = USART_IRCTRL_IRPRSSEL_PRSCH2, /**< PRS channel 2 */
@@ -223,8 +216,7 @@
#if defined(_USART_I2SCTRL_MASK)
/** I2S format selection. */
-typedef enum
-{
+typedef enum {
usartI2sFormatW32D32 = USART_I2SCTRL_FORMAT_W32D32, /**< 32-bit word, 32-bit data */
usartI2sFormatW32D24M = USART_I2SCTRL_FORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked */
usartI2sFormatW32D24 = USART_I2SCTRL_FORMAT_W32D24, /**< 32-bit word, 24-bit data */
@@ -236,8 +228,7 @@
} USART_I2sFormat_TypeDef;
/** I2S frame data justify. */
-typedef enum
-{
+typedef enum {
usartI2sJustifyLeft = USART_I2SCTRL_JUSTIFY_LEFT, /**< Data is left-justified within the frame */
usartI2sJustifyRight = USART_I2SCTRL_JUSTIFY_RIGHT /**< Data is right-justified within the frame */
} USART_I2sJustify_TypeDef;
@@ -245,8 +236,7 @@
#if defined(_USART_INPUT_MASK)
/** USART Rx input PRS selection. */
-typedef enum
-{
+typedef enum {
usartPrsRxCh0 = USART_INPUT_RXPRSSEL_PRSCH0, /**< PRSCH0 selected as USART_INPUT */
usartPrsRxCh1 = USART_INPUT_RXPRSSEL_PRSCH1, /**< PRSCH1 selected as USART_INPUT */
usartPrsRxCh2 = USART_INPUT_RXPRSSEL_PRSCH2, /**< PRSCH2 selected as USART_INPUT */
@@ -269,8 +259,7 @@
#endif
/** USART PRS Transmit Trigger Channels */
-typedef enum
-{
+typedef enum {
usartPrsTriggerCh0 = USART_TRIGCTRL_TSEL_PRSCH0, /**< PRSCH0 selected as USART Trigger */
usartPrsTriggerCh1 = USART_TRIGCTRL_TSEL_PRSCH1, /**< PRSCH0 selected as USART Trigger */
usartPrsTriggerCh2 = USART_TRIGCTRL_TSEL_PRSCH2, /**< PRSCH0 selected as USART Trigger */
@@ -289,8 +278,7 @@
******************************************************************************/
/** Asynchronous mode init structure. */
-typedef struct
-{
+typedef struct {
/** Specifies whether TX and/or RX shall be enabled when init completed. */
USART_Enable_TypeDef enable;
@@ -334,11 +322,13 @@
/** Auto CS setup time in baud cycles */
uint8_t autoCsSetup;
#endif
+#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
+ USART_HwFlowControl_TypeDef hwFlowControl;
+#endif
} USART_InitAsync_TypeDef;
/** USART PRS trigger enable */
-typedef struct
-{
+typedef struct {
#if defined(USART_TRIGCTRL_AUTOTXTEN)
/** Enable AUTOTX */
bool autoTxTriggerEnable;
@@ -352,71 +342,119 @@
} USART_PrsTriggerInit_TypeDef;
/** Default config for USART async init structure. */
+#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
-#define USART_INITASYNC_DEFAULT \
-{ \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 115200, /* 115200 bits/s. */ \
- usartOVS16, /* 16x oversampling. */ \
- usartDatabits8, /* 8 databits. */ \
- usartNoParity, /* No parity. */ \
- usartStopbits1, /* 1 stopbit. */ \
- false, /* Do not disable majority vote. */ \
- false, /* Not USART PRS input mode. */ \
- usartPrsRxCh0, /* PRS channel 0. */ \
- false, /* Auto CS functionality enable/disable switch */ \
- 0, /* Auto CS Hold cycles */ \
- 0 /* Auto CS Setup cycles */ \
-}
+#define USART_INITASYNC_DEFAULT \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartNoParity, /* No parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ false, /* Auto CS functionality enable/disable switch */ \
+ 0, /* Auto CS Hold cycles */ \
+ 0, /* Auto CS Setup cycles */ \
+ usartHwFlowControlNone /* No HW flow control */ \
+ }
#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
-#define USART_INITASYNC_DEFAULT \
-{ \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 115200, /* 115200 bits/s. */ \
- usartOVS16, /* 16x oversampling. */ \
- usartDatabits8, /* 8 databits. */ \
- usartNoParity, /* No parity. */ \
- usartStopbits1, /* 1 stopbit. */ \
- false, /* Do not disable majority vote. */ \
- false, /* Not USART PRS input mode. */ \
- usartPrsRxCh0 /* PRS channel 0. */ \
-}
+#define USART_INITASYNC_DEFAULT \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartNoParity, /* No parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ usartHwFlowControlNone /* No HW flow control */ \
+ }
+#else
+#define USART_INITASYNC_DEFAULT \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartNoParity, /* No parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ usartHwFlowControlNone /* No HW flow control */ \
+ }
+#endif
#else
-#define USART_INITASYNC_DEFAULT \
-{ \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 115200, /* 115200 bits/s. */ \
- usartOVS16, /* 16x oversampling. */ \
- usartDatabits8, /* 8 databits. */ \
- usartNoParity, /* No parity. */ \
- usartStopbits1 /* 1 stopbit. */ \
-}
+#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
+#define USART_INITASYNC_DEFAULT \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartNoParity, /* No parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ false, /* Auto CS functionality enable/disable switch */ \
+ 0, /* Auto CS Hold cycles */ \
+ 0 /* Auto CS Setup cycles */ \
+ }
+#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
+#define USART_INITASYNC_DEFAULT \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartNoParity, /* No parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0 /* PRS channel 0. */ \
+ }
+#else
+#define USART_INITASYNC_DEFAULT \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartNoParity, /* No parity. */ \
+ usartStopbits1 /* 1 stopbit. */ \
+ }
+#endif
#endif
/** Default config for USART PRS triggering structure. */
#if defined(USART_TRIGCTRL_AUTOTXTEN)
-#define USART_INITPRSTRIGGER_DEFAULT \
-{ \
- false, /* Do not enable autoTX triggering. */ \
- false, /* Do not enable receive triggering. */ \
- false, /* Do not enable transmit triggering. */ \
- usartPrsTriggerCh0 /* Set default channel to zero. */ \
-}
+#define USART_INITPRSTRIGGER_DEFAULT \
+ { \
+ false, /* Do not enable autoTX triggering. */ \
+ false, /* Do not enable receive triggering. */ \
+ false, /* Do not enable transmit triggering. */ \
+ usartPrsTriggerCh0 /* Set default channel to zero. */ \
+ }
#else
-#define USART_INITPRSTRIGGER_DEFAULT \
-{ \
- false, /* Do not enable receive triggering. */ \
- false, /* Do not enable transmit triggering. */ \
- usartPrsTriggerCh0 /* Set default channel to zero. */ \
-}
+#define USART_INITPRSTRIGGER_DEFAULT \
+ { \
+ false, /* Do not enable receive triggering. */ \
+ false, /* Do not enable transmit triggering. */ \
+ usartPrsTriggerCh0 /* Set default channel to zero. */ \
+ }
#endif
/** Synchronous mode init structure. */
-typedef struct
-{
+typedef struct {
/** Specifies whether TX and/or RX shall be enabled when init completed. */
USART_Enable_TypeDef enable;
@@ -465,52 +503,50 @@
/** Default config for USART sync init structure. */
#if defined(_USART_TIMING_CSHOLD_MASK)
#define USART_INITSYNC_DEFAULT \
-{ \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 1000000, /* 1 Mbits/s. */ \
- usartDatabits8, /* 8 databits. */ \
- true, /* Master mode. */ \
- false, /* Send least significant bit first. */ \
- usartClockMode0, /* Clock idle low, sample on rising edge. */ \
- false, /* Not USART PRS input mode. */ \
- usartPrsRxCh0, /* PRS channel 0. */ \
- false, /* No AUTOTX mode. */ \
- false, /* No AUTOCS mode */ \
- 0, /* Auto CS Hold cycles */ \
- 0 /* Auto CS Setup cycles */ \
-}
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 1000000, /* 1 Mbits/s. */ \
+ usartDatabits8, /* 8 databits. */ \
+ true, /* Master mode. */ \
+ false, /* Send least significant bit first. */ \
+ usartClockMode0, /* Clock idle low, sample on rising edge. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ false, /* No AUTOTX mode. */ \
+ false, /* No AUTOCS mode */ \
+ 0, /* Auto CS Hold cycles */ \
+ 0 /* Auto CS Setup cycles */ \
+ }
#elif defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)
#define USART_INITSYNC_DEFAULT \
-{ \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 1000000, /* 1 Mbits/s. */ \
- usartDatabits8, /* 8 databits. */ \
- true, /* Master mode. */ \
- false, /* Send least significant bit first. */ \
- usartClockMode0, /* Clock idle low, sample on rising edge. */ \
- false, /* Not USART PRS input mode. */ \
- usartPrsRxCh0, /* PRS channel 0. */ \
- false /* No AUTOTX mode. */ \
-}
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 1000000, /* 1 Mbits/s. */ \
+ usartDatabits8, /* 8 databits. */ \
+ true, /* Master mode. */ \
+ false, /* Send least significant bit first. */ \
+ usartClockMode0, /* Clock idle low, sample on rising edge. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ false /* No AUTOTX mode. */ \
+ }
#else
#define USART_INITSYNC_DEFAULT \
-{ \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 1000000, /* 1 Mbits/s. */ \
- usartDatabits8, /* 8 databits. */ \
- true, /* Master mode. */ \
- false, /* Send least significant bit first. */ \
- usartClockMode0 /* Clock idle low, sample on rising edge. */ \
-}
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 1000000, /* 1 Mbits/s. */ \
+ usartDatabits8, /* 8 databits. */ \
+ true, /* Master mode. */ \
+ false, /* Send least significant bit first. */ \
+ usartClockMode0 /* Clock idle low, sample on rising edge. */ \
+ }
#endif
-
/** IrDA mode init structure. Inherited from asynchronous mode init structure */
-typedef struct
-{
+typedef struct {
/** General Async initialization structure. */
USART_InitAsync_TypeDef async;
@@ -533,77 +569,145 @@
USART_IrDAPrsSel_Typedef irPrsSel;
} USART_InitIrDA_TypeDef;
-
/** Default config for IrDA mode init structure. */
+#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
-#define USART_INITIRDA_DEFAULT \
-{ \
- { \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 115200, /* 115200 bits/s. */ \
- usartOVS16, /* 16x oversampling. */ \
- usartDatabits8, /* 8 databits. */ \
- usartEvenParity, /* Even parity. */ \
- usartStopbits1, /* 1 stopbit. */ \
- false, /* Do not disable majority vote. */ \
- false, /* Not USART PRS input mode. */ \
- usartPrsRxCh0, /* PRS channel 0. */ \
- false, /* Auto CS functionality enable/disable switch */ \
- 0, /* Auto CS Hold cycles */ \
- 0 /* Auto CS Setup cycles */ \
- }, \
- false, /* Rx invert disabled. */ \
- false, /* Filtering disabled. */ \
- usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
- false, /* Routing to PRS is disabled. */ \
- usartIrDAPrsCh0 /* PRS channel 0. */ \
-}
+#define USART_INITIRDA_DEFAULT \
+ { \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartEvenParity,/* Even parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ false, /* Auto CS functionality enable/disable switch */ \
+ 0, /* Auto CS Hold cycles */ \
+ 0, /* Auto CS Setup cycles */ \
+ usartHwFlowControlNone /* No HW flow control */ \
+ }, \
+ false, /* Rx invert disabled. */ \
+ false, /* Filtering disabled. */ \
+ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
+ false, /* Routing to PRS is disabled. */ \
+ usartIrDAPrsCh0 /* PRS channel 0. */ \
+ }
#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
-#define USART_INITIRDA_DEFAULT \
-{ \
- { \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 115200, /* 115200 bits/s. */ \
- usartOVS16, /* 16x oversampling. */ \
- usartDatabits8, /* 8 databits. */ \
- usartEvenParity, /* Even parity. */ \
- usartStopbits1, /* 1 stopbit. */ \
- false, /* Do not disable majority vote. */ \
- false, /* Not USART PRS input mode. */ \
- usartPrsRxCh0 /* PRS channel 0. */ \
- }, \
- false, /* Rx invert disabled. */ \
- false, /* Filtering disabled. */ \
- usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
- false, /* Routing to PRS is disabled. */ \
- usartIrDAPrsCh0 /* PRS channel 0. */ \
-}
+#define USART_INITIRDA_DEFAULT \
+ { \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartEvenParity,/* Even parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ usartHwFlowControlNone /* No HW flow control */ \
+ }, \
+ false, /* Rx invert disabled. */ \
+ false, /* Filtering disabled. */ \
+ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
+ false, /* Routing to PRS is disabled. */ \
+ usartIrDAPrsCh0 /* PRS channel 0. */ \
+ }
+#else
+#define USART_INITIRDA_DEFAULT \
+ { \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartEvenParity,/* Even parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ usartHwFlowControlNone /* No HW flow control */ \
+ }, \
+ false, /* Rx invert disabled. */ \
+ false, /* Filtering disabled. */ \
+ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
+ false, /* Routing to PRS is disabled. */ \
+ usartIrDAPrsCh0 /* PRS channel 0. */ \
+ }
+#endif
#else
-#define USART_INITIRDA_DEFAULT \
-{ \
- { \
- usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 115200, /* 115200 bits/s. */ \
- usartOVS16, /* 16x oversampling. */ \
- usartDatabits8, /* 8 databits. */ \
- usartEvenParity, /* Even parity. */ \
- usartStopbits1 /* 1 stopbit. */ \
- }, \
- false, /* Rx invert disabled. */ \
- false, /* Filtering disabled. */ \
- usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
- false, /* Routing to PRS is disabled. */ \
- usartIrDAPrsCh0 /* PRS channel 0. */ \
-}
+#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
+#define USART_INITIRDA_DEFAULT \
+ { \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartEvenParity,/* Even parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ false, /* Auto CS functionality enable/disable switch */ \
+ 0, /* Auto CS Hold cycles */ \
+ 0 /* Auto CS Setup cycles */ \
+ }, \
+ false, /* Rx invert disabled. */ \
+ false, /* Filtering disabled. */ \
+ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
+ false, /* Routing to PRS is disabled. */ \
+ usartIrDAPrsCh0 /* PRS channel 0. */ \
+ }
+#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
+#define USART_INITIRDA_DEFAULT \
+ { \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartEvenParity,/* Even parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0 /* PRS channel 0. */ \
+ }, \
+ false, /* Rx invert disabled. */ \
+ false, /* Filtering disabled. */ \
+ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
+ false, /* Routing to PRS is disabled. */ \
+ usartIrDAPrsCh0 /* PRS channel 0. */ \
+ }
+#else
+#define USART_INITIRDA_DEFAULT \
+ { \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartEvenParity,/* Even parity. */ \
+ usartStopbits1 /* 1 stopbit. */ \
+ }, \
+ false, /* Rx invert disabled. */ \
+ false, /* Filtering disabled. */ \
+ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
+ false, /* Routing to PRS is disabled. */ \
+ usartIrDAPrsCh0 /* PRS channel 0. */ \
+ }
+#endif
#endif
#if defined(_USART_I2SCTRL_MASK)
/** I2S mode init structure. Inherited from synchronous mode init structure */
-typedef struct
-{
+typedef struct {
/** General Sync initialization structure. */
USART_InitSync_TypeDef sync;
@@ -625,53 +729,52 @@
bool mono;
} USART_InitI2s_TypeDef;
-
/** Default config for I2S mode init structure. */
#if defined(_USART_TIMING_CSHOLD_MASK)
#define USART_INITI2S_DEFAULT \
-{ \
{ \
- usartEnableTx, /* Enable TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 1000000, /* Baudrate 1M bits/s. */ \
- usartDatabits16, /* 16 databits. */ \
- true, /* Operate as I2S master. */ \
- true, /* Most significant bit first. */ \
- usartClockMode0, /* Clock idle low, sample on rising edge. */ \
- false, /* Don't enable USARTRx via PRS. */ \
- usartPrsRxCh0, /* PRS channel selection (dummy). */ \
- false, /* Disable AUTOTX mode. */ \
- false, /* No AUTOCS mode */ \
- 0, /* Auto CS Hold cycles */ \
- 0 /* Auto CS Setup cycles */ \
- }, \
- usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
- true, /* Delay on I2S data. */ \
- false, /* No DMA split. */ \
- usartI2sJustifyLeft, /* Data is left-justified within the frame */ \
- false /* Stereo mode. */ \
-}
+ { \
+ usartEnableTx, /* Enable TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 1000000, /* Baudrate 1M bits/s. */ \
+ usartDatabits16, /* 16 databits. */ \
+ true, /* Operate as I2S master. */ \
+ true, /* Most significant bit first. */ \
+ usartClockMode0, /* Clock idle low, sample on rising edge. */ \
+ false, /* Don't enable USARTRx via PRS. */ \
+ usartPrsRxCh0, /* PRS channel selection (dummy). */ \
+ false, /* Disable AUTOTX mode. */ \
+ false, /* No AUTOCS mode */ \
+ 0, /* Auto CS Hold cycles */ \
+ 0 /* Auto CS Setup cycles */ \
+ }, \
+ usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
+ true, /* Delay on I2S data. */ \
+ false, /* No DMA split. */ \
+ usartI2sJustifyLeft,/* Data is left-justified within the frame */ \
+ false /* Stereo mode. */ \
+ }
#else
#define USART_INITI2S_DEFAULT \
-{ \
{ \
- usartEnableTx, /* Enable TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 1000000, /* Baudrate 1M bits/s. */ \
- usartDatabits16, /* 16 databits. */ \
- true, /* Operate as I2S master. */ \
- true, /* Most significant bit first. */ \
- usartClockMode0, /* Clock idle low, sample on rising edge. */ \
- false, /* Don't enable USARTRx via PRS. */ \
- usartPrsRxCh0, /* PRS channel selection (dummy). */ \
- false /* Disable AUTOTX mode. */ \
- }, \
- usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
- true, /* Delay on I2S data. */ \
- false, /* No DMA split. */ \
- usartI2sJustifyLeft, /* Data is left-justified within the frame */ \
- false /* Stereo mode. */ \
-}
+ { \
+ usartEnableTx, /* Enable TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 1000000, /* Baudrate 1M bits/s. */ \
+ usartDatabits16, /* 16 databits. */ \
+ true, /* Operate as I2S master. */ \
+ true, /* Most significant bit first. */ \
+ usartClockMode0, /* Clock idle low, sample on rising edge. */ \
+ false, /* Don't enable USARTRx via PRS. */ \
+ usartPrsRxCh0, /* PRS channel selection (dummy). */ \
+ false /* Disable AUTOTX mode. */ \
+ }, \
+ usartI2sFormatW16D16,/* 16-bit word, 16-bit data */ \
+ true, /* Delay on I2S data. */ \
+ false, /* No DMA split. */ \
+ usartI2sJustifyLeft,/* Data is left-justified within the frame */ \
+ false /* Stereo mode. */ \
+ }
#endif
#endif
@@ -759,7 +862,6 @@
usart->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more USART interrupts.
@@ -776,7 +878,6 @@
usart->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more USART interrupts.
@@ -798,7 +899,6 @@
usart->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending USART interrupt flags.
@@ -818,7 +918,6 @@
return usart->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending USART interrupt flags.
@@ -850,7 +949,6 @@
return usart->IF & ien;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending USART interrupts from SW.
@@ -867,7 +965,6 @@
usart->IFS = flags;
}
-
/***************************************************************************//**
* @brief
* Get USART STATUS register.
@@ -890,7 +987,6 @@
uint32_t USART_RxDoubleExt(USART_TypeDef *usart);
uint16_t USART_RxExt(USART_TypeDef *usart);
-
/***************************************************************************//**
* @brief
* Receive one 4-8 bit frame, (or part of 10-16 bit frame).
@@ -924,7 +1020,6 @@
return (uint8_t)usart->RXDATA;
}
-
/***************************************************************************//**
* @brief
* Receive two 4-8 bit frames, or one 10-16 bit frame.
@@ -962,7 +1057,6 @@
return (uint16_t)usart->RXDOUBLE;
}
-
/***************************************************************************//**
* @brief
* Receive two 4-9 bit frames, or one 10-16 bit frame with extended
@@ -998,7 +1092,6 @@
return usart->RXDOUBLEX;
}
-
/***************************************************************************//**
* @brief
* Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended
@@ -1039,7 +1132,6 @@
void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data);
void USART_TxExt(USART_TypeDef *usart, uint16_t data);
-
/** @} (end addtogroup USART) */
/** @} (end addtogroup emlib) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_vcmp.h
* @brief Voltage Comparator (VCMP) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -58,8 +58,7 @@
******************************************************************************/
/** Warm-up Time in High Frequency Peripheral Clock cycles */
-typedef enum
-{
+typedef enum {
/** 4 cycles */
vcmpWarmTime4Cycles = _VCMP_CTRL_WARMTIME_4CYCLES,
/** 8 cycles */
@@ -79,8 +78,7 @@
} VCMP_WarmTime_TypeDef;
/** Hyseresis configuration */
-typedef enum
-{
+typedef enum {
/** Normal operation, no hysteresis */
vcmpHystNone,
/** Digital output will not toggle until positive edge is at least
@@ -93,8 +91,7 @@
******************************************************************************/
/** VCMP Initialization structure */
-typedef struct
-{
+typedef struct {
/** If set to true, will reduce by half the bias current */
bool halfBias;
/** BIAS current configuration, depends on halfBias setting,
@@ -121,18 +118,18 @@
/** Default VCMP initialization structure */
#define VCMP_INIT_DEFAULT \
-{ \
- true, /** Half Bias enabled */ \
- 0x7, /** Bias curernt 0.7 uA when half bias enabled */ \
- false, /** Falling edge sense not enabled */ \
- false, /** Rising edge sense not enabled */ \
- vcmpWarmTime4Cycles, /** 4 clock cycles warm-up time */ \
- vcmpHystNone, /** No hysteresis */ \
- 0, /** 0 in digital ouput when inactive */ \
- true, /** Do not use low power reference */ \
- 39, /** Trigger level just below 3V */ \
- true, /** Enable after init */ \
-}
+ { \
+ true, /** Half Bias enabled */ \
+ 0x7, /** Bias curernt 0.7 uA when half bias enabled */ \
+ false, /** Falling edge sense not enabled */ \
+ false, /** Rising edge sense not enabled */ \
+ vcmpWarmTime4Cycles, /** 4 clock cycles warm-up time */ \
+ vcmpHystNone, /** No hysteresis */ \
+ 0, /** 0 in digital ouput when inactive */ \
+ true, /** Do not use low power reference */ \
+ 39, /** Trigger level just below 3V */ \
+ true, /** Enable after init */ \
+ }
/*******************************************************************************
***************************** PROTOTYPES **********************************
@@ -151,7 +148,6 @@
VCMP->CTRL |= VCMP_CTRL_EN;
}
-
/***************************************************************************//**
* @brief
* Disable Voltage Comparator
@@ -161,7 +157,6 @@
VCMP->CTRL &= ~VCMP_CTRL_EN;
}
-
/***************************************************************************//**
* @brief
* Calculate voltage to trigger level
@@ -177,7 +172,6 @@
return (uint32_t)((v - (float)1.667) / (float)0.034);
}
-
/***************************************************************************//**
* @brief
* Returns true, if Voltage Comparator indicated VDD < trigger level, else
@@ -185,17 +179,13 @@
******************************************************************************/
__STATIC_INLINE bool VCMP_VDDLower(void)
{
- if (VCMP->STATUS & VCMP_STATUS_VCMPOUT)
- {
+ if (VCMP->STATUS & VCMP_STATUS_VCMPOUT) {
return false;
- }
- else
- {
+ } else {
return true;
}
}
-
/***************************************************************************//**
* @brief
* Returns true, if Voltage Comparator indicated VDD > trigger level, else
@@ -203,34 +193,26 @@
******************************************************************************/
__STATIC_INLINE bool VCMP_VDDHigher(void)
{
- if (VCMP->STATUS & VCMP_STATUS_VCMPOUT)
- {
+ if (VCMP->STATUS & VCMP_STATUS_VCMPOUT) {
return true;
- }
- else
- {
+ } else {
return false;
}
}
-
/***************************************************************************//**
* @brief
* VCMP output is ready
******************************************************************************/
__STATIC_INLINE bool VCMP_Ready(void)
{
- if (VCMP->STATUS & VCMP_STATUS_VCMPACT)
- {
+ if (VCMP->STATUS & VCMP_STATUS_VCMPACT) {
return true;
- }
- else
- {
+ } else {
return false;
}
}
-
/***************************************************************************//**
* @brief
* Clear one or more pending VCMP interrupts.
@@ -245,7 +227,6 @@
VCMP->IFC = flags;
}
-
/***************************************************************************//**
* @brief
* Set one or more pending VCMP interrupts from SW.
@@ -260,7 +241,6 @@
VCMP->IFS = flags;
}
-
/***************************************************************************//**
* @brief
* Disable one or more VCMP interrupts
@@ -275,7 +255,6 @@
VCMP->IEN &= ~flags;
}
-
/***************************************************************************//**
* @brief
* Enable one or more VCMP interrupts
@@ -290,7 +269,6 @@
VCMP->IEN |= flags;
}
-
/***************************************************************************//**
* @brief
* Get pending VCMP interrupt flags
@@ -307,7 +285,6 @@
return VCMP->IF;
}
-
/***************************************************************************//**
* @brief
* Get enabled and pending VCMP interrupt flags.
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vdac.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vdac.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_vdac.h
* @brief Digital to Analog Converter (VDAC) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -44,7 +44,6 @@
extern "C" {
#endif
-
/***************************************************************************//**
* @addtogroup emlib
* @{
@@ -103,8 +102,7 @@
******************************************************************************/
/** Channel refresh period. */
-typedef enum
-{
+typedef enum {
vdacRefresh8 = _VDAC_CTRL_REFRESHPERIOD_8CYCLES, /**< Refresh every 8 clock cycles. */
vdacRefresh16 = _VDAC_CTRL_REFRESHPERIOD_16CYCLES, /**< Refresh every 16 clock cycles. */
vdacRefresh32 = _VDAC_CTRL_REFRESHPERIOD_32CYCLES, /**< Refresh every 32 clock cycles. */
@@ -112,8 +110,7 @@
} VDAC_Refresh_TypeDef;
/** Reference voltage for VDAC. */
-typedef enum
-{
+typedef enum {
vdacRef1V25Ln = _VDAC_CTRL_REFSEL_1V25LN, /**< Internal low noise 1.25 V bandgap reference. */
vdacRef2V5Ln = _VDAC_CTRL_REFSEL_2V5LN, /**< Internal low noise 2.5 V bandgap reference. */
vdacRef1V25 = _VDAC_CTRL_REFSEL_1V25, /**< Internal 1.25 V bandgap reference. */
@@ -123,25 +120,31 @@
} VDAC_Ref_TypeDef;
/** Peripheral Reflex System signal used to trig VDAC channel conversion. */
-typedef enum
-{
- vdacPrsSelCh0 = _VDAC_CH0CTRL_PRSSEL_PRSCH0 , /**< PRS ch 0 triggers conversion. */
- vdacPrsSelCh1 = _VDAC_CH0CTRL_PRSSEL_PRSCH1 , /**< PRS ch 1 triggers conversion. */
- vdacPrsSelCh2 = _VDAC_CH0CTRL_PRSSEL_PRSCH2 , /**< PRS ch 2 triggers conversion. */
- vdacPrsSelCh3 = _VDAC_CH0CTRL_PRSSEL_PRSCH3 , /**< PRS ch 3 triggers conversion. */
- vdacPrsSelCh4 = _VDAC_CH0CTRL_PRSSEL_PRSCH4 , /**< PRS ch 4 triggers conversion. */
- vdacPrsSelCh5 = _VDAC_CH0CTRL_PRSSEL_PRSCH5 , /**< PRS ch 5 triggers conversion. */
- vdacPrsSelCh6 = _VDAC_CH0CTRL_PRSSEL_PRSCH6 , /**< PRS ch 6 triggers conversion. */
- vdacPrsSelCh7 = _VDAC_CH0CTRL_PRSSEL_PRSCH7 , /**< PRS ch 7 triggers conversion. */
- vdacPrsSelCh8 = _VDAC_CH0CTRL_PRSSEL_PRSCH8 , /**< PRS ch 8 triggers conversion. */
- vdacPrsSelCh9 = _VDAC_CH0CTRL_PRSSEL_PRSCH9 , /**< PRS ch 9 triggers conversion. */
+typedef enum {
+ vdacPrsSelCh0 = _VDAC_CH0CTRL_PRSSEL_PRSCH0, /**< PRS ch 0 triggers conversion. */
+ vdacPrsSelCh1 = _VDAC_CH0CTRL_PRSSEL_PRSCH1, /**< PRS ch 1 triggers conversion. */
+ vdacPrsSelCh2 = _VDAC_CH0CTRL_PRSSEL_PRSCH2, /**< PRS ch 2 triggers conversion. */
+ vdacPrsSelCh3 = _VDAC_CH0CTRL_PRSSEL_PRSCH3, /**< PRS ch 3 triggers conversion. */
+ vdacPrsSelCh4 = _VDAC_CH0CTRL_PRSSEL_PRSCH4, /**< PRS ch 4 triggers conversion. */
+ vdacPrsSelCh5 = _VDAC_CH0CTRL_PRSSEL_PRSCH5, /**< PRS ch 5 triggers conversion. */
+ vdacPrsSelCh6 = _VDAC_CH0CTRL_PRSSEL_PRSCH6, /**< PRS ch 6 triggers conversion. */
+ vdacPrsSelCh7 = _VDAC_CH0CTRL_PRSSEL_PRSCH7, /**< PRS ch 7 triggers conversion. */
+#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH8)
+ vdacPrsSelCh8 = _VDAC_CH0CTRL_PRSSEL_PRSCH8, /**< PRS ch 8 triggers conversion. */
+#endif
+#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH9)
+ vdacPrsSelCh9 = _VDAC_CH0CTRL_PRSSEL_PRSCH9, /**< PRS ch 9 triggers conversion. */
+#endif
+#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH10)
vdacPrsSelCh10 = _VDAC_CH0CTRL_PRSSEL_PRSCH10, /**< PRS ch 10 triggers conversion. */
+#endif
+#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH11)
vdacPrsSelCh11 = _VDAC_CH0CTRL_PRSSEL_PRSCH11, /**< PRS ch 11 triggers conversion. */
+#endif
} VDAC_PrsSel_TypeDef;
/** Channel conversion trigger mode. */
-typedef enum
-{
+typedef enum {
vdacTrigModeSw = _VDAC_CH0CTRL_TRIGMODE_SW, /**< Channel is triggered by CHnDATA or COMBDATA write. */
vdacTrigModePrs = _VDAC_CH0CTRL_TRIGMODE_PRS, /**< Channel is triggered by PRS input. */
vdacTrigModeRefresh = _VDAC_CH0CTRL_TRIGMODE_REFRESH, /**< Channel is triggered by Refresh timer. */
@@ -155,8 +158,7 @@
******************************************************************************/
/** VDAC init structure, common for both channels. */
-typedef struct
-{
+typedef struct {
/** Select between main and alternate output path calibration values. */
bool mainCalibration;
@@ -190,23 +192,22 @@
} VDAC_Init_TypeDef;
/** Default config for VDAC init structure. */
-#define VDAC_INIT_DEFAULT \
-{ \
- true, /* Use main output path calibration values. */ \
- false, /* Use synchronous clock mode. */ \
- false, /* Turn off between sample off conversions.*/ \
- vdacRefresh8, /* Refresh every 8th cycle. */ \
- 0, /* No prescaling. */ \
- vdacRef1V25Ln, /* 1.25V internal low noise reference. */ \
- false, /* Do not reset prescaler on CH 0 start. */ \
- false, /* VDAC output enable always on. */ \
- false, /* Disable sine mode. */ \
- false /* Single ended mode. */ \
-}
+#define VDAC_INIT_DEFAULT \
+ { \
+ true, /* Use main output path calibration values. */ \
+ false, /* Use synchronous clock mode. */ \
+ false, /* Turn off between sample off conversions.*/ \
+ vdacRefresh8, /* Refresh every 8th cycle. */ \
+ 0, /* No prescaling. */ \
+ vdacRef1V25Ln, /* 1.25V internal low noise reference. */ \
+ false, /* Do not reset prescaler on CH 0 start. */ \
+ false, /* VDAC output enable always on. */ \
+ false, /* Disable sine mode. */ \
+ false /* Single ended mode. */ \
+ }
/** VDAC channel init structure. */
-typedef struct
-{
+typedef struct {
/** Enable channel. */
bool enable;
@@ -227,14 +228,14 @@
} VDAC_InitChannel_TypeDef;
/** Default config for VDAC channel init structure. */
-#define VDAC_INITCHANNEL_DEFAULT \
-{ \
- false, /* Leave channel disabled when init done. */ \
- vdacPrsSelCh0, /* PRS CH 0 triggers conversion. */ \
- false, /* Treat PRS channel as a synchronous signal. */ \
- vdacTrigModeSw, /* Conversion trigged by CH0DATA or COMBDATA write. */ \
- false, /* Channel conversion set to continous. */ \
-}
+#define VDAC_INITCHANNEL_DEFAULT \
+ { \
+ false, /* Leave channel disabled when init done. */ \
+ vdacPrsSelCh0, /* PRS CH 0 triggers conversion. */ \
+ false, /* Treat PRS channel as a synchronous signal. */ \
+ vdacTrigModeSw, /* Conversion trigged by CH0DATA or COMBDATA write. */ \
+ false, /* Channel conversion set to continous. */ \
+ }
/*******************************************************************************
***************************** PROTOTYPES **********************************
@@ -266,7 +267,7 @@
__STATIC_INLINE void VDAC_Channel0OutputSet(VDAC_TypeDef *vdac,
uint32_t value)
{
- EFM_ASSERT(value<=_VDAC_CH0DATA_MASK);
+ EFM_ASSERT(value <= _VDAC_CH0DATA_MASK);
vdac->CH0DATA = value;
}
@@ -287,7 +288,7 @@
__STATIC_INLINE void VDAC_Channel1OutputSet(VDAC_TypeDef *vdac,
uint32_t value)
{
- EFM_ASSERT(value<=_VDAC_CH1DATA_MASK);
+ EFM_ASSERT(value <= _VDAC_CH1DATA_MASK);
vdac->CH1DATA = value;
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_version.h
* @brief Assign correct part number for include file
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -52,23 +52,26 @@
* @{
******************************************************************************/
+/* *INDENT-OFF* */
/** Version number of emlib peripheral API. */
-#define _EMLIB_VERSION 5.1.2
+#define _EMLIB_VERSION 5.3.3
+/* *INDENT-ON* */
/** Major version of emlib. Bumped when incompatible API changes introduced. */
#define _EMLIB_VERSION_MAJOR 5
/** Minor version of emlib. Bumped when functionality is added in a backwards-
compatible manner. */
-#define _EMLIB_VERSION_MINOR 1
+#define _EMLIB_VERSION_MINOR 3
/** Patch revision of emlib. Bumped when adding backwards-compatible bug
fixes.*/
-#define _EMLIB_VERSION_PATCH 2
+#define _EMLIB_VERSION_PATCH 3
-
+/* *INDENT-OFF* */
/** Version number of targeted CMSIS package. */
#define _CMSIS_VERSION 4.5.0
+/* *INDENT-ON* */
/** Major version of CMSIS. */
#define _CMSIS_VERSION_MAJOR 4
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_wdog.h
* @brief Watchdog (WDOG) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -30,7 +30,6 @@
*
******************************************************************************/
-
#ifndef EM_WDOG_H
#define EM_WDOG_H
@@ -58,16 +57,14 @@
******************************************************************************/
/** Watchdog clock selection. */
-typedef enum
-{
+typedef enum {
wdogClkSelULFRCO = _WDOG_CTRL_CLKSEL_ULFRCO, /**< Ultra low frequency (1 kHz) clock */
wdogClkSelLFRCO = _WDOG_CTRL_CLKSEL_LFRCO, /**< Low frequency RC oscillator */
wdogClkSelLFXO = _WDOG_CTRL_CLKSEL_LFXO /**< Low frequency crystal oscillator */
} WDOG_ClkSel_TypeDef;
/** Watchdog period selection. */
-typedef enum
-{
+typedef enum {
wdogPeriod_9 = 0x0, /**< 9 clock periods */
wdogPeriod_17 = 0x1, /**< 17 clock periods */
wdogPeriod_33 = 0x2, /**< 33 clock periods */
@@ -86,11 +83,9 @@
wdogPeriod_256k = 0xF /**< 262145 clock periods */
} WDOG_PeriodSel_TypeDef;
-
-#if defined( _WDOG_CTRL_WARNSEL_MASK )
+#if defined(_WDOG_CTRL_WARNSEL_MASK)
/** Select watchdog warning timeout period as percentage of timeout. */
-typedef enum
-{
+typedef enum {
wdogWarnDisable = 0,
wdogWarnTime25pct = 1,
wdogWarnTime50pct = 2,
@@ -98,10 +93,9 @@
} WDOG_WarnSel_TypeDef;
#endif
-#if defined( _WDOG_CTRL_WINSEL_MASK )
+#if defined(_WDOG_CTRL_WINSEL_MASK)
/** Select watchdog illegal window limit. */
-typedef enum
-{
+typedef enum {
wdogIllegalWindowDisable = 0,
wdogIllegalWindowTime12_5pct = 1,
wdogIllegalWindowTime25_0pct = 2,
@@ -118,8 +112,7 @@
******************************************************************************/
/** Watchdog initialization structure. */
-typedef struct
-{
+typedef struct {
/** Enable watchdog when init completed. */
bool enable;
@@ -147,60 +140,58 @@
/** Watchdog timeout period. */
WDOG_PeriodSel_TypeDef perSel;
-#if defined( _WDOG_CTRL_WARNSEL_MASK )
+#if defined(_WDOG_CTRL_WARNSEL_MASK)
/** Select warning time as % of the watchdog timeout */
WDOG_WarnSel_TypeDef warnSel;
#endif
-#if defined( _WDOG_CTRL_WINSEL_MASK )
+#if defined(_WDOG_CTRL_WINSEL_MASK)
/** Select illegal window time as % of the watchdog timeout */
WDOG_WinSel_TypeDef winSel;
#endif
-#if defined( _WDOG_CTRL_WDOGRSTDIS_MASK )
+#if defined(_WDOG_CTRL_WDOGRSTDIS_MASK)
/** Disable watchdog reset output if true */
bool resetDisable;
#endif
-
} WDOG_Init_TypeDef;
/** Suggested default config for WDOG init structure. */
-#if defined( _WDOG_CTRL_WARNSEL_MASK ) \
- && defined( _WDOG_CTRL_WDOGRSTDIS_MASK ) \
- && defined( _WDOG_CTRL_WINSEL_MASK )
-#define WDOG_INIT_DEFAULT \
-{ \
- true, /* Start watchdog when init done */ \
- false, /* WDOG not counting during debug halt */ \
- false, /* WDOG not counting when in EM2 */ \
- false, /* WDOG not counting when in EM3 */ \
- false, /* EM4 can be entered */ \
- false, /* Do not block disabling LFRCO/LFXO in CMU */ \
- false, /* Do not lock WDOG configuration (if locked,
- reset needed to unlock) */ \
- wdogClkSelULFRCO, /* Select 1kHZ WDOG oscillator */ \
- wdogPeriod_256k, /* Set longest possible timeout period */ \
- wdogWarnDisable, /* Disable warning interrupt */ \
- wdogIllegalWindowDisable, /* Disable illegal window interrupt */ \
- false /* Do not disable reset */ \
-}
+#if defined(_WDOG_CTRL_WARNSEL_MASK) \
+ && defined(_WDOG_CTRL_WDOGRSTDIS_MASK) \
+ && defined(_WDOG_CTRL_WINSEL_MASK)
+#define WDOG_INIT_DEFAULT \
+ { \
+ true, /* Start watchdog when init done */ \
+ false, /* WDOG not counting during debug halt */ \
+ false, /* WDOG not counting when in EM2 */ \
+ false, /* WDOG not counting when in EM3 */ \
+ false, /* EM4 can be entered */ \
+ false, /* Do not block disabling LFRCO/LFXO in CMU */ \
+ false, /* Do not lock WDOG configuration (if locked,
+ reset needed to unlock) */ \
+ wdogClkSelULFRCO, /* Select 1kHZ WDOG oscillator */ \
+ wdogPeriod_256k, /* Set longest possible timeout period */ \
+ wdogWarnDisable, /* Disable warning interrupt */ \
+ wdogIllegalWindowDisable, /* Disable illegal window interrupt */ \
+ false /* Do not disable reset */ \
+ }
#else
-#define WDOG_INIT_DEFAULT \
-{ \
- true, /* Start watchdog when init done */ \
- false, /* WDOG not counting during debug halt */ \
- false, /* WDOG not counting when in EM2 */ \
- false, /* WDOG not counting when in EM3 */ \
- false, /* EM4 can be entered */ \
- false, /* Do not block disabling LFRCO/LFXO in CMU */ \
- false, /* Do not lock WDOG configuration (if locked,
- reset needed to unlock) */ \
- wdogClkSelULFRCO, /* Select 1kHZ WDOG oscillator */ \
- wdogPeriod_256k /* Set longest possible timeout period */ \
-}
+#define WDOG_INIT_DEFAULT \
+ { \
+ true, /* Start watchdog when init done */ \
+ false, /* WDOG not counting during debug halt */ \
+ false, /* WDOG not counting when in EM2 */ \
+ false, /* WDOG not counting when in EM3 */ \
+ false, /* EM4 can be entered */ \
+ false, /* Do not block disabling LFRCO/LFXO in CMU */ \
+ false, /* Do not lock WDOG configuration (if locked,
+ reset needed to unlock) */ \
+ wdogClkSelULFRCO, /* Select 1kHZ WDOG oscillator */ \
+ wdogPeriod_256k /* Set longest possible timeout period */ \
+ }
#endif
-
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
@@ -210,8 +201,7 @@
void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init);
void WDOGn_Lock(WDOG_TypeDef *wdog);
-
-#if defined( _WDOG_IF_MASK )
+#if defined(_WDOG_IF_MASK)
/***************************************************************************//**
* @brief
* Clear one or more pending WDOG interrupts.
@@ -325,7 +315,6 @@
}
#endif
-
/** Default WDOG instance for deprecated functions. */
#if !defined(DEFAULT_WDOG)
#if defined(WDOG)
@@ -352,7 +341,6 @@
WDOGn_Enable(DEFAULT_WDOG, enable);
}
-
/***************************************************************************//**
* @brief
* Feed the watchdog.
@@ -366,7 +354,6 @@
WDOGn_Feed(DEFAULT_WDOG);
}
-
/***************************************************************************//**
* @brief
* Initialize watchdog (assuming the watchdog configuration has not been
@@ -385,7 +372,6 @@
WDOGn_Init(DEFAULT_WDOG, init);
}
-
/***************************************************************************//**
* @brief
* Lock the watchdog configuration.
@@ -399,7 +385,6 @@
WDOGn_Lock(DEFAULT_WDOG);
}
-
/** @} (end addtogroup WDOG) */
/** @} (end addtogroup emlib) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_acmp.c
* @brief Analog Comparator (ACMP) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -30,7 +30,6 @@
*
******************************************************************************/
-
#include "em_acmp.h"
#if defined(ACMP_COUNT) && (ACMP_COUNT > 0)
@@ -54,13 +53,17 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-
/** Validation of ACMP register block pointer reference
* for assert statements. */
#if (ACMP_COUNT == 1)
#define ACMP_REF_VALID(ref) ((ref) == ACMP0)
#elif (ACMP_COUNT == 2)
#define ACMP_REF_VALID(ref) (((ref) == ACMP0) || ((ref) == ACMP1))
+#elif (ACMP_COUNT == 4)
+#define ACMP_REF_VALID(ref) (((ref) == ACMP0) \
+ || ((ref) == ACMP1) \
+ || ((ref) == ACMP2) \
+ || ((ref) == ACMP3))
#else
#error Undefined number of analog comparators (ACMP).
#endif
@@ -75,6 +78,8 @@
#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTE_LOCATION_LOC1
#elif defined(_ACMP_ROUTELOC0_OUTLOC_LOC31)
#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTELOC0_OUTLOC_LOC31
+#elif defined(_ACMP_ROUTELOC0_OUTLOC_MASK)
+#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTELOC0_OUTLOC_MASK
#else
#error Undefined max route locations
#endif
@@ -120,8 +125,8 @@
#endif
/* Make sure biasprog is within bounds */
- EFM_ASSERT(init->biasProg <=
- (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT));
+ EFM_ASSERT(init->biasProg
+ <= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT));
/* Set control register. No need to set interrupt modes */
acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT)
@@ -138,7 +143,7 @@
#if defined(_ACMP_CTRL_ACCURACY_MASK)
| ACMP_CTRL_ACCURACY_HIGH
#endif
- ;
+ ;
#if defined(_ACMP_HYSTERESIS0_MASK)
acmp->HYSTERESIS0 = (init->vddLevelHigh << _ACMP_HYSTERESIS0_DIVVA_SHIFT)
@@ -162,7 +167,7 @@
| ACMP_INPUTSEL_VASEL_VDD
| ACMP_INPUTSEL_NEGSEL_VADIV
#endif
- ;
+ ;
/* Enable ACMP if requested. */
BUS_RegBitWrite(&(acmp->CTRL), _ACMP_CTRL_EN_SHIFT, init->enable);
@@ -197,7 +202,7 @@
/* Set channel as positive channel in ACMP */
BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_POSSEL_MASK,
- channel << _ACMP_INPUTSEL_POSSEL_SHIFT);
+ channel << _ACMP_INPUTSEL_POSSEL_SHIFT);
}
/***************************************************************************//**
@@ -312,7 +317,7 @@
/* Set GPIO inversion */
BUS_RegMaskedWrite(&acmp->CTRL, _ACMP_CTRL_GPIOINV_MASK,
- invert << _ACMP_CTRL_GPIOINV_SHIFT);
+ invert << _ACMP_CTRL_GPIOINV_SHIFT);
#if defined(_ACMP_ROUTE_MASK)
acmp->ROUTE = (location << _ACMP_ROUTE_LOCATION_SHIFT)
@@ -377,8 +382,8 @@
EFM_ASSERT(ACMP_REF_VALID(acmp));
/* Make sure biasprog is within bounds */
- EFM_ASSERT(init->biasProg <=
- (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT));
+ EFM_ASSERT(init->biasProg
+ <= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT));
/* Make sure the ACMP is disable since we might be changing the
* ACMP power source */
@@ -411,15 +416,15 @@
acmp->INPUTSEL = (0)
#if defined(_ACMP_INPUTSEL_VLPSEL_MASK)
- | (init->vlpInput << _ACMP_INPUTSEL_VLPSEL_SHIFT)
+ | (init->vlpInput << _ACMP_INPUTSEL_VLPSEL_SHIFT)
#endif
#if defined(_ACMP_INPUTSEL_LPREF_MASK)
- | (init->lowPowerReferenceEnabled << _ACMP_INPUTSEL_LPREF_SHIFT)
+ | (init->lowPowerReferenceEnabled << _ACMP_INPUTSEL_LPREF_SHIFT)
#endif
#if defined(_ACMP_INPUTSEL_VDDLEVEL_MASK)
- | (init->vddLevel << _ACMP_INPUTSEL_VDDLEVEL_SHIFT)
+ | (init->vddLevel << _ACMP_INPUTSEL_VDDLEVEL_SHIFT)
#endif
- ;
+ ;
/* Enable ACMP if requested. */
BUS_RegBitWrite(&(acmp->CTRL), _ACMP_CTRL_EN_SHIFT, init->enable);
@@ -443,11 +448,11 @@
EFM_ASSERT(vaconfig->div1 < 64);
BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VASEL_MASK,
- vaconfig->input << _ACMP_INPUTSEL_VASEL_SHIFT);
+ vaconfig->input << _ACMP_INPUTSEL_VASEL_SHIFT);
BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVA_MASK,
- vaconfig->div0 << _ACMP_HYSTERESIS0_DIVVA_SHIFT);
+ vaconfig->div0 << _ACMP_HYSTERESIS0_DIVVA_SHIFT);
BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVA_MASK,
- vaconfig->div1 << _ACMP_HYSTERESIS1_DIVVA_SHIFT);
+ vaconfig->div1 << _ACMP_HYSTERESIS1_DIVVA_SHIFT);
}
#endif
@@ -469,11 +474,11 @@
EFM_ASSERT(vbconfig->div1 < 64);
BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VBSEL_MASK,
- vbconfig->input << _ACMP_INPUTSEL_VBSEL_SHIFT);
+ vbconfig->input << _ACMP_INPUTSEL_VBSEL_SHIFT);
BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVB_MASK,
- vbconfig->div0 << _ACMP_HYSTERESIS0_DIVVB_SHIFT);
+ vbconfig->div0 << _ACMP_HYSTERESIS0_DIVVB_SHIFT);
BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVB_MASK,
- vbconfig->div1 << _ACMP_HYSTERESIS1_DIVVB_SHIFT);
+ vbconfig->div1 << _ACMP_HYSTERESIS1_DIVVB_SHIFT);
}
#endif
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_adc.c
* @brief Analog to Digital Converter (ADC) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -31,7 +31,7 @@
******************************************************************************/
#include "em_adc.h"
-#if defined( ADC_COUNT ) && ( ADC_COUNT > 0 )
+#if defined(ADC_COUNT) && (ADC_COUNT > 0)
#include "em_assert.h"
#include "em_cmu.h"
@@ -59,10 +59,14 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** Validation of ADC register block pointer reference for assert statements. */
+#if (ADC_COUNT == 1)
#define ADC_REF_VALID(ref) ((ref) == ADC0)
+#elif (ADC_COUNT == 2)
+#define ADC_REF_VALID(ref) (((ref) == ADC0) || ((ref) == ADC1))
+#endif
/** Max ADC clock */
-#if defined( _SILICON_LABS_32B_SERIES_0 )
+#if defined(_SILICON_LABS_32B_SERIES_0)
#define ADC_MAX_CLOCK 13000000
#else
#define ADC_MAX_CLOCK 16000000
@@ -72,120 +76,120 @@
#define ADC_MIN_CLOCK 32000
/** Helper defines for selecting ADC calibration and DEVINFO register fields. */
-#if defined( _DEVINFO_ADC0CAL0_1V25_GAIN_MASK )
+#if defined(_DEVINFO_ADC0CAL0_1V25_GAIN_MASK)
#define DEVINFO_ADC0_GAIN1V25_MASK _DEVINFO_ADC0CAL0_1V25_GAIN_MASK
-#elif defined( _DEVINFO_ADC0CAL0_GAIN1V25_MASK )
+#elif defined(_DEVINFO_ADC0CAL0_GAIN1V25_MASK)
#define DEVINFO_ADC0_GAIN1V25_MASK _DEVINFO_ADC0CAL0_GAIN1V25_MASK
#endif
-#if defined( _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT )
+#if defined(_DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT)
#define DEVINFO_ADC0_GAIN1V25_SHIFT _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT
-#elif defined( _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT )
+#elif defined(_DEVINFO_ADC0CAL0_GAIN1V25_SHIFT)
#define DEVINFO_ADC0_GAIN1V25_SHIFT _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT
#endif
-#if defined( _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK )
+#if defined(_DEVINFO_ADC0CAL0_1V25_OFFSET_MASK)
#define DEVINFO_ADC0_OFFSET1V25_MASK _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK
-#elif defined( _DEVINFO_ADC0CAL0_OFFSET1V25_MASK )
+#elif defined(_DEVINFO_ADC0CAL0_OFFSET1V25_MASK)
#define DEVINFO_ADC0_OFFSET1V25_MASK _DEVINFO_ADC0CAL0_OFFSET1V25_MASK
#endif
-#if defined( _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT )
+#if defined(_DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT)
#define DEVINFO_ADC0_OFFSET1V25_SHIFT _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT
-#elif defined( _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT )
+#elif defined(_DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT)
#define DEVINFO_ADC0_OFFSET1V25_SHIFT _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT
#endif
-#if defined( _DEVINFO_ADC0CAL0_2V5_GAIN_MASK )
+#if defined(_DEVINFO_ADC0CAL0_2V5_GAIN_MASK)
#define DEVINFO_ADC0_GAIN2V5_MASK _DEVINFO_ADC0CAL0_2V5_GAIN_MASK
-#elif defined( _DEVINFO_ADC0CAL0_GAIN2V5_MASK )
+#elif defined(_DEVINFO_ADC0CAL0_GAIN2V5_MASK)
#define DEVINFO_ADC0_GAIN2V5_MASK _DEVINFO_ADC0CAL0_GAIN2V5_MASK
#endif
-#if defined( _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT )
+#if defined(_DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT)
#define DEVINFO_ADC0_GAIN2V5_SHIFT _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT
-#elif defined( _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT )
+#elif defined(_DEVINFO_ADC0CAL0_GAIN2V5_SHIFT)
#define DEVINFO_ADC0_GAIN2V5_SHIFT _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT
#endif
-#if defined( _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK )
+#if defined(_DEVINFO_ADC0CAL0_2V5_OFFSET_MASK)
#define DEVINFO_ADC0_OFFSET2V5_MASK _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK
-#elif defined( _DEVINFO_ADC0CAL0_OFFSET2V5_MASK )
+#elif defined(_DEVINFO_ADC0CAL0_OFFSET2V5_MASK)
#define DEVINFO_ADC0_OFFSET2V5_MASK _DEVINFO_ADC0CAL0_OFFSET2V5_MASK
#endif
-#if defined( _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT )
+#if defined(_DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT)
#define DEVINFO_ADC0_OFFSET2V5_SHIFT _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT
-#elif defined( _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT )
+#elif defined(_DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT)
#define DEVINFO_ADC0_OFFSET2V5_SHIFT _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT
#endif
-#if defined( _DEVINFO_ADC0CAL1_VDD_GAIN_MASK )
+#if defined(_DEVINFO_ADC0CAL1_VDD_GAIN_MASK)
#define DEVINFO_ADC0_GAINVDD_MASK _DEVINFO_ADC0CAL1_VDD_GAIN_MASK
-#elif defined( _DEVINFO_ADC0CAL1_GAINVDD_MASK )
+#elif defined(_DEVINFO_ADC0CAL1_GAINVDD_MASK)
#define DEVINFO_ADC0_GAINVDD_MASK _DEVINFO_ADC0CAL1_GAINVDD_MASK
#endif
-#if defined( _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT )
+#if defined(_DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT)
#define DEVINFO_ADC0_GAINVDD_SHIFT _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT
-#elif defined( _DEVINFO_ADC0CAL1_GAINVDD_SHIFT )
+#elif defined(_DEVINFO_ADC0CAL1_GAINVDD_SHIFT)
#define DEVINFO_ADC0_GAINVDD_SHIFT _DEVINFO_ADC0CAL1_GAINVDD_SHIFT
#endif
-#if defined( _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK )
+#if defined(_DEVINFO_ADC0CAL1_VDD_OFFSET_MASK)
#define DEVINFO_ADC0_OFFSETVDD_MASK _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK
-#elif defined( _DEVINFO_ADC0CAL1_OFFSETVDD_MASK )
+#elif defined(_DEVINFO_ADC0CAL1_OFFSETVDD_MASK)
#define DEVINFO_ADC0_OFFSETVDD_MASK _DEVINFO_ADC0CAL1_OFFSETVDD_MASK
#endif
-#if defined( _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT )
+#if defined(_DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT)
#define DEVINFO_ADC0_OFFSETVDD_SHIFT _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT
-#elif defined( _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT )
+#elif defined(_DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT)
#define DEVINFO_ADC0_OFFSETVDD_SHIFT _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT
#endif
-#if defined( _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK )
+#if defined(_DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK)
#define DEVINFO_ADC0_GAIN5VDIFF_MASK _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK
-#elif defined( _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK )
+#elif defined(_DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK)
#define DEVINFO_ADC0_GAIN5VDIFF_MASK _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK
#endif
-#if defined( _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT )
+#if defined(_DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT)
#define DEVINFO_ADC0_GAIN5VDIFF_SHIFT _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT
-#elif defined( _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT )
+#elif defined(_DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT)
#define DEVINFO_ADC0_GAIN5VDIFF_SHIFT _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT
#endif
-#if defined( _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK )
+#if defined(_DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK)
#define DEVINFO_ADC0_OFFSET5VDIFF_MASK _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK
-#elif defined( _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK )
+#elif defined(_DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK)
#define DEVINFO_ADC0_OFFSET5VDIFF_MASK _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK
#endif
-#if defined( _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT )
+#if defined(_DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT)
#define DEVINFO_ADC0_OFFSET5VDIFF_SHIFT _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT
-#elif defined( _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT )
+#elif defined(_DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT)
#define DEVINFO_ADC0_OFFSET5VDIFF_SHIFT _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT
#endif
-#if defined( _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK )
+#if defined(_DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK)
#define DEVINFO_ADC0_OFFSET2XVDD_MASK _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK
-#elif defined( _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK )
+#elif defined(_DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK)
#define DEVINFO_ADC0_OFFSET2XVDD_MASK _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK
#endif
-#if defined( _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT )
+#if defined(_DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT)
#define DEVINFO_ADC0_OFFSET2XVDD_SHIFT _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT
-#elif defined( _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT )
+#elif defined(_DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT)
#define DEVINFO_ADC0_OFFSET2XVDD_SHIFT _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT
#endif
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
#define FIX_ADC_TEMP_BIAS_EN
#endif
+
/** @endcond */
-
/*******************************************************************************
*************************** LOCAL FUNCTIONS *******************************
******************************************************************************/
@@ -220,21 +224,19 @@
uint32_t newCal;
uint32_t mask;
uint32_t shift;
+ __IM uint32_t * diCalReg;
- if (setScanCal)
- {
+ if (setScanCal) {
shift = _ADC_CAL_SCANOFFSET_SHIFT;
mask = ~(_ADC_CAL_SCANOFFSET_MASK
-#if defined( _ADC_CAL_SCANOFFSETINV_MASK )
+#if defined(_ADC_CAL_SCANOFFSETINV_MASK)
| _ADC_CAL_SCANOFFSETINV_MASK
#endif
| _ADC_CAL_SCANGAIN_MASK);
- }
- else
- {
+ } else {
shift = _ADC_CAL_SINGLEOFFSET_SHIFT;
mask = ~(_ADC_CAL_SINGLEOFFSET_MASK
-#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
+#if defined(_ADC_CAL_SINGLEOFFSETINV_MASK)
| _ADC_CAL_SINGLEOFFSETINV_MASK
#endif
| _ADC_CAL_SINGLEGAIN_MASK);
@@ -243,59 +245,70 @@
calReg = adc->CAL & mask;
newCal = 0;
- switch (ref)
- {
+ if (adc == ADC0) {
+ diCalReg = &DEVINFO->ADC0CAL0;
+ }
+#if defined(ADC1)
+ else if (adc == ADC1) {
+ diCalReg = &DEVINFO->ADC1CAL0;
+ }
+#endif
+ else {
+ return;
+ }
+
+ switch (ref) {
case adcRef1V25:
- newCal |= ((DEVINFO->ADC0CAL0 & DEVINFO_ADC0_GAIN1V25_MASK)
+ newCal |= ((diCalReg[0] & DEVINFO_ADC0_GAIN1V25_MASK)
>> DEVINFO_ADC0_GAIN1V25_SHIFT)
<< _ADC_CAL_SINGLEGAIN_SHIFT;
- newCal |= ((DEVINFO->ADC0CAL0 & DEVINFO_ADC0_OFFSET1V25_MASK)
+ newCal |= ((diCalReg[0] & DEVINFO_ADC0_OFFSET1V25_MASK)
>> DEVINFO_ADC0_OFFSET1V25_SHIFT)
<< _ADC_CAL_SINGLEOFFSET_SHIFT;
-#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
- newCal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK)
+#if defined(_ADC_CAL_SINGLEOFFSETINV_MASK)
+ newCal |= ((diCalReg[0] & _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK)
>> _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT)
<< _ADC_CAL_SINGLEOFFSETINV_SHIFT;
#endif
break;
case adcRef2V5:
- newCal |= ((DEVINFO->ADC0CAL0 & DEVINFO_ADC0_GAIN2V5_MASK)
+ newCal |= ((diCalReg[0] & DEVINFO_ADC0_GAIN2V5_MASK)
>> DEVINFO_ADC0_GAIN2V5_SHIFT)
<< _ADC_CAL_SINGLEGAIN_SHIFT;
- newCal |= ((DEVINFO->ADC0CAL0 & DEVINFO_ADC0_OFFSET2V5_MASK)
+ newCal |= ((diCalReg[0] & DEVINFO_ADC0_OFFSET2V5_MASK)
>> DEVINFO_ADC0_OFFSET2V5_SHIFT)
<< _ADC_CAL_SINGLEOFFSET_SHIFT;
-#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
- newCal |= ((DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK)
+#if defined(_ADC_CAL_SINGLEOFFSETINV_MASK)
+ newCal |= ((diCalReg[0] & _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK)
>> _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT)
<< _ADC_CAL_SINGLEOFFSETINV_SHIFT;
#endif
break;
case adcRefVDD:
- newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_GAINVDD_MASK)
+ newCal |= ((diCalReg[1] & DEVINFO_ADC0_GAINVDD_MASK)
>> DEVINFO_ADC0_GAINVDD_SHIFT)
<< _ADC_CAL_SINGLEGAIN_SHIFT;
- newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_OFFSETVDD_MASK)
+ newCal |= ((diCalReg[1] & DEVINFO_ADC0_OFFSETVDD_MASK)
>> DEVINFO_ADC0_OFFSETVDD_SHIFT)
- << _ADC_CAL_SINGLEOFFSET_SHIFT;
-#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
- newCal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK)
+ << _ADC_CAL_SINGLEOFFSET_SHIFT;
+#if defined(_ADC_CAL_SINGLEOFFSETINV_MASK)
+ newCal |= ((diCalReg[1] & _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK)
>> _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT)
<< _ADC_CAL_SINGLEOFFSETINV_SHIFT;
#endif
break;
case adcRef5VDIFF:
- newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_GAIN5VDIFF_MASK)
+ newCal |= ((diCalReg[1] & DEVINFO_ADC0_GAIN5VDIFF_MASK)
>> DEVINFO_ADC0_GAIN5VDIFF_SHIFT)
<< _ADC_CAL_SINGLEGAIN_SHIFT;
- newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_OFFSET5VDIFF_MASK)
+ newCal |= ((diCalReg[1] & DEVINFO_ADC0_OFFSET5VDIFF_MASK)
>> DEVINFO_ADC0_OFFSET5VDIFF_SHIFT)
<< _ADC_CAL_SINGLEOFFSET_SHIFT;
-#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
- newCal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK)
+#if defined(_ADC_CAL_SINGLEOFFSETINV_MASK)
+ newCal |= ((diCalReg[1] & _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK)
>> _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT)
<< _ADC_CAL_SINGLEOFFSETINV_SHIFT;
#endif
@@ -303,25 +316,25 @@
case adcRef2xVDD:
/* There is no gain calibration for this reference */
- newCal |= ((DEVINFO->ADC0CAL2 & DEVINFO_ADC0_OFFSET2XVDD_MASK)
+ newCal |= ((diCalReg[2] & DEVINFO_ADC0_OFFSET2XVDD_MASK)
>> DEVINFO_ADC0_OFFSET2XVDD_SHIFT)
<< _ADC_CAL_SINGLEOFFSET_SHIFT;
-#if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
- newCal |= ((DEVINFO->ADC0CAL2 & _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK)
+#if defined(_ADC_CAL_SINGLEOFFSETINV_MASK)
+ newCal |= ((diCalReg[2] & _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK)
>> _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT)
<< _ADC_CAL_SINGLEOFFSETINV_SHIFT;
#endif
break;
-#if defined( _ADC_SINGLECTRLX_VREFSEL_VDDXWATT )
+#if defined(_ADC_SINGLECTRLX_VREFSEL_VDDXWATT)
case adcRefVddxAtt:
- newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_GAINVDD_MASK)
+ newCal |= ((diCalReg[1] & DEVINFO_ADC0_GAINVDD_MASK)
>> DEVINFO_ADC0_GAINVDD_SHIFT)
<< _ADC_CAL_SINGLEGAIN_SHIFT;
- newCal |= ((DEVINFO->ADC0CAL1 & DEVINFO_ADC0_OFFSETVDD_MASK)
+ newCal |= ((diCalReg[1] & DEVINFO_ADC0_OFFSETVDD_MASK)
>> DEVINFO_ADC0_OFFSETVDD_SHIFT)
<< _ADC_CAL_SINGLEOFFSET_SHIFT;
- newCal |= ((DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK)
+ newCal |= ((diCalReg[1] & _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK)
>> _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT)
<< _ADC_CAL_SINGLEOFFSETINV_SHIFT;
break;
@@ -375,13 +388,10 @@
EFM_ASSERT(ADC_REF_VALID(adc));
- if (presc == 0)
- {
+ if (presc == 0) {
/* Assume maximum ADC clock for prescaler 0 */
presc = ADC_PrescaleCalc(ADC_MAX_CLOCK, 0);
- }
- else
- {
+ } else {
/* Check prescaler bounds against ADC_MAX_CLOCK and ADC_MIN_CLOCK */
#if defined(_ADC_CTRL_ADCCLKMODE_MASK)
if (ADC0->CTRL & ADC_CTRL_ADCCLKMODE_SYNC)
@@ -397,35 +407,33 @@
tmp = ((uint32_t)(init->ovsRateSel) << _ADC_CTRL_OVSRSEL_SHIFT)
| (((uint32_t)(init->timebase) << _ADC_CTRL_TIMEBASE_SHIFT)
- & _ADC_CTRL_TIMEBASE_MASK)
+ & _ADC_CTRL_TIMEBASE_MASK)
| (((uint32_t)(presc) << _ADC_CTRL_PRESC_SHIFT)
- & _ADC_CTRL_PRESC_MASK)
-#if defined ( _ADC_CTRL_LPFMODE_MASK )
+ & _ADC_CTRL_PRESC_MASK)
+#if defined (_ADC_CTRL_LPFMODE_MASK)
| ((uint32_t)(init->lpfMode) << _ADC_CTRL_LPFMODE_SHIFT)
#endif
| ((uint32_t)(init->warmUpMode) << _ADC_CTRL_WARMUPMODE_SHIFT);
- if (init->tailgate)
- {
+ if (init->tailgate) {
tmp |= ADC_CTRL_TAILGATE;
}
adc->CTRL = tmp;
/* Set ADC EM2 clock configuration */
-#if defined( _ADC_CTRL_ADCCLKMODE_MASK )
+#if defined(_ADC_CTRL_ADCCLKMODE_MASK)
BUS_RegMaskedWrite(&ADC0->CTRL,
_ADC_CTRL_ADCCLKMODE_MASK | _ADC_CTRL_ASYNCCLKEN_MASK,
init->em2ClockConfig);
#endif
-#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
/* A debugger can trigger the SCANUF interrupt on EFM32xG1 or EFR32xG1 */
ADC_IntClear(adc, ADC_IFC_SCANUF);
#endif
}
-
-#if defined( _ADC_SCANINPUTSEL_MASK )
+#if defined(_ADC_SCANINPUTSEL_MASK)
/***************************************************************************//**
* @brief
* Clear ADC scan input configuration.
@@ -445,7 +453,6 @@
scanInit->scanInputConfig.scanNegSel = _ADC_SCANNEGSEL_RESETVALUE;
}
-
/***************************************************************************//**
* @brief
* Initialize ADC scan single-ended input configuration.
@@ -487,17 +494,12 @@
currentSel = (scanInit->scanInputConfig.scanInputSel >> (inputGroup * 8)) & 0xFF;
/* If none selected */
- if (currentSel == ADC_SCANINPUTSEL_GROUP_NONE)
- {
+ if (currentSel == ADC_SCANINPUTSEL_GROUP_NONE) {
scanInit->scanInputConfig.scanInputSel &= ~(0xFF << (inputGroup * 8));
scanInit->scanInputConfig.scanInputSel |= (newSel << (inputGroup * 8));
- }
- else if (currentSel == newSel)
- {
+ } else if (currentSel == newSel) {
/* Ok, but do nothing. */
- }
- else
- {
+ } else {
/* Invalid channel range. A range is already selected for this group. */
EFM_ASSERT(false);
}
@@ -509,7 +511,6 @@
return scanId;
}
-
/***************************************************************************//**
* @brief
* Initialize ADC scan differential input configuration.
@@ -557,67 +558,47 @@
scanInit->diff = true;
/* Set negative ADC input, unless the default is selected. */
- if (negInput != adcScanNegInputDefault)
- {
- if (scanId == 0)
- {
+ if (negInput != adcScanNegInputDefault) {
+ if (scanId == 0) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 0);
- }
- else if (scanId == 2)
- {
+ } else if (scanId == 2) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 0);
- }
- else if (scanId == 4)
- {
+ } else if (scanId == 4) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 0);
- }
- else if (scanId == 6)
- {
+ } else if (scanId == 6) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 0);
- }
- else if (scanId == 9)
- {
+ } else if (scanId == 9) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 1);
- }
- else if (scanId == 11)
- {
+ } else if (scanId == 11) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 1);
- }
- else if (scanId == 13)
- {
+ } else if (scanId == 13) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 1);
- }
- else if (scanId == 15)
- {
+ } else if (scanId == 15) {
negInputRegMask = _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK;
negInputRegShift = _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT;
EFM_ASSERT(inputGroup == 1);
- }
- else
- {
+ } else {
/* There is not negative input option for this positive input (negInput is posInput + 1). */
EFM_ASSERT(false);
}
/* Find ADC_SCANNEGSEL_CHxNSEL value for positive input 0, 2, 4 and 6 */
- if (inputGroup == 0)
- {
- switch (negInput)
- {
+ if (inputGroup == 0) {
+ switch (negInput) {
case adcScanNegInput1:
negInputRegVal = _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1;
break;
@@ -639,12 +620,9 @@
EFM_ASSERT(false);
break;
}
- }
- else if (inputGroup == 1)
- {
+ } else if (inputGroup == 1) {
/* Find ADC_SCANNEGSEL_CHxNSEL value for positive input 9, 11, 13 and 15 */
- switch (negInput)
- {
+ switch (negInput) {
case adcScanNegInput8:
negInputRegVal = _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8;
break;
@@ -666,9 +644,7 @@
EFM_ASSERT(false);
break;
}
- }
- else
- {
+ } else {
/* No alternative negative input for input group > 1 */
EFM_ASSERT(false);
}
@@ -681,7 +657,6 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Initialize ADC scan sequence.
@@ -720,37 +695,34 @@
ADC_LoadDevinfoCal(adc, init->reference, true);
tmp = 0
-#if defined ( _ADC_SCANCTRL_PRSSEL_MASK )
+#if defined (_ADC_SCANCTRL_PRSSEL_MASK)
| (init->prsSel << _ADC_SCANCTRL_PRSSEL_SHIFT)
#endif
| (init->acqTime << _ADC_SCANCTRL_AT_SHIFT)
-#if defined ( _ADC_SCANCTRL_INPUTMASK_MASK )
+#if defined (_ADC_SCANCTRL_INPUTMASK_MASK)
| init->input
#endif
| (init->resolution << _ADC_SCANCTRL_RES_SHIFT);
- if (init->prsEnable)
- {
+ if (init->prsEnable) {
tmp |= ADC_SCANCTRL_PRSEN;
}
- if (init->leftAdjust)
- {
+ if (init->leftAdjust) {
tmp |= ADC_SCANCTRL_ADJ_LEFT;
}
-#if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
+#if defined(_ADC_SCANCTRL_INPUTMASK_MASK)
if (init->diff)
-#elif defined( _ADC_SCANINPUTSEL_MASK )
+#elif defined(_ADC_SCANINPUTSEL_MASK)
if (init->diff)
#endif
{
tmp |= ADC_SCANCTRL_DIFF;
}
- if (init->rep)
- {
-#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
+ if (init->rep) {
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
/* Scan repeat mode does not work on EFM32JG1, EFM32PG1 or EFR32xG1x devices.
* The errata is called ADC_E211 in the errata document. */
EFM_ASSERT(false);
@@ -759,52 +731,47 @@
}
/* Set scan reference. Check if reference configuraion is extended to SCANCTRLX. */
-#if defined ( _ADC_SCANCTRLX_VREFSEL_MASK )
- if (init->reference & ADC_CTRLX_VREFSEL_REG)
- {
+#if defined (_ADC_SCANCTRLX_VREFSEL_MASK)
+ if (init->reference & ADC_CTRLX_VREFSEL_REG) {
/* Select extension register */
tmp |= ADC_SCANCTRL_REF_CONF;
- }
- else
- {
+ } else {
tmp |= init->reference << _ADC_SCANCTRL_REF_SHIFT;
}
#else
tmp |= init->reference << _ADC_SCANCTRL_REF_SHIFT;
#endif
-#if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
+#if defined(_ADC_SCANCTRL_INPUTMASK_MASK)
tmp |= init->input;
#endif
adc->SCANCTRL = tmp;
/* Update SINGLECTRLX for reference select and PRS select */
-#if defined ( _ADC_SCANCTRLX_MASK )
+#if defined (_ADC_SCANCTRLX_MASK)
tmp = adc->SCANCTRLX & ~(_ADC_SCANCTRLX_VREFSEL_MASK
- | _ADC_SCANCTRLX_PRSSEL_MASK
- | _ADC_SCANCTRLX_FIFOOFACT_MASK);
- if (init->reference & ADC_CTRLX_VREFSEL_REG)
- {
+ | _ADC_SCANCTRLX_PRSSEL_MASK
+ | _ADC_SCANCTRLX_FIFOOFACT_MASK);
+ if (init->reference & ADC_CTRLX_VREFSEL_REG) {
tmp |= (init->reference & ~ADC_CTRLX_VREFSEL_REG) << _ADC_SCANCTRLX_VREFSEL_SHIFT;
}
tmp |= init->prsSel << _ADC_SCANCTRLX_PRSSEL_SHIFT;
- if (init->fifoOverwrite)
- {
+ if (init->fifoOverwrite) {
tmp |= ADC_SCANCTRLX_FIFOOFACT_OVERWRITE;
}
adc->SCANCTRLX = tmp;
#endif
-#if defined( _ADC_CTRL_SCANDMAWU_MASK )
+#if defined(_ADC_CTRL_SCANDMAWU_MASK)
BUS_RegBitWrite(&adc->CTRL, _ADC_CTRL_SCANDMAWU_SHIFT, init->scanDmaEm2Wu);
#endif
/* Write scan input configuration */
-#if defined( _ADC_SCANINPUTSEL_MASK )
+#if defined(_ADC_SCANINPUTSEL_MASK)
/* Check for valid scan input configuration. Use @ref ADC_ScanInputClear()
@ref ADC_ScanSingleEndedInputAdd() and @ref ADC_ScanDifferentialInputAdd() to set
scan input configuration. */
@@ -815,14 +782,13 @@
#endif
/* Assert for any APORT bus conflicts programming errors */
-#if defined( _ADC_BUSCONFLICT_MASK )
+#if defined(_ADC_BUSCONFLICT_MASK)
tmp = adc->BUSREQ;
EFM_ASSERT(!(tmp & adc->BUSCONFLICT));
EFM_ASSERT(!(adc->STATUS & _ADC_STATUS_PROGERR_MASK));
#endif
}
-
/***************************************************************************//**
* @brief
* Initialize single ADC sample conversion.
@@ -864,62 +830,54 @@
ADC_LoadDevinfoCal(adc, init->reference, false);
tmp = 0
-#if defined( _ADC_SINGLECTRL_PRSSEL_MASK )
+#if defined(_ADC_SINGLECTRL_PRSSEL_MASK)
| (init->prsSel << _ADC_SINGLECTRL_PRSSEL_SHIFT)
#endif
| (init->acqTime << _ADC_SINGLECTRL_AT_SHIFT)
-#if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
+#if defined(_ADC_SINGLECTRL_INPUTSEL_MASK)
| (init->input << _ADC_SINGLECTRL_INPUTSEL_SHIFT)
#endif
-#if defined( _ADC_SINGLECTRL_POSSEL_MASK )
+#if defined(_ADC_SINGLECTRL_POSSEL_MASK)
| (init->posSel << _ADC_SINGLECTRL_POSSEL_SHIFT)
#endif
-#if defined( _ADC_SINGLECTRL_NEGSEL_MASK )
+#if defined(_ADC_SINGLECTRL_NEGSEL_MASK)
| (init->negSel << _ADC_SINGLECTRL_NEGSEL_SHIFT)
#endif
| ((uint32_t)(init->resolution) << _ADC_SINGLECTRL_RES_SHIFT);
- if (init->prsEnable)
- {
+ if (init->prsEnable) {
tmp |= ADC_SINGLECTRL_PRSEN;
}
- if (init->leftAdjust)
- {
+ if (init->leftAdjust) {
tmp |= ADC_SINGLECTRL_ADJ_LEFT;
}
- if (init->diff)
- {
+ if (init->diff) {
tmp |= ADC_SINGLECTRL_DIFF;
}
- if (init->rep)
- {
+ if (init->rep) {
tmp |= ADC_SINGLECTRL_REP;
}
-#if defined( _ADC_SINGLECTRL_POSSEL_TEMP )
+#if defined(_ADC_SINGLECTRL_POSSEL_TEMP)
/* Force at least 8 cycle acquisition time when reading internal temperature
* sensor with 1.25V reference */
if ((init->posSel == adcPosSelTEMP)
- && (init->reference == adcRef1V25)
- && (init->acqTime < adcAcqTime8))
- {
+ && (init->reference == adcRef1V25)
+ && (init->acqTime < adcAcqTime8)) {
tmp = (tmp & ~_ADC_SINGLECTRL_AT_MASK)
- | (adcAcqTime8 << _ADC_SINGLECTRL_AT_SHIFT);
+ | (adcAcqTime8 << _ADC_SINGLECTRL_AT_SHIFT);
}
#endif
/* Set single reference. Check if reference configuraion is extended to SINGLECTRLX. */
-#if defined ( _ADC_SINGLECTRLX_MASK )
- if (init->reference & ADC_CTRLX_VREFSEL_REG)
- {
+#if defined (_ADC_SINGLECTRLX_MASK)
+ if (init->reference & ADC_CTRLX_VREFSEL_REG) {
/* Select extension register */
tmp |= ADC_SINGLECTRL_REF_CONF;
- }
- else
- {
+ } else {
tmp |= (init->reference << _ADC_SINGLECTRL_REF_SHIFT);
}
#else
@@ -928,19 +886,17 @@
adc->SINGLECTRL = tmp;
/* Update SINGLECTRLX for reference select and PRS select */
-#if defined ( _ADC_SINGLECTRLX_VREFSEL_MASK )
- tmp = adc->SINGLECTRLX & (_ADC_SINGLECTRLX_VREFSEL_MASK
- | _ADC_SINGLECTRLX_PRSSEL_MASK
- | _ADC_SINGLECTRLX_FIFOOFACT_MASK);
- if (init->reference & ADC_CTRLX_VREFSEL_REG)
- {
+#if defined (_ADC_SINGLECTRLX_VREFSEL_MASK)
+ tmp = adc->SINGLECTRLX & ~(_ADC_SINGLECTRLX_VREFSEL_MASK
+ | _ADC_SINGLECTRLX_PRSSEL_MASK
+ | _ADC_SINGLECTRLX_FIFOOFACT_MASK);
+ if (init->reference & ADC_CTRLX_VREFSEL_REG) {
tmp |= ((init->reference & ~ADC_CTRLX_VREFSEL_REG) << _ADC_SINGLECTRLX_VREFSEL_SHIFT);
}
tmp |= ((init->prsSel << _ADC_SINGLECTRLX_PRSSEL_SHIFT));
- if (init->fifoOverwrite)
- {
+ if (init->fifoOverwrite) {
tmp |= ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE;
}
@@ -948,34 +904,30 @@
#endif
/* Set DMA availability in EM2 */
-#if defined( _ADC_CTRL_SINGLEDMAWU_MASK )
+#if defined(_ADC_CTRL_SINGLEDMAWU_MASK)
BUS_RegBitWrite(&adc->CTRL, _ADC_CTRL_SINGLEDMAWU_SHIFT, init->singleDmaEm2Wu);
#endif
-#if defined( _ADC_BIASPROG_GPBIASACC_MASK ) && defined( FIX_ADC_TEMP_BIAS_EN )
- if (init->posSel == adcPosSelTEMP)
- {
+#if defined(_ADC_BIASPROG_GPBIASACC_MASK) && defined(FIX_ADC_TEMP_BIAS_EN)
+ if (init->posSel == adcPosSelTEMP) {
/* ADC should always use low accuracy setting when reading the internal
* temperature sensor on platform 2 generation 1 devices. Using high
* accuracy setting can introduce a glitch. */
BUS_RegBitWrite(&adc->BIASPROG, _ADC_BIASPROG_GPBIASACC_SHIFT, 1);
- }
- else
- {
+ } else {
BUS_RegBitWrite(&adc->BIASPROG, _ADC_BIASPROG_GPBIASACC_SHIFT, 0);
}
#endif
/* Assert for any APORT bus conflicts programming errors */
-#if defined( _ADC_BUSCONFLICT_MASK )
+#if defined(_ADC_BUSCONFLICT_MASK)
tmp = adc->BUSREQ;
EFM_ASSERT(!(tmp & adc->BUSCONFLICT));
EFM_ASSERT(!(adc->STATUS & _ADC_STATUS_PROGERR_MASK));
#endif
}
-
-#if defined( _ADC_SCANDATAX_MASK )
+#if defined(_ADC_SCANDATAX_MASK)
/***************************************************************************//**
* @brief
* Get scan result and scan select ID.
@@ -1004,7 +956,6 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Calculate prescaler value used to determine ADC clock.
@@ -1027,31 +978,25 @@
uint32_t ret;
/* Make sure selected ADC clock is within valid range */
- if (adcFreq > ADC_MAX_CLOCK)
- {
+ if (adcFreq > ADC_MAX_CLOCK) {
adcFreq = ADC_MAX_CLOCK;
- }
- else if (adcFreq < ADC_MIN_CLOCK)
- {
+ } else if (adcFreq < ADC_MIN_CLOCK) {
adcFreq = ADC_MIN_CLOCK;
}
/* Use current HFPER frequency? */
- if (!hfperFreq)
- {
+ if (!hfperFreq) {
hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
}
ret = (hfperFreq + adcFreq - 1) / adcFreq;
- if (ret)
- {
+ if (ret) {
ret--;
}
return (uint8_t)ret;
}
-
/***************************************************************************//**
* @brief
* Reset ADC to same state as after a HW reset.
@@ -1068,29 +1013,29 @@
/* Stop conversions, before resetting other registers. */
adc->CMD = ADC_CMD_SINGLESTOP | ADC_CMD_SCANSTOP;
adc->SINGLECTRL = _ADC_SINGLECTRL_RESETVALUE;
-#if defined( _ADC_SINGLECTRLX_MASK )
+#if defined(_ADC_SINGLECTRLX_MASK)
adc->SINGLECTRLX = _ADC_SINGLECTRLX_RESETVALUE;
#endif
adc->SCANCTRL = _ADC_SCANCTRL_RESETVALUE;
-#if defined( _ADC_SCANCTRLX_MASK )
+#if defined(_ADC_SCANCTRLX_MASK)
adc->SCANCTRLX = _ADC_SCANCTRLX_RESETVALUE;
#endif
adc->CTRL = _ADC_CTRL_RESETVALUE;
adc->IEN = _ADC_IEN_RESETVALUE;
adc->IFC = _ADC_IFC_MASK;
adc->BIASPROG = _ADC_BIASPROG_RESETVALUE;
-#if defined( _ADC_SCANMASK_MASK )
+#if defined(_ADC_SCANMASK_MASK)
adc->SCANMASK = _ADC_SCANMASK_RESETVALUE;
#endif
-#if defined( _ADC_SCANINPUTSEL_MASK )
+#if defined(_ADC_SCANINPUTSEL_MASK)
adc->SCANINPUTSEL = _ADC_SCANINPUTSEL_RESETVALUE;
#endif
-#if defined( _ADC_SCANNEGSEL_MASK )
+#if defined(_ADC_SCANNEGSEL_MASK)
adc->SCANNEGSEL = _ADC_SCANNEGSEL_RESETVALUE;
#endif
/* Clear data FIFOs */
-#if defined( _ADC_SINGLEFIFOCLEAR_MASK )
+#if defined(_ADC_SINGLEFIFOCLEAR_MASK)
adc->SINGLEFIFOCLEAR |= ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR;
adc->SCANFIFOCLEAR |= ADC_SCANFIFOCLEAR_SCANFIFOCLEAR;
#endif
@@ -1099,12 +1044,11 @@
ADC_LoadDevinfoCal(adc, adcRef1V25, false);
ADC_LoadDevinfoCal(adc, adcRef1V25, true);
-#if defined( _ADC_SCANINPUTSEL_MASK )
+#if defined(_ADC_SCANINPUTSEL_MASK)
/* Do not reset route register, setting should be done independently */
#endif
}
-
/***************************************************************************//**
* @brief
* Calculate timebase value in order to get a timebase providing at least 1us.
@@ -1117,24 +1061,22 @@
******************************************************************************/
uint8_t ADC_TimebaseCalc(uint32_t hfperFreq)
{
- if (!hfperFreq)
- {
+ if (!hfperFreq) {
hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
/* Just in case, make sure we get non-zero freq for below calculation */
- if (!hfperFreq)
- {
+ if (!hfperFreq) {
hfperFreq = 1;
}
}
-#if defined( _EFM32_GIANT_FAMILY ) || defined( _EFM32_WONDER_FAMILY )
+#if defined(_SILICON_LABS_32B_SERIES_0) \
+ && (defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY))
/* Handle errata on Giant Gecko, max TIMEBASE is 5 bits wide or max 0x1F */
/* cycles. This will give a warmp up time of e.g. 0.645us, not the */
/* required 1us when operating at 48MHz. One must also increase acqTime */
/* to compensate for the missing clock cycles, adding up to 1us in total.*/
/* See reference manual for details. */
- if ( hfperFreq > 32000000 )
- {
+ if ( hfperFreq > 32000000 ) {
hfperFreq = 32000000;
}
#endif
@@ -1146,7 +1088,6 @@
return (uint8_t)(hfperFreq - 1);
}
-
/** @} (end addtogroup ADC) */
/** @} (end addtogroup emlib) */
#endif /* defined(ADC_COUNT) && (ADC_COUNT > 0) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_aes.c
* @brief Advanced Encryption Standard (AES) accelerator peripheral API.
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -141,21 +141,18 @@
/* Number of blocks to process */
len /= AES_BLOCKSIZE;
- #if defined( AES_CTRL_KEYBUFEN )
- if (key)
- {
+ #if defined(AES_CTRL_KEYBUFEN)
+ if (key) {
/* Load key into high key for key buffer usage */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->KEYHA = __REV(_key[i]);
}
}
#endif
- if (encrypt)
- {
+ if (encrypt) {
/* Enable encryption with auto start using XOR */
- #if defined( AES_CTRL_KEYBUFEN )
+ #if defined(AES_CTRL_KEYBUFEN)
AES->CTRL = AES_CTRL_KEYBUFEN | AES_CTRL_XORSTART;
#else
AES->CTRL = AES_CTRL_XORSTART;
@@ -163,25 +160,21 @@
/* Load initialization vector, since writing to DATA, it will */
/* not trigger encryption. */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->DATA = __REV(_iv[i]);
}
/* Encrypt data */
- while (len--)
- {
- #if !defined( AES_CTRL_KEYBUFEN )
+ while (len--) {
+ #if !defined(AES_CTRL_KEYBUFEN)
/* Load key */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->KEYLA = __REV(_key[i]);
}
#endif
/* Load data and trigger encryption */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->XORDATA = __REV(_in[i]);
}
_in += 4;
@@ -191,42 +184,35 @@
;
/* Save encrypted data */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA);
}
_out += 4;
}
- }
- else
- {
+ } else {
/* Select decryption mode */
- #if defined( AES_CTRL_KEYBUFEN )
+ #if defined(AES_CTRL_KEYBUFEN)
AES->CTRL = AES_CTRL_DECRYPT | AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART;
#else
AES->CTRL = AES_CTRL_DECRYPT | AES_CTRL_DATASTART;
#endif
/* Copy init vector to previous buffer to avoid special handling */
- for (i = 0; i < 4; i++)
- {
+ for (i = 0; i < 4; i++) {
prev[i] = _iv[i];
}
/* Decrypt data */
- while (len--)
- {
- #if !defined( AES_CTRL_KEYBUFEN )
+ while (len--) {
+ #if !defined(AES_CTRL_KEYBUFEN)
/* Load key */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->KEYLA = __REV(_key[i]);
}
#endif
/* Load data and trigger decryption */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->DATA = __REV(_in[i]);
}
@@ -236,8 +222,7 @@
/* In order to avoid additional buffer, we use HW directly for XOR and buffer */
/* (Writing to XORDATA will not trigger encoding, triggering enabled on DATA.) */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->XORDATA = __REV(prev[i]);
prev[i] = _in[i];
}
@@ -245,8 +230,7 @@
/* Then fetch decrypted data, we have to do it in a separate loop */
/* due to internal auto-shifting of words */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA);
}
_out += 4;
@@ -254,8 +238,7 @@
}
}
-
-#if defined( AES_CTRL_AES256 )
+#if defined(AES_CTRL_AES256)
/***************************************************************************//**
* @brief
* Cipher-block chaining (CBC) cipher mode encryption/decryption, 256 bit key.
@@ -307,24 +290,20 @@
/* Number of blocks to process */
len /= AES_BLOCKSIZE;
- if (encrypt)
- {
+ if (encrypt) {
/* Enable encryption with auto start using XOR */
AES->CTRL = AES_CTRL_AES256 | AES_CTRL_XORSTART;
/* Load initialization vector, since writing to DATA, it will */
/* not trigger encryption. */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->DATA = __REV(_iv[i]);
}
/* Encrypt data */
- while (len--)
- {
+ while (len--) {
/* Load key and data and trigger encryption */
- for (i = 3, j = 7; i >= 0; i--, j--)
- {
+ for (i = 3, j = 7; i >= 0; i--, j--) {
AES->KEYLA = __REV(_key[j]);
AES->KEYHA = __REV(_key[i]);
/* Write data last, since will trigger encryption on last iteration */
@@ -337,30 +316,24 @@
;
/* Save encrypted data */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA);
}
_out += 4;
}
- }
- else
- {
+ } else {
/* Select decryption mode */
AES->CTRL = AES_CTRL_AES256 | AES_CTRL_DECRYPT | AES_CTRL_DATASTART;
/* Copy init vector to previous buffer to avoid special handling */
- for (i = 0; i < 4; i++)
- {
+ for (i = 0; i < 4; i++) {
prev[i] = _iv[i];
}
/* Decrypt data */
- while (len--)
- {
+ while (len--) {
/* Load key and data and trigger decryption */
- for (i = 3, j = 7; i >= 0; i--, j--)
- {
+ for (i = 3, j = 7; i >= 0; i--, j--) {
AES->KEYLA = __REV(_key[j]);
AES->KEYHA = __REV(_key[i]);
/* Write data last, since will trigger encryption on last iteration */
@@ -372,8 +345,7 @@
;
/* In order to avoid additional buffer, we use HW directly for XOR and buffer */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->XORDATA = __REV(prev[i]);
prev[i] = _in[i];
}
@@ -381,8 +353,7 @@
/* Then fetch decrypted data, we have to do it in a separate loop */
/* due to internal auto-shifting of words */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA);
}
_out += 4;
@@ -391,7 +362,6 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Cipher feedback (CFB) cipher mode encryption/decryption, 128 bit key.
@@ -467,16 +437,15 @@
EFM_ASSERT(!(len % AES_BLOCKSIZE));
- #if defined( AES_CTRL_KEYBUFEN )
+ #if defined(AES_CTRL_KEYBUFEN)
AES->CTRL = AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART;
#else
AES->CTRL = AES_CTRL_DATASTART;
#endif
- #if defined( AES_CTRL_KEYBUFEN )
+ #if defined(AES_CTRL_KEYBUFEN)
/* Load key into high key for key buffer usage */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->KEYHA = __REV(_key[i]);
}
#endif
@@ -484,32 +453,25 @@
/* Encrypt/decrypt data */
data = _iv;
len /= AES_BLOCKSIZE;
- while (len--)
- {
- #if !defined( AES_CTRL_KEYBUFEN )
+ while (len--) {
+ #if !defined(AES_CTRL_KEYBUFEN)
/* Load key */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->KEYLA = __REV(_key[i]);
}
#endif
/* Load data and trigger encryption */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->DATA = __REV(data[i]);
}
/* Do some required processing before waiting for completion */
- if (encrypt)
- {
+ if (encrypt) {
data = _out;
- }
- else
- {
+ } else {
/* Must copy current ciphertext block since it may be overwritten */
- for (i = 0; i < 4; i++)
- {
+ for (i = 0; i < 4; i++) {
tmp[i] = _in[i];
}
data = tmp;
@@ -520,8 +482,7 @@
;
/* Save encrypted/decrypted data */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
@@ -529,8 +490,7 @@
}
}
-
-#if defined( AES_CTRL_AES256 )
+#if defined(AES_CTRL_AES256)
/***************************************************************************//**
* @brief
* Cipher feedback (CFB) cipher mode encryption/decryption, 256 bit key.
@@ -583,11 +543,9 @@
/* Encrypt/decrypt data */
data = _iv;
len /= AES_BLOCKSIZE;
- while (len--)
- {
+ while (len--) {
/* Load key and block to be encrypted/decrypted */
- for (i = 3, j = 7; i >= 0; i--, j--)
- {
+ for (i = 3, j = 7; i >= 0; i--, j--) {
AES->KEYLA = __REV(_key[j]);
AES->KEYHA = __REV(_key[i]);
/* Write data last, since will trigger encryption on last iteration */
@@ -595,15 +553,11 @@
}
/* Do some required processing before waiting for completion */
- if (encrypt)
- {
+ if (encrypt) {
data = _out;
- }
- else
- {
+ } else {
/* Must copy current ciphertext block since it may be overwritten */
- for (i = 0; i < 4; i++)
- {
+ for (i = 0; i < 4; i++) {
tmp[i] = _in[i];
}
data = tmp;
@@ -613,8 +567,7 @@
;
/* Save encrypted/decrypted data */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
@@ -623,7 +576,6 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Counter (CTR) cipher mode encryption/decryption, 128 bit key.
@@ -700,18 +652,16 @@
EFM_ASSERT(!(len % AES_BLOCKSIZE));
EFM_ASSERT(ctrFunc);
- #if defined( AES_CTRL_KEYBUFEN )
+ #if defined(AES_CTRL_KEYBUFEN)
AES->CTRL = AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART;
#else
AES->CTRL = AES_CTRL_DATASTART;
#endif
- #if defined( AES_CTRL_KEYBUFEN )
- if (key)
- {
+ #if defined(AES_CTRL_KEYBUFEN)
+ if (key) {
/* Load key into high key for key buffer usage */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->KEYHA = __REV(_key[i]);
}
}
@@ -719,19 +669,16 @@
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
- while (len--)
- {
- #if !defined( AES_CTRL_KEYBUFEN )
+ while (len--) {
+ #if !defined(AES_CTRL_KEYBUFEN)
/* Load key */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->KEYLA = __REV(_key[i]);
}
#endif
/* Load ctr to be encrypted/decrypted */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->DATA = __REV(_ctr[i]);
}
/* Increment ctr for next use */
@@ -742,8 +689,7 @@
;
/* Save encrypted/decrypted data */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
@@ -751,8 +697,7 @@
}
}
-
-#if defined( AES_CTRL_AES256 )
+#if defined(AES_CTRL_AES256)
/***************************************************************************//**
* @brief
* Counter (CTR) cipher mode encryption/decryption, 256 bit key.
@@ -804,11 +749,9 @@
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
- while (len--)
- {
+ while (len--) {
/* Load key and block to be encrypted/decrypted */
- for (i = 3, j = 7; i >= 0; i--, j--)
- {
+ for (i = 3, j = 7; i >= 0; i--, j--) {
AES->KEYLA = __REV(_key[j]);
AES->KEYHA = __REV(_key[i]);
/* Write data last, since will trigger encryption on last iteration */
@@ -822,8 +765,7 @@
;
/* Save encrypted/decrypted data */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
@@ -832,7 +774,6 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Update last 32 bits of 128 bit counter, by incrementing with 1.
@@ -854,7 +795,6 @@
_ctr[3] = __REV(__REV(_ctr[3]) + 1);
}
-
/***************************************************************************//**
* @brief
* Generate 128 bit decryption key from 128 bit encryption key. The decryption
@@ -877,8 +817,7 @@
const uint32_t *_in = (const uint32_t *)in;
/* Load key */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->KEYLA = __REV(_in[i]);
}
@@ -892,14 +831,12 @@
;
/* Save decryption key */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->KEYLA);
}
}
-
-#if defined( AES_CTRL_AES256 )
+#if defined(AES_CTRL_AES256)
/***************************************************************************//**
* @brief
* Generate 256 bit decryption key from 256 bit encryption key. The decryption
@@ -923,8 +860,7 @@
const uint32_t *_in = (const uint32_t *)in;
/* Load key */
- for (i = 3, j = 7; i >= 0; i--, j--)
- {
+ for (i = 3, j = 7; i >= 0; i--, j--) {
AES->KEYLA = __REV(_in[j]);
AES->KEYHA = __REV(_in[i]);
}
@@ -938,15 +874,13 @@
;
/* Save decryption key */
- for (i = 3, j = 7; i >= 0; i--, j--)
- {
+ for (i = 3, j = 7; i >= 0; i--, j--) {
_out[j] = __REV(AES->KEYLA);
_out[i] = __REV(AES->KEYHA);
}
}
#endif
-
/***************************************************************************//**
* @brief
* Electronic Codebook (ECB) cipher mode encryption/decryption, 128 bit key.
@@ -1011,27 +945,23 @@
EFM_ASSERT(!(len % AES_BLOCKSIZE));
- #if defined( AES_CTRL_KEYBUFEN )
+ #if defined(AES_CTRL_KEYBUFEN)
/* Load key into high key for key buffer usage */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->KEYHA = __REV(_key[i]);
}
#endif
- if (encrypt)
- {
+ if (encrypt) {
/* Select encryption mode */
- #if defined( AES_CTRL_KEYBUFEN )
+ #if defined(AES_CTRL_KEYBUFEN)
AES->CTRL = AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART;
#else
AES->CTRL = AES_CTRL_DATASTART;
#endif
- }
- else
- {
+ } else {
/* Select decryption mode */
- #if defined( AES_CTRL_KEYBUFEN )
+ #if defined(AES_CTRL_KEYBUFEN)
AES->CTRL = AES_CTRL_DECRYPT | AES_CTRL_KEYBUFEN | AES_CTRL_DATASTART;
#else
AES->CTRL = AES_CTRL_DECRYPT | AES_CTRL_DATASTART;
@@ -1040,19 +970,16 @@
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
- while (len--)
- {
- #if !defined( AES_CTRL_KEYBUFEN )
+ while (len--) {
+ #if !defined(AES_CTRL_KEYBUFEN)
/* Load key */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->KEYLA = __REV(_key[i]);
}
#endif
/* Load block to be encrypted/decrypted */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->DATA = __REV(_in[i]);
}
_in += 4;
@@ -1062,16 +989,14 @@
;
/* Save encrypted/decrypted data */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA);
}
_out += 4;
}
}
-
-#if defined( AES_CTRL_AES256 )
+#if defined(AES_CTRL_AES256)
/***************************************************************************//**
* @brief
* Electronic Codebook (ECB) cipher mode encryption/decryption, 256 bit key.
@@ -1113,24 +1038,19 @@
EFM_ASSERT(!(len % AES_BLOCKSIZE));
- if (encrypt)
- {
+ if (encrypt) {
/* Select encryption mode */
AES->CTRL = AES_CTRL_AES256 | AES_CTRL_DATASTART;
- }
- else
- {
+ } else {
/* Select decryption mode */
AES->CTRL = AES_CTRL_DECRYPT | AES_CTRL_AES256 | AES_CTRL_DATASTART;
}
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
- while (len--)
- {
+ while (len--) {
/* Load key and block to be encrypted/decrypted */
- for (i = 3, j = 7; i >= 0; i--, j--)
- {
+ for (i = 3, j = 7; i >= 0; i--, j--) {
AES->KEYLA = __REV(_key[j]);
AES->KEYHA = __REV(_key[i]);
/* Write data last, since will trigger encryption on last iteration */
@@ -1143,8 +1063,7 @@
;
/* Save encrypted/decrypted data */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA);
}
_out += 4;
@@ -1152,7 +1071,6 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Output feedback (OFB) cipher mode encryption/decryption, 128 bit key.
@@ -1225,7 +1143,7 @@
EFM_ASSERT(!(len % AES_BLOCKSIZE));
/* Select encryption mode, trigger explicitly by command */
- #if defined( AES_CTRL_KEYBUFEN )
+ #if defined(AES_CTRL_KEYBUFEN)
AES->CTRL = AES_CTRL_KEYBUFEN;
#else
AES->CTRL = 0;
@@ -1233,9 +1151,8 @@
/* Load key into high key for key buffer usage */
/* Load initialization vector */
- for (i = 3; i >= 0; i--)
- {
- #if defined( AES_CTRL_KEYBUFEN )
+ for (i = 3; i >= 0; i--) {
+ #if defined(AES_CTRL_KEYBUFEN)
AES->KEYHA = __REV(_key[i]);
#endif
AES->DATA = __REV(_iv[i]);
@@ -1243,12 +1160,10 @@
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
- while (len--)
- {
- #if !defined( AES_CTRL_KEYBUFEN )
+ while (len--) {
+ #if !defined(AES_CTRL_KEYBUFEN)
/* Load key */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->KEYLA = __REV(_key[i]);
}
#endif
@@ -1260,8 +1175,7 @@
;
/* Save encrypted/decrypted data */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
@@ -1269,8 +1183,7 @@
}
}
-
-#if defined( AES_CTRL_AES256 )
+#if defined(AES_CTRL_AES256)
/***************************************************************************//**
* @brief
* Output feedback (OFB) cipher mode encryption/decryption, 256 bit key.
@@ -1315,18 +1228,15 @@
AES->CTRL = AES_CTRL_AES256;
/* Load initialization vector */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
AES->DATA = __REV(_iv[i]);
}
/* Encrypt/decrypt data */
len /= AES_BLOCKSIZE;
- while (len--)
- {
+ while (len--) {
/* Load key */
- for (i = 3, j = 7; i >= 0; i--, j--)
- {
+ for (i = 3, j = 7; i >= 0; i--, j--) {
AES->KEYLA = __REV(_key[j]);
AES->KEYHA = __REV(_key[i]);
}
@@ -1338,8 +1248,7 @@
;
/* Save encrypted/decrypted data */
- for (i = 3; i >= 0; i--)
- {
+ for (i = 3; i >= 0; i--) {
_out[i] = __REV(AES->DATA) ^ _in[i];
}
_out += 4;
@@ -1348,7 +1257,6 @@
}
#endif
-
/** @} (end addtogroup AES) */
/** @} (end addtogroup emlib) */
#endif /* defined(AES_COUNT) && (AES_COUNT > 0) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_assert.c
* @brief Assert API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -72,8 +72,7 @@
(void)file; /* Unused parameter */
(void)line; /* Unused parameter */
- while (true)
- {
+ while (true) {
}
}
#endif /* DEBUG_EFM */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_burtc.c
* @brief Backup Real Time Counter (BURTC) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -30,7 +30,6 @@
*
******************************************************************************/
-
#include "em_burtc.h"
#if defined(BURTC_PRESENT)
@@ -78,7 +77,6 @@
return log2;
}
-
/***************************************************************************//**
* @brief
* Wait for ongoing sync of register(s) to low frequency domain to complete.
@@ -93,8 +91,7 @@
activated, or when no clock is selected for the BURTC. If no clock is
selected, then the sync is done once the clock source is set. */
if ((BURTC->FREEZE & BURTC_FREEZE_REGFREEZE)
- || ((BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK) == BURTC_CTRL_CLKSEL_NONE))
- {
+ || ((BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK) == BURTC_CTRL_CLKSEL_NONE)) {
return;
}
/* Wait for any pending previous write operation to have been completed */
@@ -104,7 +101,6 @@
}
/** @endcond */
-
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
@@ -140,13 +136,13 @@
/* Note! Giant Gecko revision C errata, do NOT use LPCOMP=7 */
EFM_ASSERT(burtcInit->lowPowerComp <= 6);
/* You cannot enable the BURTC if mode is set to disabled */
- EFM_ASSERT((burtcInit->enable == false) ||
- ((burtcInit->enable == true)
- && (burtcInit->mode != burtcModeDisable)));
+ EFM_ASSERT((burtcInit->enable == false)
+ || ((burtcInit->enable == true)
+ && (burtcInit->mode != burtcModeDisable)));
/* Low power mode is only available with LFRCO or LFXO as clock source */
EFM_ASSERT((burtcInit->clkSel != burtcClkSelULFRCO)
|| ((burtcInit->clkSel == burtcClkSelULFRCO)
- && (burtcInit->lowPowerMode == burtcLPDisable)));
+ && (burtcInit->lowPowerMode == burtcLPDisable)));
/* Calculate prescaler value from clock divider input */
/* Note! If clock select (clkSel) is ULFRCO, a clock divisor (clkDiv) of
@@ -155,8 +151,7 @@
presc = divToLog2(burtcInit->clkDiv);
/* Make sure all registers are updated simultaneously */
- if (burtcInit->enable)
- {
+ if (burtcInit->enable) {
BURTC_FreezeEnable(true);
}
@@ -184,8 +179,7 @@
BURTC->CTRL = ctrl;
/* Enable BURTC and counter */
- if (burtcInit->enable)
- {
+ if (burtcInit->enable) {
/* To enable BURTC counter, we need to disable reset */
BURTC_Enable(true);
@@ -194,7 +188,6 @@
}
}
-
/***************************************************************************//**
* @brief Set BURTC compare channel
*
@@ -216,7 +209,6 @@
BURTC->COMP0 = value;
}
-
/***************************************************************************//**
* @brief Get BURTC compare value
*
@@ -233,7 +225,6 @@
return BURTC->COMP0;
}
-
/***************************************************************************//**
* @brief Reset counter
******************************************************************************/
@@ -244,7 +235,6 @@
BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);
}
-
/***************************************************************************//**
* @brief
* Restore BURTC to reset state
@@ -263,7 +253,6 @@
BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState);
}
-
/***************************************************************************//**
* @brief
* Get clock frequency of the BURTC.
@@ -280,16 +269,12 @@
clkSel = BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK;
clkDiv = (BURTC->CTRL & _BURTC_CTRL_PRESC_MASK) >> _BURTC_CTRL_PRESC_SHIFT;
- switch (clkSel)
- {
+ switch (clkSel) {
/** Ultra low frequency (1 kHz) clock */
case BURTC_CTRL_CLKSEL_ULFRCO:
- if (_BURTC_CTRL_PRESC_DIV1 == clkDiv)
- {
+ if (_BURTC_CTRL_PRESC_DIV1 == clkDiv) {
frequency = 2000; /* 2KHz when clock divisor is 1. */
- }
- else
- {
+ } else {
frequency = SystemULFRCOClockGet(); /* 1KHz when divisor is different
from 1. */
}
@@ -312,7 +297,6 @@
return frequency;
}
-
/** @} (end addtogroup BURTC) */
/** @} (end addtogroup emlib) */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_can.c Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,912 @@
+/***************************************************************************//**
+ * @file em_can.c
+ * @brief Controller Area Network API
+ * @version 5.3.3
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#include "em_can.h"
+#include "em_common.h"
+#include "em_assert.h"
+#include "em_cmu.h"
+#include <stddef.h>
+
+#if defined(CAN_COUNT) && (CAN_COUNT > 0)
+
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+
+/* Macros to use the ID field in the CANn_MIRx_ARB register as a 11 bit
+ * standard id. The register field can be used for both an 11 bit standard
+ * id and a 29 bit extended id. */
+#define _CAN_MIR_ARB_STD_ID_SHIFT 18
+#define _CAN_MIR_MASK_STD_SHIFT 18
+#define _CAN_MIR_ARB_STD_ID_MASK 0x1FFC0000UL
+#define _CAN_MIR_ARB_STD_ID_MAX 0x7FFUL // = 2^11 - 1
+
+#if (CAN_COUNT == 2)
+#define CAN_VALID(can) ((can == CAN0) || (can == CAN1))
+#elif (CAN_COUNT == 1)
+#define CAN_VALID(can) (can == CAN0)
+#else
+#error "The actual number of CAN busses is not supported."
+#endif
+
+/** @endcond */
+
+/***************************************************************************//**
+ * @addtogroup emlib
+ * @{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @addtogroup CAN
+ * @brief Controller Area Network API
+ *
+ * @details The Controller Area Network Interface Bus (CAN) implements a
+ * multi-master serial bus for connecting microcontrollers and devices, also
+ * known as nodes, to communicate with each other in applications without a host
+ * computer. CAN is a message-based protocol, designed originally for automotive
+ * applications, but meanwhile used also in many other surroundings.
+ * The complexity of the node can range from a simple I/O device up to an
+ * embedded computer with a CAN interface and sophisticated software. The node
+ * may also be a gateway allowing a standard computer to communicate over a USB
+ * or Ethernet port to the devices on a CAN network. Devices are connected to
+ * the bus through a host processor, a CAN controller, and a CAN transceiver.
+ *
+ * @include em_can_send_example.c
+ *
+ * @{
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************** GLOBAL FUNCTIONS *******************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ * Initialize CAN.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] init
+ * Pointer to CAN initialization structure.
+ ******************************************************************************/
+void CAN_Init(CAN_TypeDef *can, const CAN_Init_TypeDef *init)
+{
+ EFM_ASSERT(CAN_VALID(can));
+
+ CAN_Enable(can, false);
+ can->CTRL = _CAN_CTRL_TEST_MASK;
+ can->TEST = _CAN_TEST_RESETVALUE;
+ if (init->resetMessages) {
+ CAN_ResetMessages(can, 0);
+ }
+ can->CTRL = CAN_CTRL_INIT;
+ CAN_SetBitTiming(can,
+ init->bitrate,
+ init->propagationTimeSegment,
+ init->phaseBufferSegment1,
+ init->phaseBufferSegment2,
+ init->synchronisationJumpWidth);
+ CAN_Enable(can, init->enable);
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get the CAN module frequency.
+ *
+ * @details
+ * There is an internal prescaler of 2 inside the CAN module.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @return
+ * Clock value
+ ******************************************************************************/
+uint32_t CAN_GetClockFrequency(CAN_TypeDef *can)
+{
+#if defined CAN0
+ if (can == CAN0) {
+ return CMU_ClockFreqGet(cmuClock_CAN0) / 2;
+ }
+#endif
+
+#if defined CAN1
+ if (can == CAN1) {
+ return CMU_ClockFreqGet(cmuClock_CAN1) / 2;
+ }
+#endif
+ EFM_ASSERT(false);
+ return 0;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Read a Message Object to find if a message was lost ; reset the
+ * 'Message Lost' flag.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] interface
+ * Indicate which Message Interface Register to use.
+ *
+ * @param[in] msgNum
+ * Message number of the Message Object, [1 - 32].
+ *
+ * @return
+ * true if a message was lost, false otherwise.
+ ******************************************************************************/
+bool CAN_MessageLost(CAN_TypeDef *can, uint8_t interface, uint8_t msgNum)
+{
+ CAN_MIR_TypeDef * mir = &can->MIR[interface];
+ bool messageLost;
+
+ /* Make sure msgNum is in the correct range */
+ EFM_ASSERT((msgNum > 0) && (msgNum <= 32));
+
+ CAN_ReadyWait(can, interface);
+
+ /* Set which registers to read from the RAM */
+ mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
+ | CAN_MIR_CMDMASK_CONTROL
+ | CAN_MIR_CMDMASK_CLRINTPND;
+
+ /* Send reading request and wait (3 to 6 cpu cycle) */
+ CAN_SendRequest(can, interface, msgNum, true);
+
+ messageLost = mir->CTRL & _CAN_MIR_CTRL_MESSAGEOF_MASK;
+
+ if (messageLost) {
+ mir->CMDMASK = CAN_MIR_CMDMASK_WRRD | CAN_MIR_CMDMASK_CONTROL;
+
+ /* Reset the 'MessageLost' bit */
+ mir->CTRL &= ~_CAN_MIR_CTRL_MESSAGEOF_MASK;
+
+ /* Send reading request and wait (3 to 6 cpu cycle) */
+ CAN_SendRequest(can, interface, msgNum, true);
+ }
+
+ /* Return the state of the MESSAGEOF bit */
+ return messageLost;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Set the ROUTE registers.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] active
+ * Boolean to activate or not the ROUTE registers.
+ *
+ * @param[in] pinRxLoc
+ * Location of the rx pin.
+ *
+ * @param[in] pinTxLoc
+ * Location of the tx pin.
+ ******************************************************************************/
+void CAN_SetRoute(CAN_TypeDef *can,
+ bool active,
+ uint16_t pinRxLoc,
+ uint16_t pinTxLoc)
+{
+ if (active) {
+ /* Set the ROUTE register */
+ can->ROUTE = CAN_ROUTE_TXPEN
+ | (pinRxLoc << _CAN_ROUTE_RXLOC_SHIFT)
+ | (pinTxLoc << _CAN_ROUTE_TXLOC_SHIFT);
+ } else {
+ /* Deactivate the ROUTE register */
+ can->ROUTE = 0x0;
+ }
+}
+
+/***************************************************************************//**
+ * @brief
+ * Set the bitrate and its parameters
+ *
+ * @details
+ * There are multiple parameters which need to be properly configured.
+ * Please refer to the reference manual for a detailed description.
+ * Careful : the BRP (Baud Rate Prescaler) is calculated by:
+ * 'brp = freq / (period * bitrate);'. freq is the frequency of the CAN
+ * device, period the time of transmission of a bit. The result is an uint32_t
+ * hence it's truncated, causing an approximation error. This error is non
+ * negligeable when period is high, bitrate is high and freq is low.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] bitrate
+ * Wanted bitrate on the CAN bus.
+ *
+ * @param[in] propagationTimeSegment
+ * Value for the Propagation Time Segment.
+ *
+ * @param[in] phaseBufferSegment1
+ * Value for the Phase Buffer Segment 1.
+ *
+ * @param[in] phaseBufferSegment2
+ * Value for the Phase Buffer Segment 2.
+ *
+ * @param[in] synchronisationJumpWidth
+ * Value for the Synchronisation Jump Width.
+ ******************************************************************************/
+void CAN_SetBitTiming(CAN_TypeDef *can,
+ uint32_t bitrate,
+ uint16_t propagationTimeSegment,
+ uint16_t phaseBufferSegment1,
+ uint16_t phaseBufferSegment2,
+ uint16_t synchronisationJumpWidth)
+{
+ uint32_t sum, brp, period, freq, brpHigh, brpLow;
+
+ /* Verification that the parameters are within range */
+ EFM_ASSERT((propagationTimeSegment <= 8) && (propagationTimeSegment > 0));
+ EFM_ASSERT((phaseBufferSegment1 <= 8) && (phaseBufferSegment1 > 0));
+ EFM_ASSERT((phaseBufferSegment2 <= 8) && (phaseBufferSegment2 > 0));
+ EFM_ASSERT(bitrate > 0);
+ EFM_ASSERT((synchronisationJumpWidth <= phaseBufferSegment1)
+ && (synchronisationJumpWidth <= phaseBufferSegment2)
+ && (synchronisationJumpWidth > 0));
+
+ /* propagationTimeSegment is counted as part of phaseBufferSegment1 in the
+ BITTIMING register */
+ sum = phaseBufferSegment1 + propagationTimeSegment;
+
+ /* period is the total length of one CAN bit. 1 is the Sync_seg */
+ period = 1 + sum + phaseBufferSegment2;
+ freq = CAN_GetClockFrequency(can);
+
+ brp = freq / (period * bitrate);
+ EFM_ASSERT(brp != 0);
+
+ /* -1 because the hardware reads 'written value + 1' */
+ brp = brp - 1;
+
+ /* brp is divided between two registers */
+ brpHigh = brp / 64;
+ brpLow = brp % 64;
+
+ /* Checking register limit */
+ EFM_ASSERT(brpHigh <= 15);
+
+ bool enabled = CAN_IsEnabled(can);
+
+ /* Enable access to the bittiming registers */
+ can->CTRL |= CAN_CTRL_CCE | CAN_CTRL_INIT;
+
+ can->BITTIMING = (brpLow << _CAN_BITTIMING_BRP_SHIFT)
+ | ((synchronisationJumpWidth - 1) << _CAN_BITTIMING_SJW_SHIFT)
+ | ((sum - 1) << _CAN_BITTIMING_TSEG1_SHIFT)
+ | ((phaseBufferSegment2 - 1) << _CAN_BITTIMING_TSEG2_SHIFT);
+ can->BRPE = brpHigh;
+
+ if (enabled) {
+ can->CTRL &= ~(_CAN_CTRL_CCE_MASK | _CAN_CTRL_INIT_MASK);
+ } else {
+ can->CTRL &= ~_CAN_CTRL_CCE_MASK;
+ }
+}
+
+/***************************************************************************//**
+ * @brief
+ * Set the CAN operation mode.
+ *
+ * @details
+ * In Init mode, the CAN module is deactivated. Reset of the Messages in all
+ * the other modes to be sure that there are no leftover data and that they
+ * need to be configured before being of use.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] mode
+ * Mode of operation : Init, Normal, Loopback, SilentLoopback, Silent, Basic.
+ ******************************************************************************/
+void CAN_SetMode(CAN_TypeDef *can, CAN_Mode_TypeDef mode)
+{
+ switch (mode) {
+ case canModeNormal:
+ can->CTRL |= _CAN_CTRL_TEST_MASK;
+ can->TEST = _CAN_TEST_RESETVALUE;
+ can->CTRL &= ~_CAN_CTRL_TEST_MASK;
+
+ can->CTRL = _CAN_CTRL_EIE_MASK
+ | _CAN_CTRL_SIE_MASK
+ | _CAN_CTRL_IE_MASK;
+ break;
+
+ case canModeBasic:
+ can->CTRL = _CAN_CTRL_EIE_MASK
+ | _CAN_CTRL_SIE_MASK
+ | _CAN_CTRL_IE_MASK
+ | CAN_CTRL_TEST;
+ can->TEST = CAN_TEST_BASIC;
+ break;
+
+ case canModeLoopBack:
+ can->CTRL = _CAN_CTRL_EIE_MASK
+ | _CAN_CTRL_SIE_MASK
+ | _CAN_CTRL_IE_MASK
+ | CAN_CTRL_TEST;
+ can->TEST = CAN_TEST_LBACK;
+ break;
+
+ case canModeSilentLoopBack:
+ can->CTRL = _CAN_CTRL_EIE_MASK
+ | _CAN_CTRL_SIE_MASK
+ | _CAN_CTRL_IE_MASK
+ | CAN_CTRL_TEST;
+ can->TEST = CAN_TEST_LBACK | CAN_TEST_SILENT;
+ break;
+
+ case canModeSilent:
+ can->CTRL = _CAN_CTRL_EIE_MASK
+ | _CAN_CTRL_SIE_MASK
+ | _CAN_CTRL_IE_MASK
+ | CAN_CTRL_TEST;
+ can->TEST = CAN_TEST_SILENT;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/***************************************************************************//**
+ * @brief
+ * Set the Id and the filter for a specific Message Object.
+ *
+ * @details
+ * The Init bit have to be 0 to use this function.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] interface
+ * Indicate which Message Interface Register to use.
+ *
+ * @param[in] useMask
+ * Boolean to choose whether or not to use the masks.
+ *
+ * @param[in] message
+ * Message Object
+ *
+ * @param[in] wait
+ * If true, wait for the end of the transfer between the MIRx registers and
+ * the RAM to exit. If false, exit immediately, the transfer can still be
+ * in progress.
+ ******************************************************************************/
+void CAN_SetIdAndFilter(CAN_TypeDef *can,
+ uint8_t interface,
+ bool useMask,
+ const CAN_MessageObject_TypeDef *message,
+ bool wait)
+{
+ /* Make sure msgNum is in the correct range */
+ EFM_ASSERT((message->msgNum > 0) && (message->msgNum <= 32));
+
+ CAN_MIR_TypeDef * mir = &can->MIR[interface];
+ CAN_ReadyWait(can, interface);
+
+ /* Set which registers to read from the RAM */
+ mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
+ | CAN_MIR_CMDMASK_ARBACC
+ | CAN_MIR_CMDMASK_CONTROL;
+
+ /* Send reading request and wait (3 to 6 cpu cycle) */
+ CAN_SendRequest(can, interface, message->msgNum, true);
+
+ /* Reset MSGVAL */
+ mir->CMDMASK |= CAN_MIR_CMDMASK_WRRD;
+ mir->ARB &= ~(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT);
+ CAN_SendRequest(can, interface, message->msgNum, true);
+
+ /* Set which registers to write to the RAM */
+ mir->CMDMASK |= CAN_MIR_CMDMASK_MASKACC;
+
+ /* Set UMASK bit */
+ BUS_RegBitWrite(&mir->CTRL, _CAN_MIR_CTRL_UMASK_SHIFT, useMask);
+
+ /* Configure the id */
+ if (message->extended) {
+ EFM_ASSERT(message->id <= _CAN_MIR_ARB_ID_MASK);
+ mir->ARB = (mir->ARB & ~_CAN_MIR_ARB_ID_MASK)
+ | (message->id << _CAN_MIR_ARB_ID_SHIFT)
+ | (uint32_t)(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT)
+ | CAN_MIR_ARB_XTD_EXT;
+ } else {
+ EFM_ASSERT(message->id <= _CAN_MIR_ARB_STD_ID_MAX);
+ mir->ARB = (mir->ARB & ~(_CAN_MIR_ARB_ID_MASK | CAN_MIR_ARB_XTD_STD))
+ | (message->id << _CAN_MIR_ARB_STD_ID_SHIFT)
+ | (uint32_t)(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT);
+ }
+
+ if (message->extendedMask) {
+ mir->MASK = (message->mask << _CAN_MIR_MASK_MASK_SHIFT);
+ } else {
+ mir->MASK = (message->mask << _CAN_MIR_MASK_STD_SHIFT)
+ & _CAN_MIR_ARB_STD_ID_MASK;
+ }
+
+ /* Configure the masks */
+ mir->MASK |= (message->extendedMask << _CAN_MIR_MASK_MXTD_SHIFT)
+ | (message->directionMask << _CAN_MIR_MASK_MDIR_SHIFT);
+
+ /* Send writing request */
+ CAN_SendRequest(can, interface, message->msgNum, wait);
+}
+
+/***************************************************************************//**
+ * @brief
+ * Configure valid, tx/rx, remoteTransfer for a specific Message Object.
+ *
+ * @details
+ * The Init bit have to be 0 to use this function.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] interface
+ * Indicate which Message Interface Register to use.
+ *
+ * @param[in] msgNum
+ * Message number of this Message Object, [1 - 32].
+ *
+ * @param[in] valid
+ * true if Message Object is valid, false otherwise.
+ *
+ * @param[in] tx
+ * true if Message Object is used for transmission, false if used for
+ * reception.
+ *
+ * @param[in] remoteTransfer
+ * true if Message Object is used for remote transmission, false otherwise.
+ *
+ * @param[in] endOfBuffer
+ * true if it is for a single Message Object or the end of a fifo buffer,
+ * false if the Message Object is part of a fifo buffer and not the last.
+ *
+ * @param[in] wait
+ * If true, wait for the end of the transfer between the MIRx registers and
+ * the RAM to exit. If false, exit immediately, the transfer can still be
+ * in progress.
+ ******************************************************************************/
+void CAN_ConfigureMessageObject(CAN_TypeDef *can,
+ uint8_t interface,
+ uint8_t msgNum,
+ bool valid,
+ bool tx,
+ bool remoteTransfer,
+ bool endOfBuffer,
+ bool wait)
+{
+ CAN_MIR_TypeDef * mir = &can->MIR[interface];
+
+ /* Make sure msgNum is in the correct range */
+ EFM_ASSERT((msgNum > 0) && (msgNum <= 32));
+
+ CAN_ReadyWait(can, interface);
+
+ /* Set which registers to read from the RAM */
+ mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
+ | CAN_MIR_CMDMASK_ARBACC
+ | CAN_MIR_CMDMASK_CONTROL;
+
+ /* Send reading request and wait (3 to 6 cpu cycle) */
+ CAN_SendRequest(can, interface, msgNum, true);
+
+ /* Set which registers to write to the RAM */
+ mir->CMDMASK |= CAN_MIR_CMDMASK_WRRD;
+
+ /* Configure valid message and direction */
+ mir->ARB = (mir->ARB & ~(_CAN_MIR_ARB_DIR_MASK | _CAN_MIR_ARB_MSGVAL_MASK))
+ | (valid << _CAN_MIR_ARB_MSGVAL_SHIFT)
+ | (tx << _CAN_MIR_ARB_DIR_SHIFT);
+
+ /* Set eob bit, rx and tx interrupts */
+ mir->CTRL = (endOfBuffer << _CAN_MIR_CTRL_EOB_SHIFT)
+ | _CAN_MIR_CTRL_TXIE_MASK
+ | _CAN_MIR_CTRL_RXIE_MASK
+ | (remoteTransfer << _CAN_MIR_CTRL_RMTEN_SHIFT);
+
+ /* Send writing request */
+ CAN_SendRequest(can, interface, msgNum, wait);
+}
+
+/***************************************************************************//**
+ * @brief
+ * Send the data from the Message Object message.
+ *
+ * @details
+ * If message is configured as tx and remoteTransfer = 0, calling this function
+ * will send the data of this Message Object if its parameters are correct.
+ * If message is tx and remoteTransfer = 1, this function will set the data of
+ * message to the RAM and exit, the data will be automatically sent after
+ * reception of a remote frame.
+ * If message is rx and remoteTransfer = 1, this function will send a remote
+ * frame to the corresponding id.
+ * If message is rx and remoteTransfer = 0, the user shouldn't call this
+ * function. It will also send a remote frame.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] interface
+ * Indicate which Message Interface Register to use.
+ *
+ * @param[in] message
+ * Message Object
+ *
+ * @param[in] wait
+ * If true, wait for the end of the transfer between the MIRx registers and
+ * the RAM to exit. If false, exit immediately, the transfer can still be
+ * in progress.
+ ******************************************************************************/
+void CAN_SendMessage(CAN_TypeDef *can,
+ uint8_t interface,
+ const CAN_MessageObject_TypeDef *message,
+ bool wait)
+{
+ CAN_MIR_TypeDef * mir = &can->MIR[interface];
+
+ /* Make sure msgNum is in the correct range */
+ EFM_ASSERT((message->msgNum > 0) && (message->msgNum <= 32));
+ /* Make sure dlc is in the correct range */
+ EFM_ASSERT(message->dlc <= _CAN_MIR_CTRL_DLC_MASK);
+
+ CAN_ReadyWait(can, interface);
+
+ /* Set LEC to unused value to be sure it is reset to 0 after sending */
+ BUS_RegMaskedWrite(&can->STATUS, _CAN_STATUS_LEC_MASK, 0x7);
+
+ /* Set which registers to read from the RAM */
+ mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
+ | CAN_MIR_CMDMASK_ARBACC
+ | CAN_MIR_CMDMASK_CONTROL;
+
+ /* Send reading request and wait (3 to 6 cpu cycle) */
+ CAN_SendRequest(can, interface, message->msgNum, true);
+
+ /* Reset MSGVAL */
+ mir->CMDMASK |= CAN_MIR_CMDMASK_WRRD;
+ mir->ARB &= ~(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT);
+ CAN_SendRequest(can, interface, message->msgNum, true);
+
+ /* Set which registers to write to the RAM */
+ mir->CMDMASK |= CAN_MIR_CMDMASK_DATAA
+ | CAN_MIR_CMDMASK_DATAB;
+
+ /* If tx = 1 and remoteTransfer = 1, nothing is sent */
+ if ( ((mir->CTRL & _CAN_MIR_CTRL_RMTEN_MASK) == 0)
+ || ((mir->ARB & _CAN_MIR_ARB_DIR_MASK) == _CAN_MIR_ARB_DIR_RX)) {
+ mir->CTRL |= CAN_MIR_CTRL_TXRQST;
+ /* DATAVALID is set only if it is not sending a remote message */
+ if ((mir->CTRL & _CAN_MIR_CTRL_RMTEN_MASK) == 0) {
+ mir->CTRL |= CAN_MIR_CTRL_DATAVALID;
+ }
+ }
+
+ /* Set the Data length Code */
+ mir->CTRL = (mir->CTRL & ~_CAN_MIR_CTRL_DLC_MASK)
+ | message->dlc;
+
+ /* Configure the id */
+ if (message->extended) {
+ EFM_ASSERT(message->id <= _CAN_MIR_ARB_ID_MASK);
+ mir->ARB = (mir->ARB & ~_CAN_MIR_ARB_ID_MASK)
+ | (message->id << _CAN_MIR_ARB_ID_SHIFT)
+ | (uint32_t)(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT)
+ | CAN_MIR_ARB_XTD_EXT;
+ } else {
+ EFM_ASSERT(message->id <= _CAN_MIR_ARB_STD_ID_MAX);
+ mir->ARB = (mir->ARB & ~(_CAN_MIR_ARB_ID_MASK | _CAN_MIR_ARB_XTD_MASK))
+ | (uint32_t)(0x1 << _CAN_MIR_ARB_MSGVAL_SHIFT)
+ | (message->id << _CAN_MIR_ARB_STD_ID_SHIFT)
+ | CAN_MIR_ARB_XTD_STD;
+ }
+
+ /* Set the data */
+ CAN_WriteData(can, interface, message);
+
+ /* Send writing request */
+ CAN_SendRequest(can, interface, message->msgNum, wait);
+}
+
+/***************************************************************************//**
+ * @brief
+ * Read the data from a Message Object in the RAM and store it in message.
+ *
+ * @details
+ * Read all the information from the RAM on this Message Object : the data but
+ * also the configuration of the other registers.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] interface
+ * Indicate which Message Interface Register to use.
+ *
+ * @param[in] message
+ * Message Object
+ ******************************************************************************/
+void CAN_ReadMessage(CAN_TypeDef *can,
+ uint8_t interface,
+ CAN_MessageObject_TypeDef *message)
+{
+ CAN_MIR_TypeDef * mir = &can->MIR[interface];
+ uint32_t buffer;
+ uint32_t i;
+
+ /* Make sure msgNum is in the correct range */
+ EFM_ASSERT((message->msgNum > 0) && (message->msgNum <= 32));
+
+ CAN_ReadyWait(can, interface);
+
+ /* Set which registers to read from the RAM */
+ mir->CMDMASK = CAN_MIR_CMDMASK_WRRD_READ
+ | CAN_MIR_CMDMASK_MASKACC
+ | CAN_MIR_CMDMASK_ARBACC
+ | CAN_MIR_CMDMASK_CONTROL
+ | CAN_MIR_CMDMASK_CLRINTPND
+ | CAN_MIR_CMDMASK_TXRQSTNEWDAT
+ | CAN_MIR_CMDMASK_DATAA
+ | CAN_MIR_CMDMASK_DATAB;
+
+ /* Send reading request and wait (3 to 6 cpu cycle) */
+ CAN_SendRequest(can, interface, message->msgNum, true);
+
+ /* Get dlc from the control register */
+ message->dlc = ((mir->CTRL & _CAN_MIR_CTRL_DLC_MASK) >> _CAN_MIR_CTRL_DLC_SHIFT);
+
+ /* Make sure dlc is in the correct range */
+ EFM_ASSERT(message->dlc <= 8);
+
+ /* Copy the data from the MIR registers to the Message Object message */
+ buffer = mir->DATAL;
+ for (i = 0; i < SL_MIN(message->dlc, 4U); ++i) {
+ message->data[i] = buffer & 0xFF;
+ buffer = buffer >> 8;
+ }
+ if (message->dlc > 3) {
+ buffer = mir->DATAH;
+ for (i = 0; i < message->dlc - 4U; ++i) {
+ message->data[i + 4] = buffer & 0xFF;
+ buffer = buffer >> 8;
+ }
+ }
+}
+
+/***************************************************************************//**
+ * @brief
+ * Abort the sending of a message
+ *
+ * @details
+ * Set the TXRQST of the CTRL register to 0. Doesn't touch the data ot the
+ * others parameters. The user can reuse CAN_SendMessage() to send the object
+ * after using CAN_AbortSendMessage().
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] interface
+ * Indicate which Message Interface Register to use.
+ *
+ * @param[in] msgNum
+ * Message number of this Message Object, [1 - 32].
+ *
+ * @param[in] wait
+ * If true, wait for the end of the transfer between the MIRx registers and
+ * the RAM to exit. If false, exit immediately, the transfer can still be
+ * in progress.
+ ******************************************************************************/
+void CAN_AbortSendMessage(CAN_TypeDef *can,
+ uint8_t interface,
+ uint8_t msgNum,
+ bool wait)
+{
+ /* Make sure msgNum is in the correct range */
+ EFM_ASSERT((msgNum > 0) && (msgNum <= 32));
+
+ CAN_MIR_TypeDef * mir = &can->MIR[interface];
+ CAN_ReadyWait(can, interface);
+
+ /* Set which registers to write to the RAM */
+ mir->CMDMASK = CAN_MIR_CMDMASK_WRRD
+ | CAN_MIR_CMDMASK_ARBACC;
+
+ /* Set TXRQST bit to 0 */
+ mir->ARB &= ~_CAN_MIR_CTRL_TXRQST_MASK;
+
+ /* Send writing request */
+ CAN_SendRequest(can, interface, msgNum, wait);
+}
+
+/***************************************************************************//**
+ * @brief
+ * Reset all the Message Objects and set their data to 0.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] interface
+ * Indicate which Message Interface Register to use.
+ ******************************************************************************/
+void CAN_ResetMessages(CAN_TypeDef *can, uint8_t interface)
+{
+ CAN_MIR_TypeDef * mir = &can->MIR[interface];
+ CAN_ReadyWait(can, interface);
+
+ /* Set which registers to read from the RAM */
+ mir->CMDMASK = CAN_MIR_CMDMASK_WRRD
+ | CAN_MIR_CMDMASK_MASKACC
+ | CAN_MIR_CMDMASK_ARBACC
+ | CAN_MIR_CMDMASK_CONTROL
+ | CAN_MIR_CMDMASK_DATAA
+ | CAN_MIR_CMDMASK_DATAB;
+
+ mir->MASK = _CAN_MIR_MASK_RESETVALUE;
+ mir->ARB = _CAN_MIR_ARB_RESETVALUE;
+ mir->CTRL = _CAN_MIR_CTRL_RESETVALUE;
+ mir->DATAL = 0x00000000;
+ mir->DATAH = 0x00000000;
+
+ /* Write each reset Message Object to the RAM */
+ for (int i = 1; i <= 32; ++i) {
+ CAN_SendRequest(can, interface, i, true);
+ }
+}
+
+/***************************************************************************//**
+ * @brief
+ * Set all the CAN registers to RESETVALUE. Leave the CAN Device disabled.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ ******************************************************************************/
+void CAN_Reset(CAN_TypeDef *can)
+{
+ CAN_ReadyWait(can, 0);
+ CAN_ReadyWait(can, 1);
+
+ CAN_Enable(can, false);
+ can->STATUS = _CAN_STATUS_RESETVALUE;
+
+ can->CTRL |= _CAN_CTRL_CCE_MASK;
+ can->BITTIMING = _CAN_BITTIMING_RESETVALUE;
+ can->CTRL &= ~_CAN_CTRL_CCE_MASK;
+
+ can->CTRL |= _CAN_CTRL_TEST_MASK;
+ can->TEST = _CAN_TEST_RESETVALUE;
+ can->CTRL &= ~_CAN_CTRL_TEST_MASK;
+
+ can->BRPE = _CAN_BRPE_RESETVALUE;
+ can->CONFIG = _CAN_CONFIG_RESETVALUE;
+ can->IF0IFS = _CAN_IF0IFS_RESETVALUE;
+ can->IF0IFC = _CAN_IF0IFC_RESETVALUE;
+ can->IF0IEN = _CAN_IF0IEN_RESETVALUE;
+ can->IF1IFS = _CAN_IF1IF_RESETVALUE;
+ can->IF1IFC = _CAN_IF1IFC_RESETVALUE;
+ can->IF1IEN = _CAN_IF1IEN_RESETVALUE;
+ can->ROUTE = _CAN_ROUTE_RESETVALUE;
+
+ for (int i = 0; i < 2; i++) {
+ can->MIR[i].CMDMASK = _CAN_MIR_CMDMASK_RESETVALUE;
+ can->MIR[i].MASK = _CAN_MIR_MASK_RESETVALUE;
+ can->MIR[i].ARB = _CAN_MIR_ARB_RESETVALUE;
+ can->MIR[i].CTRL = _CAN_MIR_CTRL_RESETVALUE;
+ can->MIR[i].DATAL = _CAN_MIR_DATAL_RESETVALUE;
+ can->MIR[i].DATAH = _CAN_MIR_DATAH_RESETVALUE;
+ can->MIR[i].CMDREQ = _CAN_MIR_CMDREQ_RESETVALUE;
+ }
+}
+
+/***************************************************************************//**
+ * @brief
+ * Write the data from message to the MIRx registers
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] interface
+ * Indicate which Message Interface Register to use.
+ *
+ * @param[in] message
+ * Message Object
+ ******************************************************************************/
+void CAN_WriteData(CAN_TypeDef *can,
+ uint8_t interface,
+ const CAN_MessageObject_TypeDef *message)
+{
+ CAN_MIR_TypeDef * mir = &can->MIR[interface];
+ uint8_t data[8] = { 0 };
+ size_t length = SL_MIN(8, message->dlc);
+
+ for (size_t i = 0; i < length; i++) {
+ data[i] = message->data[i];
+ }
+
+ CAN_ReadyWait(can, interface);
+ mir->DATAL = (data[3] << 24)
+ | (data[2] << 16)
+ | (data[1] << 8)
+ | (data[0] << 0);
+ mir->DATAH = (data[7] << 24)
+ | (data[6] << 16)
+ | (data[5] << 8)
+ | (data[4] << 0);
+}
+
+/***************************************************************************//**
+ * @brief
+ * Send request for writing or reading the RAM of Message Object msgNum.
+ *
+ * @param[in] can
+ * Pointer to CAN peripheral register block.
+ *
+ * @param[in] interface
+ * Indicate which Message Interface Register to use.
+ *
+ * @param[in] msgNum
+ * Message number of the Message Object, [1 - 32].
+ *
+ * @param[in] wait
+ * If true, wait for the end of the transfer between the MIRx registers and
+ * the RAM to exit. If false, exit immediately, the transfer can still be
+ * in progress.
+ ******************************************************************************/
+void CAN_SendRequest(CAN_TypeDef *can,
+ uint8_t interface,
+ uint8_t msgNum,
+ bool wait)
+{
+ CAN_MIR_TypeDef * mir = &can->MIR[interface];
+
+ /* Make sure msgNum is in the correct range */
+ EFM_ASSERT((msgNum > 0) && (msgNum <= 32));
+
+ /* Make sure the MIRx registers aren't busy */
+ CAN_ReadyWait(can, interface);
+
+ /* Write msgNum to the CMDREQ register */
+ mir->CMDREQ = msgNum << _CAN_MIR_CMDREQ_MSGNUM_SHIFT;
+
+ if (wait) {
+ CAN_ReadyWait(can, interface);
+ }
+}
+
+/** @} (end addtogroup CAN) */
+/** @} (end addtogroup emlib) */
+
+#endif /* defined(CAN_COUNT) && (CAN_COUNT > 0) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_cmu.c
* @brief Clock management unit (CMU) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -29,8 +29,9 @@
* arising from your use of this Software.
*
******************************************************************************/
+
#include "em_cmu.h"
-#if defined( CMU_PRESENT )
+#if defined(CMU_PRESENT)
#include <stddef.h>
#include <limits.h>
@@ -61,52 +62,216 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_0)
/** Maximum allowed core frequency when using 0 wait-states on flash access. */
-#define CMU_MAX_FREQ_0WS 26000000
+#define CMU_MAX_FREQ_0WS 16000000
/** Maximum allowed core frequency when using 1 wait-states on flash access */
-#define CMU_MAX_FREQ_1WS 40000000
-#elif defined( _SILICON_LABS_32B_SERIES_0 )
-/** Maximum allowed core frequency when using 0 wait-states on flash access. */
-#define CMU_MAX_FREQ_0WS 16000000
-/** Maximum allowed core frequency when using 1 wait-states on flash access */
-#define CMU_MAX_FREQ_1WS 32000000
+#define CMU_MAX_FREQ_1WS 32000000
+
+#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 80)
+// EFR32xG1x and EFM32xG1x
+#define CMU_MAX_FREQ_0WS_1V2 25000000
+#define CMU_MAX_FREQ_1WS_1V2 40000000
+
+#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 84)
+// EFR32xG12x and EFM32xG12x
+#define CMU_MAX_FREQ_0WS_1V2 25000000
+#define CMU_MAX_FREQ_1WS_1V2 40000000
+#define CMU_MAX_FREQ_0WS_1V1 21330000
+#define CMU_MAX_FREQ_1WS_1V1 32000000
+#define CMU_MAX_FREQ_0WS_1V0 7000000
+#define CMU_MAX_FREQ_1WS_1V0 14000000
+#define CMU_MAX_FREQ_2WS_1V0 21000000
+
+#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 89)
+// EFR32xG13x and EFM32xG13x
+#define CMU_MAX_FREQ_0WS_1V2 25000000
+#define CMU_MAX_FREQ_1WS_1V2 40000000
+#define CMU_MAX_FREQ_0WS_1V0 7000000
+#define CMU_MAX_FREQ_1WS_1V0 14000000
+#define CMU_MAX_FREQ_2WS_1V0 21000000
+
+#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 95)
+// EFR32xG14x and EFM32xG14x
+#define CMU_MAX_FREQ_0WS_1V2 25000000
+#define CMU_MAX_FREQ_1WS_1V2 40000000
+#define CMU_MAX_FREQ_0WS_1V0 7000000
+#define CMU_MAX_FREQ_1WS_1V0 14000000
+#define CMU_MAX_FREQ_2WS_1V0 21000000
+
+#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 100)
+// EFM32GG11x
+#define CMU_MAX_FREQ_0WS_1V2 18000000
+#define CMU_MAX_FREQ_1WS_1V2 36000000
+#define CMU_MAX_FREQ_2WS_1V2 54000000
+#define CMU_MAX_FREQ_3WS_1V2 72000000
+#define CMU_MAX_FREQ_0WS_1V0 7000000
+#define CMU_MAX_FREQ_1WS_1V0 14000000
+#define CMU_MAX_FREQ_2WS_1V0 21000000
+
+#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 103)
+// EFM32TG11x
+#define CMU_MAX_FREQ_0WS_1V2 25000000
+#define CMU_MAX_FREQ_1WS_1V2 48000000
+#define CMU_MAX_FREQ_0WS_1V0 10000000
+#define CMU_MAX_FREQ_1WS_1V0 21000000
+#define CMU_MAX_FREQ_2WS_1V0 21000000
+
#else
#error "Max Flash wait-state frequencies are not defined for this platform."
#endif
/** Maximum frequency for HFLE interface */
-#if defined( CMU_CTRL_HFLE )
+#if defined(CMU_CTRL_HFLE)
/** Maximum HFLE frequency for series 0 EFM32 and EZR32 Wonder Gecko. */
-#if defined( _SILICON_LABS_32B_SERIES_0 ) \
- && (defined( _EFM32_WONDER_FAMILY ) \
- || defined( _EZR32_WONDER_FAMILY ))
+#if defined(_SILICON_LABS_32B_SERIES_0) \
+ && (defined(_EFM32_WONDER_FAMILY) \
+ || defined(_EZR32_WONDER_FAMILY))
#define CMU_MAX_FREQ_HFLE 24000000
/** Maximum HFLE frequency for other series 0 parts with maximum core clock
higher than 32MHz. */
-#elif defined( _SILICON_LABS_32B_SERIES_0 ) \
- && (defined( _EFM32_GIANT_FAMILY ) \
- || defined( _EFM32_LEOPARD_FAMILY ) \
- || defined( _EZR32_LEOPARD_FAMILY ))
+#elif defined(_SILICON_LABS_32B_SERIES_0) \
+ && (defined(_EFM32_GIANT_FAMILY) \
+ || defined(_EZR32_LEOPARD_FAMILY))
#define CMU_MAX_FREQ_HFLE maxFreqHfle()
#endif
-#elif defined( CMU_CTRL_WSHFLE )
+#elif defined(CMU_CTRL_WSHFLE)
/** Maximum HFLE frequency for series 1 parts */
#define CMU_MAX_FREQ_HFLE 32000000
#endif
+#if defined(CMU_STATUS_HFXOSHUNTOPTRDY)
+#define HFXO_TUNING_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY | CMU_STATUS_HFXOSHUNTOPTRDY)
+#define HFXO_TUNING_MODE_AUTO (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD)
+#define HFXO_TUNING_MODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD)
+#elif defined(CMU_STATUS_HFXOPEAKDETRDY)
+#define HFXO_TUNING_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY)
+#define HFXO_TUNING_MODE_AUTO (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD)
+#define HFXO_TUNING_MODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD)
+#endif
+
+#if defined(CMU_HFXOCTRL_MODE_EXTCLK)
+/** HFXO external clock mode is renamed from EXTCLK to DIGEXTCLK. */
+#define CMU_HFXOCTRL_MODE_DIGEXTCLK CMU_HFXOCTRL_MODE_EXTCLK
+#endif
+
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
+#define VSCALE_DEFAULT (EMU_VScaleGet())
+#else
+#define VSCALE_DEFAULT 0
+#endif
/*******************************************************************************
************************** LOCAL VARIABLES ********************************
******************************************************************************/
-#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
+#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz;
#endif
-#if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
+#if defined(_CMU_STATUS_HFXOSHUNTOPTRDY_MASK)
#define HFXO_INVALID_TRIM (~_CMU_HFXOTRIMSTATUS_MASK)
#endif
+#if defined(CMU_OSCENCMD_DPLLEN)
+/** Table of HFRCOCTRL values and their associated min/max frequencies and
+ optional band enumerator. */
+static const struct hfrcoCtrlTableElement{
+ uint32_t minFreq;
+ uint32_t maxFreq;
+ uint32_t value;
+ CMU_HFRCOFreq_TypeDef band;
+} hfrcoCtrlTable[] =
+{
+ // minFreq maxFreq HFRCOCTRL value band
+ { 860000, 1050000, 0xBC601F00, cmuHFRCOFreq_1M0Hz },
+ { 1050000, 1280000, 0xBC611F35, (CMU_HFRCOFreq_TypeDef)0 },
+ { 1280000, 1480000, 0xBCA21F35, (CMU_HFRCOFreq_TypeDef)0 },
+ { 1480000, 1800000, 0xAD231F35, (CMU_HFRCOFreq_TypeDef)0 },
+ { 1800000, 2110000, 0xBA601F00, cmuHFRCOFreq_2M0Hz },
+ { 2110000, 2560000, 0xBA611F35, (CMU_HFRCOFreq_TypeDef)0 },
+ { 2560000, 2970000, 0xBAA21F35, (CMU_HFRCOFreq_TypeDef)0 },
+ { 2970000, 3600000, 0xAB231F35, (CMU_HFRCOFreq_TypeDef)0 },
+ { 3600000, 4220000, 0xB8601F00, cmuHFRCOFreq_4M0Hz },
+ { 4220000, 5120000, 0xB8611F35, (CMU_HFRCOFreq_TypeDef)0 },
+ { 5120000, 5930000, 0xB8A21F35, (CMU_HFRCOFreq_TypeDef)0 },
+ { 5930000, 7520000, 0xA9231F00, cmuHFRCOFreq_7M0Hz },
+ { 7520000, 9520000, 0x99241F35, (CMU_HFRCOFreq_TypeDef)0 },
+ { 9520000, 11800000, 0x99251F35, (CMU_HFRCOFreq_TypeDef)0 },
+ { 11800000, 14400000, 0x99261F00, cmuHFRCOFreq_13M0Hz },
+ { 14400000, 17200000, 0x99271F00, cmuHFRCOFreq_16M0Hz },
+ { 17200000, 19700000, 0x99481F00, cmuHFRCOFreq_19M0Hz },
+ { 19700000, 23800000, 0x99491F35, (CMU_HFRCOFreq_TypeDef)0 },
+ { 23800000, 28700000, 0x994A1F00, cmuHFRCOFreq_26M0Hz },
+ { 28700000, 34800000, 0x996B1F00, cmuHFRCOFreq_32M0Hz },
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \
+ || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) \
+ || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
+ { 34800000, 40000000, 0x996C1F00, cmuHFRCOFreq_38M0Hz }
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
+ { 34800000, 42800000, 0x996C1F00, cmuHFRCOFreq_38M0Hz },
+ { 42800000, 51600000, 0x996D1F00, cmuHFRCOFreq_48M0Hz },
+ { 51600000, 60500000, 0x998E1F00, cmuHFRCOFreq_56M0Hz },
+ { 60500000, 72000000, 0xA98F1F00, cmuHFRCOFreq_64M0Hz }
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
+ { 34800000, 42800000, 0x996C1F00, cmuHFRCOFreq_38M0Hz },
+ { 42800000, 48000000, 0x996D1F00, cmuHFRCOFreq_48M0Hz }
+#else
+ #error "HFRCOCTRL values not set for this platform."
+#endif
+};
+
+#define HFRCOCTRLTABLE_ENTRIES (sizeof(hfrcoCtrlTable) \
+ / sizeof(struct hfrcoCtrlTableElement))
+#endif // CMU_OSCENCMD_DPLLEN
+
+#if defined(_SILICON_LABS_32B_SERIES_1) && defined(_EMU_STATUS_VSCALE_MASK)
+/* Devices with Voltage Scaling needs extra handling of wait states. */
+static const struct flashWsTableElement{
+ uint32_t maxFreq;
+ uint8_t vscale;
+ uint8_t ws;
+} flashWsTable[] =
+{
+#if (_SILICON_LABS_GECKO_INTERNAL_SDID == 100)
+ { CMU_MAX_FREQ_0WS_1V2, 0, 0 }, /* 0 wait states at max frequency 18 MHz and 1.2V */
+ { CMU_MAX_FREQ_1WS_1V2, 0, 1 }, /* 1 wait states at max frequency 36 MHz and 1.2V */
+ { CMU_MAX_FREQ_2WS_1V2, 0, 2 }, /* 2 wait states at max frequency 54 MHz and 1.2V */
+ { CMU_MAX_FREQ_3WS_1V2, 0, 3 }, /* 3 wait states at max frequency 72 MHz and 1.2V */
+ { CMU_MAX_FREQ_0WS_1V0, 2, 0 }, /* 0 wait states at max frequency 7 MHz and 1.0V */
+ { CMU_MAX_FREQ_1WS_1V0, 2, 1 }, /* 1 wait states at max frequency 14 MHz and 1.0V */
+ { CMU_MAX_FREQ_2WS_1V0, 2, 2 }, /* 2 wait states at max frequency 21 MHz and 1.0V */
+#else
+ { CMU_MAX_FREQ_0WS_1V2, 0, 0 }, /* 0 wait states at 1.2V */
+ { CMU_MAX_FREQ_1WS_1V2, 0, 1 }, /* 1 wait states at 1.2V */
+ { CMU_MAX_FREQ_0WS_1V0, 2, 0 }, /* 0 wait states at 1.0V */
+ { CMU_MAX_FREQ_1WS_1V0, 2, 1 }, /* 1 wait states at 1.0V */
+ { CMU_MAX_FREQ_2WS_1V0, 2, 2 }, /* 2 wait states at 1.0V */
+#endif
+};
+
+#define FLASH_WS_TABLE_ENTRIES (sizeof(flashWsTable) / sizeof(flashWsTable[0]))
+#endif
+
+#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) \
+ || defined(_CMU_USHFRCOTUNE_MASK)
+#ifndef EFM32_USHFRCO_STARTUP_FREQ
+#define EFM32_USHFRCO_STARTUP_FREQ (48000000UL)
+#endif
+
+static uint32_t ushfrcoFreq = EFM32_USHFRCO_STARTUP_FREQ;
+#endif
+
+/*******************************************************************************
+ ************************** LOCAL PROTOTYPES *******************************
+ ******************************************************************************/
+#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
+static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq);
+#endif
+
+#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK)
+static uint32_t CMU_USHFRCODevinfoGet(CMU_USHFRCOFreq_TypeDef freq);
+#endif
+
/** @endcond */
/*******************************************************************************
@@ -115,10 +280,9 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-#if defined( _SILICON_LABS_32B_SERIES_0 ) \
- && (defined( _EFM32_GIANT_FAMILY ) \
- || defined( _EFM32_LEOPARD_FAMILY ) \
- || defined( _EZR32_LEOPARD_FAMILY ))
+#if defined(_SILICON_LABS_32B_SERIES_0) \
+ && (defined(_EFM32_GIANT_FAMILY) \
+ || defined(_EZR32_LEOPARD_FAMILY))
/***************************************************************************//**
* @brief
* Return max allowed frequency for low energy peripherals.
@@ -127,8 +291,7 @@
{
uint16_t majorMinorRev;
- switch (SYSTEM_GetFamily())
- {
+ switch (SYSTEM_GetFamily()) {
case systemPartFamilyEfm32Leopard:
case systemPartFamilyEzr32Leopard:
/* CHIP MAJOR bit [5:0] */
@@ -141,12 +304,9 @@
majorMinorRev |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK)
>> _ROMTABLE_PID3_REVMINORLSB_SHIFT);
- if (majorMinorRev >= 0x0204)
- {
+ if (majorMinorRev >= 0x0204) {
return 24000000;
- }
- else
- {
+ } else {
return 32000000;
}
@@ -161,21 +321,21 @@
}
#endif
-#if defined( CMU_MAX_FREQ_HFLE )
+#if defined(CMU_MAX_FREQ_HFLE)
/* Unified definitions for HFLE wait-state and prescaler fields. */
-#if defined( CMU_CTRL_HFLE )
-#define CMU_HFLE_WS_MASK _CMU_CTRL_HFLE_MASK
-#define CMU_HFLE_WS_SHIFT _CMU_CTRL_HFLE_SHIFT
-#define CMU_HFLE_PRESC_REG CMU->HFCORECLKDIV
-#define CMU_HFLE_PRESC_MASK _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK
-#define CMU_HFLE_PRESC_SHIFT _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT
-#elif defined( CMU_CTRL_WSHFLE )
-#define CMU_HFLE_WS_MASK _CMU_CTRL_WSHFLE_MASK
-#define CMU_HFLE_WS_SHIFT _CMU_CTRL_WSHFLE_SHIFT
-#define CMU_HFLE_PRESC_REG CMU->HFPRESC
-#define CMU_HFLE_PRESC_MASK _CMU_HFPRESC_HFCLKLEPRESC_MASK
-#define CMU_HFLE_PRESC_SHIFT _CMU_HFPRESC_HFCLKLEPRESC_SHIFT
+#if defined(CMU_CTRL_HFLE)
+#define _GENERIC_HFLE_WS_MASK _CMU_CTRL_HFLE_MASK
+#define _GENERIC_HFLE_WS_SHIFT _CMU_CTRL_HFLE_SHIFT
+#define GENERIC_HFLE_PRESC_REG CMU->HFCORECLKDIV
+#define _GENERIC_HFLE_PRESC_MASK _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK
+#define _GENERIC_HFLE_PRESC_SHIFT _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT
+#elif defined(CMU_CTRL_WSHFLE)
+#define _GENERIC_HFLE_WS_MASK _CMU_CTRL_WSHFLE_MASK
+#define _GENERIC_HFLE_WS_SHIFT _CMU_CTRL_WSHFLE_SHIFT
+#define GENERIC_HFLE_PRESC_REG CMU->HFPRESC
+#define _GENERIC_HFLE_PRESC_MASK _CMU_HFPRESC_HFCLKLEPRESC_MASK
+#define _GENERIC_HFLE_PRESC_SHIFT _CMU_HFPRESC_HFCLKLEPRESC_SHIFT
#endif
/***************************************************************************//**
@@ -184,25 +344,35 @@
*
* @param[in] maxLeFreq
* Max LE frequency
- *
- * @param[in] maxFreq
- * Max LE frequency
******************************************************************************/
-static void setHfLeConfig(uint32_t hfFreq, uint32_t maxLeFreq)
+static void setHfLeConfig(uint32_t hfFreq)
{
- /* Check for 1 bit fields. BUS_RegBitWrite() below are going to fail if the
+ unsigned int hfleWs;
+ uint32_t hflePresc;
+
+ /* Check for 1 bit fields. @ref BUS_RegBitWrite() below are going to fail if the
fields are changed to more than 1 bit. */
- EFM_ASSERT((CMU_HFLE_WS_MASK >> CMU_HFLE_WS_SHIFT) == 0x1);
- EFM_ASSERT((CMU_HFLE_PRESC_MASK >> CMU_HFLE_PRESC_SHIFT) == 0x1);
-
- /* 0: set 0 wait-states and DIV2
- 1: set 1 wait-states and DIV4 */
- unsigned int val = (hfFreq <= maxLeFreq) ? 0 : 1;
- BUS_RegBitWrite(&CMU->CTRL, CMU_HFLE_WS_SHIFT, val);
- BUS_RegBitWrite(&CMU_HFLE_PRESC_REG, CMU_HFLE_PRESC_SHIFT, val);
+ EFM_ASSERT((_GENERIC_HFLE_WS_MASK >> _GENERIC_HFLE_WS_SHIFT) == 0x1);
+
+ /* - Enable HFLE wait-state if to allow access to LE peripherals when HFBUSCLK is
+ above maxLeFreq.
+ - Set HFLE prescaler. Allowed HFLE clock frequency is maxLeFreq. */
+
+ hfleWs = 1;
+ if (hfFreq <= CMU_MAX_FREQ_HFLE) {
+ hfleWs = 0;
+ hflePresc = 0;
+ } else if (hfFreq <= (2 * CMU_MAX_FREQ_HFLE)) {
+ hflePresc = 1;
+ } else {
+ hflePresc = 2;
+ }
+ BUS_RegBitWrite(&CMU->CTRL, _GENERIC_HFLE_WS_SHIFT, hfleWs);
+ GENERIC_HFLE_PRESC_REG = (GENERIC_HFLE_PRESC_REG & ~_GENERIC_HFLE_PRESC_MASK)
+ | (hflePresc << _GENERIC_HFLE_PRESC_SHIFT);
}
-
+#if defined(_CMU_CTRL_HFLE_MASK)
/***************************************************************************//**
* @brief
* Get HFLE wait-state configuration.
@@ -212,16 +382,11 @@
******************************************************************************/
static uint32_t getHfLeConfig(void)
{
- uint32_t ws = BUS_RegBitRead(&CMU->CTRL, CMU_HFLE_WS_SHIFT);
- uint32_t presc = BUS_RegBitRead(&CMU_HFLE_PRESC_REG, CMU_HFLE_PRESC_SHIFT);
-
- /* HFLE wait-state and DIV2(0) / DIV4(1) should
- always be set to the same value. */
- EFM_ASSERT(ws == presc);
+ uint32_t ws = BUS_RegBitRead(&CMU->CTRL, _GENERIC_HFLE_WS_SHIFT);
return ws;
}
#endif
-
+#endif
/***************************************************************************//**
* @brief
@@ -235,31 +400,24 @@
{
uint32_t ret;
-#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
+#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
ret = auxHfrcoFreq;
-#elif defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
+#elif defined(_CMU_AUXHFRCOCTRL_BAND_MASK)
/* All series 0 families except EFM32G */
- switch(CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK)
- {
+ switch (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK) {
case CMU_AUXHFRCOCTRL_BAND_1MHZ:
- if ( SYSTEM_GetProdRev() >= 19 )
- {
+ if ( SYSTEM_GetProdRev() >= 19 ) {
ret = 1200000;
- }
- else
- {
+ } else {
ret = 1000000;
}
break;
case CMU_AUXHFRCOCTRL_BAND_7MHZ:
- if ( SYSTEM_GetProdRev() >= 19 )
- {
+ if ( SYSTEM_GetProdRev() >= 19 ) {
ret = 6600000;
- }
- else
- {
+ } else {
ret = 7000000;
}
break;
@@ -276,7 +434,7 @@
ret = 21000000;
break;
-#if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
+#if defined(_CMU_AUXHFRCOCTRL_BAND_28MHZ)
case CMU_AUXHFRCOCTRL_BAND_28MHZ:
ret = 28000000;
break;
@@ -297,6 +455,24 @@
return ret;
}
+#if defined (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK) \
+ || defined (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK)
+/***************************************************************************//**
+ * @brief
+ * Get the HFSRCCLK frequency.
+ *
+ * @return
+ * HFSRCCLK Frequency in Hz
+ ******************************************************************************/
+static uint32_t hfSrcClkGet(void)
+{
+ uint32_t ret;
+
+ ret = SystemHFClockGet();
+ return ret * (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
+ >> _CMU_HFPRESC_PRESC_SHIFT));
+}
+#endif
/***************************************************************************//**
* @brief
@@ -313,8 +489,7 @@
/* Get selected clock source */
clk = CMU_ClockSelectGet(cmuClock_DBG);
- switch(clk)
- {
+ switch (clk) {
case cmuSelect_HFCLK:
ret = SystemHFClockGet();
break;
@@ -331,6 +506,202 @@
return ret;
}
+#if defined(_CMU_ADCCTRL_MASK)
+/***************************************************************************//**
+ * @brief
+ * Get the ADC n asynchronous clock frequency
+ *
+ * @return
+ * ADC n asynchronous frequency in Hz
+ ******************************************************************************/
+static uint32_t adcAsyncClkGet(uint32_t adc)
+{
+ uint32_t ret;
+ CMU_Select_TypeDef clk;
+
+ /* Get selected clock source */
+ switch (adc) {
+ case 0:
+ clk = CMU_ClockSelectGet(cmuClock_ADC0ASYNC);
+ break;
+
+#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK)
+ case 1:
+ clk = CMU_ClockSelectGet(cmuClock_ADC1ASYNC);
+ break;
+#endif
+
+ default:
+ EFM_ASSERT(0);
+ return 0;
+ }
+
+ switch (clk) {
+ case cmuSelect_Disabled:
+ ret = 0;
+ break;
+
+ case cmuSelect_AUXHFRCO:
+ ret = auxClkGet();
+ break;
+
+ case cmuSelect_HFXO:
+ ret = SystemHFXOClockGet();
+ break;
+
+ case cmuSelect_HFSRCCLK:
+ ret = hfSrcClkGet();
+ break;
+
+ default:
+ EFM_ASSERT(0);
+ ret = 0;
+ break;
+ }
+ return ret;
+}
+#endif
+
+#if defined(_CMU_SDIOCTRL_MASK)
+/***************************************************************************//**
+ * @brief
+ * Get the SDIO reference clock frequency
+ *
+ * @return
+ * SDIO reference clock frequency in Hz
+ ******************************************************************************/
+static uint32_t sdioRefClkGet(void)
+{
+ uint32_t ret;
+ CMU_Select_TypeDef clk;
+
+ /* Get selected clock source */
+ clk = CMU_ClockSelectGet(cmuClock_SDIOREF);
+
+ switch (clk) {
+ case cmuSelect_HFRCO:
+ ret = SystemHfrcoFreq;
+ break;
+
+ case cmuSelect_HFXO:
+ ret = SystemHFXOClockGet();
+ break;
+
+ case cmuSelect_AUXHFRCO:
+ ret = auxClkGet();
+ break;
+
+ case cmuSelect_USHFRCO:
+ ret = ushfrcoFreq;
+ break;
+
+ default:
+ EFM_ASSERT(0);
+ ret = 0;
+ break;
+ }
+ return ret;
+}
+#endif
+
+#if defined(_CMU_QSPICTRL_MASK)
+/***************************************************************************//**
+ * @brief
+ * Get the QSPI n reference clock frequency
+ *
+ * @return
+ * QSPI n reference clock frequency in Hz
+ ******************************************************************************/
+static uint32_t qspiRefClkGet(uint32_t qspi)
+{
+ uint32_t ret;
+ CMU_Select_TypeDef clk;
+
+ /* Get selected clock source */
+ switch (qspi) {
+ case 0:
+ clk = CMU_ClockSelectGet(cmuClock_QSPI0REF);
+ break;
+
+ default:
+ EFM_ASSERT(0);
+ return 0;
+ }
+
+ switch (clk) {
+ case cmuSelect_HFRCO:
+ ret = SystemHfrcoFreq;
+ break;
+
+ case cmuSelect_HFXO:
+ ret = SystemHFXOClockGet();
+ break;
+
+ case cmuSelect_AUXHFRCO:
+ ret = auxClkGet();
+ break;
+
+ case cmuSelect_USHFRCO:
+ ret = ushfrcoFreq;
+ break;
+
+ default:
+ EFM_ASSERT(0);
+ ret = 0;
+ break;
+ }
+ return ret;
+}
+#endif
+
+#if defined(USBR_CLOCK_PRESENT)
+/***************************************************************************//**
+ * @brief
+ * Get the USB rate clock frequency
+ *
+ * @return
+ * USB rate clock frequency in Hz
+ ******************************************************************************/
+static uint32_t usbRateClkGet(void)
+{
+ uint32_t ret;
+ CMU_Select_TypeDef clk;
+
+ clk = CMU_ClockSelectGet(cmuClock_USBR);
+
+ switch (clk) {
+ case cmuSelect_USHFRCO:
+ ret = ushfrcoFreq;
+ break;
+
+ case cmuSelect_HFXO:
+ ret = SystemHFXOClockGet();
+ break;
+
+ case cmuSelect_HFXOX2:
+ ret = 2u * SystemHFXOClockGet();
+ break;
+
+ case cmuSelect_HFRCO:
+ ret = SystemHfrcoFreq;
+ break;
+
+ case cmuSelect_LFXO:
+ ret = SystemLFXOClockGet();
+ break;
+
+ case cmuSelect_LFRCO:
+ ret = SystemLFRCOClockGet();
+ break;
+
+ default:
+ EFM_ASSERT(0);
+ ret = 0;
+ break;
+ }
+ return ret;
+}
+#endif
/***************************************************************************//**
* @brief
@@ -339,14 +710,18 @@
*
* @param[in] coreFreq
* Core clock frequency to configure flash wait-states for
+ *
+ * @param[in] vscale
+ * Voltage Scale level. Supported levels are 0 and 2 where 0 is the default.
******************************************************************************/
-static void flashWaitStateControl(uint32_t coreFreq)
+static void flashWaitStateControl(uint32_t coreFreq, int vscale)
{
uint32_t mode;
bool mscLocked;
-#if defined( MSC_READCTRL_MODE_WS0SCBTP )
+#if defined(MSC_READCTRL_MODE_WS0SCBTP)
bool scbtpEn; /* Suppressed Conditional Branch Target Prefetch setting. */
#endif
+ (void) vscale; /* vscale parameter is only used on some devices */
/* Make sure the MSC is unlocked */
mscLocked = MSC->LOCK;
@@ -354,12 +729,14 @@
/* Get mode and SCBTP enable */
mode = MSC->READCTRL & _MSC_READCTRL_MODE_MASK;
-#if defined( MSC_READCTRL_MODE_WS0SCBTP )
- switch(mode)
- {
+
+#if defined(_SILICON_LABS_32B_SERIES_0)
+#if defined(MSC_READCTRL_MODE_WS0SCBTP)
+ /* Devices with MODE and SCBTP in same register field */
+ switch (mode) {
case MSC_READCTRL_MODE_WS0:
case MSC_READCTRL_MODE_WS1:
-#if defined( MSC_READCTRL_MODE_WS2 )
+#if defined(MSC_READCTRL_MODE_WS2)
case MSC_READCTRL_MODE_WS2:
#endif
scbtpEn = false;
@@ -367,63 +744,88 @@
default: /* WSxSCBTP */
scbtpEn = true;
- break;
+ break;
}
-#endif
-
/* Set mode based on the core clock frequency and SCBTP enable */
-#if defined( MSC_READCTRL_MODE_WS0SCBTP )
- if (false)
- {
+ if (false) {
}
-#if defined( MSC_READCTRL_MODE_WS2 )
- else if (coreFreq > CMU_MAX_FREQ_1WS)
- {
+#if defined(MSC_READCTRL_MODE_WS2)
+ else if (coreFreq > CMU_MAX_FREQ_1WS) {
mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2);
}
#endif
- else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
- {
+ else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS)) {
mode = (scbtpEn ? MSC_READCTRL_MODE_WS1SCBTP : MSC_READCTRL_MODE_WS1);
- }
- else
- {
+ } else {
mode = (scbtpEn ? MSC_READCTRL_MODE_WS0SCBTP : MSC_READCTRL_MODE_WS0);
}
-
-#else /* If MODE and SCBTP is in separate register fields */
-
- if (false)
- {
+#else
+ if (coreFreq <= CMU_MAX_FREQ_0WS) {
+ mode = 0;
+ } else if (coreFreq <= CMU_MAX_FREQ_1WS) {
+ mode = 1;
}
-#if defined( MSC_READCTRL_MODE_WS2 )
- else if (coreFreq > CMU_MAX_FREQ_1WS)
- {
- mode = MSC_READCTRL_MODE_WS2;
+#endif
+// End defined(_SILICON_LABS_32B_SERIES_0)
+
+#elif defined(_SILICON_LABS_32B_SERIES_1)
+#if defined(_EMU_STATUS_VSCALE_MASK)
+
+ /* These devices have specific requirements on the supported flash wait state
+ * depending on frequency and voltage scale level. */
+ uint32_t i;
+ for (i = 0; i < FLASH_WS_TABLE_ENTRIES; i++) {
+ if ((flashWsTable[i].vscale == vscale)
+ && (coreFreq <= flashWsTable[i].maxFreq)) {
+ break; // found matching entry
+ }
+ }
+
+ if (i == FLASH_WS_TABLE_ENTRIES) {
+ EFM_ASSERT(false);
+ mode = 3; // worst case flash wait state for unsupported cases
+ } else {
+ mode = flashWsTable[i].ws;
}
-#endif
- else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
- {
- mode = MSC_READCTRL_MODE_WS1;
+ mode = mode << _MSC_READCTRL_MODE_SHIFT;
+
+#else
+ /* Devices where MODE and SCBTP are in separate fields and where the device
+ * either does not support voltage scale or where the voltage scale does
+ * not impact flash wait state configuration. */
+ if (coreFreq <= CMU_MAX_FREQ_0WS_1V2) {
+ mode = 0;
+ } else if (coreFreq <= CMU_MAX_FREQ_1WS_1V2) {
+ mode = 1;
}
- else
- {
- mode = MSC_READCTRL_MODE_WS0;
+#if defined(MSC_READCTRL_MODE_WS2)
+ else if (coreFreq <= CMU_MAX_FREQ_2WS) {
+ mode = 2;
}
#endif
-
- /* BUS_RegMaskedWrite cannot be used here as it would temporarely set the
+#if defined(MSC_READCTRL_MODE_WS3)
+ else if (coreFreq <= CMU_MAX_FREQ_3WS) {
+ mode = 3;
+ }
+#endif
+ mode = mode << _MSC_READCTRL_MODE_SHIFT;
+#endif
+// End defined(_SILICON_LABS_32B_SERIES_1)
+
+#else
+#error "Undefined 32B SERIES!"
+#endif
+
+ /* BUS_RegMaskedWrite cannot be used here as it would temporarily set the
mode field to WS0 */
- MSC->READCTRL = (MSC->READCTRL &~_MSC_READCTRL_MODE_MASK) | mode;
-
- if (mscLocked)
- {
+ MSC->READCTRL = (MSC->READCTRL & ~_MSC_READCTRL_MODE_MASK) | mode;
+
+ if (mscLocked) {
MSC->LOCK = 0;
}
}
-
/***************************************************************************//**
* @brief
* Configure flash access wait states to most conservative setting for
@@ -432,9 +834,100 @@
******************************************************************************/
static void flashWaitStateMax(void)
{
- flashWaitStateControl(SystemMaxCoreClockGet());
+ flashWaitStateControl(SystemMaxCoreClockGet(), 0);
+}
+
+#if defined(_MSC_RAMCTRL_RAMWSEN_MASK)
+/***************************************************************************//**
+ * @brief
+ * Configure RAM access wait states in order to support given core clock
+ * frequency.
+ *
+ * @param[in] coreFreq
+ * Core clock frequency to configure RAM wait-states for
+ *
+ * @param[in] vscale
+ * Voltage Scale level. Supported levels are 0 and 2 where 0 is the default.
+ ******************************************************************************/
+static void setRamWaitState(uint32_t coreFreq, int vscale)
+{
+ uint32_t limit = 38000000;
+ if (vscale == 2) {
+ limit = 16000000;
+ }
+
+ if (coreFreq > limit) {
+ BUS_RegMaskedSet(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN
+ | MSC_RAMCTRL_RAM1WSEN
+ | MSC_RAMCTRL_RAM2WSEN));
+ } else {
+ BUS_RegMaskedClear(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN
+ | MSC_RAMCTRL_RAM1WSEN
+ | MSC_RAMCTRL_RAM2WSEN));
+ }
}
-
+#endif
+
+#if defined(_MSC_CTRL_WAITMODE_MASK)
+/***************************************************************************//**
+ * @brief
+ * Configure wait state for peripheral accesses over the bus to support
+ * given bus clock frequency.
+ *
+ * @param[in] busFreq
+ * peripheral bus clock frequency to configure wait-states for
+ *
+ * @param[in] vscale
+ * The voltage scale to configure wait-states for. Expected values are
+ * 0 or 2.
+ *
+ * @li 0 = 1.2 V (VSCALE2)
+ * @li 2 = 1.0 V (VSCALE0)
+ * ******************************************************************************/
+static void setBusWaitState(uint32_t busFreq, int vscale)
+{
+ if ((busFreq > 50000000) && (vscale == 0)) {
+ BUS_RegMaskedSet(&MSC->CTRL, MSC_CTRL_WAITMODE_WS1);
+ } else {
+ BUS_RegMaskedClear(&MSC->CTRL, MSC_CTRL_WAITMODE_WS1);
+ }
+}
+#endif
+
+/***************************************************************************//**
+ * @brief
+ * Configure various wait states necessary to switch to a certain frequency
+ * and a certain voltage scale.
+ *
+ * @details
+ * This function will setup the necessary flash, bus and RAM wait states.
+ * Updating the wait state configuration must be done before
+ * increasing the clock frequency, and it must be done after decreasing the
+ * clock frequency. Updating the wait state configuration must be done before
+ * core voltage is decreased, and it must be done after a core voltage is
+ * increased.
+ *
+ * @param[in] coreFreq
+ * Core clock frequency to configure wait-states for.
+ *
+ * @param[in] vscale
+ * The voltage scale to configure wait-states for. Expected values are
+ * 0 or 2, higher number is lower voltage.
+ *
+ * @li 0 = 1.2 V (VSCALE2)
+ * @li 2 = 1.0 V (VSCALE0)
+ *
+ ******************************************************************************/
+void CMU_UpdateWaitStates(uint32_t freq, int vscale)
+{
+ flashWaitStateControl(freq, vscale);
+#if defined(_MSC_RAMCTRL_RAMWSEN_MASK)
+ setRamWaitState(freq, vscale);
+#endif
+#if defined(_MSC_CTRL_WAITMODE_MASK)
+ setBusWaitState(freq, vscale);
+#endif
+}
#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)
/***************************************************************************//**
@@ -453,6 +946,40 @@
}
#endif
+#if defined(_CMU_HFXOCTRL_MASK)
+/***************************************************************************//**
+ * @brief
+ * Get the HFXO tuning mode
+ *
+ * @return
+ * The current HFXO tuning mode from the HFXOCTRL register.
+ ******************************************************************************/
+__STATIC_INLINE uint32_t getHfxoTuningMode(void)
+{
+#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
+ return (CMU->HFXOCTRL & _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK);
+#else
+ return (CMU->HFXOCTRL & _CMU_HFXOCTRL_PEAKDETMODE_MASK);
+#endif
+}
+
+/***************************************************************************//**
+ * @brief
+ * Set the HFXO tuning mode
+ *
+ * @param[in] mode
+ * the new HFXO tuning mode, this can be HFXO_TUNING_MODE_AUTO or
+ * HFXO_TUNING_MODE_CMD.
+ ******************************************************************************/
+__STATIC_INLINE void setHfxoTuningMode(uint32_t mode)
+{
+#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
+ CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) | mode;
+#else
+ CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETMODE_MASK) | mode;
+#endif
+}
+#endif
/***************************************************************************//**
* @brief
@@ -470,14 +997,13 @@
uint32_t sel;
uint32_t ret = 0;
- switch (lfClkBranch)
- {
+ switch (lfClkBranch) {
case cmuClock_LFA:
case cmuClock_LFB:
-#if defined( _CMU_LFCCLKEN0_MASK )
+#if defined(_CMU_LFCCLKEN0_MASK)
case cmuClock_LFC:
#endif
-#if defined( _CMU_LFECLKSEL_MASK )
+#if defined(_CMU_LFECLKSEL_MASK)
case cmuClock_LFE:
#endif
break;
@@ -490,12 +1016,11 @@
sel = CMU_ClockSelectGet(lfClkBranch);
/* Get clock select field */
- switch (lfClkBranch)
- {
+ switch (lfClkBranch) {
case cmuClock_LFA:
-#if defined( _CMU_LFCLKSEL_MASK )
+#if defined(_CMU_LFCLKSEL_MASK)
sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) >> _CMU_LFCLKSEL_LFA_SHIFT;
-#elif defined( _CMU_LFACLKSEL_MASK )
+#elif defined(_CMU_LFACLKSEL_MASK)
sel = (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT;
#else
EFM_ASSERT(0);
@@ -503,22 +1028,28 @@
break;
case cmuClock_LFB:
-#if defined( _CMU_LFCLKSEL_MASK )
+#if defined(_CMU_LFCLKSEL_MASK)
sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) >> _CMU_LFCLKSEL_LFB_SHIFT;
-#elif defined( _CMU_LFBCLKSEL_MASK )
+#elif defined(_CMU_LFBCLKSEL_MASK)
sel = (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) >> _CMU_LFBCLKSEL_LFB_SHIFT;
#else
EFM_ASSERT(0);
#endif
break;
-#if defined( _CMU_LFCCLKEN0_MASK )
+#if defined(_CMU_LFCCLKEN0_MASK)
case cmuClock_LFC:
+#if defined(_CMU_LFCLKSEL_LFC_MASK)
sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) >> _CMU_LFCLKSEL_LFC_SHIFT;
- break;
-#endif
-
-#if defined( _CMU_LFECLKSEL_MASK )
+#elif defined(_CMU_LFCCLKSEL_LFC_MASK)
+ sel = (CMU->LFCCLKSEL & _CMU_LFCCLKSEL_LFC_MASK) >> _CMU_LFCCLKSEL_LFC_SHIFT;
+#else
+ EFM_ASSERT(0);
+#endif
+ break;
+#endif
+
+#if defined(_CMU_LFECLKSEL_MASK)
case cmuClock_LFE:
sel = (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT;
break;
@@ -530,9 +1061,8 @@
}
/* Get clock frequency */
-#if defined( _CMU_LFCLKSEL_MASK )
- switch (sel)
- {
+#if defined(_CMU_LFCLKSEL_MASK)
+ switch (sel) {
case _CMU_LFCLKSEL_LFA_LFRCO:
ret = SystemLFRCOClockGet();
break;
@@ -541,9 +1071,11 @@
ret = SystemLFXOClockGet();
break;
-#if defined( _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
+#if defined(_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2)
case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
-#if defined( CMU_MAX_FREQ_HFLE )
+#if defined(CMU_MAX_FREQ_HFLE)
+ /* HFLE bit is or'ed by hardware with HFCORECLKLEDIV to reduce the
+ * frequency of CMU_HFCORECLKLEDIV2. */
ret = SystemCoreClockGet() / (1U << (getHfLeConfig() + 1));
#else
ret = SystemCoreClockGet() / 2U;
@@ -553,14 +1085,12 @@
case _CMU_LFCLKSEL_LFA_DISABLED:
ret = 0;
-#if defined( CMU_LFCLKSEL_LFAE )
+#if defined(CMU_LFCLKSEL_LFAE)
/* Check LF Extended bit setting for LFA or LFB ULFRCO clock */
- if ((lfClkBranch == cmuClock_LFA) || (lfClkBranch == cmuClock_LFB))
- {
+ if ((lfClkBranch == cmuClock_LFA) || (lfClkBranch == cmuClock_LFB)) {
if (CMU->LFCLKSEL >> (lfClkBranch == cmuClock_LFA
? _CMU_LFCLKSEL_LFAE_SHIFT
- : _CMU_LFCLKSEL_LFBE_SHIFT))
- {
+ : _CMU_LFCLKSEL_LFBE_SHIFT)) {
ret = SystemULFRCOClockGet();
}
}
@@ -574,9 +1104,8 @@
}
#endif /* _CMU_LFCLKSEL_MASK */
-#if defined( _CMU_LFACLKSEL_MASK )
- switch (sel)
- {
+#if defined(_CMU_LFACLKSEL_MASK)
+ switch (sel) {
case _CMU_LFACLKSEL_LFA_LFRCO:
ret = SystemLFRCOClockGet();
break;
@@ -589,25 +1118,23 @@
ret = SystemULFRCOClockGet();
break;
-#if defined( CMU_LFACLKSEL_LFA_PLFRCO )
+#if defined(CMU_LFACLKSEL_LFA_PLFRCO)
case _CMU_LFACLKSEL_LFA_PLFRCO:
ret = SystemLFRCOClockGet();
break;
#endif
-#if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
+#if defined(_CMU_LFACLKSEL_LFA_HFCLKLE)
case _CMU_LFACLKSEL_LFA_HFCLKLE:
- ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
- == CMU_HFPRESC_HFCLKLEPRESC_DIV4)
- ? SystemCoreClockGet() / 4U
- : SystemCoreClockGet() / 2U;
- break;
-#elif defined( _CMU_LFBCLKSEL_LFB_HFCLKLE )
+ ret = SystemCoreClockGet()
+ / CMU_Log2ToDiv(((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
+ >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT) + 1);
+ break;
+#elif defined(_CMU_LFBCLKSEL_LFB_HFCLKLE)
case _CMU_LFBCLKSEL_LFB_HFCLKLE:
- ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
- == CMU_HFPRESC_HFCLKLEPRESC_DIV4)
- ? SystemCoreClockGet() / 4U
- : SystemCoreClockGet() / 2U;
+ ret = SystemCoreClockGet()
+ / CMU_Log2ToDiv(((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
+ >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT) + 1);
break;
#endif
@@ -620,7 +1147,6 @@
return ret;
}
-
/***************************************************************************//**
* @brief
* Wait for ongoing sync of register(s) to low frequency domain to complete.
@@ -633,18 +1159,17 @@
{
/* Avoid deadlock if modifying the same register twice when freeze mode is */
/* activated. */
- if (CMU->FREEZE & CMU_FREEZE_REGFREEZE)
+ if (CMU->FREEZE & CMU_FREEZE_REGFREEZE) {
return;
+ }
/* Wait for any pending previous write operation to have been completed */
/* in low frequency domain */
- while (CMU->SYNCBUSY & mask)
- {
+ while (CMU->SYNCBUSY & mask) {
}
}
-
-#if defined(USB_PRESENT)
+#if defined(USBC_CLOCK_PRESENT)
/***************************************************************************//**
* @brief
* Get the USBC frequency
@@ -660,14 +1185,18 @@
/* Get selected clock source */
clk = CMU_ClockSelectGet(cmuClock_USBC);
- switch(clk)
- {
+ switch (clk) {
case cmuSelect_LFXO:
ret = SystemLFXOClockGet();
break;
case cmuSelect_LFRCO:
ret = SystemLFRCOClockGet();
break;
+#if defined (_CMU_USHFRCOCTRL_MASK)
+ case cmuSelect_USHFRCO:
+ ret = ushfrcoFreq;
+ break;
+#endif
case cmuSelect_HFCLK:
ret = SystemHFClockGet();
break;
@@ -680,14 +1209,13 @@
}
#endif
-
/** @endcond */
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
-#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
+#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK)
/***************************************************************************//**
* @brief
* Get AUXHFRCO band in use.
@@ -703,8 +1231,7 @@
}
#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */
-
-#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
+#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK)
/***************************************************************************//**
* @brief
* Set AUXHFRCO band and the tuning value based on the value in the
@@ -718,8 +1245,7 @@
uint32_t tuning;
/* Read tuning value from calibration table */
- switch (band)
- {
+ switch (band) {
case cmuAUXHFRCOBand_1MHz:
tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK)
>> _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT;
@@ -745,7 +1271,7 @@
>> _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT;
break;
-#if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
+#if defined(_CMU_AUXHFRCOCTRL_BAND_28MHZ)
case cmuAUXHFRCOBand_28MHz:
tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK)
>> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT;
@@ -758,20 +1284,18 @@
}
/* Set band/tuning */
- CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL &
- ~(_CMU_AUXHFRCOCTRL_BAND_MASK
- | _CMU_AUXHFRCOCTRL_TUNING_MASK))
+ CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL
+ & ~(_CMU_AUXHFRCOCTRL_BAND_MASK
+ | _CMU_AUXHFRCOCTRL_TUNING_MASK))
| (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT)
| (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
-
}
#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */
-
-#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
+#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
/**************************************************************************//**
* @brief
- * Get a pointer to the AUXHFRCO frequency calibration word in DEVINFO
+ * Get the AUXHFRCO frequency calibration word in DEVINFO
*
* @param[in] freq
* Frequency in Hz
@@ -781,9 +1305,8 @@
*****************************************************************************/
static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq)
{
- switch (freq)
- {
- /* 1, 2 and 4MHz share the same calibration word */
+ switch (freq) {
+ /* 1, 2 and 4MHz share the same calibration word */
case cmuAUXHFRCOFreq_1M0Hz:
case cmuAUXHFRCOFreq_2M0Hz:
case cmuAUXHFRCOFreq_4M0Hz:
@@ -810,14 +1333,21 @@
case cmuAUXHFRCOFreq_38M0Hz:
return DEVINFO->AUXHFRCOCAL12;
+#if defined(DEVINFO_AUXHFRCOCAL14)
+ case cmuAUXHFRCOFreq_48M0Hz:
+ return DEVINFO->AUXHFRCOCAL13;
+
+ case cmuAUXHFRCOFreq_50M0Hz:
+ return DEVINFO->AUXHFRCOCAL14;
+#endif
+
default: /* cmuAUXHFRCOFreq_UserDefined */
return 0;
}
}
#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
-
-#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
+#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
/***************************************************************************//**
* @brief
* Get current AUXHFRCO frequency.
@@ -831,8 +1361,7 @@
}
#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
-
-#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
+#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK)
/***************************************************************************//**
* @brief
* Set AUXHFRCO calibration for the selected target frequency.
@@ -851,11 +1380,10 @@
/* Wait for any previous sync to complete, and then set calibration data
for the selected frequency. */
- while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT));
+ while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT)) ;
/* Set divider in AUXHFRCOCTRL for 1, 2 and 4MHz */
- switch(setFreq)
- {
+ switch (setFreq) {
case cmuAUXHFRCOFreq_1M0Hz:
freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
| CMU_AUXHFRCOCTRL_CLKDIV_DIV4;
@@ -878,7 +1406,6 @@
}
#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
-
/***************************************************************************//**
* @brief
* Calibrate clock.
@@ -906,8 +1433,7 @@
EFM_ASSERT(HFCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT));
/* Set reference clock source */
- switch (ref)
- {
+ switch (ref) {
case cmuOsc_LFXO:
CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO;
break;
@@ -928,6 +1454,12 @@
CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO;
break;
+#if defined (_CMU_USHFRCOCTRL_MASK)
+ case cmuOsc_USHFRCO:
+ CMU->CALCTRL = CMU_CALCTRL_UPSEL_USHFRCO;
+ break;
+#endif
+
default:
EFM_ASSERT(0);
return 0;
@@ -939,23 +1471,20 @@
/* Start calibration */
CMU->CMD = CMU_CMD_CALSTART;
-#if defined( CMU_STATUS_CALRDY )
+#if defined(CMU_STATUS_CALRDY)
/* Wait until calibration completes */
- while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT))
- {
+ while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT)) {
}
#else
/* Wait until calibration completes */
- while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
- {
+ while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT)) {
}
#endif
return CMU->CALCNT;
}
-
-#if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
+#if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK)
/***************************************************************************//**
* @brief
* Configure clock calibration
@@ -966,9 +1495,9 @@
* Refer to the reference manual, CMU chapter, for further details.
*
* @note
- * After configuration, a call to CMU_CalibrateStart() is required, and
+ * After configuration, a call to @ref CMU_CalibrateStart() is required, and
* the resulting calibration value can be read out with the
- * CMU_CalibrateCountGet() function call.
+ * @ref CMU_CalibrateCountGet() function call.
*
* @param[in] downCycles
* The number of downSel clock cycles to run calibration. Increasing this
@@ -980,7 +1509,7 @@
* @param[in] upSel
* The reference clock, the number of cycles generated by this clock will
* be counted and added up, the result can be given with the
- * CMU_CalibrateCountGet() function call.
+ * @ref CMU_CalibrateCountGet() function call.
******************************************************************************/
void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
CMU_Osc_TypeDef upSel)
@@ -993,8 +1522,7 @@
EFM_ASSERT(downCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT));
/* Set down counting clock source - down counter */
- switch (downSel)
- {
+ switch (downSel) {
case cmuOsc_LFXO:
calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO;
break;
@@ -1015,6 +1543,12 @@
calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO;
break;
+#if defined (_CMU_USHFRCOCTRL_MASK)
+ case cmuOsc_USHFRCO:
+ calCtrl |= CMU_CALCTRL_DOWNSEL_USHFRCO;
+ break;
+#endif
+
default:
EFM_ASSERT(0);
break;
@@ -1024,8 +1558,7 @@
CMU->CALCNT = downCycles;
/* Set reference clock source - up counter */
- switch (upSel)
- {
+ switch (upSel) {
case cmuOsc_LFXO:
calCtrl |= CMU_CALCTRL_UPSEL_LFXO;
break;
@@ -1046,6 +1579,12 @@
calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO;
break;
+#if defined (_CMU_USHFRCOCTRL_MASK)
+ case cmuOsc_USHFRCO:
+ calCtrl |= CMU_CALCTRL_UPSEL_USHFRCO;
+ break;
+#endif
+
default:
EFM_ASSERT(0);
break;
@@ -1055,7 +1594,6 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Get calibration count register
@@ -1065,7 +1603,7 @@
* would be that this function call has been triggered by the CALRDY
* interrupt flag.
* @return
- * Calibration count, the number of UPSEL clocks (see CMU_CalibrateConfig)
+ * Calibration count, the number of UPSEL clocks (see @ref CMU_CalibrateConfig())
* in the period of DOWNSEL oscillator clock cycles configured by a previous
* write operation to CMU->CALCNT
******************************************************************************/
@@ -1073,30 +1611,25 @@
{
/* Wait until calibration completes, UNLESS continuous calibration mode is */
/* active */
-#if defined( CMU_CALCTRL_CONT )
- if (!BUS_RegBitRead(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT))
- {
-#if defined( CMU_STATUS_CALRDY )
+#if defined(CMU_CALCTRL_CONT)
+ if (!BUS_RegBitRead(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT)) {
+#if defined(CMU_STATUS_CALRDY)
/* Wait until calibration completes */
- while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT))
- {
+ while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT)) {
}
#else
/* Wait until calibration completes */
- while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
- {
+ while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT)) {
}
#endif
}
#else
- while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
- {
+ while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT)) {
}
#endif
return CMU->CALCNT;
}
-
/***************************************************************************//**
* @brief
* Get clock divisor/prescaler.
@@ -1111,19 +1644,18 @@
******************************************************************************/
CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)
{
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
return 1 + (uint32_t)CMU_ClockPrescGet(clock);
-#elif defined( _SILICON_LABS_32B_SERIES_0 )
+#elif defined(_SILICON_LABS_32B_SERIES_0)
uint32_t divReg;
CMU_ClkDiv_TypeDef ret;
/* Get divisor reg id */
divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
- switch (divReg)
- {
-#if defined( _CMU_CTRL_HFCLKDIV_MASK )
+ switch (divReg) {
+#if defined(_CMU_CTRL_HFCLKDIV_MASK)
case CMU_HFCLKDIV_REG:
ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
>> _CMU_CTRL_HFCLKDIV_SHIFT);
@@ -1145,8 +1677,7 @@
break;
case CMU_LFAPRESC0_REG:
- switch (clock)
- {
+ switch (clock) {
case cmuClock_RTC:
ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)
>> _CMU_LFAPRESC0_RTC_SHIFT);
@@ -1186,8 +1717,7 @@
break;
case CMU_LFBPRESC0_REG:
- switch (clock)
- {
+ switch (clock) {
#if defined(_CMU_LFBPRESC0_LEUART0_MASK)
case cmuClock_LEUART0:
ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
@@ -1221,7 +1751,6 @@
#endif
}
-
/***************************************************************************//**
* @brief
* Set clock divisor/prescaler.
@@ -1230,7 +1759,7 @@
* If setting a LF clock prescaler, synchronization into the low frequency
* domain is required. If the same register is modified before a previous
* update has completed, this function will stall until the previous
- * synchronization has completed. Please refer to CMU_FreezeEnable() for
+ * synchronization has completed. Please refer to @ref CMU_FreezeEnable() for
* a suggestion on how to reduce stalling time in some use cases.
*
* @param[in] clock
@@ -1243,35 +1772,34 @@
******************************************************************************/
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
{
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1));
-#elif defined( _SILICON_LABS_32B_SERIES_0 )
+#elif defined(_SILICON_LABS_32B_SERIES_0)
uint32_t freq;
uint32_t divReg;
/* Get divisor reg id */
divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
- switch (divReg)
- {
-#if defined( _CMU_CTRL_HFCLKDIV_MASK )
+ switch (divReg) {
+#if defined(_CMU_CTRL_HFCLKDIV_MASK)
case CMU_HFCLKDIV_REG:
- EFM_ASSERT((div>=cmuClkDiv_1) && (div<=cmuClkDiv_8));
+ EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_8));
/* Configure worst case wait states for flash access before setting divisor */
flashWaitStateMax();
/* Set divider */
CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK)
- | ((div-1) << _CMU_CTRL_HFCLKDIV_SHIFT);
+ | ((div - 1) << _CMU_CTRL_HFCLKDIV_SHIFT);
/* Update CMSIS core clock variable */
/* (The function will update the global variable) */
freq = SystemCoreClockGet();
/* Optimize flash access wait state setting for current core clk */
- flashWaitStateControl(freq);
+ CMU_UpdateWaitStates(freq, VSCALE_DEFAULT);
break;
#endif
@@ -1289,8 +1817,8 @@
/* Configure worst case wait states for flash access before setting divisor */
flashWaitStateMax();
-#if defined( CMU_MAX_FREQ_HFLE )
- setHfLeConfig(SystemHFClockGet() / div, CMU_MAX_FREQ_HFLE);
+#if defined(CMU_MAX_FREQ_HFLE)
+ setHfLeConfig(SystemHFClockGet() / div);
#endif
/* Convert to correct scale */
@@ -1304,13 +1832,12 @@
/* (The function will update the global variable) */
freq = SystemCoreClockGet();
- /* Optimize flash access wait state setting for current core clk */
- flashWaitStateControl(freq);
+ /* Optimize wait state setting for current core clk */
+ CMU_UpdateWaitStates(freq, VSCALE_DEFAULT);
break;
case CMU_LFAPRESC0_REG:
- switch (clock)
- {
+ switch (clock) {
case cmuClock_RTC:
EFM_ASSERT(div <= cmuClkDiv_32768);
@@ -1377,8 +1904,7 @@
break;
case CMU_LFBPRESC0_REG:
- switch (clock)
- {
+ switch (clock) {
#if defined(_CMU_LFBPRESC0_LEUART0_MASK)
case cmuClock_LEUART0:
EFM_ASSERT(div <= cmuClkDiv_8);
@@ -1422,7 +1948,6 @@
#endif
}
-
/***************************************************************************//**
* @brief
* Enable/disable a clock.
@@ -1438,7 +1963,7 @@
* If enabling/disabling a LF clock, synchronization into the low frequency
* domain is required. If the same register is modified before a previous
* update has completed, this function will stall until the previous
- * synchronization has completed. Please refer to CMU_FreezeEnable() for
+ * synchronization has completed. Please refer to @ref CMU_FreezeEnable() for
* a suggestion on how to reduce stalling time in some use cases.
*
* @param[in] clock
@@ -1457,30 +1982,29 @@
uint32_t sync = 0;
/* Identify enable register */
- switch ((clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK)
- {
-#if defined( _CMU_CTRL_HFPERCLKEN_MASK )
+ switch ((clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK) {
+#if defined(_CMU_CTRL_HFPERCLKEN_MASK)
case CMU_CTRL_EN_REG:
reg = &CMU->CTRL;
break;
#endif
-#if defined( _CMU_HFCORECLKEN0_MASK )
+#if defined(_CMU_HFCORECLKEN0_MASK)
case CMU_HFCORECLKEN0_EN_REG:
reg = &CMU->HFCORECLKEN0;
-#if defined( CMU_MAX_FREQ_HFLE )
- setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE);
-#endif
- break;
-#endif
-
-#if defined( _CMU_HFBUSCLKEN0_MASK )
+#if defined(CMU_MAX_FREQ_HFLE)
+ setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE));
+#endif
+ break;
+#endif
+
+#if defined(_CMU_HFBUSCLKEN0_MASK)
case CMU_HFBUSCLKEN0_EN_REG:
reg = &CMU->HFBUSCLKEN0;
break;
#endif
-#if defined( _CMU_HFPERCLKDIV_MASK )
+#if defined(_CMU_HFPERCLKDIV_MASK)
case CMU_HFPERCLKDIV_EN_REG:
reg = &CMU->HFPERCLKDIV;
break;
@@ -1490,6 +2014,12 @@
reg = &CMU->HFPERCLKEN0;
break;
+#if defined(_CMU_HFPERCLKEN1_MASK)
+ case CMU_HFPERCLKEN1_EN_REG:
+ reg = &CMU->HFPERCLKEN1;
+ break;
+#endif
+
case CMU_LFACLKEN0_EN_REG:
reg = &CMU->LFACLKEN0;
sync = CMU_SYNCBUSY_LFACLKEN0;
@@ -1500,20 +2030,39 @@
sync = CMU_SYNCBUSY_LFBCLKEN0;
break;
-#if defined( _CMU_LFCCLKEN0_MASK )
+#if defined(_CMU_LFCCLKEN0_MASK)
case CMU_LFCCLKEN0_EN_REG:
reg = &CMU->LFCCLKEN0;
sync = CMU_SYNCBUSY_LFCCLKEN0;
break;
#endif
-#if defined( _CMU_LFECLKEN0_MASK )
+#if defined(_CMU_LFECLKEN0_MASK)
case CMU_LFECLKEN0_EN_REG:
reg = &CMU->LFECLKEN0;
sync = CMU_SYNCBUSY_LFECLKEN0;
break;
#endif
+#if defined(_CMU_SDIOCTRL_MASK)
+ case CMU_SDIOREF_EN_REG:
+ reg = &CMU->SDIOCTRL;
+ enable = !enable;
+ break;
+#endif
+
+#if defined(_CMU_QSPICTRL_MASK)
+ case CMU_QSPI0REF_EN_REG:
+ reg = &CMU->QSPICTRL;
+ enable = !enable;
+ break;
+#endif
+#if defined(_CMU_USBCTRL_MASK)
+ case CMU_USBRCLK_EN_REG:
+ reg = &CMU->USBCTRL;
+ break;
+#endif
+
case CMU_PCNT_EN_REG:
reg = &CMU->PCNTCTRL;
break;
@@ -1527,8 +2076,7 @@
bit = (clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK;
/* LF synchronization required? */
- if (sync)
- {
+ if (sync) {
syncReg(sync);
}
@@ -1536,7 +2084,6 @@
BUS_RegBitWrite(reg, bit, enable);
}
-
/***************************************************************************//**
* @brief
* Get clock frequency for a clock point.
@@ -1551,31 +2098,30 @@
{
uint32_t ret;
- switch(clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS))
- {
+ switch (clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS)) {
case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS):
ret = SystemHFClockGet();
break;
case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS):
ret = SystemHFClockGet();
- /* Calculate frequency after HFPER divider. */
-#if defined( _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK )
+ /* Calculate frequency after HFPER divider. */
+#if defined(_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
>> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT;
#endif
-#if defined( _CMU_HFPERPRESC_PRESC_MASK )
+#if defined(_CMU_HFPERPRESC_PRESC_MASK)
ret /= 1U + ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)
>> _CMU_HFPERPRESC_PRESC_SHIFT);
#endif
break;
-#if defined( _SILICON_LABS_32B_SERIES_1 )
-#if defined( CRYPTO_PRESENT ) \
- || defined( LDMA_PRESENT ) \
- || defined( GPCRC_PRESENT ) \
- || defined( PRS_PRESENT ) \
- || defined( GPIO_PRESENT )
+#if defined(_SILICON_LABS_32B_SERIES_1)
+#if defined(CRYPTO_PRESENT) \
+ || defined(LDMA_PRESENT) \
+ || defined(GPCRC_PRESENT) \
+ || defined(PRS_PRESENT) \
+ || defined(GPIO_PRESENT)
case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS):
ret = SystemHFClockGet();
break;
@@ -1594,11 +2140,11 @@
break;
#endif
-#if defined( _SILICON_LABS_32B_SERIES_0 )
-#if defined( AES_PRESENT ) \
- || defined( DMA_PRESENT ) \
- || defined( EBI_PRESENT ) \
- || defined( USB_PRESENT )
+#if defined(_SILICON_LABS_32B_SERIES_0)
+#if defined(AES_PRESENT) \
+ || defined(DMA_PRESENT) \
+ || defined(EBI_PRESENT) \
+ || defined(USB_PRESENT)
case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
{
ret = SystemCoreClockGet();
@@ -1610,7 +2156,7 @@
ret = lfClkGet(cmuClock_LFA);
break;
-#if defined( _CMU_LFACLKEN0_RTC_MASK )
+#if defined(_CMU_LFACLKEN0_RTC_MASK)
case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
ret = lfClkGet(cmuClock_LFA);
ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)
@@ -1618,33 +2164,39 @@
break;
#endif
-#if defined( _CMU_LFECLKEN0_RTCC_MASK )
+#if defined(_CMU_LFECLKEN0_RTCC_MASK)
case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
ret = lfClkGet(cmuClock_LFE);
break;
#endif
-#if defined( _CMU_LFACLKEN0_LETIMER0_MASK )
+#if defined(_CMU_LFACLKEN0_LETIMER0_MASK)
case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
ret = lfClkGet(cmuClock_LFA);
-#if defined( _SILICON_LABS_32B_SERIES_0 )
+#if defined(_SILICON_LABS_32B_SERIES_0)
ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
>> _CMU_LFAPRESC0_LETIMER0_SHIFT;
-#elif defined( _SILICON_LABS_32B_SERIES_1 )
+#else
ret /= CMU_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
>> _CMU_LFAPRESC0_LETIMER0_SHIFT);
#endif
break;
#endif
-#if defined( _CMU_LFACLKEN0_LCD_MASK )
+#if defined(_CMU_LFACLKEN0_LCD_MASK)
case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
ret = lfClkGet(cmuClock_LFA);
+#if defined(_SILICON_LABS_32B_SERIES_0)
ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
>> _CMU_LFAPRESC0_LCD_SHIFT)
+ CMU_DivToLog2(cmuClkDiv_16);
- break;
-
+#else
+ ret /= CMU_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
+ >> _CMU_LFAPRESC0_LCD_SHIFT);
+#endif
+ break;
+
+#if defined(_CMU_LCDCTRL_MASK)
case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS):
ret = lfClkGet(cmuClock_LFA);
ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
@@ -1653,8 +2205,9 @@
>> _CMU_LCDCTRL_FDIV_SHIFT);
break;
#endif
-
-#if defined( _CMU_LFACLKEN0_LESENSE_MASK )
+#endif
+
+#if defined(_CMU_LFACLKEN0_LESENSE_MASK)
case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
ret = lfClkGet(cmuClock_LFA);
ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
@@ -1666,33 +2219,33 @@
ret = lfClkGet(cmuClock_LFB);
break;
-#if defined( _CMU_LFBCLKEN0_LEUART0_MASK )
+#if defined(_CMU_LFBCLKEN0_LEUART0_MASK)
case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
ret = lfClkGet(cmuClock_LFB);
-#if defined( _SILICON_LABS_32B_SERIES_0 )
+#if defined(_SILICON_LABS_32B_SERIES_0)
ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
>> _CMU_LFBPRESC0_LEUART0_SHIFT;
-#elif defined( _SILICON_LABS_32B_SERIES_1 )
+#else
ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
>> _CMU_LFBPRESC0_LEUART0_SHIFT);
#endif
break;
#endif
-#if defined( _CMU_LFBCLKEN0_LEUART1_MASK )
+#if defined(_CMU_LFBCLKEN0_LEUART1_MASK)
case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS):
ret = lfClkGet(cmuClock_LFB);
-#if defined( _SILICON_LABS_32B_SERIES_0 )
+#if defined(_SILICON_LABS_32B_SERIES_0)
ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
>> _CMU_LFBPRESC0_LEUART1_SHIFT;
-#elif defined( _SILICON_LABS_32B_SERIES_1 )
+#else
ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
>> _CMU_LFBPRESC0_LEUART1_SHIFT);
#endif
break;
#endif
-#if defined( _CMU_LFBCLKEN0_CSEN_MASK )
+#if defined(_CMU_LFBCLKEN0_CSEN_MASK)
case (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS):
ret = lfClkGet(cmuClock_LFB);
ret /= CMU_Log2ToDiv(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK)
@@ -1700,7 +2253,7 @@
break;
#endif
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
ret = lfClkGet(cmuClock_LFE);
break;
@@ -1714,12 +2267,50 @@
ret = auxClkGet();
break;
-#if defined(USB_PRESENT)
+#if defined(USBC_CLOCK_PRESENT)
case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
ret = usbCClkGet();
break;
#endif
+#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK)
+ case (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
+ ret = adcAsyncClkGet(0);
+#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK)
+ ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK)
+ >> _CMU_ADCCTRL_ADC0CLKDIV_SHIFT);
+#endif
+ break;
+#endif
+
+#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK)
+ case (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
+ ret = adcAsyncClkGet(1);
+#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK)
+ ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK)
+ >> _CMU_ADCCTRL_ADC1CLKDIV_SHIFT);
+#endif
+ break;
+#endif
+
+#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK)
+ case (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS):
+ ret = sdioRefClkGet();
+ break;
+#endif
+
+#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK)
+ case (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS):
+ ret = qspiRefClkGet(0);
+ break;
+#endif
+
+#if defined(USBR_CLOCK_PRESENT)
+ case (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS):
+ ret = usbRateClkGet();
+ break;
+#endif
+
default:
EFM_ASSERT(0);
ret = 0;
@@ -1729,8 +2320,7 @@
return ret;
}
-
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
/***************************************************************************//**
* @brief
* Get clock prescaler.
@@ -1751,50 +2341,73 @@
/* Get prescaler register id. */
prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
- switch (prescReg)
- {
+ switch (prescReg) {
case CMU_HFPRESC_REG:
- ret = ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
- >> _CMU_HFPRESC_PRESC_SHIFT);
+ ret = (CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
+ >> _CMU_HFPRESC_PRESC_SHIFT;
break;
case CMU_HFEXPPRESC_REG:
- ret = ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)
- >> _CMU_HFEXPPRESC_PRESC_SHIFT);
+ ret = (CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)
+ >> _CMU_HFEXPPRESC_PRESC_SHIFT;
break;
case CMU_HFCLKLEPRESC_REG:
- ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
- >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
+ ret = (CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
+ >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT;
break;
case CMU_HFPERPRESC_REG:
- ret = ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)
- >> _CMU_HFPERPRESC_PRESC_SHIFT);
+ ret = (CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)
+ >> _CMU_HFPERPRESC_PRESC_SHIFT;
break;
case CMU_HFCOREPRESC_REG:
- ret = ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
- >> _CMU_HFCOREPRESC_PRESC_SHIFT);
+ ret = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
+ >> _CMU_HFCOREPRESC_PRESC_SHIFT;
break;
case CMU_LFAPRESC0_REG:
- switch (clock)
- {
-#if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
+ switch (clock) {
+#if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
case cmuClock_LETIMER0:
- ret = (((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
- >> _CMU_LFAPRESC0_LETIMER0_SHIFT));
+ ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
+ >> _CMU_LFAPRESC0_LETIMER0_SHIFT;
+ /* Convert the exponent to prescaler value. */
+ ret = CMU_Log2ToDiv(ret) - 1U;
+ break;
+#endif
+
+#if defined(_CMU_LFAPRESC0_LESENSE_MASK)
+ case cmuClock_LESENSE:
+ ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
+ >> _CMU_LFAPRESC0_LESENSE_SHIFT;
/* Convert the exponent to prescaler value. */
ret = CMU_Log2ToDiv(ret) - 1U;
break;
#endif
-#if defined( _CMU_LFAPRESC0_LESENSE_MASK )
- case cmuClock_LESENSE:
- ret = (((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
- >> _CMU_LFAPRESC0_LESENSE_SHIFT));
- /* Convert the exponent to prescaler value. */
+#if defined(_CMU_LFAPRESC0_LETIMER1_MASK)
+ case cmuClock_LETIMER1:
+ ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK)
+ >> _CMU_LFAPRESC0_LETIMER1_SHIFT;
+ ret = CMU_Log2ToDiv(ret) - 1U;
+ break;
+#endif
+
+#if defined(_CMU_LFAPRESC0_LCD_MASK)
+ case cmuClock_LCD:
+ case cmuClock_LCDpre:
+ ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
+ >> _CMU_LFAPRESC0_LCD_SHIFT;
+ ret = CMU_Log2ToDiv(ret) - 1U;
+ break;
+#endif
+
+#if defined(_CMU_LFAPRESC0_RTC_MASK)
+ case cmuClock_RTC:
+ ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)
+ >> _CMU_LFAPRESC0_RTC_SHIFT;
ret = CMU_Log2ToDiv(ret) - 1U;
break;
#endif
@@ -1807,30 +2420,29 @@
break;
case CMU_LFBPRESC0_REG:
- switch (clock)
- {
-#if defined( _CMU_LFBPRESC0_LEUART0_MASK )
+ switch (clock) {
+#if defined(_CMU_LFBPRESC0_LEUART0_MASK)
case cmuClock_LEUART0:
- ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
- >> _CMU_LFBPRESC0_LEUART0_SHIFT));
+ ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
+ >> _CMU_LFBPRESC0_LEUART0_SHIFT;
/* Convert the exponent to prescaler value. */
ret = CMU_Log2ToDiv(ret) - 1U;
break;
#endif
-#if defined( _CMU_LFBPRESC0_LEUART1_MASK )
+#if defined(_CMU_LFBPRESC0_LEUART1_MASK)
case cmuClock_LEUART1:
- ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
- >> _CMU_LFBPRESC0_LEUART1_SHIFT));
+ ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
+ >> _CMU_LFBPRESC0_LEUART1_SHIFT;
/* Convert the exponent to prescaler value. */
ret = CMU_Log2ToDiv(ret) - 1U;
break;
#endif
-#if defined( _CMU_LFBPRESC0_CSEN_MASK )
+#if defined(_CMU_LFBPRESC0_CSEN_MASK)
case cmuClock_CSEN_LF:
- ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK)
- >> _CMU_LFBPRESC0_CSEN_SHIFT));
+ ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK)
+ >> _CMU_LFBPRESC0_CSEN_SHIFT;
/* Convert the exponent to prescaler value. */
ret = CMU_Log2ToDiv(ret + 4) - 1U;
break;
@@ -1844,9 +2456,8 @@
break;
case CMU_LFEPRESC0_REG:
- switch (clock)
- {
-#if defined( RTCC_PRESENT )
+ switch (clock) {
+#if defined(RTCC_PRESENT)
case cmuClock_RTCC:
/* No need to compute with LFEPRESC0_RTCC - DIV1 is the only */
/* allowed value. Convert the exponent to prescaler value. */
@@ -1861,6 +2472,27 @@
}
break;
+ case CMU_ADCASYNCDIV_REG:
+ switch (clock) {
+#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK)
+ case cmuClock_ADC0ASYNC:
+ ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK)
+ >> _CMU_ADCCTRL_ADC0CLKDIV_SHIFT;
+ break;
+#endif
+#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK)
+ case cmuClock_ADC1ASYNC:
+ ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK)
+ >> _CMU_ADCCTRL_ADC1CLKDIV_SHIFT;
+ break;
+#endif
+ default:
+ EFM_ASSERT(0);
+ ret = 0U;
+ break;
+ }
+ break;
+
default:
EFM_ASSERT(0);
ret = 0U;
@@ -1871,8 +2503,7 @@
}
#endif
-
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
/***************************************************************************//**
* @brief
* Set clock prescaler.
@@ -1881,7 +2512,7 @@
* If setting a LF clock prescaler, synchronization into the low frequency
* domain is required. If the same register is modified before a previous
* update has completed, this function will stall until the previous
- * synchronization has completed. Please refer to CMU_FreezeEnable() for
+ * synchronization has completed. Please refer to @ref CMU_FreezeEnable() for
* a suggestion on how to reduce stalling time in some use cases.
*
* @param[in] clock
@@ -1899,14 +2530,13 @@
/* Get divisor reg id */
prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
- switch (prescReg)
- {
+ switch (prescReg) {
case CMU_HFPRESC_REG:
EFM_ASSERT(presc < 32U);
/* Configure worst case wait-states for flash and HFLE. */
flashWaitStateMax();
- setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
+ setHfLeConfig(CMU_MAX_FREQ_HFLE + 1);
CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK)
| (presc << _CMU_HFPRESC_PRESC_SHIFT);
@@ -1914,8 +2544,9 @@
/* Update CMSIS core clock variable (this function updates the global variable).
Optimize flash and HFLE wait states. */
freq = SystemCoreClockGet();
- flashWaitStateControl(freq);
- setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE) ,CMU_MAX_FREQ_HFLE);
+ CMU_UpdateWaitStates(freq, VSCALE_DEFAULT);
+
+ setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE));
break;
case CMU_HFEXPPRESC_REG:
@@ -1926,10 +2557,15 @@
break;
case CMU_HFCLKLEPRESC_REG:
+#if defined (CMU_HFPRESC_HFCLKLEPRESC_DIV8)
+ EFM_ASSERT(presc < 3U);
+#else
EFM_ASSERT(presc < 2U);
-
- /* Specifies the clock divider for HFCLKLE. When running at frequencies
- * higher than 32 MHz, this must be set to DIV4. */
+#endif
+
+ /* Specifies the clock divider for HFCLKLE. This clock divider must be set
+ * high enough for the divided clock frequency to be at or below the max
+ * frequency allowed for the HFCLKLE clock. */
CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK)
| (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
break;
@@ -1946,7 +2582,7 @@
/* Configure worst case wait-states for flash and HFLE. */
flashWaitStateMax();
- setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
+ setHfLeConfig(CMU_MAX_FREQ_HFLE + 1);
CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK)
| (presc << _CMU_HFCOREPRESC_PRESC_SHIFT);
@@ -1954,14 +2590,13 @@
/* Update CMSIS core clock variable (this function updates the global variable).
Optimize flash and HFLE wait states. */
freq = SystemCoreClockGet();
- flashWaitStateControl(freq);
- setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE) ,CMU_MAX_FREQ_HFLE);
+ CMU_UpdateWaitStates(freq, VSCALE_DEFAULT);
+ setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE));
break;
case CMU_LFAPRESC0_REG:
- switch (clock)
- {
-#if defined( RTC_PRESENT )
+ switch (clock) {
+#if defined(RTC_PRESENT)
case cmuClock_RTC:
EFM_ASSERT(presc <= 32768U);
@@ -1976,9 +2611,9 @@
break;
#endif
-#if defined( RTCC_PRESENT )
+#if defined(RTCC_PRESENT)
case cmuClock_RTCC:
-#if defined( _CMU_LFEPRESC0_RTCC_MASK )
+#if defined(_CMU_LFEPRESC0_RTCC_MASK)
/* DIV1 is the only accepted value. */
EFM_ASSERT(presc <= 0U);
@@ -2002,7 +2637,7 @@
break;
#endif
-#if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
+#if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
case cmuClock_LETIMER0:
EFM_ASSERT(presc <= 32768U);
@@ -2017,7 +2652,7 @@
break;
#endif
-#if defined( _CMU_LFAPRESC0_LESENSE_MASK )
+#if defined(_CMU_LFAPRESC0_LESENSE_MASK)
case cmuClock_LESENSE:
EFM_ASSERT(presc <= 8);
@@ -2032,6 +2667,23 @@
break;
#endif
+#if defined(_CMU_LFAPRESC0_LCD_MASK)
+ case cmuClock_LCDpre:
+ case cmuClock_LCD:
+ {
+ EFM_ASSERT(presc <= 32768U);
+
+ /* Convert prescaler value to DIV exponent scale. */
+ presc = CMU_PrescToLog2(presc);
+
+ /* LF register about to be modified require sync. Busy check. */
+ syncReg(CMU_SYNCBUSY_LFAPRESC0);
+
+ CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK)
+ | (presc << _CMU_LFAPRESC0_LCD_SHIFT);
+ } break;
+#endif
+
default:
EFM_ASSERT(0);
break;
@@ -2039,9 +2691,8 @@
break;
case CMU_LFBPRESC0_REG:
- switch (clock)
- {
-#if defined( _CMU_LFBPRESC0_LEUART0_MASK )
+ switch (clock) {
+#if defined(_CMU_LFBPRESC0_LEUART0_MASK)
case cmuClock_LEUART0:
EFM_ASSERT(presc <= 8U);
@@ -2056,7 +2707,7 @@
break;
#endif
-#if defined( _CMU_LFBPRESC0_LEUART1_MASK )
+#if defined(_CMU_LFBPRESC0_LEUART1_MASK)
case cmuClock_LEUART1:
EFM_ASSERT(presc <= 8U);
@@ -2071,7 +2722,7 @@
break;
#endif
-#if defined( _CMU_LFBPRESC0_CSEN_MASK )
+#if defined(_CMU_LFBPRESC0_CSEN_MASK)
case cmuClock_CSEN_LF:
EFM_ASSERT((presc <= 127U) && (presc >= 15U));
@@ -2094,9 +2745,8 @@
break;
case CMU_LFEPRESC0_REG:
- switch (clock)
- {
-#if defined( _CMU_LFEPRESC0_RTCC_MASK )
+ switch (clock) {
+#if defined(_CMU_LFEPRESC0_RTCC_MASK)
case cmuClock_RTCC:
EFM_ASSERT(presc <= 0U);
@@ -2114,6 +2764,29 @@
}
break;
+ case CMU_ADCASYNCDIV_REG:
+ switch (clock) {
+#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK)
+ case cmuClock_ADC0ASYNC:
+ EFM_ASSERT(presc <= 3);
+ CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKDIV_MASK)
+ | (presc << _CMU_ADCCTRL_ADC0CLKDIV_SHIFT);
+ break;
+#endif
+
+#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK)
+ case cmuClock_ADC1ASYNC:
+ EFM_ASSERT(presc <= 3);
+ CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKDIV_MASK)
+ | (presc << _CMU_ADCCTRL_ADC1CLKDIV_SHIFT);
+ break;
+#endif
+ default:
+ EFM_ASSERT(0);
+ break;
+ }
+ break;
+
default:
EFM_ASSERT(0);
break;
@@ -2121,7 +2794,6 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Get currently selected reference clock used for a clock branch.
@@ -2150,12 +2822,10 @@
selReg = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
- switch (selReg)
- {
+ switch (selReg) {
case CMU_HFCLKSEL_REG:
-#if defined( _CMU_HFCLKSTATUS_MASK )
- switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
- {
+#if defined(_CMU_HFCLKSTATUS_MASK)
+ switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) {
case CMU_HFCLKSTATUS_SELECTED_LFXO:
ret = cmuSelect_LFXO;
break;
@@ -2177,11 +2847,10 @@
& (CMU_STATUS_HFRCOSEL
| CMU_STATUS_HFXOSEL
| CMU_STATUS_LFRCOSEL
-#if defined( CMU_STATUS_USHFRCODIV2SEL )
+#if defined(CMU_STATUS_USHFRCODIV2SEL)
| CMU_STATUS_USHFRCODIV2SEL
#endif
- | CMU_STATUS_LFXOSEL))
- {
+ | CMU_STATUS_LFXOSEL)) {
case CMU_STATUS_LFXOSEL:
ret = cmuSelect_LFXO;
break;
@@ -2194,7 +2863,7 @@
ret = cmuSelect_HFXO;
break;
-#if defined( CMU_STATUS_USHFRCODIV2SEL )
+#if defined(CMU_STATUS_USHFRCODIV2SEL)
case CMU_STATUS_USHFRCODIV2SEL:
ret = cmuSelect_USHFRCODIV2;
break;
@@ -2207,11 +2876,10 @@
#endif
break;
-#if defined( _CMU_LFCLKSEL_MASK ) || defined( _CMU_LFACLKSEL_MASK )
+#if defined(_CMU_LFCLKSEL_MASK) || defined(_CMU_LFACLKSEL_MASK)
case CMU_LFACLKSEL_REG:
-#if defined( _CMU_LFCLKSEL_MASK )
- switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK)
- {
+#if defined(_CMU_LFCLKSEL_MASK)
+ switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) {
case CMU_LFCLKSEL_LFA_LFRCO:
ret = cmuSelect_LFRCO;
break;
@@ -2220,16 +2888,15 @@
ret = cmuSelect_LFXO;
break;
-#if defined( CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
+#if defined(CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2)
case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
ret = cmuSelect_HFCLKLE;
break;
#endif
default:
-#if defined( CMU_LFCLKSEL_LFAE )
- if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK)
- {
+#if defined(CMU_LFCLKSEL_LFAE)
+ if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK) {
ret = cmuSelect_ULFRCO;
break;
}
@@ -2239,9 +2906,8 @@
break;
}
-#elif defined( _CMU_LFACLKSEL_MASK )
- switch (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK)
- {
+#elif defined(_CMU_LFACLKSEL_MASK)
+ switch (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) {
case CMU_LFACLKSEL_LFA_LFRCO:
ret = cmuSelect_LFRCO;
break;
@@ -2254,13 +2920,13 @@
ret = cmuSelect_ULFRCO;
break;
-#if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
+#if defined(_CMU_LFACLKSEL_LFA_HFCLKLE)
case CMU_LFACLKSEL_LFA_HFCLKLE:
ret = cmuSelect_HFCLKLE;
break;
#endif
-#if defined( CMU_LFACLKSEL_LFA_PLFRCO )
+#if defined(CMU_LFACLKSEL_LFA_PLFRCO)
case CMU_LFACLKSEL_LFA_PLFRCO:
ret = cmuSelect_PLFRCO;
break;
@@ -2274,11 +2940,10 @@
break;
#endif /* _CMU_LFCLKSEL_MASK || _CMU_LFACLKSEL_MASK */
-#if defined( _CMU_LFCLKSEL_MASK ) || defined( _CMU_LFBCLKSEL_MASK )
+#if defined(_CMU_LFCLKSEL_MASK) || defined(_CMU_LFBCLKSEL_MASK)
case CMU_LFBCLKSEL_REG:
-#if defined( _CMU_LFCLKSEL_MASK )
- switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK)
- {
+#if defined(_CMU_LFCLKSEL_MASK)
+ switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) {
case CMU_LFCLKSEL_LFB_LFRCO:
ret = cmuSelect_LFRCO;
break;
@@ -2287,22 +2952,21 @@
ret = cmuSelect_LFXO;
break;
-#if defined( CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 )
+#if defined(CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2)
case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2:
ret = cmuSelect_HFCLKLE;
break;
#endif
-#if defined( CMU_LFCLKSEL_LFB_HFCLKLE )
+#if defined(CMU_LFCLKSEL_LFB_HFCLKLE)
case CMU_LFCLKSEL_LFB_HFCLKLE:
ret = cmuSelect_HFCLKLE;
break;
#endif
default:
-#if defined( CMU_LFCLKSEL_LFBE )
- if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK)
- {
+#if defined(CMU_LFCLKSEL_LFBE)
+ if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK) {
ret = cmuSelect_ULFRCO;
break;
}
@@ -2312,9 +2976,8 @@
break;
}
-#elif defined( _CMU_LFBCLKSEL_MASK )
- switch (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK)
- {
+#elif defined(_CMU_LFBCLKSEL_MASK)
+ switch (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) {
case CMU_LFBCLKSEL_LFB_LFRCO:
ret = cmuSelect_LFRCO;
break;
@@ -2331,7 +2994,7 @@
ret = cmuSelect_HFCLKLE;
break;
-#if defined( CMU_LFBCLKSEL_LFB_PLFRCO )
+#if defined(CMU_LFBCLKSEL_LFB_PLFRCO)
case CMU_LFBCLKSEL_LFB_PLFRCO:
ret = cmuSelect_PLFRCO;
break;
@@ -2345,10 +3008,9 @@
break;
#endif /* _CMU_LFCLKSEL_MASK || _CMU_LFBCLKSEL_MASK */
-#if defined( _CMU_LFCLKSEL_LFC_MASK )
+#if defined(_CMU_LFCLKSEL_LFC_MASK)
case CMU_LFCCLKSEL_REG:
- switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK)
- {
+ switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) {
case CMU_LFCLKSEL_LFC_LFRCO:
ret = cmuSelect_LFRCO;
break;
@@ -2364,10 +3026,9 @@
break;
#endif
-#if defined( _CMU_LFECLKSEL_LFE_MASK )
+#if defined(_CMU_LFECLKSEL_LFE_MASK)
case CMU_LFECLKSEL_REG:
- switch (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK)
- {
+ switch (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) {
case CMU_LFECLKSEL_LFE_LFRCO:
ret = cmuSelect_LFRCO;
break;
@@ -2380,13 +3041,13 @@
ret = cmuSelect_ULFRCO;
break;
-#if defined ( _CMU_LFECLKSEL_LFE_HFCLKLE )
+#if defined (_CMU_LFECLKSEL_LFE_HFCLKLE)
case CMU_LFECLKSEL_LFE_HFCLKLE:
ret = cmuSelect_HFCLKLE;
break;
#endif
-#if defined( CMU_LFECLKSEL_LFE_PLFRCO )
+#if defined(CMU_LFECLKSEL_LFE_PLFRCO)
case CMU_LFECLKSEL_LFE_PLFRCO:
ret = cmuSelect_PLFRCO;
break;
@@ -2400,9 +3061,8 @@
#endif /* CMU_LFECLKSEL_REG */
case CMU_DBGCLKSEL_REG:
-#if defined( _CMU_DBGCLKSEL_DBG_MASK )
- switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK)
- {
+#if defined(_CMU_DBGCLKSEL_DBG_MASK)
+ switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK) {
case CMU_DBGCLKSEL_DBG_HFCLK:
ret = cmuSelect_HFCLK;
break;
@@ -2412,9 +3072,8 @@
break;
}
-#elif defined( _CMU_CTRL_DBGCLK_MASK )
- switch(CMU->CTRL & _CMU_CTRL_DBGCLK_MASK)
- {
+#elif defined(_CMU_CTRL_DBGCLK_MASK)
+ switch (CMU->CTRL & _CMU_CTRL_DBGCLK_MASK) {
case CMU_CTRL_DBGCLK_AUXHFRCO:
ret = cmuSelect_AUXHFRCO;
break;
@@ -2428,7 +3087,7 @@
#endif
break;
-#if defined( USB_PRESENT )
+#if defined(USBC_CLOCK_PRESENT)
case CMU_USBCCLKSEL_REG:
switch (CMU->STATUS
& (CMU_STATUS_USBCLFXOSEL
@@ -2438,8 +3097,7 @@
#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
| CMU_STATUS_USBCUSHFRCOSEL
#endif
- | CMU_STATUS_USBCLFRCOSEL))
- {
+ | CMU_STATUS_USBCLFRCOSEL)) {
#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
case CMU_STATUS_USBCHFCLKSEL:
ret = cmuSelect_HFCLK;
@@ -2467,6 +3125,124 @@
break;
#endif
+#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK)
+ case CMU_ADC0ASYNCSEL_REG:
+ switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKSEL_MASK) {
+ case CMU_ADCCTRL_ADC0CLKSEL_DISABLED:
+ ret = cmuSelect_Disabled;
+ break;
+
+ case CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO:
+ ret = cmuSelect_AUXHFRCO;
+ break;
+
+ case CMU_ADCCTRL_ADC0CLKSEL_HFXO:
+ ret = cmuSelect_HFXO;
+ break;
+
+ case CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK:
+ ret = cmuSelect_HFSRCCLK;
+ break;
+ }
+ break;
+#endif
+
+#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK)
+ case CMU_ADC1ASYNCSEL_REG:
+ switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKSEL_MASK) {
+ case CMU_ADCCTRL_ADC1CLKSEL_DISABLED:
+ ret = cmuSelect_Disabled;
+ break;
+
+ case CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO:
+ ret = cmuSelect_AUXHFRCO;
+ break;
+
+ case CMU_ADCCTRL_ADC1CLKSEL_HFXO:
+ ret = cmuSelect_HFXO;
+ break;
+
+ case CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK:
+ ret = cmuSelect_HFSRCCLK;
+ break;
+ }
+ break;
+#endif
+
+#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK)
+ case CMU_SDIOREFSEL_REG:
+ switch (CMU->SDIOCTRL & _CMU_SDIOCTRL_SDIOCLKSEL_MASK) {
+ case CMU_SDIOCTRL_SDIOCLKSEL_HFRCO:
+ ret = cmuSelect_HFRCO;
+ break;
+
+ case CMU_SDIOCTRL_SDIOCLKSEL_HFXO:
+ ret = cmuSelect_HFXO;
+ break;
+
+ case CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO:
+ ret = cmuSelect_AUXHFRCO;
+ break;
+
+ case CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO:
+ ret = cmuSelect_USHFRCO;
+ break;
+ }
+ break;
+#endif
+
+#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK)
+ case CMU_QSPI0REFSEL_REG:
+ switch (CMU->QSPICTRL & _CMU_QSPICTRL_QSPI0CLKSEL_MASK) {
+ case CMU_QSPICTRL_QSPI0CLKSEL_HFRCO:
+ ret = cmuSelect_HFRCO;
+ break;
+
+ case CMU_QSPICTRL_QSPI0CLKSEL_HFXO:
+ ret = cmuSelect_HFXO;
+ break;
+
+ case CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO:
+ ret = cmuSelect_AUXHFRCO;
+ break;
+
+ case CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO:
+ ret = cmuSelect_USHFRCO;
+ break;
+ }
+ break;
+#endif
+
+#if defined(_CMU_USBCTRL_USBCLKSEL_MASK)
+ case CMU_USBRCLKSEL_REG:
+ switch (CMU->USBCTRL & _CMU_USBCTRL_USBCLKSEL_MASK) {
+ case CMU_USBCTRL_USBCLKSEL_USHFRCO:
+ ret = cmuSelect_USHFRCO;
+ break;
+
+ case CMU_USBCTRL_USBCLKSEL_HFXO:
+ ret = cmuSelect_HFXO;
+ break;
+
+ case CMU_USBCTRL_USBCLKSEL_HFXOX2:
+ ret = cmuSelect_HFXOX2;
+ break;
+
+ case CMU_USBCTRL_USBCLKSEL_HFRCO:
+ ret = cmuSelect_HFRCO;
+ break;
+
+ case CMU_USBCTRL_USBCLKSEL_LFXO:
+ ret = cmuSelect_LFXO;
+ break;
+
+ case CMU_USBCTRL_USBCLKSEL_LFRCO:
+ ret = cmuSelect_LFRCO;
+ break;
+ }
+ break;
+#endif
+
default:
EFM_ASSERT(0);
ret = cmuSelect_Error;
@@ -2476,7 +3252,6 @@
return ret;
}
-
/***************************************************************************//**
* @brief
* Select reference clock/oscillator used for a clock branch.
@@ -2495,14 +3270,20 @@
* Clock branch to select reference clock for. One of:
* @li #cmuClock_HF
* @li #cmuClock_LFA
- * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO
+ * @li #cmuClock_LFB
+ * @if _CMU_LFCCLKEN0_MASK
* @li #cmuClock_LFC
- * @endif @if _SILICON_LABS_32B_SERIES_1
+ * @endif
+ * @if _CMU_LFECLKEN0_MASK
* @li #cmuClock_LFE
* @endif
- * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT
+ * @li #cmuClock_DBG
+ * @if _CMU_CMD_USBCLKSEL_MASK
* @li #cmuClock_USBC
* @endif
+ * @if _CMU_USBCTRL_MASK
+ * @li #cmuClock_USBR
+ * @endif
*
* @param[in] ref
* Reference selected for clocking, please refer to reference manual for
@@ -2510,10 +3291,17 @@
* @li #cmuSelect_HFRCO
* @li #cmuSelect_LFRCO
* @li #cmuSelect_HFXO
+ * @if _CMU_HFXOCTRL_HFXOX2EN_MASK
+ * @li #cmuSelect_HFXOX2
+ * @endif
* @li #cmuSelect_LFXO
* @li #cmuSelect_HFCLKLE
* @li #cmuSelect_AUXHFRCO
- * @li #cmuSelect_HFCLK @ifnot DOXYDOC_EFM32_GECKO_FAMILY
+ * @if _CMU_USHFRCOCTRL_MASK
+ * @li #cmuSelect_USHFRCO
+ * @endif
+ * @li #cmuSelect_HFCLK
+ * @ifnot DOXYDOC_EFM32_GECKO_FAMILY
* @li #cmuSelect_ULFRCO
* @li #cmuSelect_PLFRCO
* @endif
@@ -2525,30 +3313,25 @@
uint32_t freq;
uint32_t tmp;
uint32_t selRegId;
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
volatile uint32_t *selReg = NULL;
#endif
-#if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
+#if defined(CMU_LFCLKSEL_LFAE_ULFRCO)
uint32_t lfExtended = 0;
#endif
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
uint32_t vScaleFrequency = 0; /* Use default */
/* Start voltage upscaling before clock is set. */
- if (clock == cmuClock_HF)
- {
- if (ref == cmuSelect_HFXO)
- {
+ if (clock == cmuClock_HF) {
+ if (ref == cmuSelect_HFXO) {
vScaleFrequency = SystemHFXOClockGet();
- }
- else if ((ref == cmuSelect_HFRCO)
- && (CMU_HFRCOBandGet() > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX))
- {
+ } else if ((ref == cmuSelect_HFRCO)
+ && (CMU_HFRCOBandGet() > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) {
vScaleFrequency = CMU_HFRCOBandGet();
}
- if (vScaleFrequency != 0)
- {
+ if (vScaleFrequency != 0) {
EMU_VScaleEM01ByClock(vScaleFrequency, false);
}
}
@@ -2556,50 +3339,45 @@
selRegId = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
- switch (selRegId)
- {
+ switch (selRegId) {
case CMU_HFCLKSEL_REG:
- switch (ref)
- {
+ switch (ref) {
case cmuSelect_LFXO:
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
select = CMU_HFCLKSEL_HF_LFXO;
-#elif defined( _SILICON_LABS_32B_SERIES_0 )
+#elif defined(_SILICON_LABS_32B_SERIES_0)
select = CMU_CMD_HFCLKSEL_LFXO;
#endif
osc = cmuOsc_LFXO;
break;
case cmuSelect_LFRCO:
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
select = CMU_HFCLKSEL_HF_LFRCO;
-#elif defined( _SILICON_LABS_32B_SERIES_0 )
+#elif defined(_SILICON_LABS_32B_SERIES_0)
select = CMU_CMD_HFCLKSEL_LFRCO;
#endif
osc = cmuOsc_LFRCO;
break;
case cmuSelect_HFXO:
-#if defined( CMU_HFCLKSEL_HF_HFXO )
+#if defined(CMU_HFCLKSEL_HF_HFXO)
select = CMU_HFCLKSEL_HF_HFXO;
-#elif defined( CMU_CMD_HFCLKSEL_HFXO )
+#elif defined(CMU_CMD_HFCLKSEL_HFXO)
select = CMU_CMD_HFCLKSEL_HFXO;
#endif
osc = cmuOsc_HFXO;
-#if defined( CMU_MAX_FREQ_HFLE )
+#if defined(CMU_MAX_FREQ_HFLE)
/* Set 1 HFLE wait-state until the new HFCLKLE frequency is known.
This is known after 'select' is written below. */
- setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
-#endif
-#if defined( CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ )
+ setHfLeConfig(CMU_MAX_FREQ_HFLE + 1);
+#endif
+#if defined(CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ)
/* Adjust HFXO buffer current for frequencies above 32MHz */
- if (SystemHFXOClockGet() > 32000000)
- {
+ if (SystemHFXOClockGet() > 32000000) {
CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)
| CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ;
- }
- else
- {
+ } else {
CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)
| CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ;
}
@@ -2607,27 +3385,27 @@
break;
case cmuSelect_HFRCO:
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
select = CMU_HFCLKSEL_HF_HFRCO;
-#elif defined( _SILICON_LABS_32B_SERIES_0 )
+#elif defined(_SILICON_LABS_32B_SERIES_0)
select = CMU_CMD_HFCLKSEL_HFRCO;
#endif
osc = cmuOsc_HFRCO;
-#if defined( CMU_MAX_FREQ_HFLE )
+#if defined(CMU_MAX_FREQ_HFLE)
/* Set 1 HFLE wait-state until the new HFCLKLE frequency is known.
This is known after 'select' is written below. */
- setHfLeConfig(CMU_MAX_FREQ_HFLE + 1, CMU_MAX_FREQ_HFLE);
+ setHfLeConfig(CMU_MAX_FREQ_HFLE + 1);
#endif
break;
-#if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )
+#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2)
case cmuSelect_USHFRCODIV2:
select = CMU_CMD_HFCLKSEL_USHFRCODIV2;
osc = cmuOsc_USHFRCO;
break;
#endif
-#if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
+#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO)
case cmuSelect_ULFRCO:
/* ULFRCO cannot be used as HFCLK */
EFM_ASSERT(0);
@@ -2645,24 +3423,23 @@
/* Configure worst case wait states for flash access before selecting */
flashWaitStateMax();
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
/* Wait for voltage upscaling to complete before clock is set. */
- if (vScaleFrequency != 0)
- {
+ if (vScaleFrequency != 0) {
EMU_VScaleWait();
}
#endif
/* Switch to selected oscillator */
-#if defined( _CMU_HFCLKSEL_MASK )
+#if defined(_CMU_HFCLKSEL_MASK)
CMU->HFCLKSEL = select;
#else
CMU->CMD = select;
#endif
-#if defined( CMU_MAX_FREQ_HFLE )
+#if defined(CMU_MAX_FREQ_HFLE)
/* Update HFLE configuration after 'select' is set.
Note that the HFCLKLE clock is connected differently on planform 1 and 2 */
- setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE);
+ setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE));
#endif
/* Update CMSIS core clock variable */
@@ -2670,39 +3447,47 @@
freq = SystemCoreClockGet();
/* Optimize flash access wait state setting for currently selected core clk */
- flashWaitStateControl(freq);
-
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
+ CMU_UpdateWaitStates(freq, VSCALE_DEFAULT);
+
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
/* Keep EMU module informed on source HF clock frequency. This will apply voltage
downscaling after clock is set if downscaling is configured. */
- if (vScaleFrequency == 0)
- {
+ if (vScaleFrequency == 0) {
EMU_VScaleEM01ByClock(0, true);
}
#endif
break;
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
case CMU_LFACLKSEL_REG:
selReg = (selReg == NULL) ? &CMU->LFACLKSEL : selReg;
-#if !defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
+#if !defined(_CMU_LFACLKSEL_LFA_HFCLKLE)
/* HFCLKCLE can not be used as LFACLK */
EFM_ASSERT(ref != cmuSelect_HFCLKLE);
#endif
/* Fall through and select clock source */
+#if defined(_CMU_LFCCLKSEL_MASK)
+ case CMU_LFCCLKSEL_REG:
+ selReg = (selReg == NULL) ? &CMU->LFCCLKSEL : selReg;
+#if !defined(_CMU_LFCCLKSEL_LFC_HFCLKLE)
+ /* HFCLKCLE can not be used as LFCCLK */
+ EFM_ASSERT(ref != cmuSelect_HFCLKLE);
+#endif
+#endif
+ /* Fall through and select clock source */
+
case CMU_LFECLKSEL_REG:
selReg = (selReg == NULL) ? &CMU->LFECLKSEL : selReg;
-#if !defined( _CMU_LFECLKSEL_LFE_HFCLKLE )
+#if !defined(_CMU_LFECLKSEL_LFE_HFCLKLE)
/* HFCLKCLE can not be used as LFECLK */
EFM_ASSERT(ref != cmuSelect_HFCLKLE);
#endif
- /* Fall through and select clock source */
+ /* Fall through and select clock source */
case CMU_LFBCLKSEL_REG:
selReg = (selReg == NULL) ? &CMU->LFBCLKSEL : selReg;
- switch (ref)
- {
+ switch (ref) {
case cmuSelect_Disabled:
tmp = _CMU_LFACLKSEL_LFA_DISABLED;
break;
@@ -2721,7 +3506,7 @@
case cmuSelect_HFCLKLE:
/* Ensure correct HFLE wait-states and enable HFCLK to LE */
- setHfLeConfig(SystemCoreClockGet(), CMU_MAX_FREQ_HFLE);
+ setHfLeConfig(SystemCoreClockGet());
BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1);
tmp = _CMU_LFBCLKSEL_LFB_HFCLKLE;
break;
@@ -2731,7 +3516,7 @@
tmp = _CMU_LFACLKSEL_LFA_ULFRCO;
break;
-#if defined( _CMU_STATUS_PLFRCOENS_MASK )
+#if defined(_CMU_STATUS_PLFRCOENS_MASK)
case cmuSelect_PLFRCO:
/* Ensure selected oscillator is enabled, waiting for it to stabilize */
CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true);
@@ -2746,11 +3531,10 @@
*selReg = tmp;
break;
-#elif defined( _SILICON_LABS_32B_SERIES_0 )
+#elif defined(_SILICON_LABS_32B_SERIES_0)
case CMU_LFACLKSEL_REG:
case CMU_LFBCLKSEL_REG:
- switch (ref)
- {
+ switch (ref) {
case cmuSelect_Disabled:
tmp = _CMU_LFCLKSEL_LFA_DISABLED;
break;
@@ -2768,17 +3552,17 @@
break;
case cmuSelect_HFCLKLE:
-#if defined( CMU_MAX_FREQ_HFLE )
+#if defined(CMU_MAX_FREQ_HFLE)
/* Set HFLE wait-state and divider */
freq = SystemCoreClockGet();
- setHfLeConfig(freq, CMU_MAX_FREQ_HFLE);
+ setHfLeConfig(freq);
#endif
/* Ensure HFCORE to LE clocking is enabled */
BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1);
tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2;
break;
-#if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
+#if defined(CMU_LFCLKSEL_LFAE_ULFRCO)
case cmuSelect_ULFRCO:
/* ULFRCO is always enabled */
tmp = _CMU_LFCLKSEL_LFA_DISABLED;
@@ -2793,9 +3577,8 @@
}
/* Apply select */
- if (selRegId == CMU_LFACLKSEL_REG)
- {
-#if defined( _CMU_LFCLKSEL_LFAE_MASK )
+ if (selRegId == CMU_LFACLKSEL_REG) {
+#if defined(_CMU_LFCLKSEL_LFAE_MASK)
CMU->LFCLKSEL = (CMU->LFCLKSEL
& ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK))
| (tmp << _CMU_LFCLKSEL_LFA_SHIFT)
@@ -2804,10 +3587,8 @@
CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK)
| (tmp << _CMU_LFCLKSEL_LFA_SHIFT);
#endif
- }
- else
- {
-#if defined( _CMU_LFCLKSEL_LFBE_MASK )
+ } else {
+#if defined(_CMU_LFCLKSEL_LFBE_MASK)
CMU->LFCLKSEL = (CMU->LFCLKSEL
& ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK))
| (tmp << _CMU_LFCLKSEL_LFB_SHIFT)
@@ -2819,10 +3600,9 @@
}
break;
-#if defined( _CMU_LFCLKSEL_LFC_MASK )
+#if defined(_CMU_LFCLKSEL_LFC_MASK)
case CMU_LFCCLKSEL_REG:
- switch(ref)
- {
+ switch (ref) {
case cmuSelect_Disabled:
tmp = _CMU_LFCLKSEL_LFA_DISABLED;
break;
@@ -2852,11 +3632,10 @@
#endif
#endif
-#if defined( CMU_DBGCLKSEL_DBG ) || defined( CMU_CTRL_DBGCLK )
+#if defined(_CMU_DBGCLKSEL_DBG_MASK) || defined(CMU_CTRL_DBGCLK)
case CMU_DBGCLKSEL_REG:
- switch(ref)
- {
-#if defined( CMU_DBGCLKSEL_DBG )
+ switch (ref) {
+#if defined(_CMU_DBGCLKSEL_DBG_MASK)
case cmuSelect_AUXHFRCO:
/* Select AUXHFRCO as debug clock */
CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO;
@@ -2868,7 +3647,7 @@
break;
#endif
-#if defined( CMU_CTRL_DBGCLK )
+#if defined(CMU_CTRL_DBGCLK)
case cmuSelect_AUXHFRCO:
/* Select AUXHFRCO as debug clock */
CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))
@@ -2890,10 +3669,9 @@
break;
#endif
-#if defined( USB_PRESENT )
+#if defined(USBC_CLOCK_PRESENT)
case CMU_USBCCLKSEL_REG:
- switch(ref)
- {
+ switch (ref) {
case cmuSelect_LFXO:
/* Select LFXO as clock source for USB, can only be used in sleep mode */
/* Ensure selected oscillator is enabled, waiting for it to stabilize */
@@ -2903,8 +3681,7 @@
CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO;
/* Wait until clock is activated */
- while((CMU->STATUS & CMU_STATUS_USBCLFXOSEL)==0)
- {
+ while ((CMU->STATUS & CMU_STATUS_USBCLFXOSEL) == 0) {
}
break;
@@ -2917,24 +3694,22 @@
CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO;
/* Wait until clock is activated */
- while((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL)==0)
- {
+ while ((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL) == 0) {
}
break;
-#if defined( CMU_STATUS_USBCHFCLKSEL )
+#if defined(CMU_STATUS_USBCHFCLKSEL)
case cmuSelect_HFCLK:
/* Select undivided HFCLK as clock source for USB */
/* Oscillator must already be enabled to avoid a core lockup */
CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV;
/* Wait until clock is activated */
- while((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL)==0)
- {
+ while ((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL) == 0) {
}
break;
#endif
-#if defined( CMU_CMD_USBCCLKSEL_USHFRCO )
+#if defined(CMU_CMD_USBCCLKSEL_USHFRCO)
case cmuSelect_USHFRCO:
/* Select USHFRCO as clock source for USB */
/* Ensure selected oscillator is enabled, waiting for it to stabilize */
@@ -2944,8 +3719,7 @@
CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO;
/* Wait until clock is activated */
- while((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL)==0)
- {
+ while ((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL) == 0) {
}
break;
#endif
@@ -2958,16 +3732,361 @@
break;
#endif
+#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK)
+ case CMU_ADC0ASYNCSEL_REG:
+ switch (ref) {
+ case cmuSelect_Disabled:
+ tmp = _CMU_ADCCTRL_ADC0CLKSEL_DISABLED;
+ break;
+
+ case cmuSelect_AUXHFRCO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true);
+ tmp = _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO;
+ break;
+
+ case cmuSelect_HFXO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_HFXO, true, true);
+ tmp = _CMU_ADCCTRL_ADC0CLKSEL_HFXO;
+ break;
+
+ case cmuSelect_HFSRCCLK:
+ tmp = _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK;
+ break;
+
+ default:
+ /* Illegal clock source for ADC0ASYNC selected */
+ EFM_ASSERT(0);
+ return;
+ }
+
+ /* Apply select */
+ CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK)
+ | (tmp << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT);
+ break;
+#endif
+
+#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK)
+ case CMU_ADC1ASYNCSEL_REG:
+ switch (ref) {
+ case cmuSelect_Disabled:
+ tmp = _CMU_ADCCTRL_ADC1CLKSEL_DISABLED;
+ break;
+
+ case cmuSelect_AUXHFRCO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true);
+ tmp = _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO;
+ break;
+
+ case cmuSelect_HFXO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_HFXO, true, true);
+ tmp = _CMU_ADCCTRL_ADC1CLKSEL_HFXO;
+ break;
+
+ case cmuSelect_HFSRCCLK:
+ tmp = _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK;
+ break;
+
+ default:
+ /* Illegal clock source for ADC1ASYNC selected */
+ EFM_ASSERT(0);
+ return;
+ }
+
+ /* Apply select */
+ CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK)
+ | (tmp << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT);
+ break;
+#endif
+
+#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK)
+ case CMU_SDIOREFSEL_REG:
+ switch (ref) {
+ case cmuSelect_HFRCO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_HFRCO, true, true);
+ tmp = _CMU_SDIOCTRL_SDIOCLKSEL_HFRCO;
+ break;
+
+ case cmuSelect_HFXO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_HFXO, true, true);
+ tmp = _CMU_SDIOCTRL_SDIOCLKSEL_HFXO;
+ break;
+
+ case cmuSelect_AUXHFRCO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true);
+ tmp = _CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO;
+ break;
+
+ case cmuSelect_USHFRCO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true);
+ tmp = _CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO;
+ break;
+
+ default:
+ /* Illegal clock source for SDIOREF selected */
+ EFM_ASSERT(0);
+ return;
+ }
+
+ /* Apply select */
+ CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK)
+ | (tmp << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT);
+ break;
+#endif
+
+#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK)
+ case CMU_QSPI0REFSEL_REG:
+ switch (ref) {
+ case cmuSelect_HFRCO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_HFRCO, true, true);
+ tmp = _CMU_QSPICTRL_QSPI0CLKSEL_HFRCO;
+ break;
+
+ case cmuSelect_HFXO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_HFXO, true, true);
+ tmp = _CMU_QSPICTRL_QSPI0CLKSEL_HFXO;
+ break;
+
+ case cmuSelect_AUXHFRCO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true);
+ tmp = _CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO;
+ break;
+
+ case cmuSelect_USHFRCO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true);
+ tmp = _CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO;
+ break;
+
+ default:
+ /* Illegal clock source for QSPI0REF selected */
+ EFM_ASSERT(0);
+ return;
+ }
+
+ /* Apply select */
+ CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK)
+ | (tmp << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT);
+ break;
+#endif
+
+#if defined(_CMU_USBCTRL_USBCLKSEL_MASK)
+ case CMU_USBRCLKSEL_REG:
+ switch (ref) {
+ case cmuSelect_USHFRCO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true);
+ tmp = _CMU_USBCTRL_USBCLKSEL_USHFRCO;
+ break;
+
+ case cmuSelect_HFXO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_HFXO, true, true);
+ tmp = _CMU_USBCTRL_USBCLKSEL_HFXO;
+ break;
+
+ case cmuSelect_HFXOX2:
+ /* Only allowed for HFXO frequencies up to 25 MHz */
+ EFM_ASSERT(SystemHFXOClockGet() <= 25000000u);
+
+ /* Enable HFXO X2 */
+ CMU->HFXOCTRL |= CMU_HFXOCTRL_HFXOX2EN;
+
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_HFXO, true, true);
+
+ tmp = _CMU_USBCTRL_USBCLKSEL_HFXOX2;
+ break;
+
+ case cmuSelect_HFRCO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_HFRCO, true, true);
+ tmp = _CMU_USBCTRL_USBCLKSEL_HFRCO;
+ break;
+
+ case cmuSelect_LFXO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
+ tmp = _CMU_USBCTRL_USBCLKSEL_LFXO;
+ break;
+
+ case cmuSelect_LFRCO:
+ /* Ensure selected oscillator is enabled, waiting for it to stabilize */
+ CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
+ tmp = _CMU_USBCTRL_USBCLKSEL_LFRCO;
+ break;
+
+ default:
+ /* Illegal clock source for USBR selected */
+ EFM_ASSERT(0);
+ return;
+ }
+
+ /* Apply select */
+ CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK)
+ | (tmp << _CMU_USBCTRL_USBCLKSEL_SHIFT);
+ break;
+#endif
+
default:
EFM_ASSERT(0);
break;
}
-#if defined( CMU_MAX_FREQ_HFLE )
- /* Get to assert wait-state config. */
- getHfLeConfig();
-#endif
}
+#if defined(CMU_OSCENCMD_DPLLEN)
+/**************************************************************************//**
+ * @brief
+ * Lock the DPLL to a given frequency.
+ *
+ * The frequency is given by: Fout = Fref * (N+1) / (M+1).
+ *
+ * @note
+ * This function does not check if the given N & M values will actually
+ * produce the desired target frequency.
+ * Any peripheral running off HFRCO should be switched to HFRCODIV2 prior to
+ * calling this function to avoid over-clocking.
+ *
+ * @param[in] init
+ * DPLL setup parameters.
+ *
+ * @return
+ * Returns false on invalid target frequency or DPLL locking error.
+ *****************************************************************************/
+bool CMU_DPLLLock(CMU_DPLLInit_TypeDef *init)
+{
+ int index = 0;
+ unsigned int i;
+ bool hfrcoDiv2 = false;
+ uint32_t hfrcoCtrlVal, lockStatus, sysFreq;
+
+ EFM_ASSERT(init->frequency >= hfrcoCtrlTable[0].minFreq);
+ EFM_ASSERT(init->frequency
+ <= hfrcoCtrlTable[HFRCOCTRLTABLE_ENTRIES - 1].maxFreq);
+ EFM_ASSERT(init->n >= 32);
+ EFM_ASSERT(init->n <= (_CMU_DPLLCTRL1_N_MASK >> _CMU_DPLLCTRL1_N_SHIFT));
+ EFM_ASSERT(init->m <= (_CMU_DPLLCTRL1_M_MASK >> _CMU_DPLLCTRL1_M_SHIFT));
+ EFM_ASSERT(init->ssInterval <= (_CMU_HFRCOSS_SSINV_MASK
+ >> _CMU_HFRCOSS_SSINV_SHIFT));
+ EFM_ASSERT(init->ssAmplitude <= (_CMU_HFRCOSS_SSAMP_MASK
+ >> _CMU_HFRCOSS_SSAMP_SHIFT));
+
+#if defined(_EMU_STATUS_VSCALE_MASK)
+ if ((EMU_VScaleGet() == emuVScaleEM01_LowPower)
+ && (init->frequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) {
+ EFM_ASSERT(false);
+ return false;
+ }
+#endif
+
+ // Find correct HFRCO band, and retrieve a HFRCOCTRL value.
+ for (i = 0; i < HFRCOCTRLTABLE_ENTRIES; i++) {
+ if ((init->frequency >= hfrcoCtrlTable[i].minFreq)
+ && (init->frequency <= hfrcoCtrlTable[i].maxFreq)) {
+ index = i; // Correct band found
+ break;
+ }
+ }
+ if (index == HFRCOCTRLTABLE_ENTRIES) {
+ EFM_ASSERT(false);
+ return false; // Target frequency out of spec.
+ }
+ hfrcoCtrlVal = hfrcoCtrlTable[index].value;
+
+ // Check if we have a calibrated HFRCOCTRL.TUNING value in device DI page.
+ if (hfrcoCtrlTable[index].band != (CMU_HFRCOFreq_TypeDef)0) {
+ uint32_t tuning;
+
+ tuning = (CMU_HFRCODevinfoGet(hfrcoCtrlTable[index].band)
+ & _CMU_HFRCOCTRL_TUNING_MASK)
+ >> _CMU_HFRCOCTRL_TUNING_SHIFT;
+
+ // When HFRCOCTRL.FINETUNINGEN is enabled, the center frequency
+ // of the band shifts down by 5.8%. We subtract 9 to compensate.
+ if (tuning > 9) {
+ tuning -= 9;
+ } else {
+ tuning = 0;
+ }
+
+ hfrcoCtrlVal |= tuning << _CMU_HFRCOCTRL_TUNING_SHIFT;
+ }
+
+ // Update CMSIS frequency SystemHfrcoFreq value.
+ SystemHfrcoFreq = init->frequency;
+
+ // Set max wait-states while changing core clock.
+ if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) {
+ flashWaitStateMax();
+ }
+
+ // Update HFLE configuration before updating HFRCO, use new DPLL frequency.
+ if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) {
+ setHfLeConfig(init->frequency);
+
+ // Switch to HFRCO/2 before setting DPLL to avoid over-clocking.
+ hfrcoDiv2 = (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
+ == CMU_HFCLKSTATUS_SELECTED_HFRCODIV2;
+ CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCODIV2;
+ }
+
+ CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS;
+ while ((CMU->STATUS & (CMU_STATUS_DPLLENS | CMU_STATUS_DPLLRDY)) != 0) ;
+ CMU->IFC = CMU_IFC_DPLLRDY | CMU_IFC_DPLLLOCKFAILLOW
+ | CMU_IFC_DPLLLOCKFAILHIGH;
+ CMU->DPLLCTRL1 = (init->n << _CMU_DPLLCTRL1_N_SHIFT)
+ | (init->m << _CMU_DPLLCTRL1_M_SHIFT);
+ CMU->HFRCOCTRL = hfrcoCtrlVal;
+ CMU->DPLLCTRL = (init->refClk << _CMU_DPLLCTRL_REFSEL_SHIFT)
+ | (init->autoRecover << _CMU_DPLLCTRL_AUTORECOVER_SHIFT)
+ | (init->edgeSel << _CMU_DPLLCTRL_EDGESEL_SHIFT)
+ | (init->lockMode << _CMU_DPLLCTRL_MODE_SHIFT);
+ CMU->OSCENCMD = CMU_OSCENCMD_DPLLEN;
+ while ((lockStatus = (CMU->IF & (CMU_IF_DPLLRDY
+ | CMU_IF_DPLLLOCKFAILLOW
+ | CMU_IF_DPLLLOCKFAILHIGH))) == 0) ;
+
+ if ((CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)
+ && (hfrcoDiv2 == false)) {
+ CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO;
+ }
+
+ // If HFRCO is selected as HF clock, optimize flash access wait-state
+ // configuration for this frequency and update CMSIS core clock variable.
+ if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) {
+ // Call @ref SystemCoreClockGet() to update CMSIS core clock variable.
+ sysFreq = SystemCoreClockGet();
+ EFM_ASSERT(sysFreq <= init->frequency);
+ EFM_ASSERT(sysFreq <= SystemHfrcoFreq);
+ EFM_ASSERT(init->frequency == SystemHfrcoFreq);
+ CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT);
+ }
+
+ // Reduce HFLE frequency if possible.
+ setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE));
+
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
+ // Update voltage scaling.
+ EMU_VScaleEM01ByClock(0, true);
+#endif
+
+ if (lockStatus == CMU_IF_DPLLRDY) {
+ return true;
+ }
+ return false;
+}
+#endif // CMU_OSCENCMD_DPLLEN
+
/**************************************************************************//**
* @brief
* CMU low frequency register synchronization freeze control.
@@ -2999,8 +4118,7 @@
*****************************************************************************/
void CMU_FreezeEnable(bool enable)
{
- if (enable)
- {
+ if (enable) {
/* Wait for any ongoing LF synchronization to complete. This is just to */
/* protect against the rare case when a user */
/* - modifies a register requiring LF sync */
@@ -3008,20 +4126,16 @@
/* - then modifies the same register again */
/* since modifying a register while it is in sync progress should be */
/* avoided. */
- while (CMU->SYNCBUSY)
- {
+ while (CMU->SYNCBUSY) {
}
CMU->FREEZE = CMU_FREEZE_REGFREEZE;
- }
- else
- {
+ } else {
CMU->FREEZE = 0;
}
}
-
-#if defined( _CMU_HFRCOCTRL_BAND_MASK )
+#if defined(_CMU_HFRCOCTRL_BAND_MASK)
/***************************************************************************//**
* @brief
* Get HFRCO band in use.
@@ -3036,8 +4150,7 @@
}
#endif /* _CMU_HFRCOCTRL_BAND_MASK */
-
-#if defined( _CMU_HFRCOCTRL_BAND_MASK )
+#if defined(_CMU_HFRCOCTRL_BAND_MASK)
/***************************************************************************//**
* @brief
* Set HFRCO band and the tuning value based on the value in the calibration
@@ -3053,8 +4166,7 @@
CMU_Select_TypeDef osc;
/* Read tuning value from calibration table */
- switch (band)
- {
+ switch (band) {
case cmuHFRCOBand_1MHz:
tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK)
>> _DEVINFO_HFRCOCAL0_BAND1_SHIFT;
@@ -3080,7 +4192,7 @@
>> _DEVINFO_HFRCOCAL1_BAND21_SHIFT;
break;
-#if defined( _CMU_HFRCOCTRL_BAND_28MHZ )
+#if defined(_CMU_HFRCOCTRL_BAND_28MHZ)
case cmuHFRCOBand_28MHz:
tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK)
>> _DEVINFO_HFRCOCAL1_BAND28_SHIFT;
@@ -3094,39 +4206,35 @@
/* If HFRCO is used for core clock, we have to consider flash access WS. */
osc = CMU_ClockSelectGet(cmuClock_HF);
- if (osc == cmuSelect_HFRCO)
- {
+ if (osc == cmuSelect_HFRCO) {
/* Configure worst case wait states for flash access before setting divider */
flashWaitStateMax();
}
/* Set band/tuning */
- CMU->HFRCOCTRL = (CMU->HFRCOCTRL &
- ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK))
+ CMU->HFRCOCTRL = (CMU->HFRCOCTRL
+ & ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK))
| (band << _CMU_HFRCOCTRL_BAND_SHIFT)
| (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT);
/* If HFRCO is used for core clock, optimize flash WS */
- if (osc == cmuSelect_HFRCO)
- {
- /* Call SystemCoreClockGet() to update CMSIS core clock variable. */
+ if (osc == cmuSelect_HFRCO) {
+ /* Call @ref SystemCoreClockGet() to update CMSIS core clock variable. */
freq = SystemCoreClockGet();
- flashWaitStateControl(freq);
+ CMU_UpdateWaitStates(freq, VSCALE_DEFAULT);
}
#if defined(CMU_MAX_FREQ_HFLE)
/* Reduce HFLE frequency if possible. */
- setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE);
-#endif
-
+ setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE));
+#endif
}
#endif /* _CMU_HFRCOCTRL_BAND_MASK */
-
-#if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
+#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
/**************************************************************************//**
* @brief
- * Get a pointer to the HFRCO frequency calibration word in DEVINFO
+ * Get the HFRCO frequency calibration word in DEVINFO
*
* @param[in] freq
* Frequency in Hz
@@ -3136,8 +4244,7 @@
*****************************************************************************/
static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq)
{
- switch (freq)
- {
+ switch (freq) {
/* 1, 2 and 4MHz share the same calibration word */
case cmuHFRCOFreq_1M0Hz:
case cmuHFRCOFreq_2M0Hz:
@@ -3165,12 +4272,31 @@
case cmuHFRCOFreq_38M0Hz:
return DEVINFO->HFRCOCAL12;
+#if defined(_DEVINFO_HFRCOCAL13_MASK)
+ case cmuHFRCOFreq_48M0Hz:
+ return DEVINFO->HFRCOCAL13;
+#endif
+
+#if defined(_DEVINFO_HFRCOCAL14_MASK)
+ case cmuHFRCOFreq_56M0Hz:
+ return DEVINFO->HFRCOCAL14;
+#endif
+
+#if defined(_DEVINFO_HFRCOCAL15_MASK)
+ case cmuHFRCOFreq_64M0Hz:
+ return DEVINFO->HFRCOCAL15;
+#endif
+
+#if defined(_DEVINFO_HFRCOCAL16_MASK)
+ case cmuHFRCOFreq_72M0Hz:
+ return DEVINFO->HFRCOCAL16;
+#endif
+
default: /* cmuHFRCOFreq_UserDefined */
return 0;
}
}
-
/***************************************************************************//**
* @brief
* Get current HFRCO frequency.
@@ -3183,7 +4309,6 @@
return (CMU_HFRCOFreq_TypeDef)SystemHfrcoFreq;
}
-
/***************************************************************************//**
* @brief
* Set HFRCO calibration for the selected target frequency.
@@ -3195,28 +4320,28 @@
{
uint32_t freqCal;
uint32_t sysFreq;
+ uint32_t prevFreq;
/* Get DEVINFO index, set CMSIS frequency SystemHfrcoFreq */
freqCal = CMU_HFRCODevinfoGet(setFreq);
EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
+ prevFreq = SystemHfrcoFreq;
SystemHfrcoFreq = (uint32_t)setFreq;
/* Set max wait-states while changing core clock */
- if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)
- {
+ if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) {
flashWaitStateMax();
}
/* Wait for any previous sync to complete, and then set calibration data
for the selected frequency. */
- while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT));
+ while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT)) ;
/* Check for valid calibration data */
EFM_ASSERT(freqCal != UINT_MAX);
/* Set divider in HFRCOCTRL for 1, 2 and 4MHz */
- switch(setFreq)
- {
+ switch (setFreq) {
case cmuHFRCOFreq_1M0Hz:
freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
| CMU_HFRCOCTRL_CLKDIV_DIV4;
@@ -3238,37 +4363,44 @@
/* Update HFLE configuration before updating HFRCO.
Use the new set frequency. */
- if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)
- {
+ if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) {
/* setFreq is worst-case as dividers may reduce the HFLE frequency. */
- setHfLeConfig(setFreq, CMU_MAX_FREQ_HFLE);
+ setHfLeConfig(setFreq);
+ }
+
+ if (setFreq > prevFreq) {
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
+ /* When increasing frequency we need to voltage scale before the change */
+ EMU_VScaleEM01ByClock(setFreq, true);
+#endif
}
CMU->HFRCOCTRL = freqCal;
/* If HFRCO is selected as HF clock, optimize flash access wait-state configuration
for this frequency and update CMSIS core clock variable. */
- if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)
- {
- /* Call SystemCoreClockGet() to update CMSIS core clock variable. */
+ if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) {
+ /* Call @ref SystemCoreClockGet() to update CMSIS core clock variable. */
sysFreq = SystemCoreClockGet();
EFM_ASSERT(sysFreq <= (uint32_t)setFreq);
EFM_ASSERT(sysFreq <= SystemHfrcoFreq);
EFM_ASSERT(setFreq == SystemHfrcoFreq);
- flashWaitStateControl(sysFreq);
+ CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT);
}
/* Reduce HFLE frequency if possible. */
- setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE);
-
- /* Update voltage scaling */
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
- EMU_VScaleEM01ByClock(0, true);
-#endif
+ setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE));
+
+ if (setFreq <= prevFreq) {
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
+ /* When decreasing frequency we need to voltage scale after the change */
+ EMU_VScaleEM01ByClock(0, true);
+#endif
+ }
}
#endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */
-#if defined( _CMU_HFRCOCTRL_SUDELAY_MASK )
+#if defined(_CMU_HFRCOCTRL_SUDELAY_MASK)
/***************************************************************************//**
* @brief
* Get the HFRCO startup delay.
@@ -3285,7 +4417,6 @@
>> _CMU_HFRCOCTRL_SUDELAY_SHIFT;
}
-
/***************************************************************************//**
* @brief
* Set the HFRCO startup delay.
@@ -3306,8 +4437,74 @@
}
#endif
-
-#if defined( _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK )
+#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK)
+/**************************************************************************//**
+ * @brief
+ * Get the USHFRCO frequency calibration word in DEVINFO
+ *
+ * @param[in] freq
+ * Frequency in Hz
+ *
+ * @return
+ * USHFRCO calibration word for a given frequency
+ *****************************************************************************/
+static uint32_t CMU_USHFRCODevinfoGet(CMU_USHFRCOFreq_TypeDef freq)
+{
+ switch (freq) {
+ case cmuUSHFRCOFreq_16M0Hz:
+ return DEVINFO->USHFRCOCAL7;
+
+ case cmuUSHFRCOFreq_32M0Hz:
+ return DEVINFO->USHFRCOCAL11;
+
+ case cmuUSHFRCOFreq_48M0Hz:
+ return DEVINFO->USHFRCOCAL13;
+
+ case cmuUSHFRCOFreq_50M0Hz:
+ return DEVINFO->USHFRCOCAL14;
+
+ default: /* cmuUSHFRCOFreq_UserDefined */
+ return 0;
+ }
+}
+
+/***************************************************************************//**
+ * @brief
+ * Get current USHFRCO frequency.
+ *
+ * @return
+ * HFRCO frequency
+ ******************************************************************************/
+CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void)
+{
+ return (CMU_USHFRCOFreq_TypeDef) ushfrcoFreq;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Set USHFRCO calibration for the selected target frequency.
+ *
+ * @param[in] setFreq
+ * USHFRCO frequency to set
+ ******************************************************************************/
+void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq)
+{
+ uint32_t freqCal;
+
+ /* Get DEVINFO calibration values */
+ freqCal = CMU_USHFRCODevinfoGet(setFreq);
+ EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
+ ushfrcoFreq = (uint32_t)setFreq;
+
+ /* Wait for any previous sync to complete, and then set calibration data
+ for the selected frequency. */
+ while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_USHFRCOBSY_SHIFT)) ;
+
+ CMU->USHFRCOCTRL = freqCal;
+}
+#endif /* _CMU_USHFRCOCTRL_FREQRANGE_MASK */
+
+#if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK)
/***************************************************************************//**
* @brief
* Enable or disable HFXO autostart
@@ -3335,35 +4532,33 @@
uint32_t hfxoCtrl;
/* Mask supported enable bits. */
-#if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
+#if defined(_CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK)
userSel &= _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK;
#else
userSel = 0;
#endif
- hfxoCtrl = CMU->HFXOCTRL & ~( userSel
- | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
- | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK);
+ hfxoCtrl = CMU->HFXOCTRL & ~(userSel
+ | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
+ | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK);
hfxoCtrl |= userSel
| (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0)
| (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0);
/* Set wait-states for HFXO if automatic start and select is configured. */
- if (userSel || enEM0EM1StartSel)
- {
+ if (userSel || enEM0EM1StartSel) {
hfxoFreq = SystemHFXOClockGet();
- flashWaitStateControl(hfxoFreq);
- setHfLeConfig(hfxoFreq, CMU_MAX_FREQ_HFLE);
+ CMU_UpdateWaitStates(hfxoFreq, VSCALE_DEFAULT);
+ setHfLeConfig(hfxoFreq);
}
-
- /* Update HFXOCTRL after wait-states are updated as HF may automatically switch
+
+ /* Update HFXOCTRL after wait-states are updated as HF may automatically switch
to HFXO when automatic select is enabled . */
CMU->HFXOCTRL = hfxoCtrl;
}
#endif
-
/**************************************************************************//**
* @brief
* Set HFXO control registers
@@ -3381,94 +4576,109 @@
/* Do not disable HFXO if it is currently selected as HF/Core clock */
EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO);
- /* REGPWRSEL must be set to DVDD before the HFXO can be enabled. */
-#if defined( _EMU_PWRCTRL_REGPWRSEL_MASK )
- EFM_ASSERT(EMU->PWRCTRL & EMU_PWRCTRL_REGPWRSEL_DVDD);
-#endif
-
/* HFXO must be disabled before reconfiguration */
CMU_OscillatorEnable(cmuOsc_HFXO, false, true);
-#if defined( _CMU_HFXOCTRL_MASK )
+#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100)
+ uint32_t tmp = CMU_HFXOCTRL_MODE_XTAL;
+
+ switch (hfxoInit->mode) {
+ case cmuOscMode_Crystal:
+ tmp = CMU_HFXOCTRL_MODE_XTAL;
+ break;
+ case cmuOscMode_External:
+ tmp = CMU_HFXOCTRL_MODE_DIGEXTCLK;
+ break;
+ case cmuOscMode_AcCoupled:
+ tmp = CMU_HFXOCTRL_MODE_ACBUFEXTCLK;
+ break;
+ default:
+ EFM_ASSERT(false); /* Unsupported configuration */
+ }
+ CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_MODE_MASK) | tmp;
+
+#if defined(CMU_HFXOCTRL_HFXOX2EN)
+ /* HFXO Doubler can only be enabled on crystals up to max 25 MHz */
+ tmp = 0;
+ if (SystemHFXOClockGet() <= 25000000) {
+ tmp |= CMU_HFXOCTRL_HFXOX2EN;
+ }
+
+ CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_HFXOX2EN_MASK) | tmp;
+#endif
+
+ /* Set tuning for startup and steady state */
+ CMU->HFXOSTARTUPCTRL = (hfxoInit->ctuneStartup << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT)
+ | (hfxoInit->xoCoreBiasTrimStartup << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT);
+
+ CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK
+ | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK))
+ | (hfxoInit->ctuneSteadyState << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT)
+ | (hfxoInit->xoCoreBiasTrimSteadyState << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT);
+
+ /* Set timeouts */
+ CMU->HFXOTIMEOUTCTRL = (hfxoInit->timeoutPeakDetect << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT)
+ | (hfxoInit->timeoutSteady << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT)
+ | (hfxoInit->timeoutStartup << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT);
+
+#elif defined(_CMU_HFXOCTRL_MASK)
/* Verify that the deprecated autostart fields are not used,
* @ref CMU_HFXOAutostartEnable must be used instead. */
EFM_ASSERT(!(hfxoInit->autoStartEm01
- || hfxoInit->autoSelEm01
- || hfxoInit->autoStartSelOnRacWakeup));
-
- uint32_t mode = CMU_HFXOCTRL_MODE_XTAL;
+ || hfxoInit->autoSelEm01
+ || hfxoInit->autoStartSelOnRacWakeup));
+
+ uint32_t tmp = CMU_HFXOCTRL_MODE_XTAL;
/* AC coupled external clock not supported */
EFM_ASSERT(hfxoInit->mode != cmuOscMode_AcCoupled);
- if (hfxoInit->mode == cmuOscMode_External)
- {
- mode = CMU_HFXOCTRL_MODE_EXTCLK;
+ if (hfxoInit->mode == cmuOscMode_External) {
+ tmp = CMU_HFXOCTRL_MODE_DIGEXTCLK;
}
/* Apply control settings */
- BUS_RegMaskedWrite(&CMU->HFXOCTRL,
- _CMU_HFXOCTRL_LOWPOWER_MASK | _CMU_HFXOCTRL_MODE_MASK,
- (hfxoInit->lowPowerMode ? CMU_HFXOCTRL_LOWPOWER : 0) | mode);
+ CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_MODE_MASK)
+ | tmp;
+ BUS_RegBitWrite(&CMU->HFXOCTRL, _CMU_HFXOCTRL_LOWPOWER_SHIFT, hfxoInit->lowPowerMode);
/* Set XTAL tuning parameters */
#if defined(_CMU_HFXOCTRL1_PEAKDETTHR_MASK)
/* Set peak detection threshold */
- BUS_RegMaskedWrite(&CMU->HFXOCTRL1,
- _CMU_HFXOCTRL1_PEAKDETTHR_MASK,
- hfxoInit->thresholdPeakDetect);
-#endif
-
+ CMU->HFXOCTRL1 = (CMU->HFXOCTRL1 & ~_CMU_HFXOCTRL1_PEAKDETTHR_MASK)
+ | (hfxoInit->thresholdPeakDetect << _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT);
+#endif
/* Set tuning for startup and steady state */
- BUS_RegMaskedWrite(&CMU->HFXOSTARTUPCTRL,
- _CMU_HFXOSTARTUPCTRL_CTUNE_MASK
- | _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK,
- (hfxoInit->ctuneStartup
- << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT)
- | (hfxoInit->xoCoreBiasTrimStartup
- << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT));
-
- BUS_RegMaskedWrite(&CMU->HFXOSTEADYSTATECTRL,
- _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK
- | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
- | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
- | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK,
- (hfxoInit->ctuneSteadyState
- << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT)
- | (hfxoInit->regIshSteadyState
- << _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT)
- | (hfxoInit->xoCoreBiasTrimSteadyState
- << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT)
- | getRegIshUpperVal(hfxoInit->regIshSteadyState));
+ CMU->HFXOSTARTUPCTRL = (hfxoInit->ctuneStartup << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT)
+ | (hfxoInit->xoCoreBiasTrimStartup << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT);
+
+ CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK
+ | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
+ | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
+ | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK))
+ | (hfxoInit->ctuneSteadyState << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT)
+ | (hfxoInit->xoCoreBiasTrimSteadyState << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT)
+ | (hfxoInit->regIshSteadyState << _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT)
+ | getRegIshUpperVal(hfxoInit->regIshSteadyState);
/* Set timeouts */
- BUS_RegMaskedWrite(&CMU->HFXOTIMEOUTCTRL,
- _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK
- | _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK
- | _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK
- | _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK,
- (hfxoInit->timeoutShuntOptimization
- << _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT)
- | (hfxoInit->timeoutPeakDetect
- << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT)
- | (hfxoInit->timeoutSteady
- << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT)
- | (hfxoInit->timeoutStartup
- << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT));
+ CMU->HFXOTIMEOUTCTRL = (hfxoInit->timeoutPeakDetect << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT)
+ | (hfxoInit->timeoutSteady << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT)
+ | (hfxoInit->timeoutStartup << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT)
+ | (hfxoInit->timeoutShuntOptimization << _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT);
+
#else
- BUS_RegMaskedWrite(&CMU->CTRL,
- _CMU_CTRL_HFXOTIMEOUT_MASK
- | _CMU_CTRL_HFXOBOOST_MASK
- | _CMU_CTRL_HFXOMODE_MASK
- | _CMU_CTRL_HFXOGLITCHDETEN_MASK,
- (hfxoInit->timeout << _CMU_CTRL_HFXOTIMEOUT_SHIFT)
- | (hfxoInit->boost << _CMU_CTRL_HFXOBOOST_SHIFT)
- | (hfxoInit->mode << _CMU_CTRL_HFXOMODE_SHIFT)
- | (hfxoInit->glitchDetector ? CMU_CTRL_HFXOGLITCHDETEN : 0));
+ CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_HFXOTIMEOUT_MASK
+ | _CMU_CTRL_HFXOBOOST_MASK
+ | _CMU_CTRL_HFXOMODE_MASK
+ | _CMU_CTRL_HFXOGLITCHDETEN_MASK))
+ | (hfxoInit->timeout << _CMU_CTRL_HFXOTIMEOUT_SHIFT)
+ | (hfxoInit->boost << _CMU_CTRL_HFXOBOOST_SHIFT)
+ | (hfxoInit->mode << _CMU_CTRL_HFXOMODE_SHIFT)
+ | (hfxoInit->glitchDetector ? CMU_CTRL_HFXOGLITCHDETEN : 0);
#endif
}
-
/***************************************************************************//**
* @brief
* Get the LCD framerate divisor (FDIV) setting.
@@ -3478,14 +4688,13 @@
******************************************************************************/
uint32_t CMU_LCDClkFDIVGet(void)
{
-#if defined( LCD_PRESENT )
+#if defined(LCD_PRESENT) && defined(_CMU_LCDCTRL_MASK)
return (CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT;
#else
return 0;
#endif /* defined(LCD_PRESENT) */
}
-
/***************************************************************************//**
* @brief
* Set the LCD framerate divisor (FDIV) setting.
@@ -3494,19 +4703,18 @@
* The FDIV field (CMU LCDCTRL register) should only be modified while the
* LCD module is clock disabled (CMU LFACLKEN0.LCD bit is 0). This function
* will NOT modify FDIV if the LCD module clock is enabled. Please refer to
- * CMU_ClockEnable() for disabling/enabling LCD clock.
+ * @ref CMU_ClockEnable() for disabling/enabling LCD clock.
*
* @param[in] div
* The FDIV setting to use.
******************************************************************************/
void CMU_LCDClkFDIVSet(uint32_t div)
{
-#if defined( LCD_PRESENT )
+#if defined(LCD_PRESENT) && defined(_CMU_LCDCTRL_MASK)
EFM_ASSERT(div <= cmuClkDiv_128);
/* Do not allow modification if LCD clock enabled */
- if (CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD)
- {
+ if (CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD) {
return;
}
@@ -3518,7 +4726,6 @@
#endif /* defined(LCD_PRESENT) */
}
-
/**************************************************************************//**
* @brief
* Set LFXO control registers
@@ -3539,7 +4746,7 @@
/* LFXO must be disabled before reconfiguration */
CMU_OscillatorEnable(cmuOsc_LFXO, false, false);
-#if defined( _CMU_LFXOCTRL_MASK )
+#if defined(_CMU_LFXOCTRL_MASK)
BUS_RegMaskedWrite(&CMU->LFXOCTRL,
_CMU_LFXOCTRL_TUNING_MASK
| _CMU_LFXOCTRL_GAIN_MASK
@@ -3560,13 +4767,12 @@
| (lfxoInit->mode << _CMU_CTRL_LFXOMODE_SHIFT));
#endif
-#if defined( _EMU_AUXCTRL_REDLFXOBOOST_MASK )
+#if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK)
bool emuReduce = (lfxoInit->boost & 0x1);
BUS_RegBitWrite(&EMU->AUXCTRL, _EMU_AUXCTRL_REDLFXOBOOST_SHIFT, emuReduce ? 1 : 0);
#endif
}
-
/***************************************************************************//**
* @brief
* Enable/disable oscillator.
@@ -3594,23 +4800,22 @@
void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)
{
uint32_t rdyBitPos;
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
uint32_t ensBitPos;
#endif
-#if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
+#if defined(_CMU_STATUS_HFXOPEAKDETRDY_MASK)
uint32_t hfxoTrimStatus;
#endif
uint32_t enBit;
uint32_t disBit;
- switch (osc)
- {
+ switch (osc) {
case cmuOsc_HFRCO:
enBit = CMU_OSCENCMD_HFRCOEN;
disBit = CMU_OSCENCMD_HFRCODIS;
rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT;
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT;
#endif
break;
@@ -3619,7 +4824,7 @@
enBit = CMU_OSCENCMD_HFXOEN;
disBit = CMU_OSCENCMD_HFXODIS;
rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT;
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
ensBitPos = _CMU_STATUS_HFXOENS_SHIFT;
#endif
break;
@@ -3628,7 +4833,7 @@
enBit = CMU_OSCENCMD_AUXHFRCOEN;
disBit = CMU_OSCENCMD_AUXHFRCODIS;
rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT;
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT;
#endif
break;
@@ -3637,7 +4842,7 @@
enBit = CMU_OSCENCMD_LFRCOEN;
disBit = CMU_OSCENCMD_LFRCODIS;
rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT;
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT;
#endif
break;
@@ -3646,23 +4851,23 @@
enBit = CMU_OSCENCMD_LFXOEN;
disBit = CMU_OSCENCMD_LFXODIS;
rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT;
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
ensBitPos = _CMU_STATUS_LFXOENS_SHIFT;
#endif
break;
-#if defined( _CMU_STATUS_USHFRCOENS_MASK )
+#if defined(_CMU_STATUS_USHFRCOENS_MASK)
case cmuOsc_USHFRCO:
enBit = CMU_OSCENCMD_USHFRCOEN;
disBit = CMU_OSCENCMD_USHFRCODIS;
rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT;
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT;
#endif
break;
#endif
-#if defined( _CMU_STATUS_PLFRCOENS_MASK )
+#if defined(_CMU_STATUS_PLFRCOENS_MASK)
case cmuOsc_PLFRCO:
enBit = CMU_OSCENCMD_PLFRCOEN;
disBit = CMU_OSCENCMD_PLFRCODIS;
@@ -3679,51 +4884,46 @@
return;
}
- if (enable)
- {
- #if defined( _CMU_HFXOCTRL_MASK )
+ if (enable) {
+ #if defined(_CMU_HFXOCTRL_MASK)
bool firstHfxoEnable = false;
/* Enabling the HFXO for the first time requires special handling. We use the
* PEAKDETSHUTOPTMODE field of the HFXOCTRL register to see if this is the
* first time the HFXO is enabled. */
- if ((osc == cmuOsc_HFXO) &&
- ((CMU->HFXOCTRL & (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK))
- == CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD))
- {
+ if ((osc == cmuOsc_HFXO) && (getHfxoTuningMode() == HFXO_TUNING_MODE_AUTO)) {
+ /* REGPWRSEL must be set to DVDD before the HFXO can be enabled. */
+#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK)
+ EFM_ASSERT(EMU->PWRCTRL & EMU_PWRCTRL_REGPWRSEL_DVDD);
+#endif
+
firstHfxoEnable = true;
/* First time we enable an external clock we should switch to CMD mode to make sure that
* we only do SCO and not PDA tuning. */
- if ((CMU->HFXOCTRL & (_CMU_HFXOCTRL_MODE_MASK)) == CMU_HFXOCTRL_MODE_EXTCLK)
- {
- CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
- | CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD;
+ if ((CMU->HFXOCTRL & (_CMU_HFXOCTRL_MODE_MASK)) == CMU_HFXOCTRL_MODE_DIGEXTCLK) {
+ setHfxoTuningMode(HFXO_TUNING_MODE_CMD);
}
}
#endif
CMU->OSCENCMD = enBit;
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
/* Always wait for ENS to go high */
- while (!BUS_RegBitRead(&CMU->STATUS, ensBitPos))
- {
+ while (!BUS_RegBitRead(&CMU->STATUS, ensBitPos)) {
}
#endif
/* Wait for clock to become ready after enable */
- if (wait)
- {
- while (!BUS_RegBitRead(&CMU->STATUS, rdyBitPos));
-#if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
- if ((osc == cmuOsc_HFXO) && firstHfxoEnable)
- {
- if ((CMU->HFXOCTRL & _CMU_HFXOCTRL_MODE_MASK) == CMU_HFXOCTRL_MODE_EXTCLK)
- {
+ if (wait) {
+ while (!BUS_RegBitRead(&CMU->STATUS, rdyBitPos)) ;
+#if defined(_SILICON_LABS_32B_SERIES_1)
+ if ((osc == cmuOsc_HFXO) && firstHfxoEnable) {
+ if ((CMU->HFXOCTRL & _CMU_HFXOCTRL_MODE_MASK) == CMU_HFXOCTRL_MODE_DIGEXTCLK) {
+#if defined(CMU_CMD_HFXOSHUNTOPTSTART)
/* External clock mode should only do shunt current optimization. */
CMU_OscillatorTuningOptimize(cmuOsc_HFXO, cmuHFXOTuningMode_ShuntCommand, true);
- }
- else
- {
+#endif
+ } else {
/* Wait for peak detection and shunt current optimization to complete. */
CMU_OscillatorTuningWait(cmuOsc_HFXO, cmuHFXOTuningMode_Auto);
}
@@ -3736,25 +4936,21 @@
/* Restart in CMD mode. */
CMU->OSCENCMD = enBit;
- while (!BUS_RegBitRead(&CMU->STATUS, rdyBitPos));
+ while (!BUS_RegBitRead(&CMU->STATUS, rdyBitPos)) ;
}
#endif
}
- }
- else
- {
+ } else {
CMU->OSCENCMD = disBit;
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
/* Always wait for ENS to go low */
- while (BUS_RegBitRead(&CMU->STATUS, ensBitPos))
- {
+ while (BUS_RegBitRead(&CMU->STATUS, ensBitPos)) {
}
#endif
}
}
-
/***************************************************************************//**
* @brief
* Get oscillator frequency tuning setting.
@@ -3762,7 +4958,9 @@
* @param[in] osc
* Oscillator to get tuning value for, one of:
* @li #cmuOsc_LFRCO
- * @li #cmuOsc_HFRCO
+ * @li #cmuOsc_HFRCO @if _CMU_USHFRCOCTRL_TUNING_MASK
+ * @li #cmuOsc_USHFRCO
+ * @endif
* @li #cmuOsc_AUXHFRCO
* @li #cmuOsc_HFXO if CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE is defined
*
@@ -3773,8 +4971,7 @@
{
uint32_t ret;
- switch (osc)
- {
+ switch (osc) {
case cmuOsc_LFRCO:
ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK)
>> _CMU_LFRCOCTRL_TUNING_SHIFT;
@@ -3785,15 +4982,25 @@
>> _CMU_HFRCOCTRL_TUNING_SHIFT;
break;
+#if defined (_CMU_USHFRCOCTRL_TUNING_MASK)
+ case cmuOsc_USHFRCO:
+ ret = (CMU->USHFRCOCTRL & _CMU_USHFRCOCTRL_TUNING_MASK)
+ >> _CMU_USHFRCOCTRL_TUNING_SHIFT;
+ break;
+#endif
+
case cmuOsc_AUXHFRCO:
ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK)
>> _CMU_AUXHFRCOCTRL_TUNING_SHIFT;
break;
-#if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
+#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
case cmuOsc_HFXO:
- ret = CMU->HFXOTRIMSTATUS & ( _CMU_HFXOTRIMSTATUS_REGISH_MASK
- | _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK);
+ ret = CMU->HFXOTRIMSTATUS & (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK
+#if defined(_CMU_HFXOTRIMSTATUS_REGISH_MASK)
+ | _CMU_HFXOTRIMSTATUS_REGISH_MASK
+#endif
+ );
break;
#endif
@@ -3806,7 +5013,6 @@
return ret;
}
-
/***************************************************************************//**
* @brief
* Set the oscillator frequency tuning control.
@@ -3820,7 +5026,9 @@
* @param[in] osc
* Oscillator to set tuning value for, one of:
* @li #cmuOsc_LFRCO
- * @li #cmuOsc_HFRCO
+ * @li #cmuOsc_HFRCO @if _CMU_USHFRCOCTRL_TUNING_MASK
+ * @li #cmuOsc_USHFRCO
+ * @endif
* @li #cmuOsc_AUXHFRCO
* @li #cmuOsc_HFXO if PEAKDETSHUNTOPTMODE is available. Note that CMD mode is set.
*
@@ -3829,18 +5037,17 @@
******************************************************************************/
void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val)
{
-#if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
+#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK)
uint32_t regIshUpper;
#endif
- switch (osc)
- {
+ switch (osc) {
case cmuOsc_LFRCO:
EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK
>> _CMU_LFRCOCTRL_TUNING_SHIFT));
val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT);
-#if defined( _SILICON_LABS_32B_SERIES_1 )
- while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_LFRCOBSY_SHIFT));
+#if defined(_SILICON_LABS_32B_SERIES_1)
+ while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_LFRCOBSY_SHIFT)) ;
#endif
CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK))
| (val << _CMU_LFRCOCTRL_TUNING_SHIFT);
@@ -3850,29 +5057,41 @@
EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK
>> _CMU_HFRCOCTRL_TUNING_SHIFT));
val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT);
-#if defined( _SILICON_LABS_32B_SERIES_1 )
- while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT))
- {
+#if defined(_SILICON_LABS_32B_SERIES_1)
+ while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT)) {
}
#endif
CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK))
| (val << _CMU_HFRCOCTRL_TUNING_SHIFT);
break;
+#if defined (_CMU_USHFRCOCTRL_TUNING_MASK)
+ case cmuOsc_USHFRCO:
+ EFM_ASSERT(val <= (_CMU_USHFRCOCTRL_TUNING_MASK
+ >> _CMU_USHFRCOCTRL_TUNING_SHIFT));
+ val &= (_CMU_USHFRCOCTRL_TUNING_MASK >> _CMU_USHFRCOCTRL_TUNING_SHIFT);
+#if defined(_SILICON_LABS_32B_SERIES_1)
+ while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_USHFRCOBSY_SHIFT)) {
+ }
+#endif
+ CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~(_CMU_USHFRCOCTRL_TUNING_MASK))
+ | (val << _CMU_USHFRCOCTRL_TUNING_SHIFT);
+ break;
+#endif
+
case cmuOsc_AUXHFRCO:
EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK
>> _CMU_AUXHFRCOCTRL_TUNING_SHIFT));
val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
-#if defined( _SILICON_LABS_32B_SERIES_1 )
- while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT))
- {
+#if defined(_SILICON_LABS_32B_SERIES_1)
+ while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT)) {
}
#endif
CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK))
| (val << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
break;
-#if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
+#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
case cmuOsc_HFXO:
/* Do set PEAKDETSHUNTOPTMODE or HFXOSTEADYSTATECTRL if HFXO is enabled */
@@ -3883,14 +5102,21 @@
CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
| CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD;
+#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK)
regIshUpper = getRegIshUpperVal((val & _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK)
>> _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT);
-
- BUS_RegMaskedWrite(&CMU->HFXOSTEADYSTATECTRL,
- _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
- | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
- | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK,
- val | regIshUpper);
+ CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL
+ & ~(_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
+ | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
+ | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK))
+ | val
+ | regIshUpper;
+#else
+ CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL
+ & ~_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK)
+ | val;
+#endif
+
break;
#endif
@@ -3900,7 +5126,7 @@
}
}
-#if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK )
+#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK)
/***************************************************************************//**
* @brief
* Wait for oscillator tuning optimization.
@@ -3918,48 +5144,48 @@
bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc,
CMU_HFXOTuningMode_TypeDef mode)
{
+ uint32_t waitFlags;
EFM_ASSERT(osc == cmuOsc_HFXO);
- uint32_t waitFlags;
/* Currently implemented for HFXO with PEAKDETSHUNTOPTMODE only */
(void)osc;
- if (BUS_RegMaskedRead(&CMU->HFXOCTRL, _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
- == CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD)
- {
- waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY | CMU_STATUS_HFXOPEAKDETRDY;
- }
- else
- {
+ if (getHfxoTuningMode() == HFXO_TUNING_MODE_AUTO) {
+ waitFlags = HFXO_TUNING_READY_FLAGS;
+ } else {
/* Set wait flags for each command and wait */
- switch (mode)
- {
+ switch (mode) {
+#if defined(_CMU_STATUS_HFXOSHUNTOPTRDY_MASK)
case cmuHFXOTuningMode_ShuntCommand:
waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY;
break;
-
+#endif
case cmuHFXOTuningMode_Auto:
- /* Fall through */
+ waitFlags = HFXO_TUNING_READY_FLAGS;
+ break;
+
+#if defined(CMU_CMD_HFXOSHUNTOPTSTART)
case cmuHFXOTuningMode_PeakShuntCommand:
- waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY | CMU_STATUS_HFXOPEAKDETRDY;
+ waitFlags = HFXO_TUNING_READY_FLAGS;
break;
+#endif
default:
waitFlags = _CMU_STATUS_MASK;
EFM_ASSERT(false);
}
}
- while ((CMU->STATUS & waitFlags) != waitFlags);
-
+ while ((CMU->STATUS & waitFlags) != waitFlags) ;
+
+#if defined(CMU_IF_HFXOPEAKDETERR)
/* Check error flags */
- if (waitFlags & CMU_STATUS_HFXOPEAKDETRDY)
- {
+ if (waitFlags & CMU_STATUS_HFXOPEAKDETRDY) {
return (CMU->IF & CMU_IF_HFXOPEAKDETERR ? true : false);
}
+#endif
return true;
}
-
/***************************************************************************//**
* @brief
* Start and optionally wait for oscillator tuning optimization.
@@ -3983,19 +5209,19 @@
CMU_HFXOTuningMode_TypeDef mode,
bool wait)
{
- switch (osc)
- {
+ switch (osc) {
case cmuOsc_HFXO:
- if (mode)
- {
+ if (mode) {
+#if defined(CMU_IF_HFXOPEAKDETERR)
/* Clear error flag before command write */
CMU->IFC = CMU_IFC_HFXOPEAKDETERR;
+#endif
CMU->CMD = mode;
}
- if (wait)
- {
+ if (wait) {
return CMU_OscillatorTuningWait(osc, mode);
}
+ break;
default:
EFM_ASSERT(false);
@@ -4004,7 +5230,6 @@
}
#endif
-
/**************************************************************************//**
* @brief
* Determine if currently selected PCNTn clock used is external or LFBCLK.
@@ -4020,19 +5245,18 @@
{
uint32_t setting;
- switch (instance)
- {
-#if defined( _CMU_PCNTCTRL_PCNT0CLKEN_MASK )
+ switch (instance) {
+#if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK)
case 0:
setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0;
break;
-#if defined( _CMU_PCNTCTRL_PCNT1CLKEN_MASK )
+#if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK)
case 1:
setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0;
break;
-#if defined( _CMU_PCNTCTRL_PCNT2CLKEN_MASK )
+#if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK)
case 2:
setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0;
break;
@@ -4047,7 +5271,6 @@
return (setting ? true : false);
}
-
/**************************************************************************//**
* @brief
* Select PCNTn clock.
@@ -4060,13 +5283,12 @@
*****************************************************************************/
void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
{
-#if defined( PCNT_PRESENT )
+#if defined(PCNT_PRESENT)
uint32_t setting = 0;
EFM_ASSERT(instance < PCNT_COUNT);
- if (external)
- {
+ if (external) {
setting = 1;
}
@@ -4078,8 +5300,7 @@
#endif
}
-
-#if defined( _CMU_USHFRCOCONF_BAND_MASK )
+#if defined(_CMU_USHFRCOCONF_BAND_MASK)
/***************************************************************************//**
* @brief
* Get USHFRCO band in use.
@@ -4095,7 +5316,7 @@
}
#endif
-#if defined( _CMU_USHFRCOCONF_BAND_MASK )
+#if defined(_CMU_USHFRCOCONF_BAND_MASK)
/***************************************************************************//**
* @brief
* Set USHFRCO band to use.
@@ -4114,14 +5335,14 @@
EFM_ASSERT((CMU_USHFRCOBandGet() != band) && (osc != cmuSelect_USHFRCO));
/* Read tuning value from calibration table */
- switch (band)
- {
+ switch (band) {
case cmuUSHFRCOBand_24MHz:
tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK)
>> _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT;
fineTuning = (DEVINFO->USHFRCOCAL0
& _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK)
>> _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT;
+ ushfrcoFreq = 24000000UL;
break;
case cmuUSHFRCOBand_48MHz:
@@ -4132,6 +5353,7 @@
>> _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT;
/* Enable the clock divider before switching the band from 24 to 48MHz */
BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0);
+ ushfrcoFreq = 48000000UL;
break;
default:
@@ -4148,15 +5370,12 @@
| (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT);
/* Disable the clock divider after switching the band from 48 to 24MHz */
- if (band == cmuUSHFRCOBand_24MHz)
- {
+ if (band == cmuUSHFRCOBand_24MHz) {
BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1);
}
}
#endif
-
-
/** @} (end addtogroup CMU) */
/** @} (end addtogroup emlib) */
#endif /* __EM_CMU_H */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_core.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_core.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_core.c
* @brief Core interrupt handling API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -41,6 +41,7 @@
* @{
******************************************************************************/
+/* *INDENT-OFF* */
/***************************************************************************//**
@addtogroup CORE
@brief Core interrupt handling API
@@ -65,17 +66,16 @@
@li <b>CRITICAL</b> section: Inside a critical sections all interrupts are
disabled (except for fault handlers). The PRIMASK register is always used for
interrupt disable/enable.
- @li <b>ATOMIC</b> section: This type of section is configurable and the default
- method is to use PRIMASK. With BASEPRI configuration, interrupts with priority
- equal to or lower than a given configurable level are disabled. The interrupt
- disable priority level is defined at compile time. The BASEPRI register is not
+ @li <b>ATOMIC</b> section: This type of section is configurable and the default
+ method is to use PRIMASK. With BASEPRI configuration, interrupts with priority
+ equal to or lower than a given configurable level are disabled. The interrupt
+ disable priority level is defined at compile time. The BASEPRI register is not
available for all architectures.
@li <b>NVIC mask</b> section: Disable NVIC (external interrupts) on an
individual manner.
em_core also has an API for manipulating RAM based interrupt vector tables.
-
@n @section core_conf Compile time configuration
The following @htmlonly #defines @endhtmlonly are used to configure em_core:
@@ -101,7 +101,6 @@
devices ATOMIC section helper macros are available but they are
implemented as CRITICAL sections using PRIMASK register.
-
@n @section core_macro_api The macro API
The primary em_core API is the macro API. The macro API will map to correct
@@ -152,7 +151,6 @@
Refer to @em Macros or <em>Macro Definition Documentation</em> below for a
full list of macros.
-
@n @section core_reimplementation API reimplementation
Most of the functions in the API are implemented as weak functions. This means
@@ -187,7 +185,6 @@
#define CORE_INTERRUPT_EXIT() OSIntExit()
@endverbatim
-
@n @section core_vector_tables Interrupt vector tables
When using RAM based interrupt vector tables it is the users responsibility
@@ -227,7 +224,7 @@
@endverbatim
@n @section core_porting Porting from em_int
-
+
Existing code using INT_Enable() and INT_Disable() must be ported to the
em_core API. While em_int used a global counter to store the interrupt state,
em_core uses a local variable. Any usage of INT_Disable() therefore needs to
@@ -259,6 +256,7 @@
@endverbatim
* @{
******************************************************************************/
+/* *INDENT-ON* */
/*******************************************************************************
******************************* DEFINES ***********************************
@@ -295,7 +293,7 @@
// Compile time sanity check.
#if (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_PRIMASK) \
- && (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_BASEPRI)
+ && (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_BASEPRI)
#error "em_core: Undefined ATOMIC IRQ handling strategy."
#endif
@@ -518,7 +516,7 @@
CORE_CRITICAL_SECTION(
*nvicState = *(CORE_nvicMask_t*)&NVIC->ICER[0];
*(CORE_nvicMask_t*)&NVIC->ICER[0] = *disable;
- )
+ )
}
/***************************************************************************//**
@@ -532,7 +530,7 @@
{
CORE_CRITICAL_SECTION(
*(CORE_nvicMask_t*)&NVIC->ICER[0] = *disable;
- )
+ )
}
/***************************************************************************//**
@@ -546,7 +544,7 @@
{
CORE_CRITICAL_SECTION(
*(CORE_nvicMask_t*)&NVIC->ISER[0] = *enable;
- )
+ )
}
/***************************************************************************//**
@@ -567,7 +565,7 @@
// Get current NVIC enable mask.
CORE_CRITICAL_SECTION(
nvicMask = *(CORE_nvicMask_t*)&NVIC->ISER[0];
- )
+ )
// Make a mask with bits set for those interrupts that are currently
// disabled but are set in the enable mask.
@@ -576,7 +574,6 @@
nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0];
if (nvicMask.a[0] != 0) {
-
#elif (CORE_NVIC_REG_WORDS == 2)
nvicMask.a[0] &= enable->a[0];
nvicMask.a[1] &= enable->a[1];
@@ -584,7 +581,6 @@
nvicMask.a[1] = ~nvicMask.a[1] & enable->a[1];
if ((nvicMask.a[0] != 0) || (nvicMask.a[1] != 0)) {
-
#elif (CORE_NVIC_REG_WORDS == 3)
nvicMask.a[0] &= enable->a[0];
nvicMask.a[1] &= enable->a[1];
@@ -729,7 +725,7 @@
{
CORE_CRITICAL_SECTION(
*mask = *(CORE_nvicMask_t*)&NVIC->ISER[0];
- )
+ )
}
/***************************************************************************//**
@@ -748,8 +744,7 @@
CORE_CRITICAL_SECTION(
nvicMask = *(CORE_nvicMask_t*)&NVIC->ISER[0];
- )
-
+ )
#if (CORE_NVIC_REG_WORDS == 1)
return (mask->a[0] & nvicMask.a[0]) == 0;
@@ -800,7 +795,7 @@
void *CORE_GetNvicRamTableHandler(IRQn_Type irqN)
{
EFM_ASSERT((irqN >= -16) && (irqN < EXT_IRQ_COUNT));
- return (void*)(((uint32_t*)SCB->VTOR)[irqN+16]);
+ return (void*)(((uint32_t*)SCB->VTOR)[irqN + 16]);
}
/***************************************************************************//**
@@ -819,7 +814,7 @@
void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler)
{
EFM_ASSERT((irqN >= -16) && (irqN < EXT_IRQ_COUNT));
- ((uint32_t*)SCB->VTOR)[irqN+16] = (uint32_t)handler;
+ ((uint32_t*)SCB->VTOR)[irqN + 16] = (uint32_t)handler;
}
/***************************************************************************//**
@@ -879,15 +874,15 @@
EFM_ASSERT(((uint32_t)targetTable
& ((1 << (32 - __CLZ((targetSize * 4) - 1))) - 1)) == 0);
- for (i=0; i<targetSize; i++) {
+ for (i = 0; i < targetSize; i++) {
if (overwriteActive) { // Overwrite target entries ?
- if (i<sourceSize) { // targetSize <= sourceSize
+ if (i < sourceSize) { // targetSize <= sourceSize
targetTable[i] = sourceTable[i];
} else { // targetSize > sourceSize
targetTable[i] = (uint32_t)defaultHandler;
}
} else { // Overwrite target entries which are 0
- if (i<sourceSize) { // targetSize <= sourceSize
+ if (i < sourceSize) { // targetSize <= sourceSize
if (targetTable[i] == 0) {
targetTable[i] = sourceTable[i];
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_cryotimer.c
* @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -52,9 +52,9 @@
{
CRYOTIMER->PERIODSEL = (uint32_t)init->period & _CRYOTIMER_PERIODSEL_MASK;
CRYOTIMER->CTRL = ((uint32_t)init->enable << _CRYOTIMER_CTRL_EN_SHIFT)
- | ((uint32_t)init->debugRun << _CRYOTIMER_CTRL_DEBUGRUN_SHIFT)
- | ((uint32_t)init->osc << _CRYOTIMER_CTRL_OSCSEL_SHIFT)
- | ((uint32_t)init->presc << _CRYOTIMER_CTRL_PRESC_SHIFT);
+ | ((uint32_t)init->debugRun << _CRYOTIMER_CTRL_DEBUGRUN_SHIFT)
+ | ((uint32_t)init->osc << _CRYOTIMER_CTRL_OSCSEL_SHIFT)
+ | ((uint32_t)init->presc << _CRYOTIMER_CTRL_PRESC_SHIFT);
CRYOTIMER_EM4WakeupEnable(init->em4Wakeup);
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_crypto.c
* @brief Cryptography accelerator peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -54,24 +54,24 @@
#define CRYPTO_INSTRUCTIONS_PER_REG (4)
#define CRYPTO_INSTRUCTIONS_MAX (12)
-#define CRYPTO_INSTRUCTION_REGS (CRYPTO_INSTRUCTIONS_MAX/CRYPTO_INSTRUCTIONS_PER_REG)
+#define CRYPTO_INSTRUCTION_REGS (CRYPTO_INSTRUCTIONS_MAX / CRYPTO_INSTRUCTIONS_PER_REG)
#define CRYPTO_SHA1_BLOCK_SIZE_IN_BITS (512)
-#define CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES (CRYPTO_SHA1_BLOCK_SIZE_IN_BITS/8)
-#define CRYPTO_SHA1_BLOCK_SIZE_IN_32BIT_WORDS (CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES/sizeof(uint32_t))
-#define CRYPTO_SHA1_DIGEST_SIZE_IN_32BIT_WORDS (CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES/sizeof(uint32_t))
+#define CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES (CRYPTO_SHA1_BLOCK_SIZE_IN_BITS / 8)
+#define CRYPTO_SHA1_BLOCK_SIZE_IN_32BIT_WORDS (CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES / sizeof(uint32_t))
+#define CRYPTO_SHA1_DIGEST_SIZE_IN_32BIT_WORDS (CRYPTO_SHA1_DIGEST_SIZE_IN_BYTES / sizeof(uint32_t))
#define CRYPTO_SHA256_BLOCK_SIZE_IN_BITS (512)
-#define CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES (CRYPTO_SHA256_BLOCK_SIZE_IN_BITS/8)
-#define CRYPTO_SHA256_BLOCK_SIZE_IN_32BIT_WORDS (CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES/sizeof(uint32_t))
+#define CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES (CRYPTO_SHA256_BLOCK_SIZE_IN_BITS / 8)
+#define CRYPTO_SHA256_BLOCK_SIZE_IN_32BIT_WORDS (CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES / sizeof(uint32_t))
-#define CRYPTO_SHA256_DIGEST_SIZE_IN_32BIT_WORDS (CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES/sizeof(uint32_t))
+#define CRYPTO_SHA256_DIGEST_SIZE_IN_32BIT_WORDS (CRYPTO_SHA256_DIGEST_SIZE_IN_BYTES / sizeof(uint32_t))
#define PARTIAL_OPERAND_WIDTH_LOG2 (7) /* 2^7 = 128 */
-#define PARTIAL_OPERAND_WIDTH (1<<PARTIAL_OPERAND_WIDTH_LOG2)
-#define PARTIAL_OPERAND_WIDTH_MASK (PARTIAL_OPERAND_WIDTH-1)
-#define PARTIAL_OPERAND_WIDTH_IN_BYTES (PARTIAL_OPERAND_WIDTH/8)
-#define PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS (PARTIAL_OPERAND_WIDTH_IN_BYTES/sizeof(uint32_t))
+#define PARTIAL_OPERAND_WIDTH (1 << PARTIAL_OPERAND_WIDTH_LOG2)
+#define PARTIAL_OPERAND_WIDTH_MASK (PARTIAL_OPERAND_WIDTH - 1)
+#define PARTIAL_OPERAND_WIDTH_IN_BYTES (PARTIAL_OPERAND_WIDTH / 8)
+#define PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS (PARTIAL_OPERAND_WIDTH_IN_BYTES / sizeof(uint32_t))
#define SWAP32(x) (__REV(x))
@@ -152,16 +152,15 @@
int i;
volatile uint32_t * reg = (volatile uint32_t *) dataReg;
- if (valSize < 4)
- {
+ if (valSize < 4) {
/* Non optimal write of data. */
- for (i = 0; i < valSize; i++)
+ for (i = 0; i < valSize; i++) {
*reg = *val++;
- for (; i < 4; i++)
+ }
+ for (; i < 4; i++) {
*reg = 0;
- }
- else
- {
+ }
+ } else {
CRYPTO_BurstToCrypto(reg, &val[0]);
}
}
@@ -192,8 +191,7 @@
{
uint32_t temp = crypto->WAC & (~(_CRYPTO_WAC_MODULUS_MASK | _CRYPTO_WAC_MODOP_MASK));
- switch (modulusId)
- {
+ switch (modulusId) {
case cryptoModulusBin256:
case cryptoModulusBin128:
case cryptoModulusGcmBin128:
@@ -248,8 +246,7 @@
EFM_ASSERT(val);
CRYPTO_BurstFromCrypto(&crypto->KEY, &val[0]);
- if (keyWidth == cryptoKey256Bits)
- {
+ if (keyWidth == cryptoKey256Bits) {
CRYPTO_BurstFromCrypto(&crypto->KEY, &val[4]);
}
}
@@ -282,7 +279,7 @@
uint32_t temp;
uint32_t len;
int blockLen;
- uint32_t shaBlock[CRYPTO_SHA1_BLOCK_SIZE_IN_32BIT_WORDS]=
+ uint32_t shaBlock[CRYPTO_SHA1_BLOCK_SIZE_IN_32BIT_WORDS] =
{
/* Initial value */
0x67452301, 0xefcdab89, 0x98badcfe, 0x10325476, 0xc3d2e1f0
@@ -307,8 +304,7 @@
len = msgLen;
- while (len >= CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES)
- {
+ while (len >= CRYPTO_SHA1_BLOCK_SIZE_IN_BYTES) {
/* Write block to QDATA1. */
CRYPTO_QDataWrite(&crypto->QDATA1BIG, (uint32_t *) msg);
@@ -325,8 +321,9 @@
blockLen = 0;
/* Build the last (or second to last) block */
- for (; len; len--)
+ for (; len; len--) {
p8ShaBlock[blockLen++] = *msg++;
+ }
/* append the '1' bit */
p8ShaBlock[blockLen++] = 0x80;
@@ -335,8 +332,7 @@
* then compress. Then we can fall back to padding zeros and length
* encoding like normal.
*/
- if (blockLen > 56)
- {
+ if (blockLen > 56) {
while (blockLen < 64)
p8ShaBlock[blockLen++] = 0;
@@ -412,7 +408,7 @@
uint32_t temp;
uint32_t len;
int blockLen;
- uint32_t shaBlock[CRYPTO_SHA256_BLOCK_SIZE_IN_32BIT_WORDS]=
+ uint32_t shaBlock[CRYPTO_SHA256_BLOCK_SIZE_IN_32BIT_WORDS] =
{
/* Initial value */
0x6a09e667, 0xbb67ae85, 0x3c6ef372, 0xa54ff53a,
@@ -437,8 +433,7 @@
CRYPTO_CMD_INSTR_SELDDATA0DDATA1);
len = msgLen;
- while (len >= CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES)
- {
+ while (len >= CRYPTO_SHA256_BLOCK_SIZE_IN_BYTES) {
/* Write block to QDATA1BIG. */
CRYPTO_QDataWrite(&crypto->QDATA1BIG, (uint32_t *) msg);
@@ -455,8 +450,9 @@
blockLen = 0;
/* Build the last (or second to last) block */
- for (; len; len--)
+ for (; len; len--) {
p8ShaBlock[blockLen++] = *msg++;
+ }
/* append the '1' bit */
p8ShaBlock[blockLen++] = 0x80;
@@ -465,8 +461,7 @@
* then compress. Then we can fall back to padding zeros and length
* encoding like normal.
*/
- if (blockLen > 56)
- {
+ if (blockLen > 56) {
while (blockLen < 64)
p8ShaBlock[blockLen++] = 0;
@@ -532,9 +527,11 @@
int num32bitWords)
{
int i;
- for (i=0; i<num32bitWords; i++)
- if (++words32bits[i] != 0)
+ for (i = 0; i < num32bitWords; i++) {
+ if (++words32bits[i] != 0) {
break;
+ }
+ }
return;
}
@@ -565,18 +562,18 @@
/**************** Initializations ******************/
#ifdef USE_VARIABLE_SIZED_DATA_LOADS
- int numWordsLastOperandA = (aSize&PARTIAL_OPERAND_WIDTH_MASK)>>5;
- int numPartialOperandsA = numWordsLastOperandA ?
- (aSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1 :
- aSize >> PARTIAL_OPERAND_WIDTH_LOG2;
- int numWordsLastOperandB = (bSize&PARTIAL_OPERAND_WIDTH_MASK)>>5;
- int numPartialOperandsB = numWordsLastOperandB ?
- (bSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1 :
- bSize >> PARTIAL_OPERAND_WIDTH_LOG2;
- int numWordsLastOperandR = (rSize&PARTIAL_OPERAND_WIDTH_MASK)>>5;
- int numPartialOperandsR = numWordsLastOperandR ?
- (rSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1 :
- rSize >> PARTIAL_OPERAND_WIDTH_LOG2;
+ int numWordsLastOperandA = (aSize & PARTIAL_OPERAND_WIDTH_MASK) >> 5;
+ int numPartialOperandsA = numWordsLastOperandA
+ ? (aSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1
+ : aSize >> PARTIAL_OPERAND_WIDTH_LOG2;
+ int numWordsLastOperandB = (bSize & PARTIAL_OPERAND_WIDTH_MASK) >> 5;
+ int numPartialOperandsB = numWordsLastOperandB
+ ? (bSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1
+ : bSize >> PARTIAL_OPERAND_WIDTH_LOG2;
+ int numWordsLastOperandR = (rSize & PARTIAL_OPERAND_WIDTH_MASK) >> 5;
+ int numPartialOperandsR = numWordsLastOperandR
+ ? (rSize >> PARTIAL_OPERAND_WIDTH_LOG2) + 1
+ : rSize >> PARTIAL_OPERAND_WIDTH_LOG2;
EFM_ASSERT(numPartialOperandsA + numPartialOperandsB <= numPartialOperandsR);
#else
int numPartialOperandsA = aSize >> PARTIAL_OPERAND_WIDTH_LOG2;
@@ -597,8 +594,8 @@
can take place immediately when CRYPTO is ready inside the instruction
sequence. */
crypto->CTRL =
- CRYPTO_CTRL_DMA0RSEL_DATA0 | CRYPTO_CTRL_DMA0MODE_FULL |
- CRYPTO_CTRL_DMA1RSEL_DATA1 | CRYPTO_CTRL_DMA1MODE_FULL;
+ CRYPTO_CTRL_DMA0RSEL_DATA0 | CRYPTO_CTRL_DMA0MODE_FULL
+ | CRYPTO_CTRL_DMA1RSEL_DATA1 | CRYPTO_CTRL_DMA1MODE_FULL;
CRYPTO_EXECUTE_4(crypto,
CRYPTO_CMD_INSTR_CCLR, /* Carry = 0 */
@@ -607,12 +604,12 @@
CRYPTO_CMD_INSTR_DDATA0TODDATA2,
CRYPTO_CMD_INSTR_SELDDATA1DDATA3);
/*
- register map:
- DDATA0: working register
- DDATA1: B(j)
- DDATA2: R(i+j+1) and R(i+j), combined with DMA entry for B(j)
- DDATA3: A(i)
- */
+ register map:
+ DDATA0: working register
+ DDATA1: B(j)
+ DDATA2: R(i+j+1) and R(i+j), combined with DMA entry for B(j)
+ DDATA3: A(i)
+ */
CRYPTO_SEQ_LOAD_10(crypto,
/* Temporarily load partial operand B(j) to DATA0. */
@@ -645,30 +642,31 @@
/**************** End Initializations ******************/
- for(i=0; i<numPartialOperandsA; i++)
- {
+ for (i = 0; i < numPartialOperandsA; i++) {
/* Load partial operand #1 A>>(i*PARTIAL_OPERAND_WIDTH) to DDATA1. */
#ifdef USE_VARIABLE_SIZED_DATA_LOADS
- if ( (numWordsLastOperandA != 0) && ( i == numPartialOperandsA-1 ) )
+ if ( (numWordsLastOperandA != 0) && (i == numPartialOperandsA - 1) ) {
CRYPTO_DataWriteVariableSize(&crypto->DATA2,
- &A[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
+ &A[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
numWordsLastOperandA);
- else
- CRYPTO_DataWrite(&crypto->DATA2, &A[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+ } else {
+ CRYPTO_DataWrite(&crypto->DATA2, &A[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+ }
#else
- CRYPTO_DataWrite(&crypto->DATA2, &A[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+ CRYPTO_DataWrite(&crypto->DATA2, &A[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
#endif
/* Load partial result in R>>(i*PARTIAL_OPERAND_WIDTH) to DATA1. */
#ifdef USE_VARIABLE_SIZED_DATA_LOADS
- if ( (numWordsLastOperandR != 0) && ( i == numPartialOperandsR-1 ) )
+ if ( (numWordsLastOperandR != 0) && (i == numPartialOperandsR - 1) ) {
CRYPTO_DataWriteVariableSize(&crypto->DATA1,
- &R[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
+ &R[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
numWordsLastOperandR);
- else
- CRYPTO_DataWrite(&crypto->DATA1, &R[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+ } else {
+ CRYPTO_DataWrite(&crypto->DATA1, &R[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+ }
#else
- CRYPTO_DataWrite(&crypto->DATA1, &R[i*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+ CRYPTO_DataWrite(&crypto->DATA1, &R[i * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
#endif
/* Clear carry */
@@ -676,59 +674,59 @@
/* Setup number of sequence iterations and block size. */
crypto->SEQCTRL = CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES
- | (PARTIAL_OPERAND_WIDTH_IN_BYTES * numPartialOperandsB);
+ | (PARTIAL_OPERAND_WIDTH_IN_BYTES * numPartialOperandsB);
/* Execute the MULtiply instruction sequence. */
CRYPTO_InstructionSequenceExecute(crypto);
- for (j=0; j<numPartialOperandsB; j++)
- {
+ for (j = 0; j < numPartialOperandsB; j++) {
/* Load partial operand 2 B>>(j*`PARTIAL_OPERAND_WIDTH) to DDATA2
(via DATA0). */
#ifdef USE_VARIABLE_SIZED_DATA_LOADS
- if ( (numWordsLastOperandB != 0) && ( j == numPartialOperandsB-1 ) )
+ if ( (numWordsLastOperandB != 0) && (j == numPartialOperandsB - 1) ) {
CRYPTO_DataWriteVariableSize(&crypto->DATA0,
- &B[j*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
+ &B[j * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
numWordsLastOperandB);
- else
+ } else {
CRYPTO_DataWrite(&crypto->DATA0,
- &B[j*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+ &B[j * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+ }
#else
CRYPTO_DataWrite(&crypto->DATA0,
- &B[j*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+ &B[j * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
#endif
/* Load most significant partial result
R>>((i+j+1)*`PARTIAL_OPERAND_WIDTH) into DATA1. */
#ifdef USE_VARIABLE_SIZED_DATA_LOADS
- if ( (numWordsLastOperandR != 0) && ( (i+j+1) == numPartialOperandsR-1 ) )
+ if ( (numWordsLastOperandR != 0) && ( (i + j + 1) == numPartialOperandsR - 1) ) {
CRYPTO_DataWriteVariableSize(&crypto->DATA1,
- &R[(i+j+1)*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
+ &R[(i + j + 1) * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
numWordsLastOperandR);
- else
+ } else {
CRYPTO_DataWrite(&crypto->DATA1,
- &R[(i+j+1)*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+ &R[(i + j + 1) * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+ }
#else
CRYPTO_DataWrite(&crypto->DATA1,
- &R[(i+j+1)*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
+ &R[(i + j + 1) * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
#endif
/* Store least significant partial result */
CRYPTO_DataRead(&crypto->DATA0,
- &R[(i+j)*PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
-
+ &R[(i + j) * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
} /* for (j=0; j<numPartialOperandsB; j++) */
/* Handle carry at the end of the inner loop. */
- if (CRYPTO_CarryIsSet(crypto))
- cryptoBigintIncrement(&R[(i+numPartialOperandsB+1)
- *PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
- (numPartialOperandsA-i-1)
- *PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS);
+ if (CRYPTO_CarryIsSet(crypto)) {
+ cryptoBigintIncrement(&R[(i + numPartialOperandsB + 1)
+ * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS],
+ (numPartialOperandsA - i - 1)
+ * PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS);
+ }
CRYPTO_DataRead(&crypto->DATA1,
- &R[(i+numPartialOperandsB)
+ &R[(i + numPartialOperandsB)
* PARTIAL_OPERAND_WIDTH_IN_32BIT_WORDS]);
-
} /* for (i=0; i<numPartialOperandsA; i++) */
}
@@ -1141,7 +1139,7 @@
/* Setup CRYPTO in AES-128 mode. */
crypto->CTRL = CRYPTO_CTRL_AES_AES128;
-
+
/* Load key */
CRYPTO_BurstToCrypto(&crypto->KEYBUF, &_in[0]);
@@ -1179,7 +1177,7 @@
/* Setup CRYPTO in AES-256 mode. */
crypto->CTRL = CRYPTO_CTRL_AES_AES256;
-
+
/* Load key */
CRYPTO_BurstToCrypto(&crypto->KEYBUF, &_in[0]);
CRYPTO_BurstToCrypto(&crypto->KEYBUF, &_in[4]);
@@ -1466,27 +1464,22 @@
CRYPTO_KeyBufWrite(crypto, (uint32_t *)key, keyWidth);
- if (encrypt)
- {
+ if (encrypt) {
CRYPTO_DataWrite(&crypto->DATA0, (uint32_t *)iv);
- crypto->SEQ0 =
- CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR0_SHIFT |
- CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR1_SHIFT;
+ crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR0_SHIFT
+ | CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR1_SHIFT;
CRYPTO_AES_ProcessLoop(crypto, len,
&crypto->DATA1, (uint32_t *) in,
&crypto->DATA0, (uint32_t *) out);
- }
- else
- {
+ } else {
CRYPTO_DataWrite(&crypto->DATA2, (uint32_t *) iv);
- crypto->SEQ0 =
- CRYPTO_CMD_INSTR_DATA1TODATA0 << _CRYPTO_SEQ0_INSTR0_SHIFT |
- CRYPTO_CMD_INSTR_AESDEC << _CRYPTO_SEQ0_INSTR1_SHIFT |
- CRYPTO_CMD_INSTR_DATA2TODATA0XOR << _CRYPTO_SEQ0_INSTR2_SHIFT |
- CRYPTO_CMD_INSTR_DATA1TODATA2 << _CRYPTO_SEQ0_INSTR3_SHIFT;
+ crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA1TODATA0 << _CRYPTO_SEQ0_INSTR0_SHIFT
+ | CRYPTO_CMD_INSTR_AESDEC << _CRYPTO_SEQ0_INSTR1_SHIFT
+ | CRYPTO_CMD_INSTR_DATA2TODATA0XOR << _CRYPTO_SEQ0_INSTR2_SHIFT
+ | CRYPTO_CMD_INSTR_DATA1TODATA2 << _CRYPTO_SEQ0_INSTR3_SHIFT;
crypto->SEQ1 = 0;
@@ -1552,30 +1545,25 @@
CRYPTO_KeyBufWrite(crypto, (uint32_t *)key, keyWidth);
/* Load instructions to CRYPTO sequencer. */
- if (encrypt)
- {
+ if (encrypt) {
/* Load IV */
CRYPTO_DataWrite(&crypto->DATA0, (uint32_t *)iv);
- crypto->SEQ0 =
- CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR0_SHIFT |
- CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR1_SHIFT;
+ crypto->SEQ0 = CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR0_SHIFT
+ | CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR1_SHIFT;
CRYPTO_AES_ProcessLoop(crypto, len,
&crypto->DATA1, (uint32_t *)in,
&crypto->DATA0, (uint32_t *)out
);
- }
- else
- {
+ } else {
/* Load IV */
CRYPTO_DataWrite(&crypto->DATA2, (uint32_t *)iv);
- crypto->SEQ0 =
- CRYPTO_CMD_INSTR_DATA2TODATA0 << _CRYPTO_SEQ0_INSTR0_SHIFT |
- CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR1_SHIFT |
- CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR2_SHIFT |
- CRYPTO_CMD_INSTR_DATA1TODATA2 << _CRYPTO_SEQ0_INSTR3_SHIFT;
+ crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA2TODATA0 << _CRYPTO_SEQ0_INSTR0_SHIFT
+ | CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR1_SHIFT
+ | CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ0_INSTR2_SHIFT
+ | CRYPTO_CMD_INSTR_DATA1TODATA2 << _CRYPTO_SEQ0_INSTR3_SHIFT;
crypto->SEQ1 = 0;
CRYPTO_AES_ProcessLoop(crypto, len,
@@ -1643,10 +1631,10 @@
CRYPTO_DataWrite(&crypto->DATA1, (uint32_t *) ctr);
- crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA1TODATA0 << _CRYPTO_SEQ0_INSTR0_SHIFT |
- CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR1_SHIFT |
- CRYPTO_CMD_INSTR_DATA0TODATA3 << _CRYPTO_SEQ0_INSTR2_SHIFT |
- CRYPTO_CMD_INSTR_DATA1INC << _CRYPTO_SEQ0_INSTR3_SHIFT;
+ crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA1TODATA0 << _CRYPTO_SEQ0_INSTR0_SHIFT
+ | CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR1_SHIFT
+ | CRYPTO_CMD_INSTR_DATA0TODATA3 << _CRYPTO_SEQ0_INSTR2_SHIFT
+ | CRYPTO_CMD_INSTR_DATA1INC << _CRYPTO_SEQ0_INSTR3_SHIFT;
crypto->SEQ1 = CRYPTO_CMD_INSTR_DATA2TODATA0XOR << _CRYPTO_SEQ1_INSTR4_SHIFT;
@@ -1704,17 +1692,12 @@
CRYPTO_KeyBufWrite(crypto, (uint32_t *)key, keyWidth);
- if (encrypt)
- {
- crypto->SEQ0 =
- (CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR0_SHIFT |
- CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR1_SHIFT);
- }
- else
- {
- crypto->SEQ0 =
- (CRYPTO_CMD_INSTR_AESDEC << _CRYPTO_SEQ0_INSTR0_SHIFT |
- CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR1_SHIFT);
+ if (encrypt) {
+ crypto->SEQ0 = CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR0_SHIFT
+ | CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR1_SHIFT;
+ } else {
+ crypto->SEQ0 = CRYPTO_CMD_INSTR_AESDEC << _CRYPTO_SEQ0_INSTR0_SHIFT
+ | CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR1_SHIFT;
}
CRYPTO_AES_ProcessLoop(crypto, len,
@@ -1769,14 +1752,12 @@
CRYPTO_DataWrite(&crypto->DATA2, (uint32_t *)iv);
- crypto->SEQ0 =
- CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR0_SHIFT |
- CRYPTO_CMD_INSTR_DATA2TODATA0 << _CRYPTO_SEQ0_INSTR1_SHIFT |
- CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR2_SHIFT |
- CRYPTO_CMD_INSTR_DATA0TODATA2 << _CRYPTO_SEQ0_INSTR3_SHIFT;
- crypto->SEQ1 =
- CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ1_INSTR4_SHIFT |
- CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ1_INSTR5_SHIFT;
+ crypto->SEQ0 = CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ0_INSTR0_SHIFT
+ | CRYPTO_CMD_INSTR_DATA2TODATA0 << _CRYPTO_SEQ0_INSTR1_SHIFT
+ | CRYPTO_CMD_INSTR_AESENC << _CRYPTO_SEQ0_INSTR2_SHIFT
+ | CRYPTO_CMD_INSTR_DATA0TODATA2 << _CRYPTO_SEQ0_INSTR3_SHIFT;
+ crypto->SEQ1 = CRYPTO_CMD_INSTR_DATA1TODATA0XOR << _CRYPTO_SEQ1_INSTR4_SHIFT
+ | CRYPTO_CMD_INSTR_DATA0TODATA1 << _CRYPTO_SEQ1_INSTR5_SHIFT;
CRYPTO_AES_ProcessLoop(crypto, len,
&crypto->DATA0, (uint32_t *) in,
@@ -1821,8 +1802,7 @@
len /= CRYPTO_AES_BLOCKSIZE;
crypto->SEQCTRL = 16 << _CRYPTO_SEQCTRL_LENGTHA_SHIFT;
- while (len--)
- {
+ while (len--) {
/* Load data and trigger encryption */
CRYPTO_DataWrite(inReg, (uint32_t *)in);
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_csen.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_csen.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_csen.c
* @brief Capacitive Sense Module (CSEN) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -31,7 +31,7 @@
******************************************************************************/
#include "em_csen.h"
-#if defined( CSEN_COUNT ) && ( CSEN_COUNT > 0 )
+#if defined(CSEN_COUNT) && (CSEN_COUNT > 0)
#include "em_assert.h"
#include "em_cmu.h"
@@ -68,8 +68,8 @@
*
* @details
* Sets the initial value of the integrator(s) for the Delta Modulation (DM)
- * converter. The initial value for the ramp-down integrator has no effect
- * if low frequency attenuation was not selected by the mode initialization
+ * converter. The initial value for the ramp-down integrator has no effect
+ * if low frequency attenuation was not selected by the mode initialization
* function @ref CSEN_InitMode().
*
* @note
@@ -82,7 +82,7 @@
* Initial value for the ramp-up integrator.
*
* @param[in] down
- * Initial value for the ramp-down integrator. Has no effect if low frequency
+ * Initial value for the ramp-down integrator. Has no effect if low frequency
* attenuation is not configured.
******************************************************************************/
void CSEN_DMBaselineSet(CSEN_TypeDef *csen, uint32_t up, uint32_t down)
@@ -94,7 +94,6 @@
| (down << _CSEN_DMBASELINE_BASELINEDN_SHIFT);
}
-
/***************************************************************************//**
* @brief
* Initialize CSEN.
@@ -122,18 +121,15 @@
/* Initialize CTRL. This will stop any conversion in progress. */
tmp = CSEN_CTRL_STM_DEFAULT;
- if (init->cpAccuracyHi)
- {
+ if (init->cpAccuracyHi) {
tmp |= CSEN_CTRL_CPACCURACY_HI;
}
- if (init->localSense)
- {
+ if (init->localSense) {
tmp |= _CSEN_CTRL_LOCALSENS_MASK;
}
- if (init->keepWarm)
- {
+ if (init->keepWarm) {
tmp |= CSEN_CTRL_WARMUPMODE_KEEPCSENWARM;
}
@@ -160,18 +156,17 @@
| (init->input56To63 << _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT);
}
-
/***************************************************************************//**
* @brief
* Initialize a CSEN measurement mode.
*
* @details
- * Used to configure any type of measurement mode. After the measurement
- * has been configured, calling @ref CSEN_Enable() will enable CSEN and
- * allow it to start a conversion from the selected trigger source. To
- * manually start a conversion use @ref CSEN_Start(). To check if a
+ * Used to configure any type of measurement mode. After the measurement
+ * has been configured, calling @ref CSEN_Enable() will enable CSEN and
+ * allow it to start a conversion from the selected trigger source. To
+ * manually start a conversion use @ref CSEN_Start(). To check if a
* conversion is in progress use @ref CSEN_IsBusy(), or alternatively
- * use the interrupt flags returned by @ref CSEN_IntGet() to detect when
+ * use the interrupt flags returned by @ref CSEN_IntGet() to detect when
* a conversion is completed.
*
* @note
@@ -191,36 +186,33 @@
EFM_ASSERT(init->dmIterPerCycle < 0x10);
EFM_ASSERT(init->dmCycles < 0x10);
- /* Initialize CTRL. This will stop any conversion in progress.
- * These composite inputs set multiple fields. They do not need
+ /* Initialize CTRL. This will stop any conversion in progress.
+ * These composite inputs set multiple fields. They do not need
* to be shifted. */
tmp = ((uint32_t)init->sampleMode
- | (uint32_t)init->convSel
- | (uint32_t)init->cmpMode);
+ | (uint32_t)init->convSel
+ | (uint32_t)init->cmpMode);
tmp |= (init->trigSel << _CSEN_CTRL_STM_SHIFT)
| (init->accMode << _CSEN_CTRL_ACU_SHIFT)
| (init->sarRes << _CSEN_CTRL_SARCR_SHIFT);
- if (init->enableDma)
- {
+ if (init->enableDma) {
tmp |= CSEN_CTRL_DMAEN_ENABLE;
}
- if (init->sumOnly)
- {
+ if (init->sumOnly) {
tmp |= CSEN_CTRL_DRSF_ENABLE;
}
- if (init->autoGnd)
- {
+ if (init->autoGnd) {
tmp |= CSEN_CTRL_AUTOGND_ENABLE;
}
/* Preserve the fields that were initialized by CSEN_Init(). */
tmp |= csen->CTRL & (_CSEN_CTRL_CPACCURACY_MASK
- | _CSEN_CTRL_LOCALSENS_MASK
- | _CSEN_CTRL_WARMUPMODE_MASK);
+ | _CSEN_CTRL_LOCALSENS_MASK
+ | _CSEN_CTRL_WARMUPMODE_MASK);
csen->CTRL = tmp;
@@ -243,8 +235,7 @@
| (init->dmIterPerCycle << _CSEN_DMCFG_DMR_SHIFT)
| (init->dmDelta << _CSEN_DMCFG_DMG_SHIFT);
- if (init->dmFixedDelta)
- {
+ if (init->dmFixedDelta) {
tmp |= CSEN_DMCFG_DMGRDIS;
}
@@ -256,7 +247,6 @@
| (init->gainSel << _CSEN_ANACTRL_IREFPROG_SHIFT);
}
-
/***************************************************************************//**
* @brief
* Reset CSEN to same state as after a HW reset.
@@ -288,7 +278,6 @@
csen->IFC = _CSEN_IF_MASK;
}
-
/** @} (end addtogroup CSEN) */
/** @} (end addtogroup emlib) */
#endif /* defined(CSEN_COUNT) && (CSEN_COUNT > 0) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_dac.c
* @brief Digital to Analog Converter (DAC) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -90,19 +90,15 @@
EFM_ASSERT(DAC_REF_VALID(dac));
EFM_ASSERT(DAC_CH_VALID(ch));
- if (!ch)
- {
+ if (!ch) {
reg = &(dac->CH0CTRL);
- }
- else
- {
+ } else {
reg = &(dac->CH1CTRL);
}
BUS_RegBitWrite(reg, _DAC_CH0CTRL_EN_SHIFT, enable);
}
-
/***************************************************************************//**
* @brief
* Initialize DAC.
@@ -131,8 +127,7 @@
BUS_RegBitWrite(&(dac->CH1CTRL), _DAC_CH0CTRL_EN_SHIFT, 0);
/* Load proper calibration data depending on selected reference */
- switch (init->reference)
- {
+ switch (init->reference) {
case dacRef2V5:
dac->CAL = DEVINFO->DAC0CAL1;
break;
@@ -153,30 +148,25 @@
| ((uint32_t)(init->outMode) << _DAC_CTRL_OUTMODE_SHIFT)
| ((uint32_t)(init->convMode) << _DAC_CTRL_CONVMODE_SHIFT);
- if (init->ch0ResetPre)
- {
+ if (init->ch0ResetPre) {
tmp |= DAC_CTRL_CH0PRESCRST;
}
- if (init->outEnablePRS)
- {
+ if (init->outEnablePRS) {
tmp |= DAC_CTRL_OUTENPRS;
}
- if (init->sineEnable)
- {
+ if (init->sineEnable) {
tmp |= DAC_CTRL_SINEMODE;
}
- if (init->diff)
- {
+ if (init->diff) {
tmp |= DAC_CTRL_DIFF;
}
dac->CTRL = tmp;
}
-
/***************************************************************************//**
* @brief
* Initialize DAC channel.
@@ -201,32 +191,25 @@
tmp = (uint32_t)(init->prsSel) << _DAC_CH0CTRL_PRSSEL_SHIFT;
- if (init->enable)
- {
+ if (init->enable) {
tmp |= DAC_CH0CTRL_EN;
}
- if (init->prsEnable)
- {
+ if (init->prsEnable) {
tmp |= DAC_CH0CTRL_PRSEN;
}
- if (init->refreshEnable)
- {
+ if (init->refreshEnable) {
tmp |= DAC_CH0CTRL_REFREN;
}
- if (ch)
- {
+ if (ch) {
dac->CH1CTRL = tmp;
- }
- else
- {
+ } else {
dac->CH0CTRL = tmp;
}
}
-
/***************************************************************************//**
* @brief
* Set the output signal of a DAC channel to a given value.
@@ -244,12 +227,11 @@
* @param[in] value
* Value to write to the channel output register CHnDATA.
******************************************************************************/
-void DAC_ChannelOutputSet( DAC_TypeDef *dac,
- unsigned int channel,
- uint32_t value )
+void DAC_ChannelOutputSet(DAC_TypeDef *dac,
+ unsigned int channel,
+ uint32_t value)
{
- switch(channel)
- {
+ switch (channel) {
case 0:
DAC_Channel0OutputSet(dac, value);
break;
@@ -262,7 +244,6 @@
}
}
-
/***************************************************************************//**
* @brief
* Calculate prescaler value used to determine DAC clock.
@@ -289,37 +270,33 @@
uint32_t ret;
/* Make sure selected DAC clock is below max value */
- if (dacFreq > DAC_MAX_CLOCK)
- {
+ if (dacFreq > DAC_MAX_CLOCK) {
dacFreq = DAC_MAX_CLOCK;
}
/* Use current HFPER frequency? */
- if (!hfperFreq)
- {
+ if (!hfperFreq) {
hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
}
/* Iterate in order to determine best prescale value. Only a few possible */
/* values. We start with lowest prescaler value in order to get first */
/* equal or below wanted DAC frequency value. */
- for (ret = 0; ret <= (_DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT); ret++)
- {
- if ((hfperFreq >> ret) <= dacFreq)
+ for (ret = 0; ret <= (_DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT); ret++) {
+ if ((hfperFreq >> ret) <= dacFreq) {
break;
+ }
}
/* If ret is higher than the max prescaler value, make sure to return
the max value. */
- if (ret > (_DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT))
- {
+ if (ret > (_DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT)) {
ret = _DAC_CTRL_PRESC_MASK >> _DAC_CTRL_PRESC_SHIFT;
}
return (uint8_t)ret;
}
-
/***************************************************************************//**
* @brief
* Reset DAC to same state as after a HW reset.
@@ -340,7 +317,6 @@
/* Do not reset route register, setting should be done independently */
}
-
/** @} (end addtogroup DAC) */
/** @} (end addtogroup emlib) */
#endif /* defined(DAC_COUNT) && (DAC_COUNT > 0) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_dbg.c
* @brief Debug (DBG) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -32,7 +32,7 @@
#include "em_dbg.h"
-#if defined( CoreDebug_DHCSR_C_DEBUGEN_Msk )
+#if defined(CoreDebug_DHCSR_C_DEBUGEN_Msk)
#include "em_assert.h"
#include "em_cmu.h"
@@ -57,7 +57,7 @@
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
-#if defined( GPIO_ROUTE_SWOPEN ) || defined( GPIO_ROUTEPEN_SWVPEN )
+#if defined(GPIO_ROUTE_SWOPEN) || defined(GPIO_ROUTEPEN_SWVPEN)
/***************************************************************************//**
* @brief
* Enable Serial Wire Output (SWO) pin.
@@ -96,10 +96,10 @@
EFM_ASSERT(location < AFCHANLOC_MAX);
-#if defined ( AF_DBG_SWO_PORT )
+#if defined (AF_DBG_SWO_PORT)
port = AF_DBG_SWO_PORT(location);
pin = AF_DBG_SWO_PIN(location);
-#elif defined (AF_DBG_SWV_PORT )
+#elif defined (AF_DBG_SWV_PORT)
port = AF_DBG_SWV_PORT(location);
pin = AF_DBG_SWV_PIN(location);
#else
@@ -107,8 +107,7 @@
#endif
/* Port/pin location not defined for device? */
- if ((pin < 0) || (port < 0))
- {
+ if ((pin < 0) || (port < 0)) {
EFM_ASSERT(0);
return;
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_dma.c
* @brief Direct memory access (DMA) module peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -31,7 +31,7 @@
******************************************************************************/
#include "em_dma.h"
-#if defined( DMA_PRESENT )
+#if defined(DMA_PRESENT)
#include "em_cmu.h"
#include "em_assert.h"
@@ -186,12 +186,9 @@
primDescr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE)) + channel;
/* Find descriptor to configure */
- if (primary)
- {
+ if (primary) {
descr = primDescr;
- }
- else
- {
+ } else {
descr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->ALTCTRLBASE)) + channel;
}
@@ -199,53 +196,38 @@
/* for primary or alternate descriptor. Mainly needed for ping-pong */
/* cycles. */
cb = (DMA_CB_TypeDef *)(primDescr->USER);
- if (cb)
- {
+ if (cb) {
cb->primary = (uint8_t)primary;
}
- if (src)
- {
+ if (src) {
inc = (descr->CTRL & _DMA_CTRL_SRC_INC_MASK) >> _DMA_CTRL_SRC_INC_SHIFT;
- if (inc == _DMA_CTRL_SRC_INC_NONE)
- {
+ if (inc == _DMA_CTRL_SRC_INC_NONE) {
descr->SRCEND = (volatile void*)src;
- }
- else
- {
+ } else {
descr->SRCEND = (void *)((uint32_t)src + (nMinus1 << inc));
}
}
- if (dst)
- {
+ if (dst) {
inc = (descr->CTRL & _DMA_CTRL_DST_INC_MASK) >> _DMA_CTRL_DST_INC_SHIFT;
- if (inc == _DMA_CTRL_DST_INC_NONE)
- {
+ if (inc == _DMA_CTRL_DST_INC_NONE) {
descr->DSTEND = dst;
- }
- else
- {
+ } else {
descr->DSTEND = (void *)((uint32_t)dst + (nMinus1 << inc));
}
}
chBit = 1 << channel;
- if (useBurst)
- {
+ if (useBurst) {
DMA->CHUSEBURSTS = chBit;
- }
- else
- {
+ } else {
DMA->CHUSEBURSTC = chBit;
}
- if (primary)
- {
+ if (primary) {
DMA->CHALTC = chBit;
- }
- else
- {
+ } else {
DMA->CHALTS = chBit;
}
@@ -302,15 +284,12 @@
/* defined with high priority, then those with default priority. */
prio = DMA->CHPRIS;
pendingPrio = pending & prio;
- for (i = 0; i < 2; i++)
- {
+ for (i = 0; i < 2; i++) {
channel = 0;
/* Process pending interrupts within high/default priority group */
/* honouring priority within group. */
- while (pendingPrio)
- {
- if (pendingPrio & 1)
- {
+ while (pendingPrio) {
+ if (pendingPrio & 1) {
DMA_DESCRIPTOR_TypeDef *descr = (DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE);
uint32_t chmask = 1 << channel;
@@ -322,14 +301,12 @@
/* check if callback is defined anyway. Callback info is always */
/* located in primary descriptor. */
cb = (DMA_CB_TypeDef *)(descr[channel].USER);
- if (cb)
- {
+ if (cb) {
/* Toggle next-descriptor indicator always prior to invoking */
/* callback (in case callback reconfigurs something) */
primaryCpy = cb->primary;
cb->primary ^= 1;
- if (cb->cbFunc)
- {
+ if (cb->cbFunc) {
cb->cbFunc(channel, (bool)primaryCpy, cb->userPtr);
}
}
@@ -346,7 +323,6 @@
#endif /* EXCLUDE_DEFAULT_DMA_IRQ_HANDLER */
-
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
@@ -407,7 +383,6 @@
DMA->CHSWREQ = chBit; /* Activate with SW request */
}
-
/***************************************************************************//**
* @brief
* Activate DMA basic cycle (used for memory-peripheral transfers).
@@ -468,7 +443,6 @@
DMA->CHENS = 1 << channel;
}
-
/***************************************************************************//**
* @brief
* Activate DMA ping-pong cycle (used for memory-peripheral transfers).
@@ -553,7 +527,6 @@
DMA->CHENS = 1 << channel;
}
-
/***************************************************************************//**
* @brief
* Activate DMA scatter-gather cycle (used for either memory-peripheral
@@ -612,8 +585,8 @@
/* The destination end address in the primary descriptor MUST point */
/* to the corresponding alternate descriptor in scatter-gather mode. */
- descr->DSTEND = (uint32_t *)((DMA_DESCRIPTOR_TypeDef *)(DMA->ALTCTRLBASE) +
- channel + 1) - 1;
+ descr->DSTEND = (uint32_t *)((DMA_DESCRIPTOR_TypeDef *)(DMA->ALTCTRLBASE)
+ + channel + 1) - 1;
/* The user field of the descriptor is used for callback configuration, */
/* and already configured when channel is configured. Do not modify it. */
@@ -630,13 +603,10 @@
/* order to have dma_done signal asserted when complete. Otherwise interrupt */
/* will not be triggered when done. */
altDescr[count - 1].CTRL &= ~_DMA_CTRL_CYCLE_CTRL_MASK;
- if (cycleCtrl == dmaCycleCtrlMemScatterGather)
- {
+ if (cycleCtrl == dmaCycleCtrlMemScatterGather) {
altDescr[count - 1].CTRL |= (uint32_t)dmaCycleCtrlAuto
<< _DMA_CTRL_CYCLE_CTRL_SHIFT;
- }
- else
- {
+ } else {
altDescr[count - 1].CTRL |= (uint32_t)dmaCycleCtrlBasic
<< _DMA_CTRL_CYCLE_CTRL_SHIFT;
}
@@ -646,22 +616,21 @@
/* but do for consistency. Always set to alternate, since that is the last */
/* descriptor actually used. */
cb = (DMA_CB_TypeDef *)(descr->USER);
- if (cb)
- {
+ if (cb) {
cb->primary = false;
}
/* Configure primary descriptor control word */
- descr->CTRL =((uint32_t)dmaDataInc4 << _DMA_CTRL_DST_INC_SHIFT)
- | ((uint32_t)dmaDataSize4 << _DMA_CTRL_DST_SIZE_SHIFT)
- | ((uint32_t)dmaDataInc4 << _DMA_CTRL_SRC_INC_SHIFT)
- | ((uint32_t)dmaDataSize4 << _DMA_CTRL_SRC_SIZE_SHIFT)
- /* Use same protection scheme as for alternate descriptors */
- | (altDescr->CTRL & _DMA_CTRL_SRC_PROT_CTRL_MASK)
- | ((uint32_t)dmaArbitrate4 << _DMA_CTRL_R_POWER_SHIFT)
- | (((count * 4) - 1) << _DMA_CTRL_N_MINUS_1_SHIFT)
- | (((uint32_t)useBurst & 1) << _DMA_CTRL_NEXT_USEBURST_SHIFT)
- | cycleCtrl;
+ descr->CTRL = ((uint32_t)dmaDataInc4 << _DMA_CTRL_DST_INC_SHIFT)
+ | ((uint32_t)dmaDataSize4 << _DMA_CTRL_DST_SIZE_SHIFT)
+ | ((uint32_t)dmaDataInc4 << _DMA_CTRL_SRC_INC_SHIFT)
+ | ((uint32_t)dmaDataSize4 << _DMA_CTRL_SRC_SIZE_SHIFT)
+ /* Use same protection scheme as for alternate descriptors */
+ | (altDescr->CTRL & _DMA_CTRL_SRC_PROT_CTRL_MASK)
+ | ((uint32_t)dmaArbitrate4 << _DMA_CTRL_R_POWER_SHIFT)
+ | (((count * 4) - 1) << _DMA_CTRL_N_MINUS_1_SHIFT)
+ | (((uint32_t)useBurst & 1) << _DMA_CTRL_NEXT_USEBURST_SHIFT)
+ | cycleCtrl;
chBit = 1 << channel;
@@ -673,13 +642,11 @@
/* Send request if memory scatter-gather, otherwise request signal is */
/* provided by peripheral. */
- if (cycleCtrl == dmaCycleCtrlMemScatterGather)
- {
+ if (cycleCtrl == dmaCycleCtrlMemScatterGather) {
DMA->CHSWREQ = chBit;
}
}
-
/***************************************************************************//**
* @brief
* Configure a DMA channel.
@@ -710,12 +677,9 @@
descr[channel].USER = (uint32_t)(cfg->cb);
/* Set to specified priority for channel */
- if (cfg->highPri)
- {
+ if (cfg->highPri) {
DMA->CHPRIS = 1 << channel;
- }
- else
- {
+ } else {
DMA->CHPRIC = 1 << channel;
}
@@ -723,18 +687,14 @@
DMA->CH[channel].CTRL = cfg->select;
/* Enable/disable interrupt as specified */
- if (cfg->enableInt)
- {
+ if (cfg->enableInt) {
DMA->IFC = (1 << channel);
BUS_RegBitWrite(&(DMA->IEN), channel, 1);
- }
- else
- {
+ } else {
BUS_RegBitWrite(&(DMA->IEN), channel, 0);
}
}
-
/***************************************************************************//**
* @brief
* Configure DMA descriptor for auto-request, basic or ping-pong DMA cycles.
@@ -783,12 +743,9 @@
EFM_ASSERT(cfg);
/* Find descriptor to configure */
- if (primary)
- {
+ if (primary) {
descr = (DMA_DESCRIPTOR_TypeDef *)DMA->CTRLBASE;
- }
- else
- {
+ } else {
descr = (DMA_DESCRIPTOR_TypeDef *)DMA->ALTCTRLBASE;
}
descr += channel;
@@ -806,8 +763,7 @@
| DMA_CTRL_CYCLE_CTRL_INVALID; /* Set when activated */
}
-
-#if defined( _DMA_LOOP0_MASK ) && defined( _DMA_LOOP1_MASK )
+#if defined(_DMA_LOOP0_MASK) && defined(_DMA_LOOP1_MASK)
/***************************************************************************//**
* @brief Configure DMA channel for Loop mode or 2D transfer.
*
@@ -827,22 +783,20 @@
EFM_ASSERT(cfg->nMinus1 <= 1023);
/* Configure LOOP setting */
- switch( channel )
- {
- case 0:
- DMA->LOOP0 = (cfg->enable << _DMA_LOOP0_EN_SHIFT)
- | (cfg->nMinus1 << _DMA_LOOP0_WIDTH_SHIFT);
- break;
- case 1:
- DMA->LOOP1 = (cfg->enable << _DMA_LOOP1_EN_SHIFT)
- | (cfg->nMinus1 << _DMA_LOOP1_WIDTH_SHIFT);
- break;
+ switch ( channel ) {
+ case 0:
+ DMA->LOOP0 = (cfg->enable << _DMA_LOOP0_EN_SHIFT)
+ | (cfg->nMinus1 << _DMA_LOOP0_WIDTH_SHIFT);
+ break;
+ case 1:
+ DMA->LOOP1 = (cfg->enable << _DMA_LOOP1_EN_SHIFT)
+ | (cfg->nMinus1 << _DMA_LOOP1_WIDTH_SHIFT);
+ break;
}
}
#endif
-
-#if defined( _DMA_RECT0_MASK )
+#if defined(_DMA_RECT0_MASK)
/***************************************************************************//**
* @brief Configure DMA channel 2D transfer properties.
*
@@ -862,13 +816,12 @@
EFM_ASSERT(cfg->height <= 1023);
/* Configure rectangular/2D copy */
- DMA->RECT0 = (cfg->dstStride << _DMA_RECT0_DSTSTRIDE_SHIFT)
- | (cfg->srcStride << _DMA_RECT0_SRCSTRIDE_SHIFT)
- | (cfg->height << _DMA_RECT0_HEIGHT_SHIFT);
+ DMA->RECT0 = (cfg->dstStride << _DMA_RECT0_DSTSTRIDE_SHIFT)
+ | (cfg->srcStride << _DMA_RECT0_SRCSTRIDE_SHIFT)
+ | (cfg->height << _DMA_RECT0_HEIGHT_SHIFT);
}
#endif
-
/***************************************************************************//**
* @brief
* Configure an alternate DMA descriptor for use with scatter-gather DMA
@@ -907,22 +860,16 @@
/* Point to selected entry in alternate descriptor table */
descr += indx;
- if (cfg->srcInc == dmaDataIncNone)
- {
+ if (cfg->srcInc == dmaDataIncNone) {
descr->SRCEND = cfg->src;
- }
- else
- {
+ } else {
descr->SRCEND = (void *)((uint32_t)(cfg->src)
+ ((uint32_t)(cfg->nMinus1) << cfg->srcInc));
}
- if (cfg->dstInc == dmaDataIncNone)
- {
+ if (cfg->dstInc == dmaDataIncNone) {
descr->DSTEND = cfg->dst;
- }
- else
- {
+ } else {
descr->DSTEND = (void *)((uint32_t)(cfg->dst)
+ ((uint32_t)(cfg->nMinus1) << cfg->dstInc));
}
@@ -930,31 +877,27 @@
/* User definable part not used */
descr->USER = 0;
- if (cfg->peripheral)
- {
+ if (cfg->peripheral) {
cycleCtrl = (uint32_t)dmaCycleCtrlPerScatterGather + 1;
- }
- else
- {
+ } else {
cycleCtrl = (uint32_t)dmaCycleCtrlMemScatterGather + 1;
}
- descr->CTRL =(cfg->dstInc << _DMA_CTRL_DST_INC_SHIFT)
- | (cfg->size << _DMA_CTRL_DST_SIZE_SHIFT)
- | (cfg->srcInc << _DMA_CTRL_SRC_INC_SHIFT)
- | (cfg->size << _DMA_CTRL_SRC_SIZE_SHIFT)
- | ((uint32_t)(cfg->hprot) << _DMA_CTRL_SRC_PROT_CTRL_SHIFT)
- | (cfg->arbRate << _DMA_CTRL_R_POWER_SHIFT)
- | ((uint32_t)(cfg->nMinus1) << _DMA_CTRL_N_MINUS_1_SHIFT)
- /* Never set next useburst bit, since the descriptor used after the */
- /* alternate descriptor is the primary descriptor which operates on */
- /* memory. If the alternate descriptors need to have useBurst set, this */
- /* done when setting up the primary descriptor, ie when activating. */
- | (0 << _DMA_CTRL_NEXT_USEBURST_SHIFT)
- | (cycleCtrl << _DMA_CTRL_CYCLE_CTRL_SHIFT);
+ descr->CTRL = (cfg->dstInc << _DMA_CTRL_DST_INC_SHIFT)
+ | (cfg->size << _DMA_CTRL_DST_SIZE_SHIFT)
+ | (cfg->srcInc << _DMA_CTRL_SRC_INC_SHIFT)
+ | (cfg->size << _DMA_CTRL_SRC_SIZE_SHIFT)
+ | ((uint32_t)(cfg->hprot) << _DMA_CTRL_SRC_PROT_CTRL_SHIFT)
+ | (cfg->arbRate << _DMA_CTRL_R_POWER_SHIFT)
+ | ((uint32_t)(cfg->nMinus1) << _DMA_CTRL_N_MINUS_1_SHIFT)
+ /* Never set next useburst bit, since the descriptor used after the */
+ /* alternate descriptor is the primary descriptor which operates on */
+ /* memory. If the alternate descriptors need to have useBurst set, this */
+ /* done when setting up the primary descriptor, ie when activating. */
+ | (0 << _DMA_CTRL_NEXT_USEBURST_SHIFT)
+ | (cycleCtrl << _DMA_CTRL_CYCLE_CTRL_SHIFT);
}
-
/***************************************************************************//**
* @brief
* Enable or disable a DMA channel.
@@ -975,17 +918,13 @@
{
EFM_ASSERT(channel < DMA_CHAN_COUNT);
- if (enable)
- {
- DMA->CHENS = 1<<channel;
- }
- else
- {
- DMA->CHENC = 1<<channel;
+ if (enable) {
+ DMA->CHENS = 1 << channel;
+ } else {
+ DMA->CHENC = 1 << channel;
}
}
-
/***************************************************************************//**
* @brief
* Check if DMA channel is enabled.
@@ -1007,7 +946,6 @@
return (bool)((DMA->CHENS >> channel) & 1);
}
-
/***************************************************************************//**
* @brief
* Enable or disable a DMA channel request.
@@ -1026,17 +964,13 @@
{
EFM_ASSERT(channel < DMA_CHAN_COUNT);
- if (enable)
- {
- BUS_RegBitWrite (&DMA->CHREQMASKC, channel, 1);
- }
- else
- {
- BUS_RegBitWrite (&DMA->CHREQMASKS, channel, 1);
+ if (enable) {
+ BUS_RegBitWrite(&DMA->CHREQMASKC, channel, 1);
+ } else {
+ BUS_RegBitWrite(&DMA->CHREQMASKS, channel, 1);
}
}
-
/***************************************************************************//**
* @brief
* Initializes DMA controller.
@@ -1090,7 +1024,6 @@
| DMA_CONFIG_EN;
}
-
/***************************************************************************//**
* @brief
* Refresh a descriptor used in a DMA ping-pong cycle.
@@ -1150,58 +1083,41 @@
EFM_ASSERT(nMinus1 <= (_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT));
/* The ping-pong DMA cycle may be stopped by issuing a basic cycle type */
- if (stop)
- {
+ if (stop) {
cycleCtrl = dmaCycleCtrlBasic;
- }
- else
- {
+ } else {
cycleCtrl = dmaCycleCtrlPingPong;
}
/* Find descriptor to configure */
- if (primary)
- {
+ if (primary) {
descr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE)) + channel;
- }
- else
- {
+ } else {
descr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->ALTCTRLBASE)) + channel;
}
- if (src)
- {
+ if (src) {
inc = (descr->CTRL & _DMA_CTRL_SRC_INC_MASK) >> _DMA_CTRL_SRC_INC_SHIFT;
- if (inc == _DMA_CTRL_SRC_INC_NONE)
- {
+ if (inc == _DMA_CTRL_SRC_INC_NONE) {
descr->SRCEND = (volatile void*)src;
- }
- else
- {
+ } else {
descr->SRCEND = (void *)((uint32_t)src + (nMinus1 << inc));
}
}
- if (dst)
- {
+ if (dst) {
inc = (descr->CTRL & _DMA_CTRL_DST_INC_MASK) >> _DMA_CTRL_DST_INC_SHIFT;
- if (inc == _DMA_CTRL_DST_INC_NONE)
- {
+ if (inc == _DMA_CTRL_DST_INC_NONE) {
descr->DSTEND = dst;
- }
- else
- {
+ } else {
descr->DSTEND = (void *)((uint32_t)dst + (nMinus1 << inc));
}
}
chBit = 1 << channel;
- if (useBurst)
- {
+ if (useBurst) {
DMA->CHUSEBURSTS = chBit;
- }
- else
- {
+ } else {
DMA->CHUSEBURSTC = chBit;
}
@@ -1212,7 +1128,6 @@
descr->CTRL = tmp;
}
-
/***************************************************************************//**
* @brief
* Reset the DMA controller.
@@ -1243,13 +1158,11 @@
DMA->IFC = _DMA_IFC_MASK;
/* Clear channel control flags */
- for (i = 0; i < DMA_CHAN_COUNT; i++)
- {
+ for (i = 0; i < DMA_CHAN_COUNT; i++) {
DMA->CH[i].CTRL = _DMA_CH_CTRL_RESETVALUE;
}
}
-
/** @} (end addtogroup DMA) */
/** @} (end addtogroup emlib) */
#endif /* defined( DMA_PRESENT ) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_ebi.c
* @brief External Bus Interface (EBI) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -50,6 +50,55 @@
* @{
******************************************************************************/
+/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
+
+/* The ROUTE register has been renamed in the newest platform so these register
+ * field names have been created in order to make it easier to work with both
+ * the new and the old names in a generic way. */
+#if defined(_EBI_ROUTE_MASK)
+#define _EBI_GENERIC_ALEPEN_SHIFT _EBI_ROUTE_ALEPEN_SHIFT
+#define _EBI_GENERIC_BLPEN_SHIFT _EBI_ROUTE_BLPEN_SHIFT
+#define _EBI_GENERIC_EBIPEN_SHIFT _EBI_ROUTE_EBIPEN_SHIFT
+#define _EBI_GENERIC_CS0PEN_SHIFT _EBI_ROUTE_CS0PEN_SHIFT
+#define _EBI_GENERIC_CS1PEN_SHIFT _EBI_ROUTE_CS1PEN_SHIFT
+#define _EBI_GENERIC_CS2PEN_SHIFT _EBI_ROUTE_CS2PEN_SHIFT
+#define _EBI_GENERIC_CS3PEN_SHIFT _EBI_ROUTE_CS3PEN_SHIFT
+#define _EBI_GENERIC_RESETVALUE _EBI_ROUTE_RESETVALUE
+#define EBI_GENERIC_ROUTE_REG EBI->ROUTE
+#define _EBI_GENERIC_ALB_MASK _EBI_ROUTE_ALB_MASK
+#define _EBI_GENERIC_APEN_MASK _EBI_ROUTE_APEN_MASK
+#define EBI_GENERIC_TFTPEN EBI_ROUTE_TFTPEN
+#else
+#define _EBI_GENERIC_ALEPEN_SHIFT _EBI_ROUTEPEN_ALEPEN_SHIFT
+#define _EBI_GENERIC_BLPEN_SHIFT _EBI_ROUTEPEN_BLPEN_SHIFT
+#define _EBI_GENERIC_EBIPEN_SHIFT _EBI_ROUTEPEN_EBIPEN_SHIFT
+#define _EBI_GENERIC_CS0PEN_SHIFT _EBI_ROUTEPEN_CS0PEN_SHIFT
+#define _EBI_GENERIC_CS1PEN_SHIFT _EBI_ROUTEPEN_CS1PEN_SHIFT
+#define _EBI_GENERIC_CS2PEN_SHIFT _EBI_ROUTEPEN_CS2PEN_SHIFT
+#define _EBI_GENERIC_CS3PEN_SHIFT _EBI_ROUTEPEN_CS3PEN_SHIFT
+#define _EBI_GENERIC_RESETVALUE _EBI_ROUTEPEN_RESETVALUE
+#define EBI_GENERIC_ROUTE_REG EBI->ROUTEPEN
+#define _EBI_GENERIC_ALB_MASK _EBI_ROUTEPEN_ALB_MASK
+#define _EBI_GENERIC_APEN_MASK _EBI_ROUTEPEN_APEN_MASK
+#define EBI_GENERIC_TFTPEN EBI_ROUTEPEN_TFTPEN
+#endif
+
+/***************************************************************************//**
+ * @brief
+ * Perform a single-bit write operation on a EBI route register
+ *
+ * @param[in] bit
+ * bit Bit position to write, 0-31
+ *
+ * @param[in] val
+ * 0 to clear bit and 1 to set bit
+ ******************************************************************************/
+__STATIC_INLINE void EBI_RouteBitWrite(uint32_t bit, uint32_t val)
+{
+ BUS_RegBitWrite(&(EBI_GENERIC_ROUTE_REG), bit, val);
+}
+/** @endcond */
+
/***************************************************************************//**
* @brief
* Configure and enable External Bus Interface
@@ -65,7 +114,18 @@
{
uint32_t ctrl = EBI->CTRL;
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(_EFM32_GECKO_FAMILY)
+ /* Set polarity of address ready */
+ EBI_PolaritySet(ebiLineARDY, ebiInit->ardyPolarity);
+ /* Set polarity of address latch enable */
+ EBI_PolaritySet(ebiLineALE, ebiInit->alePolarity);
+ /* Set polarity of write enable */
+ EBI_PolaritySet(ebiLineWE, ebiInit->wePolarity);
+ /* Set polarity of read enable */
+ EBI_PolaritySet(ebiLineRE, ebiInit->rePolarity);
+ /* Set polarity of chip select lines */
+ EBI_PolaritySet(ebiLineCS, ebiInit->csPolarity);
+#else
/* Enable Independent Timing for devices that supports it */
ctrl |= EBI_CTRL_ITS;
@@ -81,23 +141,36 @@
EBI_BankPolaritySet(ebiInit->banks, ebiLineCS, ebiInit->csPolarity);
/* Set polarity of byte lane line */
EBI_BankPolaritySet(ebiInit->banks, ebiLineBL, ebiInit->blPolarity);
-#else
- /* Set polarity of address ready */
- EBI_PolaritySet(ebiLineARDY, ebiInit->ardyPolarity);
- /* Set polarity of address latch enable */
- EBI_PolaritySet(ebiLineALE, ebiInit->alePolarity);
- /* Set polarity of write enable */
- EBI_PolaritySet(ebiLineWE, ebiInit->wePolarity);
- /* Set polarity of read enable */
- EBI_PolaritySet(ebiLineRE, ebiInit->rePolarity);
- /* Set polarity of chip select lines */
- EBI_PolaritySet(ebiLineCS, ebiInit->csPolarity);
#endif
/* Configure EBI mode and control settings */
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
- if (ebiInit->banks & EBI_BANK0)
- {
+#if defined(_EFM32_GECKO_FAMILY)
+ ctrl &= ~(_EBI_CTRL_MODE_MASK
+ | _EBI_CTRL_ARDYEN_MASK
+ | _EBI_CTRL_ARDYTODIS_MASK
+ | _EBI_CTRL_BANK0EN_MASK
+ | _EBI_CTRL_BANK1EN_MASK
+ | _EBI_CTRL_BANK2EN_MASK
+ | _EBI_CTRL_BANK3EN_MASK);
+ if ( ebiInit->enable) {
+ if ( ebiInit->banks & EBI_BANK0 ) {
+ ctrl |= EBI_CTRL_BANK0EN;
+ }
+ if ( ebiInit->banks & EBI_BANK1 ) {
+ ctrl |= EBI_CTRL_BANK1EN;
+ }
+ if ( ebiInit->banks & EBI_BANK2 ) {
+ ctrl |= EBI_CTRL_BANK2EN;
+ }
+ if ( ebiInit->banks & EBI_BANK3 ) {
+ ctrl |= EBI_CTRL_BANK3EN;
+ }
+ }
+ ctrl |= ebiInit->mode;
+ ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
+ ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
+#else
+ if (ebiInit->banks & EBI_BANK0) {
ctrl &= ~(_EBI_CTRL_MODE_MASK
| _EBI_CTRL_ARDYEN_MASK
| _EBI_CTRL_ARDYTODIS_MASK
@@ -109,13 +182,11 @@
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT);
- if ( ebiInit->enable)
- {
+ if ( ebiInit->enable) {
ctrl |= EBI_CTRL_BANK0EN;
}
}
- if (ebiInit->banks & EBI_BANK1)
- {
+ if (ebiInit->banks & EBI_BANK1) {
ctrl &= ~(_EBI_CTRL_BL1_MASK
| _EBI_CTRL_MODE1_MASK
| _EBI_CTRL_ARDY1EN_MASK
@@ -127,13 +198,11 @@
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT);
- if ( ebiInit->enable)
- {
+ if ( ebiInit->enable) {
ctrl |= EBI_CTRL_BANK1EN;
}
}
- if (ebiInit->banks & EBI_BANK2)
- {
+ if (ebiInit->banks & EBI_BANK2) {
ctrl &= ~(_EBI_CTRL_BL2_MASK
| _EBI_CTRL_MODE2_MASK
| _EBI_CTRL_ARDY2EN_MASK
@@ -145,13 +214,11 @@
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT);
- if ( ebiInit->enable)
- {
+ if ( ebiInit->enable) {
ctrl |= EBI_CTRL_BANK2EN;
}
}
- if (ebiInit->banks & EBI_BANK3)
- {
+ if (ebiInit->banks & EBI_BANK3) {
ctrl &= ~(_EBI_CTRL_BL3_MASK
| _EBI_CTRL_MODE3_MASK
| _EBI_CTRL_ARDY3EN_MASK
@@ -163,45 +230,23 @@
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT);
- if ( ebiInit->enable)
- {
+ if ( ebiInit->enable) {
ctrl |= EBI_CTRL_BANK3EN;
}
}
-#else
- ctrl &= ~(_EBI_CTRL_MODE_MASK
- | _EBI_CTRL_ARDYEN_MASK
- | _EBI_CTRL_ARDYTODIS_MASK
- | _EBI_CTRL_BANK0EN_MASK
- | _EBI_CTRL_BANK1EN_MASK
- | _EBI_CTRL_BANK2EN_MASK
- | _EBI_CTRL_BANK3EN_MASK);
- if ( ebiInit->enable)
- {
- if ( ebiInit->banks & EBI_BANK0 )
- {
- ctrl |= EBI_CTRL_BANK0EN;
- }
- if ( ebiInit->banks & EBI_BANK1 )
- {
- ctrl |= EBI_CTRL_BANK1EN;
- }
- if ( ebiInit->banks & EBI_BANK2 )
- {
- ctrl |= EBI_CTRL_BANK2EN;
- }
- if ( ebiInit->banks & EBI_BANK3 )
- {
- ctrl |= EBI_CTRL_BANK3EN;
- }
- }
- ctrl |= ebiInit->mode;
- ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
- ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
#endif
/* Configure timing */
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(_EFM32_GECKO_FAMILY)
+ EBI_ReadTimingSet(ebiInit->readSetupCycles,
+ ebiInit->readStrobeCycles,
+ ebiInit->readHoldCycles);
+ EBI_WriteTimingSet(ebiInit->writeSetupCycles,
+ ebiInit->writeStrobeCycles,
+ ebiInit->writeHoldCycles);
+ EBI_AddressTimingSet(ebiInit->addrSetupCycles,
+ ebiInit->addrHoldCycles);
+#else
EBI_BankReadTimingSet(ebiInit->banks,
ebiInit->readSetupCycles,
ebiInit->readStrobeCycles,
@@ -222,57 +267,49 @@
ebiInit->addrHoldCycles);
EBI_BankAddressTimingConfig(ebiInit->banks,
ebiInit->addrHalfALE);
-#else
- EBI_ReadTimingSet(ebiInit->readSetupCycles,
- ebiInit->readStrobeCycles,
- ebiInit->readHoldCycles);
- EBI_WriteTimingSet(ebiInit->writeSetupCycles,
- ebiInit->writeStrobeCycles,
- ebiInit->writeHoldCycles);
- EBI_AddressTimingSet(ebiInit->addrSetupCycles,
- ebiInit->addrHoldCycles);
#endif
/* Activate new configuration */
EBI->CTRL = ctrl;
/* Configure Adress Latch Enable */
- switch (ebiInit->mode)
- {
+ switch (ebiInit->mode) {
case ebiModeD16A16ALE:
case ebiModeD8A24ALE:
/* Address Latch Enable */
- BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 1);
+ EBI_RouteBitWrite(_EBI_GENERIC_ALEPEN_SHIFT, 1);
break;
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(EBI_CTRL_MODE_D16)
case ebiModeD16:
#endif
case ebiModeD8A8:
/* Make sure Address Latch is disabled */
- BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 0);
+ EBI_RouteBitWrite(_EBI_GENERIC_ALEPEN_SHIFT, 0);
break;
}
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+
+#if !defined(_EFM32_GECKO_FAMILY)
/* Limit pin enable */
- EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_ALB_MASK) | ebiInit->aLow;
- EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_APEN_MASK) | ebiInit->aHigh;
+ EBI_GENERIC_ROUTE_REG = (EBI_GENERIC_ROUTE_REG & ~_EBI_GENERIC_ALB_MASK) | ebiInit->aLow;
+ EBI_GENERIC_ROUTE_REG = (EBI_GENERIC_ROUTE_REG & ~_EBI_GENERIC_APEN_MASK) | ebiInit->aHigh;
+#if defined(_EBI_ROUTE_LOCATION_MASK)
/* Location */
EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_LOCATION_MASK) | ebiInit->location;
+#endif
/* Enable EBI BL pin if necessary */
- if(ctrl & (_EBI_CTRL_BL_MASK|_EBI_CTRL_BL1_MASK|_EBI_CTRL_BL2_MASK|_EBI_CTRL_BL3_MASK))
- {
- BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_BLPEN_SHIFT, ebiInit->blEnable);
+ if (ctrl & (_EBI_CTRL_BL_MASK | _EBI_CTRL_BL1_MASK | _EBI_CTRL_BL2_MASK | _EBI_CTRL_BL3_MASK)) {
+ EBI_RouteBitWrite(_EBI_GENERIC_BLPEN_SHIFT, ebiInit->blEnable);
}
#endif
+
/* Enable EBI pins EBI_WEn and EBI_REn */
- BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_EBIPEN_SHIFT, 1);
+ EBI_RouteBitWrite(_EBI_GENERIC_EBIPEN_SHIFT, 1);
/* Enable chip select lines */
EBI_ChipSelectEnable(ebiInit->csLines, true);
}
-
/***************************************************************************//**
* @brief
* Disable External Bus Interface
@@ -280,12 +317,11 @@
void EBI_Disable(void)
{
/* Disable pins */
- EBI->ROUTE = _EBI_ROUTE_RESETVALUE;
+ EBI_GENERIC_ROUTE_REG = _EBI_GENERIC_RESETVALUE;
/* Disable banks */
EBI->CTRL = _EBI_CTRL_RESETVALUE;
}
-
/***************************************************************************//**
* @brief
* Enable or disable EBI Bank
@@ -298,25 +334,20 @@
******************************************************************************/
void EBI_BankEnable(uint32_t banks, bool enable)
{
- if (banks & EBI_BANK0)
- {
+ if (banks & EBI_BANK0) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK0EN_SHIFT, enable);
}
- if (banks & EBI_BANK1)
- {
+ if (banks & EBI_BANK1) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK1EN_SHIFT, enable);
}
- if (banks & EBI_BANK2)
- {
+ if (banks & EBI_BANK2) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK2EN_SHIFT, enable);
}
- if (banks & EBI_BANK3)
- {
+ if (banks & EBI_BANK3) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK3EN_SHIFT, enable);
}
}
-
/***************************************************************************//**
* @brief
* Return base address of EBI bank
@@ -329,22 +360,20 @@
******************************************************************************/
uint32_t EBI_BankAddress(uint32_t bank)
{
-#if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
- if(EBI->CTRL & EBI_CTRL_ALTMAP)
- {
- switch (bank)
- {
+#if defined (EBI_CTRL_ALTMAP)
+ if (EBI->CTRL & EBI_CTRL_ALTMAP) {
+ switch (bank) {
case EBI_BANK0:
- return(EBI_MEM_BASE);
+ return EBI_MEM_BASE;
case EBI_BANK1:
- return(EBI_MEM_BASE + 0x10000000UL);
+ return EBI_MEM_BASE + 0x10000000UL;
case EBI_BANK2:
- return(EBI_MEM_BASE + 0x20000000UL);
+ return EBI_MEM_BASE + 0x20000000UL;
case EBI_BANK3:
- return(EBI_MEM_BASE + 0x30000000UL);
+ return EBI_MEM_BASE + 0x30000000UL;
default:
EFM_ASSERT(0);
@@ -352,19 +381,18 @@
}
}
#endif
- switch (bank)
- {
+ switch (bank) {
case EBI_BANK0:
- return(EBI_MEM_BASE);
+ return EBI_MEM_BASE;
case EBI_BANK1:
- return(EBI_MEM_BASE + 0x04000000UL);
+ return EBI_MEM_BASE + 0x04000000UL;
case EBI_BANK2:
- return(EBI_MEM_BASE + 0x08000000UL);
+ return EBI_MEM_BASE + 0x08000000UL;
case EBI_BANK3:
- return(EBI_MEM_BASE + 0x0C000000UL);
+ return EBI_MEM_BASE + 0x0C000000UL;
default:
EFM_ASSERT(0);
@@ -373,7 +401,6 @@
return 0;
}
-
/***************************************************************************//**
* @brief
* Enable or disable EBI Chip Select
@@ -386,25 +413,20 @@
******************************************************************************/
void EBI_ChipSelectEnable(uint32_t cs, bool enable)
{
- if (cs & EBI_CS0)
- {
- BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS0PEN_SHIFT, enable);
+ if (cs & EBI_CS0) {
+ EBI_RouteBitWrite(_EBI_GENERIC_CS0PEN_SHIFT, enable);
}
- if (cs & EBI_CS1)
- {
- BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS1PEN_SHIFT, enable);
+ if (cs & EBI_CS1) {
+ EBI_RouteBitWrite(_EBI_GENERIC_CS1PEN_SHIFT, enable);
}
- if (cs & EBI_CS2)
- {
- BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS2PEN_SHIFT, enable);
+ if (cs & EBI_CS2) {
+ EBI_RouteBitWrite(_EBI_GENERIC_CS2PEN_SHIFT, enable);
}
- if (cs & EBI_CS3)
- {
- BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS3PEN_SHIFT, enable);
+ if (cs & EBI_CS3) {
+ EBI_RouteBitWrite(_EBI_GENERIC_CS3PEN_SHIFT, enable);
}
}
-
/***************************************************************************//**
* @brief
* Configure EBI pin polarity
@@ -417,41 +439,42 @@
******************************************************************************/
void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
{
- switch (line)
- {
+ switch (line) {
case ebiLineARDY:
- BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
+ BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
break;
case ebiLineALE:
- BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ALEPOL_SHIFT, polarity);
+ BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_ALEPOL_SHIFT, polarity);
break;
case ebiLineWE:
- BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_WEPOL_SHIFT, polarity);
+ BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_WEPOL_SHIFT, polarity);
break;
case ebiLineRE:
- BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_REPOL_SHIFT, polarity);
+ BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_REPOL_SHIFT, polarity);
break;
case ebiLineCS:
- BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_CSPOL_SHIFT, polarity);
+ BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_CSPOL_SHIFT, polarity);
break;
-#if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(_EBI_POLARITY_BLPOL_MASK)
case ebiLineBL:
- BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_BLPOL_SHIFT, polarity);
+ BUS_RegBitWrite(&EBI->POLARITY, _EBI_POLARITY_BLPOL_SHIFT, polarity);
break;
+#endif
+#if defined (_EBI_TFTPOLARITY_MASK)
case ebiLineTFTVSync:
- BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
+ BUS_RegBitWrite(&EBI->TFTPOLARITY, _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
break;
case ebiLineTFTHSync:
- BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
+ BUS_RegBitWrite(&EBI->TFTPOLARITY, _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
break;
case ebiLineTFTDataEn:
- BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
+ BUS_RegBitWrite(&EBI->TFTPOLARITY, _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
break;
case ebiLineTFTDClk:
- BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
+ BUS_RegBitWrite(&EBI->TFTPOLARITY, _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
break;
case ebiLineTFTCS:
- BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
+ BUS_RegBitWrite(&EBI->TFTPOLARITY, _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
break;
#endif
default:
@@ -460,7 +483,6 @@
}
}
-
/***************************************************************************//**
* @brief
* Configure timing values of read bus accesses
@@ -489,7 +511,6 @@
| (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
| (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
-
EBI->RDTIMING = (EBI->RDTIMING
& ~(_EBI_RDTIMING_RDSETUP_MASK
| _EBI_RDTIMING_RDSTRB_MASK
@@ -497,7 +518,6 @@
| readTiming;
}
-
/***************************************************************************//**
* @brief
* Configure timing values of write bus accesses
@@ -532,7 +552,6 @@
| writeTiming;
}
-
/***************************************************************************//**
* @brief
* Configure timing values of address latch bus accesses
@@ -562,7 +581,7 @@
| addressLatchTiming;
}
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if defined(_EBI_TFTCTRL_MASK)
/***************************************************************************//**
* @brief
* Configure and initialize TFT Direct Drive
@@ -614,13 +633,11 @@
EBI->TFTCTRL = ctrl;
/* Enable TFT pins */
- if (ebiTFTInit->driveMode != ebiTFTDDModeDisabled)
- {
- EBI->ROUTE |= EBI_ROUTE_TFTPEN;
+ if (ebiTFTInit->driveMode != ebiTFTDDModeDisabled) {
+ EBI_GENERIC_ROUTE_REG |= EBI_GENERIC_TFTPEN;
}
}
-
/***************************************************************************//**
* @brief
* Configure and initialize TFT size settings
@@ -632,11 +649,11 @@
******************************************************************************/
void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical)
{
- EFM_ASSERT((horizontal-1) < 1024);
- EFM_ASSERT((vertical-1) < 1024);
+ EFM_ASSERT((horizontal - 1) < 1024);
+ EFM_ASSERT((vertical - 1) < 1024);
- EBI->TFTSIZE = ((horizontal-1) << _EBI_TFTSIZE_HSZ_SHIFT)
- | ((vertical-1) << _EBI_TFTSIZE_VSZ_SHIFT);
+ EBI->TFTSIZE = ((horizontal - 1) << _EBI_TFTSIZE_HSZ_SHIFT)
+ | ((vertical - 1) << _EBI_TFTSIZE_VSZ_SHIFT);
}
/***************************************************************************//**
@@ -654,14 +671,13 @@
{
EFM_ASSERT(front < 256);
EFM_ASSERT(back < 256);
- EFM_ASSERT((pulseWidth-1) < 128);
+ EFM_ASSERT((pulseWidth - 1) < 128);
EBI->TFTHPORCH = (front << _EBI_TFTHPORCH_HFPORCH_SHIFT)
| (back << _EBI_TFTHPORCH_HBPORCH_SHIFT)
- | ((pulseWidth-1) << _EBI_TFTHPORCH_HSYNC_SHIFT);
+ | ((pulseWidth - 1) << _EBI_TFTHPORCH_HSYNC_SHIFT);
}
-
/***************************************************************************//**
* @brief
* Configure Vertical Porch Settings
@@ -677,14 +693,13 @@
{
EFM_ASSERT(front < 256);
EFM_ASSERT(back < 256);
- EFM_ASSERT((pulseWidth-1) < 128);
+ EFM_ASSERT((pulseWidth - 1) < 128);
EBI->TFTVPORCH = (front << _EBI_TFTVPORCH_VFPORCH_SHIFT)
| (back << _EBI_TFTVPORCH_VBPORCH_SHIFT)
- | ((pulseWidth-1) << _EBI_TFTVPORCH_VSYNC_SHIFT);
+ | ((pulseWidth - 1) << _EBI_TFTVPORCH_VSYNC_SHIFT);
}
-
/***************************************************************************//**
* @brief
* Configure TFT Direct Drive Timing Settings
@@ -715,7 +730,7 @@
}
#endif
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#if !defined(_EFM32_GECKO_FAMILY)
/***************************************************************************//**
* @brief
* Configure read operation parameters for selected bank
@@ -734,30 +749,26 @@
******************************************************************************/
void EBI_BankReadTimingConfig(uint32_t banks, bool pageMode, bool prefetch, bool halfRE)
{
- /* Verify only valid banks are used */
+ /* Verify only valid banks are used */
EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
/* Configure read operation parameters */
- if( banks & EBI_BANK0 )
- {
+ if ( banks & EBI_BANK0 ) {
BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
}
- if( banks & EBI_BANK1 )
- {
+ if ( banks & EBI_BANK1 ) {
BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
}
- if( banks & EBI_BANK2 )
- {
+ if ( banks & EBI_BANK2 ) {
BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
}
- if( banks & EBI_BANK3 )
- {
+ if ( banks & EBI_BANK3 ) {
BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
@@ -798,32 +809,28 @@
| (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
| (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
- if (banks & EBI_BANK0)
- {
+ if (banks & EBI_BANK0) {
EBI->RDTIMING = (EBI->RDTIMING
& ~(_EBI_RDTIMING_RDSETUP_MASK
| _EBI_RDTIMING_RDSTRB_MASK
| _EBI_RDTIMING_RDHOLD_MASK))
| readTiming;
}
- if (banks & EBI_BANK1)
- {
+ if (banks & EBI_BANK1) {
EBI->RDTIMING1 = (EBI->RDTIMING1
& ~(_EBI_RDTIMING1_RDSETUP_MASK
- | _EBI_RDTIMING1_RDSTRB_MASK
- | _EBI_RDTIMING1_RDHOLD_MASK))
+ | _EBI_RDTIMING1_RDSTRB_MASK
+ | _EBI_RDTIMING1_RDHOLD_MASK))
| readTiming;
}
- if (banks & EBI_BANK2)
- {
+ if (banks & EBI_BANK2) {
EBI->RDTIMING2 = (EBI->RDTIMING2
& ~(_EBI_RDTIMING2_RDSETUP_MASK
| _EBI_RDTIMING2_RDSTRB_MASK
| _EBI_RDTIMING2_RDHOLD_MASK))
| readTiming;
}
- if (banks & EBI_BANK3)
- {
+ if (banks & EBI_BANK3) {
EBI->RDTIMING3 = (EBI->RDTIMING3
& ~(_EBI_RDTIMING3_RDSETUP_MASK
| _EBI_RDTIMING3_RDSTRB_MASK
@@ -832,7 +839,6 @@
}
}
-
/***************************************************************************//**
* @brief
* Configure write operation parameters for selected bank
@@ -852,29 +858,24 @@
EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
/* Configure write operation parameters */
- if( banks & EBI_BANK0 )
- {
+ if ( banks & EBI_BANK0 ) {
BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
}
- if( banks & EBI_BANK1 )
- {
+ if ( banks & EBI_BANK1 ) {
BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
}
- if( banks & EBI_BANK2 )
- {
+ if ( banks & EBI_BANK2 ) {
BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
}
- if( banks & EBI_BANK3 )
- {
+ if ( banks & EBI_BANK3 ) {
BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
}
}
-
/***************************************************************************//**
* @brief
* Configure timing values of write bus accesses
@@ -908,32 +909,28 @@
| (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
| (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
- if (banks & EBI_BANK0)
- {
+ if (banks & EBI_BANK0) {
EBI->WRTIMING = (EBI->WRTIMING
& ~(_EBI_WRTIMING_WRSETUP_MASK
| _EBI_WRTIMING_WRSTRB_MASK
| _EBI_WRTIMING_WRHOLD_MASK))
| writeTiming;
}
- if (banks & EBI_BANK1)
- {
+ if (banks & EBI_BANK1) {
EBI->WRTIMING1 = (EBI->WRTIMING1
& ~(_EBI_WRTIMING1_WRSETUP_MASK
| _EBI_WRTIMING1_WRSTRB_MASK
| _EBI_WRTIMING1_WRHOLD_MASK))
| writeTiming;
}
- if (banks & EBI_BANK2)
- {
+ if (banks & EBI_BANK2) {
EBI->WRTIMING2 = (EBI->WRTIMING2
& ~(_EBI_WRTIMING2_WRSETUP_MASK
| _EBI_WRTIMING2_WRSTRB_MASK
| _EBI_WRTIMING2_WRHOLD_MASK))
| writeTiming;
}
- if (banks & EBI_BANK3)
- {
+ if (banks & EBI_BANK3) {
EBI->WRTIMING3 = (EBI->WRTIMING3
& ~(_EBI_WRTIMING3_WRSETUP_MASK
| _EBI_WRTIMING3_WRSTRB_MASK
@@ -942,7 +939,6 @@
}
}
-
/***************************************************************************//**
* @brief
* Configure address operation parameters for selected bank
@@ -958,25 +954,20 @@
/* Verify only valid banks are used */
EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
- if( banks & EBI_BANK0 )
- {
+ if ( banks & EBI_BANK0 ) {
BUS_RegBitWrite(&EBI->ADDRTIMING, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
}
- if( banks & EBI_BANK1 )
- {
+ if ( banks & EBI_BANK1 ) {
BUS_RegBitWrite(&EBI->ADDRTIMING1, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
}
- if( banks & EBI_BANK2 )
- {
+ if ( banks & EBI_BANK2 ) {
BUS_RegBitWrite(&EBI->ADDRTIMING2, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
}
- if( banks & EBI_BANK3 )
- {
+ if ( banks & EBI_BANK3 ) {
BUS_RegBitWrite(&EBI->ADDRTIMING3, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
}
}
-
/***************************************************************************//**
* @brief
* Configure timing values of address latch bus accesses
@@ -1006,29 +997,25 @@
addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
| (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
- if (banks & EBI_BANK0)
- {
+ if (banks & EBI_BANK0) {
EBI->ADDRTIMING = (EBI->ADDRTIMING
& ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
| _EBI_ADDRTIMING_ADDRHOLD_MASK))
| addressLatchTiming;
}
- if (banks & EBI_BANK1)
- {
+ if (banks & EBI_BANK1) {
EBI->ADDRTIMING1 = (EBI->ADDRTIMING1
& ~(_EBI_ADDRTIMING1_ADDRSETUP_MASK
| _EBI_ADDRTIMING1_ADDRHOLD_MASK))
| addressLatchTiming;
}
- if (banks & EBI_BANK2)
- {
+ if (banks & EBI_BANK2) {
EBI->ADDRTIMING2 = (EBI->ADDRTIMING2
& ~(_EBI_ADDRTIMING2_ADDRSETUP_MASK
| _EBI_ADDRTIMING2_ADDRHOLD_MASK))
| addressLatchTiming;
}
- if (banks & EBI_BANK3)
- {
+ if (banks & EBI_BANK3) {
EBI->ADDRTIMING3 = (EBI->ADDRTIMING3
& ~(_EBI_ADDRTIMING3_ADDRSETUP_MASK
| _EBI_ADDRTIMING3_ADDRHOLD_MASK))
@@ -1036,7 +1023,6 @@
}
}
-
/***************************************************************************//**
* @brief
* Configure EBI pin polarity for selected bank(s) for devices with individual
@@ -1059,37 +1045,26 @@
/* Verify only valid banks are used */
EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
- while (banks)
- {
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
- if (banks & EBI_BANK0)
- {
+ while (banks) {
+ if (banks & EBI_BANK0) {
polRegister = &EBI->POLARITY;
bankSet = EBI_BANK0;
}
- if (banks & EBI_BANK1)
- {
+ if (banks & EBI_BANK1) {
polRegister = &EBI->POLARITY1;
bankSet = EBI_BANK1;
}
- if (banks & EBI_BANK2)
- {
+ if (banks & EBI_BANK2) {
polRegister = &EBI->POLARITY2;
bankSet = EBI_BANK2;
}
- if (banks & EBI_BANK3)
- {
+ if (banks & EBI_BANK3) {
polRegister = &EBI->POLARITY3;
bankSet = EBI_BANK3;
}
-#else
- polRegister = &EBI->POLARITY;
- banks = 0;
-#endif
/* What line to configure */
- switch (line)
- {
+ switch (line) {
case ebiLineARDY:
BUS_RegBitWrite(polRegister, _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
break;
@@ -1105,7 +1080,6 @@
case ebiLineCS:
BUS_RegBitWrite(polRegister, _EBI_POLARITY_CSPOL_SHIFT, polarity);
break;
-#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
case ebiLineBL:
BUS_RegBitWrite(polRegister, _EBI_POLARITY_BLPOL_SHIFT, polarity);
break;
@@ -1124,7 +1098,6 @@
case ebiLineTFTCS:
BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
break;
-#endif
default:
EFM_ASSERT(0);
break;
@@ -1133,7 +1106,6 @@
}
}
-
/***************************************************************************//**
* @brief
* Configure Byte Lane Enable for select banks
@@ -1151,25 +1123,20 @@
EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
/* Configure byte lane support for each selected bank */
- if (banks & EBI_BANK0)
- {
+ if (banks & EBI_BANK0) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL_SHIFT, enable);
}
- if (banks & EBI_BANK1)
- {
+ if (banks & EBI_BANK1) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL1_SHIFT, enable);
}
- if (banks & EBI_BANK2)
- {
+ if (banks & EBI_BANK2) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL2_SHIFT, enable);
}
- if (banks & EBI_BANK3)
- {
+ if (banks & EBI_BANK3) {
BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL3_SHIFT, enable);
}
}
-
/***************************************************************************//**
* @brief
* Configure Alternate Address Map support
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_emu.c
* @brief Energy Management Unit (EMU) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -33,12 +33,12 @@
#include <limits.h>
#include "em_emu.h"
-#if defined( EMU_PRESENT ) && ( EMU_COUNT > 0 )
+#if defined(EMU_PRESENT) && (EMU_COUNT > 0)
+#include "em_assert.h"
#include "em_cmu.h"
+#include "em_common.h"
#include "em_system.h"
-#include "em_common.h"
-#include "em_assert.h"
/***************************************************************************//**
* @addtogroup emlib
@@ -71,52 +71,60 @@
#endif
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-#if defined( _SILICON_LABS_32B_SERIES_0 )
+#if defined(_SILICON_LABS_32B_SERIES_0)
/* Fix for errata EMU_E107 - non-WIC interrupt masks.
* Zero Gecko and future families are not affected by errata EMU_E107 */
-#if defined( _EFM32_GECKO_FAMILY )
-#define ERRATA_FIX_EMU_E107_EN
+#if defined(_EFM32_GECKO_FAMILY)
+#define ERRATA_FIX_EMU_E107_ENABLE
#define NON_WIC_INT_MASK_0 (~(0x0dfc0323U))
#define NON_WIC_INT_MASK_1 (~(0x0U))
-#elif defined( _EFM32_TINY_FAMILY )
-#define ERRATA_FIX_EMU_E107_EN
+#elif defined(_EFM32_TINY_FAMILY)
+#define ERRATA_FIX_EMU_E107_ENABLE
#define NON_WIC_INT_MASK_0 (~(0x001be323U))
#define NON_WIC_INT_MASK_1 (~(0x0U))
-#elif defined( _EFM32_GIANT_FAMILY )
-#define ERRATA_FIX_EMU_E107_EN
+#elif defined(_EFM32_GIANT_FAMILY)
+#define ERRATA_FIX_EMU_E107_ENABLE
#define NON_WIC_INT_MASK_0 (~(0xff020e63U))
#define NON_WIC_INT_MASK_1 (~(0x00000046U))
-#elif defined( _EFM32_WONDER_FAMILY )
-#define ERRATA_FIX_EMU_E107_EN
+#elif defined(_EFM32_WONDER_FAMILY)
+#define ERRATA_FIX_EMU_E107_ENABLE
#define NON_WIC_INT_MASK_0 (~(0xff020e63U))
#define NON_WIC_INT_MASK_1 (~(0x00000046U))
#endif
#endif
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_74) \
+ || (defined(_SILICON_LABS_32B_SERIES_0) \
+ && (defined(_EFM32_HAPPY_FAMILY) || defined(_EFM32_ZERO_FAMILY)))
+// Fix for errata EMU_E110 - Potential Hard Fault when Exiting EM2.
+#include "em_core.h"
+#include "em_ramfunc.h"
+#define ERRATA_FIX_EMU_E110_ENABLE
+#endif
+
/* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */
-#if defined(_SILICON_LABS_32B_SERIES_0) && defined( _EFM32_HAPPY_FAMILY )
-#define ERRATA_FIX_EMU_E108_EN
+#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY)
+#define ERRATA_FIX_EMU_E108_ENABLE
#endif
/* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H */
-#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
-#define ERRATA_FIX_EMU_E208_EN
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
+#define ERRATA_FIX_EMU_E208_ENABLE
#endif
/* Enable FETCNT tuning errata fix */
-#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
-#define ERRATA_FIX_DCDC_FETCNT_SET_EN
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
+#define ERRATA_FIX_DCDC_FETCNT_SET_ENABLE
#endif
/* Enable LN handshake errata fix */
-#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
-#define ERRATA_FIX_DCDC_LNHS_BLOCK_EN
-typedef enum
-{
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
+#define ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE
+typedef enum {
errataFixDcdcHsInit,
errataFixDcdcHsTrimSet,
errataFixDcdcHsBypassLn,
@@ -131,21 +139,43 @@
#define ADDRESS_NOT_IN_BLOCK(addr, block) ((addr) <= (block))
/* RAM Block layout for various device families. Note that some devices
- * have special layout in RAM0. */
+ * have special layout in RAM0 and some devices have a special RAM block
+ * at the end of their block layout. */
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
#define RAM1_BLOCKS 2
#define RAM1_BLOCK_SIZE 0x10000 // 64 kB blocks
+#define RAM2_BLOCKS 1
+#define RAM2_BLOCK_SIZE 0x800 // 2 kB block
#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
#define RAM0_BLOCKS 2
#define RAM0_BLOCK_SIZE 0x4000
#define RAM1_BLOCKS 2
#define RAM1_BLOCK_SIZE 0x4000 // 16 kB blocks
+#define RAM2_BLOCKS 1
+#define RAM2_BLOCK_SIZE 0x800 // 2 kB block
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
+#define RAM0_BLOCKS 1
+#define RAM0_BLOCK_SIZE 0x4000 // 16 kB block
+#define RAM1_BLOCKS 1
+#define RAM1_BLOCK_SIZE 0x4000 // 16 kB block
+#define RAM2_BLOCKS 1
+#define RAM2_BLOCK_SIZE 0x800 // 2 kB block
+#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
+#define RAM0_BLOCKS 4
+#define RAM0_BLOCK_SIZE 0x2000 // 8 kB blocks
#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY)
#define RAM0_BLOCKS 4
#define RAM0_BLOCK_SIZE 0x8000 // 32 kB blocks
#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY)
#define RAM0_BLOCKS 4
#define RAM0_BLOCK_SIZE 0x1000 // 4 kB blocks
+#elif defined(_SILICON_LABS_32B_SERIES_1) && defined(_EFM32_GIANT_FAMILY)
+#define RAM0_BLOCKS 8
+#define RAM0_BLOCK_SIZE 0x4000 // 16 kB blocks
+#define RAM1_BLOCKS 8
+#define RAM1_BLOCK_SIZE 0x4000 // 16 kB blocks
+#define RAM2_BLOCKS 4
+#define RAM2_BLOCK_SIZE 0x10000 // 64 kB blocks
#endif
#if defined(_SILICON_LABS_32B_SERIES_0)
@@ -155,10 +185,15 @@
#define RAM0_END RAM_MEM_END
#endif
+#if defined(CMU_STATUS_HFXOSHUNTOPTRDY)
+#define HFXO_STATUS_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY | CMU_STATUS_HFXOSHUNTOPTRDY)
+#elif defined(CMU_STATUS_HFXOPEAKDETRDY)
+#define HFXO_STATUS_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY)
+#endif
+
/** @endcond */
-
-#if defined( _EMU_DCDCCTRL_MASK )
+#if defined(_EMU_DCDCCTRL_MASK)
/* DCDCTODVDD output range min/max */
#if !defined(PWRCFG_DCDCTODVDD_VMIN)
#define PWRCFG_DCDCTODVDD_VMIN 1800
@@ -175,24 +210,23 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/* Static user configuration */
-#if defined( _EMU_DCDCCTRL_MASK )
+#if defined(_EMU_DCDCCTRL_MASK)
static uint16_t dcdcMaxCurrent_mA;
static uint16_t dcdcEm01LoadCurrent_mA;
static EMU_DcdcLnReverseCurrentControl_TypeDef dcdcReverseCurrentControl;
#endif
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
-static EMU_EM01Init_TypeDef vScaleEM01Config = {false};
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
+static EMU_EM01Init_TypeDef vScaleEM01Config = { false };
#endif
/** @endcond */
-
/*******************************************************************************
************************** LOCAL FUNCTIONS ********************************
******************************************************************************/
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
/* Convert from level to EM0 and 1 command bit */
__STATIC_INLINE uint32_t vScaleEM01Cmd(EMU_VScaleEM01_TypeDef level)
{
@@ -200,6 +234,17 @@
}
#endif
+#if defined(ERRATA_FIX_EMU_E110_ENABLE)
+SL_RAMFUNC_DECLARATOR static void __attribute__ ((noinline)) ramWFI(void);
+SL_RAMFUNC_DEFINITION_BEGIN
+static void __attribute__ ((noinline)) ramWFI(void)
+{
+ __WFI(); // Enter EM2 or EM3
+ *(volatile uint32_t*)4; // Clear faulty read data after wakeup
+}
+SL_RAMFUNC_DEFINITION_END
+#endif
+
/***************************************************************************//**
* @brief
* Save/restore/update oscillator, core clock and voltage scaling configuration on
@@ -211,8 +256,7 @@
* such configuration bits and is used to restore state if needed.
*
******************************************************************************/
-typedef enum
-{
+typedef enum {
emState_Save, /* Save EMU and CMU state */
emState_Restore, /* Restore and unlock */
} emState_TypeDef;
@@ -223,29 +267,25 @@
uint32_t cmuLocked;
static uint32_t cmuStatus;
static CMU_Select_TypeDef hfClock;
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
static uint8_t vScaleStatus;
#endif
-
/* Save or update state */
- if (action == emState_Save)
- {
+ if (action == emState_Save) {
/* Save configuration. */
cmuStatus = CMU->STATUS;
hfClock = CMU_ClockSelectGet(cmuClock_HF);
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
/* Save vscale */
EMU_VScaleWait();
vScaleStatus = (uint8_t)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK)
>> _EMU_STATUS_VSCALE_SHIFT);
#endif
- }
- else if (action == emState_Restore) /* Restore state */
- {
+ } else if (action == emState_Restore) { /* Restore state */
/* Apply saved configuration. */
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
- /* Restore EM0 and 1 voltage scaling level. EMU_VScaleWait() is called later,
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
+ /* Restore EM0 and 1 voltage scaling level. @ref EMU_VScaleWait() is called later,
just before HF clock select is set. */
EMU->CMD = vScaleEM01Cmd((EMU_VScaleEM01_TypeDef)vScaleStatus);
#endif
@@ -264,38 +304,34 @@
oscEnCmd |= ((cmuStatus & CMU_STATUS_LFRCOENS) ? CMU_OSCENCMD_LFRCOEN : 0);
oscEnCmd |= ((cmuStatus & CMU_STATUS_HFXOENS) ? CMU_OSCENCMD_HFXOEN : 0);
oscEnCmd |= ((cmuStatus & CMU_STATUS_LFXOENS) ? CMU_OSCENCMD_LFXOEN : 0);
-#if defined( _CMU_STATUS_USHFRCOENS_MASK )
+#if defined(_CMU_STATUS_USHFRCOENS_MASK)
oscEnCmd |= ((cmuStatus & CMU_STATUS_USHFRCOENS) ? CMU_OSCENCMD_USHFRCOEN : 0);
#endif
CMU->OSCENCMD = oscEnCmd;
-#if defined( _EMU_STATUS_VSCALE_MASK )
+#if defined(_EMU_STATUS_VSCALE_MASK)
/* Wait for upscale to complete and then restore selected clock */
EMU_VScaleWait();
#endif
- if (hfClock != cmuSelect_HFRCO)
- {
+ if (hfClock != cmuSelect_HFRCO) {
CMU_ClockSelectSet(cmuClock_HF, hfClock);
}
/* If HFRCO was disabled before entering Energy Mode, turn it off again */
/* as it is automatically enabled by wake up */
- if ( ! (cmuStatus & CMU_STATUS_HFRCOENS) )
- {
+ if ( !(cmuStatus & CMU_STATUS_HFRCOENS) ) {
CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS;
}
/* Restore CMU register locking */
- if (cmuLocked)
- {
+ if (cmuLocked) {
CMU_Lock();
}
}
}
-
-#if defined( ERRATA_FIX_EMU_E107_EN )
+#if defined(ERRATA_FIX_EMU_E107_ENABLE)
/* Get enable conditions for errata EMU_E107 fix. */
__STATIC_INLINE bool getErrataFixEmuE107En(void)
{
@@ -316,13 +352,13 @@
majorMinorRev |= (ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK)
>> _ROMTABLE_PID3_REVMINORLSB_SHIFT;
-#if defined( _EFM32_GECKO_FAMILY )
+#if defined(_EFM32_GECKO_FAMILY)
return (majorMinorRev <= 0x0103);
-#elif defined( _EFM32_TINY_FAMILY )
+#elif defined(_EFM32_TINY_FAMILY)
return (majorMinorRev <= 0x0102);
-#elif defined( _EFM32_GIANT_FAMILY )
+#elif defined(_EFM32_GIANT_FAMILY)
return (majorMinorRev <= 0x0103) || (majorMinorRev == 0x0204);
-#elif defined( _EFM32_WONDER_FAMILY )
+#elif defined(_EFM32_WONDER_FAMILY)
return (majorMinorRev == 0x0100);
#else
/* Zero Gecko and future families are not affected by errata EMU_E107 */
@@ -334,95 +370,81 @@
/* LP prepare / LN restore P/NFET count */
#define DCDC_LP_PFET_CNT 7
#define DCDC_LP_NFET_CNT 7
-#if defined( ERRATA_FIX_DCDC_FETCNT_SET_EN )
+#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE)
static void currentLimitersUpdate(void);
static void dcdcFetCntSet(bool lpModeSet)
{
uint32_t tmp;
static uint32_t emuDcdcMiscCtrlReg;
- if (lpModeSet)
- {
+ if (lpModeSet) {
emuDcdcMiscCtrlReg = EMU->DCDCMISCCTRL;
tmp = EMU->DCDCMISCCTRL
& ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK | _EMU_DCDCMISCCTRL_NFETCNT_MASK);
tmp |= (DCDC_LP_PFET_CNT << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT)
- | (DCDC_LP_NFET_CNT << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT);
+ | (DCDC_LP_NFET_CNT << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT);
EMU->DCDCMISCCTRL = tmp;
currentLimitersUpdate();
- }
- else
- {
+ } else {
EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg;
currentLimitersUpdate();
}
}
#endif
-#if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN )
+#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE)
static void dcdcHsFixLnBlock(void)
{
-#define EMU_DCDCSTATUS (* (volatile uint32_t *)(EMU_BASE + 0x7C))
+#define EMU_DCDCSTATUS (*(volatile uint32_t *)(EMU_BASE + 0x7C))
if ((errataFixDcdcHsState == errataFixDcdcHsTrimSet)
- || (errataFixDcdcHsState == errataFixDcdcHsBypassLn))
- {
+ || (errataFixDcdcHsState == errataFixDcdcHsBypassLn)) {
/* Wait for LNRUNNING */
- if ((EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE)
- {
- while (!(EMU_DCDCSTATUS & (0x1 << 16)));
+ if ((EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE) {
+ while (!(EMU_DCDCSTATUS & (0x1 << 16))) ;
}
errataFixDcdcHsState = errataFixDcdcHsLnWaitDone;
}
}
#endif
-
-#if defined( _EMU_CTRL_EM23VSCALE_MASK )
+#if defined(_EMU_CTRL_EM23VSCALE_MASK)
/* Configure EMU and CMU for EM2 and 3 voltage downscale */
static void vScaleDownEM23Setup(void)
{
uint32_t hfSrcClockFrequency;
EMU_VScaleEM23_TypeDef scaleEM23Voltage =
- (EMU_VScaleEM23_TypeDef)((EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK)
- >> _EMU_CTRL_EM23VSCALE_SHIFT);
+ (EMU_VScaleEM23_TypeDef)((EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK)
+ >> _EMU_CTRL_EM23VSCALE_SHIFT);
EMU_VScaleEM01_TypeDef currentEM01Voltage =
- (EMU_VScaleEM01_TypeDef)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK)
- >> _EMU_STATUS_VSCALE_SHIFT);
+ (EMU_VScaleEM01_TypeDef)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK)
+ >> _EMU_STATUS_VSCALE_SHIFT);
/* Wait until previous scaling is done. */
EMU_VScaleWait();
/* Inverse coding. */
- if ((uint32_t)scaleEM23Voltage > (uint32_t)currentEM01Voltage)
- {
+ if ((uint32_t)scaleEM23Voltage > (uint32_t)currentEM01Voltage) {
/* Set safe clock and wait-states. */
- if (scaleEM23Voltage == emuVScaleEM23_LowPower)
- {
+ if (scaleEM23Voltage == emuVScaleEM23_LowPower) {
hfSrcClockFrequency = CMU_ClockDivGet(cmuClock_HF) * CMU_ClockFreqGet(cmuClock_HF);
/* Set default low power voltage HFRCO band as HF clock. */
- if (hfSrcClockFrequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)
- {
+ if (hfSrcClockFrequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX) {
CMU_HFRCOBandSet(cmuHFRCOFreq_19M0Hz);
}
CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO);
- }
- else
- {
+ } else {
/* Other voltage scaling levels are not currently supported. */
EFM_ASSERT(false);
}
- }
- else
- {
+ } else {
/* Same voltage or hardware will scale to min(EMU_CTRL_EM23VSCALE, EMU_STATUS_VSCALE) */
}
}
#endif
/** @endcond */
-
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
@@ -451,6 +473,9 @@
* support detecting stable oscillator, and an asynchronous switch to the
* original oscillator. See CMU documentation. Such a feature is however
* outside the scope of the implementation in this function.
+ * @note
+ * If ERRATA_FIX_EMU_E110_ENABLE is active, the core's SLEEPONEXIT feature
+ * can not be used.
* @par
* If HFXO is re-enabled by this function, and NOT used to clock the core,
* this function will not wait for HFXO to stabilize. This must be considered
@@ -461,33 +486,37 @@
* upon entering EM2. It will thus remain enabled when returning to EM0
* regardless of the @p restore parameter.
* @par
- * If HFXO autostart and select is enabled by using CMU_HFXOAutostartEnable(),
+ * If HFXO autostart and select is enabled by using @ref CMU_HFXOAutostartEnable(),
* the starting and selecting of the core clocks will be identical to the user
* independently of the value of the @p restore parameter when waking up on
* the wakeup sources corresponding to the autostart and select setting.
* @par
- * If voltage scaling is supported, the restore parameter is true and the EM0
- * voltage scaling level is set higher than the EM2 level, then the EM0 level is
+ * If voltage scaling is supported, the restore parameter is true and the EM0
+ * voltage scaling level is set higher than the EM2 level, then the EM0 level is
* also restored.
*
* @param[in] restore
- * @li true - restore oscillators, clocks and voltage scaling, see function details.
- * @li false - do not restore oscillators and clocks, see function details.
+ * @li true - save and restore oscillators, clocks and voltage scaling, see
+ * function details.
+ * @li false - do not save and restore oscillators and clocks, see function
+ * details.
* @par
* The @p restore option should only be used if all clock control is done
* via the CMU API.
******************************************************************************/
void EMU_EnterEM2(bool restore)
{
-#if defined( ERRATA_FIX_EMU_E107_EN )
+#if defined(ERRATA_FIX_EMU_E107_ENABLE)
bool errataFixEmuE107En;
uint32_t nonWicIntEn[2];
#endif
- /* Save EMU and CMU state requiring restore on EM2 exit. */
- emState(emState_Save);
+ /* Only save EMU and CMU state if restored on wake-up. */
+ if (restore) {
+ emState(emState_Save);
+ }
-#if defined( _EMU_CTRL_EM23VSCALE_MASK )
+#if defined(_EMU_CTRL_EM23VSCALE_MASK)
vScaleDownEM23Setup();
#endif
@@ -496,10 +525,9 @@
/* Fix for errata EMU_E107 - store non-WIC interrupt enable flags.
Disable the enabled non-WIC interrupts. */
-#if defined( ERRATA_FIX_EMU_E107_EN )
+#if defined(ERRATA_FIX_EMU_E107_ENABLE)
errataFixEmuE107En = getErrataFixEmuE107En();
- if (errataFixEmuE107En)
- {
+ if (errataFixEmuE107En) {
nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0;
NVIC->ICER[0] = nonWicIntEn[0];
#if (NON_WIC_INT_MASK_1 != (~(0x0U)))
@@ -509,23 +537,26 @@
}
#endif
-#if defined( ERRATA_FIX_DCDC_FETCNT_SET_EN )
+#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE)
dcdcFetCntSet(true);
#endif
-#if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN )
+#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE)
dcdcHsFixLnBlock();
#endif
+#if defined(ERRATA_FIX_EMU_E110_ENABLE)
+ CORE_CRITICAL_SECTION(ramWFI(); )
+#else
__WFI();
+#endif
-#if defined( ERRATA_FIX_DCDC_FETCNT_SET_EN )
+#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE)
dcdcFetCntSet(false);
#endif
/* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */
-#if defined( ERRATA_FIX_EMU_E107_EN )
- if (errataFixEmuE107En)
- {
+#if defined(ERRATA_FIX_EMU_E107_ENABLE)
+ if (errataFixEmuE107En) {
NVIC->ISER[0] = nonWicIntEn[0];
#if (NON_WIC_INT_MASK_1 != (~(0x0U)))
NVIC->ISER[1] = nonWicIntEn[1];
@@ -534,12 +565,9 @@
#endif
/* Restore oscillators/clocks and voltage scaling if supported. */
- if (restore)
- {
+ if (restore) {
emState(emState_Restore);
- }
- else
- {
+ } else {
/* If not restoring, and original clock was not HFRCO, we have to */
/* update CMSIS core clock variable since HF clock has changed */
/* to HFRCO. */
@@ -547,7 +575,6 @@
}
}
-
/***************************************************************************//**
* @brief
* Enter energy mode 3 (EM3).
@@ -573,6 +600,9 @@
* and an asynchronous switch to the original oscillator. See CMU
* documentation. Such a feature is however outside the scope of the
* implementation in this function.
+ * @note
+ * If ERRATA_FIX_EMU_E110_ENABLE is active, the core's SLEEPONEXIT feature
+ * can not be used.
* @par
* If HFXO/LFXO/LFRCO are re-enabled by this function, and NOT used to clock
* the core, this function will not wait for those oscillators to stabilize.
@@ -583,13 +613,15 @@
* upon entering EM3. It will thus remain enabled when returning to EM0
* regardless of the @p restore parameter.
* @par
- * If voltage scaling is supported, the restore parameter is true and the EM0
- * voltage scaling level is set higher than the EM3 level, then the EM0 level is
+ * If voltage scaling is supported, the restore parameter is true and the EM0
+ * voltage scaling level is set higher than the EM3 level, then the EM0 level is
* also restored.
*
* @param[in] restore
- * @li true - restore oscillators, clocks and voltage scaling, see function details.
- * @li false - do not restore oscillators and clocks, see function details.
+ * @li true - save and restore oscillators, clocks and voltage scaling, see
+ * function details.
+ * @li false - do not save and restore oscillators and clocks, see function
+ * details.
* @par
* The @p restore option should only be used if all clock control is done
* via the CMU API.
@@ -598,15 +630,17 @@
{
uint32_t cmuLocked;
-#if defined( ERRATA_FIX_EMU_E107_EN )
+#if defined(ERRATA_FIX_EMU_E107_ENABLE)
bool errataFixEmuE107En;
uint32_t nonWicIntEn[2];
#endif
- /* Save EMU and CMU state requiring restore on EM2 exit. */
- emState(emState_Save);
+ /* Only save EMU and CMU state if restored on wake-up. */
+ if (restore) {
+ emState(emState_Save);
+ }
-#if defined( _EMU_CTRL_EM23VSCALE_MASK )
+#if defined(_EMU_CTRL_EM23VSCALE_MASK)
vScaleDownEM23Setup();
#endif
@@ -618,8 +652,7 @@
CMU->OSCENCMD = CMU_OSCENCMD_LFXODIS | CMU_OSCENCMD_LFRCODIS;
/* Restore CMU register locking */
- if (cmuLocked)
- {
+ if (cmuLocked) {
CMU_Lock();
}
@@ -628,10 +661,9 @@
/* Fix for errata EMU_E107 - store non-WIC interrupt enable flags.
Disable the enabled non-WIC interrupts. */
-#if defined( ERRATA_FIX_EMU_E107_EN )
+#if defined(ERRATA_FIX_EMU_E107_ENABLE)
errataFixEmuE107En = getErrataFixEmuE107En();
- if (errataFixEmuE107En)
- {
+ if (errataFixEmuE107En) {
nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0;
NVIC->ICER[0] = nonWicIntEn[0];
#if (NON_WIC_INT_MASK_1 != (~(0x0U)))
@@ -641,23 +673,26 @@
}
#endif
-#if defined( ERRATA_FIX_DCDC_FETCNT_SET_EN )
+#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE)
dcdcFetCntSet(true);
#endif
-#if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN )
+#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE)
dcdcHsFixLnBlock();
#endif
+#if defined(ERRATA_FIX_EMU_E110_ENABLE)
+ CORE_CRITICAL_SECTION(ramWFI(); )
+#else
__WFI();
+#endif
-#if defined( ERRATA_FIX_DCDC_FETCNT_SET_EN )
+#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE)
dcdcFetCntSet(false);
#endif
/* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */
-#if defined( ERRATA_FIX_EMU_E107_EN )
- if (errataFixEmuE107En)
- {
+#if defined(ERRATA_FIX_EMU_E107_ENABLE)
+ if (errataFixEmuE107En) {
NVIC->ISER[0] = nonWicIntEn[0];
#if (NON_WIC_INT_MASK_1 != (~(0x0U)))
NVIC->ISER[1] = nonWicIntEn[1];
@@ -666,12 +701,9 @@
#endif
/* Restore oscillators/clocks and voltage scaling if supported. */
- if (restore)
- {
+ if (restore) {
emState(emState_Restore);
- }
- else
- {
+ } else {
/* If not restoring, and original clock was not HFRCO, we have to */
/* update CMSIS core clock variable since HF clock has changed */
/* to HFRCO. */
@@ -679,13 +711,27 @@
}
}
+/***************************************************************************//**
+ * @brief
+ * Save CMU HF clock select state, oscillator enable and voltage scaling
+ * (if available) before @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called
+ * with the restore parameter set to false. Calling this function is
+ * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the
+ * restore parameter set to true, but it allows the state to be saved without
+ * going to sleep. The state can be restored manually by calling
+ * @ref EMU_Restore().
+ ******************************************************************************/
+void EMU_Save(void)
+{
+ emState(emState_Save);
+}
/***************************************************************************//**
* @brief
- * Restore CMU HF clock select state, oscillator enable and voltage scaling
- * (if available) after @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called
+ * Restore CMU HF clock select state, oscillator enable and voltage scaling
+ * (if available) after @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called
* with the restore parameter set to false. Calling this function is
- * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the
+ * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the
* restore parameter set to true, but it allows the application to evaluate the
* wakeup reason before restoring state.
******************************************************************************/
@@ -694,7 +740,6 @@
emState(emState_Restore);
}
-
/***************************************************************************//**
* @brief
* Enter energy mode 4 (EM4).
@@ -706,7 +751,7 @@
{
int i;
-#if defined( _EMU_EM4CTRL_EM4ENTRY_SHIFT )
+#if defined(_EMU_EM4CTRL_EM4ENTRY_SHIFT)
uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK)
| (2 << _EMU_EM4CTRL_EM4ENTRY_SHIFT);
uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK)
@@ -721,13 +766,11 @@
/* Make sure register write lock is disabled */
EMU_Unlock();
-#if defined( _EMU_EM4CTRL_MASK )
- if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S)
- {
+#if defined(_EMU_EM4CTRL_MASK)
+ if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S) {
uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK;
if (dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWNOISE
- || dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER)
- {
+ || dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER) {
/* DCDC is not supported in EM4S so we switch DCDC to bypass mode before
* entering EM4S */
EMU_DCDCModeSet(emuDcdcMode_Bypass);
@@ -735,9 +778,8 @@
}
#endif
-#if defined( _EMU_EM4CTRL_MASK ) && defined( ERRATA_FIX_EMU_E208_EN )
- if (EMU->EM4CTRL & EMU_EM4CTRL_EM4STATE_EM4H)
- {
+#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_ENABLE)
+ if (EMU->EM4CTRL & EMU_EM4CTRL_EM4STATE_EM4H) {
/* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H.
* Full description of errata fix can be found in the errata document. */
__disable_irq();
@@ -747,22 +789,21 @@
}
#endif
-#if defined( ERRATA_FIX_EMU_E108_EN )
+#if defined(ERRATA_FIX_EMU_E108_ENABLE)
/* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */
__disable_irq();
*(volatile uint32_t *)0x400C80E4 = 0;
#endif
-#if defined( ERRATA_FIX_DCDC_FETCNT_SET_EN )
+#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE)
dcdcFetCntSet(true);
#endif
-#if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN )
+#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE)
dcdcHsFixLnBlock();
#endif
- for (i = 0; i < 4; i++)
- {
-#if defined( _EMU_EM4CTRL_EM4ENTRY_SHIFT )
+ for (i = 0; i < 4; i++) {
+#if defined(_EMU_EM4CTRL_EM4ENTRY_SHIFT)
EMU->EM4CTRL = em4seq2;
EMU->EM4CTRL = em4seq3;
}
@@ -775,7 +816,7 @@
#endif
}
-#if defined( _EMU_EM4CTRL_MASK )
+#if defined(_EMU_EM4CTRL_MASK)
/***************************************************************************//**
* @brief
* Enter energy mode 4 hibernate (EM4H).
@@ -824,9 +865,9 @@
******************************************************************************/
void EMU_MemPwrDown(uint32_t blocks)
{
-#if defined( _EMU_MEMCTRL_MASK )
+#if defined(_EMU_MEMCTRL_MASK)
EMU->MEMCTRL = blocks & _EMU_MEMCTRL_MASK;
-#elif defined( _EMU_RAM0CTRL_MASK )
+#elif defined(_EMU_RAM0CTRL_MASK)
EMU->RAM0CTRL = blocks & _EMU_RAM0CTRL_MASK;
#else
(void)blocks;
@@ -871,14 +912,12 @@
{
uint32_t mask = 0;
- if (end == 0)
- {
+ if (end == 0) {
end = SRAM_BASE + SRAM_SIZE;
}
// Check to see if something in RAM0 can be powered down
- if (end > RAM0_END)
- {
+ if (end > RAM0_END) {
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) // EFM32xG12 and EFR32xG12
// Block 0 is 16 kB and cannot be powered off
mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000) << 0; // Block 1, 16 kB
@@ -893,17 +932,16 @@
mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000) << 3; // Block 4, 7 kB
#elif defined(RAM0_BLOCKS)
// These platforms have equally sized RAM blocks
- for (int i = 1; i < RAM0_BLOCKS; i++)
- {
+ for (int i = 1; i < RAM0_BLOCKS; i++) {
mask |= ADDRESS_NOT_IN_BLOCK(start, RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i - 1);
}
#endif
}
// Power down the selected blocks
-#if defined( _EMU_MEMCTRL_MASK )
+#if defined(_EMU_MEMCTRL_MASK)
EMU->MEMCTRL = EMU->MEMCTRL | mask;
-#elif defined( _EMU_RAM0CTRL_MASK )
+#elif defined(_EMU_RAM0CTRL_MASK)
EMU->RAM0CTRL = EMU->RAM0CTRL | mask;
#else
// These devices are unable to power down RAM blocks
@@ -913,15 +951,23 @@
#if defined(RAM1_MEM_END)
mask = 0;
- if (end > RAM1_MEM_END)
- {
- for (int i = 0; i < RAM1_BLOCKS; i++)
- {
+ if (end > RAM1_MEM_END) {
+ for (int i = 0; i < RAM1_BLOCKS; i++) {
mask |= ADDRESS_NOT_IN_BLOCK(start, RAM1_MEM_BASE + (i * RAM1_BLOCK_SIZE)) << i;
}
}
EMU->RAM1CTRL |= mask;
#endif
+
+#if defined(RAM2_MEM_END)
+ mask = 0;
+ if (end > RAM2_MEM_END) {
+ for (int i = 0; i < RAM2_BLOCKS; i++) {
+ mask |= ADDRESS_NOT_IN_BLOCK(start, RAM2_MEM_BASE + (i * RAM2_BLOCK_SIZE)) << i;
+ }
+ }
+ EMU->RAM2CTRL |= mask;
+#endif
}
#if defined(_EMU_EM23PERNORETAINCTRL_MASK)
@@ -947,7 +993,6 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Update EMU module with CMU oscillator selection/enable status.
@@ -960,8 +1005,7 @@
emState(emState_Save);
}
-
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
/***************************************************************************//**
* @brief
* Voltage scale in EM0 and 1 by clock frequency.
@@ -971,10 +1015,10 @@
* custom clock frequency is required if using a non-standard HFXO
* frequency.
* @param[in] wait
- * Wait for scaling to complate.
+ * Wait for scaling to complete.
*
* @note
- * This function is primarely needed by the @ref CMU module.
+ * This function is primarily needed by the @ref CMU module.
******************************************************************************/
void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait)
{
@@ -983,35 +1027,23 @@
>> _CMU_HFPRESC_PRESC_SHIFT);
/* VSCALE frequency is HFSRCCLK */
- if (clockFrequency == 0)
- {
+ if (clockFrequency == 0) {
hfSrcClockFrequency = SystemHFClockGet() * hfPresc;
- }
- else
- {
+ } else {
hfSrcClockFrequency = clockFrequency;
}
/* Apply EM0 and 1 voltage scaling command. */
if (vScaleEM01Config.vScaleEM01LowPowerVoltageEnable
- && (hfSrcClockFrequency < CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX))
- {
- EMU->CMD = vScaleEM01Cmd(emuVScaleEM01_LowPower);
- }
- else
- {
- EMU->CMD = vScaleEM01Cmd(emuVScaleEM01_HighPerformance);
- }
-
- if (wait)
- {
- EMU_VScaleWait();
+ && (hfSrcClockFrequency < CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) {
+ EMU_VScaleEM01(emuVScaleEM01_LowPower, wait);
+ } else {
+ EMU_VScaleEM01(emuVScaleEM01_HighPerformance, wait);
}
}
#endif
-
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
/***************************************************************************//**
* @brief
* Force voltage scaling in EM0 and 1 to a specific voltage level.
@@ -1035,23 +1067,36 @@
uint32_t hfSrcClockFrequency;
uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
>> _CMU_HFPRESC_PRESC_SHIFT);
- hfSrcClockFrequency = SystemHFClockGet() * hfPresc;
+ uint32_t hfFreq = SystemHFClockGet();
+ EMU_VScaleEM01_TypeDef current = EMU_VScaleGet();
- if (voltage == emuVScaleEM01_LowPower)
- {
+ if (current == voltage) {
+ /* Voltage is already at correct level. */
+ return;
+ }
+
+ hfSrcClockFrequency = hfFreq * hfPresc;
+
+ if (voltage == emuVScaleEM01_LowPower) {
EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX);
+ /* Update wait states before scaling down voltage */
+ CMU_UpdateWaitStates(hfFreq, emuVScaleEM01_LowPower);
}
EMU->CMD = vScaleEM01Cmd(voltage);
- if (wait)
- {
+
+ if (voltage == emuVScaleEM01_HighPerformance) {
+ /* Update wait states after scaling up voltage */
+ CMU_UpdateWaitStates(hfFreq, emuVScaleEM01_HighPerformance);
+ }
+
+ if (wait) {
EMU_VScaleWait();
}
}
#endif
-
-#if defined( _EMU_CMD_EM01VSCALE0_MASK )
+#if defined(_EMU_CMD_EM01VSCALE0_MASK)
/***************************************************************************//**
* @brief
* Update EMU module with Energy Mode 0 and 1 configuration
@@ -1067,7 +1112,6 @@
}
#endif
-
/***************************************************************************//**
* @brief
* Update EMU module with Energy Mode 2 and 3 configuration
@@ -1077,24 +1121,23 @@
******************************************************************************/
void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init)
{
-#if defined( _EMU_CTRL_EMVREG_MASK )
+#if defined(_EMU_CTRL_EMVREG_MASK)
EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EMVREG)
- : (EMU->CTRL & ~EMU_CTRL_EMVREG);
-#elif defined( _EMU_CTRL_EM23VREG_MASK )
+ : (EMU->CTRL & ~EMU_CTRL_EMVREG);
+#elif defined(_EMU_CTRL_EM23VREG_MASK)
EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EM23VREG)
- : (EMU->CTRL & ~EMU_CTRL_EM23VREG);
+ : (EMU->CTRL & ~EMU_CTRL_EM23VREG);
#else
(void)em23Init;
#endif
-#if defined( _EMU_CTRL_EM23VSCALE_MASK )
+#if defined(_EMU_CTRL_EM23VSCALE_MASK)
EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM23VSCALE_MASK)
| (em23Init->vScaleEM23Voltage << _EMU_CTRL_EM23VSCALE_SHIFT);
#endif
}
-
-#if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
+#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK)
/***************************************************************************//**
* @brief
* Update EMU module with Energy Mode 4 configuration
@@ -1104,7 +1147,7 @@
******************************************************************************/
void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init)
{
-#if defined( _EMU_EM4CONF_MASK )
+#if defined(_EMU_EM4CONF_MASK)
/* Init for platforms with EMU->EM4CONF register */
uint32_t em4conf = EMU->EM4CONF;
@@ -1112,18 +1155,20 @@
em4conf &= ~(_EMU_EM4CONF_LOCKCONF_MASK
| _EMU_EM4CONF_OSC_MASK
| _EMU_EM4CONF_BURTCWU_MASK
- | _EMU_EM4CONF_VREGEN_MASK);
+ | _EMU_EM4CONF_VREGEN_MASK
+ | _EMU_EM4CONF_BUBODRSTDIS_MASK);
/* Configure new settings */
em4conf |= (em4Init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT)
| (em4Init->osc)
| (em4Init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT)
- | (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT);
+ | (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT)
+ | (em4Init->buBodRstDis << _EMU_EM4CONF_BUBODRSTDIS_SHIFT);
/* Apply configuration. Note that lock can be set after this stage. */
EMU->EM4CONF = em4conf;
-#elif defined( _EMU_EM4CTRL_MASK )
+#elif defined(_EMU_EM4CTRL_MASK)
/* Init for platforms with EMU->EM4CTRL register */
uint32_t em4ctrl = EMU->EM4CTRL;
@@ -1135,23 +1180,22 @@
| _EMU_EM4CTRL_EM4IORETMODE_MASK);
em4ctrl |= (em4Init->retainLfxo ? EMU_EM4CTRL_RETAINLFXO : 0)
- | (em4Init->retainLfrco ? EMU_EM4CTRL_RETAINLFRCO : 0)
- | (em4Init->retainUlfrco ? EMU_EM4CTRL_RETAINULFRCO : 0)
- | (em4Init->em4State ? EMU_EM4CTRL_EM4STATE_EM4H : 0)
- | (em4Init->pinRetentionMode);
+ | (em4Init->retainLfrco ? EMU_EM4CTRL_RETAINLFRCO : 0)
+ | (em4Init->retainUlfrco ? EMU_EM4CTRL_RETAINULFRCO : 0)
+ | (em4Init->em4State ? EMU_EM4CTRL_EM4STATE_EM4H : 0)
+ | (em4Init->pinRetentionMode);
EMU->EM4CTRL = em4ctrl;
#endif
-#if defined( _EMU_CTRL_EM4HVSCALE_MASK )
+#if defined(_EMU_CTRL_EM4HVSCALE_MASK)
EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM4HVSCALE_MASK)
| (em4Init->vScaleEM4HVoltage << _EMU_CTRL_EM4HVSCALE_SHIFT);
#endif
}
#endif
-
-#if defined( BU_PRESENT )
+#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
/***************************************************************************//**
* @brief
* Configure Backup Power Domain settings
@@ -1209,7 +1253,6 @@
BUS_RegBitWrite(&(RMU->CTRL), _RMU_CTRL_BURSTEN_SHIFT, !bupdInit->enable);
}
-
/***************************************************************************//**
* @brief
* Configure Backup Power Domain BOD Threshold value
@@ -1220,23 +1263,21 @@
******************************************************************************/
void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value)
{
- EFM_ASSERT(value<8);
- EFM_ASSERT(value<=(_EMU_BUACT_BUEXTHRES_MASK>>_EMU_BUACT_BUEXTHRES_SHIFT));
+ EFM_ASSERT(value < 8);
+ EFM_ASSERT(value <= (_EMU_BUACT_BUEXTHRES_MASK >> _EMU_BUACT_BUEXTHRES_SHIFT));
- switch(mode)
- {
+ switch (mode) {
case emuBODMode_Active:
EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXTHRES_MASK)
- | (value<<_EMU_BUACT_BUEXTHRES_SHIFT);
+ | (value << _EMU_BUACT_BUEXTHRES_SHIFT);
break;
case emuBODMode_Inactive:
EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENTHRES_MASK)
- | (value<<_EMU_BUINACT_BUENTHRES_SHIFT);
+ | (value << _EMU_BUINACT_BUENTHRES_SHIFT);
break;
}
}
-
/***************************************************************************//**
* @brief
* Configure Backup Power Domain BOD Threshold Range
@@ -1248,46 +1289,43 @@
void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value)
{
EFM_ASSERT(value < 4);
- EFM_ASSERT(value<=(_EMU_BUACT_BUEXRANGE_MASK>>_EMU_BUACT_BUEXRANGE_SHIFT));
+ EFM_ASSERT(value <= (_EMU_BUACT_BUEXRANGE_MASK >> _EMU_BUACT_BUEXRANGE_SHIFT));
- switch(mode)
- {
+ switch (mode) {
case emuBODMode_Active:
EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXRANGE_MASK)
- | (value<<_EMU_BUACT_BUEXRANGE_SHIFT);
+ | (value << _EMU_BUACT_BUEXRANGE_SHIFT);
break;
case emuBODMode_Inactive:
EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENRANGE_MASK)
- | (value<<_EMU_BUINACT_BUENRANGE_SHIFT);
+ | (value << _EMU_BUINACT_BUENRANGE_SHIFT);
break;
}
}
#endif
-
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-#if defined( _EMU_DCDCCTRL_MASK )
+#if defined(_EMU_DCDCCTRL_MASK)
/* Translate fields with different names across platform generations to common names. */
-#if defined( _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK )
+#if defined(_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK)
#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK
#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT
-#elif defined( _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK )
+#elif defined(_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK)
#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK
#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT
#endif
-#if defined( _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK )
+#if defined(_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK)
#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK
#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT
-#elif defined( _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK )
+#elif defined(_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK)
#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK
#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT
#endif
/* Internal DCDC trim modes. */
-typedef enum
-{
+typedef enum {
dcdcTrimMode_EM234H_LP = 0,
-#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK )
+#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK)
dcdcTrimMode_EM01_LP,
#endif
dcdcTrimMode_LN,
@@ -1303,7 +1341,7 @@
******************************************************************************/
static bool dcdcConstCalibrationLoad(void)
{
-#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
uint32_t val;
volatile uint32_t *reg;
@@ -1315,8 +1353,7 @@
volatile uint32_t* const diCal_EMU_DCDCTRIM0 = (volatile uint32_t *)(0x0FE08058);
volatile uint32_t* const diCal_EMU_DCDCTRIM1 = (volatile uint32_t *)(0x0FE08060);
- if (DEVINFO->DCDCLPVCTRL0 != UINT_MAX)
- {
+ if (DEVINFO->DCDCLPVCTRL0 != UINT_MAX) {
val = *(diCal_EMU_DCDCLNFREQCTRL + 1);
reg = (volatile uint32_t *)*diCal_EMU_DCDCLNFREQCTRL;
*reg = val;
@@ -1352,7 +1389,6 @@
#endif
}
-
/***************************************************************************//**
* @brief
* Set recommended and validated current optimization and timing settings
@@ -1364,11 +1400,11 @@
#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1)
/* Comparator threshold on the high side */
#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2)
-#define EMU_DCDCSMCTRL (* (volatile uint32_t *)(EMU_BASE + 0x44))
+#define EMU_DCDCSMCTRL (*(volatile uint32_t *)(EMU_BASE + 0x44))
uint32_t lnForceCcm;
-#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
uint32_t dcdcTiming;
SYSTEM_ChipRevision_TypeDef rev;
#endif
@@ -1381,18 +1417,15 @@
* LNFORCECCM is default 0 for EFM32
*/
lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT);
- if (lnForceCcm)
- {
+ if (lnForceCcm) {
/* 7MHz is recommended for LNFORCECCM = 1 */
EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz);
- }
- else
- {
+ } else {
/* 3MHz is recommended for LNFORCECCM = 0 */
EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz);
}
-#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK;
EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LPCMPHYSDIS
| EMU_DCDCMISCCTRL_LPCMPHYSHI;
@@ -1400,15 +1433,14 @@
SYSTEM_ChipRevisionGet(&rev);
if ((rev.major == 1)
&& (rev.minor < 3)
- && (errataFixDcdcHsState == errataFixDcdcHsInit))
- {
+ && (errataFixDcdcHsState == errataFixDcdcHsInit)) {
/* LPCMPWAITDIS = 1 */
EMU_DCDCSMCTRL |= 1;
dcdcTiming = EMU->DCDCTIMING;
dcdcTiming &= ~(_EMU_DCDCTIMING_LPINITWAIT_MASK
- |_EMU_DCDCTIMING_LNWAIT_MASK
- |_EMU_DCDCTIMING_BYPWAIT_MASK);
+ | _EMU_DCDCTIMING_LNWAIT_MASK
+ | _EMU_DCDCTIMING_BYPWAIT_MASK);
dcdcTiming |= ((180 << _EMU_DCDCTIMING_LPINITWAIT_SHIFT)
| (12 << _EMU_DCDCTIMING_LNWAIT_SHIFT)
@@ -1420,7 +1452,6 @@
#endif
}
-
/***************************************************************************//**
* @brief
* Compute current limiters:
@@ -1435,11 +1466,11 @@
uint32_t pFetCnt;
uint16_t maxReverseCurrent_mA;
- /* 80mA as recommended peak in Application Note AN0948.
- The peak current is the average current plus 50% of the current ripple.
- Hence, a 14mA average current is recommended in LP mode. Since LP PFETCNT is also
- a constant, we get lpcLimImSel = 1. The following calculation is provided
- for documentation only. */
+ /* 80mA as recommended peak in Application Note AN0948.
+ The peak current is the average current plus 50% of the current ripple.
+ Hence, a 14mA average current is recommended in LP mode. Since LP PFETCNT is also
+ a constant, we get lpcLimImSel = 1. The following calculation is provided
+ for documentation only. */
const uint32_t lpcLim = (((14 + 40) + ((14 + 40) / 2))
/ (5 * (DCDC_LP_PFET_CNT + 1)))
- 1;
@@ -1447,7 +1478,7 @@
/* Get enabled PFETs */
pFetCnt = (EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_PFETCNT_MASK)
- >> _EMU_DCDCMISCCTRL_PFETCNT_SHIFT;
+ >> _EMU_DCDCMISCCTRL_PFETCNT_SHIFT;
/* Compute LN current limiter threshold from nominal user input current and
LN PFETCNT as described in the register description for
@@ -1459,7 +1490,7 @@
/* Saturate the register field value */
lncLimSel = SL_MIN(lncLimSel,
_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK
- >> _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT);
+ >> _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT);
lncLimSel <<= _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT;
@@ -1469,23 +1500,21 @@
EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK
| _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK))
- | (lncLimSel | lpcLimSel);
-
+ | (lncLimSel | lpcLimSel);
/* Compute reverse current limit threshold for the zero detector from user input
maximum reverse current and LN PFETCNT as described in the register description
for EMU_DCDCZDETCTRL_ZDETILIMSEL. */
- if (dcdcReverseCurrentControl >= 0)
- {
+ if (dcdcReverseCurrentControl >= 0) {
/* If dcdcReverseCurrentControl < 0, then EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care" */
maxReverseCurrent_mA = (uint16_t)dcdcReverseCurrentControl;
zdetLimSel = ( ((maxReverseCurrent_mA + 40) + ((maxReverseCurrent_mA + 40) / 2))
- / ((2 * (pFetCnt + 1)) + ((pFetCnt + 1) / 2)) );
+ / ((2 * (pFetCnt + 1)) + ((pFetCnt + 1) / 2)) );
/* Saturate the register field value */
zdetLimSel = SL_MIN(zdetLimSel,
_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK
- >> _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT);
+ >> _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT);
zdetLimSel <<= _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT;
@@ -1493,11 +1522,10 @@
EFM_ASSERT((zdetLimSel & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) == 0x0);
EMU->DCDCZDETCTRL = (EMU->DCDCZDETCTRL & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK)
- | zdetLimSel;
+ | zdetLimSel;
}
}
-
/***************************************************************************//**
* @brief
* Set static variables that hold the user set maximum peak current
@@ -1516,7 +1544,6 @@
dcdcReverseCurrentControl = reverseCurrentControl;
}
-
/***************************************************************************//**
* @brief
* Set DCDC low noise compensator control register
@@ -1526,8 +1553,7 @@
******************************************************************************/
static void compCtrlSet(EMU_DcdcLnCompCtrl_TypeDef comp)
{
- switch (comp)
- {
+ switch (comp) {
case emuDcdcLnCompCtrl_1u0F:
EMU->DCDCLNCOMPCTRL = 0x57204077UL;
break;
@@ -1573,41 +1599,35 @@
{
lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL0;
- if (lpAttenuation)
- {
+ if (lpAttenuation) {
lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK)
- >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT;
+ >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT;
+ } else {
+ lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK)
+ >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT;
}
- else
- {
- lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK)
- >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT;
- }
- }
- else
- {
+ } else {
/* devinfoRev >= 4: load LPCMPBIAS indexed calibration data */
lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL1;
- switch (lpCmpBias)
- {
+ switch (lpCmpBias) {
case 0:
lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK)
- >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT;
+ >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT;
break;
case 1:
lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK)
- >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT;
+ >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT;
break;
case 2:
lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK)
- >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT;
+ >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT;
break;
case 3:
lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK)
- >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT;
+ >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT;
break;
default:
@@ -1618,12 +1638,10 @@
}
/* Set trims */
- if (trimMode == dcdcTrimMode_EM234H_LP)
- {
+ if (trimMode == dcdcTrimMode_EM234H_LP) {
/* Make sure the sel value is within the field range. */
lpcmpHystSel <<= _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT;
- if (lpcmpHystSel & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK)
- {
+ if (lpcmpHystSel & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) {
EFM_ASSERT(false);
/* Return when assertions are disabled */
return false;
@@ -1631,13 +1649,11 @@
EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | lpcmpHystSel;
}
-#if defined( _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK )
- if (trimMode == dcdcTrimMode_EM01_LP)
- {
+#if defined(_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK)
+ if (trimMode == dcdcTrimMode_EM01_LP) {
/* Make sure the sel value is within the field range. */
lpcmpHystSel <<= _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT;
- if (lpcmpHystSel & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK)
- {
+ if (lpcmpHystSel & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) {
EFM_ASSERT(false);
/* Return when assertions are disabled */
return false;
@@ -1649,7 +1665,6 @@
return true;
}
-
/***************************************************************************//**
* @brief
* Load LPVREF low and high from DEVINFO.
@@ -1674,8 +1689,7 @@
/* Find VREF high and low in DEVINFO indexed by LPCMPBIAS (lpcmpBias)
and LPATT (lpAttenuation) */
uint32_t switchVal = (lpcmpBias << 8) | (lpAttenuation ? 1 : 0);
- switch (switchVal)
- {
+ switch (switchVal) {
case ((0 << 8) | 1):
vrefLow = DEVINFO->DCDCLPVCTRL2;
vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK)
@@ -1759,24 +1773,32 @@
******************************************************************************/
void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode)
{
- uint32_t currentDcdcMode = (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK);
+ uint32_t currentDcdcMode;
+
+ /* Wait for any previous write sync to complete and read DCDC mode. */
+ while (EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) ;
+ currentDcdcMode = (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK);
- if ((EMU_DcdcMode_TypeDef)currentDcdcMode == dcdcMode)
- {
- /* Mode already set - do nothing */
+ /* Enable bypass current limiter when not in bypass mode to prevent
+ excessive current between VREGVDD and DVDD supplies when reentering bypass mode. */
+ if (currentDcdcMode != EMU_DCDCCTRL_DCDCMODE_BYPASS) {
+ BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 1);
+ }
+
+ if ((EMU_DcdcMode_TypeDef)currentDcdcMode == dcdcMode) {
+ /* Mode already set. If already in bypass, make sure bypass current limiter
+ is disabled. */
+ if (dcdcMode == emuDcdcMode_Bypass) {
+ BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0);
+ }
return;
}
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
- while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY);
- /* Configure bypass current limiter */
- BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, dcdcMode == emuDcdcMode_Bypass ? 0 : 1);
-
/* Fix for errata DCDC_E203 */
- if (((EMU_DcdcMode_TypeDef)currentDcdcMode == emuDcdcMode_Bypass)
- && (dcdcMode == emuDcdcMode_LowNoise))
- {
+ if ((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS)
+ && (dcdcMode == emuDcdcMode_LowNoise)) {
errataFixDcdcHsState = errataFixDcdcHsBypassLn;
}
@@ -1784,22 +1806,25 @@
/* Fix for errata DCDC_E204 */
if (((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_OFF) || (currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS))
- && ((dcdcMode == emuDcdcMode_LowPower) || (dcdcMode == emuDcdcMode_LowNoise)))
- {
+ && ((dcdcMode == emuDcdcMode_LowPower) || (dcdcMode == emuDcdcMode_LowNoise))) {
/* Always start in LOWNOISE mode and then switch to LOWPOWER mode once LOWNOISE startup is complete. */
EMU_IntClear(EMU_IFC_DCDCLNRUNNING);
- while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY);
+ while (EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) ;
EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | EMU_DCDCCTRL_DCDCMODE_LOWNOISE;
- while(!(EMU_IntGet() & EMU_IF_DCDCLNRUNNING));
+ while (!(EMU_IntGet() & EMU_IF_DCDCLNRUNNING)) ;
}
#endif
/* Set user requested mode. */
- while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY);
+ while (EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) ;
EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | dcdcMode;
+
+ /* Disable bypass current limiter after bypass mode is entered.
+ Enable the limiter if any other mode is entered. */
+ while (EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) ;
+ BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, dcdcMode == emuDcdcMode_Bypass ? 0 : 1);
}
-
/***************************************************************************//**
* @brief
* Set DCDC LN regulator conduction mode
@@ -1822,26 +1847,19 @@
EMU_DCDCMISCCTRL_LNFORCECCM is set. Restore current DCDC mode. */
EMU_IntClear(EMU_IFC_DCDCINBYPASS);
EMU_DCDCModeSet(emuDcdcMode_Bypass);
- while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY);
- while(!(EMU_IntGet() & EMU_IF_DCDCINBYPASS));
- if (conductionMode == emuDcdcConductionMode_DiscontinuousLN)
- {
- EMU->DCDCMISCCTRL &= ~ EMU_DCDCMISCCTRL_LNFORCECCM;
- if (rcoDefaultSet)
- {
+ while (EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) ;
+ while (!(EMU_IntGet() & EMU_IF_DCDCINBYPASS)) ;
+ if (conductionMode == emuDcdcConductionMode_DiscontinuousLN) {
+ EMU->DCDCMISCCTRL &= ~EMU_DCDCMISCCTRL_LNFORCECCM;
+ if (rcoDefaultSet) {
EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz);
- }
- else
- {
+ } else {
/* emuDcdcConductionMode_DiscontinuousLN supports up to 4MHz LN RCO. */
EFM_ASSERT(rcoBand <= emuDcdcLnRcoBand_4MHz);
}
- }
- else
- {
+ } else {
EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LNFORCECCM;
- if (rcoDefaultSet)
- {
+ if (rcoDefaultSet) {
EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz);
}
}
@@ -1850,7 +1868,6 @@
EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA);
}
-
/***************************************************************************//**
* @brief
* Configure DCDC regulator
@@ -1858,7 +1875,7 @@
* @note
* If the power circuit is configured for NODCDC as described in Section
* 11.3.4.3 of the Reference Manual, do not call this function. Instead call
- * EMU_DCDCPowerOff().
+ * @ref EMU_DCDCPowerOff().
*
* @param[in] dcdcInit
* DCDC initialization structure
@@ -1877,8 +1894,7 @@
/* EMU->PWRCFG is write-once and POR reset only. Check that
we could set the desired power configuration. */
- if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != EMU_PWRCFG_PWRCFG_DCDCTODVDD)
- {
+ if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != EMU_PWRCFG_PWRCFG_DCDCTODVDD) {
/* If this assert triggers unexpectedly, please power cycle the
kit to reset the power configuration. */
EFM_ASSERT(false);
@@ -1895,14 +1911,12 @@
EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= dcdcInit->maxCurrent_mA);
EFM_ASSERT(dcdcInit->reverseCurrentControl <= 200);
- if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise)
- {
+ if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise) {
/* DCDC low-noise supports max 200mA */
EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 200);
}
#if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80)
- else if (dcdcInit->dcdcMode == emuDcdcMode_LowPower)
- {
+ else if (dcdcInit->dcdcMode == emuDcdcMode_LowPower) {
/* Up to 10mA is supported for EM01-LP mode. */
EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 10);
}
@@ -1911,20 +1925,13 @@
/* EM2/3/4 current above 10mA is not supported */
EFM_ASSERT(dcdcInit->em234LoadCurrent_uA <= 10000);
- if (dcdcInit->em234LoadCurrent_uA < 75)
- {
+ if (dcdcInit->em234LoadCurrent_uA < 75) {
lpCmpBiasSelEM234H = 0;
- }
- else if (dcdcInit->em234LoadCurrent_uA < 500)
- {
+ } else if (dcdcInit->em234LoadCurrent_uA < 500) {
lpCmpBiasSelEM234H = 1 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT;
- }
- else if (dcdcInit->em234LoadCurrent_uA < 2500)
- {
+ } else if (dcdcInit->em234LoadCurrent_uA < 2500) {
lpCmpBiasSelEM234H = 2 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT;
- }
- else
- {
+ } else {
lpCmpBiasSelEM234H = 3 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT;
}
@@ -1936,9 +1943,9 @@
=> Updates DCDCMISCCTRL_LNFORCECCM */
EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK
| _EMU_DCDCMISCCTRL_LNFORCECCM_MASK))
- | ((uint32_t)lpCmpBiasSelEM234H
- | (dcdcInit->reverseCurrentControl >= 0 ?
- EMU_DCDCMISCCTRL_LNFORCECCM : 0));
+ | ((uint32_t)lpCmpBiasSelEM234H
+ | (dcdcInit->reverseCurrentControl >= 0
+ ? EMU_DCDCMISCCTRL_LNFORCECCM : 0));
#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK)
/* Only 10mA EM01-LP current is supported */
EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK)
@@ -1951,7 +1958,7 @@
dcdcValidatedConfigSet();
/* 3. Updated static currents and limits user data.
- Limiters are updated in EMU_DCDCOptimizeSlice() */
+ Limiters are updated in @ref EMU_DCDCOptimizeSlice() */
userCurrentLimitsSet(dcdcInit->maxCurrent_mA,
dcdcInit->reverseCurrentControl);
dcdcEm01LoadCurrent_mA = dcdcInit->em01LoadCurrent_mA;
@@ -1970,14 +1977,13 @@
compCtrlSet(dcdcInit->dcdcLnCompCtrl);
/* Set DCDC output voltage */
- if (!EMU_DCDCOutputVoltageSet(dcdcInit->mVout, true, true))
- {
+ if (!EMU_DCDCOutputVoltageSet(dcdcInit->mVout, true, true)) {
EFM_ASSERT(false);
/* Return when assertions are disabled */
return false;
}
-#if ( _SILICON_LABS_GECKO_INTERNAL_SDID == 80 )
+#if (_SILICON_LABS_GECKO_INTERNAL_SDID == 80)
/* Select analog peripheral power supply. This must be done before
DCDC mode is set for all EFM32xG1 and EFR32xG1 devices. */
BUS_RegBitWrite(&EMU->PWRCTRL,
@@ -1992,11 +1998,11 @@
#endif
/* Set EM0 DCDC operating mode. Output voltage set in
- EMU_DCDCOutputVoltageSet() above takes effect if mode
+ @ref EMU_DCDCOutputVoltageSet() above takes effect if mode
is changed from bypass/off mode. */
EMU_DCDCModeSet(dcdcInit->dcdcMode);
-#if ( _SILICON_LABS_GECKO_INTERNAL_SDID != 80 )
+#if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80)
/* Select analog peripheral power supply. This must be done after
DCDC mode is set for all devices other than EFM32xG1 and EFR32xG1. */
BUS_RegBitWrite(&EMU->PWRCTRL,
@@ -2021,7 +2027,7 @@
bool setLpVoltage,
bool setLnVoltage)
{
-#if defined( _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK )
+#if defined(_DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK)
#define DCDC_TRIM_MODES ((uint8_t)dcdcTrimMode_LN + 1)
bool validOutVoltage;
@@ -2029,18 +2035,17 @@
uint32_t mVlow = 0;
uint32_t mVhigh = 0;
uint32_t mVdiff;
- uint32_t vrefVal[DCDC_TRIM_MODES] = {0};
- uint32_t vrefLow[DCDC_TRIM_MODES] = {0};
- uint32_t vrefHigh[DCDC_TRIM_MODES] = {0};
- uint8_t lpcmpBias[DCDC_TRIM_MODES] = {0};
+ uint32_t vrefVal[DCDC_TRIM_MODES] = { 0 };
+ uint32_t vrefLow[DCDC_TRIM_MODES] = { 0 };
+ uint32_t vrefHigh[DCDC_TRIM_MODES] = { 0 };
+ uint8_t lpcmpBias[DCDC_TRIM_MODES] = { 0 };
/* Check that the set voltage is within valid range.
Voltages are obtained from the datasheet. */
validOutVoltage = ((mV >= PWRCFG_DCDCTODVDD_VMIN)
&& (mV <= PWRCFG_DCDCTODVDD_VMAX));
- if (!validOutVoltage)
- {
+ if (!validOutVoltage) {
EFM_ASSERT(false);
/* Return when assertions are disabled */
return false;
@@ -2048,111 +2053,98 @@
/* Set attenuation to use and low/high range. */
attenuationSet = (mV > 1800);
- if (attenuationSet)
- {
+ if (attenuationSet) {
mVlow = 1800;
mVhigh = 3000;
mVdiff = mVhigh - mVlow;
- }
- else
- {
+ } else {
mVlow = 1200;
mVhigh = 1800;
mVdiff = mVhigh - mVlow;
}
- /* Get 2-point calib data from DEVINFO */
+ /* Get 2-point calib data from DEVINFO */
+
+ /* LN mode */
+ if (attenuationSet) {
+ vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0;
+ vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK)
+ >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT;
+ vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK)
+ >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT;
+ } else {
+ vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0;
+ vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK)
+ >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT;
+ vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK)
+ >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT;
+ }
- /* LN mode */
- if (attenuationSet)
- {
- vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0;
- vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK)
- >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT;
- vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK)
- >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT;
- }
- else
- {
- vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0;
- vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK)
- >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT;
- vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK)
- >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT;
- }
+ /* LP EM234H mode */
+ lpcmpBias[dcdcTrimMode_EM234H_LP] = (EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK)
+ >> _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT;
+ lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM234H_LP],
+ &vrefHigh[dcdcTrimMode_EM234H_LP],
+ attenuationSet,
+ lpcmpBias[dcdcTrimMode_EM234H_LP]);
-
- /* LP EM234H mode */
- lpcmpBias[dcdcTrimMode_EM234H_LP] = (EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK)
- >> _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT;
- lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM234H_LP],
- &vrefHigh[dcdcTrimMode_EM234H_LP],
- attenuationSet,
- lpcmpBias[dcdcTrimMode_EM234H_LP]);
-
-#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK )
- /* LP EM01 mode */
- lpcmpBias[dcdcTrimMode_EM01_LP] = (EMU->DCDCLPEM01CFG & _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK)
- >> _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT;
- lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM01_LP],
- &vrefHigh[dcdcTrimMode_EM01_LP],
- attenuationSet,
- lpcmpBias[dcdcTrimMode_EM01_LP]);
+#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK)
+ /* LP EM01 mode */
+ lpcmpBias[dcdcTrimMode_EM01_LP] = (EMU->DCDCLPEM01CFG & _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK)
+ >> _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT;
+ lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM01_LP],
+ &vrefHigh[dcdcTrimMode_EM01_LP],
+ attenuationSet,
+ lpcmpBias[dcdcTrimMode_EM01_LP]);
#endif
-
- /* Calculate output voltage trims */
- vrefVal[dcdcTrimMode_LN] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_LN] - vrefLow[dcdcTrimMode_LN]))
- / mVdiff;
- vrefVal[dcdcTrimMode_LN] += vrefLow[dcdcTrimMode_LN];
+ /* Calculate output voltage trims */
+ vrefVal[dcdcTrimMode_LN] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_LN] - vrefLow[dcdcTrimMode_LN]))
+ / mVdiff;
+ vrefVal[dcdcTrimMode_LN] += vrefLow[dcdcTrimMode_LN];
- vrefVal[dcdcTrimMode_EM234H_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM234H_LP] - vrefLow[dcdcTrimMode_EM234H_LP]))
- / mVdiff;
- vrefVal[dcdcTrimMode_EM234H_LP] += vrefLow[dcdcTrimMode_EM234H_LP];
+ vrefVal[dcdcTrimMode_EM234H_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM234H_LP] - vrefLow[dcdcTrimMode_EM234H_LP]))
+ / mVdiff;
+ vrefVal[dcdcTrimMode_EM234H_LP] += vrefLow[dcdcTrimMode_EM234H_LP];
-#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK )
- vrefVal[dcdcTrimMode_EM01_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM01_LP] - vrefLow[dcdcTrimMode_EM01_LP]))
- / mVdiff;
- vrefVal[dcdcTrimMode_EM01_LP] += vrefLow[dcdcTrimMode_EM01_LP];
+#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK)
+ vrefVal[dcdcTrimMode_EM01_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM01_LP] - vrefLow[dcdcTrimMode_EM01_LP]))
+ / mVdiff;
+ vrefVal[dcdcTrimMode_EM01_LP] += vrefLow[dcdcTrimMode_EM01_LP];
#endif
/* Range checks */
if ((vrefVal[dcdcTrimMode_LN] > vrefHigh[dcdcTrimMode_LN])
|| (vrefVal[dcdcTrimMode_LN] < vrefLow[dcdcTrimMode_LN])
-#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK )
+#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK)
|| (vrefVal[dcdcTrimMode_EM01_LP] > vrefHigh[dcdcTrimMode_EM01_LP])
|| (vrefVal[dcdcTrimMode_EM01_LP] < vrefLow[dcdcTrimMode_EM01_LP])
#endif
|| (vrefVal[dcdcTrimMode_EM234H_LP] > vrefHigh[dcdcTrimMode_EM234H_LP])
- || (vrefVal[dcdcTrimMode_EM234H_LP] < vrefLow[dcdcTrimMode_EM234H_LP]))
- {
+ || (vrefVal[dcdcTrimMode_EM234H_LP] < vrefLow[dcdcTrimMode_EM234H_LP])) {
EFM_ASSERT(false);
/* Return when assertions are disabled */
return false;
}
/* Update output voltage tuning for LN and LP modes. */
- if (setLnVoltage)
- {
+ if (setLnVoltage) {
EMU->DCDCLNVCTRL = (EMU->DCDCLNVCTRL & ~(_EMU_DCDCLNVCTRL_LNVREF_MASK | _EMU_DCDCLNVCTRL_LNATT_MASK))
- | (vrefVal[dcdcTrimMode_LN] << _EMU_DCDCLNVCTRL_LNVREF_SHIFT)
- | (attenuationSet ? EMU_DCDCLNVCTRL_LNATT : 0);
+ | (vrefVal[dcdcTrimMode_LN] << _EMU_DCDCLNVCTRL_LNVREF_SHIFT)
+ | (attenuationSet ? EMU_DCDCLNVCTRL_LNATT : 0);
}
- if (setLpVoltage)
- {
+ if (setLpVoltage) {
/* Load LP EM234H comparator hysteresis calibration */
- if(!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM234H_LP], dcdcTrimMode_EM234H_LP)))
- {
+ if (!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM234H_LP], dcdcTrimMode_EM234H_LP))) {
EFM_ASSERT(false);
/* Return when assertions are disabled */
return false;
}
-#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK )
+#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK)
/* Load LP EM234H comparator hysteresis calibration */
- if(!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM01_LP], dcdcTrimMode_EM01_LP)))
- {
+ if (!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM01_LP], dcdcTrimMode_EM01_LP))) {
EFM_ASSERT(false);
/* Return when assertions are disabled */
return false;
@@ -2165,14 +2157,13 @@
/* Don't exceed max available code as specified in the reference manual for EMU_DCDCLPVCTRL. */
vrefVal[dcdcTrimMode_EM234H_LP] = SL_MIN(vrefVal[dcdcTrimMode_EM234H_LP], 0xE7U);
EMU->DCDCLPVCTRL = (EMU->DCDCLPVCTRL & ~(_EMU_DCDCLPVCTRL_LPVREF_MASK | _EMU_DCDCLPVCTRL_LPATT_MASK))
- | (vrefVal[dcdcTrimMode_EM234H_LP] << _EMU_DCDCLPVCTRL_LPVREF_SHIFT)
- | (attenuationSet ? EMU_DCDCLPVCTRL_LPATT : 0);
+ | (vrefVal[dcdcTrimMode_EM234H_LP] << _EMU_DCDCLPVCTRL_LPVREF_SHIFT)
+ | (attenuationSet ? EMU_DCDCLPVCTRL_LPATT : 0);
}
#endif
return true;
}
-
/***************************************************************************//**
* @brief
* Optimize DCDC slice count based on the estimated average load current
@@ -2185,53 +2176,33 @@
{
uint32_t sliceCount = 0;
uint32_t rcoBand = (EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
- >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT;
+ >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT;
/* Set recommended slice count */
- if ((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) && (rcoBand >= emuDcdcLnRcoBand_5MHz))
- {
- if (em0LoadCurrent_mA < 20)
- {
+ if ((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) && (rcoBand >= emuDcdcLnRcoBand_5MHz)) {
+ if (em0LoadCurrent_mA < 20) {
sliceCount = 4;
- }
- else if ((em0LoadCurrent_mA >= 20) && (em0LoadCurrent_mA < 40))
- {
+ } else if ((em0LoadCurrent_mA >= 20) && (em0LoadCurrent_mA < 40)) {
sliceCount = 8;
- }
- else
- {
+ } else {
sliceCount = 16;
}
- }
- else if ((!(EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK)) && (rcoBand <= emuDcdcLnRcoBand_4MHz))
- {
- if (em0LoadCurrent_mA < 10)
- {
+ } else if ((!(EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK)) && (rcoBand <= emuDcdcLnRcoBand_4MHz)) {
+ if (em0LoadCurrent_mA < 10) {
sliceCount = 4;
- }
- else if ((em0LoadCurrent_mA >= 10) && (em0LoadCurrent_mA < 20))
- {
+ } else if ((em0LoadCurrent_mA >= 10) && (em0LoadCurrent_mA < 20)) {
sliceCount = 8;
- }
- else
- {
+ } else {
sliceCount = 16;
}
- }
- else if ((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) && (rcoBand <= emuDcdcLnRcoBand_4MHz))
- {
- if (em0LoadCurrent_mA < 40)
- {
+ } else if ((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) && (rcoBand <= emuDcdcLnRcoBand_4MHz)) {
+ if (em0LoadCurrent_mA < 40) {
sliceCount = 8;
- }
- else
- {
+ } else {
sliceCount = 16;
}
- }
- else
- {
- /* This configuration is not recommended. EMU_DCDCInit() applies a recommended
+ } else {
+ /* This configuration is not recommended. @ref EMU_DCDCInit() applies a recommended
configuration. */
EFM_ASSERT(false);
}
@@ -2266,7 +2237,7 @@
EFM_ASSERT((!forcedCcm && band <= emuDcdcLnRcoBand_4MHz) || forcedCcm);
EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
- | (band << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);
+ | (band << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);
/* Update slice configuration as this depends on the RCO band. */
EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA);
@@ -2279,7 +2250,7 @@
* @details
* This function powers off the DCDC controller. This function should only be
* used if the external power circuit is wired for no DCDC. If the external power
- * circuit is wired for DCDC usage, then use EMU_DCDCInit() and set the
+ * circuit is wired for DCDC usage, then use @ref EMU_DCDCInit() and set the
* DCDC in bypass mode to disable DCDC.
*
* @return
@@ -2303,7 +2274,7 @@
/* Set DCDC to OFF and disable LP in EM2/3/4. Verify that the required
mode could be set. */
- while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY);
+ while (EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) ;
EMU->DCDCCTRL = EMU_DCDCCTRL_DCDCMODE_OFF;
dcdcModeSet = (EMU->DCDCCTRL == EMU_DCDCCTRL_DCDCMODE_OFF);
@@ -2313,18 +2284,132 @@
}
#endif
-
-#if defined( EMU_STATUS_VMONRDY )
+#if defined(EMU_STATUS_VMONRDY)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-__STATIC_INLINE uint32_t vmonMilliVoltToCoarseThreshold(int mV)
+
+/***************************************************************************//**
+ * @brief
+ * Get calibrated threshold value.
+ *
+ * @details
+ * All VMON channels have two calibration fields in the DI page that
+ * describes the threshold at 1.86V and 2.98V. This function will convert
+ * the uncalibrated input voltage threshold in millivolts into a calibrated
+ * threshold.
+ *
+ * @param[in] channel
+ * VMON channel
+ *
+ * @param[in] threshold
+ * Desired threshold in millivolts.
+ *
+ * @return
+ * Calibrated threshold value to use. First digit of return value is placed
+ * in the "fine" register fields while the next digits are placed in the
+ * "coarse" register fields.
+ ******************************************************************************/
+static uint32_t vmonCalibratedThreshold(EMU_VmonChannel_TypeDef channel,
+ int threshold)
{
- return (mV - 1200) / 200;
+ uint32_t tLow;
+ uint32_t tHigh;
+ uint32_t calReg;
+
+ /* Get calibration values for 1.86V and 2.98V */
+ switch (channel) {
+ case emuVmonChannel_AVDD:
+ calReg = DEVINFO->VMONCAL0;
+ tLow = (10 * ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK)
+ >> _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT))
+ + ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK)
+ >> _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT);
+ tHigh = (10 * ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK)
+ >> _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT))
+ + ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK)
+ >> _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT);
+ break;
+ case emuVmonChannel_ALTAVDD:
+ calReg = DEVINFO->VMONCAL0;
+ tLow = (10 * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK)
+ >> _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT))
+ + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK)
+ >> _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT);
+ tHigh = (10 * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK)
+ >> _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT))
+ + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK)
+ >> _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT);
+ break;
+ case emuVmonChannel_DVDD:
+ calReg = DEVINFO->VMONCAL1;
+ tLow = (10 * ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK)
+ >> _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT))
+ + ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK)
+ >> _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT);
+ tHigh = (10 * ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK)
+ >> _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT))
+ + ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK)
+ >> _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT);
+ break;
+ case emuVmonChannel_IOVDD0:
+ calReg = DEVINFO->VMONCAL1;
+ tLow = (10 * ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK)
+ >> _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT))
+ + ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK)
+ >> _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT);
+ tHigh = (10 * ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK)
+ >> _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT))
+ + ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK)
+ >> _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT);
+ break;
+#if defined(_EMU_VMONIO1CTRL_EN_MASK)
+ case emuVmonChannel_IOVDD1:
+ calReg = DEVINFO->VMONCAL2;
+ tLow = (10 * ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_MASK)
+ >> _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_SHIFT))
+ + ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESFINE_MASK)
+ >> _DEVINFO_VMONCAL2_IO11V86THRESFINE_SHIFT);
+ tHigh = (10 * ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_MASK)
+ >> _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_SHIFT))
+ + ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESFINE_MASK)
+ >> _DEVINFO_VMONCAL2_IO12V98THRESFINE_SHIFT);
+ break;
+#endif
+#if defined(_EMU_VMONBUVDDCTRL_EN_MASK)
+ case emuVmonChannel_BUVDD:
+ calReg = DEVINFO->VMONCAL2;
+ tLow = (10 * ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_MASK)
+ >> _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_SHIFT))
+ + ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_MASK)
+ >> _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_SHIFT);
+ tHigh = (10 * ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_MASK)
+ >> _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_SHIFT))
+ + ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_MASK)
+ >> _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_SHIFT);
+ break;
+#endif
+ default:
+ EFM_ASSERT(false);
+ return threshold;
+ }
+
+ int32_t divisor = tHigh - tLow;
+ if (divisor <= 0) {
+ /* Uncalibrated device guard */
+ return threshold;
+ } else {
+ /* Calculate threshold.
+ *
+ * Note that volt is used in the reference manual, however we are interested
+ * in millivolt results. We also increase the precision of Va and Vb in the
+ * calculation instead of using floating points.
+ */
+ uint32_t va = (1120 * 100) / (divisor);
+ uint32_t vb = (1860 * 100) - (va * tLow);
+ /* Round threshold to nearest integer value. */
+ return ((threshold * 100) - vb + (va / 2)) / va;
+ }
}
-__STATIC_INLINE uint32_t vmonMilliVoltToFineThreshold(int mV, uint32_t coarseThreshold)
-{
- return (mV - 1200 - (coarseThreshold * 200)) / 20;
-}
/** @endcond */
/***************************************************************************//**
@@ -2334,7 +2419,8 @@
* @details
* Initialize a VMON channel without hysteresis. If the channel supports
* separate rise and fall triggers, both thresholds will be set to the same
- * value.
+ * value. The threshold will be converted to a register field value based
+ * on calibration values from the DI page.
*
* @param[in] vmonInit
* VMON initialization struct
@@ -2342,47 +2428,74 @@
void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit)
{
uint32_t thresholdCoarse, thresholdFine;
- EFM_ASSERT((vmonInit->threshold >= 1200) && (vmonInit->threshold <= 3980));
+ uint32_t threshold;
+
+ EFM_ASSERT((vmonInit->threshold >= 1620) && (vmonInit->threshold <= 3400));
- thresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->threshold);
- thresholdFine = vmonMilliVoltToFineThreshold(vmonInit->threshold, thresholdCoarse);
+ threshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->threshold);
+ thresholdFine = threshold % 10;
+ thresholdCoarse = threshold / 10;
+
+ /* Saturate threshold to max values. */
+ if (thresholdCoarse > 0xF) {
+ thresholdCoarse = 0xF;
+ thresholdFine = 9;
+ }
- switch(vmonInit->channel)
- {
- case emuVmonChannel_AVDD:
- EMU->VMONAVDDCTRL = (thresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT)
- | (thresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT)
- | (thresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT)
- | (thresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT)
- | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0)
- | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0)
- | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0);
- break;
- case emuVmonChannel_ALTAVDD:
- EMU->VMONALTAVDDCTRL = (thresholdCoarse << _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT)
- | (thresholdFine << _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT)
- | (vmonInit->riseWakeup ? EMU_VMONALTAVDDCTRL_RISEWU : 0)
- | (vmonInit->fallWakeup ? EMU_VMONALTAVDDCTRL_FALLWU : 0)
- | (vmonInit->enable ? EMU_VMONALTAVDDCTRL_EN : 0);
- break;
- case emuVmonChannel_DVDD:
- EMU->VMONDVDDCTRL = (thresholdCoarse << _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT)
- | (thresholdFine << _EMU_VMONDVDDCTRL_THRESFINE_SHIFT)
- | (vmonInit->riseWakeup ? EMU_VMONDVDDCTRL_RISEWU : 0)
- | (vmonInit->fallWakeup ? EMU_VMONDVDDCTRL_FALLWU : 0)
- | (vmonInit->enable ? EMU_VMONDVDDCTRL_EN : 0);
- break;
- case emuVmonChannel_IOVDD0:
- EMU->VMONIO0CTRL = (thresholdCoarse << _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT)
- | (thresholdFine << _EMU_VMONIO0CTRL_THRESFINE_SHIFT)
- | (vmonInit->retDisable ? EMU_VMONIO0CTRL_RETDIS : 0)
- | (vmonInit->riseWakeup ? EMU_VMONIO0CTRL_RISEWU : 0)
- | (vmonInit->fallWakeup ? EMU_VMONIO0CTRL_FALLWU : 0)
- | (vmonInit->enable ? EMU_VMONIO0CTRL_EN : 0);
- break;
- default:
- EFM_ASSERT(false);
- return;
+ switch (vmonInit->channel) {
+ case emuVmonChannel_AVDD:
+ EMU->VMONAVDDCTRL = (thresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT)
+ | (thresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT)
+ | (thresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT)
+ | (thresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT)
+ | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0)
+ | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0)
+ | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0);
+ break;
+ case emuVmonChannel_ALTAVDD:
+ EMU->VMONALTAVDDCTRL = (thresholdCoarse << _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT)
+ | (thresholdFine << _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT)
+ | (vmonInit->riseWakeup ? EMU_VMONALTAVDDCTRL_RISEWU : 0)
+ | (vmonInit->fallWakeup ? EMU_VMONALTAVDDCTRL_FALLWU : 0)
+ | (vmonInit->enable ? EMU_VMONALTAVDDCTRL_EN : 0);
+ break;
+ case emuVmonChannel_DVDD:
+ EMU->VMONDVDDCTRL = (thresholdCoarse << _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT)
+ | (thresholdFine << _EMU_VMONDVDDCTRL_THRESFINE_SHIFT)
+ | (vmonInit->riseWakeup ? EMU_VMONDVDDCTRL_RISEWU : 0)
+ | (vmonInit->fallWakeup ? EMU_VMONDVDDCTRL_FALLWU : 0)
+ | (vmonInit->enable ? EMU_VMONDVDDCTRL_EN : 0);
+ break;
+ case emuVmonChannel_IOVDD0:
+ EMU->VMONIO0CTRL = (thresholdCoarse << _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT)
+ | (thresholdFine << _EMU_VMONIO0CTRL_THRESFINE_SHIFT)
+ | (vmonInit->retDisable ? EMU_VMONIO0CTRL_RETDIS : 0)
+ | (vmonInit->riseWakeup ? EMU_VMONIO0CTRL_RISEWU : 0)
+ | (vmonInit->fallWakeup ? EMU_VMONIO0CTRL_FALLWU : 0)
+ | (vmonInit->enable ? EMU_VMONIO0CTRL_EN : 0);
+ break;
+#if defined(_EMU_VMONIO1CTRL_EN_MASK)
+ case emuVmonChannel_IOVDD1:
+ EMU->VMONIO1CTRL = (thresholdCoarse << _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT)
+ | (thresholdFine << _EMU_VMONIO1CTRL_THRESFINE_SHIFT)
+ | (vmonInit->retDisable ? EMU_VMONIO1CTRL_RETDIS : 0)
+ | (vmonInit->riseWakeup ? EMU_VMONIO1CTRL_RISEWU : 0)
+ | (vmonInit->fallWakeup ? EMU_VMONIO1CTRL_FALLWU : 0)
+ | (vmonInit->enable ? EMU_VMONIO1CTRL_EN : 0);
+ break;
+#endif
+#if defined(_EMU_VMONBUVDDCTRL_EN_MASK)
+ case emuVmonChannel_BUVDD:
+ EMU->VMONBUVDDCTRL = (thresholdCoarse << _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT)
+ | (thresholdFine << _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT)
+ | (vmonInit->riseWakeup ? EMU_VMONBUVDDCTRL_RISEWU : 0)
+ | (vmonInit->fallWakeup ? EMU_VMONBUVDDCTRL_FALLWU : 0)
+ | (vmonInit->enable ? EMU_VMONBUVDDCTRL_EN : 0);
+ break;
+#endif
+ default:
+ EFM_ASSERT(false);
+ return;
}
}
@@ -2392,39 +2505,40 @@
*
* @details
* Initialize a VMON channel which supports hysteresis. The AVDD channel is
- * the only channel to support separate rise and fall triggers.
+ * the only channel to support separate rise and fall triggers. The rise and
+ * fall thresholds will be converted to a register field value based on
+ * calibration values from the DI page.
*
* @param[in] vmonInit
* VMON Hysteresis initialization struct
******************************************************************************/
void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit)
{
- uint32_t riseThresholdCoarse, riseThresholdFine, fallThresholdCoarse, fallThresholdFine;
- /* VMON supports voltages between 1200 mV and 3980 mV (inclusive) in 20 mV increments */
- EFM_ASSERT((vmonInit->riseThreshold >= 1200) && (vmonInit->riseThreshold < 4000));
- EFM_ASSERT((vmonInit->fallThreshold >= 1200) && (vmonInit->fallThreshold < 4000));
+ uint32_t riseThreshold;
+ uint32_t fallThreshold;
+
+ /* VMON supports voltages between 1620 mV and 3400 mV (inclusive) */
+ EFM_ASSERT((vmonInit->riseThreshold >= 1620) && (vmonInit->riseThreshold <= 3400));
+ EFM_ASSERT((vmonInit->fallThreshold >= 1620) && (vmonInit->fallThreshold <= 3400));
/* Fall threshold has to be lower than rise threshold */
EFM_ASSERT(vmonInit->fallThreshold <= vmonInit->riseThreshold);
- riseThresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->riseThreshold);
- riseThresholdFine = vmonMilliVoltToFineThreshold(vmonInit->riseThreshold, riseThresholdCoarse);
- fallThresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->fallThreshold);
- fallThresholdFine = vmonMilliVoltToFineThreshold(vmonInit->fallThreshold, fallThresholdCoarse);
+ riseThreshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->riseThreshold);
+ fallThreshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->fallThreshold);
- switch(vmonInit->channel)
- {
- case emuVmonChannel_AVDD:
- EMU->VMONAVDDCTRL = (riseThresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT)
- | (riseThresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT)
- | (fallThresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT)
- | (fallThresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT)
- | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0)
- | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0)
- | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0);
- break;
- default:
- EFM_ASSERT(false);
- return;
+ switch (vmonInit->channel) {
+ case emuVmonChannel_AVDD:
+ EMU->VMONAVDDCTRL = ((riseThreshold / 10) << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT)
+ | ((riseThreshold % 10) << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT)
+ | ((fallThreshold / 10) << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT)
+ | ((fallThreshold % 10) << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT)
+ | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0)
+ | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0)
+ | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0);
+ break;
+ default:
+ EFM_ASSERT(false);
+ return;
}
}
@@ -2443,27 +2557,38 @@
uint32_t volatile * reg;
uint32_t bit;
- switch(channel)
- {
- case emuVmonChannel_AVDD:
- reg = &(EMU->VMONAVDDCTRL);
- bit = _EMU_VMONAVDDCTRL_EN_SHIFT;
- break;
- case emuVmonChannel_ALTAVDD:
- reg = &(EMU->VMONALTAVDDCTRL);
- bit = _EMU_VMONALTAVDDCTRL_EN_SHIFT;
- break;
- case emuVmonChannel_DVDD:
- reg = &(EMU->VMONDVDDCTRL);
- bit = _EMU_VMONDVDDCTRL_EN_SHIFT;
- break;
- case emuVmonChannel_IOVDD0:
- reg = &(EMU->VMONIO0CTRL);
- bit = _EMU_VMONIO0CTRL_EN_SHIFT;
- break;
- default:
- EFM_ASSERT(false);
- return;
+ switch (channel) {
+ case emuVmonChannel_AVDD:
+ reg = &(EMU->VMONAVDDCTRL);
+ bit = _EMU_VMONAVDDCTRL_EN_SHIFT;
+ break;
+ case emuVmonChannel_ALTAVDD:
+ reg = &(EMU->VMONALTAVDDCTRL);
+ bit = _EMU_VMONALTAVDDCTRL_EN_SHIFT;
+ break;
+ case emuVmonChannel_DVDD:
+ reg = &(EMU->VMONDVDDCTRL);
+ bit = _EMU_VMONDVDDCTRL_EN_SHIFT;
+ break;
+ case emuVmonChannel_IOVDD0:
+ reg = &(EMU->VMONIO0CTRL);
+ bit = _EMU_VMONIO0CTRL_EN_SHIFT;
+ break;
+#if defined(_EMU_VMONIO1CTRL_EN_MASK)
+ case emuVmonChannel_IOVDD1:
+ reg = &(EMU->VMONIO1CTRL);
+ bit = _EMU_VMONIO1CTRL_EN_SHIFT;
+ break;
+#endif
+#if defined(_EMU_VMONBUVDDCTRL_EN_MASK)
+ case emuVmonChannel_BUVDD:
+ reg = &(EMU->VMONBUVDDCTRL);
+ bit = _EMU_VMONBUVDDCTRL_EN_SHIFT;
+ break;
+#endif
+ default:
+ EFM_ASSERT(false);
+ return;
}
BUS_RegBitWrite(reg, bit, enable);
@@ -2482,30 +2607,39 @@
bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel)
{
uint32_t bit;
- switch(channel)
- {
- case emuVmonChannel_AVDD:
- bit = _EMU_STATUS_VMONAVDD_SHIFT;
- break;
- case emuVmonChannel_ALTAVDD:
- bit = _EMU_STATUS_VMONALTAVDD_SHIFT;
- break;
- case emuVmonChannel_DVDD:
- bit = _EMU_STATUS_VMONDVDD_SHIFT;
- break;
- case emuVmonChannel_IOVDD0:
- bit = _EMU_STATUS_VMONIO0_SHIFT;
- break;
- default:
- EFM_ASSERT(false);
- bit = 0;
+ switch (channel) {
+ case emuVmonChannel_AVDD:
+ bit = _EMU_STATUS_VMONAVDD_SHIFT;
+ break;
+ case emuVmonChannel_ALTAVDD:
+ bit = _EMU_STATUS_VMONALTAVDD_SHIFT;
+ break;
+ case emuVmonChannel_DVDD:
+ bit = _EMU_STATUS_VMONDVDD_SHIFT;
+ break;
+ case emuVmonChannel_IOVDD0:
+ bit = _EMU_STATUS_VMONIO0_SHIFT;
+ break;
+#if defined(_EMU_VMONIO1CTRL_EN_MASK)
+ case emuVmonChannel_IOVDD1:
+ bit = _EMU_STATUS_VMONIO1_SHIFT;
+ break;
+#endif
+#if defined(_EMU_VMONBUVDDCTRL_EN_MASK)
+ case emuVmonChannel_BUVDD:
+ bit = _EMU_STATUS_VMONBUVDD_SHIFT;
+ break;
+#endif
+ default:
+ EFM_ASSERT(false);
+ bit = 0;
}
return BUS_RegBitRead(&EMU->STATUS, bit);
}
#endif /* EMU_STATUS_VMONRDY */
-#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
/***************************************************************************//**
* @brief
* Adjust the bias refresh rate
@@ -2529,23 +2663,18 @@
uint32_t freq = 0x2u;
bool emuTestLocked = false;
- if (mode == emuBiasMode_1KHz)
- {
+ if (mode == emuBiasMode_1KHz) {
freq = 0x0u;
}
- if (EMU_TESTLOCK == 0x1u)
- {
+ if (EMU_TESTLOCK == 0x1u) {
emuTestLocked = true;
EMU_TESTLOCK = 0xADE8u;
}
- if (mode == emuBiasMode_Continuous)
- {
+ if (mode == emuBiasMode_Continuous) {
EMU_BIASCONF &= ~0x74u;
- }
- else
- {
+ } else {
EMU_BIASCONF |= 0x74u;
}
@@ -2554,8 +2683,7 @@
| ((freq & 0x3u) << 10u);
EMU_BIASTESTCTRL &= ~0x8u;
- if (emuTestLocked)
- {
+ if (emuTestLocked) {
EMU_TESTLOCK = 0u;
}
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpcrc.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpcrc.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file
* @brief General Purpose Cyclic Redundancy Check (GPCRC) API.
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -30,6 +30,7 @@
*
******************************************************************************/
+#include "em_common.h"
#include "em_gpcrc.h"
#include "em_assert.h"
@@ -73,29 +74,26 @@
void GPCRC_Init(GPCRC_TypeDef * gpcrc, const GPCRC_Init_TypeDef * init)
{
uint32_t polySelect;
+ uint32_t revPoly = 0;
- if (init->crcPoly == 0x04C11DB7)
- {
+ if (init->crcPoly == 0x04C11DB7) {
polySelect = GPCRC_CTRL_POLYSEL_CRC32;
- }
- else
- {
+ } else {
// If not using the fixed CRC-32 polynomial then we must be using 16-bit
EFM_ASSERT((init->crcPoly & 0xFFFF0000) == 0);
polySelect = GPCRC_CTRL_POLYSEL_16;
+ revPoly = SL_RBIT16(init->crcPoly);
}
gpcrc->CTRL = (((uint32_t)init->autoInit << _GPCRC_CTRL_AUTOINIT_SHIFT)
- | ((uint32_t)init->reverseByteOrder << _GPCRC_CTRL_BYTEREVERSE_SHIFT)
- | ((uint32_t)init->reverseBits << _GPCRC_CTRL_BITREVERSE_SHIFT)
- | ((uint32_t)init->enableByteMode << _GPCRC_CTRL_BYTEMODE_SHIFT)
- | polySelect
- | ((uint32_t)init->enable << _GPCRC_CTRL_EN_SHIFT));
+ | ((uint32_t)init->reverseByteOrder << _GPCRC_CTRL_BYTEREVERSE_SHIFT)
+ | ((uint32_t)init->reverseBits << _GPCRC_CTRL_BITREVERSE_SHIFT)
+ | ((uint32_t)init->enableByteMode << _GPCRC_CTRL_BYTEMODE_SHIFT)
+ | polySelect
+ | ((uint32_t)init->enable << _GPCRC_CTRL_EN_SHIFT));
- if (polySelect == GPCRC_CTRL_POLYSEL_16)
- {
+ if (polySelect == GPCRC_CTRL_POLYSEL_16) {
// Set CRC polynomial value
- uint32_t revPoly = __RBIT(init->crcPoly) >> 16;
gpcrc->POLY = revPoly & _GPCRC_POLY_POLY_MASK;
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c Thu Dec 07 14:01:42 2017 +0000
@@ -2,9 +2,9 @@
* @file em_gpio.c
* @brief General Purpose IO (GPIO) peripheral API
* devices.
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -31,7 +31,6 @@
*
******************************************************************************/
-
#include "em_gpio.h"
#if defined(GPIO_COUNT) && (GPIO_COUNT > 0)
@@ -60,12 +59,11 @@
/** Validation of pin typically usable in assert statements. */
#define GPIO_DRIVEMODE_VALID(mode) ((mode) <= 3)
-#define GPIO_STRENGHT_VALID(strenght) (!((strenght) & \
- ~(_GPIO_P_CTRL_DRIVESTRENGTH_MASK \
- | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK)))
+#define GPIO_STRENGHT_VALID(strenght) (!((strenght) \
+ & ~(_GPIO_P_CTRL_DRIVESTRENGTH_MASK \
+ | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK)))
/** @endcond */
-
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
@@ -82,11 +80,11 @@
******************************************************************************/
void GPIO_DbgLocationSet(unsigned int location)
{
-#if defined ( _GPIO_ROUTE_SWLOCATION_MASK )
+#if defined (_GPIO_ROUTE_SWLOCATION_MASK)
EFM_ASSERT(location < AFCHANLOC_MAX);
- GPIO->ROUTE = (GPIO->ROUTE & ~_GPIO_ROUTE_SWLOCATION_MASK) |
- (location << _GPIO_ROUTE_SWLOCATION_SHIFT);
+ GPIO->ROUTE = (GPIO->ROUTE & ~_GPIO_ROUTE_SWLOCATION_MASK)
+ | (location << _GPIO_ROUTE_SWLOCATION_SHIFT);
#else
(void)location;
#endif
@@ -138,8 +136,8 @@
* Configure GPIO external pin interrupt.
*
* @details
- * If reconfiguring a GPIO interrupt that is already enabled, it is generally
- * recommended to disable it first, see GPIO_Disable().
+ * It is recommended to disable interrupts before configuring a GPIO pin interrupt.
+ * See @ref GPIO_IntDisable() for more information.
*
* The actual GPIO interrupt handler must be in place before enabling the
* interrupt.
@@ -154,10 +152,10 @@
* On series 1 devices, pin number can be selected freely within a group.
* Interrupt numbers are divided into 4 groups (intNo / 4) and valid pin
* number within the interrupt groups are:
- * 0: pins 0-3
- * 1: pins 4-7
- * 2: pins 8-11
- * 3: pins 12-15
+ * 0: pins 0-3 (interrupt number 0-3)
+ * 1: pins 4-7 (interrupt number 4-7)
+ * 2: pins 8-11 (interrupt number 8-11)
+ * 3: pins 12-15 (interrupt number 12-15)
*
* @param[in] port
* The port to associate with @p pin.
@@ -176,7 +174,7 @@
*
* @param[in] enable
* Set to true if interrupt shall be enabled after configuration completed,
- * false to leave disabled. See GPIO_IntDisable() and GPIO_IntEnable().
+ * false to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable().
******************************************************************************/
void GPIO_ExtIntConfig(GPIO_Port_TypeDef port,
unsigned int pin,
@@ -198,15 +196,12 @@
/* There are two registers controlling the interrupt configuration:
* The EXTIPSELL register controls pins 0-7 and EXTIPSELH controls
* pins 8-15. */
- if (intNo < 8)
- {
+ if (intNo < 8) {
BUS_RegMaskedWrite(&GPIO->EXTIPSELL,
_GPIO_EXTIPSELL_EXTIPSEL0_MASK
<< (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo),
port << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo));
- }
- else
- {
+ } else {
tmp = intNo - 8;
BUS_RegMaskedWrite(&GPIO->EXTIPSELH,
_GPIO_EXTIPSELH_EXTIPSEL8_MASK
@@ -218,16 +213,13 @@
/* There are two registers controlling the interrupt/pin number mapping:
* The EXTIPINSELL register controls interrupt 0-7 and EXTIPINSELH controls
* interrupt 8-15. */
- if (intNo < 8)
- {
+ if (intNo < 8) {
BUS_RegMaskedWrite(&GPIO->EXTIPINSELL,
_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK
<< (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo),
((pin % 4) & _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK)
<< (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo));
- }
- else
- {
+ } else {
BUS_RegMaskedWrite(&GPIO->EXTIPINSELH,
_GPIO_EXTIPINSELH_EXTIPINSEL8_MASK
<< (_GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT * tmp),
@@ -275,39 +267,28 @@
/* If disabling pin, do not modify DOUT in order to reduce chance for */
/* glitch/spike (may not be sufficient precaution in all use cases) */
- if (mode != gpioModeDisabled)
- {
- if (out)
- {
+ if (mode != gpioModeDisabled) {
+ if (out) {
GPIO_PinOutSet(port, pin);
- }
- else
- {
+ } else {
GPIO_PinOutClear(port, pin);
}
}
/* There are two registers controlling the pins for each port. The MODEL
* register controls pins 0-7 and MODEH controls pins 8-15. */
- if (pin < 8)
- {
+ if (pin < 8) {
GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xFu << (pin * 4)))
| (mode << (pin * 4));
- }
- else
- {
+ } else {
GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xFu << ((pin - 8) * 4)))
| (mode << ((pin - 8) * 4));
}
- if (mode == gpioModeDisabled)
- {
- if (out)
- {
+ if (mode == gpioModeDisabled) {
+ if (out) {
GPIO_PinOutSet(port, pin);
- }
- else
- {
+ } else {
GPIO_PinOutClear(port, pin);
}
}
@@ -331,17 +312,14 @@
{
EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
- if (pin < 8)
- {
+ if (pin < 8) {
return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEL >> (pin * 4)) & 0xF);
- }
- else
- {
+ } else {
return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEH >> ((pin - 8) * 4)) & 0xF);
}
}
-#if defined( _GPIO_EM4WUEN_MASK )
+#if defined(_GPIO_EM4WUEN_MASK)
/**************************************************************************//**
* @brief
* Enable GPIO pin wake-up from EM4. When the function exits,
@@ -362,11 +340,11 @@
{
EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0);
-#if defined( _GPIO_EM4WUPOL_MASK )
+#if defined(_GPIO_EM4WUPOL_MASK)
EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0);
GPIO->EM4WUPOL &= ~pinmask; /* Set wakeup polarity */
GPIO->EM4WUPOL |= pinmask & polaritymask;
-#elif defined( _GPIO_EXTILEVEL_MASK )
+#elif defined(_GPIO_EXTILEVEL_MASK)
EFM_ASSERT((polaritymask & ~_GPIO_EXTILEVEL_MASK) == 0);
GPIO->EXTILEVEL &= ~pinmask;
GPIO->EXTILEVEL |= pinmask & polaritymask;
@@ -375,9 +353,9 @@
GPIO_EM4SetPinRetention(true); /* Enable pin retention */
-#if defined( _GPIO_CMD_EM4WUCLR_MASK )
+#if defined(_GPIO_CMD_EM4WUCLR_MASK)
GPIO->CMD = GPIO_CMD_EM4WUCLR; /* Clear wake-up logic */
-#elif defined( _GPIO_IFC_EM4WU_MASK )
+#elif defined(_GPIO_IFC_EM4WU_MASK)
GPIO_IntClear(pinmask);
#endif
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_i2c.c
* @brief Inter-integrated Circuit (I2C) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -66,7 +66,7 @@
#elif (I2C_COUNT == 2)
#define I2C_REF_VALID(ref) ((ref == I2C0) || (ref == I2C1))
#elif (I2C_COUNT == 3)
-#define I2C_REF_VALID(ref) ((ref == I2C0) || (ref == I2C1)|| (ref == I2C2))
+#define I2C_REF_VALID(ref) ((ref == I2C0) || (ref == I2C1) || (ref == I2C2))
#endif
/** Error flags indicating I2C transfer has failed somehow. */
@@ -77,9 +77,9 @@
#define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST)
/* Max I2C transmission rate constant */
-#if defined( _SILICON_LABS_32B_SERIES_0 )
+#if defined(_SILICON_LABS_32B_SERIES_0)
#define I2C_CR_MAX 4
-#elif defined( _SILICON_LABS_32B_SERIES_1 )
+#elif defined(_SILICON_LABS_32B_SERIES_1)
#define I2C_CR_MAX 8
#else
#warning "Max I2C transmission rate constant is not defined"
@@ -94,8 +94,7 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** Master mode transfer states. */
-typedef enum
-{
+typedef enum {
i2cStateStartAddrSend, /**< Send start + (first part of) address. */
i2cStateAddrWFAckNack, /**< Wait for ACK/NACK on (first part of) address. */
i2cStateAddrWF2ndAckNack, /**< Wait for ACK/NACK on second part of 10 bit address. */
@@ -117,8 +116,7 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** Structure used to store state information on an ongoing master mode transfer. */
-typedef struct
-{
+typedef struct {
/** Current state. */
I2C_TransferState_TypeDef state;
@@ -186,7 +184,6 @@
return (freqHfper / ((n * (i2c->CLKDIV + 1)) + I2C_CR_MAX));
}
-
/***************************************************************************//**
* @brief
* Set I2C bus frequency.
@@ -234,8 +231,7 @@
/* Avoid divide by 0 */
EFM_ASSERT(freqScl);
- if (!freqScl)
- {
+ if (!freqScl) {
return;
}
@@ -243,45 +239,39 @@
i2c->CTRL &= ~_I2C_CTRL_CLHR_MASK;
BUS_RegMaskedWrite(&i2c->CTRL,
_I2C_CTRL_CLHR_MASK,
- i2cMode <<_I2C_CTRL_CLHR_SHIFT);
+ i2cMode << _I2C_CTRL_CLHR_SHIFT);
- if (!freqRef)
- {
+ if (!freqRef) {
freqRef = CMU_ClockFreqGet(cmuClock_HFPER);
}
- /* Check minumum HF peripheral clock */
+ /* Check minumum HF peripheral clock */
minFreq = UINT_MAX;
- if (i2c->CTRL & I2C_CTRL_SLAVE)
- {
- switch(i2cMode)
- {
+ if (i2c->CTRL & I2C_CTRL_SLAVE) {
+ switch (i2cMode) {
case i2cClockHLRStandard:
-#if defined( _SILICON_LABS_32B_SERIES_0 )
+#if defined(_SILICON_LABS_32B_SERIES_0)
minFreq = 4200000; break;
-#elif defined( _SILICON_LABS_32B_SERIES_1 )
+#elif defined(_SILICON_LABS_32B_SERIES_1)
minFreq = 2000000; break;
#endif
case i2cClockHLRAsymetric:
-#if defined( _SILICON_LABS_32B_SERIES_0 )
+#if defined(_SILICON_LABS_32B_SERIES_0)
minFreq = 11000000; break;
-#elif defined( _SILICON_LABS_32B_SERIES_1 )
+#elif defined(_SILICON_LABS_32B_SERIES_1)
minFreq = 5000000; break;
#endif
case i2cClockHLRFast:
-#if defined( _SILICON_LABS_32B_SERIES_0 )
+#if defined(_SILICON_LABS_32B_SERIES_0)
minFreq = 24400000; break;
-#elif defined( _SILICON_LABS_32B_SERIES_1 )
+#elif defined(_SILICON_LABS_32B_SERIES_1)
minFreq = 14000000; break;
#endif
}
- }
- else
- {
+ } else {
/* For master mode, platform 1 and 2 share the same
min frequencies */
- switch(i2cMode)
- {
+ switch (i2cMode) {
case i2cClockHLRStandard:
minFreq = 2000000; break;
case i2cClockHLRAsymetric:
@@ -311,14 +301,12 @@
/* Clock divisor must be at least 1 in slave mode according to reference */
/* manual (in which case there is normally no need to set bus frequency). */
- if ((i2c->CTRL & I2C_CTRL_SLAVE) && !div)
- {
+ if ((i2c->CTRL & I2C_CTRL_SLAVE) && !div) {
div = 1;
}
i2c->CLKDIV = (uint32_t)div;
}
-
/***************************************************************************//**
* @brief
* Enable/disable I2C.
@@ -339,7 +327,6 @@
BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, enable);
}
-
/***************************************************************************//**
* @brief
* Initialize I2C.
@@ -365,7 +352,6 @@
BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, init->enable);
}
-
/***************************************************************************//**
* @brief
* Reset I2C to same state as after a HW reset.
@@ -388,7 +374,6 @@
/* Do not reset route register, setting should be done independently */
}
-
/***************************************************************************//**
* @brief
* Continue an initiated I2C transfer (single master mode only).
@@ -435,38 +420,35 @@
EFM_ASSERT(I2C_REF_VALID(i2c));
/* Support up to 2 I2C buses */
- if (i2c == I2C0)
- {
+ if (i2c == I2C0) {
transfer = i2cTransfer;
}
#if (I2C_COUNT > 1)
- else if (i2c == I2C1)
- {
+ else if (i2c == I2C1) {
transfer = i2cTransfer + 1;
}
#endif
- else
- {
+#if (I2C_COUNT > 2)
+ else if (i2c == I2C2) {
+ transfer = i2cTransfer + 2;
+ }
+#endif
+ else {
return i2cTransferUsageFault;
}
seq = transfer->seq;
- for (;; )
- {
+ for (;; ) {
pending = i2c->IF;
/* If some sort of fault, abort transfer. */
- if (pending & I2C_IF_ERRORS)
- {
- if (pending & I2C_IF_ARBLOST)
- {
+ if (pending & I2C_IF_ERRORS) {
+ if (pending & I2C_IF_ARBLOST) {
/* If arbitration fault, it indicates either a slave device */
/* not responding as expected, or other master which is not */
/* supported by this SW. */
transfer->result = i2cTransferArbLost;
- }
- else if (pending & I2C_IF_BUSERR)
- {
+ } else if (pending & I2C_IF_BUSERR) {
/* A bus error indicates a misplaced start or stop, which should */
/* not occur in master mode controlled by this SW. */
transfer->result = i2cTransferBusErr;
@@ -479,306 +461,258 @@
goto done;
}
- switch (transfer->state)
- {
- /***************************************************/
- /* Send first start+address (first byte if 10 bit) */
- /***************************************************/
- case i2cStateStartAddrSend:
- if (seq->flags & I2C_FLAG_10BIT_ADDR)
- {
- tmp = (((uint32_t)(seq->addr) >> 8) & 0x06) | 0xf0;
+ switch (transfer->state) {
+ /***************************************************/
+ /* Send first start+address (first byte if 10 bit) */
+ /***************************************************/
+ case i2cStateStartAddrSend:
+ if (seq->flags & I2C_FLAG_10BIT_ADDR) {
+ tmp = (((uint32_t)(seq->addr) >> 8) & 0x06) | 0xf0;
+
+ /* In 10 bit address mode, the address following the first */
+ /* start always indicate write. */
+ } else {
+ tmp = (uint32_t)(seq->addr) & 0xfe;
+
+ if (seq->flags & I2C_FLAG_READ) {
+ /* Indicate read request */
+ tmp |= 1;
+ }
+ }
+
+ transfer->state = i2cStateAddrWFAckNack;
+ i2c->TXDATA = tmp;/* Data not transmitted until START sent */
+ i2c->CMD = I2C_CMD_START;
+ goto done;
+
+ /*******************************************************/
+ /* Wait for ACK/NACK on address (first byte if 10 bit) */
+ /*******************************************************/
+ case i2cStateAddrWFAckNack:
+ if (pending & I2C_IF_NACK) {
+ i2c->IFC = I2C_IFC_NACK;
+ transfer->result = i2cTransferNack;
+ transfer->state = i2cStateWFStopSent;
+ i2c->CMD = I2C_CMD_STOP;
+ } else if (pending & I2C_IF_ACK) {
+ i2c->IFC = I2C_IFC_ACK;
- /* In 10 bit address mode, the address following the first */
- /* start always indicate write. */
- }
- else
- {
- tmp = (uint32_t)(seq->addr) & 0xfe;
+ /* If 10 bit address, send 2nd byte of address. */
+ if (seq->flags & I2C_FLAG_10BIT_ADDR) {
+ transfer->state = i2cStateAddrWF2ndAckNack;
+ i2c->TXDATA = (uint32_t)(seq->addr) & 0xff;
+ } else {
+ /* Determine whether receiving or sending data */
+ if (seq->flags & I2C_FLAG_READ) {
+ transfer->state = i2cStateWFData;
+ if (seq->buf[transfer->bufIndx].len == 1) {
+ i2c->CMD = I2C_CMD_NACK;
+ }
+ } else {
+ transfer->state = i2cStateDataSend;
+ continue;
+ }
+ }
+ }
+ goto done;
- if (seq->flags & I2C_FLAG_READ)
- {
+ /******************************************************/
+ /* Wait for ACK/NACK on second byte of 10 bit address */
+ /******************************************************/
+ case i2cStateAddrWF2ndAckNack:
+ if (pending & I2C_IF_NACK) {
+ i2c->IFC = I2C_IFC_NACK;
+ transfer->result = i2cTransferNack;
+ transfer->state = i2cStateWFStopSent;
+ i2c->CMD = I2C_CMD_STOP;
+ } else if (pending & I2C_IF_ACK) {
+ i2c->IFC = I2C_IFC_ACK;
+
+ /* If using plain read sequence with 10 bit address, switch to send */
+ /* repeated start. */
+ if (seq->flags & I2C_FLAG_READ) {
+ transfer->state = i2cStateRStartAddrSend;
+ }
+ /* Otherwise expected to write 0 or more bytes */
+ else {
+ transfer->state = i2cStateDataSend;
+ }
+ continue;
+ }
+ goto done;
+
+ /*******************************/
+ /* Send repeated start+address */
+ /*******************************/
+ case i2cStateRStartAddrSend:
+ if (seq->flags & I2C_FLAG_10BIT_ADDR) {
+ tmp = ((seq->addr >> 8) & 0x06) | 0xf0;
+ } else {
+ tmp = seq->addr & 0xfe;
+ }
+
+ /* If this is a write+read combined sequence, then read is about to start */
+ if (seq->flags & I2C_FLAG_WRITE_READ) {
/* Indicate read request */
tmp |= 1;
}
- }
- transfer->state = i2cStateAddrWFAckNack;
- i2c->TXDATA = tmp; /* Data not transmitted until START sent */
- i2c->CMD = I2C_CMD_START;
- goto done;
+ transfer->state = i2cStateRAddrWFAckNack;
+ /* We have to write START cmd first since repeated start, otherwise */
+ /* data would be sent first. */
+ i2c->CMD = I2C_CMD_START;
+ i2c->TXDATA = tmp;
+ goto done;
- /*******************************************************/
- /* Wait for ACK/NACK on address (first byte if 10 bit) */
- /*******************************************************/
- case i2cStateAddrWFAckNack:
- if (pending & I2C_IF_NACK)
- {
- i2c->IFC = I2C_IFC_NACK;
- transfer->result = i2cTransferNack;
- transfer->state = i2cStateWFStopSent;
- i2c->CMD = I2C_CMD_STOP;
- }
- else if (pending & I2C_IF_ACK)
- {
- i2c->IFC = I2C_IFC_ACK;
+ /**********************************************************************/
+ /* Wait for ACK/NACK on repeated start+address (first byte if 10 bit) */
+ /**********************************************************************/
+ case i2cStateRAddrWFAckNack:
+ if (pending & I2C_IF_NACK) {
+ i2c->IFC = I2C_IFC_NACK;
+ transfer->result = i2cTransferNack;
+ transfer->state = i2cStateWFStopSent;
+ i2c->CMD = I2C_CMD_STOP;
+ } else if (pending & I2C_IF_ACK) {
+ i2c->IFC = I2C_IFC_ACK;
- /* If 10 bit address, send 2nd byte of address. */
- if (seq->flags & I2C_FLAG_10BIT_ADDR)
- {
- transfer->state = i2cStateAddrWF2ndAckNack;
- i2c->TXDATA = (uint32_t)(seq->addr) & 0xff;
- }
- else
- {
/* Determine whether receiving or sending data */
- if (seq->flags & I2C_FLAG_READ)
- {
+ if (seq->flags & I2C_FLAG_WRITE_READ) {
transfer->state = i2cStateWFData;
- if(seq->buf[transfer->bufIndx].len==1)
- {
- i2c->CMD = I2C_CMD_NACK;
- }
- }
- else
- {
+ } else {
transfer->state = i2cStateDataSend;
continue;
}
}
- }
- goto done;
-
- /******************************************************/
- /* Wait for ACK/NACK on second byte of 10 bit address */
- /******************************************************/
- case i2cStateAddrWF2ndAckNack:
- if (pending & I2C_IF_NACK)
- {
- i2c->IFC = I2C_IFC_NACK;
- transfer->result = i2cTransferNack;
- transfer->state = i2cStateWFStopSent;
- i2c->CMD = I2C_CMD_STOP;
- }
- else if (pending & I2C_IF_ACK)
- {
- i2c->IFC = I2C_IFC_ACK;
+ goto done;
- /* If using plain read sequence with 10 bit address, switch to send */
- /* repeated start. */
- if (seq->flags & I2C_FLAG_READ)
- {
- transfer->state = i2cStateRStartAddrSend;
- }
- /* Otherwise expected to write 0 or more bytes */
- else
- {
- transfer->state = i2cStateDataSend;
- }
- continue;
- }
- goto done;
-
- /*******************************/
- /* Send repeated start+address */
- /*******************************/
- case i2cStateRStartAddrSend:
- if (seq->flags & I2C_FLAG_10BIT_ADDR)
- {
- tmp = ((seq->addr >> 8) & 0x06) | 0xf0;
- }
- else
- {
- tmp = seq->addr & 0xfe;
- }
+ /*****************************/
+ /* Send a data byte to slave */
+ /*****************************/
+ case i2cStateDataSend:
+ /* Reached end of data buffer? */
+ if (transfer->offset >= seq->buf[transfer->bufIndx].len) {
+ /* Move to next message part */
+ transfer->offset = 0;
+ transfer->bufIndx++;
- /* If this is a write+read combined sequence, then read is about to start */
- if (seq->flags & I2C_FLAG_WRITE_READ)
- {
- /* Indicate read request */
- tmp |= 1;
- }
-
- transfer->state = i2cStateRAddrWFAckNack;
- /* We have to write START cmd first since repeated start, otherwise */
- /* data would be sent first. */
- i2c->CMD = I2C_CMD_START;
- i2c->TXDATA = tmp;
- goto done;
-
- /**********************************************************************/
- /* Wait for ACK/NACK on repeated start+address (first byte if 10 bit) */
- /**********************************************************************/
- case i2cStateRAddrWFAckNack:
- if (pending & I2C_IF_NACK)
- {
- i2c->IFC = I2C_IFC_NACK;
- transfer->result = i2cTransferNack;
- transfer->state = i2cStateWFStopSent;
- i2c->CMD = I2C_CMD_STOP;
- }
- else if (pending & I2C_IF_ACK)
- {
- i2c->IFC = I2C_IFC_ACK;
+ /* Send repeated start when switching to read mode on 2nd buffer */
+ if (seq->flags & I2C_FLAG_WRITE_READ) {
+ transfer->state = i2cStateRStartAddrSend;
+ continue;
+ }
- /* Determine whether receiving or sending data */
- if (seq->flags & I2C_FLAG_WRITE_READ)
- {
- transfer->state = i2cStateWFData;
- }
- else
- {
- transfer->state = i2cStateDataSend;
- continue;
- }
- }
- goto done;
+ /* Only writing from one buffer, or finished both buffers */
+ if ((seq->flags & I2C_FLAG_WRITE) || (transfer->bufIndx > 1)) {
+ transfer->state = i2cStateWFStopSent;
+ i2c->CMD = I2C_CMD_STOP;
+ goto done;
+ }
- /*****************************/
- /* Send a data byte to slave */
- /*****************************/
- case i2cStateDataSend:
- /* Reached end of data buffer? */
- if (transfer->offset >= seq->buf[transfer->bufIndx].len)
- {
- /* Move to next message part */
- transfer->offset = 0;
- transfer->bufIndx++;
-
- /* Send repeated start when switching to read mode on 2nd buffer */
- if (seq->flags & I2C_FLAG_WRITE_READ)
- {
- transfer->state = i2cStateRStartAddrSend;
+ /* Reprocess in case next buffer is empty */
continue;
}
- /* Only writing from one buffer, or finished both buffers */
- if ((seq->flags & I2C_FLAG_WRITE) || (transfer->bufIndx > 1))
- {
- transfer->state = i2cStateWFStopSent;
- i2c->CMD = I2C_CMD_STOP;
- goto done;
- }
-
- /* Reprocess in case next buffer is empty */
- continue;
- }
-
- /* Send byte */
- i2c->TXDATA = (uint32_t)(seq->buf[transfer->bufIndx].data[transfer->offset++]);
- transfer->state = i2cStateDataWFAckNack;
- goto done;
+ /* Send byte */
+ i2c->TXDATA = (uint32_t)(seq->buf[transfer->bufIndx].data[transfer->offset++]);
+ transfer->state = i2cStateDataWFAckNack;
+ goto done;
- /*********************************************************/
- /* Wait for ACK/NACK from slave after sending data to it */
- /*********************************************************/
- case i2cStateDataWFAckNack:
- if (pending & I2C_IF_NACK)
- {
- i2c->IFC = I2C_IFC_NACK;
- transfer->result = i2cTransferNack;
- transfer->state = i2cStateWFStopSent;
- i2c->CMD = I2C_CMD_STOP;
- }
- else if (pending & I2C_IF_ACK)
- {
- i2c->IFC = I2C_IFC_ACK;
- transfer->state = i2cStateDataSend;
- continue;
- }
- goto done;
+ /*********************************************************/
+ /* Wait for ACK/NACK from slave after sending data to it */
+ /*********************************************************/
+ case i2cStateDataWFAckNack:
+ if (pending & I2C_IF_NACK) {
+ i2c->IFC = I2C_IFC_NACK;
+ transfer->result = i2cTransferNack;
+ transfer->state = i2cStateWFStopSent;
+ i2c->CMD = I2C_CMD_STOP;
+ } else if (pending & I2C_IF_ACK) {
+ i2c->IFC = I2C_IFC_ACK;
+ transfer->state = i2cStateDataSend;
+ continue;
+ }
+ goto done;
- /****************************/
- /* Wait for data from slave */
- /****************************/
- case i2cStateWFData:
- if (pending & I2C_IF_RXDATAV)
- {
- uint8_t data;
- unsigned int rxLen = seq->buf[transfer->bufIndx].len;
-
- /* Must read out data in order to not block further progress */
- data = (uint8_t)(i2c->RXDATA);
+ /****************************/
+ /* Wait for data from slave */
+ /****************************/
+ case i2cStateWFData:
+ if (pending & I2C_IF_RXDATAV) {
+ uint8_t data;
+ unsigned int rxLen = seq->buf[transfer->bufIndx].len;
- /* Make sure not storing beyond end of buffer just in case */
- if (transfer->offset < rxLen)
- {
- seq->buf[transfer->bufIndx].data[transfer->offset++] = data;
- }
+ /* Must read out data in order to not block further progress */
+ data = (uint8_t)(i2c->RXDATA);
- /* If we have read all requested data, then the sequence should end */
- if (transfer->offset >= rxLen)
- {
- /* If there is only one byte to receive we need to transmit the
- NACK now, before the stop. */
- if (1 == rxLen)
- {
- i2c->CMD = I2C_CMD_NACK;
+ /* Make sure not storing beyond end of buffer just in case */
+ if (transfer->offset < rxLen) {
+ seq->buf[transfer->bufIndx].data[transfer->offset++] = data;
}
- transfer->state = i2cStateWFStopSent;
- i2c->CMD = I2C_CMD_STOP;
- }
- else
- {
- /* Send ACK and wait for next byte */
- i2c->CMD = I2C_CMD_ACK;
+ /* If we have read all requested data, then the sequence should end */
+ if (transfer->offset >= rxLen) {
+ /* If there is only one byte to receive we need to transmit the
+ NACK now, before the stop. */
+ if (1 == rxLen) {
+ i2c->CMD = I2C_CMD_NACK;
+ }
- if ( (1<rxLen) && (transfer->offset == (rxLen-1)) )
- {
- /* If there is more than one byte to receive and this is the next
- to last byte we need to transmit the NACK now, before receiving
- the last byte. */
- i2c->CMD = I2C_CMD_NACK;
+ transfer->state = i2cStateWFStopSent;
+ i2c->CMD = I2C_CMD_STOP;
+ } else {
+ /* Send ACK and wait for next byte */
+ i2c->CMD = I2C_CMD_ACK;
+
+ if ( (1 < rxLen) && (transfer->offset == (rxLen - 1)) ) {
+ /* If there is more than one byte to receive and this is the next
+ to last byte we need to transmit the NACK now, before receiving
+ the last byte. */
+ i2c->CMD = I2C_CMD_NACK;
+ }
}
}
- }
- goto done;
+ goto done;
- /***********************************/
- /* Wait for STOP to have been sent */
- /***********************************/
- case i2cStateWFStopSent:
- if (pending & I2C_IF_MSTOP)
- {
- i2c->IFC = I2C_IFC_MSTOP;
- transfer->state = i2cStateDone;
- }
- goto done;
+ /***********************************/
+ /* Wait for STOP to have been sent */
+ /***********************************/
+ case i2cStateWFStopSent:
+ if (pending & I2C_IF_MSTOP) {
+ i2c->IFC = I2C_IFC_MSTOP;
+ transfer->state = i2cStateDone;
+ }
+ goto done;
- /******************************/
- /* Unexpected state, SW fault */
- /******************************/
- default:
- transfer->result = i2cTransferSwFault;
- transfer->state = i2cStateDone;
- goto done;
+ /******************************/
+ /* Unexpected state, SW fault */
+ /******************************/
+ default:
+ transfer->result = i2cTransferSwFault;
+ transfer->state = i2cStateDone;
+ goto done;
}
}
- done:
+ done:
- if (transfer->state == i2cStateDone)
- {
+ if (transfer->state == i2cStateDone) {
/* Disable interrupt sources when done */
i2c->IEN = 0;
/* Update result unless some fault already occurred */
- if (transfer->result == i2cTransferInProgress)
- {
+ if (transfer->result == i2cTransferInProgress) {
transfer->result = i2cTransferDone;
}
}
/* Until transfer is done keep returning i2cTransferInProgress */
- else
- {
+ else {
return i2cTransferInProgress;
}
return transfer->result;
}
-
/***************************************************************************//**
* @brief
* Prepare and start an I2C transfer (single master mode only).
@@ -813,25 +747,26 @@
EFM_ASSERT(seq);
/* Support up to 2 I2C buses */
- if (i2c == I2C0)
- {
+ if (i2c == I2C0) {
transfer = i2cTransfer;
}
#if (I2C_COUNT > 1)
- else if (i2c == I2C1)
- {
+ else if (i2c == I2C1) {
transfer = i2cTransfer + 1;
}
#endif
- else
- {
+#if (I2C_COUNT > 2)
+ else if (i2c == I2C2) {
+ transfer = i2cTransfer + 2;
+ }
+#endif
+ else {
return i2cTransferUsageFault;
}
/* Check if in busy state. Since this SW assumes single master, we can */
/* just issue an abort. The BUSY state is normal after a reset. */
- if (i2c->STATE & I2C_STATE_BUSY)
- {
+ if (i2c->STATE & I2C_STATE_BUSY) {
i2c->CMD = I2C_CMD_ABORT;
}
@@ -839,10 +774,9 @@
/* possible according to I2C spec, since slave will always start */
/* sending first byte ACK on address. The read operation can */
/* only be stopped by NACKing a received byte, ie minimum 1 byte. */
- if (((seq->flags & I2C_FLAG_READ) && !(seq->buf[0].len)) ||
- ((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len))
- )
- {
+ if (((seq->flags & I2C_FLAG_READ) && !(seq->buf[0].len))
+ || ((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len))
+ ) {
return i2cTransferUsageFault;
}
@@ -855,8 +789,7 @@
/* Ensure buffers are empty */
i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX;
- if (i2c->IF & I2C_IF_RXDATAV)
- {
+ if (i2c->IF & I2C_IF_RXDATAV) {
(void)i2c->RXDATA;
}
@@ -866,8 +799,8 @@
/* Enable those interrupts we are interested in throughout transfer. */
/* Notice that the I2C interrupt must also be enabled in the NVIC, but */
/* that is left for an additional driver wrapper. */
- i2c->IEN |= I2C_IF_NACK | I2C_IF_ACK | I2C_IF_MSTOP |
- I2C_IF_RXDATAV | I2C_IF_ERRORS;
+ i2c->IEN |= I2C_IF_NACK | I2C_IF_ACK | I2C_IF_MSTOP
+ | I2C_IF_RXDATAV | I2C_IF_ERRORS;
/* Start transfer */
return I2C_Transfer(i2c);
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_idac.c
* @brief Current Digital to Analog Converter (IDAC) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -48,8 +48,8 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/* Fix for errata IDAC_E101 - IDAC output current degradation */
-#if defined(_SILICON_LABS_32B_SERIES_0) \
- && (defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY))
+#if defined(_SILICON_LABS_32B_SERIES_0) \
+ && (defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY))
#define ERRATA_FIX_IDAC_E101_EN
#endif
/** @endcond */
@@ -58,7 +58,6 @@
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
-
/***************************************************************************//**
* @brief
* Initialize IDAC.
@@ -86,27 +85,23 @@
tmp |= init->outMode;
- if (init->enable)
- {
+ if (init->enable) {
tmp |= IDAC_CTRL_EN;
}
- if (init->prsEnable)
- {
+ if (init->prsEnable) {
#if defined(_IDAC_CTRL_OUTENPRS_MASK)
tmp |= IDAC_CTRL_OUTENPRS;
#else
tmp |= IDAC_CTRL_APORTOUTENPRS;
#endif
}
- if (init->sinkEnable)
- {
+ if (init->sinkEnable) {
tmp |= IDAC_CTRL_CURSINK;
}
idac->CTRL = tmp;
}
-
/***************************************************************************//**
* @brief
* Enable/disable IDAC.
@@ -123,7 +118,6 @@
BUS_RegBitWrite(&idac->CTRL, _IDAC_CTRL_EN_SHIFT, enable);
}
-
/***************************************************************************//**
* @brief
* Reset IDAC to same state as after a HW reset.
@@ -144,8 +138,8 @@
idac->CTRL = _IDAC_CTRL_RESETVALUE | IDAC_CTRL_EN;
/* Set lowest current (50 nA) */
- idac->CURPROG = IDAC_CURPROG_RANGESEL_RANGE0 |
- (0x0 << _IDAC_CURPROG_STEPSEL_SHIFT);
+ idac->CURPROG = IDAC_CURPROG_RANGESEL_RANGE0
+ | (0x0 << _IDAC_CURPROG_STEPSEL_SHIFT);
/* Enable duty-cycling for all energy modes */
idac->DUTYCONFIG = IDAC_DUTYCONFIG_DUTYCYCLEEN;
@@ -154,12 +148,11 @@
idac->CURPROG = _IDAC_CURPROG_RESETVALUE;
idac->DUTYCONFIG = _IDAC_DUTYCONFIG_RESETVALUE;
#endif
-#if defined ( _IDAC_CAL_MASK )
+#if defined (_IDAC_CAL_MASK)
idac->CAL = _IDAC_CAL_RESETVALUE;
#endif
}
-
/***************************************************************************//**
* @brief
* Enable/disable Minimal Output Transition mode.
@@ -176,7 +169,6 @@
BUS_RegBitWrite(&idac->CTRL, _IDAC_CTRL_MINOUTTRANS_SHIFT, enable);
}
-
/***************************************************************************//**
* @brief
* Set the current range of the IDAC output.
@@ -196,7 +188,7 @@
void IDAC_RangeSet(IDAC_TypeDef *idac, const IDAC_Range_TypeDef range)
{
uint32_t tmp;
-#if defined( _IDAC_CURPROG_TUNING_MASK )
+#if defined(_IDAC_CURPROG_TUNING_MASK)
uint32_t diCal0;
uint32_t diCal1;
#endif
@@ -205,11 +197,10 @@
EFM_ASSERT(((uint32_t)range >> _IDAC_CURPROG_RANGESEL_SHIFT)
<= (_IDAC_CURPROG_RANGESEL_MASK >> _IDAC_CURPROG_RANGESEL_SHIFT));
-#if defined ( _IDAC_CAL_MASK )
+#if defined (_IDAC_CAL_MASK)
/* Load proper calibration data depending on selected range */
- switch ((IDAC_Range_TypeDef)range)
- {
+ switch ((IDAC_Range_TypeDef)range) {
case idacCurrentRange0:
idac->CAL = (DEVINFO->IDAC0CAL0 & _DEVINFO_IDAC0CAL0_RANGE0_MASK)
>> _DEVINFO_IDAC0CAL0_RANGE0_SHIFT;
@@ -231,7 +222,7 @@
tmp = idac->CURPROG & ~_IDAC_CURPROG_RANGESEL_MASK;
tmp |= (uint32_t)range;
-#elif defined( _IDAC_CURPROG_TUNING_MASK )
+#elif defined(_IDAC_CURPROG_TUNING_MASK)
/* Load calibration data depending on selected range and sink/source mode */
/* TUNING (calibration) field in CURPROG register. */
@@ -241,10 +232,8 @@
tmp = idac->CURPROG & ~(_IDAC_CURPROG_TUNING_MASK
| _IDAC_CURPROG_RANGESEL_MASK);
- if (idac->CTRL & IDAC_CTRL_CURSINK)
- {
- switch (range)
- {
+ if (idac->CTRL & IDAC_CTRL_CURSINK) {
+ switch (range) {
case idacCurrentRange0:
tmp |= ((diCal1 & _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK)
>> _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT)
@@ -269,11 +258,8 @@
<< _IDAC_CURPROG_TUNING_SHIFT;
break;
}
- }
- else
- {
- switch (range)
- {
+ } else {
+ switch (range) {
case idacCurrentRange0:
tmp |= ((diCal0 & _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK)
>> _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT)
@@ -309,7 +295,6 @@
idac->CURPROG = tmp;
}
-
/***************************************************************************//**
* @brief
* Set the current step of the IDAC output.
@@ -333,7 +318,6 @@
idac->CURPROG = tmp;
}
-
/***************************************************************************//**
* @brief
* Enable/disable the IDAC OUT pin.
@@ -354,7 +338,6 @@
#endif
}
-
/** @} (end addtogroup IDAC) */
/** @} (end addtogroup emlib) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c Thu Nov 23 11:57:25 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,78 +0,0 @@
-/**************************************************************************//**
- * @file em_int.c
- * @brief Interrupt enable/disable unit API
- * @version 5.1.2
- ******************************************************************************
- * @section License
- * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
- *******************************************************************************
- *
- * Permission is granted to anyone to use this software for any purpose,
- * including commercial applications, and to alter it and redistribute it
- * freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- * claim that you wrote the original software.
- * 2. Altered source versions must be plainly marked as such, and must not be
- * misrepresented as being the original software.
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
- * obligation to support this Software. Silicon Labs is providing the
- * Software "AS IS", with no express or implied warranties of any kind,
- * including, but not limited to, any implied warranties of merchantability
- * or fitness for any particular purpose or warranties against infringement
- * of any proprietary rights of a third party.
- *
- * Silicon Labs will not be liable for any consequential, incidental, or
- * special damages, or any other relief, or for any claim by any third party,
- * arising from your use of this Software.
- *
- ******************************************************************************/
-
-#include <stdint.h>
-#include "em_int.h"
-
-/***************************************************************************//**
- * @addtogroup emlib
- * @{
- ******************************************************************************/
-
-/***************************************************************************//**
- * @addtogroup INT
- * @brief Safe nesting of interrupt disable/enable API
- * @{
- * @deprecated
- * These functions are deprecated and marked for removal in a later release.
- * Please use the @ref CORE module instead. See @ref core_porting for
- * information on how to convert existing code bases to use @ref CORE.
- *
- * @details
- * This module contains functions to safely disable and enable interrupts
- * at CPU level. INT_Disable() disables interrupts globally and increments a lock
- * level counter (counting semaphore). INT_Enable() decrements the lock level
- * counter and enable interrupts if the counter reaches zero.
- *
- * These functions would normally be used to secure critical regions, and
- * to make sure that a critical section that calls into another critical
- * section does not unintentionally terminate the callee critical section.
- *
- * These functions should also be used inside interrupt handlers:
- * @verbatim
- * void SysTick_Handler(void)
- * {
- * INT_Disable();
- * .
- * .
- * .
- * INT_Enable();
- * }
- * @endverbatim
- ******************************************************************************/
-
-/** Interrupt lock level counter. Set to zero initially as we normally enter
- * main with interrupts enabled */
-uint32_t INT_LockCnt = 0;
-
-/** @} (end addtogroup INT) */
-/** @} (end addtogroup emlib) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_lcd.c
* @brief Liquid Crystal Display (LCD) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -81,27 +81,48 @@
| _LCD_DISPCTRL_MUX_MASK
| _LCD_DISPCTRL_BIAS_MASK
| _LCD_DISPCTRL_WAVE_MASK
+#if defined(_LCD_DISPCTRL_VLCDSEL_MASK)
| _LCD_DISPCTRL_VLCDSEL_MASK
- | _LCD_DISPCTRL_CONCONF_MASK);
+#endif
+#if defined(_LCD_DISPCTRL_CONCONF_MASK)
+ | _LCD_DISPCTRL_CONCONF_MASK
+#endif
+#if defined(_LCD_DISPCTRL_MODE_MASK)
+ | _LCD_DISPCTRL_MODE_MASK
+#endif
+#if defined(_LCD_DISPCTRL_CHGRDST_MASK)
+ | _LCD_DISPCTRL_CHGRDST_MASK
+#endif
+ );
/* Configure controller according to initialization structure */
dispCtrl |= lcdInit->mux; /* also configures MUXE */
dispCtrl |= lcdInit->bias;
dispCtrl |= lcdInit->wave;
+#if defined(_SILICON_LABS_32B_SERIES_0)
dispCtrl |= lcdInit->vlcd;
dispCtrl |= lcdInit->contrast;
+#endif
+#if defined(_SILICON_LABS_32B_SERIES_1)
+ dispCtrl |= lcdInit->mode;
+ dispCtrl |= (lcdInit->chgrDst << _LCD_DISPCTRL_CHGRDST_SHIFT);
+#endif
/* Update display controller */
LCD->DISPCTRL = dispCtrl;
+#if defined(_SILICON_LABS_32B_SERIES_1)
+ LCD->FRAMERATE = lcdInit->frameRateDivider;
+ LCD_ContrastSet(lcdInit->contrastLevel);
+#endif
+
/* Enable controller if wanted */
- if (lcdInit->enable)
- {
+ if (lcdInit->enable) {
LCD_Enable(true);
}
}
-
+#if defined(_SILICON_LABS_32B_SERIES_0)
/***************************************************************************//**
* @brief
* Select source for VLCD
@@ -115,8 +136,7 @@
/* Select VEXT or VDD */
dispctrl &= ~_LCD_DISPCTRL_VLCDSEL_MASK;
- switch (vlcd)
- {
+ switch (vlcd) {
case lcdVLCDSelVExtBoost:
dispctrl |= LCD_DISPCTRL_VLCDSEL_VEXTBOOST;
break;
@@ -129,7 +149,7 @@
LCD->DISPCTRL = dispctrl;
}
-
+#endif
/***************************************************************************//**
* @brief
@@ -143,7 +163,6 @@
LCD->CTRL = (LCD->CTRL & ~_LCD_CTRL_UDCTRL_MASK) | ud;
}
-
/***************************************************************************//**
* @brief
* Initialize LCD Frame Counter
@@ -172,7 +191,6 @@
LCD_FrameCountEnable(fcInit->enable);
}
-
/***************************************************************************//**
* @brief
* Configures LCD controller Animation feature
@@ -202,12 +220,9 @@
#if defined(LCD_BACTRL_ALOC)
bactrl &= ~(_LCD_BACTRL_ALOC_MASK);
- if(animInit->startSeg == 0)
- {
+ if (animInit->startSeg == 0) {
bactrl |= LCD_BACTRL_ALOC_SEG0TO7;
- }
- else if(animInit->startSeg == 8)
- {
+ } else if (animInit->startSeg == 8) {
bactrl |= LCD_BACTRL_ALOC_SEG8TO15;
}
#endif
@@ -219,7 +234,6 @@
LCD_AnimEnable(animInit->enable);
}
-
/***************************************************************************//**
* @brief
* Enables update of this range of LCD segment lines
@@ -231,18 +245,16 @@
* @param[in] enable
* Bool true to enable segment updates, false to disable updates
******************************************************************************/
+#if defined(_SILICON_LABS_32B_SERIES_0)
void LCD_SegmentRangeEnable(LCD_SegmentRange_TypeDef segmentRange, bool enable)
{
- if (enable)
- {
+ if (enable) {
LCD->SEGEN |= segmentRange;
- }
- else
- {
+ } else {
LCD->SEGEN &= ~((uint32_t)segmentRange);
}
}
-
+#endif
/***************************************************************************//**
* @brief
@@ -280,55 +292,46 @@
#endif
/* Use bitband access for atomic bit set/clear of segment */
- switch (com)
- {
+ switch (com) {
case 0:
- if (bit < 32)
- {
+ if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD0L), bit, enable);
}
#if defined(_LCD_SEGD0H_MASK)
- else
- {
+ else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD0H), bit, enable);
}
#endif
break;
case 1:
- if (bit < 32)
- {
+ if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD1L), bit, enable);
}
#if defined(_LCD_SEGD1H_MASK)
- else
- {
+ else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD1H), bit, enable);
}
#endif
break;
case 2:
- if (bit < 32)
- {
+ if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD2L), bit, enable);
}
#if defined(_LCD_SEGD2H_MASK)
- else
- {
+ else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD2H), bit, enable);
}
#endif
break;
case 3:
- if (bit < 32)
- {
+ if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD3L), bit, enable);
}
#if defined(_LCD_SEGD3H_MASK)
- else
- {
+ else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD3H), bit, enable);
}
@@ -336,13 +339,11 @@
break;
#if defined(_LCD_SEGD4L_MASK)
case 4:
- if (bit < 32)
- {
+ if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD4L), bit, enable);
}
#if defined(_LCD_SEGD4H_MASK)
- else
- {
+ else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD4H), bit, enable);
}
@@ -351,13 +352,11 @@
#endif
#if defined(_LCD_SEGD5L_MASK)
case 5:
- if (bit < 32)
- {
+ if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD5L), bit, enable);
}
#if defined(_LCD_SEGD5H_MASK)
- else
- {
+ else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD5H), bit, enable);
}
@@ -366,13 +365,11 @@
#endif
case 6:
#if defined(_LCD_SEGD6L_MASK)
- if (bit < 32)
- {
+ if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD6L), bit, enable);
}
#if defined(_LCD_SEGD6H_MASK)
- else
- {
+ else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD6H), bit, enable);
}
@@ -381,13 +378,11 @@
#endif
#if defined(_LCD_SEGD7L_MASK)
case 7:
- if (bit < 32)
- {
+ if (bit < 32) {
BUS_RegBitWrite(&(LCD->SEGD7L), bit, enable);
}
#if defined(_LCD_SEGD7H_MASK)
- else
- {
+ else {
bit -= 32;
BUS_RegBitWrite(&(LCD->SEGD7H), bit, enable);
}
@@ -401,7 +396,6 @@
}
}
-
/***************************************************************************//**
* @brief
* Updates the 0-31 lowest segments on a given COM-line in one operation,
@@ -428,8 +422,7 @@
EFM_ASSERT(com < 4);
#endif
- switch (com)
- {
+ switch (com) {
case 0:
segData = LCD->SEGD0L;
segData &= ~(mask);
@@ -492,7 +485,6 @@
}
}
-
#if defined(_LCD_SEGD0H_MASK)
/***************************************************************************//**
* @brief
@@ -518,8 +510,7 @@
#endif
/* Maximum number of com lines */
- switch (com)
- {
+ switch (com) {
case 0:
segData = LCD->SEGD0H;
segData &= ~(mask);
@@ -582,6 +573,7 @@
}
#endif
+#if defined(_SILICON_LABS_32B_SERIES_0)
/***************************************************************************//**
* @brief
* Configure contrast level on LCD panel
@@ -596,8 +588,38 @@
LCD->DISPCTRL = (LCD->DISPCTRL & ~_LCD_DISPCTRL_CONLEV_MASK)
| (level << _LCD_DISPCTRL_CONLEV_SHIFT);
}
+#endif
+#if defined(_SILICON_LABS_32B_SERIES_1)
+/***************************************************************************//**
+ * @brief
+ * Configure contrast level on LCD panel
+ *
+ * @param[in] level
+ * Contrast level in the range 0-63
+ ******************************************************************************/
+void LCD_ContrastSet(int level)
+{
+ EFM_ASSERT(level < 64);
+ LCD->DISPCTRL = (LCD->DISPCTRL & ~_LCD_DISPCTRL_CONTRAST_MASK)
+ | (level << _LCD_DISPCTRL_CONTRAST_SHIFT);
+}
+#endif
+
+/***************************************************************************//**
+ * @brief
+ * Configure bias level on LCD panel
+ *
+ * @param[in] bias
+ * Bias level
+ ******************************************************************************/
+void LCD_BiasSet(LCD_Bias_TypeDef bias)
+{
+ LCD->DISPCTRL = (LCD->DISPCTRL & ~_LCD_DISPCTRL_BIAS_MASK) | bias;
+}
+
+#if defined(_SILICON_LABS_32B_SERIES_0)
/***************************************************************************//**
* @brief
* Configure voltage booster
@@ -612,7 +634,7 @@
/* Reconfigure Voltage Boost */
LCD->DISPCTRL = (LCD->DISPCTRL & ~_LCD_DISPCTRL_VBLEV_MASK) | vboost;
}
-
+#endif
#if defined(LCD_CTRL_DSC)
/***************************************************************************//**
@@ -647,8 +669,7 @@
biasRegister = segmentLine / 8;
bitShift = (segmentLine % 8) * 4;
- switch (biasRegister)
- {
+ switch (biasRegister) {
case 0:
segmentRegister = &LCD->SEGD0L;
break;
@@ -673,48 +694,35 @@
biasRegister = segmentLine / 10;
bitShift = (segmentLine % 10) * 4;
- switch (biasRegister)
- {
+ switch (biasRegister) {
case 0:
- if (bitShift < 32)
- {
+ if (bitShift < 32) {
segmentRegister = &LCD->SEGD0L;
- }
- else
- {
+ } else {
segmentRegister = &LCD->SEGD0H;
bitShift -= 32;
}
break;
case 1:
- if (bitShift < 32)
- {
+ if (bitShift < 32) {
segmentRegister = &LCD->SEGD1L;
- }
- else
- {
+ } else {
segmentRegister = &LCD->SEGD1H;
bitShift -= 32;
}
break;
case 2:
- if (bitShift < 32)
- {
+ if (bitShift < 32) {
segmentRegister = &LCD->SEGD2L;
- }
- else
- {
+ } else {
segmentRegister = &LCD->SEGD1H;
bitShift -= 32;
}
break;
case 3:
- if (bitShift < 32)
- {
+ if (bitShift < 32) {
segmentRegister = &LCD->SEGD3L;
- }
- else
- {
+ } else {
segmentRegister = &LCD->SEGD3H;
bitShift -= 32;
}
@@ -731,7 +739,6 @@
}
#endif
-
#if defined(LCD_CTRL_DSC)
/***************************************************************************//**
* @brief
@@ -762,6 +769,35 @@
}
#endif
+#if defined(_SILICON_LABS_32B_SERIES_1)
+/***************************************************************************//**
+ * @brief
+ * Configure the mode for the LCD panel
+ *
+ * @param[in] mode
+ * Mode
+ ******************************************************************************/
+void LCD_ModeSet(LCD_Mode_Typedef mode)
+{
+ LCD->DISPCTRL = (LCD->DISPCTRL & ~_LCD_DISPCTRL_MODE_MASK) | mode;
+}
+
+/***************************************************************************//**
+ * @brief
+ * Configure the charge redistribution cycles for the LCD panel
+ *
+ * @param[in] chgrDst
+ * Charge redistribution cycles, range 0-4
+ ******************************************************************************/
+void LCD_ChargeRedistributionCyclesSet(uint8_t cycles)
+{
+ EFM_ASSERT(cycles <= 4);
+
+ LCD->DISPCTRL = (LCD->DISPCTRL & ~_LCD_DISPCTRL_CHGRDST_MASK)
+ | (cycles << _LCD_DISPCTRL_CHGRDST_SHIFT);
+}
+#endif
+
/** @} (end addtogroup LCD) */
/** @} (end addtogroup emlib) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_ldma.c
* @brief Direct memory access (LDMA) module peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -32,7 +32,7 @@
#include "em_ldma.h"
-#if defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
+#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1)
#include <stddef.h>
#include "em_assert.h"
@@ -50,7 +50,7 @@
* @{
******************************************************************************/
-#if defined( LDMA_IRQ_HANDLER_TEMPLATE )
+#if defined(LDMA_IRQ_HANDLER_TEMPLATE)
/***************************************************************************//**
* @brief
* Template for an LDMA IRQ handler.
@@ -62,16 +62,13 @@
uint32_t pending = LDMA_IntGetEnabled();
/* Loop here on an LDMA error to enable debugging. */
- while (pending & LDMA_IF_ERROR)
- {
+ while (pending & LDMA_IF_ERROR) {
}
/* Iterate over all LDMA channels. */
- for (ch = 0; ch < DMA_CHAN_COUNT; ch++)
- {
+ for (ch = 0; ch < DMA_CHAN_COUNT; ch++) {
uint32_t mask = 0x1 << ch;
- if (pending & mask)
- {
+ if (pending & mask) {
/* Clear interrupt flag. */
LDMA->IFC = mask;
@@ -204,7 +201,7 @@
EFM_ASSERT(!((transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT)
& ~_LDMA_CH_CFG_ARBSLOTS_MASK));
EFM_ASSERT(!((transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT)
- & ~_LDMA_CH_CFG_SRCINCSIGN_MASK ) );
+ & ~_LDMA_CH_CFG_SRCINCSIGN_MASK) );
EFM_ASSERT(!((transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT)
& ~_LDMA_CH_CFG_DSTINCSIGN_MASK));
EFM_ASSERT(!((transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT)
@@ -228,37 +225,31 @@
/* Enable channel interrupt. */
LDMA->IEN |= chMask;
- if (transfer->ldmaReqDis)
- {
+ if (transfer->ldmaReqDis) {
LDMA->REQDIS |= chMask;
}
- if (transfer->ldmaDbgHalt)
- {
+ if (transfer->ldmaDbgHalt) {
LDMA->DBGHALT |= chMask;
}
tmp = LDMA->CTRL;
- if (transfer->ldmaCtrlSyncPrsClrOff)
- {
+ if (transfer->ldmaCtrlSyncPrsClrOff) {
tmp &= ~_LDMA_CTRL_SYNCPRSCLREN_MASK
| (~transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT);
}
- if (transfer->ldmaCtrlSyncPrsClrOn)
- {
+ if (transfer->ldmaCtrlSyncPrsClrOn) {
tmp |= transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT;
}
- if (transfer->ldmaCtrlSyncPrsSetOff)
- {
+ if (transfer->ldmaCtrlSyncPrsSetOff) {
tmp &= ~_LDMA_CTRL_SYNCPRSSETEN_MASK
| (~transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT);
}
- if (transfer->ldmaCtrlSyncPrsSetOn)
- {
+ if (transfer->ldmaCtrlSyncPrsSetOn) {
tmp |= transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT;
}
@@ -290,7 +281,7 @@
CORE_ATOMIC_SECTION(
LDMA->IEN &= ~chMask;
BUS_RegMaskedClear(&LDMA->CHEN, chMask);
- )
+ )
}
/***************************************************************************//**
@@ -312,11 +303,10 @@
CORE_ATOMIC_SECTION(
if (((LDMA->CHEN & chMask) == 0)
- && ((LDMA->CHDONE & chMask) == chMask))
- {
- retVal = true;
- }
- )
+ && ((LDMA->CHDONE & chMask) == chMask)) {
+ retVal = true;
+ }
+ )
return retVal;
}
@@ -346,15 +336,14 @@
iflag = LDMA->IF;
done = LDMA->CHDONE;
remaining = LDMA->CH[ch].CTRL;
- )
+ )
iflag &= chMask;
done &= chMask;
remaining = (remaining & _LDMA_CH_CTRL_XFERCNT_MASK)
>> _LDMA_CH_CTRL_XFERCNT_SHIFT;
- if (done || ((remaining == 0) && iflag))
- {
+ if (done || ((remaining == 0) && iflag)) {
return 0;
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_lesense.c
* @brief Low Energy Sensor (LESENSE) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -79,7 +79,6 @@
************************** LOCAL FUNCTIONS ********************************
******************************************************************************/
-
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
@@ -124,8 +123,7 @@
#endif
/* Reset LESENSE registers if requested. */
- if (reqReset)
- {
+ if (reqReset) {
LESENSE_Reset();
}
@@ -166,27 +164,32 @@
* Set DAC0 and DAC1 data source, conversion mode, output mode. Set DAC
* prescaler and reference. Set ACMP0 and ACMP1 control mode. Set ACMP and DAC
* duty cycle (warm up) mode. */
- LESENSE->PERCTRL =
- ((uint32_t)init->perCtrl.dacCh0Data << _LESENSE_PERCTRL_DACCH0DATA_SHIFT)
- | ((uint32_t)init->perCtrl.dacCh1Data << _LESENSE_PERCTRL_DACCH1DATA_SHIFT)
+ LESENSE->PERCTRL = 0
+#if defined(_LESENSE_PERCTRL_DACCH0EN_MASK)
+ | ((uint32_t)init->perCtrl.dacCh0En << _LESENSE_PERCTRL_DACCH0EN_SHIFT)
+ | ((uint32_t)init->perCtrl.dacCh1En << _LESENSE_PERCTRL_DACCH1EN_SHIFT)
+#endif
+ | ((uint32_t)init->perCtrl.dacCh0Data << _LESENSE_PERCTRL_DACCH0DATA_SHIFT)
+ | ((uint32_t)init->perCtrl.dacCh1Data << _LESENSE_PERCTRL_DACCH1DATA_SHIFT)
#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK)
- | ((uint32_t)init->perCtrl.dacCh0ConvMode << _LESENSE_PERCTRL_DACCH0CONV_SHIFT)
- | ((uint32_t)init->perCtrl.dacCh0OutMode << _LESENSE_PERCTRL_DACCH0OUT_SHIFT)
- | ((uint32_t)init->perCtrl.dacCh1ConvMode << _LESENSE_PERCTRL_DACCH1CONV_SHIFT)
- | ((uint32_t)init->perCtrl.dacCh1OutMode << _LESENSE_PERCTRL_DACCH1OUT_SHIFT)
- | ((uint32_t)init->perCtrl.dacPresc << _LESENSE_PERCTRL_DACPRESC_SHIFT)
- | (uint32_t)init->perCtrl.dacRef
-#endif
- | ((uint32_t)init->perCtrl.acmp0Mode << _LESENSE_PERCTRL_ACMP0MODE_SHIFT)
- | ((uint32_t)init->perCtrl.acmp1Mode << _LESENSE_PERCTRL_ACMP1MODE_SHIFT)
-#if defined(_LESENSE_PERCTRL_ACMP0INV_MASK)
- | ((uint32_t)init->coreCtrl.invACMP0 << _LESENSE_PERCTRL_ACMP0INV_SHIFT)
- | ((uint32_t)init->coreCtrl.invACMP1 << _LESENSE_PERCTRL_ACMP1INV_SHIFT)
+ | ((uint32_t)init->perCtrl.dacCh0ConvMode << _LESENSE_PERCTRL_DACCH0CONV_SHIFT)
+ | ((uint32_t)init->perCtrl.dacCh0OutMode << _LESENSE_PERCTRL_DACCH0OUT_SHIFT)
+ | ((uint32_t)init->perCtrl.dacCh1ConvMode << _LESENSE_PERCTRL_DACCH1CONV_SHIFT)
+ | ((uint32_t)init->perCtrl.dacCh1OutMode << _LESENSE_PERCTRL_DACCH1OUT_SHIFT)
+ | ((uint32_t)init->perCtrl.dacPresc << _LESENSE_PERCTRL_DACPRESC_SHIFT)
+ | (uint32_t)init->perCtrl.dacRef
#endif
#if defined(_LESENSE_PERCTRL_DACCONVTRIG_MASK)
- | ((uint32_t)init->perCtrl.dacScan << _LESENSE_PERCTRL_DACCONVTRIG_SHIFT)
+ | ((uint32_t)init->perCtrl.dacStartupHalf << _LESENSE_PERCTRL_DACSTARTUP_SHIFT)
+ | ((uint32_t)init->perCtrl.dacScan << _LESENSE_PERCTRL_DACCONVTRIG_SHIFT)
#endif
- | (uint32_t)init->perCtrl.warmupMode;
+ | ((uint32_t)init->perCtrl.acmp0Mode << _LESENSE_PERCTRL_ACMP0MODE_SHIFT)
+ | ((uint32_t)init->perCtrl.acmp1Mode << _LESENSE_PERCTRL_ACMP1MODE_SHIFT)
+#if defined(_LESENSE_PERCTRL_ACMP0INV_MASK)
+ | ((uint32_t)init->coreCtrl.invACMP0 << _LESENSE_PERCTRL_ACMP0INV_SHIFT)
+ | ((uint32_t)init->coreCtrl.invACMP1 << _LESENSE_PERCTRL_ACMP1INV_SHIFT)
+#endif
+ | (uint32_t)init->perCtrl.warmupMode;
/* LESENSE decoder general control configuration.
* Set decoder input source, select PRS input for decoder bits.
@@ -217,7 +220,6 @@
LESENSE->BIASCTRL = (uint32_t)init->coreCtrl.biasMode;
}
-
/***************************************************************************//**
* @brief
* Set scan frequency for periodic scanning.
@@ -252,11 +254,9 @@
uint32_t pcTop = 63UL; /* Period counter top value (max. 63). */
uint32_t calcScanFreq; /* Variable for testing the calculation algorithm. */
-
/* If refFreq is set to 0, the currently configured reference clock is
* assumed. */
- if (!refFreq)
- {
+ if (!refFreq) {
refFreq = CMU_ClockFreqGet(cmuClock_LESENSE);
}
@@ -272,8 +272,7 @@
* biggest possible resolution for setting scan frequency.
* Maximum number of calculation cycles is 7 (value of lesenseClkDiv_128). */
while ((refFreq / ((uint32_t)scanFreq * clkDiv) > (pcTop + 1UL))
- && (pcPresc < lesenseClkDiv_128))
- {
+ && (pcPresc < lesenseClkDiv_128)) {
++pcPresc;
clkDiv = (uint32_t)1UL << pcPresc;
}
@@ -299,7 +298,6 @@
return calcScanFreq;
}
-
/***************************************************************************//**
* @brief
* Set scan mode of the LESENSE channels.
@@ -331,7 +329,6 @@
{
uint32_t tmp; /* temporary storage of the CTRL register value */
-
/* Save the CTRL register value to tmp.
* Please be aware the effects of the non-atomic Read-Modify-Write cycle! */
tmp = LESENSE->CTRL & ~(_LESENSE_CTRL_SCANMODE_MASK);
@@ -343,13 +340,11 @@
LESENSE->CTRL = tmp;
/* Start sensor scanning if requested. */
- if (start)
- {
+ if (start) {
LESENSE_ScanStart();
}
}
-
/***************************************************************************//**
* @brief
* Set start delay of sensor interaction on each channel.
@@ -372,7 +367,6 @@
{
uint32_t tmp; /* temporary storage of the TIMCTRL register value */
-
/* Sanity check of startDelay. */
EFM_ASSERT(startDelay < 4U);
@@ -386,7 +380,6 @@
LESENSE->TIMCTRL = tmp;
}
-
/***************************************************************************//**
* @brief
* Set clock division for LESENSE timers.
@@ -416,10 +409,8 @@
{
uint32_t tmp;
-
/* Select clock to prescale */
- switch (clk)
- {
+ switch (clk) {
case lesenseClkHF:
/* Sanity check of clock divisor for HF clock. */
EFM_ASSERT((uint32_t)clkDiv <= lesenseClkDiv_8);
@@ -451,7 +442,6 @@
}
}
-
/***************************************************************************//**
* @brief
* Configure all (16) LESENSE sensor channels.
@@ -478,14 +468,12 @@
uint32_t i;
/* Iterate through all the 16 channels */
- for (i = 0U; i < LESENSE_NUM_CHANNELS; ++i)
- {
+ for (i = 0U; i < LESENSE_NUM_CHANNELS; ++i) {
/* Configure scan channels. */
LESENSE_ChannelConfig(&confChAll->Ch[i], i);
}
}
-
/***************************************************************************//**
* @brief
* Configure a single LESENSE sensor channel.
@@ -513,7 +501,6 @@
{
uint32_t tmp; /* Service variable. */
-
/* Sanity check of configuration parameters */
EFM_ASSERT(chIdx < LESENSE_NUM_CHANNELS);
EFM_ASSERT(confCh->exTime <= (_LESENSE_CH_TIMING_EXTIME_MASK >> _LESENSE_CH_TIMING_EXTIME_SHIFT));
@@ -527,8 +514,7 @@
* configuration parameters, check the parameter description of acmpThres for
* for more details! */
EFM_ASSERT(confCh->acmpThres < 4096U);
- if (confCh->chPinExMode == lesenseChPinExDACOut)
- {
+ if (confCh->chPinExMode == lesenseChPinExDACOut) {
EFM_ASSERT((0x1 << chIdx) & DACOUT_SUPPORT);
}
@@ -563,25 +549,25 @@
* alternate excitation usage and interrupt mode on scan channel chIdx in
* LESENSE_CHchIdx_INTERACT. */
LESENSE->CH[chIdx].INTERACT =
- ((uint32_t)confCh->exClk << _LESENSE_CH_INTERACT_EXCLK_SHIFT)
- | ((uint32_t)confCh->sampleClk << _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT)
- | (uint32_t)confCh->sampleMode
- | (uint32_t)confCh->intMode
- | (uint32_t)confCh->chPinExMode
- | ((uint32_t)confCh->useAltEx << _LESENSE_CH_INTERACT_ALTEX_SHIFT);
+ ((uint32_t)confCh->exClk << _LESENSE_CH_INTERACT_EXCLK_SHIFT)
+ | ((uint32_t)confCh->sampleClk << _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT)
+ | (uint32_t)confCh->sampleMode
+ | (uint32_t)confCh->intMode
+ | (uint32_t)confCh->chPinExMode
+ | ((uint32_t)confCh->useAltEx << _LESENSE_CH_INTERACT_ALTEX_SHIFT);
/* Configure channel specific counter comparison mode, optional result
* forwarding to decoder, optional counter value storing and optional result
* inverting on scan channel chIdx in LESENSE_CHchIdx_EVAL. */
LESENSE->CH[chIdx].EVAL =
- (uint32_t)confCh->compMode
- | ((uint32_t)confCh->shiftRes << _LESENSE_CH_EVAL_DECODE_SHIFT)
- | ((uint32_t)confCh->storeCntRes << _LESENSE_CH_EVAL_STRSAMPLE_SHIFT)
- | ((uint32_t)confCh->invRes << _LESENSE_CH_EVAL_SCANRESINV_SHIFT)
+ (uint32_t)confCh->compMode
+ | ((uint32_t)confCh->shiftRes << _LESENSE_CH_EVAL_DECODE_SHIFT)
+ | ((uint32_t)confCh->storeCntRes << _LESENSE_CH_EVAL_STRSAMPLE_SHIFT)
+ | ((uint32_t)confCh->invRes << _LESENSE_CH_EVAL_SCANRESINV_SHIFT)
#if defined(_LESENSE_CH_EVAL_MODE_MASK)
- | ((uint32_t)confCh->evalMode << _LESENSE_CH_EVAL_MODE_SHIFT)
+ | ((uint32_t)confCh->evalMode << _LESENSE_CH_EVAL_MODE_SHIFT)
#endif
- ;
+ ;
/* Configure analog comparator (ACMP) threshold and decision threshold for
* counter separately with the function provided for that. */
@@ -599,7 +585,6 @@
BUS_RegBitWrite(&LESENSE->CHEN, chIdx, confCh->enaScanCh);
}
-
/***************************************************************************//**
* @brief
* Configure the LESENSE alternate excitation modes.
@@ -622,7 +607,6 @@
uint32_t i;
uint32_t tmp;
-
/* Configure alternate excitation mapping.
* Atomic read-modify-write using BUS_RegBitWrite function in order to
* support reconfiguration during LESENSE operation. */
@@ -630,12 +614,10 @@
_LESENSE_CTRL_ALTEXMAP_SHIFT,
confAltEx->altExMap);
- switch (confAltEx->altExMap)
- {
+ switch (confAltEx->altExMap) {
case lesenseAltExMapALTEX:
/* Iterate through the 8 possible alternate excitation pin descriptors. */
- for (i = 0U; i < 8U; ++i)
- {
+ for (i = 0U; i < 8U; ++i) {
/* Enable/disable alternate excitation pin i.
* Atomic read-modify-write using BUS_RegBitWrite function in order to
* support reconfiguration during LESENSE operation. */
@@ -663,8 +645,7 @@
case lesenseAltExMapCH:
#endif
/* Iterate through all the 16 alternate excitation channels */
- for (i = 0U; i < 16U; ++i)
- {
+ for (i = 0U; i < 16U; ++i) {
/* Enable/disable alternate ACMP excitation channel pin i. */
/* Atomic read-modify-write using BUS_RegBitWrite function in order to
* support reconfiguration during LESENSE operation. */
@@ -680,7 +661,6 @@
}
}
-
/***************************************************************************//**
* @brief
* Enable/disable LESENSE scan channel and the pin assigned to it.
@@ -719,7 +699,6 @@
BUS_RegBitWrite(&LESENSE->CHEN, chIdx, enaScanCh);
}
-
/***************************************************************************//**
* @brief
* Enable/disable LESENSE scan channel and the pin assigned to it.
@@ -750,7 +729,6 @@
GENERIC_LESENSE_ROUTE = pinMask;
}
-
/***************************************************************************//**
* @brief
* Set LESENSE channel timing parameters.
@@ -795,12 +773,11 @@
/* Channel specific timing configuration on scan channel chIdx.
* Setting excitation time, sampling delay, measurement delay. */
LESENSE->CH[chIdx].TIMING =
- ((uint32_t)exTime << _LESENSE_CH_TIMING_EXTIME_SHIFT)
- | ((uint32_t)sampleDelay << _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT)
- | ((uint32_t)measDelay << _LESENSE_CH_TIMING_MEASUREDLY_SHIFT);
+ ((uint32_t)exTime << _LESENSE_CH_TIMING_EXTIME_SHIFT)
+ | ((uint32_t)sampleDelay << _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT)
+ | ((uint32_t)measDelay << _LESENSE_CH_TIMING_MEASUREDLY_SHIFT);
}
-
/***************************************************************************//**
* @brief
* Set LESENSE channel threshold parameters.
@@ -840,7 +817,6 @@
{
uint32_t tmp; /* temporary storage */
-
/* Sanity check for acmpThres only, cntThres is 16bit value. */
EFM_ASSERT(acmpThres < 4096U);
/* Sanity check for LESENSE channel id. */
@@ -1001,14 +977,12 @@
uint32_t i;
/* Iterate through all the 16 or 32 decoder states. */
- for (i = 0U; i < LESENSE_NUM_DECODER_STATES; ++i)
- {
+ for (i = 0U; i < LESENSE_NUM_DECODER_STATES; ++i) {
/* Configure decoder state i. */
LESENSE_DecoderStateConfig(&confDecStAll->St[i], i);
}
}
-
/***************************************************************************//**
* @brief
* Configure a single LESENSE decoder state.
@@ -1052,14 +1026,13 @@
* Setting sensor compare value, sensor mask, next state index, transition
* action and interrupt flag option configurations. */
LESENSE->ST[decSt].TCONFB =
- (uint32_t)confDecSt->confB.prsAct
+ (uint32_t)confDecSt->confB.prsAct
| ((uint32_t)confDecSt->confB.compMask << _LESENSE_ST_TCONFB_MASK_SHIFT)
| ((uint32_t)confDecSt->confB.compVal << _LESENSE_ST_TCONFB_COMP_SHIFT)
| ((uint32_t)confDecSt->confB.nextState << _LESENSE_ST_TCONFB_NEXTSTATE_SHIFT)
| ((uint32_t)confDecSt->confB.setInt << _LESENSE_ST_TCONFB_SETIF_SHIFT);
}
-
/***************************************************************************//**
* @brief
* Set LESENSE decoder state.
@@ -1083,7 +1056,6 @@
LESENSE->DECSTATE = decSt & _LESENSE_DECSTATE_DECSTATE_MASK;
}
-
/***************************************************************************//**
* @brief
* Get the current state of the LESENSE decoder.
@@ -1149,7 +1121,6 @@
;
}
-
/***************************************************************************//**
* @brief
* Stop scanning of sensors.
@@ -1182,7 +1153,6 @@
;
}
-
/***************************************************************************//**
* @brief
* Start LESENSE decoder.
@@ -1212,7 +1182,6 @@
;
}
-
/***************************************************************************//**
* @brief
* Clear result buffer.
@@ -1241,7 +1210,6 @@
;
}
-
/***************************************************************************//**
* @brief
* Reset the LESENSE module.
@@ -1297,16 +1265,14 @@
#endif
/* Reset all channel configuration registers */
- for (i = 0U; i < LESENSE_NUM_CHANNELS; ++i)
- {
+ for (i = 0U; i < LESENSE_NUM_CHANNELS; ++i) {
LESENSE->CH[i].TIMING = _LESENSE_CH_TIMING_RESETVALUE;
LESENSE->CH[i].INTERACT = _LESENSE_CH_INTERACT_RESETVALUE;
LESENSE->CH[i].EVAL = _LESENSE_CH_EVAL_RESETVALUE;
}
/* Reset all decoder state configuration registers */
- for (i = 0U; i < LESENSE_NUM_DECODER_STATES; ++i)
- {
+ for (i = 0U; i < LESENSE_NUM_DECODER_STATES; ++i) {
LESENSE->ST[i].TCONFA = _LESENSE_ST_TCONFA_RESETVALUE;
LESENSE->ST[i].TCONFB = _LESENSE_ST_TCONFB_RESETVALUE;
}
@@ -1317,7 +1283,6 @@
;
}
-
/** @} (end addtogroup LESENSE) */
/** @} (end addtogroup emlib) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_letimer.c
* @brief Low Energy Timer (LETIMER) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -60,14 +60,19 @@
#define LETIMER_COMP_REG_VALID(reg) (((reg) <= 1))
/** Validation of LETIMER register block pointer reference for assert statements. */
+#if (LETIMER_COUNT == 1)
#define LETIMER_REF_VALID(ref) ((ref) == LETIMER0)
+#elif (LETIMER_COUNT == 2)
+#define LETIMER_REF_VALID(ref) (((ref) == LETIMER0) || ((ref) == LETIMER1))
+#else
+#error Undefined number of analog comparators (ACMP).
+#endif
/** Validation of valid repeat counter register for assert statements. */
#define LETIMER_REP_REG_VALID(reg) (((reg) <= 1))
/** @endcond */
-
/*******************************************************************************
************************** LOCAL FUNCTIONS ********************************
******************************************************************************/
@@ -96,8 +101,9 @@
#if defined(_LETIMER_FREEZE_MASK)
/* Avoid deadlock if modifying the same register twice when freeze mode is */
/* activated. */
- if (letimer->FREEZE & LETIMER_FREEZE_REGFREEZE)
+ if (letimer->FREEZE & LETIMER_FREEZE_REGFREEZE) {
return;
+ }
#endif
/* Wait for any pending previous write operation to have been completed */
@@ -133,8 +139,7 @@
EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_COMP_REG_VALID(comp));
/* Initialize selected compare value */
- switch (comp)
- {
+ switch (comp) {
case 0:
ret = letimer->COMP0;
break;
@@ -152,7 +157,6 @@
return(ret);
}
-
/***************************************************************************//**
* @brief
* Set LETIMER compare register value.
@@ -186,8 +190,7 @@
== 0));
/* Initialize selected compare value */
- switch (comp)
- {
+ switch (comp) {
case 0:
compReg = &(letimer->COMP0);
break;
@@ -209,7 +212,6 @@
*compReg = value;
}
-
/***************************************************************************//**
* @brief
* Start/stop LETIMER.
@@ -237,12 +239,9 @@
regSync(letimer, LETIMER_SYNCBUSY_CMD);
#endif
- if (enable)
- {
+ if (enable) {
letimer->CMD = LETIMER_CMD_START;
- }
- else
- {
+ } else {
letimer->CMD = LETIMER_CMD_STOP;
}
}
@@ -277,8 +276,7 @@
******************************************************************************/
void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable)
{
- if (enable)
- {
+ if (enable) {
/*
* Wait for any ongoing LF synchronization to complete. This is just to
* protect against the rare case when a user
@@ -292,9 +290,7 @@
;
letimer->FREEZE = LETIMER_FREEZE_REGFREEZE;
- }
- else
- {
+ } else {
letimer->FREEZE = 0;
}
}
@@ -331,8 +327,7 @@
EFM_ASSERT(LETIMER_REF_VALID(letimer));
/* Stop timer if specified to be disabled and running */
- if (!(init->enable) && (letimer->STATUS & LETIMER_STATUS_RUNNING))
- {
+ if (!(init->enable) && (letimer->STATUS & LETIMER_STATUS_RUNNING)) {
#if defined(_EFM32_GECKO_FAMILY)
/* LF register about to be modified require sync. busy check */
regSync(letimer, LETIMER_SYNCBUSY_CMD);
@@ -342,40 +337,33 @@
/* Configure DEBUGRUN flag, sets whether or not counter should be
* updated when debugger is active */
- if (init->debugRun)
- {
+ if (init->debugRun) {
tmp |= LETIMER_CTRL_DEBUGRUN;
}
#if defined(LETIMER_CTRL_RTCC0TEN)
- if (init->rtcComp0Enable)
- {
+ if (init->rtcComp0Enable) {
tmp |= LETIMER_CTRL_RTCC0TEN;
}
- if (init->rtcComp1Enable)
- {
+ if (init->rtcComp1Enable) {
tmp |= LETIMER_CTRL_RTCC1TEN;
}
#endif
- if (init->comp0Top)
- {
+ if (init->comp0Top) {
tmp |= LETIMER_CTRL_COMP0TOP;
}
- if (init->bufTop)
- {
+ if (init->bufTop) {
tmp |= LETIMER_CTRL_BUFTOP;
}
- if (init->out0Pol)
- {
+ if (init->out0Pol) {
tmp |= LETIMER_CTRL_OPOL0;
}
- if (init->out1Pol)
- {
+ if (init->out1Pol) {
tmp |= LETIMER_CTRL_OPOL1;
}
@@ -390,8 +378,7 @@
letimer->CTRL = tmp;
/* Start timer if specified to be enabled and not already running */
- if (init->enable && !(letimer->STATUS & LETIMER_STATUS_RUNNING))
- {
+ if (init->enable && !(letimer->STATUS & LETIMER_STATUS_RUNNING)) {
#if defined(_EFM32_GECKO_FAMILY)
/* LF register about to be modified require sync. busy check */
regSync(letimer, LETIMER_SYNCBUSY_CMD);
@@ -400,7 +387,6 @@
}
}
-
/***************************************************************************//**
* @brief
* Get LETIMER repeat register value.
@@ -421,8 +407,7 @@
EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_REP_REG_VALID(rep));
/* Initialize selected compare value */
- switch (rep)
- {
+ switch (rep) {
case 0:
ret = letimer->REP0;
break;
@@ -440,7 +425,6 @@
return(ret);
}
-
/***************************************************************************//**
* @brief
* Set LETIMER repeat counter register value.
@@ -476,8 +460,7 @@
== 0));
/* Initialize selected compare value */
- switch (rep)
- {
+ switch (rep) {
case 0:
repReg = &(letimer->REP0);
#if defined(_EFM32_GECKO_FAMILY)
@@ -505,7 +488,6 @@
*repReg = value;
}
-
/***************************************************************************//**
* @brief
* Reset LETIMER to same state as after a HW reset.
@@ -542,7 +524,6 @@
#endif
}
-
/** @} (end addtogroup LETIMER) */
/** @} (end addtogroup emlib) */
#endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c Thu Dec 07 14:01:42 2017 +0000
@@ -2,9 +2,9 @@
* @file em_leuart.c
* @brief Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
* Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -60,7 +60,6 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-
/** Validation of LEUART register block pointer reference
* for assert statements. */
#if (LEUART_COUNT == 1)
@@ -94,8 +93,7 @@
{
/* Avoid deadlock if modifying the same register twice when freeze mode is */
/* activated. */
- if (leuart->FREEZE & LEUART_FREEZE_REGFREEZE)
- {
+ if (leuart->FREEZE & LEUART_FREEZE_REGFREEZE) {
return;
}
@@ -194,7 +192,6 @@
return br;
}
-
/***************************************************************************//**
* @brief
* Get current baudrate for LEUART.
@@ -215,18 +212,15 @@
CMU_Clock_TypeDef clock;
/* Get current frequency */
- if (leuart == LEUART0)
- {
+ if (leuart == LEUART0) {
clock = cmuClock_LEUART0;
}
#if (LEUART_COUNT > 1)
- else if (leuart == LEUART1)
- {
+ else if (leuart == LEUART1) {
clock = cmuClock_LEUART1;
}
#endif
- else
- {
+ else {
EFM_ASSERT(0);
return 0;
}
@@ -236,7 +230,6 @@
return LEUART_BaudrateCalc(freq, leuart->CLKDIV);
}
-
/***************************************************************************//**
* @brief
* Configure baudrate (or as close as possible to specified baudrate).
@@ -295,20 +288,16 @@
*/
/* Get current frequency? */
- if (!refFreq)
- {
- if (leuart == LEUART0)
- {
+ if (!refFreq) {
+ if (leuart == LEUART0) {
clock = cmuClock_LEUART0;
}
#if (LEUART_COUNT > 1)
- else if (leuart == LEUART1)
- {
+ else if (leuart == LEUART1) {
clock = cmuClock_LEUART1;
}
#endif
- else
- {
+ else {
EFM_ASSERT(0);
return;
}
@@ -333,7 +322,6 @@
leuart->CLKDIV = clkdiv;
}
-
/***************************************************************************//**
* @brief
* Enable/disable LEUART receiver and/or transmitter.
@@ -374,7 +362,6 @@
leuart->CMD = tmp;
}
-
/***************************************************************************//**
* @brief
* LEUART register synchronization freeze control.
@@ -404,8 +391,7 @@
******************************************************************************/
void LEUART_FreezeEnable(LEUART_TypeDef *leuart, bool enable)
{
- if (enable)
- {
+ if (enable) {
/*
* Wait for any ongoing LF synchronization to complete. This is just to
* protect against the rare case when a user
@@ -419,14 +405,11 @@
;
leuart->FREEZE = LEUART_FREEZE_REGFREEZE;
- }
- else
- {
+ } else {
leuart->FREEZE = 0;
}
}
-
/***************************************************************************//**
* @brief
* Init LEUART.
@@ -489,7 +472,6 @@
LEUART_FreezeEnable(leuart, false);
}
-
/***************************************************************************//**
* @brief
* Reset LEUART to same state as after a HW reset.
@@ -526,7 +508,6 @@
LEUART_FreezeEnable(leuart, false);
}
-
/***************************************************************************//**
* @brief
* Receive one 8 bit frame, (or part of 9 bit frame).
@@ -556,7 +537,6 @@
return (uint8_t)leuart->RXDATA;
}
-
/***************************************************************************//**
* @brief
* Receive one 8-9 bit frame, with extended information.
@@ -582,7 +562,6 @@
return (uint16_t)leuart->RXDATAX;
}
-
/***************************************************************************//**
* @brief
* Transmit one frame.
@@ -618,7 +597,6 @@
leuart->TXDATA = (uint32_t)data;
}
-
/***************************************************************************//**
* @brief
* Transmit one 8-9 bit frame with extended control.
@@ -667,12 +645,9 @@
/* LF register about to be modified require sync. busy check */
LEUART_Sync(leuart, LEUART_SYNCBUSY_CTRL);
- if (enable)
- {
+ if (enable) {
leuart->CTRL |= LEUART_CTRL_TXDMAWU;
- }
- else
- {
+ } else {
leuart->CTRL &= ~LEUART_CTRL_TXDMAWU;
}
}
@@ -694,17 +669,13 @@
/* LF register about to be modified require sync. busy check */
LEUART_Sync(leuart, LEUART_SYNCBUSY_CTRL);
- if (enable)
- {
+ if (enable) {
leuart->CTRL |= LEUART_CTRL_RXDMAWU;
- }
- else
- {
+ } else {
leuart->CTRL &= ~LEUART_CTRL_RXDMAWU;
}
}
-
/** @} (end addtogroup LEUART) */
/** @} (end addtogroup emlib) */
#endif /* defined(LEUART_COUNT) && (LEUART_COUNT > 0) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_mpu.c
* @brief Memory Protection Unit (MPU) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -34,13 +34,11 @@
#if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1)
#include "em_assert.h"
-
/***************************************************************************//**
* @addtogroup emlib
* @{
******************************************************************************/
-
/***************************************************************************//**
* @addtogroup MPU
* @brief Memory Protection Unit (MPU) Peripheral API
@@ -69,12 +67,10 @@
* @{
******************************************************************************/
-
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
-
/***************************************************************************//**
* @brief
* Configure an MPU region.
@@ -90,13 +86,12 @@
******************************************************************************/
void MPU_ConfigureRegion(const MPU_RegionInit_TypeDef *init)
{
- EFM_ASSERT(init->regionNo < ((MPU->TYPE & MPU_TYPE_DREGION_Msk) >>
- MPU_TYPE_DREGION_Pos));
+ EFM_ASSERT(init->regionNo < ((MPU->TYPE & MPU_TYPE_DREGION_Msk)
+ >> MPU_TYPE_DREGION_Pos));
MPU->RNR = init->regionNo;
- if (init->regionEnable)
- {
+ if (init->regionEnable) {
EFM_ASSERT(!(init->baseAddress & ~MPU_RBAR_ADDR_Msk));
EFM_ASSERT(init->tex <= 0x7);
@@ -110,15 +105,12 @@
| (init->srd << MPU_RASR_SRD_Pos)
| (init->size << MPU_RASR_SIZE_Pos)
| (1 << MPU_RASR_ENABLE_Pos);
- }
- else
- {
+ } else {
MPU->RBAR = 0;
MPU->RASR = 0;
}
}
-
/** @} (end addtogroup CMU) */
/** @} (end addtogroup emlib) */
#endif /* defined(__MPU_PRESENT) && (__MPU_PRESENT == 1) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_msc.c
* @brief Flash controller (MSC) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -31,10 +31,10 @@
******************************************************************************/
#include "em_msc.h"
-#if defined( MSC_COUNT ) && ( MSC_COUNT > 0 )
+#if defined(MSC_COUNT) && (MSC_COUNT > 0)
#include "em_system.h"
-#if defined( _MSC_TIMEBASE_MASK )
+#if defined(_MSC_TIMEBASE_MASK)
#include "em_cmu.h"
#endif
#include "em_assert.h"
@@ -51,13 +51,13 @@
#error "Running Flash write/erase operations from Flash is not supported on EFM32G."
#endif
-#if defined( MSC_WRITECTRL_WDOUBLE )
+#if defined(MSC_WRITECTRL_WDOUBLE)
#define WORDS_PER_DATA_PHASE (FLASH_SIZE < (512 * 1024) ? 1 : 2)
#else
#define WORDS_PER_DATA_PHASE (1)
#endif
-#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
/* Fix for errata FLASH_E201 - Potential program failure after Power On */
#define ERRATA_FIX_FLASH_E201_EN
#endif
@@ -68,18 +68,18 @@
} MSC_WriteStrategy_Typedef;
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
- MSC_WriteWordI(uint32_t *address,
- void const *data,
- uint32_t numBytes,
- MSC_WriteStrategy_Typedef writeStrategy);
+MSC_WriteWordI(uint32_t *address,
+ void const *data,
+ uint32_t numBytes,
+ MSC_WriteStrategy_Typedef writeStrategy);
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
- MSC_LoadWriteData(uint32_t* data,
- uint32_t numWords,
- MSC_WriteStrategy_Typedef writeStrategy);
+MSC_LoadWriteData(uint32_t* data,
+ uint32_t numWords,
+ MSC_WriteStrategy_Typedef writeStrategy);
MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef
- MSC_LoadVerifyAddress(uint32_t* address);
+MSC_LoadVerifyAddress(uint32_t* address);
#if !defined(EM_MSC_RUN_FROM_FLASH)
@@ -108,8 +108,7 @@
(void)file; /* Unused parameter */
(void)line; /* Unused parameter */
- while (true)
- {
+ while (true) {
}
}
MSC_RAMFUNC_DEFINITION_END
@@ -146,21 +145,14 @@
* @note
* This function must be called before flash operations when
* AUXHFRCO clock has been changed from default band.
- * @note
- * This function calls SystemCoreClockGet in order to set the global variable
- * SystemCoreClock which is used in subseqent calls of MSC_WriteWord to make
- * sure the frequency is sufficiently high for flash operations. If the clock
- * frequency is changed then software is responsible for calling MSC_Init or
- * SystemCoreClockGet in order to set the SystemCoreClock variable to the
- * correct value.
******************************************************************************/
void MSC_Init(void)
{
-#if defined( _MSC_TIMEBASE_MASK )
+#if defined(_MSC_TIMEBASE_MASK)
uint32_t freq, cycles;
#endif
-#if defined( _EMU_STATUS_VSCALE_MASK )
+#if defined(_EMU_STATUS_VSCALE_MASK)
/* VSCALE must be done and flash erase and write requires VSCALE2 */
EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK));
EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2);
@@ -171,21 +163,13 @@
/* Disable writing to the flash */
MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN;
- /* Call SystemCoreClockGet in order to set the global variable SystemCoreClock
- which is used in MSC_LoadWriteData to make sure the frequency is
- sufficiently high. If the clock frequency is changed then software is
- responsible for calling MSC_Init or SystemCoreClockGet in order to set the
- SystemCoreClock variable to the correct value. */
- SystemCoreClockGet();
-
-#if defined( _MSC_TIMEBASE_MASK )
+#if defined(_MSC_TIMEBASE_MASK)
/* Configure MSC->TIMEBASE according to selected frequency */
freq = CMU_ClockFreqGet(cmuClock_AUX);
/* Timebase 5us is used for the 1/1.2MHz band only. Note that the 1MHz band
is tuned to 1.2MHz on newer revisions. */
- if (freq > 1200000)
- {
+ if (freq > 1200000) {
/* Calculate number of clock cycles for 1us as base period */
freq = (freq * 11) / 10;
cycles = (freq / 1000000) + 1;
@@ -195,9 +179,7 @@
| _MSC_TIMEBASE_PERIOD_MASK))
| MSC_TIMEBASE_PERIOD_1US
| (cycles << _MSC_TIMEBASE_BASE_SHIFT);
- }
- else
- {
+ } else {
/* Calculate number of clock cycles for 5us as base period */
freq = (freq * 5 * 11) / 10;
cycles = (freq / 1000000) + 1;
@@ -223,7 +205,6 @@
MSC->LOCK = 0;
}
-
/***************************************************************************//**
* @brief
* Set MSC code execution configuration
@@ -235,77 +216,65 @@
{
uint32_t mscReadCtrl;
-#if defined( MSC_READCTRL_MODE_WS0SCBTP )
+#if defined(MSC_READCTRL_MODE_WS0SCBTP)
mscReadCtrl = MSC->READCTRL & _MSC_READCTRL_MODE_MASK;
- if ((mscReadCtrl == MSC_READCTRL_MODE_WS0) && (execConfig->scbtEn))
- {
+ if ((mscReadCtrl == MSC_READCTRL_MODE_WS0) && (execConfig->scbtEn)) {
mscReadCtrl |= MSC_READCTRL_MODE_WS0SCBTP;
- }
- else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1) && (execConfig->scbtEn))
- {
+ } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1) && (execConfig->scbtEn)) {
mscReadCtrl |= MSC_READCTRL_MODE_WS1SCBTP;
- }
- else if ((mscReadCtrl == MSC_READCTRL_MODE_WS0SCBTP) && (!execConfig->scbtEn))
- {
+ } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS0SCBTP) && (!execConfig->scbtEn)) {
mscReadCtrl |= MSC_READCTRL_MODE_WS0;
- }
- else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1SCBTP) && (!execConfig->scbtEn))
- {
+ } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1SCBTP) && (!execConfig->scbtEn)) {
mscReadCtrl |= MSC_READCTRL_MODE_WS1;
- }
- else
- {
+ } else {
/* No change needed */
}
#endif
mscReadCtrl = MSC->READCTRL & ~(0
-#if defined( MSC_READCTRL_SCBTP )
+#if defined(MSC_READCTRL_SCBTP)
| MSC_READCTRL_SCBTP
#endif
-#if defined( MSC_READCTRL_USEHPROT )
+#if defined(MSC_READCTRL_USEHPROT)
| MSC_READCTRL_USEHPROT
#endif
-#if defined( MSC_READCTRL_PREFETCH )
+#if defined(MSC_READCTRL_PREFETCH)
| MSC_READCTRL_PREFETCH
#endif
-#if defined( MSC_READCTRL_ICCDIS )
+#if defined(MSC_READCTRL_ICCDIS)
| MSC_READCTRL_ICCDIS
#endif
-#if defined( MSC_READCTRL_AIDIS )
+#if defined(MSC_READCTRL_AIDIS)
| MSC_READCTRL_AIDIS
#endif
-#if defined( MSC_READCTRL_IFCDIS )
+#if defined(MSC_READCTRL_IFCDIS)
| MSC_READCTRL_IFCDIS
#endif
);
mscReadCtrl |= (0
-#if defined( MSC_READCTRL_SCBTP )
- | (execConfig->scbtEn ? MSC_READCTRL_SCBTP : 0)
+#if defined(MSC_READCTRL_SCBTP)
+ | (execConfig->scbtEn ? MSC_READCTRL_SCBTP : 0)
#endif
-#if defined( MSC_READCTRL_USEHPROT )
- | (execConfig->useHprot ? MSC_READCTRL_USEHPROT : 0)
+#if defined(MSC_READCTRL_USEHPROT)
+ | (execConfig->useHprot ? MSC_READCTRL_USEHPROT : 0)
#endif
-#if defined( MSC_READCTRL_PREFETCH )
- | (execConfig->prefetchEn ? MSC_READCTRL_PREFETCH : 0)
+#if defined(MSC_READCTRL_PREFETCH)
+ | (execConfig->prefetchEn ? MSC_READCTRL_PREFETCH : 0)
#endif
-#if defined( MSC_READCTRL_ICCDIS )
- | (execConfig->iccDis ? MSC_READCTRL_ICCDIS : 0)
+#if defined(MSC_READCTRL_ICCDIS)
+ | (execConfig->iccDis ? MSC_READCTRL_ICCDIS : 0)
#endif
-#if defined( MSC_READCTRL_AIDIS )
- | (execConfig->aiDis ? MSC_READCTRL_AIDIS : 0)
+#if defined(MSC_READCTRL_AIDIS)
+ | (execConfig->aiDis ? MSC_READCTRL_AIDIS : 0)
#endif
-#if defined( MSC_READCTRL_IFCDIS )
- | (execConfig->ifcDis ? MSC_READCTRL_IFCDIS : 0)
+#if defined(MSC_READCTRL_IFCDIS)
+ | (execConfig->ifcDis ? MSC_READCTRL_IFCDIS : 0)
#endif
- );
+ );
MSC->READCTRL = mscReadCtrl;
}
-
-
-
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/***************************************************************************//**
@@ -333,14 +302,12 @@
/* Wait for the MSC to become ready. */
timeOut = MSC_PROGRAM_TIMEOUT;
- while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0))
- {
+ while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) {
timeOut--;
}
/* Check for timeout */
- if (timeOut == 0)
- {
+ if (timeOut == 0) {
return mscReturnTimeOut;
}
/* Load address */
@@ -348,20 +315,20 @@
MSC->WRITECMD = MSC_WRITECMD_LADDRIM;
status = MSC->STATUS;
- if (status & (MSC_STATUS_INVADDR | MSC_STATUS_LOCKED))
- {
+ if (status & (MSC_STATUS_INVADDR | MSC_STATUS_LOCKED)) {
/* Check for invalid address */
- if (status & MSC_STATUS_INVADDR)
+ if (status & MSC_STATUS_INVADDR) {
return mscReturnInvalidAddr;
+ }
/* Check for write protected page */
- if (status & MSC_STATUS_LOCKED)
+ if (status & MSC_STATUS_LOCKED) {
return mscReturnLocked;
+ }
}
return mscReturnOk;
}
MSC_RAMFUNC_DEFINITION_END
-
/***************************************************************************//**
* @brief
* Perform a Flash data write phase.
@@ -391,28 +358,24 @@
uint32_t wordIndex;
bool useWDouble = false;
MSC_Status_TypeDef retval = mscReturnOk;
-#if !defined( _EFM32_GECKO_FAMILY )
+#if !defined(_EFM32_GECKO_FAMILY)
uint32_t irqState;
#endif
#if defined(_MSC_WRITECTRL_LPWRITE_MASK) && defined(_MSC_WRITECTRL_WDOUBLE_MASK)
/* If LPWRITE (Low Power Write) is NOT enabled, set WDOUBLE (Write Double word) */
- if (!(MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE))
- {
+ if (!(MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE)) {
#if defined(_SILICON_LABS_32B_SERIES_0)
/* If the number of words to be written are odd, we need to align by writing
a single word first, before setting the WDOUBLE bit. */
- if (numWords & 0x1)
- {
+ if (numWords & 0x1) {
/* Wait for the MSC to become ready for the next word. */
timeOut = MSC_PROGRAM_TIMEOUT;
- while ((!(MSC->STATUS & MSC_STATUS_WDATAREADY)) && (timeOut != 0))
- {
+ while ((!(MSC->STATUS & MSC_STATUS_WDATAREADY)) && (timeOut != 0)) {
timeOut--;
}
/* Check for timeout */
- if (timeOut == 0)
- {
+ if (timeOut == 0) {
return mscReturnTimeOut;
}
/* Clear double word option, in order to write the initial single word. */
@@ -424,13 +387,11 @@
/* Wait for the operation to finish. It may be required to change the WDOUBLE
config after the initial write. It should not be changed while BUSY. */
timeOut = MSC_PROGRAM_TIMEOUT;
- while((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0))
- {
+ while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) {
timeOut--;
}
/* Check for timeout */
- if (timeOut == 0)
- {
+ if (timeOut == 0) {
return mscReturnTimeOut;
}
/* Subtract this initial odd word for the write loop below */
@@ -446,37 +407,29 @@
#endif /* defined( _MSC_WRITECTRL_LPWRITE_MASK ) && defined( _MSC_WRITECTRL_WDOUBLE_MASK ) */
/* Write the rest as double word write if wordsPerDataPhase == 2 */
- if (numWords > 0)
- {
+ if (numWords > 0) {
/**** Write strategy: mscWriteIntSafe ****/
- if (writeStrategy == mscWriteIntSafe)
- {
+ if (writeStrategy == mscWriteIntSafe) {
/* Requires a system core clock at 1MHz or higher */
EFM_ASSERT(SystemCoreClock >= 1000000);
wordIndex = 0;
- while(wordIndex < numWords)
- {
- if (!useWDouble)
- {
+ while (wordIndex < numWords) {
+ if (!useWDouble) {
MSC->WDATA = *data++;
wordIndex++;
MSC->WRITECMD = MSC_WRITECMD_WRITEONCE;
- }
-
- else // useWDouble == true
- {
- /* Trigger double write according to flash properties. */
-#if defined(_SILICON_LABS_32B_SERIES_0)
+ } else { // useWDouble == true
+ /* Trigger double write according to flash properties. */
+#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_MSC_WRITECTRL_WDOUBLE_MASK)
MSC->WDATA = *data++;
- while (!(MSC->STATUS & MSC_STATUS_WDATAREADY));
+ while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)) ;
MSC->WDATA = *data++;
wordIndex += 2;
MSC->WRITECMD = MSC_WRITECMD_WRITEONCE;
-#elif (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2)
- while (!(MSC->STATUS & MSC_STATUS_WDATAREADY));
- do
- {
+#elif defined(_SILICON_LABS_32B_SERIES_1) && defined(_MSC_WRITECTRL_WDOUBLE_MASK)
+ while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)) ;
+ do {
MSC->WDATA = *data++;
wordIndex++;
} while ((MSC->STATUS & MSC_STATUS_WDATAREADY)
@@ -487,27 +440,23 @@
/* Wait for the transaction to finish. */
timeOut = MSC_PROGRAM_TIMEOUT;
- while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0))
- {
+ while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) {
timeOut--;
}
/* Check for timeout */
- if (timeOut == 0)
- {
+ if (timeOut == 0) {
retval = mscReturnTimeOut;
break;
}
-#if defined( _EFM32_GECKO_FAMILY )
+#if defined(_EFM32_GECKO_FAMILY)
MSC->ADDRB += 4;
MSC->WRITECMD = MSC_WRITECMD_LADDRIM;
#endif
}
}
-
/**** Write strategy: mscWriteFast ****/
- else
- {
-#if defined( _EFM32_GECKO_FAMILY )
+ else {
+#if defined(_EFM32_GECKO_FAMILY)
/* Gecko does not have auto-increment of ADDR. */
EFM_ASSERT(false);
#else
@@ -522,11 +471,9 @@
__disable_irq();
wordIndex = 0;
- while(wordIndex < numWords)
- {
+ while (wordIndex < numWords) {
/* Wait for the MSC to be ready for the next word. */
- while (!(MSC->STATUS & MSC_STATUS_WDATAREADY))
- {
+ while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)) {
/* If the write to MSC->WDATA below missed the 30us timeout and the
following MSC_WRITECMD_WRITETRIG command arrived while
MSC_STATUS_BUSY is 1, then the MSC_WRITECMD_WRITETRIG could be ignored by
@@ -535,39 +482,32 @@
complete write of data in MSC->WDATA.
If WDATAREADY became high since entry into this loop, exit and continue
to the next WDATA write.
- */
+ */
if ((MSC->STATUS & (MSC_STATUS_WORDTIMEOUT
| MSC_STATUS_BUSY
| MSC_STATUS_WDATAREADY))
- == MSC_STATUS_WORDTIMEOUT)
- {
+ == MSC_STATUS_WORDTIMEOUT) {
MSC->WRITECMD = MSC_WRITECMD_WRITETRIG;
}
}
- if (!useWDouble)
- {
+ if (!useWDouble) {
MSC->WDATA = *data;
MSC->WRITECMD = MSC_WRITECMD_WRITETRIG;
data++;
wordIndex++;
- }
-
- else // useWDouble == true
- {
- /* Trigger double write according to flash properties. */
+ } else { // useWDouble == true
+ /* Trigger double write according to flash properties. */
#if defined(_SILICON_LABS_32B_SERIES_0)
MSC->WDATA = *data;
- if (wordIndex & 0x1)
- {
+ if (wordIndex & 0x1) {
MSC->WRITECMD = MSC_WRITECMD_WRITETRIG;
}
data++;
wordIndex++;
#elif (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2)
- do
- {
+ do {
MSC->WDATA = *data++;
wordIndex++;
} while ((MSC->STATUS & MSC_STATUS_WDATAREADY)
@@ -577,28 +517,25 @@
}
}
- if (irqState == 0)
- {
+ if (irqState == 0) {
/* Restore previous interrupt state. */
__enable_irq();
}
/* Wait for the transaction to finish. */
timeOut = MSC_PROGRAM_TIMEOUT;
- while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0))
- {
+ while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) {
timeOut--;
}
/* Check for timeout */
- if (timeOut == 0)
- {
+ if (timeOut == 0) {
retval = mscReturnTimeOut;
}
#endif
} /* writeStrategy */
}
-#if defined( _MSC_WRITECTRL_WDOUBLE_MASK )
+#if defined(_MSC_WRITECTRL_WDOUBLE_MASK)
/* Clear double word option, which should not be left on when returning. */
MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE;
#endif
@@ -607,7 +544,6 @@
}
MSC_RAMFUNC_DEFINITION_END
-
/***************************************************************************//**
* @brief
* Internal flash write function with select write strategy parameter
@@ -640,7 +576,7 @@
/* Check number of bytes. Must be divisable by four */
EFM_ASSERT((numBytes & 0x3) == 0);
-#if defined( _EMU_STATUS_VSCALE_MASK )
+#if defined(_EMU_STATUS_VSCALE_MASK)
/* VSCALE must be done and flash write requires VSCALE2 */
EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK));
EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2);
@@ -656,35 +592,31 @@
/* The following loop splits the data into chunks corresponding to flash pages.
The address is loaded only once per page, because the hardware automatically
increments the address internally for each data load inside a page. */
- for (wordCount = 0, pData = (uint32_t *)data; wordCount < numWords; )
- {
+ for (wordCount = 0, pData = (uint32_t *)data; wordCount < numWords; ) {
/* First we load address. The address is auto-incremented within a page.
Therefore the address phase is only needed once for each page. */
retval = MSC_LoadVerifyAddress(address + wordCount);
- if (mscReturnOk != retval)
- {
+ if (mscReturnOk != retval) {
return retval;
}
/* Compute the number of words to write to the current page. */
pageWords =
- (FLASH_PAGE_SIZE -
- (((uint32_t) (address + wordCount)) & (FLASH_PAGE_SIZE - 1)))
+ (FLASH_PAGE_SIZE
+ - (((uint32_t) (address + wordCount)) & (FLASH_PAGE_SIZE - 1)))
/ sizeof(uint32_t);
- if (pageWords > numWords - wordCount)
- {
+ if (pageWords > numWords - wordCount) {
pageWords = numWords - wordCount;
}
/* Now write the data in the current page. */
retval = MSC_LoadWriteData(pData, pageWords, writeStrategy);
- if (mscReturnOk != retval)
- {
+ if (mscReturnOk != retval) {
break;
}
wordCount += pageWords;
pData += pageWords;
}
-#if defined( ERRATA_FIX_FLASH_E201_EN )
+#if defined(ERRATA_FIX_FLASH_E201_EN)
/* Fix for errata FLASH_E201 - Potential program failure after Power On.
*
* Check if the first word was programmed correctly. If a failure is detected
@@ -692,11 +624,9 @@
*
* Full description of errata can be found in the errata document */
pData = (uint32_t *) data;
- if (*address != *pData)
- {
+ if (*address != *pData) {
retval = MSC_LoadVerifyAddress(address);
- if (mscReturnOk == retval)
- {
+ if (mscReturnOk == retval) {
retval = MSC_LoadWriteData(pData, 1, writeStrategy);
}
}
@@ -705,8 +635,8 @@
/* Disable writing to the MSC */
MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN;
-#if defined( _MSC_WRITECTRL_WDOUBLE_MASK )
-#if ( WORDS_PER_DATA_PHASE == 2 )
+#if defined(_MSC_WRITECTRL_WDOUBLE_MASK)
+#if (WORDS_PER_DATA_PHASE == 2)
/* Turn off double word write cycle support. */
MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE;
#endif
@@ -718,7 +648,6 @@
/** @endcond */
-
/***************************************************************************//**
* @brief
* Erases a page in flash memory.
@@ -751,7 +680,7 @@
/* Address must be aligned to pages */
EFM_ASSERT((((uint32_t) startAddress) & (FLASH_PAGE_SIZE - 1)) == 0);
-#if defined( _EMU_STATUS_VSCALE_MASK )
+#if defined(_EMU_STATUS_VSCALE_MASK)
/* VSCALE must be done and flash erase requires VSCALE2 */
EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK));
EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2);
@@ -765,15 +694,13 @@
MSC->WRITECMD = MSC_WRITECMD_LADDRIM;
/* Check for invalid address */
- if (MSC->STATUS & MSC_STATUS_INVADDR)
- {
+ if (MSC->STATUS & MSC_STATUS_INVADDR) {
/* Disable writing to the MSC */
MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN;
return mscReturnInvalidAddr;
}
/* Check for write protected page */
- if (MSC->STATUS & MSC_STATUS_LOCKED)
- {
+ if (MSC->STATUS & MSC_STATUS_LOCKED) {
/* Disable writing to the MSC */
MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN;
return mscReturnLocked;
@@ -782,12 +709,10 @@
MSC->WRITECMD = MSC_WRITECMD_ERASEPAGE;
/* Wait for the erase to complete */
- while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0))
- {
+ while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) {
timeOut--;
}
- if (timeOut == 0)
- {
+ if (timeOut == 0) {
/* Disable writing to the MSC */
MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN;
return mscReturnTimeOut;
@@ -798,7 +723,6 @@
}
MSC_RAMFUNC_DEFINITION_END
-
/***************************************************************************//**
* @brief
* Writes data to flash memory. This function is interrupt safe, but slower than
@@ -844,8 +768,7 @@
}
MSC_RAMFUNC_DEFINITION_END
-
-#if !defined( _EFM32_GECKO_FAMILY )
+#if !defined(_EFM32_GECKO_FAMILY)
/***************************************************************************//**
* @brief
* Writes data to flash memory. This function is faster than MSC_WriteWord(),
@@ -853,9 +776,8 @@
* a number of bytes that is divisable by four.
* @note
* It is recommended to erase the flash page before performing a write.
-
- * It is recommended to run this code from RAM. On the Gecko family, it is required
- * to run this function from RAM.
+ * It is required to run this function from RAM on parts that include a
+ * flash write buffer.
*
* For IAR, Rowley, SimplicityStudio, Atollic and armgcc this will be achieved
* automatically by using attributes in the function proctype. For Keil uVision you
@@ -879,6 +801,7 @@
* the next word into the DWORD register.
* @endverbatim
******************************************************************************/
+#if !defined (EM_MSC_RUN_FROM_FLASH) || (_SILICON_LABS_GECKO_INTERNAL_SDID < 84)
MSC_RAMFUNC_DEFINITION_BEGIN
MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address,
void const *data,
@@ -889,9 +812,9 @@
MSC_RAMFUNC_DEFINITION_END
#endif
-
+#endif
-#if defined( _MSC_MASSLOCK_MASK )
+#if defined(_MSC_MASSLOCK_MASK)
/***************************************************************************//**
* @brief
* Erase entire flash in one operation
@@ -915,14 +838,14 @@
MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN0;
/* Waiting for erase to complete */
- while ((MSC->STATUS & MSC_STATUS_BUSY));
+ while ((MSC->STATUS & MSC_STATUS_BUSY)) ;
-#if ((FLASH_SIZE >= (512 * 1024)) && defined( _MSC_WRITECMD_ERASEMAIN1_MASK ))
+#if ((FLASH_SIZE >= (512 * 1024)) && defined(_MSC_WRITECMD_ERASEMAIN1_MASK))
/* Erase second 512K block */
MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN1;
/* Waiting for erase to complete */
- while ((MSC->STATUS & MSC_STATUS_BUSY));
+ while ((MSC->STATUS & MSC_STATUS_BUSY)) ;
#endif
/* Restore mass erase lock */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
-/**************************************************************************//**
+/***************************************************************************//**
* @file em_opamp.c
* @brief Operational Amplifier (OPAMP) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -32,7 +32,7 @@
#include "em_opamp.h"
#if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \
- || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0)))
+ || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0)))
#include "em_system.h"
#include "em_assert.h"
@@ -42,7 +42,7 @@
* @{
******************************************************************************/
-
+/* *INDENT-OFF* */
/***************************************************************************//**
* @addtogroup OPAMP
* @brief Operational Amplifier (OPAMP) peripheral API
@@ -206,7 +206,7 @@
* @if DOXYDOC_P2_DEVICE
* \n<b>Instrumentation amplifier.</b>\n
* Use predefined macros @ref OPA_INIT_INSTR_AMP_OPA0 and
- * @ref OPA_INIT_INSTR_AMP_OPA0.
+ * @ref OPA_INIT_INSTR_AMP_OPA1.
* @verbatim
|\
@@ -235,6 +235,7 @@
*
* @{
******************************************************************************/
+/* *INDENT-ON* */
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
@@ -268,18 +269,13 @@
EFM_ASSERT(DAC_REF_VALID(dac));
EFM_ASSERT(DAC_OPA_VALID(opa));
- if (opa == OPA0)
- {
+ if (opa == OPA0) {
dac->CH0CTRL &= ~DAC_CH0CTRL_EN;
dac->OPACTRL &= ~DAC_OPACTRL_OPA0EN;
- }
- else if (opa == OPA1)
- {
+ } else if (opa == OPA1) {
dac->CH1CTRL &= ~DAC_CH1CTRL_EN;
dac->OPACTRL &= ~DAC_OPACTRL_OPA1EN;
- }
- else /* OPA2 */
- {
+ } else { /* OPA2 */
dac->OPACTRL &= ~DAC_OPACTRL_OPA2EN;
}
@@ -287,31 +283,28 @@
EFM_ASSERT(VDAC_REF_VALID(dac));
EFM_ASSERT(VDAC_OPA_VALID(opa));
- if (opa == OPA0)
- {
+ if (opa == OPA0) {
+#if defined(VDAC_STATUS_OPA0ENS)
dac->CMD |= VDAC_CMD_OPA0DIS;
- while (dac->STATUS & VDAC_STATUS_OPA0ENS)
- {
+ while (dac->STATUS & VDAC_STATUS_OPA0ENS) {
}
- }
- else if (opa == OPA1)
- {
+#endif
+ } else if (opa == OPA1) {
+#if defined(VDAC_STATUS_OPA1ENS)
dac->CMD |= VDAC_CMD_OPA1DIS;
- while (dac->STATUS & VDAC_STATUS_OPA1ENS)
- {
+ while (dac->STATUS & VDAC_STATUS_OPA1ENS) {
}
- }
- else /* OPA2 */
- {
+#endif
+ } else { /* OPA2 */
+#if defined(VDAC_STATUS_OPA2ENS)
dac->CMD |= VDAC_CMD_OPA2DIS;
- while (dac->STATUS & VDAC_STATUS_OPA2ENS)
- {
+ while (dac->STATUS & VDAC_STATUS_OPA2ENS) {
}
+#endif
}
#endif
}
-
/***************************************************************************//**
* @brief
* Configure and enable an Operational Amplifier.
@@ -379,15 +372,14 @@
const OPAMP_Init_TypeDef *init)
{
#if defined(_SILICON_LABS_32B_SERIES_0)
- uint32_t offset;
+ uint32_t gain;
EFM_ASSERT(DAC_REF_VALID(dac));
EFM_ASSERT(DAC_OPA_VALID(opa));
EFM_ASSERT(init->bias <= (_DAC_BIASPROG_BIASPROG_MASK
- >> _DAC_BIASPROG_BIASPROG_SHIFT));
+ >> _DAC_BIASPROG_BIASPROG_SHIFT));
- if (opa == OPA0)
- {
+ if (opa == OPA0) {
EFM_ASSERT((init->outPen & ~_DAC_OPA0MUX_OUTPEN_MASK) == 0);
dac->BIASPROG = (dac->BIASPROG
@@ -396,14 +388,11 @@
| (init->bias << _DAC_BIASPROG_BIASPROG_SHIFT)
| (init->halfBias ? DAC_BIASPROG_HALFBIAS : 0);
- if (init->defaultOffset)
- {
- offset = SYSTEM_GetCalibrationValue(&dac->CAL);
- dac->CAL = (dac->CAL & ~_DAC_CAL_CH0OFFSET_MASK)
- | (offset & _DAC_CAL_CH0OFFSET_MASK);
- }
- else
- {
+ if (init->defaultOffset) {
+ gain = dac->CAL & _DAC_CAL_GAIN_MASK;
+ SYSTEM_GetCalibrationValue(&dac->CAL);
+ dac->CAL = (dac->CAL & ~_DAC_CAL_GAIN_MASK) | gain;
+ } else {
EFM_ASSERT(init->offset <= (_DAC_CAL_CH0OFFSET_MASK
>> _DAC_CAL_CH0OFFSET_SHIFT));
@@ -417,9 +406,9 @@
| (uint32_t)init->resInMux
| (uint32_t)init->negSel
| (uint32_t)init->posSel
- | ( init->nextOut ? DAC_OPA0MUX_NEXTOUT : 0)
- | ( init->npEn ? DAC_OPA0MUX_NPEN : 0)
- | ( init->ppEn ? DAC_OPA0MUX_PPEN : 0);
+ | (init->nextOut ? DAC_OPA0MUX_NEXTOUT : 0)
+ | (init->npEn ? DAC_OPA0MUX_NPEN : 0)
+ | (init->ppEn ? DAC_OPA0MUX_PPEN : 0);
dac->CH0CTRL |= DAC_CH0CTRL_EN;
dac->OPACTRL = (dac->OPACTRL
@@ -433,25 +422,20 @@
? DAC_OPACTRL_OPA0LPFDIS_NLPFDIS : 0)
| (init->hcmDisable ? DAC_OPACTRL_OPA0HCMDIS : 0)
| DAC_OPACTRL_OPA0EN;
- }
- else if ( opa == OPA1 )
- {
+ } else if ( opa == OPA1 ) {
EFM_ASSERT((init->outPen & ~_DAC_OPA1MUX_OUTPEN_MASK) == 0);
dac->BIASPROG = (dac->BIASPROG
& ~(_DAC_BIASPROG_BIASPROG_MASK
| DAC_BIASPROG_HALFBIAS))
| (init->bias << _DAC_BIASPROG_BIASPROG_SHIFT)
- | (init->halfBias ? DAC_BIASPROG_HALFBIAS : 0 );
+ | (init->halfBias ? DAC_BIASPROG_HALFBIAS : 0);
- if (init->defaultOffset)
- {
- offset = SYSTEM_GetCalibrationValue(&dac->CAL);
- dac->CAL = (dac->CAL & ~_DAC_CAL_CH1OFFSET_MASK)
- | (offset & _DAC_CAL_CH1OFFSET_MASK);
- }
- else
- {
+ if (init->defaultOffset) {
+ gain = dac->CAL & _DAC_CAL_GAIN_MASK;
+ SYSTEM_GetCalibrationValue(&dac->CAL);
+ dac->CAL = (dac->CAL & ~_DAC_CAL_GAIN_MASK) | gain;
+ } else {
EFM_ASSERT(init->offset <= (_DAC_CAL_CH1OFFSET_MASK
>> _DAC_CAL_CH1OFFSET_SHIFT));
@@ -481,9 +465,7 @@
? DAC_OPACTRL_OPA1LPFDIS_NLPFDIS : 0)
| (init->hcmDisable ? DAC_OPACTRL_OPA1HCMDIS : 0)
| DAC_OPACTRL_OPA1EN;
- }
- else /* OPA2 */
- {
+ } else { /* OPA2 */
EFM_ASSERT((init->posSel == DAC_OPA2MUX_POSSEL_DISABLE)
|| (init->posSel == DAC_OPA2MUX_POSSEL_POSPAD)
|| (init->posSel == DAC_OPA2MUX_POSSEL_OPA1INP)
@@ -499,14 +481,9 @@
| (init->bias << _DAC_BIASPROG_OPA2BIASPROG_SHIFT)
| (init->halfBias ? DAC_BIASPROG_OPA2HALFBIAS : 0);
- if (init->defaultOffset)
- {
- offset = SYSTEM_GetCalibrationValue(&dac->OPAOFFSET);
- dac->OPAOFFSET = (dac->OPAOFFSET & ~_DAC_OPAOFFSET_OPA2OFFSET_MASK)
- | (offset & _DAC_OPAOFFSET_OPA2OFFSET_MASK);
- }
- else
- {
+ if (init->defaultOffset) {
+ SYSTEM_GetCalibrationValue(&dac->OPAOFFSET);
+ } else {
EFM_ASSERT(init->offset <= (_DAC_OPAOFFSET_OPA2OFFSET_MASK
>> _DAC_OPAOFFSET_OPA2OFFSET_SHIFT));
dac->OPAOFFSET = (dac->OPAOFFSET & ~_DAC_OPAOFFSET_OPA2OFFSET_MASK)
@@ -519,9 +496,9 @@
| (uint32_t)init->resInMux
| (uint32_t)init->negSel
| (uint32_t)init->posSel
- | ( init->nextOut ? DAC_OPA2MUX_NEXTOUT : 0 )
- | ( init->npEn ? DAC_OPA2MUX_NPEN : 0 )
- | ( init->ppEn ? DAC_OPA2MUX_PPEN : 0 );
+ | (init->nextOut ? DAC_OPA2MUX_NEXTOUT : 0)
+ | (init->npEn ? DAC_OPA2MUX_NPEN : 0)
+ | (init->ppEn ? DAC_OPA2MUX_PPEN : 0);
dac->OPACTRL = (dac->OPACTRL
& ~(DAC_OPACTRL_OPA2SHORT
@@ -548,8 +525,8 @@
>> _VDAC_OPA_TIMER_STARTUPDLY_SHIFT));
EFM_ASSERT((init->outPen & ~_VDAC_OPA_OUT_ALTOUTPADEN_MASK) == 0);
EFM_ASSERT(!((init->gain3xEn == true)
- && ((init->negSel == opaNegSelResTap)
- || (init->posSel == opaPosSelResTap))));
+ && ((init->negSel == opaNegSelResTap)
+ || (init->posSel == opaPosSelResTap))));
EFM_ASSERT((init->drvStr == opaDrvStrLowerAccLowStr)
|| (init->drvStr == opaDrvStrLowAccLowStr)
|| (init->drvStr == opaDrvStrHighAccHighStr)
@@ -559,11 +536,10 @@
OPAMP_Disable(dac, opa);
/* Get the calibration value based on OPAMP, Drive Strength, and INCBW. */
- switch (opa)
- {
+ switch (opa) {
+#if defined(VDAC_STATUS_OPA0ENS)
case OPA0:
- switch (init->drvStr)
- {
+ switch (init->drvStr) {
case opaDrvStrLowerAccLowStr:
calData = (init->ugBwScale ? DEVINFO->OPA0CAL0 : DEVINFO->OPA0CAL4);
break;
@@ -578,10 +554,11 @@
break;
}
break;
+#endif
+#if defined(VDAC_STATUS_OPA1ENS)
case OPA1:
- switch (init->drvStr)
- {
+ switch (init->drvStr) {
case opaDrvStrLowerAccLowStr:
calData = (init->ugBwScale ? DEVINFO->OPA1CAL0 : DEVINFO->OPA1CAL4);
break;
@@ -596,10 +573,11 @@
break;
}
break;
+#endif
+#if defined(VDAC_STATUS_OPA2ENS)
case OPA2:
- switch (init->drvStr)
- {
+ switch (init->drvStr) {
case opaDrvStrLowerAccLowStr:
calData = (init->ugBwScale ? DEVINFO->OPA2CAL0 : DEVINFO->OPA2CAL4);
break;
@@ -614,16 +592,15 @@
break;
}
break;
+#endif
}
- if (!init->defaultOffsetN)
- {
+ if (!init->defaultOffsetN) {
EFM_ASSERT(init->offsetN <= (_VDAC_OPA_CAL_OFFSETN_MASK
>> _VDAC_OPA_CAL_OFFSETN_SHIFT));
calData = (calData & ~_VDAC_OPA_CAL_OFFSETN_MASK)
| (init->offsetN << _VDAC_OPA_CAL_OFFSETN_SHIFT);
}
- if (!init->defaultOffsetP)
- {
+ if (!init->defaultOffsetP) {
EFM_ASSERT(init->offsetP <= (_VDAC_OPA_CAL_OFFSETP_MASK
>> _VDAC_OPA_CAL_OFFSETP_SHIFT));
calData = (calData & ~_VDAC_OPA_CAL_OFFSETP_MASK)
@@ -641,8 +618,7 @@
dac->OPA[opa].OUT = (uint32_t)init->outMode
| (uint32_t)init->outPen;
- switch (init->drvStr)
- {
+ switch (init->drvStr) {
case opaDrvStrHigherAccHighStr:
warmupTime = 6;
break;
@@ -678,22 +654,23 @@
| (init->prsEn ? VDAC_OPA_CTRL_PRSEN : 0)
| (init->halfDrvStr
? VDAC_OPA_CTRL_OUTSCALE_HALF
- : VDAC_OPA_CTRL_OUTSCALE_FULL)
+ : VDAC_OPA_CTRL_OUTSCALE_FULL)
| (init->hcmDisable ? VDAC_OPA_CTRL_HCMDIS : 0)
| (init->ugBwScale ? VDAC_OPA_CTRL_INCBW : 0)
| (uint32_t)init->drvStr;
- if (opa == OPA0)
- {
+ if (opa == OPA0) {
+#if defined(VDAC_STATUS_OPA0ENS)
dac->CMD |= VDAC_CMD_OPA0EN;
- }
- else if (opa == OPA1)
- {
+#endif
+ } else if (opa == OPA1) {
+#if defined(VDAC_STATUS_OPA1ENS)
dac->CMD |= VDAC_CMD_OPA1EN;
- }
- else /* OPA2 */
- {
+#endif
+ } else { /* OPA2 */
+#if defined(VDAC_STATUS_OPA2ENS)
dac->CMD |= VDAC_CMD_OPA2EN;
+#endif
}
#endif
@@ -703,4 +680,4 @@
/** @} (end addtogroup emlib) */
#endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)
- || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */
+ || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_pcnt.c
* @brief Pulse Counter (PCNT) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -59,22 +59,20 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-
/** Validation of PCNT register block pointer reference for assert statements. */
#if (PCNT_COUNT == 1)
#define PCNT_REF_VALID(ref) ((ref) == PCNT0)
#elif (PCNT_COUNT == 2)
#define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1))
#elif (PCNT_COUNT == 3)
-#define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1) || \
- ((ref) == PCNT2))
+#define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1) \
+ || ((ref) == PCNT2))
#else
#error "Undefined number of pulse counters (PCNT)."
#endif
/** @endcond */
-
/*******************************************************************************
************************** LOCAL FUNCTIONS ********************************
******************************************************************************/
@@ -96,7 +94,6 @@
return ((uint32_t)pcnt - PCNT0_BASE) / 0x400;
}
-
/***************************************************************************//**
* @brief
* Wait for ongoing sync of register(s) to low frequency domain to complete.
@@ -112,8 +109,7 @@
{
/* Avoid deadlock if modifying the same register twice when freeze mode is
* activated. */
- if (pcnt->FREEZE & PCNT_FREEZE_REGFREEZE)
- {
+ if (pcnt->FREEZE & PCNT_FREEZE_REGFREEZE) {
return;
}
@@ -154,7 +150,6 @@
BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0);
}
-
/***************************************************************************//**
* @brief
* Set counter and top values.
@@ -186,26 +181,23 @@
EFM_ASSERT(PCNT_REF_VALID(pcnt));
#ifdef PCNT0
- if (PCNT0 == pcnt)
- {
- EFM_ASSERT((1<<PCNT0_CNT_SIZE) > count);
- EFM_ASSERT((1<<PCNT0_CNT_SIZE) > top);
+ if (PCNT0 == pcnt) {
+ EFM_ASSERT((1 << PCNT0_CNT_SIZE) > count);
+ EFM_ASSERT((1 << PCNT0_CNT_SIZE) > top);
}
#endif
#ifdef PCNT1
- if (PCNT1 == pcnt)
- {
- EFM_ASSERT((1<<PCNT1_CNT_SIZE) > count);
- EFM_ASSERT((1<<PCNT1_CNT_SIZE) > top);
+ if (PCNT1 == pcnt) {
+ EFM_ASSERT((1 << PCNT1_CNT_SIZE) > count);
+ EFM_ASSERT((1 << PCNT1_CNT_SIZE) > top);
}
#endif
#ifdef PCNT2
- if (PCNT2 == pcnt)
- {
- EFM_ASSERT((1<<PCNT2_CNT_SIZE) > count);
- EFM_ASSERT((1<<PCNT2_CNT_SIZE) > top);
+ if (PCNT2 == pcnt) {
+ EFM_ASSERT((1 << PCNT2_CNT_SIZE) > count);
+ EFM_ASSERT((1 << PCNT2_CNT_SIZE) > top);
}
#endif
@@ -213,8 +205,7 @@
ctrl = pcnt->CTRL;
/* If enabled, disable pulse counter before changing values */
- if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE)
- {
+ if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE) {
PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
pcnt->CTRL = (ctrl & ~_PCNT_CTRL_MODE_MASK) | PCNT_CTRL_MODE_DISABLE;
}
@@ -236,8 +227,7 @@
/* Restore TOP? ('count' setting has been loaded into pcnt->TOP, better
* to use 'top' than pcnt->TOP in compare, since latter may in theory not
* be visible yet.) */
- if (top != count)
- {
+ if (top != count) {
/* Wait for command to sync LCNTIM before setting TOPB */
PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD);
@@ -251,14 +241,12 @@
}
/* Reenable if it was enabled */
- if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE)
- {
+ if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE) {
PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL | PCNT_SYNCBUSY_CMD);
pcnt->CTRL = ctrl;
}
}
-
/***************************************************************************//**
* @brief
* Set PCNT operational mode.
@@ -320,8 +308,7 @@
EFM_ASSERT(PCNT_REF_VALID(pcnt));
/* Enable/disable the selected PRS input on the selected PCNT module. */
- switch (prsInput)
- {
+ switch (prsInput) {
/* Enable/disable PRS input S0. */
case pcntPRSInputS0:
BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S0PRSEN_SHIFT, enable);
@@ -335,12 +322,11 @@
/* Invalid parameter, asserted. */
default:
EFM_ASSERT(0);
- break;
+ break;
}
}
#endif
-
/***************************************************************************//**
* @brief
* PCNT register synchronization freeze control.
@@ -372,8 +358,7 @@
{
EFM_ASSERT(PCNT_REF_VALID(pcnt));
- if (enable)
- {
+ if (enable) {
/* Wait for any ongoing LF synchronization to complete. This is just to
* protect against the rare case when a user:
* - modifies a register requiring LF sync
@@ -385,14 +370,11 @@
;
pcnt->FREEZE = PCNT_FREEZE_REGFREEZE;
- }
- else
- {
+ } else {
pcnt->FREEZE = 0;
}
}
-
/***************************************************************************//**
* @brief
* Init pulse counter.
@@ -440,26 +422,23 @@
EFM_ASSERT(PCNT_REF_VALID(pcnt));
#ifdef PCNT0
- if (PCNT0 == pcnt)
- {
- EFM_ASSERT((1<<PCNT0_CNT_SIZE) > init->counter);
- EFM_ASSERT((1<<PCNT0_CNT_SIZE) > init->top);
+ if (PCNT0 == pcnt) {
+ EFM_ASSERT((1 << PCNT0_CNT_SIZE) > init->counter);
+ EFM_ASSERT((1 << PCNT0_CNT_SIZE) > init->top);
}
#endif
#ifdef PCNT1
- if (PCNT1 == pcnt)
- {
- EFM_ASSERT((1<<PCNT1_CNT_SIZE) > init->counter);
- EFM_ASSERT((1<<PCNT1_CNT_SIZE) > init->top);
+ if (PCNT1 == pcnt) {
+ EFM_ASSERT((1 << PCNT1_CNT_SIZE) > init->counter);
+ EFM_ASSERT((1 << PCNT1_CNT_SIZE) > init->top);
}
#endif
#ifdef PCNT2
- if (PCNT2 == pcnt)
- {
- EFM_ASSERT((1<<PCNT2_CNT_SIZE) > init->counter);
- EFM_ASSERT((1<<PCNT2_CNT_SIZE) > init->top);
+ if (PCNT2 == pcnt) {
+ EFM_ASSERT((1 << PCNT2_CNT_SIZE) > init->counter);
+ EFM_ASSERT((1 << PCNT2_CNT_SIZE) > init->top);
}
#endif
@@ -471,38 +450,33 @@
* written with a Read-Modify-Write sequence in order to keep the value of the
* input enable bits which can be modified using PCNT_PRSInputEnable(). */
tmp = pcnt->INPUT & ~(_PCNT_INPUT_S0PRSSEL_MASK | _PCNT_INPUT_S1PRSSEL_MASK);
- tmp |= ((uint32_t)init->s0PRS << _PCNT_INPUT_S0PRSSEL_SHIFT) |
- ((uint32_t)init->s1PRS << _PCNT_INPUT_S1PRSSEL_SHIFT);
+ tmp |= ((uint32_t)init->s0PRS << _PCNT_INPUT_S0PRSSEL_SHIFT)
+ | ((uint32_t)init->s1PRS << _PCNT_INPUT_S1PRSSEL_SHIFT);
pcnt->INPUT = tmp;
#endif
/* Build CTRL setting, except for mode */
tmp = 0;
- if (init->negEdge)
- {
+ if (init->negEdge) {
tmp |= PCNT_CTRL_EDGE_NEG;
}
- if (init->countDown)
- {
+ if (init->countDown) {
tmp |= PCNT_CTRL_CNTDIR_DOWN;
}
- if (init->filter)
- {
+ if (init->filter) {
tmp |= PCNT_CTRL_FILT;
}
#if defined(PCNT_CTRL_HYST)
- if (init->hyst)
- {
+ if (init->hyst) {
tmp |= PCNT_CTRL_HYST;
}
#endif
#if defined(PCNT_CTRL_S1CDIR)
- if (init->s1CntDir)
- {
+ if (init->s1CntDir) {
tmp |= PCNT_CTRL_S1CDIR;
}
#endif
@@ -518,10 +492,9 @@
the CTRL register because the AUXCNTEV field values are different from
the CNTEV field values, and cntEvent and auxCntEvent are of the same type
PCNT_CntEvent_TypeDef.
- */
+ */
uint32_t auxCntEventField = 0; /* Get rid of compiler warning. */
- switch (init->auxCntEvent)
- {
+ switch (init->auxCntEvent) {
case pcntCntEventBoth:
auxCntEventField = pcntCntEventNone;
break;
@@ -549,8 +522,7 @@
CMU_PCNTClockExternalSet(inst, false);
/* Handling depends on whether using external clock or not. */
- switch (init->mode)
- {
+ switch (init->mode) {
case pcntModeExtSingle:
case pcntModeExtQuad:
tmp |= init->mode << _PCNT_CTRL_MODE_SHIFT;
@@ -596,8 +568,7 @@
/* pcntModeOvsSingle */
default:
/* No need to set disabled mode if already disabled. */
- if ((pcnt->CTRL & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE)
- {
+ if ((pcnt->CTRL & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE) {
/* Set control to disabled mode, leave reset on until ensured disabled.
* We don't need to wait for CTRL SYNCBUSY completion here, it was
* triggered by reset bit above, which is asynchronous. */
@@ -615,8 +586,7 @@
PCNT_CounterTopSet(pcnt, init->counter, init->top);
/* Enter oversampling mode if selected. */
- if (init->mode == pcntModeOvsSingle)
- {
+ if (init->mode == pcntModeOvsSingle) {
PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
pcnt->CTRL = tmp | (init->mode << _PCNT_CTRL_MODE_SHIFT);
}
@@ -624,7 +594,6 @@
}
}
-
/***************************************************************************//**
* @brief
* Reset PCNT to same state as after a HW reset.
@@ -695,7 +664,8 @@
* @param[in] enable
* Whether to enable or disable filtering
******************************************************************************/
-void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable) {
+void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable)
+{
uint32_t ovscfg = 0;
EFM_ASSERT(PCNT_REF_VALID(pcnt));
@@ -708,15 +678,11 @@
PCNT_Sync(pcnt, PCNT_SYNCBUSY_OVSCFG);
pcnt->OVSCFG = ovscfg;
-
/* Set new state of filter. LF register requires sync check before writing. */
PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
- if(enable)
- {
+ if (enable) {
pcnt->CTRL |= PCNT_CTRL_FILT;
- }
- else
- {
+ } else {
pcnt->CTRL &= ~PCNT_CTRL_FILT;
}
}
@@ -744,7 +710,8 @@
* @param[in] config
* Pointer to configuration structure to be applied.
******************************************************************************/
-void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config){
+void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config)
+{
uint32_t ctrl = 0;
uint32_t mask = _PCNT_CTRL_TCCMODE_MASK
| _PCNT_CTRL_TCCPRESC_MASK
@@ -756,12 +723,12 @@
EFM_ASSERT(PCNT_REF_VALID(pcnt));
/* construct TCC part of configuration register */
- ctrl |= (config->mode << _PCNT_CTRL_TCCMODE_SHIFT ) & _PCNT_CTRL_TCCMODE_MASK;
- ctrl |= (config->prescaler << _PCNT_CTRL_TCCPRESC_SHIFT ) & _PCNT_CTRL_TCCPRESC_MASK;
- ctrl |= (config->compare << _PCNT_CTRL_TCCCOMP_SHIFT ) & _PCNT_CTRL_TCCCOMP_MASK;
- ctrl |= (config->tccPRS << _PCNT_CTRL_TCCPRSSEL_SHIFT ) & _PCNT_CTRL_TCCPRSSEL_MASK;
- ctrl |= (config->prsPolarity << _PCNT_CTRL_TCCPRSPOL_SHIFT ) & _PCNT_CTRL_TCCPRSPOL_MASK;
- ctrl |= (config->prsGateEnable << _PCNT_CTRL_PRSGATEEN_SHIFT ) & _PCNT_CTRL_PRSGATEEN_MASK;
+ ctrl |= (config->mode << _PCNT_CTRL_TCCMODE_SHIFT) & _PCNT_CTRL_TCCMODE_MASK;
+ ctrl |= (config->prescaler << _PCNT_CTRL_TCCPRESC_SHIFT) & _PCNT_CTRL_TCCPRESC_MASK;
+ ctrl |= (config->compare << _PCNT_CTRL_TCCCOMP_SHIFT) & _PCNT_CTRL_TCCCOMP_MASK;
+ ctrl |= (config->tccPRS << _PCNT_CTRL_TCCPRSSEL_SHIFT) & _PCNT_CTRL_TCCPRSSEL_MASK;
+ ctrl |= (config->prsPolarity << _PCNT_CTRL_TCCPRSPOL_SHIFT) & _PCNT_CTRL_TCCPRSPOL_MASK;
+ ctrl |= (config->prsGateEnable << _PCNT_CTRL_PRSGATEEN_SHIFT) & _PCNT_CTRL_PRSGATEEN_MASK;
/* Load new TCC config to PCNT. LF register requires sync check before write. */
PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
@@ -794,7 +761,6 @@
pcnt->TOPB = val;
}
-
/***************************************************************************//**
* @brief
* Set top value.
@@ -816,23 +782,20 @@
EFM_ASSERT(PCNT_REF_VALID(pcnt));
#ifdef PCNT0
- if (PCNT0 == pcnt)
- {
- EFM_ASSERT((1<<PCNT0_CNT_SIZE) > val);
+ if (PCNT0 == pcnt) {
+ EFM_ASSERT((1 << PCNT0_CNT_SIZE) > val);
}
#endif
#ifdef PCNT1
- if (PCNT1 == pcnt)
- {
- EFM_ASSERT((1<<PCNT1_CNT_SIZE) > val);
+ if (PCNT1 == pcnt) {
+ EFM_ASSERT((1 << PCNT1_CNT_SIZE) > val);
}
#endif
#ifdef PCNT2
- if (PCNT2 == pcnt)
- {
- EFM_ASSERT((1<<PCNT2_CNT_SIZE) > val);
+ if (PCNT2 == pcnt) {
+ EFM_ASSERT((1 << PCNT2_CNT_SIZE) > val);
}
#endif
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_prs.c
* @brief Peripheral Reflex System (PRS) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -83,7 +83,7 @@
| (uint32_t)edge;
}
-#if defined( PRS_CH_CTRL_ASYNC )
+#if defined(PRS_CH_CTRL_ASYNC)
/***************************************************************************//**
* @brief
* Set source and asynchronous signal to be used for a channel.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_qspi.c Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,287 @@
+/***************************************************************************//**
+ * @file em_qspi.c
+ * @brief QSPI Octal-SPI Flash Controller API
+ * @version 5.3.3
+ *******************************************************************************
+ * # License
+ * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ *******************************************************************************
+ *
+ * Permission is granted to anyone to use this software for any purpose,
+ * including commercial applications, and to alter it and redistribute it
+ * freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ * claim that you wrote the original software.
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ * misrepresented as being the original software.
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
+ * obligation to support this Software. Silicon Labs is providing the
+ * Software "AS IS", with no express or implied warranties of any kind,
+ * including, but not limited to, any implied warranties of merchantability
+ * or fitness for any particular purpose or warranties against infringement
+ * of any proprietary rights of a third party.
+ *
+ * Silicon Labs will not be liable for any consequential, incidental, or
+ * special damages, or any other relief, or for any claim by any third party,
+ * arising from your use of this Software.
+ *
+ ******************************************************************************/
+
+#include "em_qspi.h"
+
+#if defined(QSPI_COUNT) && (QSPI_COUNT > 0)
+
+#include "em_assert.h"
+
+/***************************************************************************//**
+ * @addtogroup emlib
+ * @{
+ ******************************************************************************/
+
+/* *INDENT-OFF* */
+/***************************************************************************//**
+ * @addtogroup QSPI
+ * @brief QSPI Octal-SPI Controller API
+ * @details
+ * These QSPI functions provide basic support for using the QSPI peripheral
+ * in the following configurations:
+ * @li @b Direct Read/Write, used for memory mapped access to external
+ * memory.
+ * @li @b STIG Command, used for configuring and executing commands on the
+ * external memory device.
+ *
+ * Indirect read/write, PHY configuration and Execute-In-Place (XIP)
+ * configuration is not supported.
+ *
+ * The example below shows how to set up the QSPI for direct read and write
+ * operation:
+ * @code
+ CMU_ClockEnable(cmuClock_GPIO, true);
+ CMU_ClockEnable(cmuClock_QSPI0, true);
+
+ QSPI_Init_TypeDef initQspi = QSPI_INIT_DEFAULT;
+ QSPI_Init(QSPI0, &initQspi);
+
+ // Configure QSPI pins
+ GPIO_PinModeSet(EXTFLASH_PORT_CS, EXTFLASH_PIN_CS, gpioModePushPull, 0);
+ GPIO_PinModeSet(EXTFLASH_PORT_SCLK, EXTFLASH_PIN_SCLK, gpioModePushPull, 0);
+ GPIO_PinModeSet(EXTFLASH_PORT_DQ0, EXTFLASH_PIN_DQ0, gpioModePushPull, 0);
+ GPIO_PinModeSet(EXTFLASH_PORT_DQ1, EXTFLASH_PIN_DQ1, gpioModePushPull, 0);
+ GPIO_PinModeSet(EXTFLASH_PORT_DQ2, EXTFLASH_PIN_DQ2, gpioModePushPull, 0);
+ GPIO_PinModeSet(EXTFLASH_PORT_DQ3, EXTFLASH_PIN_DQ3, gpioModePushPull, 0);
+
+ // Configure QSPI routing to GPIO
+ QSPI0->ROUTELOC0 = EXTFLASH_QSPI_LOC;
+ QSPI0->ROUTEPEN = QSPI_ROUTEPEN_SCLKPEN
+ | EXTFLASH_QSPI_CSPEN
+ | QSPI_ROUTEPEN_DQ0PEN
+ | QSPI_ROUTEPEN_DQ1PEN
+ | QSPI_ROUTEPEN_DQ2PEN
+ | QSPI_ROUTEPEN_DQ3PEN;
+
+ // Configure direct read
+ QSPI_ReadConfig_TypeDef readConfig = QSPI_READCONFIG_DEFAULT;
+
+ readConfig.dummyCycles = 8;
+ readConfig.opCode = 0x6B;
+ readConfig.instTransfer = qspiTransferSingle;
+ readConfig.addrTransfer = qspiTransferSingle;
+ readConfig.dataTransfer = qspiTransferQuad;
+
+ QSPI_ReadConfig(QSPI0, &readConfig);
+
+ // Configure direct write
+ QSPI_WriteConfig_TypeDef writeConfig = QSPI_WRITECONFIG_DEFAULT;
+
+ writeConfig.dummyCycles = 0;
+ writeConfig.opCode = 0x38;
+ writeConfig.addrTransfer = qspiTransferQuad;
+ writeConfig.dataTransfer = qspiTransferQuad;
+ writeConfig.autoWEL = true;
+
+ QSPI_WriteConfig(QSPI0, &writeConfig);@endcode
+ *
+ * To configure an external flash, commands can set up and executed using the
+ * Software Triggered Instruction Generator (STIG) function of the QSPI, as
+ * shown in the example below:
+ * @code
+ uint8_t status;
+ QSPI_StigCmd_TypeDef stigCmd = {0};
+ stigCmd.cmdOpcode = EXTFLASH_OPCODE_READ_STATUS;
+ stigCmd.readDataSize = 1;
+ stigCmd.readBuffer = &status;
+ QSPI_ExecStigCmd(QSPI0, &stigCmd);@endcode
+ * @{
+ ******************************************************************************/
+/* *INDENT-OFF* */
+
+/*******************************************************************************
+ ************************** GLOBAL FUNCTIONS *******************************
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * @brief
+ * Initialize QSPI.
+ *
+ * @param[in] qspi
+ * Pointer to the QSPI peripheral register block.
+ *
+ * @param[in] init
+ * Pointer to initialization structure used to configure QSPI.
+ ******************************************************************************/
+void QSPI_Init(QSPI_TypeDef * qspi, const QSPI_Init_TypeDef * init)
+{
+ uint32_t divisor;
+
+ EFM_ASSERT((init->divisor >= 2) && (init->divisor <= 32));
+ divisor = init->divisor / 2 - 1;
+
+ qspi->CONFIG = (qspi->CONFIG & ~_QSPI_CONFIG_MSTRBAUDDIV_MASK)
+ | (divisor << _QSPI_CONFIG_MSTRBAUDDIV_SHIFT);
+ QSPI_Enable(qspi, init->enable);
+}
+
+/***************************************************************************//**
+ * @brief
+ * Configure Read Operations.
+ *
+ * @param[in] qspi
+ * Pointer to the QSPI peripheral register block.
+ *
+ * @param[in] config
+ * Pointer to configuration structure for QSPI read operations.
+ ******************************************************************************/
+void QSPI_ReadConfig(QSPI_TypeDef * qspi, const QSPI_ReadConfig_TypeDef * config)
+{
+ EFM_ASSERT(config->dummyCycles < 31);
+
+ QSPI_WaitForIdle(qspi);
+ qspi->DEVINSTRRDCONFIG = (config->opCode << _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_SHIFT)
+ | (config->dummyCycles << _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_SHIFT)
+ | (config->addrTransfer << _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_SHIFT)
+ | (config->dataTransfer << _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_SHIFT)
+ | (config->instTransfer << _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_SHIFT);
+}
+
+/***************************************************************************//**
+ * @brief
+ * Configure Write Operations.
+ *
+ * @param[in] qspi
+ * Pointer to the QSPI peripheral register block.
+ *
+ * @param[in] config
+ * Pointer to configuration structure for QSPI write operations.
+ ******************************************************************************/
+void QSPI_WriteConfig(QSPI_TypeDef * qspi, const QSPI_WriteConfig_TypeDef * config)
+{
+ EFM_ASSERT(config->dummyCycles < 31);
+
+ QSPI_WaitForIdle(qspi);
+ qspi->DEVINSTRWRCONFIG = (config->opCode << _QSPI_DEVINSTRWRCONFIG_WROPCODE_SHIFT)
+ | (config->dummyCycles << _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_SHIFT)
+ | (config->addrTransfer << _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_SHIFT)
+ | (config->dataTransfer << _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_SHIFT)
+ | ((config->autoWEL ? 0 : 1) << _QSPI_DEVINSTRWRCONFIG_WELDIS_SHIFT);
+}
+
+/***************************************************************************//**
+ * @brief
+ * Execute a STIG command.
+ *
+ * @details
+ * STIG means "software triggered instruction generator" and is used when the
+ * application needs to access status registers, configuration registers or
+ * perform erase functions. The STIG commands can be used to perform any
+ * instruction that the flash device supports.
+ *
+ * @param[in] qspi
+ * Pointer to the QSPI peripheral register block.
+ *
+ * @param[in] stigCmd
+ * Pointer to a structure that describes the STIG command.
+ ******************************************************************************/
+void QSPI_ExecStigCmd(QSPI_TypeDef * qspi, const QSPI_StigCmd_TypeDef * stigCmd)
+{
+ uint32_t i;
+
+ EFM_ASSERT(stigCmd->addrSize <= 4);
+ EFM_ASSERT(stigCmd->writeDataSize <= 8);
+ EFM_ASSERT(stigCmd->readDataSize <= 8);
+ EFM_ASSERT(stigCmd->dummyCycles < 32);
+
+ if (stigCmd->writeDataSize) {
+ EFM_ASSERT(stigCmd->writeBuffer);
+ }
+
+ if (stigCmd->readDataSize) {
+ EFM_ASSERT(stigCmd->readBuffer);
+ }
+
+ QSPI_WaitForIdle(qspi);
+
+ qspi->FLASHCMDCTRL = (stigCmd->cmdOpcode << _QSPI_FLASHCMDCTRL_CMDOPCODE_SHIFT)
+ | (stigCmd->dummyCycles << _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_SHIFT);
+
+ if (stigCmd->writeDataSize) {
+ uint32_t buffer[2] = { 0, 0 };
+ uint8_t * dst = (uint8_t *) buffer;
+ uint8_t * src = stigCmd->writeBuffer;
+
+ qspi->FLASHCMDCTRL |= QSPI_FLASHCMDCTRL_ENBWRITEDATA
+ | ((stigCmd->writeDataSize - 1)
+ << _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_SHIFT);
+
+ for (i = 0; i < stigCmd->writeDataSize; i++) {
+ dst[i] = src[i];
+ }
+
+ qspi->FLASHWRDATALOWER = buffer[0];
+ qspi->FLASHWRDATAUPPER = buffer[1];
+ }
+
+ if (stigCmd->addrSize) {
+ qspi->FLASHCMDCTRL |= QSPI_FLASHCMDCTRL_ENBCOMDADDR
+ | ((stigCmd->addrSize - 1)
+ << _QSPI_FLASHCMDCTRL_NUMADDRBYTES_SHIFT);
+ qspi->FLASHCMDADDR = stigCmd->address;
+ }
+
+ if (stigCmd->modeBitEnable) {
+ qspi->FLASHCMDCTRL |= QSPI_FLASHCMDCTRL_ENBMODEBIT;
+ }
+
+ if (stigCmd->readDataSize) {
+ qspi->FLASHCMDCTRL |= QSPI_FLASHCMDCTRL_ENBREADDATA
+ | ((stigCmd->readDataSize - 1)
+ << _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_SHIFT);
+ }
+
+ // Start command execution
+ qspi->FLASHCMDCTRL |= QSPI_FLASHCMDCTRL_CMDEXEC;
+
+ while (qspi->FLASHCMDCTRL & QSPI_FLASHCMDCTRL_CMDEXECSTATUS)
+ ;
+
+ // Read data if any
+ if (stigCmd->readDataSize) {
+ uint32_t buffer[2] = { 0, 0 };
+ const uint8_t * src = (const uint8_t *)buffer;
+ uint8_t * dst = stigCmd->readBuffer;
+
+ buffer[0] = qspi->FLASHRDDATALOWER;
+ buffer[1] = qspi->FLASHRDDATAUPPER;
+
+ for (i = 0; i < stigCmd->readDataSize; i++) {
+ dst[i] = src[i];
+ }
+ }
+}
+
+/** @} (end addtogroup QSPI) */
+/** @} (end addtogroup emlib) */
+
+#endif /* defined(QSPI_COUNT) && (QSPI_COUNT > 0) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c Thu Dec 07 14:01:42 2017 +0000
@@ -2,9 +2,9 @@
* @file em_rmu.c
* @brief Reset Management Unit (RMU) peripheral module peripheral API
*
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -124,11 +124,25 @@
#define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */
#define NUM_RSTCAUSES 9
+/* EFM32GG11 */
+#elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00011F1DUL)
+#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */
+#define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */
+#define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */
+#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */
+#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */
+#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */
+#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */
+#define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */
+#define RMU_RSTCAUSE_BUMODERST_XMASK 0x0000001DUL /** 0000000000011101 < Backup mode reset */
+#define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */
+#define NUM_RSTCAUSES 10
+
#else
#error "RMU_RSTCAUSE XMASKs are not defined for this family."
#endif
-#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
/* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H */
#define ERRATA_FIX_EMU_E208_EN
#endif
@@ -138,63 +152,62 @@
******************************************************************************/
/** Reset cause mask type. */
-typedef struct
-{
+typedef struct {
/** Reset-cause 1 bits */
uint32_t resetCauseMask;
/** Reset-cause 0 and "don't care" bits */
uint32_t resetCauseZeroXMask;
} RMU_ResetCauseMasks_Typedef;
-
/*******************************************************************************
******************************* TYPEDEFS **********************************
******************************************************************************/
/** Reset cause mask table. */
static const RMU_ResetCauseMasks_Typedef resetCauseMasks[NUM_RSTCAUSES] =
- {
- { RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK },
+{
+ { RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK },
#if defined(RMU_RSTCAUSE_BODUNREGRST)
- { RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK },
+ { RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK },
#endif
#if defined(RMU_RSTCAUSE_BODREGRST)
- { RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK },
+ { RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK },
#endif
#if defined(RMU_RSTCAUSE_AVDDBOD)
- { RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK },
+ { RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK },
#endif
#if defined(RMU_RSTCAUSE_DVDDBOD)
- { RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK },
+ { RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK },
#endif
#if defined(RMU_RSTCAUSE_DECBOD)
- { RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK },
+ { RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK },
#endif
- { RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK },
- { RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK },
- { RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK },
- { RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK },
+ { RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK },
+ { RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK },
+ { RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK },
+ { RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK },
#if defined(RMU_RSTCAUSE_EM4RST)
- { RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK },
+ { RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK },
#endif
#if defined(RMU_RSTCAUSE_EM4WURST)
- { RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK },
+ { RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK },
#endif
#if defined(RMU_RSTCAUSE_BODAVDD0)
- { RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK },
+ { RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK },
#endif
#if defined(RMU_RSTCAUSE_BODAVDD1)
- { RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK },
+ { RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK },
#endif
-#if defined(BU_PRESENT)
- { RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK },
- { RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK },
- { RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK },
- { RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK },
- { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK },
+#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
+ { RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK },
+ { RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK },
+ { RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK },
+ { RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK },
+ { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK },
+#elif defined(RMU_RSTCAUSE_BUMODERST)
+ { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK },
#endif
- };
-
+};
/*******************************************************************************
******************************** TEST ********************************
@@ -236,7 +249,6 @@
#endif
}
-
/***************************************************************************//**
* @brief
* Clear the reset cause register.
@@ -257,23 +269,20 @@
/* Clear some reset causes not cleared with RMU CMD register */
/* (If EMU registers locked, they must be unlocked first) */
locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED;
- if (locked)
- {
+ if (locked) {
EMU_Unlock();
}
BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1);
BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0);
- if (locked)
- {
+ if (locked) {
EMU_Lock();
}
}
#endif
}
-
/***************************************************************************//**
* @brief
* Get the cause of the last reset.
@@ -290,7 +299,7 @@
******************************************************************************/
uint32_t RMU_ResetCauseGet(void)
{
-#define LB_CLW0 (* ((volatile uint32_t *)(LOCKBITS_BASE) + 122))
+#define LB_CLW0 (*((volatile uint32_t *)(LOCKBITS_BASE) +122))
#define LB_CLW0_PINRESETSOFT (1 << 2)
#if !defined(EMLIB_REGRESSION_TEST)
@@ -300,22 +309,19 @@
uint32_t zeroXMask;
uint32_t i;
- for (i = 0; i < NUM_RSTCAUSES; i++)
- {
+ for (i = 0; i < NUM_RSTCAUSES; i++) {
zeroXMask = resetCauseMasks[i].resetCauseZeroXMask;
-#if defined( _SILICON_LABS_32B_SERIES_1 )
+#if defined(_SILICON_LABS_32B_SERIES_1)
/* Handle soft/hard pin reset */
- if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT))
- {
+ if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT)) {
/* RSTCAUSE_EXTRST must be 0 if pin reset is configured as hard reset */
- switch (resetCauseMasks[i].resetCauseMask)
- {
+ switch (resetCauseMasks[i].resetCauseMask) {
case RMU_RSTCAUSE_LOCKUPRST:
- /* Fallthrough */
+ /* Fallthrough */
case RMU_RSTCAUSE_SYSREQRST:
- /* Fallthrough */
+ /* Fallthrough */
case RMU_RSTCAUSE_WDOGRST:
- /* Fallthrough */
+ /* Fallthrough */
case RMU_RSTCAUSE_EM4RST:
zeroXMask |= RMU_RSTCAUSE_EXTRST;
break;
@@ -323,10 +329,9 @@
}
#endif
-#if defined( _EMU_EM4CTRL_MASK ) && defined( ERRATA_FIX_EMU_E208_EN )
+#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN)
/* Ignore BOD flags impacted by EMU_E208 */
- if (*(volatile uint32_t *)(EMU_BASE + 0x88) & (0x1 << 8))
- {
+ if (*(volatile uint32_t *)(EMU_BASE + 0x88) & (0x1 << 8)) {
zeroXMask &= ~(RMU_RSTCAUSE_DECBOD
| RMU_RSTCAUSE_DVDDBOD
| RMU_RSTCAUSE_AVDDBOD);
@@ -336,25 +341,22 @@
/* Check reset cause requirements. Note that a bit is "don't care" if 0 in
both resetCauseMask and resetCauseZeroXMask. */
if ((rstCause & resetCauseMasks[i].resetCauseMask)
- && !(rstCause & zeroXMask))
- {
+ && !(rstCause & zeroXMask)) {
/* Add this reset-cause to the mask of qualified reset-causes */
validRstCause |= resetCauseMasks[i].resetCauseMask;
}
}
-#if defined( _EMU_EM4CTRL_MASK ) && defined( ERRATA_FIX_EMU_E208_EN )
+#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN)
/* Clear BOD flags impacted by EMU_E208 */
- if (validRstCause & RMU_RSTCAUSE_EM4RST)
- {
+ if (validRstCause & RMU_RSTCAUSE_EM4RST) {
validRstCause &= ~(RMU_RSTCAUSE_DECBOD
- | RMU_RSTCAUSE_DVDDBOD
- | RMU_RSTCAUSE_AVDDBOD);
+ | RMU_RSTCAUSE_DVDDBOD
+ | RMU_RSTCAUSE_AVDDBOD);
}
#endif
return validRstCause;
}
-
/** @} (end addtogroup RMU) */
/** @} (end addtogroup emlib) */
#endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_rtc.c
* @brief Real Time Counter (RTC) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -61,7 +61,6 @@
/** @endcond */
-
/*******************************************************************************
************************** LOCAL FUNCTIONS ********************************
******************************************************************************/
@@ -88,8 +87,9 @@
{
/* Avoid deadlock if modifying the same register twice when freeze mode is */
/* activated. */
- if (RTC->FREEZE & RTC_FREEZE_REGFREEZE)
+ if (RTC->FREEZE & RTC_FREEZE_REGFREEZE) {
return;
+ }
/* Wait for any pending previous write operation to have been completed */
/* in low frequency domain. This is only required for the Gecko Family */
@@ -120,9 +120,11 @@
EFM_ASSERT(RTC_COMP_REG_VALID(comp));
+#if defined(_RTC_COMP_COMP_MASK)
+ ret = RTC->COMP[comp].COMP;
+#elif defined(_RTC_COMP0_MASK)
/* Initialize selected compare value */
- switch (comp)
- {
+ switch (comp) {
case 0:
ret = RTC->COMP0;
break;
@@ -136,11 +138,10 @@
ret = 0;
break;
}
-
+#endif
return ret;
}
-
/***************************************************************************//**
* @brief
* Set RTC compare register value.
@@ -165,13 +166,19 @@
uint32_t syncbusy;
#endif
- EFM_ASSERT(RTC_COMP_REG_VALID(comp)
- && ((value & ~(_RTC_COMP0_COMP0_MASK
- >> _RTC_COMP0_COMP0_SHIFT)) == 0));
+ EFM_ASSERT(RTC_COMP_REG_VALID(comp));
+#if defined(_RTC_COMP_COMP_COMP_MASK)
+ EFM_ASSERT((value & ~(_RTC_COMP_COMP_COMP_MASK >> _RTC_COMP_COMP_COMP_SHIFT)) == 0);
+#elif defined(_RTC_COMP0_COMP0_MASK)
+ EFM_ASSERT((value & ~(_RTC_COMP0_COMP0_MASK >> _RTC_COMP0_COMP0_SHIFT)) == 0);
+#endif
+
+#if defined(_RTC_COMP_COMP_MASK)
+ compReg = &(RTC->COMP[comp].COMP);
+#elif defined(_RTC_COMP0_MASK)
/* Initialize selected compare value */
- switch (comp)
- {
+ switch (comp) {
case 0:
compReg = &(RTC->COMP0);
#if defined(_EFM32_GECKO_FAMILY)
@@ -190,6 +197,8 @@
/* Unknown compare register selected, abort */
return;
}
+#endif
+
#if defined(_EFM32_GECKO_FAMILY)
/* LF register about to be modified require sync. busy check */
regSync(syncbusy);
@@ -198,7 +207,6 @@
*compReg = value;
}
-
/***************************************************************************//**
* @brief
* Enable/disable RTC.
@@ -231,7 +239,7 @@
#endif
}
-
+#if defined(_RTC_FREEZE_MASK)
/***************************************************************************//**
* @brief
* RTC register synchronization freeze control.
@@ -260,8 +268,7 @@
******************************************************************************/
void RTC_FreezeEnable(bool enable)
{
- if (enable)
- {
+ if (enable) {
#if defined(_EFM32_GECKO_FAMILY)
/* Wait for any ongoing LF synchronization to complete. This is just to */
/* protect against the rare case when a user */
@@ -274,13 +281,11 @@
;
#endif
RTC->FREEZE = RTC_FREEZE_REGFREEZE;
- }
- else
- {
+ } else {
RTC->FREEZE = 0;
}
}
-
+#endif
/***************************************************************************//**
* @brief
@@ -306,26 +311,21 @@
{
uint32_t tmp;
- if (init->enable)
- {
+ if (init->enable) {
tmp = RTC_CTRL_EN;
- }
- else
- {
+ } else {
tmp = 0;
}
/* Configure DEBUGRUN flag, sets whether or not counter should be
* updated when debugger is active */
- if (init->debugRun)
- {
+ if (init->debugRun) {
tmp |= RTC_CTRL_DEBUGRUN;
}
/* Configure COMP0TOP, this will use the COMP0 compare value as an
* overflow value, instead of default 24-bit 0x00ffffff */
- if (init->comp0Top)
- {
+ if (init->comp0Top) {
tmp |= RTC_CTRL_COMP0TOP;
}
@@ -337,8 +337,6 @@
RTC->CTRL = tmp;
}
-
-
/***************************************************************************//**
* @brief
* Restore RTC to reset state
@@ -346,10 +344,17 @@
void RTC_Reset(void)
{
/* Restore all essential RTC register to default config */
+#if defined(_RTC_FREEZE_MASK)
RTC->FREEZE = _RTC_FREEZE_RESETVALUE;
+#endif
RTC->CTRL = _RTC_CTRL_RESETVALUE;
+#if defined(_RTC_COMP_COMP_MASK)
+ RTC->COMP[0].COMP = _RTC_COMP_COMP_RESETVALUE;
+ RTC->COMP[1].COMP = _RTC_COMP_COMP_RESETVALUE;
+#elif defined(_RTC_COMP0_MASK)
RTC->COMP0 = _RTC_COMP0_RESETVALUE;
RTC->COMP1 = _RTC_COMP1_RESETVALUE;
+#endif
RTC->IEN = _RTC_IEN_RESETVALUE;
RTC->IFC = _RTC_IFC_RESETVALUE;
@@ -361,8 +366,6 @@
#endif
}
-
-
/***************************************************************************//**
* @brief
* Restart RTC counter from zero
@@ -374,7 +377,6 @@
RTC_Enable(true);
}
-
/** @} (end addtogroup RTC) */
/** @} (end addtogroup emlib) */
#endif /* defined(RTC_COUNT) && (RTC_COUNT > 0) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file
* @brief Real Time Counter with Calendar (RTCC) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -31,7 +31,7 @@
******************************************************************************/
#include "em_rtcc.h"
-#if defined( RTCC_COUNT ) && ( RTCC_COUNT == 1 )
+#if defined(RTCC_COUNT) && (RTCC_COUNT == 1)
#include "em_bus.h"
/***************************************************************************//**
@@ -78,21 +78,21 @@
* @param[in] confPtr
* Pointer to configuration structure.
******************************************************************************/
-void RTCC_ChannelInit( int ch, RTCC_CCChConf_TypeDef const *confPtr )
+void RTCC_ChannelInit(int ch, RTCC_CCChConf_TypeDef const *confPtr)
{
- EFM_ASSERT( RTCC_CH_VALID( ch ) );
+ EFM_ASSERT(RTCC_CH_VALID(ch) );
EFM_ASSERT( (uint32_t)confPtr->compMask
- < ( _RTCC_CC_CTRL_COMPMASK_MASK >> _RTCC_CC_CTRL_COMPMASK_SHIFT )
- + 1 );
+ < (_RTCC_CC_CTRL_COMPMASK_MASK >> _RTCC_CC_CTRL_COMPMASK_SHIFT)
+ + 1);
/** Configure the selected capture/compare channel. */
- RTCC->CC[ch].CTRL = ( (uint32_t)confPtr->chMode << _RTCC_CC_CTRL_MODE_SHIFT )
- | ( (uint32_t)confPtr->compMatchOutAction << _RTCC_CC_CTRL_CMOA_SHIFT )
- | ( (uint32_t)confPtr->prsSel << _RTCC_CC_CTRL_PRSSEL_SHIFT )
- | ( (uint32_t)confPtr->inputEdgeSel << _RTCC_CC_CTRL_ICEDGE_SHIFT )
- | ( (uint32_t)confPtr->compBase << _RTCC_CC_CTRL_COMPBASE_SHIFT )
- | ( (uint32_t)confPtr->compMask << _RTCC_CC_CTRL_COMPMASK_SHIFT )
- | ( (uint32_t)confPtr->dayCompMode << _RTCC_CC_CTRL_DAYCC_SHIFT );
+ RTCC->CC[ch].CTRL = ( (uint32_t)confPtr->chMode << _RTCC_CC_CTRL_MODE_SHIFT)
+ | ( (uint32_t)confPtr->compMatchOutAction << _RTCC_CC_CTRL_CMOA_SHIFT)
+ | ( (uint32_t)confPtr->prsSel << _RTCC_CC_CTRL_PRSSEL_SHIFT)
+ | ( (uint32_t)confPtr->inputEdgeSel << _RTCC_CC_CTRL_ICEDGE_SHIFT)
+ | ( (uint32_t)confPtr->compBase << _RTCC_CC_CTRL_COMPBASE_SHIFT)
+ | ( (uint32_t)confPtr->compMask << _RTCC_CC_CTRL_COMPMASK_SHIFT)
+ | ( (uint32_t)confPtr->dayCompMode << _RTCC_CC_CTRL_DAYCC_SHIFT);
}
/***************************************************************************//**
@@ -102,7 +102,7 @@
* @param[in] enable
* True to enable RTCC, false to disable.
******************************************************************************/
-void RTCC_Enable( bool enable )
+void RTCC_Enable(bool enable)
{
/* Bitbanding the enable bit in the CTRL register (atomic). */
BUS_RegBitWrite((&RTCC->CTRL), _RTCC_CTRL_ENABLE_SHIFT, enable);
@@ -120,27 +120,27 @@
* @param[in] init
* Pointer to RTCC initialization structure.
******************************************************************************/
-void RTCC_Init( const RTCC_Init_TypeDef *init )
+void RTCC_Init(const RTCC_Init_TypeDef *init)
{
- RTCC->CTRL = ( (uint32_t)init->enable << _RTCC_CTRL_ENABLE_SHIFT )
- | ( (uint32_t)init->debugRun << _RTCC_CTRL_DEBUGRUN_SHIFT )
- | ( (uint32_t)init->precntWrapOnCCV0 << _RTCC_CTRL_PRECCV0TOP_SHIFT )
- | ( (uint32_t)init->cntWrapOnCCV1 << _RTCC_CTRL_CCV1TOP_SHIFT )
- | ( (uint32_t)init->presc << _RTCC_CTRL_CNTPRESC_SHIFT )
- | ( (uint32_t)init->prescMode << _RTCC_CTRL_CNTTICK_SHIFT )
+ RTCC->CTRL = ( (uint32_t)init->enable << _RTCC_CTRL_ENABLE_SHIFT)
+ | ( (uint32_t)init->debugRun << _RTCC_CTRL_DEBUGRUN_SHIFT)
+ | ( (uint32_t)init->precntWrapOnCCV0 << _RTCC_CTRL_PRECCV0TOP_SHIFT)
+ | ( (uint32_t)init->cntWrapOnCCV1 << _RTCC_CTRL_CCV1TOP_SHIFT)
+ | ( (uint32_t)init->presc << _RTCC_CTRL_CNTPRESC_SHIFT)
+ | ( (uint32_t)init->prescMode << _RTCC_CTRL_CNTTICK_SHIFT)
#if defined(_RTCC_CTRL_BUMODETSEN_MASK)
- | ( (uint32_t)init->enaBackupModeSet << _RTCC_CTRL_BUMODETSEN_SHIFT )
+ | ( (uint32_t)init->enaBackupModeSet << _RTCC_CTRL_BUMODETSEN_SHIFT)
#endif
- | ( (uint32_t)init->enaOSCFailDetect << _RTCC_CTRL_OSCFDETEN_SHIFT )
- | ( (uint32_t)init->cntMode << _RTCC_CTRL_CNTMODE_SHIFT )
- | ( (uint32_t)init->disLeapYearCorr << _RTCC_CTRL_LYEARCORRDIS_SHIFT );
+ | ( (uint32_t)init->enaOSCFailDetect << _RTCC_CTRL_OSCFDETEN_SHIFT)
+ | ( (uint32_t)init->cntMode << _RTCC_CTRL_CNTMODE_SHIFT)
+ | ( (uint32_t)init->disLeapYearCorr << _RTCC_CTRL_LYEARCORRDIS_SHIFT);
}
/***************************************************************************//**
* @brief
* Restore RTCC to its reset state.
******************************************************************************/
-void RTCC_Reset( void )
+void RTCC_Reset(void)
{
int i;
@@ -156,8 +156,7 @@
RTCC_StatusClear();
RTCC->EM4WUEN = _RTCC_EM4WUEN_RESETVALUE;
- for (i = 0; i < 3; i++)
- {
+ for (i = 0; i < 3; i++) {
RTCC->CC[i].CTRL = _RTCC_CC_CTRL_RESETVALUE;
RTCC->CC[i].CCV = _RTCC_CC_CCV_RESETVALUE;
RTCC->CC[i].TIME = _RTCC_CC_TIME_RESETVALUE;
@@ -169,10 +168,9 @@
* @brief
* Clear STATUS register.
******************************************************************************/
-void RTCC_StatusClear( void )
+void RTCC_StatusClear(void)
{
- while ( RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD )
- {
+ while ( RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD ) {
// Wait for syncronization.
}
RTCC->CMD = RTCC_CMD_CLRSTATUS;
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_system.c
* @brief System Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -61,10 +61,10 @@
uint8_t tmp;
EFM_ASSERT(rev);
-
- uint32_t pid0 = SECURE_READ(&(ROMTABLE->PID0));
- uint32_t pid1 = SECURE_READ(&(ROMTABLE->PID1));
- uint32_t pid2 = SECURE_READ(&(ROMTABLE->PID2));
+
+ uint32_t pid0 = SECURE_READ(&(ROMTABLE->PID0));
+ uint32_t pid1 = SECURE_READ(&(ROMTABLE->PID1));
+ uint32_t pid2 = SECURE_READ(&(ROMTABLE->PID2));
uint32_t pid3 = SECURE_READ(&(ROMTABLE->PID3));
/* CHIP FAMILY bit [5:2] */
@@ -83,7 +83,6 @@
rev->minor = tmp;
}
-
/***************************************************************************//**
* @brief
* Get factory calibration value for a given peripheral register.
@@ -103,15 +102,8 @@
p = (SYSTEM_CalAddrVal_TypeDef *)(DEVINFO_BASE & 0xFFFFF000);
end = (SYSTEM_CalAddrVal_TypeDef *)DEVINFO_BASE;
- for ( ; p < end; p++)
- {
- if (p->address == 0xFFFFFFFF)
- {
- /* Found table terminator */
- return false;
- }
- if (p->address == (uint32_t)regAddress)
- {
+ for (; p < end; p++) {
+ if (p->address == (uint32_t)regAddress) {
*regAddress = p->calValue;
return true;
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_timer.c
* @brief Timer/counter (TIMER) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -51,7 +51,6 @@
* @{
******************************************************************************/
-
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
@@ -78,8 +77,7 @@
EFM_ASSERT(TIMER_REF_VALID(timer));
/* Stop timer if specified to be disabled (dosn't hurt if already stopped) */
- if (!(init->enable))
- {
+ if (!(init->enable)) {
timer->CMD = TIMER_CMD_STOP;
}
@@ -103,13 +101,11 @@
| (init->sync ? TIMER_CTRL_SYNC : 0);
/* Start timer if specified to be enabled (dosn't hurt if already started) */
- if (init->enable)
- {
+ if (init->enable) {
timer->CMD = TIMER_CMD_START;
}
}
-
/***************************************************************************//**
* @brief
* Initialize TIMER compare/capture channel.
@@ -148,7 +144,6 @@
| (init->outInvert ? TIMER_CC_CTRL_OUTINV : 0);
}
-
#if defined(_TIMER_DTCTRL_MASK)
/***************************************************************************//**
* @brief
@@ -165,7 +160,7 @@
EFM_ASSERT(TIMER0 == timer);
/* Make sure the DTI unit is disabled while initializing. */
- TIMER_EnableDTI (timer, false);
+ TIMER_EnableDTI(timer, false);
/* Setup the DTCTRL register.
The enable bit will be set at the end of the function if specified. */
@@ -199,11 +194,10 @@
TIMER_ClearDTIFault(timer, TIMER_GetDTIFault(timer));
/* Enable/disable before returning. */
- TIMER_EnableDTI (timer, init->enable);
+ TIMER_EnableDTI(timer, init->enable);
}
#endif
-
/***************************************************************************//**
* @brief
* Reset TIMER to same state as after a HW reset.
@@ -234,8 +228,7 @@
/* Do not reset route register, setting should be done independently */
/* (Note: ROUTE register may be locked by DTLOCK register.) */
- for (i = 0; TIMER_CH_VALID(i); i++)
- {
+ for (i = 0; TIMER_CH_VALID(i); i++) {
timer->CC[i].CTRL = _TIMER_CC_CTRL_RESETVALUE;
timer->CC[i].CCV = _TIMER_CC_CCV_RESETVALUE;
timer->CC[i].CCVB = _TIMER_CC_CCVB_RESETVALUE;
@@ -255,7 +248,6 @@
#endif
}
-
/** @} (end addtogroup TIMER) */
/** @} (end addtogroup emlib) */
#endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c Thu Dec 07 14:01:42 2017 +0000
@@ -2,9 +2,9 @@
* @file em_usart.c
* @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART)
* Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -54,7 +54,6 @@
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-
/** Validation of USART register block pointer reference for assert statements. */
#if (USART_COUNT == 1) && defined(USART0)
#define USART_REF_VALID(ref) ((ref) == USART0)
@@ -69,19 +68,19 @@
#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1))
#elif (USART_COUNT == 3)
-#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || \
- ((ref) == USART2))
+#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \
+ || ((ref) == USART2))
#elif (USART_COUNT == 4)
-#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || \
- ((ref) == USART2) || ((ref) == USART3))
+#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \
+ || ((ref) == USART2) || ((ref) == USART3))
#elif (USART_COUNT == 5)
-#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || \
- ((ref) == USART2) || ((ref) == USART3) || \
- ((ref) == USART4))
+#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \
+ || ((ref) == USART2) || ((ref) == USART3) \
+ || ((ref) == USART4))
#elif (USART_COUNT == 6)
-#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || \
- ((ref) == USART2) || ((ref) == USART3) || \
- ((ref) == USART4) || ((ref) == USART5))
+#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \
+ || ((ref) == USART2) || ((ref) == USART3) \
+ || ((ref) == USART4) || ((ref) == USART5))
#else
#error "Undefined number of USARTs."
#endif
@@ -98,6 +97,18 @@
#define USARTRF_REF_VALID(ref) (0)
#endif
+#if defined(_SILICON_LABS_32B_SERIES_1)
+#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
+// If GG11 or TG11
+#define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART2))
+#elif defined(USART3)
+#define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2) || ((ref) == USART3))
+#elif defined(USART2)
+#define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2))
+#else
+#define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1))
+#endif
+#elif defined(_SILICON_LABS_32B_SERIES_0)
#if defined(_EZR32_HAPPY_FAMILY)
#define USART_IRDA_VALID(ref) ((ref) == USART0)
#elif defined(_EFM32_HAPPY_FAMILY)
@@ -106,21 +117,30 @@
#define USART_IRDA_VALID(ref) ((ref) == USART0)
#elif (USART_COUNT == 1) && defined(USART1)
#define USART_IRDA_VALID(ref) ((ref) == USART1)
+#elif defined(USARTRF0)
+#define USART_IRDA_VALID(ref) ((ref) == USARTRF0)
#else
#define USART_IRDA_VALID(ref) (0)
#endif
+#endif
#if defined(_SILICON_LABS_32B_SERIES_1)
- #define USART_I2S_VALID(ref) ((ref) == USART1)
+#if defined(USART4)
+#define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3) || ((ref) == USART4))
+#elif defined(USART3)
+#define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3))
+#else
+#define USART_I2S_VALID(ref) ((ref) == USART1)
+#endif
#elif defined(_SILICON_LABS_32B_SERIES_0)
- #if defined(_EZR32_HAPPY_FAMILY)
- #define USART_I2S_VALID(ref) ((ref) == USART0)
- #elif defined(_EFM32_HAPPY_FAMILY)
- #define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1))
- #elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY)
- #define USART_I2S_VALID(ref) ((ref) == USART1)
- #elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
- #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2))
+#if defined(_EZR32_HAPPY_FAMILY)
+#define USART_I2S_VALID(ref) ((ref) == USART0)
+#elif defined(_EFM32_HAPPY_FAMILY)
+#define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1))
+#elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY)
+#define USART_I2S_VALID(ref) ((ref) == USART1)
+#elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
+#define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2))
#endif
#endif
@@ -132,9 +152,14 @@
#define UART_REF_VALID(ref) (0)
#endif
+#if defined(_USART_CLKDIV_DIVEXT_MASK)
+#define CLKDIV_MASK (_USART_CLKDIV_DIV_MASK | _USART_CLKDIV_DIVEXT_MASK)
+#else
+#define CLKDIV_MASK _USART_CLKDIV_DIV_MASK
+#endif
+
/** @endcond */
-
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
@@ -201,14 +226,12 @@
*/
/* HFPERCLK used to clock all USART/UART peripheral modules */
- if (!refFreq)
- {
+ if (!refFreq) {
refFreq = CMU_ClockFreqGet(cmuClock_HFPER);
}
/* Map oversampling */
- switch (ovs)
- {
+ switch (ovs) {
case usartOVS16:
EFM_ASSERT(baudrate <= (refFreq / 16));
oversample = 16;
@@ -236,34 +259,33 @@
}
/* Calculate and set CLKDIV with fractional bits.
- * The addend (oversample*baudrate)/2 in the first line is to round the
- * divisor up by half the divisor before the division in order to reduce the
- * integer division error, which consequently results in a higher baudrate
- * than desired. */
-#if defined(_USART_CLKDIV_DIV_MASK) && (_USART_CLKDIV_DIV_MASK >= 0x7FFFF8UL)
+ * The added (oversample*baudrate)/2 in the first line is to round the
+ * divisor to the nearest fractional divisor. */
+#if defined(_SILICON_LABS_32B_SERIES_0) && !defined(_EFM32_HAPPY_FAMILY)
+ /* Devices with 2 fractional bits. CLKDIV[7:6] */
+ clkdiv = 4 * refFreq + (oversample * baudrate) / 2;
+ clkdiv /= (oversample * baudrate);
+ clkdiv -= 4;
+ clkdiv *= 64;
+#else
+ /* Devices with 5 fractional bits. CLKDIV[7:3] */
clkdiv = 32 * refFreq + (oversample * baudrate) / 2;
clkdiv /= (oversample * baudrate);
clkdiv -= 32;
clkdiv *= 8;
-#else
- clkdiv = 4 * refFreq + (oversample * baudrate) / 2;
- clkdiv /= (oversample * baudrate);
- clkdiv -= 4;
- clkdiv *= 64;
#endif
/* Verify that resulting clock divider is within limits */
- EFM_ASSERT(clkdiv <= _USART_CLKDIV_DIV_MASK);
+ EFM_ASSERT(clkdiv <= CLKDIV_MASK);
- /* If EFM_ASSERT is not enabled, make sure we don't write to reserved bits */
- clkdiv &= _USART_CLKDIV_DIV_MASK;
+ /* Make sure we don't write to reserved bits */
+ clkdiv &= CLKDIV_MASK;
usart->CTRL &= ~_USART_CTRL_OVS_MASK;
usart->CTRL |= ovs;
usart->CLKDIV = clkdiv;
}
-
/***************************************************************************//**
* @brief
* Calculate baudrate for USART/UART given reference frequency, clock division
@@ -305,17 +327,16 @@
uint32_t br;
/* Out of bound clkdiv ? */
- EFM_ASSERT(clkdiv <= _USART_CLKDIV_DIV_MASK);
+ EFM_ASSERT(clkdiv <= CLKDIV_MASK);
/* Mask out unused bits */
- clkdiv &= _USART_CLKDIV_DIV_MASK;
+ clkdiv &= CLKDIV_MASK;
/* We want to use integer division to avoid forcing in float division */
/* utils, and yet keep rounding effect errors to a minimum. */
/* Baudrate calculation depends on if synchronous or asynchronous mode */
- if (syncmode)
- {
+ if (syncmode) {
/*
* Baudrate is given by:
*
@@ -327,9 +348,7 @@
*/
oversample = 1; /* Not used in sync mode, ie 1 */
factor = 128;
- }
- else
- {
+ } else {
/*
* Baudrate in asynchronous mode is given by:
*
@@ -343,8 +362,7 @@
* (part of) oversample part of the divisor.
*/
- switch (ovs)
- {
+ switch (ovs) {
case usartOVS16:
oversample = 1;
factor = 256 / 16;
@@ -413,7 +431,6 @@
return br;
}
-
/***************************************************************************//**
* @brief
* Get current baudrate for USART/UART.
@@ -434,12 +451,9 @@
USART_OVS_TypeDef ovs;
bool syncmode;
- if (usart->CTRL & USART_CTRL_SYNC)
- {
+ if (usart->CTRL & USART_CTRL_SYNC) {
syncmode = true;
- }
- else
- {
+ } else {
syncmode = false;
}
@@ -449,7 +463,6 @@
return USART_BaudrateCalc(freq, usart->CLKDIV, syncmode, ovs);
}
-
/***************************************************************************//**
* @brief
* Configure USART operating in synchronous mode to use a given baudrate
@@ -491,8 +504,7 @@
*/
/* HFPERCLK used to clock all USART/UART peripheral modules */
- if (!refFreq)
- {
+ if (!refFreq) {
refFreq = CMU_ClockFreqGet(cmuClock_HFPER);
}
@@ -500,15 +512,11 @@
clkdiv = clkdiv << 8;
/* Verify that resulting clock divider is within limits */
- EFM_ASSERT(!(clkdiv & ~_USART_CLKDIV_DIV_MASK));
+ EFM_ASSERT(!(clkdiv & ~CLKDIV_MASK));
- /* If EFM_ASSERT is not enabled, make sure we don't write to reserved bits */
- clkdiv &= _USART_CLKDIV_DIV_MASK;
-
- BUS_RegMaskedWrite(&usart->CLKDIV, _USART_CLKDIV_DIV_MASK, clkdiv);
+ usart->CLKDIV = clkdiv;
}
-
/***************************************************************************//**
* @brief
* Enable/disable USART/UART receiver and/or transmitter.
@@ -529,9 +537,9 @@
uint32_t tmp;
/* Make sure the module exists on the selected chip */
- EFM_ASSERT( USART_REF_VALID(usart)
- || USARTRF_REF_VALID(usart)
- || UART_REF_VALID(usart) );
+ EFM_ASSERT(USART_REF_VALID(usart)
+ || USARTRF_REF_VALID(usart)
+ || UART_REF_VALID(usart) );
/* Disable as specified */
tmp = ~((uint32_t) (enable));
@@ -542,7 +550,6 @@
usart->CMD = (uint32_t) (enable);
}
-
/***************************************************************************//**
* @brief
* Init USART/UART for normal asynchronous mode.
@@ -569,23 +576,21 @@
void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init)
{
/* Make sure the module exists on the selected chip */
- EFM_ASSERT( USART_REF_VALID(usart)
- || USARTRF_REF_VALID(usart)
- || UART_REF_VALID(usart) );
+ EFM_ASSERT(USART_REF_VALID(usart)
+ || USARTRF_REF_VALID(usart)
+ || UART_REF_VALID(usart) );
/* Init USART registers to HW reset state. */
USART_Reset(usart);
#if defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
/* Disable majority vote if specified. */
- if (init->mvdis)
- {
+ if (init->mvdis) {
usart->CTRL |= USART_CTRL_MVDIS;
}
/* Configure PRS input mode. */
- if (init->prsRxEnable)
- {
+ if (init->prsRxEnable) {
usart->INPUT = (uint32_t) init->prsRxCh | USART_INPUT_RXPRS;
}
#endif
@@ -603,16 +608,20 @@
& _USART_TIMING_CSHOLD_MASK)
| ((init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT)
& _USART_TIMING_CSSETUP_MASK);
- if (init->autoCsEnable)
- {
+ if (init->autoCsEnable) {
usart->CTRL |= USART_CTRL_AUTOCS;
}
#endif
+
+#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK)
+ usart->ROUTEPEN &= ~(_USART_ROUTEPEN_RTSPEN_MASK | _USART_ROUTEPEN_CTSPEN_MASK);
+ usart->ROUTEPEN |= init->hwFlowControl;
+#endif
+
/* Finally enable (as specified) */
usart->CMD = (uint32_t)init->enable;
}
-
/***************************************************************************//**
* @brief
* Init USART for synchronous mode.
@@ -640,7 +649,7 @@
void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init)
{
/* Make sure the module exists on the selected chip */
- EFM_ASSERT( USART_REF_VALID(usart) || USARTRF_REF_VALID(usart) );
+ EFM_ASSERT(USART_REF_VALID(usart) || USARTRF_REF_VALID(usart) );
/* Init USART registers to HW reset state. */
USART_Reset(usart);
@@ -656,8 +665,7 @@
#if defined(_USART_INPUT_RXPRS_MASK)
/* Configure PRS input mode. */
- if (init->prsRxEnable)
- {
+ if (init->prsRxEnable) {
usart->INPUT = (uint32_t)init->prsRxCh | USART_INPUT_RXPRS;
}
#endif
@@ -671,8 +679,7 @@
USART_BaudrateSyncSet(usart, init->refFreq, init->baudrate);
/* Finally enable (as specified) */
- if (init->master)
- {
+ if (init->master) {
usart->CMD = USART_CMD_MASTEREN;
}
@@ -681,8 +688,7 @@
& _USART_TIMING_CSHOLD_MASK)
| ((init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT)
& _USART_TIMING_CSSETUP_MASK);
- if (init->autoCsEnable)
- {
+ if (init->autoCsEnable) {
usart->CTRL |= USART_CTRL_AUTOCS;
}
#endif
@@ -729,8 +735,7 @@
usart->CTRL |= USART_CTRL_TXINV;
/* Invert Rx signal before demodulator if enabled */
- if (init->irRxInv)
- {
+ if (init->irRxInv) {
usart->CTRL |= USART_CTRL_RXINV;
}
@@ -796,14 +801,12 @@
| (init->mono ? USART_I2SCTRL_MONO : 0)
| USART_I2SCTRL_EN;
- if (enable != usartDisable)
- {
+ if (enable != usartDisable) {
USART_Enable(usart, enable);
}
}
#endif
-
/***************************************************************************//**
* @brief
* Initialize automatic transmissions using PRS channel as trigger
@@ -826,17 +829,14 @@
| _USART_TRIGCTRL_TSEL_MASK);
#if defined(USART_TRIGCTRL_AUTOTXTEN)
- if (init->autoTxTriggerEnable)
- {
+ if (init->autoTxTriggerEnable) {
trigctrl |= USART_TRIGCTRL_AUTOTXTEN;
}
#endif
- if (init->txTriggerEnable)
- {
+ if (init->txTriggerEnable) {
trigctrl |= USART_TRIGCTRL_TXTEN;
}
- if (init->rxTriggerEnable)
- {
+ if (init->rxTriggerEnable) {
trigctrl |= USART_TRIGCTRL_RXTEN;
}
trigctrl |= init->prsTriggerChannel;
@@ -845,7 +845,6 @@
usart->TRIGCTRL = trigctrl;
}
-
/***************************************************************************//**
* @brief
* Reset USART/UART to same state as after a HW reset.
@@ -856,9 +855,9 @@
void USART_Reset(USART_TypeDef *usart)
{
/* Make sure the module exists on the selected chip */
- EFM_ASSERT( USART_REF_VALID(usart)
- || USARTRF_REF_VALID(usart)
- || UART_REF_VALID(usart) );
+ EFM_ASSERT(USART_REF_VALID(usart)
+ || USARTRF_REF_VALID(usart)
+ || UART_REF_VALID(usart) );
/* Make sure disabled first, before resetting other registers */
usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS
@@ -878,8 +877,7 @@
usart->ROUTE = _USART_ROUTE_RESETVALUE;
#endif
- if (USART_IRDA_VALID(usart))
- {
+ if (USART_IRDA_VALID(usart)) {
usart->IRCTRL = _USART_IRCTRL_RESETVALUE;
}
@@ -888,14 +886,12 @@
#endif
#if defined(_USART_I2SCTRL_RESETVALUE)
- if (USART_I2S_VALID(usart))
- {
+ if (USART_I2S_VALID(usart)) {
usart->I2SCTRL = _USART_I2SCTRL_RESETVALUE;
}
#endif
}
-
/***************************************************************************//**
* @brief
* Receive one 4-8 bit frame, (or part of 10-16 bit frame).
@@ -928,7 +924,6 @@
return (uint8_t)usart->RXDATA;
}
-
/***************************************************************************//**
* @brief
* Receive two 4-8 bit frames, or one 10-16 bit frame.
@@ -961,7 +956,6 @@
return (uint16_t)usart->RXDOUBLE;
}
-
/***************************************************************************//**
* @brief
* Receive two 4-9 bit frames, or one 10-16 bit frame with extended
@@ -994,7 +988,6 @@
return usart->RXDOUBLEX;
}
-
/***************************************************************************//**
* @brief
* Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended
@@ -1027,7 +1020,6 @@
return (uint16_t)usart->RXDATAX;
}
-
/***************************************************************************//**
* @brief
* Perform one 8 bit frame SPI transfer.
@@ -1057,7 +1049,6 @@
return (uint8_t)usart->RXDATA;
}
-
/***************************************************************************//**
* @brief
* Transmit one 4-9 bit frame.
@@ -1089,7 +1080,6 @@
usart->TXDATA = (uint32_t)data;
}
-
/***************************************************************************//**
* @brief
* Transmit two 4-9 bit frames, or one 10-16 bit frame.
@@ -1125,7 +1115,6 @@
usart->TXDOUBLE = (uint32_t)data;
}
-
/***************************************************************************//**
* @brief
* Transmit two 4-9 bit frames, or one 10-16 bit frame with extended control.
@@ -1161,7 +1150,6 @@
usart->TXDOUBLEX = data;
}
-
/***************************************************************************//**
* @brief
* Transmit one 4-9 bit frame with extended control.
@@ -1189,7 +1177,6 @@
usart->TXDATAX = (uint32_t)data;
}
-
/** @} (end addtogroup USART) */
/** @} (end addtogroup emlib) */
#endif /* defined(USART_COUNT) && (USART_COUNT > 0) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_vcmp.c
* @brief Voltage Comparator (VCMP) peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -64,12 +64,9 @@
EFM_ASSERT((vcmpInit->biasProg >= 0) && (vcmpInit->biasProg < 16));
/* Configure Half Bias setting */
- if (vcmpInit->halfBias)
- {
+ if (vcmpInit->halfBias) {
VCMP->CTRL |= VCMP_CTRL_HALFBIAS;
- }
- else
- {
+ } else {
VCMP->CTRL &= ~(VCMP_CTRL_HALFBIAS);
}
@@ -78,22 +75,16 @@
VCMP->CTRL |= (vcmpInit->biasProg << _VCMP_CTRL_BIASPROG_SHIFT);
/* Configure sense for falling edge */
- if (vcmpInit->irqFalling)
- {
+ if (vcmpInit->irqFalling) {
VCMP->CTRL |= VCMP_CTRL_IFALL;
- }
- else
- {
+ } else {
VCMP->CTRL &= ~(VCMP_CTRL_IFALL);
}
/* Configure sense for rising edge */
- if (vcmpInit->irqRising)
- {
+ if (vcmpInit->irqRising) {
VCMP->CTRL |= VCMP_CTRL_IRISE;
- }
- else
- {
+ } else {
VCMP->CTRL &= ~(VCMP_CTRL_IRISE);
}
@@ -102,8 +93,7 @@
VCMP->CTRL |= (vcmpInit->warmup << _VCMP_CTRL_WARMTIME_SHIFT);
/* Configure hysteresis */
- switch (vcmpInit->hyst)
- {
+ switch (vcmpInit->hyst) {
case vcmpHyst20mV:
VCMP->CTRL |= VCMP_CTRL_HYSTEN;
break;
@@ -121,22 +111,18 @@
VCMP_TriggerSet(vcmpInit->triggerLevel);
/* Enable or disable VCMP */
- if (vcmpInit->enable)
- {
+ if (vcmpInit->enable) {
VCMP->CTRL |= VCMP_CTRL_EN;
- }
- else
- {
+ } else {
VCMP->CTRL &= ~(VCMP_CTRL_EN);
}
/* If Low Power Reference is enabled, wait until VCMP is ready */
/* before enabling it, see reference manual for deatils */
/* Configuring Low Power Ref without enable has no effect */
- if(vcmpInit->lowPowerRef && vcmpInit->enable)
- {
+ if (vcmpInit->lowPowerRef && vcmpInit->enable) {
/* Poll for VCMP ready */
- while(!VCMP_Ready());
+ while (!VCMP_Ready()) ;
VCMP_LowPowerRefSet(vcmpInit->lowPowerRef);
}
@@ -144,7 +130,6 @@
VCMP_IntClear(VCMP_IF_EDGE);
}
-
/***************************************************************************//**
* @brief
* Enable or disable Low Power Reference setting
@@ -154,17 +139,13 @@
******************************************************************************/
void VCMP_LowPowerRefSet(bool enable)
{
- if (enable)
- {
+ if (enable) {
VCMP->INPUTSEL |= VCMP_INPUTSEL_LPREF;
- }
- else
- {
+ } else {
VCMP->INPUTSEL &= ~VCMP_INPUTSEL_LPREF;
}
}
-
/***************************************************************************//**
* @brief
* Configure trigger level of voltage comparator
@@ -182,7 +163,6 @@
| (level << _VCMP_INPUTSEL_TRIGLEVEL_SHIFT);
}
-
/** @} (end addtogroup VCMP) */
/** @} (end addtogroup emlib) */
#endif /* defined(VCMP_COUNT) && (VCMP_COUNT > 0) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vdac.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vdac.c Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
/***************************************************************************//**
* @file em_vdac.c
* @brief Digital to Analog Converter (VDAC) Peripheral API
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -83,28 +83,19 @@
EFM_ASSERT(VDAC_REF_VALID(vdac));
EFM_ASSERT(VDAC_CH_VALID(ch));
- if (ch == 0)
- {
- if (enable)
- {
+ if (ch == 0) {
+ if (enable) {
vdac->CMD = VDAC_CMD_CH0EN;
- }
- else
- {
+ } else {
vdac->CMD = VDAC_CMD_CH0DIS;
- while (vdac->STATUS & VDAC_STATUS_CH0ENS);
+ while (vdac->STATUS & VDAC_STATUS_CH0ENS) ;
}
- }
- else
- {
- if (enable)
- {
+ } else {
+ if (enable) {
vdac->CMD = VDAC_CMD_CH1EN;
- }
- else
- {
+ } else {
vdac->CMD = VDAC_CMD_CH1DIS;
- while (vdac->STATUS & VDAC_STATUS_CH1ENS);
+ while (vdac->STATUS & VDAC_STATUS_CH1ENS) ;
}
}
}
@@ -138,25 +129,21 @@
/* Make sure both channels are disabled. */
vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS;
- while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS));
+ while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)) ;
/* Get OFFSETTRIM calibration value. */
cal = ((DEVINFO->VDAC0CH1CAL & _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK)
>> _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT)
<< _VDAC_CAL_OFFSETTRIM_SHIFT;
- if (init->mainCalibration)
- {
+ if (init->mainCalibration) {
calData = &DEVINFO->VDAC0MAINCAL;
- }
- else
- {
+ } else {
calData = &DEVINFO->VDAC0ALTCAL;
}
/* Get correct GAINERRTRIM calibration value. */
- switch (init->reference)
- {
+ switch (init->reference) {
case vdacRef1V25Ln:
tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK)
>> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT;
@@ -188,8 +175,7 @@
cal |= tmp << _VDAC_CAL_GAINERRTRIM_SHIFT;
/* Get GAINERRTRIMCH1 calibration value. */
- switch (init->reference)
- {
+ switch (init->reference) {
case vdacRef1V25Ln:
case vdacRef1V25:
case vdacRefAvdd:
@@ -249,48 +235,36 @@
/* Make sure both channels are disabled. */
vdacStatus = vdac->STATUS;
vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS;
- while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS));
+ while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)) ;
vdacChCtrl = ((uint32_t)init->prsSel << _VDAC_CH0CTRL_PRSSEL_SHIFT)
| ((uint32_t)init->prsAsync << _VDAC_CH0CTRL_PRSASYNC_SHIFT)
| ((uint32_t)init->trigMode << _VDAC_CH0CTRL_TRIGMODE_SHIFT)
| ((uint32_t)init->sampleOffMode << _VDAC_CH0CTRL_CONVMODE_SHIFT);
- if (ch == 0)
- {
+ if (ch == 0) {
vdac->CH0CTRL = vdacChCtrl;
- }
- else
- {
+ } else {
vdac->CH1CTRL = vdacChCtrl;
}
/* Check if the channel must be enabled. */
- if (init->enable)
- {
- if (ch == 0)
- {
+ if (init->enable) {
+ if (ch == 0) {
vdac->CMD = VDAC_CMD_CH0EN;
- }
- else
- {
+ } else {
vdac->CMD = VDAC_CMD_CH1EN;
}
}
/* Check if the other channel had to be turned off above
* and needs to be turned on again. */
- if (ch == 0)
- {
- if (vdacStatus & VDAC_STATUS_CH1ENS)
- {
+ if (ch == 0) {
+ if (vdacStatus & VDAC_STATUS_CH1ENS) {
vdac->CMD = VDAC_CMD_CH1EN;
}
- }
- else
- {
- if (vdacStatus & VDAC_STATUS_CH0ENS)
- {
+ } else {
+ if (vdacStatus & VDAC_STATUS_CH0ENS) {
vdac->CMD = VDAC_CMD_CH0EN;
}
}
@@ -317,8 +291,7 @@
unsigned int channel,
uint32_t value)
{
- switch(channel)
- {
+ switch (channel) {
case 0:
VDAC_Channel0OutputSet(vdac, value);
break;
@@ -368,23 +341,16 @@
uint32_t ret, refFreq;
/* Make sure selected VDAC clock is below max value */
- if (vdacFreq > VDAC_MAX_CLOCK)
- {
+ if (vdacFreq > VDAC_MAX_CLOCK) {
vdacFreq = VDAC_MAX_CLOCK;
}
- if (!syncMode)
- {
+ if (!syncMode) {
refFreq = VDAC_INTERNAL_CLOCK_FREQ;
- }
- else
- {
- if (hfperFreq)
- {
+ } else {
+ if (hfperFreq) {
refFreq = hfperFreq;
- }
- else
- {
+ } else {
refFreq = CMU_ClockFreqGet(cmuClock_HFPER);
}
}
@@ -392,18 +358,15 @@
/* Iterate in order to determine best prescale value. Start with lowest */
/* prescaler value in order to get the first equal or less VDAC */
/* frequency value. */
- for (ret = 0; ret <= _VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT; ret++)
- {
- if ((refFreq / (ret + 1)) <= vdacFreq)
- {
+ for (ret = 0; ret <= _VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT; ret++) {
+ if ((refFreq / (ret + 1)) <= vdacFreq) {
break;
}
}
/* If ret is higher than the max prescaler value, make sure to return
the max value. */
- if (ret > (_VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT))
- {
+ if (ret > (_VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT)) {
ret = _VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT;
}
@@ -421,7 +384,7 @@
{
/* Disable channels, before resetting other registers. */
vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS;
- while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS));
+ while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)) ;
vdac->CH0CTRL = _VDAC_CH0CTRL_RESETVALUE;
vdac->CH1CTRL = _VDAC_CH1CTRL_RESETVALUE;
vdac->CH0DATA = _VDAC_CH0DATA_RESETVALUE;
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c Thu Dec 07 14:01:42 2017 +0000
@@ -2,9 +2,9 @@
* @file em_wdog.c
* @brief Watchdog (WDOG) peripheral API
* devices.
- * @version 5.1.2
+ * @version 5.3.3
*******************************************************************************
- * @section License
+ * # License
* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
*******************************************************************************
*
@@ -75,16 +75,13 @@
void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable)
{
/* SYNCBUSY may stall when locked. */
- if (wdog->CTRL & WDOG_CTRL_LOCK)
- {
+ if (wdog->CTRL & WDOG_CTRL_LOCK) {
return;
}
- if (!enable)
- {
+ if (!enable) {
/* If the user intends to disable and the WDOG is enabled */
- if (BUS_RegBitRead(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT))
- {
+ if (BUS_RegBitRead(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT)) {
/* Wait for any pending previous write operation to have been completed in */
/* low frequency domain */
while (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
@@ -92,14 +89,11 @@
BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT, 0);
}
- }
- else
- {
+ } else {
BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT, 1);
}
}
-
/***************************************************************************//**
* @brief
* Feed the watchdog.
@@ -108,15 +102,14 @@
* When the watchdog is activated, it must be fed (ie clearing the counter)
* before it reaches the defined timeout period. Otherwise, the watchdog
* will generate a reset.
- *
+ *
* @param[in] wdog
* Pointer to WDOG peripheral register block.
******************************************************************************/
void WDOGn_Feed(WDOG_TypeDef *wdog)
{
/* The watchdog should not be fed while it is disabled */
- if (!(wdog->CTRL & WDOG_CTRL_EN))
- {
+ if (!(wdog->CTRL & WDOG_CTRL_EN)) {
return;
}
@@ -124,8 +117,7 @@
/* is no point in waiting for it to complete before clearing over again. */
/* This avoids stalling the core in the typical use case where some idle loop */
/* keeps clearing the watchdog. */
- if (wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD)
- {
+ if (wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) {
return;
}
/* Before writing to the WDOG_CMD register we also need to make sure that
@@ -136,7 +128,6 @@
wdog->CMD = WDOG_CMD_CLEAR;
}
-
/***************************************************************************//**
* @brief
* Initialize watchdog (assuming the watchdog configuration has not been
@@ -159,53 +150,43 @@
{
uint32_t setting;
- if (init->enable)
- {
+ if (init->enable) {
setting = WDOG_CTRL_EN;
- }
- else
- {
+ } else {
setting = 0;
}
- if (init->debugRun)
- {
+ if (init->debugRun) {
setting |= WDOG_CTRL_DEBUGRUN;
}
- if (init->em2Run)
- {
+ if (init->em2Run) {
setting |= WDOG_CTRL_EM2RUN;
}
- if (init->em3Run)
- {
+ if (init->em3Run) {
setting |= WDOG_CTRL_EM3RUN;
}
- if (init->em4Block)
- {
+ if (init->em4Block) {
setting |= WDOG_CTRL_EM4BLOCK;
}
- if (init->swoscBlock)
- {
+ if (init->swoscBlock) {
setting |= WDOG_CTRL_SWOSCBLOCK;
}
- if (init->lock)
- {
+ if (init->lock) {
setting |= WDOG_CTRL_LOCK;
}
-#if defined( _WDOG_CTRL_WDOGRSTDIS_MASK )
- if (init->resetDisable)
- {
+#if defined(_WDOG_CTRL_WDOGRSTDIS_MASK)
+ if (init->resetDisable) {
setting |= WDOG_CTRL_WDOGRSTDIS;
}
#endif
setting |= ((uint32_t)(init->clkSel) << _WDOG_CTRL_CLKSEL_SHIFT)
-#if defined( _WDOG_CTRL_WARNSEL_MASK )
+#if defined(_WDOG_CTRL_WARNSEL_MASK)
| ((uint32_t)(init->warnSel) << _WDOG_CTRL_WARNSEL_SHIFT)
#endif
-#if defined( _WDOG_CTRL_WINSEL_MASK )
+#if defined(_WDOG_CTRL_WINSEL_MASK)
| ((uint32_t)(init->winSel) << _WDOG_CTRL_WINSEL_SHIFT)
#endif
| ((uint32_t)(init->perSel) << _WDOG_CTRL_PERSEL_SHIFT);
@@ -218,7 +199,6 @@
wdog->CTRL = setting;
}
-
/***************************************************************************//**
* @brief
* Lock the watchdog configuration.
@@ -251,7 +231,6 @@
BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_LOCK_SHIFT, 1);
}
-
/** @} (end addtogroup WDOG) */
/** @} (end addtogroup emlib) */
#endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/flash_api.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/flash_api.c Thu Dec 07 14:01:42 2017 +0000
@@ -93,10 +93,17 @@
(void)obj;
(void)address;
+#if FLASH_BASE > 0
if (address < FLASH_BASE || address >= FLASH_BASE + FLASH_SIZE) {
// Address outside of flash -- invalid sector
return MBED_FLASH_INVALID_SIZE;
}
+#else
+ if (address >= FLASH_BASE + FLASH_SIZE) {
+ // Address outside of flash -- invalid sector
+ return MBED_FLASH_INVALID_SIZE;
+ }
+#endif
return FLASH_PAGE_SIZE;
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c Thu Nov 23 11:57:25 2017 +0000 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c Thu Dec 07 14:01:42 2017 +0000 @@ -29,7 +29,6 @@ #include "pinmap.h" #include "em_gpio.h" -#include "em_int.h" #include "em_cmu.h" #include "sleep_api.h" #include "sleepmodes.h"
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c Thu Dec 07 14:01:42 2017 +0000
@@ -99,11 +99,11 @@
I2CName i2c_sda = (I2CName) pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName) pinmap_peripheral(scl, PinMap_I2C_SCL);
obj->i2c.i2c = (I2C_TypeDef*) pinmap_merge(i2c_sda, i2c_scl);
- MBED_ASSERT(((int) obj->i2c.i2c) != NC);
-
+ MBED_ASSERT(((unsigned int) obj->i2c.i2c) != NC);
+
/* You need both SDA and SCL for I2C, so configuring one of them to NC is illegal */
- MBED_ASSERT((uint32_t)sda != (uint32_t)NC);
- MBED_ASSERT((uint32_t)scl != (uint32_t)NC);
+ MBED_ASSERT((unsigned int)sda != NC);
+ MBED_ASSERT((unsigned int)scl != NC);
/* Enable clock for the peripheral */
CMU_ClockEnable(i2c_get_clock(obj), true);
@@ -116,9 +116,9 @@
/* Enable pins at correct location */
#ifdef I2C_ROUTE_SDAPEN
/* Find common location in pinmap */
- int loc_sda = pin_location(sda, PinMap_I2C_SDA);
- int loc_scl = pin_location(scl, PinMap_I2C_SCL);
- int loc = pinmap_merge(loc_sda, loc_scl);
+ unsigned int loc_sda = pin_location(sda, PinMap_I2C_SDA);
+ unsigned int loc_scl = pin_location(scl, PinMap_I2C_SCL);
+ unsigned int loc = pinmap_merge(loc_sda, loc_scl);
MBED_ASSERT(loc != NC);
/* Set location */
obj->i2c.location = I2C_ROUTE_SDAPEN | I2C_ROUTE_SCLPEN | (loc << _I2C_ROUTE_LOCATION_SHIFT);
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c Thu Dec 07 14:01:42 2017 +0000
@@ -214,7 +214,7 @@
if(pwmout_all_inactive()) {
PWM_TIMER->ROUTE |= pinmap_find_function(pin,PinMap_PWM) << _TIMER_ROUTE_LOCATION_SHIFT;
} else {
- MBED_ASSERT(PWM_TIMER->ROUTE & _TIMER_ROUTE_LOCATION_MASK == pinmap_find_function(pin,PinMap_PWM) << _TIMER_ROUTE_LOCATION_SHIFT);
+ MBED_ASSERT((PWM_TIMER->ROUTE & _TIMER_ROUTE_LOCATION_MASK) == pinmap_find_function(pin,PinMap_PWM) << _TIMER_ROUTE_LOCATION_SHIFT);
}
#endif
@@ -230,14 +230,14 @@
} else {
//This channel was disabled already
}
-
+
pwmout_enable_pins(obj, false);
-
+
if(pwmout_all_inactive()) {
//Stop timer
PWM_TIMER->CMD = TIMER_CMD_STOP;
while(PWM_TIMER->STATUS & TIMER_STATUS_RUNNING);
-
+
//Disable clock
CMU_ClockEnable(PWM_TIMER_CLOCK, false);
}
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c Thu Dec 07 14:01:42 2017 +0000
@@ -78,7 +78,7 @@
/* Interrupt handler from mbed common */
static uart_irq_handler irq_handler;
/* Keep track of incoming DMA IRQ's */
-static bool serial_dma_irq_fired[DMACTRL_CH_CNT] = { false };
+static bool serial_dma_irq_fired[DMA_CHAN_COUNT] = { false };
/* Serial interface on USBTX/USBRX retargets stdio */
int stdio_uart_inited = 0;
@@ -120,6 +120,18 @@
static void usart2_rx_irq() { uart_irq(USART_2, RxIrq); }
static void usart2_tx_irq() { uart_irq(USART_2, TxIrq); USART_IntClear((USART_TypeDef*)USART_2, USART_IFC_TXC);}
#endif
+#ifdef USART3
+static void usart3_rx_irq() { uart_irq(USART_3, RxIrq); }
+static void usart3_tx_irq() { uart_irq(USART_3, TxIrq); USART_IntClear((USART_TypeDef*)USART_3, USART_IFC_TXC);}
+#endif
+#ifdef USART4
+static void usart4_rx_irq() { uart_irq(USART_4, RxIrq); }
+static void usart4_tx_irq() { uart_irq(USART_4, TxIrq); USART_IntClear((USART_TypeDef*)USART_4, USART_IFC_TXC);}
+#endif
+#ifdef USART5
+static void usart5_rx_irq() { uart_irq(USART_5, RxIrq); }
+static void usart5_tx_irq() { uart_irq(USART_5, TxIrq); USART_IntClear((USART_TypeDef*)USART_5, USART_IFC_TXC);}
+#endif
#ifdef LEUART0
static void leuart0_irq()
{
@@ -250,6 +262,18 @@
if (serial_ptr == USART_2) return index;
index++;
#endif
+#ifdef USART3
+ if (serial_ptr == USART_3) return index;
+ index++;
+#endif
+#ifdef USART4
+ if (serial_ptr == USART_4) return index;
+ index++;
+#endif
+#ifdef USART5
+ if (serial_ptr == USART_5) return index;
+ index++;
+#endif
#ifdef LEUART0
if (serial_ptr == LEUART_0) return index;
index++;
@@ -301,6 +325,18 @@
case USART_2:
return USART2_RX_IRQn;
#endif
+#ifdef USART3
+ case USART_3:
+ return USART3_RX_IRQn;
+#endif
+#ifdef USART4
+ case USART_4:
+ return USART4_RX_IRQn;
+#endif
+#ifdef USART5
+ case USART_5:
+ return USART5_RX_IRQn;
+#endif
#ifdef LEUART0
case LEUART_0:
return LEUART0_IRQn;
@@ -344,6 +380,18 @@
case USART_2:
return USART2_TX_IRQn;
#endif
+#ifdef USART3
+ case USART_3:
+ return USART3_TX_IRQn;
+#endif
+#ifdef USART4
+ case USART_4:
+ return USART4_TX_IRQn;
+#endif
+#ifdef USART5
+ case USART_5:
+ return USART5_TX_IRQn;
+#endif
#ifdef LEUART0
case LEUART_0:
return LEUART0_IRQn;
@@ -387,6 +435,18 @@
case USART_2:
return cmuClock_USART2;
#endif
+#ifdef USART3
+ case USART_3:
+ return cmuClock_USART3;
+#endif
+#ifdef USART4
+ case USART_4:
+ return cmuClock_USART4;
+#endif
+#ifdef USART5
+ case USART_5:
+ return cmuClock_USART5;
+#endif
#ifdef LEUART0
case LEUART_0:
return cmuClock_LEUART0;
@@ -407,7 +467,7 @@
UARTName uart_rx = (UARTName) pinmap_peripheral(rx, PinMap_UART_RX);
/* Check that pins are connected to same UART */
UARTName uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
- MBED_ASSERT((int) uart != NC);
+ MBED_ASSERT((unsigned int) uart != NC);
obj->serial.periph.uart = (USART_TypeDef *) uart;
@@ -418,7 +478,7 @@
#if defined(_SILICON_LABS_32B_PLATFORM_1)
/* Check that pins are used by same location for the given UART */
obj->serial.location = pinmap_merge(uart_tx_loc, uart_rx_loc);
- MBED_ASSERT(obj->serial.location != (uint32_t)NC);
+ MBED_ASSERT(obj->serial.location != NC);
#else
obj->serial.location_tx = uart_tx_loc;
obj->serial.location_rx = uart_rx_loc;
@@ -466,6 +526,27 @@
NVIC_SetPriority(USART2_TX_IRQn, 1);
break;
#endif
+#ifdef USART3
+ case USART_3:
+ NVIC_SetVector(USART3_RX_IRQn, (uint32_t) &usart3_rx_irq);
+ NVIC_SetVector(USART3_TX_IRQn, (uint32_t) &usart3_tx_irq);
+ NVIC_SetPriority(USART3_TX_IRQn, 1);
+ break;
+#endif
+#ifdef USART4
+ case USART_4:
+ NVIC_SetVector(USART4_RX_IRQn, (uint32_t) &usart4_rx_irq);
+ NVIC_SetVector(USART4_TX_IRQn, (uint32_t) &usart4_tx_irq);
+ NVIC_SetPriority(USART4_TX_IRQn, 1);
+ break;
+#endif
+#ifdef USART5
+ case USART_5:
+ NVIC_SetVector(USART5_RX_IRQn, (uint32_t) &usart5_rx_irq);
+ NVIC_SetVector(USART5_TX_IRQn, (uint32_t) &usart5_tx_irq);
+ NVIC_SetPriority(USART5_TX_IRQn, 1);
+ break;
+#endif
#ifdef LEUART0
case LEUART_0:
NVIC_SetVector(LEUART0_IRQn, (uint32_t) &leuart0_irq);
@@ -507,12 +588,12 @@
if(LEUART_REF_VALID(obj->serial.periph.leuart)) {
#ifdef _LEUART_ROUTE_LOCATION_SHIFT
obj->serial.periph.leuart->ROUTE = (obj->serial.location << _LEUART_ROUTE_LOCATION_SHIFT);
- if(obj->serial.tx_pin != (uint32_t)NC) {
+ if(obj->serial.tx_pin != NC) {
obj->serial.periph.leuart->ROUTE |= LEUART_ROUTE_TXPEN;
} else {
obj->serial.periph.leuart->ROUTE &= ~LEUART_ROUTE_TXPEN;
}
- if(obj->serial.rx_pin != (uint32_t)NC) {
+ if(obj->serial.rx_pin != NC) {
obj->serial.periph.leuart->ROUTE |= LEUART_ROUTE_RXPEN;
} else {
obj->serial.periph.leuart->CMD = LEUART_CMD_RXBLOCKEN;
@@ -536,12 +617,12 @@
} else {
#ifdef _USART_ROUTE_LOCATION_SHIFT
obj->serial.periph.uart->ROUTE = (obj->serial.location << _LEUART_ROUTE_LOCATION_SHIFT);
- if(obj->serial.tx_pin != (uint32_t)NC) {
+ if(obj->serial.tx_pin != NC) {
obj->serial.periph.uart->ROUTE |= USART_ROUTE_TXPEN;
} else {
obj->serial.periph.uart->ROUTE &= ~USART_ROUTE_TXPEN;
}
- if(obj->serial.rx_pin != (uint32_t)NC) {
+ if(obj->serial.rx_pin != NC) {
obj->serial.periph.uart->ROUTE |= USART_ROUTE_RXPEN;
} else {
obj->serial.periph.uart->CMD = USART_CMD_RXBLOCKEN;
@@ -1174,6 +1255,21 @@
channelConfig.select = DMAREQ_USART2_TXBL;
break;
#endif
+#ifdef USART3
+ case USART_3:
+ channelConfig.select = DMAREQ_USART3_TXBL;
+ break;
+#endif
+#ifdef USART4
+ case USART_4:
+ channelConfig.select = DMAREQ_USART4_TXBL;
+ break;
+#endif
+#ifdef USART5
+ case USART_5:
+ channelConfig.select = DMAREQ_USART5_TXBL;
+ break;
+#endif
#ifdef LEUART0
case LEUART_0:
channelConfig.select = DMAREQ_LEUART0_TXBL;
@@ -1219,6 +1315,21 @@
channelConfig.select = DMAREQ_USART2_RXDATAV;
break;
#endif
+#ifdef USART3
+ case USART_3:
+ channelConfig.select = DMAREQ_USART3_RXDATAV;
+ break;
+#endif
+#ifdef USART4
+ case USART_4:
+ channelConfig.select = DMAREQ_USART4_RXDATAV;
+ break;
+#endif
+#ifdef USART5
+ case USART_5:
+ channelConfig.select = DMAREQ_USART5_RXDATAV;
+ break;
+#endif
#ifdef LEUART0
case LEUART_0:
channelConfig.select = DMAREQ_LEUART0_RXDATAV;
@@ -1453,6 +1564,34 @@
obj->serial.periph.uart->CMD = USART_CMD_RXEN | USART_CMD_CLEARRX;
break;
#endif
+#ifdef USART2
+ case USART_2:
+ dma_periph = ldmaPeripheralSignal_USART2_RXDATAV;
+ source_addr = &USART2->RXDATA;
+ obj->serial.periph.uart->CMD = USART_CMD_RXEN | USART_CMD_CLEARRX;
+ break;
+#endif
+#ifdef USART3
+ case USART_3:
+ dma_periph = ldmaPeripheralSignal_USART3_RXDATAV;
+ source_addr = &USART3->RXDATA;
+ obj->serial.periph.uart->CMD = USART_CMD_RXEN | USART_CMD_CLEARRX;
+ break;
+#endif
+#ifdef USART4
+ case USART_4:
+ dma_periph = ldmaPeripheralSignal_USART4_RXDATAV;
+ source_addr = &USART4->RXDATA;
+ obj->serial.periph.uart->CMD = USART_CMD_RXEN | USART_CMD_CLEARRX;
+ break;
+#endif
+#ifdef USART5
+ case USART_5:
+ dma_periph = ldmaPeripheralSignal_USART5_RXDATAV;
+ source_addr = &USART5->RXDATA;
+ obj->serial.periph.uart->CMD = USART_CMD_RXEN | USART_CMD_CLEARRX;
+ break;
+#endif
#ifdef LEUART0
case LEUART_0:
dma_periph = ldmaPeripheralSignal_LEUART0_RXDATAV;
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c Thu Dec 07 14:01:42 2017 +0000
@@ -60,6 +60,18 @@
case SPI_2:
return cmuClock_USART2;
#endif
+#ifdef USART3
+ case SPI_3:
+ return cmuClock_USART3;
+#endif
+#ifdef USART4
+ case SPI_4:
+ return cmuClock_USART4;
+#endif
+#ifdef USART5
+ case SPI_5:
+ return cmuClock_USART5;
+#endif
default:
error("Spi module not available.. Out of bound access.");
return cmuClock_HFPER;
@@ -85,6 +97,21 @@
index = 2;
break;
#endif
+#ifdef USART3
+ case SPI_3:
+ index = 3;
+ break;
+#endif
+#ifdef USART4
+ case SPI_4:
+ index = 4;
+ break;
+#endif
+#ifdef USART5
+ case SPI_5:
+ index = 5;
+ break;
+#endif
default:
error("Spi module not available.. Out of bound access.");
break;
@@ -123,7 +150,7 @@
SPIName spi_ctrl = (SPIName) pinmap_merge(spi_clk, spi_cs);
obj->spi.spi = (USART_TypeDef *) pinmap_merge(spi_data, spi_ctrl);
- MBED_ASSERT((int) obj->spi.spi != NC);
+ MBED_ASSERT((unsigned int) obj->spi.spi != NC);
if (cs != NC) { /* Slave mode */
obj->spi.master = false;
@@ -287,6 +314,21 @@
IRQvector = USART2_RX_IRQn;
break;
#endif
+#ifdef USART3
+ case USART_3:
+ IRQvector = USART3_RX_IRQn;
+ break;
+#endif
+#ifdef USART4
+ case USART_4:
+ IRQvector = USART4_RX_IRQn;
+ break;
+#endif
+#ifdef USART5
+ case USART_5:
+ IRQvector = USART5_RX_IRQn;
+ break;
+#endif
default:
error("Undefined SPI peripheral");
return;
@@ -771,6 +813,24 @@
txChnlCfg.select = DMAREQ_USART2_TXEMPTY;
break;
#endif
+#ifdef USART3
+ case SPI_3:
+ rxChnlCfg.select = DMAREQ_USART3_RXDATAV;
+ txChnlCfg.select = DMAREQ_USART3_TXEMPTY;
+ break;
+#endif
+#ifdef USART4
+ case SPI_4:
+ rxChnlCfg.select = DMAREQ_USART4_RXDATAV;
+ txChnlCfg.select = DMAREQ_USART4_TXEMPTY;
+ break;
+#endif
+#ifdef USART5
+ case SPI_5:
+ rxChnlCfg.select = DMAREQ_USART5_RXDATAV;
+ txChnlCfg.select = DMAREQ_USART5_TXEMPTY;
+ break;
+#endif
default:
error("Spi module not available.. Out of bound access.");
break;
@@ -799,12 +859,36 @@
/* Select RX source address. 9 bit frame length requires to use extended register.
10 bit and larger frame requires to use RXDOUBLE register. */
switch((int)obj->spi.spi) {
+#ifdef USART0
case USART_0:
dma_periph = ldmaPeripheralSignal_USART0_RXDATAV;
break;
+#endif
+#ifdef USART1
case USART_1:
dma_periph = ldmaPeripheralSignal_USART1_RXDATAV;
break;
+#endif
+#ifdef USART2
+ case USART_2:
+ dma_periph = ldmaPeripheralSignal_USART2_RXDATAV;
+ break;
+#endif
+#ifdef USART3
+ case USART_3:
+ dma_periph = ldmaPeripheralSignal_USART3_RXDATAV;
+ break;
+#endif
+#ifdef USART4
+ case USART_4:
+ dma_periph = ldmaPeripheralSignal_USART4_RXDATAV;
+ break;
+#endif
+#ifdef USART5
+ case USART_5:
+ dma_periph = ldmaPeripheralSignal_USART5_RXDATAV;
+ break;
+#endif
default:
EFM_ASSERT(0);
while(1);
@@ -1222,7 +1306,7 @@
rx_pointer = ((uint16_t *)obj->rx_buff.buffer) + obj->rx_buff.pos;
} else {
rx_pointer = ((uint8_t *)obj->rx_buff.buffer) + obj->rx_buff.pos;
- }
+ }
}
uint32_t rx_length = obj->rx_buff.length - obj->rx_buff.pos;
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c Thu Dec 07 14:01:42 2017 +0000
@@ -38,21 +38,27 @@
* the upper 16 bits are implemented in software.
*/
-static uint8_t us_ticker_inited = 0; // Is ticker initialized yet
+static uint8_t us_ticker_inited = 0; // Is ticker initialized yet
-static volatile uint32_t ticker_cnt = 0; //Internal overflow count, used to extend internal 16-bit counter to (MHz * 32-bit)
-static volatile uint32_t ticker_int_cnt = 0; //Amount of overflows until user interrupt
-static volatile uint8_t ticker_freq_mhz = 0; //Frequency of timer in MHz
-static volatile uint32_t ticker_top_us = 0; //Amount of us corresponding to the top value of the timer
+static volatile uint32_t ticker_cnt = 0; // Internal overflow count, used to extend internal 16-bit counter to (MHz * 32-bit)
+static volatile uint32_t ticker_int_cnt = 0; // Amount of overflows until user interrupt
+static volatile uint32_t ticker_freq_khz = 0; // Frequency of timer in MHz
+static volatile uint32_t ticker_top_ms = 0; // Amount of ms corresponding to the top value of the timer
+static volatile uint32_t soft_timer_top = 0; // When to wrap the software counter
void us_ticker_irq_handler_internal(void)
{
- /* Handle timer overflow */
- if (TIMER_IntGet(US_TICKER_TIMER) & TIMER_IF_OF) {
- ticker_cnt++;
- if(ticker_cnt >= ((uint32_t)ticker_freq_mhz << 16)) ticker_cnt = 0;
- TIMER_IntClear(US_TICKER_TIMER, TIMER_IF_OF);
- }
+ /* Handle timer overflow */
+ if (TIMER_IntGet(US_TICKER_TIMER) & TIMER_IF_OF) {
+ ticker_cnt++;
+
+ /* Wrap ticker_cnt when we've gone over 32-bit us value */
+ if (ticker_cnt >= soft_timer_top) {
+ ticker_cnt = 0;
+ }
+
+ TIMER_IntClear(US_TICKER_TIMER, TIMER_IF_OF);
+ }
/* Check for user interrupt expiration */
if (TIMER_IntGet(US_TICKER_TIMER) & TIMER_IF_CC0) {
@@ -78,28 +84,28 @@
/* Clear TIMER counter value */
TIMER_CounterSet(US_TICKER_TIMER, 0);
- /* Get frequency of clock in MHz for scaling ticks to microseconds */
- ticker_freq_mhz = (REFERENCE_FREQUENCY / 1000000);
- MBED_ASSERT(ticker_freq_mhz > 0);
+ /* Get frequency of clock in kHz for scaling ticks to microseconds */
+ ticker_freq_khz = (REFERENCE_FREQUENCY / 1000);
+ MBED_ASSERT(ticker_freq_khz > 0);
/*
- * Calculate maximum prescaler that gives at least 1 MHz frequency, while keeping clock as an integer multiple of 1 MHz.
- * Example: 14 MHz => prescaler = 1 (i.e. DIV2), ticker_freq_mhz = 7;
- * 24 MHz => prescaler = 3 (i.e. DIV8), ticker_freq_mhz = 3;
- * 48 MHz => prescaler = 4 (i.e. DIV16), ticker_freq_mhz = 3;
+ * Calculate maximum prescaler that gives at least 1 MHz frequency, giving us 1us resolution.
* Limit prescaling to maximum prescaler value, which is 10 (DIV1024).
*/
uint32_t prescaler = 0;
- while((ticker_freq_mhz & 1) == 0 && prescaler <= 10) {
- ticker_freq_mhz = ticker_freq_mhz >> 1;
+ while((ticker_freq_khz >= 2000) && prescaler <= 10) {
+ ticker_freq_khz = ticker_freq_khz >> 1;
prescaler++;
}
/* Set prescaler */
US_TICKER_TIMER->CTRL = (US_TICKER_TIMER->CTRL & ~_TIMER_CTRL_PRESC_MASK) | (prescaler << _TIMER_CTRL_PRESC_SHIFT);
- /* calculate top value */
- ticker_top_us = (uint32_t) 0x10000 / ticker_freq_mhz;
+ /* calculate top value.*/
+ ticker_top_ms = (uint32_t) 0x10000 / ticker_freq_khz;
+
+ /* calculate software timer overflow */
+ soft_timer_top = ((0xFFFFFFFFUL / 1000UL) / ticker_top_ms) + 1;
/* Select Compare Channel parameters */
TIMER_InitCC_TypeDef timerCCInit = TIMER_INITCC_DEFAULT;
@@ -114,7 +120,7 @@
NVIC_EnableIRQ(US_TICKER_TIMER_IRQ);
/* Set top value */
- TIMER_TopSet(US_TICKER_TIMER, (ticker_top_us * ticker_freq_mhz) - 1);
+ TIMER_TopSet(US_TICKER_TIMER, (ticker_top_ms * ticker_freq_khz) - 1);
/* Start TIMER */
TIMER_Enable(US_TICKER_TIMER, true);
@@ -123,7 +129,7 @@
uint32_t us_ticker_read()
{
uint32_t countH_old, countH;
- uint16_t countL;
+ uint32_t countL;
if (!us_ticker_inited) {
us_ticker_init();
@@ -145,12 +151,12 @@
/* Timer count value needs to be div'ed by the frequency to get to 1MHz ticks.
* For the software-extended part, the amount of us in one overflow is constant.
*/
- return (countL / ticker_freq_mhz) + (countH * ticker_top_us);
+ return ((countL * 1000UL) / ticker_freq_khz) + (countH * ticker_top_ms * 1000);
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- uint64_t goal = timestamp;
+ uint32_t goal = timestamp;
uint32_t trigger;
if((US_TICKER_TIMER->IEN & TIMER_IEN_CC0) == 0) {
@@ -160,51 +166,41 @@
TIMER_IntDisable(US_TICKER_TIMER, TIMER_IEN_CC0);
/* convert us delta value back to timer ticks */
- goal -= us_ticker_read();
+ trigger = us_ticker_read();
+ if (trigger < goal) {
+ goal -= trigger;
+ } else {
+ goal = (0xFFFFFFFFUL - (trigger - goal));
+ }
trigger = US_TICKER_TIMER->CNT;
/* Catch "Going back in time" */
- if(goal < (50 / (REFERENCE_FREQUENCY / 1000000)) ||
+ if(goal < 10 ||
goal >= 0xFFFFFF00UL) {
TIMER_IntClear(US_TICKER_TIMER, TIMER_IFC_CC0);
- TIMER_CompareSet(US_TICKER_TIMER, 0, (US_TICKER_TIMER->CNT + 3 > US_TICKER_TIMER->TOP ? 3 : US_TICKER_TIMER->CNT + 3));
+ TIMER_CompareSet(US_TICKER_TIMER, 0, (US_TICKER_TIMER->CNT + 3 >= US_TICKER_TIMER->TOP ? 3 : US_TICKER_TIMER->CNT + 3));
TIMER_IntEnable(US_TICKER_TIMER, TIMER_IEN_CC0);
return;
}
- /* Cap at 32 bit */
- goal &= 0xFFFFFFFFUL;
- /* Convert to ticker timebase */
- goal *= ticker_freq_mhz;
+ uint32_t timer_top = TIMER_TopGet(US_TICKER_TIMER);
+ uint32_t top_us = 1000 * ticker_top_ms;
+
+ /* Amount of times we expect to overflow: us offset / us period of timer */
+ ticker_int_cnt = goal / top_us;
- /* Note: we should actually populate the following fields by the division and remainder
- * of goal / ticks_per_overflow, but since we're keeping the frequency as low
- * as possible, and ticks_per_overflow as close to FFFF as possible, we can
- * get away with ditching the division here and saving cycles.
- *
- * "exact" implementation:
- * ticker_int_cnt = goal / TIMER_TopGet(US_TICKER_TIMER);
- * ticker_int_rem = goal % TIMER_TopGet(US_TICKER_TIMER);
- */
- ticker_int_cnt = (goal >> 16) & 0xFFFFFFFF;
+ /* Leftover microseconds need to be converted to timer timebase */
+ trigger += (((goal % top_us) * ticker_freq_khz) / 1000);
+
+ /* Cap compare value to timer top */
+ if (trigger >= timer_top) {
+ trigger -= timer_top;
+ }
/* Set compare channel 0 to (current position + lower 16 bits of target).
* When lower 16 bits match, run complete cycles with ticker_int_rem as trigger value
* for ticker_int_cnt times. */
- TIMER_IntClear(US_TICKER_TIMER, TIMER_IFC_CC0);
-
- /* Take top of timer into account so that we don't end up missing a cycle */
- /* Set trigger point by adding delta to current time */
- if((goal & 0xFFFF) >= TIMER_TopGet(US_TICKER_TIMER)) {
- trigger += (goal & 0xFFFF) - TIMER_TopGet(US_TICKER_TIMER);
- ticker_int_cnt++;
- } else {
- trigger += (goal & 0xFFFF);
- }
-
- if(trigger >= TIMER_TopGet(US_TICKER_TIMER)) {
- trigger -= TIMER_TopGet(US_TICKER_TIMER);
- }
+ TIMER_IntClear(US_TICKER_TIMER, TIMER_IEN_CC0);
TIMER_CompareSet(US_TICKER_TIMER, 0, trigger);
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/LICENSE Thu Nov 23 11:57:25 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2 +0,0 @@ -Unless specifically indicated otherwise in a file, files are licensed -under the Apache 2.0 license, as can be found in: apache-2.0.txt \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/Silabs_License_Agreement.txt Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,113 @@
+END-USER LICENSE AGREEMENT
+IMPORTANT: READ CAREFULLY
+BEFORE AGREEING TO TERMS
+
+THIS PRODUCT CONTAINS CERTAIN COMPUTER PROGRAMS AND OTHER THIRD PARTY
+PROPRIETARY MATERIAL ("LICENSED PRODUCT"), THE USE OF WHICH IS SUBJECT TO THIS
+END-USER LICENSE AGREEMENT. INDICATING YOUR AGREEMENT CONSTITUTES YOUR AND
+(IF APPLICABLE) YOUR COMPANY'S ASSENT TO AND ACCEPTANCE OF THIS END-USER LICENSE
+AGREEMENT (THE "LICENSE" OR "AGREEMENT"). IF YOU DO NOT AGREE WITH ALL OF THE
+TERMS, YOU MUST NOT USE THIS PRODUCT. WRITTEN APPROVAL IS NOT A PREREQUISITE TO
+THE VALIDITY OR ENFORCEABILITY OF THIS AGREEMENT, AND NO SOLICITATION OF SUCH
+WRITTEN APPROVAL BY OR ON BEHALF OF SILICON LABORATORIES, INC. ("SILICON LABS")
+SHALL BE CONSTRUED AS AN INFERENCE TO THE CONTRARY. IF THESE TERMS ARE
+CONSIDERED AN OFFER BY SILICON LABS, ACCEPTANCE IS EXPRESSLY LIMITED TO THESE
+TERMS.
+
+LICENSE AND WARRANTY: The Licensed Product and the embedded Software which is
+made the subject of this License is either the property of SILICON LABS or a
+third party from whom SILICON LABS has the authorization to distribute to you
+subject to the terms of this Agreement. This Licensed Product is protected by
+state, federal, and international copyright law. Although SILICON LABS continues
+to own the Licensed Product and the right to distribute the embedded third party
+Software, you will have certain rights to use the Licensed Product and the
+embedded Software after your acceptance of this License. Except as may be
+modified by a license addendum which accompanies this License, your rights and
+obligations with respect to the use of this Product and the embedded software
+are as follows:
+
+1. AS APPROPRIATE WITH RESPECT TO THE LICENSED PRODUCT, YOU MAY: Use, copy,
+ distribute and make derivative works of the Software for any purpose,
+ including commercial applications, subject to the following restrictions:
+ (i) The origin of this software must not be misrepresented; (ii) you must
+ not claim that you wrote the original software; (iii) altered source
+ versions must be plainly marked as such, and must not be misrepresented as
+ being the original software; and (iv) any notices contained in the Software
+ may not be removed or altered, including notices in source code versions.
+
+2. YOU MAY NOT: (A) Sublicense, assign, rent or lease any portion of the
+ Licensed Product or the embedded Software; or (B) Remove any product
+ identification, copyright or other notices that appear on the Licensed
+ Product or embedded Software.
+
+3. Limited Use: Use of any of the Software is strictly limited to use in
+ systems containing one or more SILICON LABS products when the Software is
+ enabled to be functional. Any unauthorized use is expressly prohibited and
+ will constitute a breach of this Agreement.
+
+4. Warranty: SILICON LABS does not warrant that the Licensed Product or
+ embedded Software will meet your requirements or that operation of the
+ Licensed Product will be uninterrupted or that the embedded Software will be
+ error-free. You agree that the Licensed Product is provided "AS IS" and
+ that SILICON LABS makes no warranty as to the Licensed Product or embedded
+ Software. SILICON LABS DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
+ INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT, RELATED TO THE
+ SOFTWARE, ITS USE OR ANY INABILITY TO USE IT, THE RESULTS OF ITS USE AND
+ THIS AGREEMENT.
+
+ YOU MAY HAVE OTHER RIGHTS, WHICH VARY FROM STATE TO STATE.
+
+5. Disclaimer of Damages: IN NO EVENT WILL SILICON LABS BE LIABLE TO YOU FOR
+ ANY SPECIAL, CONSEQUENTIAL, INDIRECT, OR SIMILAR DAMAGES, INCLUDING ANY LOST
+ PROFITS OR LOST DATA ARISING OUT OF THE USE OR INABILITY TO USE THE LICENSED
+ PRODUCT EVEN IF SILICON LABS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+ DAMAGES.
+
+ SOME STATES DO NOT ALLOW THE LIMITATION OR EXCLUSION OF LIABILITY FOR
+ INCIDENTAL OR CONSEQUENTIAL DAMAGES. SO THE ABOVE LIMITATION OR EXCLUSION
+ MAY NOT APPLY TO YOU.
+
+ IN NO CASE SHALL SILICON LABS' LIABILITY EXCEED THE PURCHASE PRICE FOR THE
+ LICENSED PRODUCT. The disclaimers and limitations set forth above will
+ apply regardless of whether you accept the Licensed Software.
+
+6. Term and Termination: The term of this Agreement and the License granted
+ herein shall begin upon use of the Licensed Product and continue in
+ perpetuity unless you breach any of the obligations set out under this
+ Agreement. Upon your breach of this Agreement by you, the license granted
+ hereunder shall terminate immediately and you shall cease all use of the
+ Licensed Products and return same as well as any copies of the Licensed
+ Product and/or embedded Software to SILICON LABS immediately. Termination
+ of this License upon your breach is only one remedy available to SILICON
+ LABS. In addition to termination of this Agreement upon your breach,
+ SILICON LABS shall be entitled to seek any and all other available remedies,
+ at law or at equity, arising from your breach.
+
+7. Export: You shall comply with all applicable federal, provincial, state and
+ local laws, regulations and ordinances including but not limited to
+ applicable U.S. Export Administration Laws and Regulations. You shall not
+ export or re-export, or allow the export or re-export of the Licensed
+ Product, any component of the Licensed Product, or any copy of the embedded
+ Software in violation of any such restrictions, laws or regulations, or to
+ Cuba, Libya, North Korea, Iran, Iraq, or Rwanda or to any Group D:1 or E:2
+ country (or any national of such country) specified in the then current
+ Supplement No. 1 to Part 740, or, in violation of the embargo provisions in
+ Part 746, of the U.S. Export Administration Regulations (or any successor
+ regulations or supplement), except in compliance with and with all licenses
+ and approvals required under applicable export laws and regulations,
+ including without limitation, those of the U.S. Department of Commerce.
+
+8. General: This Agreement will be governed by the laws of the State of Texas
+ and any applicable federal laws or regulations. The waiver by either Party
+ of any default or breach of this Agreement shall not constitute a waiver of
+ any other or subsequent default or breach. This Agreement constitutes the
+ complete and exclusive statement of the mutual understanding between you and
+ SILICON LABS with respect to this subject matter herein. This Agreement may
+ only be modified by a written addendum, which has been signed by both you
+ and SILICON LABS. Should you have any questions concerning this Agreement,
+ or if you desire to contact SILICON LABS for any reason, please write:
+
+Silicon Laboratories, Inc.
+400 West Cesar Chavez
+Austin, Texas 78701, U.S.A.
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/apache-2.0.txt Thu Nov 23 11:57:25 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,56 +0,0 @@ - - -Apache License - -Version 2.0, January 2004 - -http://www.apache.org/licenses/ - -TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - -1. Definitions. - -"License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document. - -"Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License. - -"Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity. - -"You" (or "Your") shall mean an individual or Legal Entity exercising permissions granted by this License. - -"Source" form shall mean the preferred form for making modifications, including but not limited to software source code, documentation source, and configuration files. - -"Object" form shall mean any form resulting from mechanical transformation or translation of a Source form, including but not limited to compiled object code, generated documentation, and conversions to other media types. - -"Work" shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is included in or attached to the work (an example is provided in the Appendix below). - -"Derivative Works" shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof. - -"Contribution" shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to submit on behalf of the copyright owner. For the purposes of this definition, "submitted" means any form of electronic, verbal, or written communication sent to the Licensor or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue tracking systems that are managed by, or on behalf of, the Licensor for the purpose of discussing and improving the Work, but excluding communication that is conspicuously marked or otherwise designated in writing by the copyright owner as "Not a Contribution." - -"Contributor" shall mean Licensor and any individual or Legal Entity on behalf of whom a Contribution has been received by Licensor and subsequently incorporated within the Work. - -2. Grant of Copyright License. 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If You institute patent litigation against any entity (including a cross-claim or counterclaim in a lawsuit) alleging that the Work or a Contribution incorporated within the Work constitutes direct or contributory patent infringement, then any patent licenses granted to You under this License for that Work shall terminate as of the date such litigation is filed. - -4. Redistribution. You may reproduce and distribute copies of the Work or Derivative Works thereof in any medium, with or without modifications, and in Source or Object form, provided that You meet the following conditions: - - You must give any other recipients of the Work or Derivative Works a copy of this License; and - You must cause any modified files to carry prominent notices stating that You changed the files; and - You must retain, in the Source form of any Derivative Works that You distribute, all copyright, patent, trademark, and attribution notices from the Source form of the Work, excluding those notices that do not pertain to any part of the Derivative Works; and - If the Work includes a "NOTICE" text file as part of its distribution, then any Derivative Works that You distribute must include a readable copy of the attribution notices contained within such NOTICE file, excluding those notices that do not pertain to any part of the Derivative Works, in at least one of the following places: within a NOTICE text file distributed as part of the Derivative Works; within the Source form or documentation, if provided along with the Derivative Works; or, within a display generated by the Derivative Works, if and wherever such third-party notices normally appear. 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You are solely responsible for determining the appropriateness of using or redistributing the Work and assume any risks associated with Your exercise of permissions under this License. - -8. Limitation of Liability. In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages. - -9. Accepting Warranty or Additional Liability. While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. - -END OF TERMS AND CONDITIONS \ No newline at end of file
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/buffer-pool-memory-manager/buffer_pool_allocator.c Thu Nov 23 11:57:25 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,105 +0,0 @@
-/***************************************************************************//**
- * @file buffer_pool_allocator.c
- * @brief The source for a simple memory allocator that statically creates pools
- * of fixed size buffers to allocate from.
- * @copyright Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************/
-
-#include <stdlib.h>
-
-#include "buffer_pool_allocator.h"
-
-#include "em_core.h"
-
-#ifdef CONFIGURATION_HEADER
-#include CONFIGURATION_HEADER
-#endif
-
-// -----------------------------------------------------------------------------
-// Configuration Macros
-// -----------------------------------------------------------------------------
-
-#ifndef BUFFER_POOL_SIZE
-#define BUFFER_POOL_SIZE 8
-#endif
-#ifndef MAX_BUFFER_SIZE
-#define MAX_BUFFER_SIZE 160
-#endif
-
-#define INVALID_BUFFER_OBJ ((void*)0xFFFFFFFF)
-
-typedef struct {
- uint8_t refCount;
- uint8_t data[MAX_BUFFER_SIZE];
-} BufferPoolObj_t;
-
-static BufferPoolObj_t memoryObjs[BUFFER_POOL_SIZE];
-
-void* memoryAllocate(uint32_t size)
-{
- uint32_t i = 0;
- void *handle = INVALID_BUFFER_OBJ;
-
- // We can't support sizes greater than the maximum heap buffer size
- if(size > MAX_BUFFER_SIZE) {
- return INVALID_BUFFER_OBJ;
- }
-
- CORE_DECLARE_IRQ_STATE;
- CORE_ENTER_CRITICAL();
- for(i = 0; i < BUFFER_POOL_SIZE; i++)
- {
- if(memoryObjs[i].refCount == 0)
- {
- memoryObjs[i].refCount = 1;
- handle = (void*)i;
- break;
- }
- }
- CORE_EXIT_CRITICAL();
-
- return handle;
-}
-
-void *memoryPtrFromHandle(void *handle)
-{
- void *ptr = NULL;
-
- // Make sure we were given a valid handle
- if((handle == INVALID_BUFFER_OBJ) || ((uint32_t)handle > BUFFER_POOL_SIZE))
- {
- return NULL;
- }
-
- CORE_DECLARE_IRQ_STATE;
- CORE_ENTER_CRITICAL();
- if(memoryObjs[(uint32_t)handle].refCount > 0)
- {
- ptr = memoryObjs[(uint32_t)handle].data;
- }
- CORE_EXIT_CRITICAL();
-
- return ptr;
-}
-
-void memoryFree(void *handle)
-{
- CORE_DECLARE_IRQ_STATE;
- CORE_ENTER_CRITICAL();
- if(memoryPtrFromHandle(handle) != NULL)
- {
- memoryObjs[(uint32_t)handle].refCount--;
- }
- CORE_EXIT_CRITICAL();
-}
-
-void memoryTakeReference(void *handle)
-{
- CORE_DECLARE_IRQ_STATE;
- CORE_ENTER_CRITICAL();
- if(memoryPtrFromHandle(handle) != NULL)
- {
- memoryObjs[(uint32_t)handle].refCount++;
- }
- CORE_EXIT_CRITICAL();
-}
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/buffer-pool-memory-manager/buffer_pool_allocator.h Thu Nov 23 11:57:25 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,51 +0,0 @@ -/***************************************************************************//** - * @file buffer_pool_allocator.h - * @brief This is a simple memory allocator that uses a build time defined pool - * of constant sized buffers. It's a very simple allocator, but one that can - * be easily used in any application. - * - * @copyright Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com - ******************************************************************************/ - -#ifndef BUFFER_POOL_ALLOCATOR_H__ -#define BUFFER_POOL_ALLOCATOR_H__ - -// Get the standard include types -#include <stdint.h> - -/** - * Allocate a buffer with at least the number of bytes specified. If there is - * not enough space then this function will return NULL. - * @param size The number of bytes to allocate for this buffer - * @return Returns a handle to a buffer at least size bytes long or NULL if no - * buffer could be allocated. - */ -void* memoryAllocate(uint32_t size); - -/** - * Free the buffer pointed to by handle. This will only decrement the reference - * counter for this buffer. The memory is not freed until the reference counter - * reaches zero. - * @param handle The handle to free. Must match the value returned by - * the memoryAllocate() function. - */ -void memoryFree(void *handle); - -/** - * Take a memory handle and get the data pointer associated with it. This will - * return NULL if passed an invalid or unallocated handle. - * @param handle The handle to get the pointer for. Must match the value - * returned by the memoryAllocate() function. - */ -void *memoryPtrFromHandle(void *handle); - -/** - * Increment the reference counter on the memory pointed to by handle. After - * doing this there will have to be an additional call to memoryFree() to - * release the memory. - * @param handle The handle to the object which needs its reference count - * increased. Must match the value returned by the memoryAllocate() function. - */ -void memoryTakeReference(void *handle); - -#endif // BUFFER_POOL_ALLOCATOR_H__
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/buffer-pool-memory-manager/rail_integration.c Thu Nov 23 11:57:25 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,35 +0,0 @@
-/***************************************************************************//**
- * @file rail_integration.c
- * @brief Simple code to link this memory manager with a RAIL application by
-* implementing the appropriate callbacks.
- * @copyright Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************/
-
-#include <stdint.h>
-#include "rail.h"
-#include "buffer_pool_allocator.h"
-
-/// Rely on the pool allocator's allocate function to get memory
-void *RAILCb_AllocateMemory(uint32_t size)
-{
- return memoryAllocate(size);
-}
-
-/// Use the pool allocator's free function to return the memory to the pool
-void RAILCb_FreeMemory(void *ptr)
-{
- memoryFree(ptr);
-}
-
-/// Get the memory pointer for this handle and offset into it as requested
-void *RAILCb_BeginWriteMemory(void *handle,
- uint32_t offset,
- uint32_t *available)
-{
- return ((uint8_t*)memoryPtrFromHandle(handle)) + offset;
-}
-
-/// We don't need to track the completion of a memory write so do nothing
-void RAILCb_EndWriteMemory(void *handle, uint32_t offset, uint32_t size)
-{
-}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TARGET_EFR32_1/ieee802154_subg_efr32xg1_configurator_out.c Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,155 @@
+/***************************************************************************//**
+ * @brief RAIL Configuration
+ * @copyright Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com
+ ******************************************************************************/
+//=============================================================================
+//
+// WARNING: Auto-Generated Radio Config - DO NOT EDIT
+//
+//=============================================================================
+#include <stdint.h>
+
+const uint32_t ieee802154_config_863[] = {
+0x01010FF4UL, 0x00000000UL,
+0x01010FF8UL, 0x0003C000UL,
+0x01010FFCUL, 0x0003C008UL,
+0x00010004UL, 0x00157001UL,
+0x00010008UL, 0x0000007FUL,
+0x00010018UL, 0x00000000UL,
+0x0001001CUL, 0x00000000UL,
+0x00010028UL, 0x00000000UL,
+0x0001002CUL, 0x00000000UL,
+0x00010030UL, 0x00000000UL,
+0x00010034UL, 0x00000000UL,
+0x0001003CUL, 0x00000000UL,
+0x00010040UL, 0x000007A0UL,
+0x00010048UL, 0x00000000UL,
+0x00010054UL, 0x00000000UL,
+0x00010058UL, 0x00000000UL,
+0x000100A0UL, 0x00004000UL,
+0x000100A4UL, 0x00004CFFUL,
+0x000100A8UL, 0x00004100UL,
+0x000100ACUL, 0x00004DFFUL,
+0x00012000UL, 0x00000704UL,
+0x00012010UL, 0x00000000UL,
+0x00012018UL, 0x00008408UL,
+0x00013008UL, 0x0000AC3FUL,
+0x0001302CUL, 0x021EB000UL,
+0x00013030UL, 0x00108000UL,
+0x00013034UL, 0x00000003UL,
+0x0001303CUL, 0x00014000UL,
+0x00013040UL, 0x00000000UL,
+0x000140A0UL, 0x0F00277AUL,
+0x000140F4UL, 0x00001020UL,
+0x00014134UL, 0x00000880UL,
+0x00014138UL, 0x000087F6UL,
+0x00014140UL, 0x00880048UL,
+0x00014144UL, 0x1153E6C0UL,
+0x00016014UL, 0x00000010UL,
+0x00016018UL, 0x04127920UL,
+0x0001601CUL, 0x0051C007UL,
+0x00016020UL, 0x000000C2UL,
+0x00016024UL, 0x00000000UL,
+0x00016028UL, 0x03000000UL,
+0x0001602CUL, 0x00000000UL,
+0x00016030UL, 0x00FF0BF4UL,
+0x00016034UL, 0x00000C20UL,
+0x00016038UL, 0x0102000AUL,
+0x0001603CUL, 0x00080430UL,
+0x00016040UL, 0x000000A7UL,
+0x00016044UL, 0x00000000UL,
+0x00016048UL, 0x04602123UL,
+0x0001604CUL, 0x0000A47CUL,
+0x00016050UL, 0x00000018UL,
+0x00016054UL, 0x00000000UL,
+0x00016058UL, 0x00000000UL,
+0x0001605CUL, 0x30100101UL,
+0x00016060UL, 0x7F7F7050UL,
+0x00016064UL, 0x00000000UL,
+0x00017014UL, 0x000270F1UL,
+0x00017018UL, 0x00001700UL,
+0x0001701CUL, 0x82840000UL,
+0x00017028UL, 0x00000000UL,
+0x00017048UL, 0x0000383EUL,
+0x0001704CUL, 0x000025BCUL,
+0x00017070UL, 0x00010103UL,
+0x00017074UL, 0x00000442UL,
+0x00017078UL, 0x006D8480UL,
+0xFFFFFFFFUL,
+};
+const uint32_t ieee802154_config_863_min[] = {
+0xFFFFFFFFUL,
+};
+
+const uint32_t ieee802154_config_915[] = {
+0x01010FF4UL, 0x00000000UL,
+0x01010FF8UL, 0x0003C000UL,
+0x01010FFCUL, 0x0003C008UL,
+0x00010004UL, 0x00157001UL,
+0x00010008UL, 0x0000007FUL,
+0x00010018UL, 0x00000000UL,
+0x0001001CUL, 0x00000000UL,
+0x00010028UL, 0x00000000UL,
+0x0001002CUL, 0x00000000UL,
+0x00010030UL, 0x00000000UL,
+0x00010034UL, 0x00000000UL,
+0x0001003CUL, 0x00000000UL,
+0x00010040UL, 0x000007A0UL,
+0x00010048UL, 0x00000000UL,
+0x00010054UL, 0x00000000UL,
+0x00010058UL, 0x00000000UL,
+0x000100A0UL, 0x00004000UL,
+0x000100A4UL, 0x00004CFFUL,
+0x000100A8UL, 0x00004100UL,
+0x000100ACUL, 0x00004DFFUL,
+0x00012000UL, 0x00000704UL,
+0x00012010UL, 0x00000000UL,
+0x00012018UL, 0x00008408UL,
+0x00013008UL, 0x0000AC3FUL,
+0x0001302CUL, 0x02364000UL,
+0x00013030UL, 0x00108000UL,
+0x00013034UL, 0x00000003UL,
+0x0001303CUL, 0x00014000UL,
+0x00013040UL, 0x00000000UL,
+0x000140A0UL, 0x0F00277AUL,
+0x000140F4UL, 0x00001020UL,
+0x00014134UL, 0x00000880UL,
+0x00014138UL, 0x000087F6UL,
+0x00014140UL, 0x00880048UL,
+0x00014144UL, 0x1153E6C0UL,
+0x00016014UL, 0x00000010UL,
+0x00016018UL, 0x04127920UL,
+0x0001601CUL, 0x0051C007UL,
+0x00016020UL, 0x000000C2UL,
+0x00016024UL, 0x00000000UL,
+0x00016028UL, 0x03000000UL,
+0x0001602CUL, 0x00000000UL,
+0x00016030UL, 0x00FF04C8UL,
+0x00016034UL, 0x000008A2UL,
+0x00016038UL, 0x0100000AUL,
+0x0001603CUL, 0x00080430UL,
+0x00016040UL, 0x000000A7UL,
+0x00016044UL, 0x00000000UL,
+0x00016048UL, 0x0AC02123UL,
+0x0001604CUL, 0x0000A47CUL,
+0x00016050UL, 0x00000018UL,
+0x00016054UL, 0x00000000UL,
+0x00016058UL, 0x00000000UL,
+0x0001605CUL, 0x30100101UL,
+0x00016060UL, 0x7F7F7050UL,
+0x00016064UL, 0x00000000UL,
+0x00017014UL, 0x000270F1UL,
+0x00017018UL, 0x00001700UL,
+0x0001701CUL, 0x82840000UL,
+0x00017028UL, 0x00000000UL,
+0x00017048UL, 0x0000383EUL,
+0x0001704CUL, 0x000025BCUL,
+0x00017070UL, 0x00010103UL,
+0x00017074UL, 0x00000442UL,
+0x00017078UL, 0x006D8480UL,
+0xFFFFFFFFUL,
+};
+const uint32_t ieee802154_config_915_min[] = {
+0xFFFFFFFFUL,
+};
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TARGET_EFR32_1/ieee802154_subg_efr32xg1_configurator_out.h Thu Dec 07 14:01:42 2017 +0000 @@ -0,0 +1,31 @@ + +/***************************************************************************//** + * @file ieee802154_gb868_efr32xg1_configurator_out.h + * @brief IEEE802154 GB868_Configuration + * @copyright Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************/ + +#ifndef __IEEE802154_GB868_EFR32XG1_CONFIGURATOR_OUT_H__ +#define __IEEE802154_GB868_EFR32XG1_CONFIGURATOR_OUT_H__ + +#include <stdint.h> + +#define IEEE802154_863_RADIO_CONFIG_BASE_FREQUENCY 868300000UL +#define IEEE802154_863_RADIO_CONFIG_XTAL_FREQUENCY 38400000UL +#define IEEE802154_863_RADIO_CONFIG_BITRATE "100kbps" +#define IEEE802154_863_RADIO_CONFIG_MODULATION_TYPE "OQPSK" +#define IEEE802154_863_RADIO_CONFIG_DEVIATION "333.3kHz" + +extern const uint32_t ieee802154_config_863[]; +extern const uint32_t ieee802154_config_863_min[]; + +#define IEEE802154_915_RADIO_CONFIG_BASE_FREQUENCY 906000000UL +#define IEEE802154_915_RADIO_CONFIG_XTAL_FREQUENCY 38400000UL +#define IEEE802154_915_RADIO_CONFIG_BITRATE "250kbps" +#define IEEE802154_915_RADIO_CONFIG_MODULATION_TYPE "OQPSK" +#define IEEE802154_915_RADIO_CONFIG_DEVIATION "333.3kHz" + +extern const uint32_t ieee802154_config_915[]; +extern const uint32_t ieee802154_config_915_min[]; + +#endif // __IEEE802154_GB868_EFR32XG1_CONFIGURATOR_OUT_H__
Binary file targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TARGET_EFR32_1/librail_efr32xg1_release.a has changed
Binary file targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TARGET_EFR32_12/librail_efr32xg12_release.a has changed
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/ieee802154_efr32xg1_configurator_out.h Thu Nov 23 11:57:25 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,18 +0,0 @@ - -/***************************************************************************//** - * @file ieee802154_config.h - * @brief IEEE802154 Configuration - * @copyright Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com - ******************************************************************************/ - -#ifndef __IEEE802154_EFR32XG1_CONFIGURATOR_OUT_H__ -#define __IEEE802154_EFR32XG1_CONFIGURATOR_OUT_H__ - -#include <stdint.h> - -extern const uint32_t ieee802154_config_base[]; -extern const uint32_t ieee802154_config_base_min[]; -extern const uint32_t ieee802154_config_2415MHz_min[]; -extern const uint32_t ieee802154_config_2420MHz_min[]; - -#endif // __IEEE802154_EFR32XG1_CONFIGURATOR_OUT_H__
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/ieee802154_subg_efr32xg1_configurator_out.c Thu Nov 23 11:57:25 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,155 +0,0 @@
-/***************************************************************************//**
- * @brief RAIL Configuration
- * @copyright Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************/
-//=============================================================================
-//
-// WARNING: Auto-Generated Radio Config - DO NOT EDIT
-//
-//=============================================================================
-#include <stdint.h>
-
-const uint32_t ieee802154_config_863[] = {
-0x01010FF4UL, 0x00000000UL,
-0x01010FF8UL, 0x0003C000UL,
-0x01010FFCUL, 0x0003C008UL,
-0x00010004UL, 0x00157001UL,
-0x00010008UL, 0x0000007FUL,
-0x00010018UL, 0x00000000UL,
-0x0001001CUL, 0x00000000UL,
-0x00010028UL, 0x00000000UL,
-0x0001002CUL, 0x00000000UL,
-0x00010030UL, 0x00000000UL,
-0x00010034UL, 0x00000000UL,
-0x0001003CUL, 0x00000000UL,
-0x00010040UL, 0x000007A0UL,
-0x00010048UL, 0x00000000UL,
-0x00010054UL, 0x00000000UL,
-0x00010058UL, 0x00000000UL,
-0x000100A0UL, 0x00004000UL,
-0x000100A4UL, 0x00004CFFUL,
-0x000100A8UL, 0x00004100UL,
-0x000100ACUL, 0x00004DFFUL,
-0x00012000UL, 0x00000704UL,
-0x00012010UL, 0x00000000UL,
-0x00012018UL, 0x00008408UL,
-0x00013008UL, 0x0000AC3FUL,
-0x0001302CUL, 0x021EB000UL,
-0x00013030UL, 0x00108000UL,
-0x00013034UL, 0x00000003UL,
-0x0001303CUL, 0x00014000UL,
-0x00013040UL, 0x00000000UL,
-0x000140A0UL, 0x0F00277AUL,
-0x000140F4UL, 0x00001020UL,
-0x00014134UL, 0x00000880UL,
-0x00014138UL, 0x000087F6UL,
-0x00014140UL, 0x00880048UL,
-0x00014144UL, 0x1153E6C0UL,
-0x00016014UL, 0x00000010UL,
-0x00016018UL, 0x04127920UL,
-0x0001601CUL, 0x0051C007UL,
-0x00016020UL, 0x000000C2UL,
-0x00016024UL, 0x00000000UL,
-0x00016028UL, 0x03000000UL,
-0x0001602CUL, 0x00000000UL,
-0x00016030UL, 0x00FF0BF4UL,
-0x00016034UL, 0x00000C20UL,
-0x00016038UL, 0x0102000AUL,
-0x0001603CUL, 0x00080430UL,
-0x00016040UL, 0x000000A7UL,
-0x00016044UL, 0x00000000UL,
-0x00016048UL, 0x04602123UL,
-0x0001604CUL, 0x0000A47CUL,
-0x00016050UL, 0x00000018UL,
-0x00016054UL, 0x00000000UL,
-0x00016058UL, 0x00000000UL,
-0x0001605CUL, 0x30100101UL,
-0x00016060UL, 0x7F7F7050UL,
-0x00016064UL, 0x00000000UL,
-0x00017014UL, 0x000270F1UL,
-0x00017018UL, 0x00001700UL,
-0x0001701CUL, 0x82840000UL,
-0x00017028UL, 0x00000000UL,
-0x00017048UL, 0x0000383EUL,
-0x0001704CUL, 0x000025BCUL,
-0x00017070UL, 0x00010103UL,
-0x00017074UL, 0x00000442UL,
-0x00017078UL, 0x006D8480UL,
-0xFFFFFFFFUL,
-};
-const uint32_t ieee802154_config_863_min[] = {
-0xFFFFFFFFUL,
-};
-
-const uint32_t ieee802154_config_915[] = {
-0x01010FF4UL, 0x00000000UL,
-0x01010FF8UL, 0x0003C000UL,
-0x01010FFCUL, 0x0003C008UL,
-0x00010004UL, 0x00157001UL,
-0x00010008UL, 0x0000007FUL,
-0x00010018UL, 0x00000000UL,
-0x0001001CUL, 0x00000000UL,
-0x00010028UL, 0x00000000UL,
-0x0001002CUL, 0x00000000UL,
-0x00010030UL, 0x00000000UL,
-0x00010034UL, 0x00000000UL,
-0x0001003CUL, 0x00000000UL,
-0x00010040UL, 0x000007A0UL,
-0x00010048UL, 0x00000000UL,
-0x00010054UL, 0x00000000UL,
-0x00010058UL, 0x00000000UL,
-0x000100A0UL, 0x00004000UL,
-0x000100A4UL, 0x00004CFFUL,
-0x000100A8UL, 0x00004100UL,
-0x000100ACUL, 0x00004DFFUL,
-0x00012000UL, 0x00000704UL,
-0x00012010UL, 0x00000000UL,
-0x00012018UL, 0x00008408UL,
-0x00013008UL, 0x0000AC3FUL,
-0x0001302CUL, 0x02364000UL,
-0x00013030UL, 0x00108000UL,
-0x00013034UL, 0x00000003UL,
-0x0001303CUL, 0x00014000UL,
-0x00013040UL, 0x00000000UL,
-0x000140A0UL, 0x0F00277AUL,
-0x000140F4UL, 0x00001020UL,
-0x00014134UL, 0x00000880UL,
-0x00014138UL, 0x000087F6UL,
-0x00014140UL, 0x00880048UL,
-0x00014144UL, 0x1153E6C0UL,
-0x00016014UL, 0x00000010UL,
-0x00016018UL, 0x04127920UL,
-0x0001601CUL, 0x0051C007UL,
-0x00016020UL, 0x000000C2UL,
-0x00016024UL, 0x00000000UL,
-0x00016028UL, 0x03000000UL,
-0x0001602CUL, 0x00000000UL,
-0x00016030UL, 0x00FF04C8UL,
-0x00016034UL, 0x000008A2UL,
-0x00016038UL, 0x0100000AUL,
-0x0001603CUL, 0x00080430UL,
-0x00016040UL, 0x000000A7UL,
-0x00016044UL, 0x00000000UL,
-0x00016048UL, 0x0AC02123UL,
-0x0001604CUL, 0x0000A47CUL,
-0x00016050UL, 0x00000018UL,
-0x00016054UL, 0x00000000UL,
-0x00016058UL, 0x00000000UL,
-0x0001605CUL, 0x30100101UL,
-0x00016060UL, 0x7F7F7050UL,
-0x00016064UL, 0x00000000UL,
-0x00017014UL, 0x000270F1UL,
-0x00017018UL, 0x00001700UL,
-0x0001701CUL, 0x82840000UL,
-0x00017028UL, 0x00000000UL,
-0x00017048UL, 0x0000383EUL,
-0x0001704CUL, 0x000025BCUL,
-0x00017070UL, 0x00010103UL,
-0x00017074UL, 0x00000442UL,
-0x00017078UL, 0x006D8480UL,
-0xFFFFFFFFUL,
-};
-const uint32_t ieee802154_config_915_min[] = {
-0xFFFFFFFFUL,
-};
-
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/ieee802154_subg_efr32xg1_configurator_out.h Thu Nov 23 11:57:25 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,31 +0,0 @@ - -/***************************************************************************//** - * @file ieee802154_gb868_efr32xg1_configurator_out.h - * @brief IEEE802154 GB868_Configuration - * @copyright Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com - ******************************************************************************/ - -#ifndef __IEEE802154_GB868_EFR32XG1_CONFIGURATOR_OUT_H__ -#define __IEEE802154_GB868_EFR32XG1_CONFIGURATOR_OUT_H__ - -#include <stdint.h> - -#define IEEE802154_863_RADIO_CONFIG_BASE_FREQUENCY 868300000UL -#define IEEE802154_863_RADIO_CONFIG_XTAL_FREQUENCY 38400000UL -#define IEEE802154_863_RADIO_CONFIG_BITRATE "100kbps" -#define IEEE802154_863_RADIO_CONFIG_MODULATION_TYPE "OQPSK" -#define IEEE802154_863_RADIO_CONFIG_DEVIATION "333.3kHz" - -extern const uint32_t ieee802154_config_863[]; -extern const uint32_t ieee802154_config_863_min[]; - -#define IEEE802154_915_RADIO_CONFIG_BASE_FREQUENCY 906000000UL -#define IEEE802154_915_RADIO_CONFIG_XTAL_FREQUENCY 38400000UL -#define IEEE802154_915_RADIO_CONFIG_BITRATE "250kbps" -#define IEEE802154_915_RADIO_CONFIG_MODULATION_TYPE "OQPSK" -#define IEEE802154_915_RADIO_CONFIG_DEVIATION "333.3kHz" - -extern const uint32_t ieee802154_config_915[]; -extern const uint32_t ieee802154_config_915_min[]; - -#endif // __IEEE802154_GB868_EFR32XG1_CONFIGURATOR_OUT_H__
Binary file targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/librail_efr32xg1_gcc_release.a has changed
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.h Thu Nov 23 11:57:25 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,18 +0,0 @@ - -/***************************************************************************//** - * @file ieee802154_config.h - * @brief IEEE802154 Configuration - * @copyright Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com - ******************************************************************************/ - -#ifndef __IEEE802154_EFR32XG12_CONFIGURATOR_OUT_H__ -#define __IEEE802154_EFR32XG12_CONFIGURATOR_OUT_H__ - -#include <stdint.h> - -extern const uint32_t ieee802154_config_base[]; -extern const uint32_t ieee802154_config_base_min[]; -extern const uint32_t ieee802154_config_2415MHz_min[]; -extern const uint32_t ieee802154_config_2420MHz_min[]; - -#endif // __IEEE802154_EFR32XG12_CONFIGURATOR_OUT_H__
Binary file targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/librail_efr32xg12_gcc_release.a has changed
Binary file targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG1/librail_efr32xg1_gcc_release.a has changed
Binary file targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG12/librail_efr32xg12_iar_release.a has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/ble/rail_ble.h Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,218 @@
+/***************************************************************************//**
+ * @file rail_ble.h
+ * @brief The BLE specific header file for the RAIL library.
+ * @copyright Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com
+ ******************************************************************************/
+
+#ifndef __RAIL_BLE_H__
+#define __RAIL_BLE_H__
+
+// Get the standard include types
+#include <stdint.h>
+#include <stdbool.h>
+
+// Get the RAIL specific structures and types
+#include "rail_types.h"
+
+/**
+ * @addtogroup BLE
+ * @ingroup Protocol_Specific
+ * Accelerator routines for Bluetooth Low Energy (BLE).
+ *
+ * The APIs in this module help take care of configuring the radio for BLE
+ * operation and provide some additional helper routines necessary for
+ * normal BLE send/receive that aren't available directly in RAIL. To initialize
+ * the radio you will still have to call RAIL_Init(). However
+ * RAIL_ConfigChannels(), and RAIL_ConfigRadio() will be taken care of for you.
+ *
+ * To implement a standard BLE link layer you will also need to handle tight
+ * turnaround times and send packets at specific instants. This can all be
+ * managed through general RAIL functions like RAIL_ScheduleTx(),
+ * RAIL_ScheduleRx(), and RAIL_SetStateTiming(). See the full RAIL API for more
+ * useful functions.
+ *
+ * A simple example of how to setup your application to be in BLE mode is shown
+ * below. Note that this will put the radio on the first advertising channel
+ * with the advertising Access Address. In any full featured BLE application you
+ * will need to use the RAIL_BLE_ConfigChannelRadioParams() function to change
+ * the sync word and other parameters as needed based on your connection.
+ *
+ * @code{.c}
+ *
+ * // Put the radio into receive on the first BLE advertising channel
+ * int bleAdvertiseEnable(void)
+ * {
+ * // Call the BLE initialization function to load the right radio config
+ * RAIL_BLE_Init();
+ *
+ * // Configure us for the first advertising channel (Physical: 0, Logical: 37)
+ * // The CRC init value and Access Address come from the BLE specification.
+ * RAIL_BLE_ConfigChannelRadioParams(0x555555, 0x8E89BED6, 37, false);
+ *
+ * // Start receiving on this channel (Physical: 0, Logical: 37)
+ * RAIL_StartRx(0);
+ * }
+ * @endcode
+ *
+ * @{
+ */
+
+/**
+ * @enum RAIL_BLE_Coding_t
+ * @brief The variant of the BLE Coded PHY
+ */
+RAIL_ENUM(RAIL_BLE_Coding_t) {
+ RAIL_BLE_Coding_125kbps = 0,
+ RAIL_BLE_Coding_125kbps_DSA = 1,
+ RAIL_BLE_Coding_500kbps = 2,
+ RAIL_BLE_Coding_500kbps_DSA = 3,
+};
+
+/**
+ * @struct RAIL_BLE_State_t
+ * @brief State structure for BLE.
+ *
+ * This structure must be allocated in application global read-write memory
+ * that persists for the duration of BLE usage. It cannot be allocated
+ * in read-only memory or on the call stack.
+ */
+typedef struct RAIL_BLE_State {
+ uint32_t crcInit; /**< The value used for CRC initialization. */
+ uint32_t accessAddress; /**< The access address used for the connection. */
+ uint16_t channel; /**< The logical channel used. */
+ bool disableWhitening; /**< Whether the whitening engine should be off. */
+} RAIL_BLE_State_t;
+
+/**
+ * Configure RAIL to run in BLE mode.
+ *
+ * @param[in] railHandle Handle for RAIL instance.
+ * This function will change your radio and channel configuration and other
+ * parameters to match what is needed for BLE. If you need to switch back to a
+ * default RAIL mode then you must call RAIL_BLE_Deinit() first. This function
+ * will configure the protocol output on PTI to \ref RAIL_PTI_PROTOCOL_BLE.
+ */
+void RAIL_BLE_Init(RAIL_Handle_t railHandle);
+
+/**
+ * Take RAIL out of BLE mode.
+ *
+ * @param[in] railHandle Handle for RAIL instance.
+ * This function will undo some of the configuration that happens when you call
+ * RAIL_BLE_Init(). After this you can safely run your normal radio
+ * initialization code to use a non-BLE configuration. This function will \b
+ * not change back your radio or channel configurations so you must do this by
+ * manually reinitializing. This also resets the protocol output on PTI to \ref
+ * RAIL_PTI_PROTOCOL_CUSTOM.
+ */
+void RAIL_BLE_Deinit(RAIL_Handle_t railHandle);
+
+/**
+ * Determine whether BLE mode is enabled or not.
+ *
+ * @param[in] railHandle Handle for RAIL instance.
+ * @return True if BLE mode is enabled and false otherwise.
+ * This function returns the current status of RAIL's BLE mode. It is enabled by
+ * a call to RAIL_BLE_Init() and disabled by a call to RAIL_BLE_Deinit().
+ */
+bool RAIL_BLE_IsEnabled(RAIL_Handle_t railHandle);
+
+/**
+ * Switch the Viterbi 1Mbps BLE PHY.
+ *
+ * @param[in] railHandle Handle for RAIL instance.
+ * @return Status code indicating success of the function call.
+ *
+ * You can use this function to switch back to the defualt BLE 1Mbps PHY if you
+ * have switched to the 2Mbps or another configuration. You may only call this
+ * function after initializing BLE and while the radio is idle.
+ */
+RAIL_Status_t RAIL_BLE_ConfigPhy1MbpsViterbi(RAIL_Handle_t railHandle);
+
+/**
+ * Switch the legacy non-Viterbi 1Mbps BLE PHY.
+ *
+ * @param[in] railHandle Handle for RAIL instance.
+ * @return Status code indicating success of the function call.
+ *
+ * You can use this function to switch back to the legacy BLE 1Mbps PHY if you
+ * have switched to the 2Mbps or another configuration. You may only call this
+ * function after initializing BLE and while the radio is idle.
+ */
+RAIL_Status_t RAIL_BLE_ConfigPhy1Mbps(RAIL_Handle_t railHandle);
+
+/**
+ * Switch the Viterbi 2Mbps BLE PHY.
+ *
+ * @param[in] railHandle Handle for RAIL instance.
+ * @return Status code indicating success of the function call.
+ *
+ * You can use this function to switch back to the BLE 2Mbps PHY from the
+ * default 1Mbps option. You may only call this function after initializing BLE
+ * and while the radio is idle.
+ *
+ * @note Not all chips support the 2Mbps PHY. Consult your part's reference
+ * manual to be sure that it does before trying this.
+ */
+RAIL_Status_t RAIL_BLE_ConfigPhy2MbpsViterbi(RAIL_Handle_t railHandle);
+
+/**
+ * Switch the legacy non-Viterbi 2Mbps BLE PHY.
+ *
+ * @param[in] railHandle Handle for RAIL instance.
+ * @return Status code indicating success of the function call.
+ *
+ * You can use this function to switch back to legacy BLE 2Mbps PHY from the
+ * default 1Mbps option. You may only call this function after initializing BLE
+ * and while the radio is idle.
+ *
+ * @note Not all chips support the 2Mbps PHY. Consult your part's reference
+ * manual to be sure that it does before trying this.
+ */
+RAIL_Status_t RAIL_BLE_ConfigPhy2Mbps(RAIL_Handle_t railHandle);
+
+/**
+ * Switch to the BLE Coded PHY.
+ *
+ * @param[in] railHandle Handle for RAIL instance.
+ * @param[in] ble_coding The RAIL_BLE_Coding_t to use
+ * @return Status code indicating success of the function call.
+ *
+ * You can use this function to switch back to BLE Coded PHY from the default
+ * 1Mbps option. You may only call this function after initializing BLE and
+ * while the radio is idle. When using a BLE Coded PHY, the subPhy in
+ * RAIL_AppendedInfo_t marks the coding of the received packet. A subPhy of 0
+ * marks a 500kbps packet, and a subPhy of 1 marks a 125kbps packet.
+ *
+ * @note Not all chips support the BLE Coded PHY. Consult your part's reference
+ * manual to be sure that it does before trying this.
+ */
+RAIL_Status_t RAIL_BLE_ConfigPhyCoded(RAIL_Handle_t railHandle,
+ RAIL_BLE_Coding_t ble_coding);
+
+/**
+ * Helper function to change BLE radio parameters.
+ *
+ * @param[in] railHandle Handle for RAIL instance.
+ * @param[in] crcInit The value to use for CRC initialization.
+ * @param[in] accessAddress The access address to use for the connection.
+ * @param[in] channel The logical channel that you're changing to. This is used to
+ * initialize the whitener if you're using whitening.
+ * @param[in] disableWhitening This can turn off the whitening engine and is useful
+ * for sending BLE test mode packets that don't have this turned on.
+ * @return Status code indicating success of the function call.
+ *
+ * This function can be used to switch radio parameters on every connection
+ * and/or channel change. It is BLE-aware and will set the access address,
+ * preamble, CRC initialization value, and whitening configuration without
+ * requiring you to load a new radio config.
+ */
+RAIL_Status_t RAIL_BLE_ConfigChannelRadioParams(RAIL_Handle_t railHandle,
+ uint32_t crcInit,
+ uint32_t accessAddress,
+ uint16_t channel,
+ bool disableWhitening);
+
+/** @} */ // end of BLE
+
+#endif // __RAIL_BLE_H__
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/ieee802154/rail_ieee802154.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/ieee802154/rail_ieee802154.h Thu Dec 07 14:01:42 2017 +0000
@@ -7,13 +7,11 @@
#ifndef __RAIL_IEEE802154_H__
#define __RAIL_IEEE802154_H__
-/**
- * @addtogroup Protocol_Specific
- * @{
- */
+#include "rail_types.h"
/**
- * @addtogroup IEEE802_15_4
+ * @addtogroup IEEE802_15_4 IEEE 802.15.4
+ * @ingroup Protocol_Specific
* @brief IEEE 802.15.4 configuration routines
*
* The functions in this group configure RAIL IEEE 802.15.4 hardware
@@ -21,14 +19,14 @@
* RAIL_IEEE802154_Init(). Make note that this function calls many other RAIL
* functions; the application is advised to not reconfigure any of these
* functions. When using 802.15.4 functionality in the 2.4 GHz band, consider
- * using RAIL_IEEE802154_2p4GHzRadioConfig() instead of RAIL_RadioConfig() and
- * RAIL_ChannelConfig().
+ * using RAIL_IEEE802154_Config2p4GHzRadio() instead of RAIL_ConfigRadio() and
+ * RAIL_ConfigChannels().
*
* @code{.c}
- * RAIL_IEEE802154_Config_t config = { false, false,
+ * RAIL_IEEE802154_Config_t config = { NULL, {100, 192, 894, RAIL_RF_STATE_RX},
* RAIL_IEEE802154_ACCEPT_STANDARD_FRAMES,
- * RAIL_RF_STATE_RX, 100, 192, 894, NULL };
- * RAIL_IEEE802154_2p4GHzRadioConfig();
+ * false, false };
+ * RAIL_IEEE802154_Config2p4GHzRadio();
* RAIL_IEEE802154_Init(&config);
* @endcode
*
@@ -40,24 +38,29 @@
* configuration.
*
* @code{.c}
- * uint8_t longAddress[8] = { 0x11, 0x22, 0x33, 0x44,
- * 0x55, 0x66, 0x77, 0x88};
* // PanID OTA value of 0x34 0x12
* // Short Address OTA byte order of 0x78 0x56
* // Long address with OTA byte order of 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88
- * RAIL_IEEE802154_AddrConfig_t nodeAddress = { 0x1234, 0x5678,
- * &longAddress[0] };
+ * RAIL_IEEE802154_AddrConfig_t nodeAddress = {
+ * { 0x1234, 0xFFFF },
+ * { 0x5678, 0xFFFF },
+ * { { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88 },
+ * { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }
+ * };
*
* bool status = RAIL_IEEE802154_SetAddresses(&nodeAddress);
*
* // Alternative methods:
- * status = RAIL_IEEE802154_SetPanId(nodeAddress.panId);
- * status = RAIL_IEEE802154_SetShortAddress(nodeAddress.shortAddr);
- * status = RAIL_IEEE802154_SetLongAddress(nodeAddress.longAddr);
+ * status = RAIL_IEEE802154_SetPanId(nodeAddress.panId[0], 0);
+ * status = RAIL_IEEE802154_SetPanId(nodeAddress.panId[1], 1);
+ * status = RAIL_IEEE802154_SetShortAddress(nodeAddress.shortAddr[0], 0);
+ * status = RAIL_IEEE802154_SetShortAddress(nodeAddress.shortAddr[1], 1);
+ * status = RAIL_IEEE802154_SetLongAddress(nodeAddress.longAddr[0], 0);
+ * status = RAIL_IEEE802154_SetLongAddress(nodeAddress.longAddr[1], 1);
* @endcode
*
* Auto ack is initialized through RAIL_IEEE802154_Init(). It is not advised
- * to call RAIL_AutoAckConfig() while 802.15.4 hardware acceleration is
+ * to call RAIL_ConfigAutoAck() while 802.15.4 hardware acceleration is
* enabled. The default IEEE 802.15.4 ack will have a 5 byte length. The frame
* type will be an ack. The frame pending bit will be set based on the
* RAIL_IEEE802154_SetFramePending() function. The sequence number will be set to
@@ -72,11 +75,10 @@
* @enum RAIL_IEEE802154_AddressLength_t
* @brief Different lengths that an 802.15.4 address can have
*/
-typedef enum RAIL_IEEE802154_AddressLength
-{
+RAIL_ENUM(RAIL_IEEE802154_AddressLength_t) {
RAIL_IEEE802154_ShortAddress = 2, /**< 2 byte short address. */
RAIL_IEEE802154_LongAddress = 3, /**< 8 byte extended address. */
-} RAIL_IEEE802154_AddressLength_t;
+};
/**
* @struct RAIL_IEEE802154_Address_t
@@ -84,30 +86,51 @@
* This structure is only used for a received address, which needs to be parsed
* to discover the type.
*/
-typedef struct RAIL_IEEE802154_Address
-{
+typedef struct RAIL_IEEE802154_Address{
+ /** Convenient storage for different address types */
+ union {
+ uint16_t shortAddress; /**< Present for 2 byte addresses. */
+ uint8_t longAddress[8]; /**< Present for 8 byte addresses. */
+ };
/**
* Enum of the received address length
*/
RAIL_IEEE802154_AddressLength_t length;
- union
- {
- uint16_t shortAddress; /**< Present for 2 byte addresses. */
- uint8_t longAddress[8]; /**< Present for 8 byte addresses. */
- };
} RAIL_IEEE802154_Address_t;
+/** The maximum number of allowed addresses of each type. */
+#define RAIL_IEEE802154_MAX_ADDRESSES 3
+
/**
* @struct RAIL_IEEE802154_AddrConfig_t
* @brief Configuration structure for IEEE 802.15.4 Address Filtering. The
* broadcast addresses are handled separately, and do not need to be specified
- * here. Any address which is NULL will be ignored.
+ * here. Any address to be ignored should be set with all bits high.
+ *
+ * This structure allows configuration of dual-PAN functionality, by specifying
+ * multiple PAN IDs and short addresses. A packet will be received if it
+ * matches either PAN ID and the long address. The short addresses are specific
+ * to a given PAN, so the first short address goes with the first PAN ID, and
+ * not with the second PAN ID. The broadcast PAN ID and address will work with
+ * any address or PAN ID, respectively.
*/
-typedef struct RAIL_IEEE802154_AddrConfig
-{
- uint16_t panId; /**< PAN ID for destination filtering. */
- uint16_t shortAddr; /**< Network address for destination filtering. */
- uint8_t *longAddr; /**< 64 bit address for destination filtering. In OTA byte order.*/
+typedef struct RAIL_IEEE802154_AddrConfig{
+ /**
+ * PAN IDs for destination filtering. Both must be specified.
+ * To disable a PAN ID, set it to the broadcast value, 0xFFFF.
+ */
+ uint16_t panId[RAIL_IEEE802154_MAX_ADDRESSES];
+ /**
+ * Short network addresses for destination filtering. Both must be specified.
+ * To disable a short address, set it to the broadcast value, 0xFFFF.
+ */
+ uint16_t shortAddr[RAIL_IEEE802154_MAX_ADDRESSES];
+ /**
+ * 64 bit address for destination filtering. Both must be specified.
+ * This field is parsed in over-the-air (OTA) byte order. To disable a long
+ * address, set it to the reserved value of 0x00 00 00 00 00 00 00 00.
+ */
+ uint8_t longAddr[RAIL_IEEE802154_MAX_ADDRESSES][8];
} RAIL_IEEE802154_AddrConfig_t;
/**
@@ -116,6 +139,28 @@
*/
typedef struct RAIL_IEEE802154_Config {
/**
+ * Configure the RAIL Address Filter to allow the given destination
+ * addresses. If addresses is NULL, defer destination address configuration.
+ * If a member of addresses is NULL, defer configuration of just that member.
+ * This can be overridden via RAIL_IEEE802154_SetAddresses(), or the
+ * individual members can be changed via RAIL_IEEE802154_SetPanId(),
+ * RAIL_IEEE802154_SetShortAddress(), and RAIL_IEEE802154_SetLongAddress().
+ */
+ const RAIL_IEEE802154_AddrConfig_t *addresses;
+ /**
+ * Defines the acking configuration for the IEEE 802.15.4 implementation
+ */
+ RAIL_AutoAckConfig_t ackConfig;
+ /**
+ * Defines state timings for the IEEE 802.15.4 implementation
+ */
+ RAIL_StateTiming_t timings;
+ /**
+ * Set which 802.15.4 frame types will be received, of Beacon, Data, Ack, and
+ * Command. This setting can be overridden via RAIL_IEEE802154_AcceptFrames().
+ */
+ uint8_t framesMask;
+ /**
* Enable promiscuous mode during configuration. This can be overridden via
* RAIL_IEEE802154_SetPromiscuousMode() afterwards.
*/
@@ -125,48 +170,14 @@
* be overridden via RAIL_IEEE802154_SetPanCoordinator() afterwards.
*/
bool isPanCoordinator;
- /**
- * Set which 802.15.4 frame types will be received, of Beacon, Data, Ack, and
- * Command. This setting can be overridden via RAIL_IEEE802154_AcceptFrames().
- */
- uint8_t framesMask;
- /**
- * Defines the default radio state after a transmit operation (transmit
- * packet, wait for ack) or a receive operation (receive packet, transmit
- * ack) finishes.
- */
- RAIL_RadioState_t defaultState;
- /**
- * Define the idleToRx and idleToTx time
- * This defines the time it takes for the radio to go into RX or TX from an
- * idle radio state
- */
- uint16_t idleTime;
- /**
- * Define the turnaround time after receiving a packet and transmitting an
- * ack and vice versa
- */
- uint16_t turnaroundTime;
- /**
- * Define the ack timeout time in microseconds
- */
- uint16_t ackTimeout;
- /**
- * Configure the RAIL Address Filter to allow the given destination
- * addresses. If addresses is NULL, defer destination address configuration.
- * If a member of addresses is NULL, defer configuration of just that member.
- * This can be overridden via RAIL_IEEE802154_SetAddresses(), or the
- * individual members can be changed via RAIL_IEEE802154_SetPanId(),
- * RAIL_IEEE802154_SetShortAddress(), and RAIL_IEEE802154_SetLongAddress().
- */
- RAIL_IEEE802154_AddrConfig_t *addresses;
} RAIL_IEEE802154_Config_t;
/**
* Initialize RAIL for IEEE802.15.4 features
*
+ * @param[in] railHandle Handle of RAIL instance
* @param[in] config IEEE802154 configuration struct
- * @return \ref RAIL_STATUS_NO_ERROR if successfully configured.
+ * @return Status code indicating success of the function call.
*
* This function calls the following RAIL functions to configure the radio for
* IEEE802.15.4 features.
@@ -177,128 +188,153 @@
* - Configures RAIL Address Filter for 802.15.4 address filtering
*
* It calls the following functions:
- * - RAIL_AutoAckConfig()
+ * - RAIL_ConfigAutoAck()
* - RAIL_SetRxTransitions()
* - RAIL_SetTxTransitions()
* - RAIL_SetStateTiming()
- * - RAIL_AddressFilterConfig()
- * - RAIL_AddressFilterEnable()
+ * - RAIL_ConfigAddressFilter()
+ * - RAIL_EnableAddressFilter()
*/
-RAIL_Status_t RAIL_IEEE802154_Init(RAIL_IEEE802154_Config_t *config);
+RAIL_Status_t RAIL_IEEE802154_Init(RAIL_Handle_t railHandle,
+ const RAIL_IEEE802154_Config_t *config);
/**
* Configures the radio for 2.4GHz 802.15.4 operation
*
- * @return \ref RAIL_STATUS_NO_ERROR if successfully configured.
+ * @param[in] railHandle Handle of RAIL instance
+ * @return Status code indicating success of the function call.
*
* This initializes the radio for 2.4GHz operation. It takes the place of
- * calling \ref RAIL_RadioConfig and \ref RAIL_ChannelConfig. After this call,
+ * calling \ref RAIL_ConfigRadio and \ref RAIL_ConfigChannels. After this call,
* channels 11-26 will be available, giving the frequencies of those channels
* on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2.
*/
-RAIL_Status_t RAIL_IEEE802154_2p4GHzRadioConfig(void);
+RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadio(RAIL_Handle_t railHandle);
/**
* De-initializes IEEE802.15.4 hardware acceleration
*
- * @return 0 if IEEE802.15.4 hardware acceleration is successfully
- * deinitialized. Error code on failure
+ * @param[in] railHandle Handle of RAIL instance
+ * @return Status code indicating success of the function call.
*
* Disables and resets all IEE802.15.4 hardware acceleration features. This
* function should only be called when the radio is IDLE. This calls the
* following:
- * - RAIL_AutoAckDisable(), which resets the state transitions to IDLE
* - RAIL_SetStateTiming(), to reset all timings to 100 us
- * - RAIL_AddressFilterDisable()
- * - RAIL_AddressFilterReset()
+ * - RAIL_EnableAddressFilter(false)
+ * - RAIL_ResetAddressFilter()
*/
-RAIL_Status_t RAIL_IEEE802154_Deinit(void);
+RAIL_Status_t RAIL_IEEE802154_Deinit(RAIL_Handle_t railHandle);
/**
* Return whether IEEE802.15.4 hardware accelertion is currently enabled.
*
+ * @param[in] railHandle Handle of RAIL instance
* @return True if IEEE802.15.4 hardware acceleration was enabled to start with
* and false otherwise
*/
-bool RAIL_IEEE802154_IsEnabled(void);
+bool RAIL_IEEE802154_IsEnabled(RAIL_Handle_t railHandle);
/**
* Configure the RAIL Address Filter for 802.15.4 filtering
*
+ * @param[in] railHandle Handle of RAIL instance
* @param[in] addresses The address information that should be used
- * @return True if addresses were successfully set, false otherwise
+ * @return Status code indicating success of the function call. If this returns
+ * an error, then the 802.15.4 address filter is in an undefined state.
*
* Set up the 802.15.4 address filter to accept messages to the given
- * addresses. This will return true if at least one address was successfully
- * stored to be used.
+ * addresses. This will return false if any of the addresses failed to be set.
+ * If NULL is passed in for addresses, then all addresses will be set to their
+ * reset value.
*/
-bool RAIL_IEEE802154_SetAddresses(RAIL_IEEE802154_AddrConfig_t *addresses);
+RAIL_Status_t RAIL_IEEE802154_SetAddresses(RAIL_Handle_t railHandle,
+ const RAIL_IEEE802154_AddrConfig_t *addresses);
/**
* Set a PAN ID for 802.15.4 address filtering
*
+ * @param[in] railHandle Handle of RAIL instance
* @param[in] panId The 16-bit PAN ID information.
* This will be matched against the destination PAN ID of incoming messages.
* The PAN ID is sent little endian over the air meaning panId[7:0] is first in
* the payload followed by panId[15:8].
- * @return True if the PAN ID was successfully set, false otherwise
+ * @param[in] index Which PAN ID to set. Must be below
+ * RAIL_IEEE802154_MAX_ADDRESSES.
+ * @return Status code indicating success of the function call.
*
* Set up the 802.15.4 address filter to accept messages to the given PAN ID.
*/
-bool RAIL_IEEE802154_SetPanId(uint16_t panId);
+RAIL_Status_t RAIL_IEEE802154_SetPanId(RAIL_Handle_t railHandle,
+ uint16_t panId,
+ uint8_t index);
/**
* Set a short address for 802.15.4 address filtering
*
+ * @param[in] railHandle Handle of RAIL instance
* @param[in] shortAddr 16 bit short address value. This will be matched against the
* destination short address of incoming messages. The short address is sent
* little endian over the air meaning shortAddr[7:0] is first in the payload
* followed by shortAddr[15:8].
- * @return True if the short address was successfully set, false otherwise
+ * @param[in] index Which short address to set. Must be below
+ * RAIL_IEEE802154_MAX_ADDRESSES.
+ * @return Status code indicating success of the function call.
*
* Set up the 802.15.4 address filter to accept messages to the given short
* address.
*/
-bool RAIL_IEEE802154_SetShortAddress(uint16_t shortAddr);
+RAIL_Status_t RAIL_IEEE802154_SetShortAddress(RAIL_Handle_t railHandle,
+ uint16_t shortAddr,
+ uint8_t index);
/**
* Set a long address for 802.15.4 address filtering
*
+ * @param[in] railHandle Handle of RAIL instance
* @param[in] longAddr Pointer to a 8 byte array containing the long address
* information. The long address must be in over the air byte order. This will
* be matched against the destination long address of incoming messages.
- * @return True if the long address was successfully set, false otherwise
+ * @param[in] index Which long address to set. Must be below
+ * RAIL_IEEE802154_MAX_ADDRESSES.
+ * @return Status code indicating success of the function call.
*
* Set up the 802.15.4 address filter to accept messages to the given long
* address.
*/
-bool RAIL_IEEE802154_SetLongAddress(uint8_t *longAddr);
+RAIL_Status_t RAIL_IEEE802154_SetLongAddress(RAIL_Handle_t railHandle,
+ const uint8_t *longAddr,
+ uint8_t index);
/**
* Set whether the current node is a PAN coordinator
*
+ * @param[in] railHandle Handle of RAIL instance
* @param[in] isPanCoordinator True if this device is a PAN coordinator
- * @return Returns zero on success and an error code on error
+ * @return Status code indicating success of the function call.
*
* If the device is a PAN Coordinator, then it will accept data and command
* frames with no destination address. This function will fail if 802.15.4
* hardware acceleration is not currently enabled. This setting may be changed
* at any time when 802.15.4 hardwarea acceleration is enabled.
*/
-RAIL_Status_t RAIL_IEEE802154_SetPanCoordinator(bool isPanCoordinator);
+RAIL_Status_t RAIL_IEEE802154_SetPanCoordinator(RAIL_Handle_t railHandle,
+ bool isPanCoordinator);
/**
* Set whether to enable 802.15.4 promiscuous mode
*
+ * @param[in] railHandle Handle of RAIL instance
* @param[in] enable True if all frames and addresses should be accepted
- * @return Returns zero on success and an error code on error
+ * @return Status code indicating success of the function call.
*
* If promiscuous mode is enabled, then no frame or address filtering steps
* will be performed, other than checking the CRC. This function will fail if
* 802.15.4 hardware acceleration is not currently enabled. This setting may be
* changed at any time when 802.15.4 hardware acceleration is enabled.
*/
-RAIL_Status_t RAIL_IEEE802154_SetPromiscuousMode(bool enable);
+RAIL_Status_t RAIL_IEEE802154_SetPromiscuousMode(RAIL_Handle_t railHandle,
+ bool enable);
/// When receiving packets, accept 802.15.4 BEACON frame types
#define RAIL_IEEE802154_ACCEPT_BEACON_FRAMES (0x01)
@@ -313,15 +349,16 @@
/// In standard operation, accept BEACON, DATA and COMMAND frames.
/// Only receive ACK frames while waiting for ack
-#define RAIL_IEEE802154_ACCEPT_STANDARD_FRAMES (RAIL_IEEE802154_ACCEPT_BEACON_FRAMES | \
- RAIL_IEEE802154_ACCEPT_DATA_FRAMES | \
- RAIL_IEEE802154_ACCEPT_COMMAND_FRAMES)
+#define RAIL_IEEE802154_ACCEPT_STANDARD_FRAMES (RAIL_IEEE802154_ACCEPT_BEACON_FRAMES \
+ | RAIL_IEEE802154_ACCEPT_DATA_FRAMES \
+ | RAIL_IEEE802154_ACCEPT_COMMAND_FRAMES)
/**
* Set which 802.15.4 frame types to accept
*
+ * @param[in] railHandle Handle of RAIL instance
* @param[in] framesMask Mask containing which 802.15.4 frame types to receive
- * @return Returns zero on success and an error code on error
+ * @return Status code indicating success of the function call.
*
* This function will fail if 802.15.4 hardware acceleration is not currently
* enabled. This setting may be changed at any time when 802.15.4 hardware
@@ -335,40 +372,36 @@
* RAIL_IEEE802154_ACCEPT_ACK_FRAMES is not set, ACK frames will be filtered
* unless the radio is waiting for an ACK.
*/
-RAIL_Status_t RAIL_IEEE802154_AcceptFrames(uint8_t framesMask);
-
-/**
- * Callback for when a Data Request is being received
- *
- * @param address The source address of the data request command
- *
- * This function is called when the command byte of an incoming frame is for a
- * data request, which requests an ACK. This callback will be called before the
- * packet is fully received, to allow the node to have more time to decide
- * whether to set frame pending in the outgoing ACK.
- */
-void RAILCb_IEEE802154_DataRequestCommand(RAIL_IEEE802154_Address_t *address);
+RAIL_Status_t RAIL_IEEE802154_AcceptFrames(RAIL_Handle_t railHandle,
+ uint8_t framesMask);
/**
* Set the frame pending bit on the outgoing ACK
*
- * @return Returns zero on success and an error code on error
+ * @param[in] railHandle Handle of RAIL instance
+ * @return Status code indicating success of the function call.
*
- * This function should be called after receiving
- * RAILCb_IEEE802154_DataRequestCommand(), if the given source address has a
- * pending frame. This will return \ref RAIL_STATUS_INVALID_STATE if it is too
- * late to modify the ACK.
+ * This function should be called after receiving \ref
+ * RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND, if the given source address has
+ * a pending frame. This will return \ref RAIL_STATUS_INVALID_STATE if it is
+ * too late to modify the ACK.
*/
-RAIL_Status_t RAIL_IEEE802154_SetFramePending(void);
+RAIL_Status_t RAIL_IEEE802154_SetFramePending(RAIL_Handle_t railHandle);
/**
- * @}
- * end of IEEE802.15.4
+ * Get the source address of the incoming data request.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[out] pAddress Pointer to \ref RAIL_IEEE802154_Address_t structure
+ * to populate with address information.
+ * @return Status code indicating success of the function call.
+ *
+ * This function should only be called when handling the \ref
+ * RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND event.
*/
+RAIL_Status_t RAIL_IEEE802154_GetAddress(RAIL_Handle_t railHandle,
+ RAIL_IEEE802154_Address_t *pAddress);
-/**
- * @}
- * end of Protocol_Specific
- */
+/** @} */ // end of IEEE802.15.4
#endif // __RAIL_IEEE802154_H__
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/pa.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/pa.h Thu Dec 07 14:01:42 2017 +0000
@@ -34,6 +34,27 @@
#include <stdint.h>
#include <stdbool.h>
+#include "timing_state.h"
+#include "rail_chip_specific.h"
+
+// Once this is a RAIL API this code can be removed as rail-types.h does this
+#ifndef RAIL_ENUM
+#ifdef DOXYGEN_SHOULD_SKIP_THIS
+/// The RAIL library does not use actual enums because the ARM EABI leaves their
+/// size ambiguous. This ambiguity causes problems if the application is built
+/// with different flags than the library. To work around this we use uint8_t
+/// typedefs in compiled code for all enums. For documentation purposes this is
+/// converted to an actual enum since it's much easier to read in Doxygen.
+#define RAIL_ENUM(name) enum name
+#else
+/// Define used for the actual RAIL library which sets each enum to a uint8_t
+/// typedef and creates a named enum structure for the enumeration values.
+#define RAIL_ENUM(name) typedef uint8_t name; enum name##_enum
+// For debugging use the following define to turn this back into a proper enum
+// #define RAIL_ENUM(name) typedef enum name##_enum name; enum name##_enum
+#endif
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -49,55 +70,6 @@
******************************************************************************/
/*******************************************************************************
- **************************** CONFIGURATION ********************************
- ******************************************************************************/
-/** Scaling factor applied to all dBm power level inputs and outputs * */
-#define PA_SCALING_FACTOR 10
-
-/**
- * @brief Selection of the rf power amplifier (PA) to use
- */
-typedef enum RADIO_PASel
-{
- /** High power PA */
- PA_SEL_2P4_HP,
- /** Low power PA */
- PA_SEL_2P4_LP,
- /** SubGig PA*/
- PA_SEL_SUBGIG,
- /** Invalid PA Selection */
- PA_SEL_INVALID
-} RADIO_PASel_t;
-
-/**
- * @brief Selection should match the configuration of the voltage on the vPa pin
- * of the chip.
- */
-typedef enum RADIO_PAVoltMode
-{
- /** Vpa = Vbat = 3.3V */
- PA_VOLTMODE_VBAT,
- /** Vpa = DCDC Vout = 1.8V */
- PA_VOLTMODE_DCDC
-} RADIO_PAVoltMode_t;
-
-/**
- * @brief Configuration structure for the rf power amplifier (PA)
- */
-typedef struct RADIO_PAInit {
- /** Power Amplifier mode */
- RADIO_PASel_t paSel;
- /** Power Amplifier vPA Voltage mode */
- RADIO_PAVoltMode_t voltMode;
- /** Desired output power in dBm * \ref PA_SCALING_FACTOR */
- int16_t power;
- /** Output power offset in dBm * \ref PA_SCALING_FACTOR */
- int16_t offset;
- /** Desired ramp time in us */
- uint16_t rampTime;
-} RADIO_PAInit_t;
-
-/*******************************************************************************
****************************** PROTOTYPES *********************************
******************************************************************************/
@@ -106,65 +78,38 @@
* Initilize the PA settings based on the settings provided in the paInit
* structure.
*
- * @param[in] paInit
+ * @param[in] paConfig
* Pointer to a structure containing the desired PA configuration settings.
*
* @return
- * True if the settings were accepted.
- * False if settings were invalid.
+ * RAIL_Status_t indicating success
*
* @warning
* The radio should not be transmitting when this function is called!
-*/
-bool RADIO_PA_Init(RADIO_PAInit_t * paInit);
+ */
+RAIL_Status_t PA_Config(const RAIL_TxPowerConfig_t *paConfig);
+
+/**
+ * @brief
+ * Get the current PA settings in use
+ *
+ * @param[out] config
+ * Pointer to memory location into which the configuration will be
+ * copied
+ *
+ * @return
+ * RAIL_Status_t indicating success
+ */
+RAIL_Status_t PA_GetTxPowerConfig(RAIL_TxPowerConfig_t *config);
/**
* @brief
* Returns the current power level of transmit power
*
* @return
- * Current power level in dBm * \ref PA_SCALING_FACTOR
+ * Current power level in deci-dBm
*/
-int32_t PA_OutputPowerGet(void);
-
-/**
- * @brief
- * Sets the output power of the PA.
- *
- * Each PA has distinct maximum power, minimum power, and power step sizes.
- * This API will calculate the best pa output power level setting to acheieve
- * the desired output power.
- *
- * @note
- * Board and chip variations will affect the accuracy of this API. Use
- * of the RADIO_PAInit_t.offset paramter can help account for this variation.
- *
- * @param[in] power
- * Power value in dBm * \ref PA_SCALING_FACTOR
- *
- * Examples with \ref PA_SCALING_FACTOR of 10:
- * - 10 dBm --> 100
- * - 5.5 dBm --> 55
- *
- * @return
- * Returns the actual power that was set in dBm * \ref PA_SCALING_FACTOR
- *
- * @warning
- * The radio should not be transmitting when this function is called!
- */
-int32_t PA_OutputPowerSet(int32_t power);
-
-/**
- * @brief
- * Set the maximum possible output power for the selected PA.
- *
- * @return
- * Returns the actual power that was set in dBm * \ref PA_SCALING_FACTOR
- *
- * @warning
- * The radio should not be transmitting when this function is called!
- */
-int32_t PA_MaxOutputPowerSet(void);
+RAIL_TxPowerLevel_t PA_GetPowerLevel(void);
/**
* @brief
@@ -173,7 +118,7 @@
* @return
* Current ramp time in microseconds
*/
-uint32_t PA_RampTimeGet(void);
+uint32_t PA_GetRampTime(void);
/**
* @brief
@@ -193,7 +138,18 @@
* @warning
* The radio should not be transmitting when this function is called!
*/
-uint32_t PA_RampTimeSet(uint32_t ramptime);
+uint32_t PA_SetRampTime(uint32_t ramptime, StateTimings_t *timings);
+
+/**
+ * Enable/Disable PA calibration
+ *
+ * @param[in] enable Enables/Disables PA calibration
+ * @return void
+ *
+ * Enabling this will ensure that the PA power remains constant chip to chip.
+ * By default this feature is disabled after reset.
+ */
+void PA_EnableCal(bool enable);
/***************************************************************************//**
* @addtogroup EFR32xG1x_PA_Advanced
@@ -211,13 +167,13 @@
* @param[in] rxPaCtuneValue
* Receive value for pa ctune
*
- * @note PACTUNE will reset to default values when RADIO_PA_Init() or
- * RAIL_RadioConfig() are called.
+ * @note PACTUNE will reset to default values when PA_Config() or
+ * RAIL_ConfigRadio() are called.
*
* @warning
* The radio should not be transmitting when this function is called!
*/
-void PA_CTuneSet(uint8_t txPaCtuneValue, uint8_t rxPaCtuneValue);
+void PA_SetCTune(uint8_t txPaCtuneValue, uint8_t rxPaCtuneValue);
/**
* @brief
@@ -231,43 +187,50 @@
* @param[in] pwrLevel
* Output power level. Note that the maximum power level will change
* depending on PA selection.
- * @param[in] boostMode
- * Output boost mode. Some PA selections have a mode that will increase the
- * output power for each step if this is enabled.
*
* @return
- * MSB Configured boost mode. \n
- * LSB Configured power level
+ * Power level set in the current PA.
*
* @warning
* The radio should not be transmitting when this function is called!
*/
-uint16_t PA_PowerLevelSet(uint8_t pwrLevel, uint8_t boostMode);
-
-/**
- * @brief
- * Optimize the PA settings based on expected output power level.
- *
- * @details
- * This API optimizes the current consumption of the radio based on the
- * provided output power. This is only necessary when output power is
- * controlled by PA_PowerLevelSet().
- *
- * @param[in] power
- * Power value in dBm * \ref PA_SCALING_FACTOR
- *
- * @warning
- * The radio should not be transmitting when this function is called!
- */
-void PA_PowerLevelOptimize(int32_t power);
+RAIL_TxPowerLevel_t PA_SetPowerLevel(RAIL_TxPowerLevel_t pwrLevel);
/** @} (end addtogroup EFR32xG1x_PA_Advanced) */
/** @} (end addtogroup EFR32xG1x_PA) */
/** @} (end addtogroup Chip_Specific) */
+/**
+ * Non RAIL functions.
+ *
+ * The following functions can only be safely used by customers not yet on the
+ * RAIL platform yet. For those on RAIL, please see RAIL_ConvertDbmToRaw and
+ * RAIL_ConvertRawToDbm.
+ */
+
+/**
+ * Function used to convert deci-dBm values to raw values that can be used in
+ * SetTxPower.
+ *
+ * @param[in] power deci-dBm value that should be converted to the appropriate
+ * raw power for the current PA
+ * @return equivalent raw power for the deci-dBm value supplied, for the active
+ * PA.
+ */
+RAIL_TxPowerLevel_t PA_ConvertDbmToRaw(RAIL_TxPower_t power);
+
+/**
+ * Function to convert the raw power levels returned from GetTxPower to
+ * the equivalent deci-dBm value for the current PA.
+ *
+ * @param[in] powerLevel Raw PA power level that should be converted into
+ * the equivalent deci-dBm value for the active PA
+ * @return equivalent deci-dBm value for the raw power level passed in.
+ */
+RAIL_TxPower_t PA_ConvertRawToDbm(RAIL_TxPowerLevel_t powerLevel);
+
#ifdef __cplusplus
}
#endif
-
#endif /* __RADIO_PA_H */
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/pti.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/pti.h Thu Dec 07 14:01:42 2017 +0000
@@ -13,60 +13,76 @@
#endif
#include <stdint.h>
+
#include "em_gpio.h"
-/******************************** TYPEDEFS *********************************/
-
-/** Channel type enumeration. */
-typedef enum RADIO_PTIMode
-{
- /** SPI mode. */
- RADIO_PTI_MODE_SPI = 0U,
- /** UART mode. */
- RADIO_PTI_MODE_UART = 1U,
- /** 9bit UART mode. */
- RADIO_PTI_MODE_UART_ONEWIRE = 2U,
- /** Turn PTI off entirely */
- RADIO_PTI_MODE_DISABLED = 3U,
-} RADIO_PTIMode_t;
-
-/**
- * @struct RADIO_PTIInit_t
- * @brief Configuration structure for the packet trace interface (PTI)
- */
-typedef struct RADIO_PTIInit {
- /** Packet Trace mode (UART or SPI) */
- RADIO_PTIMode_t mode;
+#include "rail_chip_specific.h"
- /** Output baudrate for PTI in Hz */
- uint32_t baud;
-
- /** Data output (DOUT) location for pin/port */
- uint8_t doutLoc;
- /** Data output (DOUT) GPIO port */
- GPIO_Port_TypeDef doutPort;
- /** Data output (DOUT) GPIO pin */
- uint8_t doutPin;
+// Once this is a RAIL API this code can be removed as rail-types.h does this
+#ifndef RAIL_ENUM
+#ifdef DOXYGEN_SHOULD_SKIP_THIS
+/// The RAIL library does not use actual enums because the ARM EABI leaves their
+/// size ambiguous. This ambiguity causes problems if the application is built
+/// with different flags than the library. To work around this we use uint8_t
+/// typedefs in compiled code for all enums. For documentation purposes this is
+/// converted to an actual enum since it's much easier to read in Doxygen.
+#define RAIL_ENUM(name) enum name
+#else
+/// Define used for the actual RAIL library which sets each enum to a uint8_t
+/// typedef and creates a named enum structure for the enumeration values.
+#define RAIL_ENUM(name) typedef uint8_t name; enum name##_enum
+// For debugging use the following define to turn this back into a proper enum
+// #define RAIL_ENUM(name) typedef enum name##_enum name; enum name##_enum
+#endif
+#endif
- /** Data clock (DCLK) location for pin/port. Only used in SPI mode */
- uint8_t dclkLoc;
- /** Data clock (DCLK) GPIO port. Only used in SPI mode */
- GPIO_Port_TypeDef dclkPort;
- /** Data clock (DCLK) GPIO pin. Only used in SPI mode */
- uint8_t dclkPin;
+/***************************************************************************//**
+ * @addtogroup Chip_Specific
+ * @{
+ ******************************************************************************/
- /** Data frame (DFRAME) location for pin/port. Only used for */
- uint8_t dframeLoc;
- /** Data frame (DFRAME) GPIO port */
- GPIO_Port_TypeDef dframePort;
- /** Data frame (DFRAME) GPIO pin */
- uint8_t dframePin;
-} RADIO_PTIInit_t;
+/***************************************************************************//**
+ * @addtogroup EFR32xG1x_PTI
+ * @{
+ * @brief EFR32 Packet Trace Interface (PTI) setup and configuration
+ ******************************************************************************/
/************************* FUNCTION PROTOTYPES *****************************/
-void RADIO_PTI_Init(RADIO_PTIInit_t *pitInit);
-void RADIO_PTI_Enable(void);
-void RADIO_PTI_Disable(void);
+
+/**
+ * Initialize the PTI interface
+ *
+ * @param ptiInit The structure that defines what pins and modes to use for
+ * packet trace.
+ *
+ * This API will initialize the packet trace interface. It allows you to
+ * configure what mode and pins to use for packet trace output. You must call
+ * this API either before RAIL initialization or before an explicit call to
+ * \ref PTI_Enable() to properly initialize PTI.
+ */
+RAIL_Status_t PTI_Config(const RAIL_PtiConfig_t *config);
+
+/**
+ * Enable or disable the PTI interface
+ *
+ * This API will turn on or off the packet trace interface (PTI). By default
+ * this is turned on already during init time. Note that you must call \ref
+ * RADIO_PTI_Init() with a valid initialization structure before calling this
+ * API or PTI will not actually turn on.
+ */
+RAIL_Status_t PTI_Enable(bool enable);
+
+/**
+ * Get the current state of the PTI
+ *
+ * This function will return a pointer to a copy of the PTI state. If you
+ * actually want to change the settings, the referenced structure must be
+ * updated and then passed back to \ref RADIO_PTI_Config
+ */
+RAIL_Status_t PTI_GetConfig(RAIL_PtiConfig_t *ptiConfig);
+
+/** @} (end addtogroup EFR32xG1x_PTI) */
+/** @} (end addtogroup Chip_Specific) */
#ifdef __cplusplus
}
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
-/***************************************************************************//**
+/**************************************************************************//**
* @file rail.h
* @brief The main header file for the RAIL library. It describes the external
* APIs available to a RAIL user
* @copyright Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************/
+ *****************************************************************************/
#ifndef __RAIL_H__
#define __RAIL_H__
@@ -12,468 +12,606 @@
#include <stdint.h>
#include <stdbool.h>
-// Get the RAIL specific structures and types
+// Get the RAIL-specific structures and types
+#include "rail_chip_specific.h"
#include "rail_types.h"
/**
- * @addtogroup RAIL_API
+ * @addtogroup RAIL_API RAIL API
* @brief This is the primary API layer for the Radio Abstraction Interface
- * Layer (RAIL)
+ * Layer (RAIL)
* @{
*/
+/**
+ * @defgroup Protocol_Specific Protocol Specific
+ * @brief Protocol specific RAIL APIs
+ */
+
/******************************************************************************
* General Radio Operation
*****************************************************************************/
/**
* @addtogroup General
- * @brief Basic APIs for setting up and interacting with the RAIL library
+ * @brief Basic APIs to set up and interact with the RAIL library
+ * @{
+ */
+
+/**
+ * Gets the version information for the compiled RAIL library.
+ *
+ * @param[out] version A pointer to \ref RAIL_Version_t structure to
+ * populate with version information.
+ * @param[in] verbose Populate \ref RAIL_Version_t struct with verbose
+ * information.
+ * @return void.
+ *
+ * The version information contains a major version number, a minor version
+ * number, and a rev (revision) number.
+ */
+void RAIL_GetVersion(RAIL_Version_t *version, bool verbose);
+
+/**
+ * Initializes RAIL.
+ *
+ * @param[in,out] railCfg The configuration and state structure for setting up
+ * the library, which contains memory and other options needed by RAIL.
+ * This structure must be allocated in application global read-write
+ * memory. RAIL may modify fields within or referenced by this structure
+ * during its operation.
+ * @param[in] cb A callback that notifies the application when the radio is
+ * finished initializing and is ready for further configuration. This
+ * callback is useful for potential transceiver products that require a
+ * power up sequence before further configuration is available. After the
+ * callback fires, the radio is ready for additional configuration before
+ * transmit and receive operations.
+ * @return Handle for initialized rail instance or NULL if an
+ * invalid value was passed in the railCfg.
+ */
+RAIL_Handle_t RAIL_Init(RAIL_Config_t *railCfg,
+ RAIL_InitCompleteCallbackPtr_t cb);
+
+/**
+ * Collects entropy from the radio if available.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[out] buffer The buffer to write the collected entropy.
+ * @param[in] bytes The number of bytes to fill in in the input buffer.
+ * @return Returns the number of bytes of entropy collected. For
+ * chips that don't support entropy collection, the function returns 0.
+ * Values less than the requested amount may also be returned on platforms
+ * that use entropy pools to collect random data periodically.
+ *
+ * Attempts to fill the provided buffer with the requested number of bytes of
+ * entropy. If the requested number of bytes can't be provided, as many
+ * bytes as possible will be filled and returned. For chips
+ * that do not support this function, 0 bytes will always be returned. For
+ * information about the specific mechanism for gathering entropy, see
+ * documentation for the chip family.
+ */
+uint16_t RAIL_GetRadioEntropy(RAIL_Handle_t railHandle,
+ uint8_t *buffer,
+ uint16_t bytes);
+
+/** @} */ // end of group General
+
+/******************************************************************************
+ * PTI
+ *****************************************************************************/
+/**
+ * @addtogroup PTI Packet Trace (PTI)
+ * @brief Basic APIs to set up and interact with PTI settings
* @{
*/
/**
- * Get the version information for the compiled RAIL library.
+ * Configures PTI pin locations, serial protocols, and baud rates.
+ *
+ * @param[in] railHandle A RAIL instance handle (currently not used).
+ * @param[in] config A configuration structure applied to the
+ * relevant PTI registers.
+ * @return Status code indicating success of the function call.
*
- * @param[in] version Pointer to \ref RAIL_Version_t struct to populate with version
- * information.
- * @param[in] verbose Populate \ref RAIL_Version_t struct with verbose information
- *
- * Version information contains a major version number, a minor version number,
- * and a rev (revision) number.
+ * This method must be called before RAIL_EnablePti() is called.
+ * Although we do take a RAIL handle for potential future
+ * expansion of this function, it is currently not used. That is,
+ * there is only one PTI configuration that can be active on a
+ * chip, regardless of the number of protocols (unless the application
+ * takes responsibility to update the configuration upon a protocol switch),
+ * and the configuration is not saved in your RAIL instance. For optimal
+ * future compatibility, pass in a chip specific handle, such as
+ * \ref RAIL_EFR32_HANDLE for now.
*/
-void RAIL_VersionGet(RAIL_Version_t * version, bool verbose);
+RAIL_Status_t RAIL_ConfigPti(RAIL_Handle_t railHandle,
+ const RAIL_PtiConfig_t *config);
/**
- * Initialize RAIL
+ * Gets the currently active PTI configuration.
+ *
+ * @param[in] railHandle A RAIL instance handle (currently not used).
+ * @param[out] ptiConfig A configuration structure filled with the active
+ * PTI configuration.
+ * @return RAIL status indicating success of the function call.
*
- * @param[in] railInit The initialization structure to be used for setting up
- * the library. This will contain memory and other options needed by RAIL.
- * @return Returns zero on success and an error code on error.
- *
- * RF initialization sets the overall maximum packet length, the xtal frequency
- * of the radio, and the calibrations to perform.
+ * Although most combinations of configurations can be set, it is safest
+ * to call this method after configuration to confirm which values were
+ * actually set. As in RAIL_ConfigPti, railHandle is not used. This function
+ * will always return the single active PTI configuration regardless of the
+ * active protocol. For optimal future compatibility, pass in a chip
+ * specific handle, such as \ref RAIL_EFR32_HANDLE for now.
*/
-uint8_t RAIL_RfInit(const RAIL_Init_t *railInit);
+RAIL_Status_t RAIL_GetPtiConfig(RAIL_Handle_t railHandle,
+ RAIL_PtiConfig_t *ptiConfig);
/**
- * Set protocol that RAIL outputs on PTI
+ * Enables the PTI output of the packet data.
+ *
+ * @param[in] railHandle A RAIL instance handle (currently not used).
+ * @param[in] enable PTI is enabled if true; disable if false.
+ * @return RAIL status indicating success of the function call.
*
- * @param protocol The enum representing which protocol the node is using
- * @return Returns zero on success and an error code on error.
+ * Similarly to how there is only one PTI configuration per chip,
+ * PTI can only be enabled or disabled for all protocols. It cannot
+ * be individually set to enabled and disabled per protocol
+ * (unless the application takes the responsibility of switching it when
+ * the protocol switches), and enable/disable is not saved as part of your
+ * RAIL instance. For optimal future compatibility, pass in a chip
+ * specific handle, such as \ref RAIL_EFR32_HANDLE for now.
+ */
+RAIL_Status_t RAIL_EnablePti(RAIL_Handle_t railHandle,
+ bool enable);
+
+/**
+ * Sets a protocol that RAIL outputs on PTI.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] protocol The enum representing which protocol the node is using.
+ * @return Status code indicating success of the function call.
*
* The protocol is output via the Packet Trace Interface (PTI) for each packet.
* Before any protocol is set, the default value is \ref
- * RAIL_PTI_PROTOCOL_CUSTOM. One of the enum values should be used in order for
- * Network Analyzer to be able to decode the packet.
+ * RAIL_PTI_PROTOCOL_CUSTOM. One of the enum values should be used so that
+ * the Network Analyzer can decode the packet.
*/
-RAIL_Status_t RAIL_SetPtiProtocol(RAIL_PtiProtocol_t protocol);
-
-/**
- * Callback for when the radio is finished initializing from \ref RAIL_RfInit
- * and is ready to be configured
- *
- * @return void
- *
- * Callback that notifies the application when the radio is finished
- * initializing and is ready for further configuration. This callback is
- * useful for potential transceiver products that require a power up sequence
- * before further configuration is available. After this callback fires, the
- * radio is ready for additional configuration before transmit and receive
- * operations.
- */
-void RAILCb_RfReady(void);
+RAIL_Status_t RAIL_SetPtiProtocol(RAIL_Handle_t railHandle,
+ RAIL_PtiProtocol_t protocol);
-/**
- * Get the current radio state
- *
- * @return An enumeration for current radio state
- *
- * Returns the state of the radio as either TX, RX, or IDLE. There are
- * intermediate states that the radio can transistion through which are not
- * reported, but are instead bucketed into the state being transitioned
- * into. (Example: When the transmitter is in the process of shutting down,
- * this function will return TX, as if the shutdown process hadn't started yet)
- */
-RAIL_RadioState_t RAIL_RfStateGet(void);
+/** @} */ // end of group PTI
-/**
- * Configure RAIL automatic state transitions after RX
- *
- * @param[in] success The next radio state to enter after a successful packet
- * reception.
- * @param[in] error The next radio state to enter after an error during packet
- * reception.
- * @param[in] ignoreErrors Define errors during packet handling to be ignored
- * @return Returns zero on success and an error code on error.
- *
- * This function fails if unsupported transitions are passed in, or if the
- * radio is currently in the RX state. Success can transition to TX, RX, or
- * IDLE, while error can transition to RX or IDLE. The full list of options for
- * the ignoreErrors parameter is any define that starts with
- * \link RAIL_IGNORE_NO_ERRORS RAIL_IGNORE_\endlink.
- */
-RAIL_Status_t RAIL_SetRxTransitions(RAIL_RadioState_t success,
- RAIL_RadioState_t error,
- uint8_t ignoreErrors);
-
+/******************************************************************************
+ * Radio Configuration
+ *****************************************************************************/
/**
- * Configure RAIL automatic state transitions after TX
- *
- * @param[in] success The next radio state to enter after a successful packet
- * transmission.
- * @param[in] error The next radio state to enter after an error during packet
- * transmission.
- * @return Returns zero on success and an error code on error.
- *
- * This function fails if unsupported transitions are passed in, or if the
- * radio is currently the TX state. Success and error can each transition to RX
- * or IDLE.
- */
-RAIL_Status_t RAIL_SetTxTransitions(RAIL_RadioState_t success,
- RAIL_RadioState_t error);
-
-/**
- * Configure RAIL automatic state transition timing
- *
- * @param[in] timings The timings used to configure the RAIL state machine. This
- * structure will be overwritten with the actual times that were set, in the
- * case of an input timing that is invalid.
- * @return Returns zero on success and an error code on error.
- *
- * The timings given will be close to the actual transition time, but there is
- * some software overhead that is not yet characterized. Also, timings are not
- * always adhered to when using an automatic transition after an error, due to
- * the cleanup required to recover from the error.
- */
-RAIL_Status_t RAIL_SetStateTiming(RAIL_StateTiming_t *timings);
-
-/**
- * Place the radio into an idle state
- *
- * @return void
- *
- * This function is used to remove the radio from TX and RX states.
- */
-void RAIL_RfIdle(void);
-
-/**
- * Extended radio idle API
- *
- * @param[in] mode The method to use for shutting down the radio.
- * @param[in] wait Whether this function should wait for the radio to reach idle
- * before returning.
- *
- * This is an extended version of the simple RAIL_RfIdle() API which lets the
- * application specify how it reaches idle state and if the function should
- * busy wait.
- */
-void RAIL_RfIdleExt(RAIL_RfIdleMode_t mode, bool wait);
-
-/**
- * Start/Stop RF Sense functionality for use during low-energy sleep modes.
+ * @addtogroup Radio_Configuration Radio Configuration
+ * @brief Routines for setting up and querying radio configuration information.
*
- * @param[in] band The frequency band(s) on which to sense RF energy.
- * To stop Rf Sense, specify \ref RAIL_RFSENSE_OFF.
- * @param[in] senseTime The time (in microseconds) RF energy must be
- * continually detected to be considered "sensed".
- * @param[in] enableCb Set true to enable \ref RAILCb_RxRadioStatus() callback
- * with status \ref RAIL_RX_CONFIG_RF_SENSED when Rf is sensed. Set false if
- * prefer to poll via \ref RAIL_RfSensed().
- *
- * @return The actual senseTime utilized, which may be different than
- * requested due to limitations of the hardware. If 0, RF sense was
- * disabled or it could not be enabled (no callback will be issued).
- *
- * The EFR32 has the ability to sense the presence of RF Energy above -20 dBm
- * within either or both the 2.4 GHz and Sub-GHz bands, and trigger an event
- * if that energy is continuously present for certain durations of time.
- *
- * @note After RF energy has been sensed, RF Sense is automatically disabled,
- * and RAIL_RfSense() must be called again to reactivate it.
- *
- * @warning RF Sense functionality is only guaranteed from 0 to
- * 85 degrees Celsius. RF Sense should be disabled
- * outside this Temperature range.
- */
-uint32_t RAIL_RfSense(RAIL_RfSenseBand_t band, uint32_t senseTime, bool enableCb);
-
-/**
- * Check if RF was sensed.
- *
- * @return true if RF was sensed since last call to \ref RAIL_RfSense; false
- * otherwise.
- *
- * This function is useful if \ref RAIL_RfSense has been called with enableCb
- * set to false. It is generally used after EM4 reboot, but can be used any
- * time.
- */
-bool RAIL_RfSensed(void);
-
-/**
- * Modify the currently configured fixed length
- *
- * @param[in] length Expected fixed length; 0 is infinite
- * @return Length configured; 0xFFFF if not in fixed length, 0 if in infinite
- *
- * Set the fixed length configuration for transmit and receive. Users should
- * be careful when using this function in receive and transmit. This function
- * returns \ref RAIL_SETFIXEDLENGTH_INVALID if the radio is not in fixed length
- * mode. The function returns 0 if in infinite length mode. Otherwise it will
- * return the length configured into the hardware.
- */
-uint16_t RAIL_SetFixedLength(uint16_t length);
-
-/***************************************************************************//**
- * Collect entropy from the radio if available.
- *
- * @param buffer The buffer to write the collected entropy to.
- * @param bytes The number of bytes to fill in in the input buffer
- * @return Returns the number of bytes of entropy we were able to collect. For
- * chips that don't support entropy collection this will return 0. Values less
- * than the requested amount may also be returned on platforms that use entropy
- * pools to collect random data periodically.
- *
- * Attempts to fill up the provided buffer with the requested number of bytes of
- * entropy. If we cannot provide as many bytes as requested then we will fill in
- * whatever we can and return the number of bytes we were able to get. For chips
- * that do not support this function we will always return 0 bytes. For
- * information about the specific mechanism for gathering entropy consult the
- * documentation for the chip family you're using.
- ******************************************************************************/
-uint16_t RAIL_GetRadioEntropy(uint8_t *buffer, uint16_t bytes);
-
-/**
- * @}
- */
-
-/**
- * @addtogroup Memory_Management
- * @brief Application callbacks to provide memory for RAIL actions.
- *
- * The RAIL library does not want to dictate how upper layers handle memory
- * allocation for packet receive data. At the same time we need to put the
- * packets somewhere to give them to the upper layers. To abstract this we
- * require the user application to implement the RAILCb_AllocateMemory(),
- * RAILCb_FreeMemory(), RAILCb_BeginWriteMemory(), and RAILCb_EndWriteMemory()
- * callbacks. These callbacks will be called from interrupt context to interact
- * with whatever memory allocation system your application uses.
- *
- * Memory will be allocated for receiving a packet whenever we think we need
- * it. This depends on the chip you're using and possibly the size of your
- * maximum packet. We will never ask for more memory than `MAX_PACKET_SIZE +
- * sizeof(\ref RAIL_RxPacketInfo_t)` where MAX_PACKET_SIZE is the maximum
- * packet your PHY is configured to receive over the air. Once you give us the
- * handle to this memory it must stay valid until we tell you we are done with
- * it using the RAILCb_FreeMemory() callback. Generally this will happen
- * immediately after we call the RAILCb_RxPacketReceived() function with that
- * handle. RAIL has no concept of an invalid handle so we will attempt to use
- * whatever you pass to us. This means that you will still receive all
- * callbacks for invalid handles even if we are forced to drop receive packet
- * bytes because they don't fit anywhere.
- *
- * If the handle is invalid you must make sure your callbacks do not
- * crash and that RAILCb_BeginWriteMemory() returns a NULL pointer or 0 bytes
- * available so that we do not try to write to this memory. In this case, the
- * packet data will be dropped.
- *
- * To actually write data to the handle you provide us we need to convert it
- * into an actual memory pointer. We will do this each time we need to access
- * the memory by calling RAILCb_BeginWriteMemory(). This function must return
- * a pointer to the requested offset in the memory buffer allocated. If you are
- * using non-contiguous memory buffers you can also return the number of bytes
- * available before we need to re-request a pointer with a new offset. Once the
- * access is complete we will call RAILCb_EndWriteMemory() with information
- * about exactly how many bytes were written at the specified offset. After this
- * call we will always call RAILCb_BeginWriteMemory() again before trying to
- * write any more data. In the event that you receive an invalid handle these
- * APIs must return NULL or set available bytes to 0 so that we do not attempt
- * to write packet data to the buffer.
- *
- * This system is fairly flexible and can tie into many higher level memory
- * allocation APIs. A simple example using one static buffer for memory
- * allocation is shown below. You will probably want a more advanced system
- * that can handle receiving multiple packets simultaneously.
+ * These routines allow for runtime flexibility in the radio
+ * configuration. Some of the parameters, however, are meant to be generated
+ * from the radio calculator in Simplicity Studio. The basic code to configure
+ * the radio from this calculator output looks like the example below.
*
* @code{.c}
- * static uint8_t buffer[MAX_PACKET_SIZE + sizeof(RAIL_RxPacketInfo_t)];
- * static bool isAllocated = false;
- *
- * void *RAILCb_AllocateMemory(uint32_t size)
- * {
- * int i = 0;
- * void *ptr = NULL;
- * CORE_DECLARE_IRQ_STATE;
- *
- * // We can't support sizes greater than the maximum buffer size
- * if(size > (MAX_PACKET_SIZE + sizeof(RAIL_RxPacketInfo_t))) {
- * return NULL;
- * }
+ * // Associate a specific channel config with a particular RAIL instance, and
+ * // load the settings that correspond to the first usable channel.
+ * RAIL_ConfigChannels(railHandle, channelConfigs[0]);
+ * @endcode
*
- * // Disable interrupts and attempt to grab the buffer
- * CORE_ENTER_CRITICAL();
- * if (isAllocated) {
- * ptr = NULL;
- * } else {
- * isAllocated = true;
- * ptr = buffer;
- * }
- * CORE_EXIT_CRITICAL();
- *
- * return ptr;
- * }
- *
- * void RAILCb_FreeMemory(void *ptr)
- * {
- * CORE_CRITICAL_SECTION(
- * isAllocated = false;
- * );
- * }
- *
- * void *RAILCb_BeginWriteMemory(void *handle,
- * uint32_t offset,
- * uint32_t *available)
- * {
- * return ((uint8_t*)handle) + offset;
- * }
- *
- * void RAILCb_EndWriteMemory(void *handle, uint32_t offset, uint32_t size)
- * {
- * // Do nothing
- * }
- * @endcode
+ * For more information about the types of parameters that can be changed in
+ * the other functions and how to use them, see their individual documentation.
*
* @{
*/
/**
- * Callback function used by RAIL to request memory.
+ * Loads a static radio configuration.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] config A pointer to a radio configuration.
+ * @return Status code indicating success of the function call.
*
- * @param[in] size The amount of memory in bytes that we need for this packet
- * @return A handle to memory in your storage system.
+ * The configuration passed into this function should be generated for you
+ * and not manually created or edited. By default this function should not be
+ * called in RAIL 2.x and later unless a non-default radio configuration needs
+ * to be applied. In RAIL 2.x and later, the RAIL_ConfigChannels function
+ * applies the default radio configuration automatically.
+ */
+RAIL_Status_t RAIL_ConfigRadio(RAIL_Handle_t railHandle,
+ RAIL_RadioConfig_t config);
+
+/**
+ * Modifies the currently configured fixed frame length in bytes.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] length The expected fixed frame length. A value of 0 is infinite.
+ * A value of RAIL_SETFIXEDLENGTH_INVALID restores the frame's length back to
+ * that length specified by the default frame type configuration.
+ * @return Length configured; The new frame length configured into the hardware
+ * for use. 0 if in infinite mode, or RAIL_SETFIXEDLENGTH_INVALID if not in
+ * fixed length mode or if the frame length has not yet been overridden by a
+ * valid value.
*
- * This is used to allocate memory for receive packets and must be implemented
- * by the application.
+ * Sets the fixed-length configuration for transmit and receive.
+ * Be careful when using this function in receive and transmit as this
+ * function changes the default frame configuration and remains in force until
+ * it is called again with an input value of RAIL_SETFIXEDLENGTH_INVALID.
*/
-void *RAILCb_AllocateMemory(uint32_t size);
+uint16_t RAIL_SetFixedLength(RAIL_Handle_t railHandle, uint16_t length);
+
+/**
+ * Configures the channels supported by this device.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] config A pointer to the channel configuration for your device.
+ * This pointer will be cached in the library so it must be something that
+ * will exist for the runtime of the application. Typically, this should be
+ * what is stored in Flash by the configuration tool.
+ * @param[in] cb Function called whenever a radio configuration change occurs.
+ * @return Returns the first available channel in the configuration.
+ *
+ * When configuring channels on the EFR32, the radio tuner is reconfigured
+ * based on the frequency and channel spacing in the channel configuration.
+ */
+uint16_t RAIL_ConfigChannels(RAIL_Handle_t railHandle,
+ const RAIL_ChannelConfig_t *config,
+ RAIL_RadioConfigChangedCallback_t cb);
+
+/**
+ * Get the active channel config.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return The active channel config.
+ */
+const RAIL_ChannelConfig_t *RAIL_GetActiveChannelConfig(RAIL_Handle_t railHandle);
+
+/**
+ * Get the active channel config entry.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return The active channel config entry.
+ */
+const RAIL_ChannelConfigEntry_t *RAIL_GetActiveChannelConfigEntry(RAIL_Handle_t railHandle);
/**
- * Callback function used by RAIL to free memory.
+ * Checks to see if the channel exists in RAIL.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] channel A channel number to check.
+ * @return Returns RAIL_STATUS_NO_ERROR if channel exists
+ *
+ * Returns RAIL_STATUS_INVALID_PARAMETER if the given channel does not exist
+ * in the channel configuration currently used, and RAIL_STATUS_NO_ERROR if the
+ * channel is valid.
+ */
+RAIL_Status_t RAIL_IsValidChannel(RAIL_Handle_t railHandle,
+ uint16_t channel);
+
+/**
+ * Returns the symbol rate for the current PHY.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return The symbol rate in symbols per second or 0.
*
- * @param[in] handle A handle to a memory block allocated with the
- * RAILCb_AllocateMemory() API above.
+ * The symbol rate is the rate of symbol changes over the air. For non-DSSS
+ * PHYs, this is the same as the baudrate. For DSSS PHYs, it is the baudrate
+ * divided by the length of a chipping sequence. For more information,
+ * see the modem calculator documentation. If the rate is unable to be
+ * calculated, this function will return 0.
+ */
+uint32_t RAIL_GetSymbolRate(RAIL_Handle_t railHandle);
+
+/**
+ * Returns the bit rate for the current PHY.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return The bit rate in bits per second or 0.
+ *
+ * The bit rate is the effective over-the-air data rate. It does not account
+ * for extra spreading for forward error correction, and so on, but
+ * accounts for modulation schemes, DSSS, and other configurations. For more
+ * information, see the modem calculator documentation. If the rate is unable
+ * to be calculated, this function will return 0.
+ */
+uint32_t RAIL_GetBitRate(RAIL_Handle_t railHandle);
+
+/**
+ * Sets the PA capacitor tune value for transmit and receive.
*
- * This is used to free memory that was allocated with the
- * RAILCb_AllocateMemory() function when RAIL is done using it.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] txPaCtuneValue PA Ctune value for TX mode.
+ * @param[in] rxPaCtuneValue PA Ctune value for RX mode.
+ * @return Status code indicating success of the function call.
+ *
+ * Provides the ability to tune the impedance of the transmit
+ * and receive modes by changing the amount of capacitance at
+ * the PA output.
*/
-void RAILCb_FreeMemory(void *handle);
+RAIL_Status_t RAIL_SetPaCTune(RAIL_Handle_t railHandle,
+ uint8_t txPaCtuneValue,
+ uint8_t rxPaCtuneValue);
+
+/** @} */ // end of group Radio_Configuration
+
+/******************************************************************************
+ * Timing Information
+ *****************************************************************************/
+/**
+ * @addtogroup System_Timing System Timing
+ * @brief Functionality related to the RAIL timer and general system time.
+ *
+ * These functions can be used to get information about the current system time
+ * or to manipulate the RAIL timer.
+ *
+ * The system time returned by RAIL_GetTime() is in the same timebase that is
+ * used throughout RAIL. Any callbacks that return a timestamp, such as
+ * rxPacketReceived() callback, will use this same timebase as will any APIs
+ * that accept an absolute time for scheduling their action. Throughout this
+ * documentation the timebase used for this will be referred to as the RAIL
+ * timebase. This is currently a value in microseconds from chip boot time.
+ * This means that it will wrap every 1.19 hours.
+ * (`(2^32 - 1) / (3600 sec/hr * 1000000 us/sec)`).
+ *
+ * The provided timer is hardware backed and interrupt driven. It can be used
+ * for timing any event in your system, but will be especially helpful for
+ * timing protocol based state machines and other systems that interact with
+ * the radio. If you do not want to process the expiration in interrupt
+ * context, leave the timerExpired() callback empty and poll for expiration
+ * with the RAIL_IsTimerExpired() function.
+ *
+ * @{
+ */
/**
- * Called to begin copying received data into the current memory handle.
+ * Gets the current RAIL time.
+ *
+ * @return Returns the RAIL timebase in microseconds. Note that this wraps
+ * after around 1.19 hours since it's stored in a 32bit value.
+ *
+ * Returns the current time in the RAIL timebase (microseconds). It can be
+ * used to compare with packet timestamps or to schedule transmits.
+ */
+uint32_t RAIL_GetTime(void);
+
+/**
+ * Sets the current RAIL time.
+ *
+ * @param[in] time Set the RAIL timebase to this value in microseconds.
+ * @return Status code indicating success of the function call.
*
- * @param[in] handle A handle to the current memory block for packet data.
- * @param[in] offset The offset in bytes from the start of the handle that we
- * need a pointer for.
- * @param[out] available The number of bytes available to be written to this
- * return pointer. If this is zero the receive will terminate. This parameter
- * will default to all spaces allocated to handle contiguous allocators. If your
- * allocator is different you *must* set this appropriately.
- * @return A pointer to the address to write data for this handle.
+ * Sets the current time in the RAIL timebase in microseconds.
+ */
+RAIL_Status_t RAIL_SetTime(uint32_t time);
+
+/**
+ * Schedules a timer to expire using the RAIL timebase.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] time The timer's expiration time in the RAIL timebase.
+ * @param[in] mode Indicates whether the time argument is an absolute
+ * RAIL time or relative to the current RAIL time. Specifying mode
+ * \ref RAIL_TIME_DISABLED is the same as calling RAIL_CancelTimer().
+ * @param[in] cb The callback for RAIL to call when the timer expires.
+ * @return RAIL_STATUS_NO_ERROR on success and
+ * RAIL_STATUS_INVALID_PARAMETER if the timer could not be scheduled.
+ *
+ * Configures a timer to expire after some period in the RAIL timebase.
+ * This timer can be used to implement low level protocol features.
*
- * This function is called before every memory write to a handle so that we can
- * get the actual address this handle references in the system. When we're done
- * writing there will be a corresponding call to RAILCb_EndWriteMemory().
+ * @warning It is an error to attempt to schedule the timer when it is
+ * still running from a previous request -- unless the cb callback is
+ * identical to that used in the previous request, in which case the
+ * timer is rescheduled to the new time. Note that in this case if
+ * the original timer expires as it is being rescheduled, the callback
+ * may or may not occur. It is generally good practice to cancel a
+ * running timer before rescheduling it to minimize such ambiguity.
+ */
+RAIL_Status_t RAIL_SetTimer(RAIL_Handle_t railHandle,
+ uint32_t time,
+ RAIL_TimeMode_t mode,
+ RAIL_TimerCallback_t cb);
+
+/**
+ * Returns the absolute time that the RAIL timer was configured to expire.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return The absolute time that this timer was set to expire.
*
- * @note You must have at least `sizeof(RAIL_RxPacketInfo_t)` contiguous bytes at
- * offset 0 or the appended info will not be written.
+ * It will give the absolute time regardless of the \ref RAIL_TimeMode_t that
+ * was passed into \ref RAIL_SetTimer. Note that this time might be in the
+ * past if the timer already expired. The return value is undefined if the
+ * timer was never set.
*/
-void *RAILCb_BeginWriteMemory(void *handle,
- uint32_t offset,
- uint32_t *available);
+uint32_t RAIL_GetTimer(RAIL_Handle_t railHandle);
+
+/**
+ * Stops the currently scheduled RAIL timer.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return void.
+ *
+ * Cancels the timer. If this function is called before the timer expires,
+ * the cb callback specified in the earlier RAIL_SetTimer() call will never
+ * be called.
+ */
+void RAIL_CancelTimer(RAIL_Handle_t railHandle);
/**
- * Called to complete the write memory transaction.
+ * Checks whether the RAIL timer has expired.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return True if the previously scheduled timer has expired and false
+ * otherwise.
*
- * @param handle The handle to the current memory block we're modifying.
- * @param offset The offset in bytes from the start of the handle that this data
- * was written to.
- * @param size The number of bytes that were written.
+ * Polling via this function can be used as an alternative to the callback.
+ */
+bool RAIL_IsTimerExpired(RAIL_Handle_t railHandle);
+
+/**
+ * Checks whether the RAIL timer is currently running.
*
- * This callback indicates the completeion of a write memory transaction. It
- * can be used to store information about how many bytes were written or
- * anything else needed. Once this is called the pointer returned by
- * RAILCb_BeginWriteMemory() will no longer be assumed to be valid and we will
- * call that function again for any future writes.
+ * @param[in] railHandle A RAIL instance handle.
+ * @return Returns true if the timer is running and false if
+ * the timer has expired or was never set.
*/
-void RAILCb_EndWriteMemory(void *handle, uint32_t offset, uint32_t size);
+bool RAIL_IsTimerRunning(RAIL_Handle_t railHandle);
+
+/**
+ * Initialize RAIL timer synchronization.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] sleepConfig A sleep configuration.
+ *
+ * @return Status code indicating success of the function call.
+ */
+RAIL_Status_t RAIL_ConfigSleep(RAIL_Handle_t railHandle,
+ RAIL_SleepConfig_t sleepConfig);
/**
- * @}
+ * Stop the RAIL timer and prepare RAIL for sleep.
+ *
+ * @param[in] wakeupProcessTime Time in microseconds that the application and
+ * hardware need to recover from sleep state.
+ * @param[out] deepSleepAllowed
+ * true - system can go to deep sleep.
+ * false - system should not go to deep sleep. Deep sleep should be blocked
+ * in this case.
+ *
+ * @return Status code indicating success of the function call.
+ *
+ * @warning The active RAIL configuration must be idle for enabling sleep.
+ */
+RAIL_Status_t RAIL_Sleep(uint16_t wakeupProcessTime, bool *deepSleepAllowed);
+
+/**
+ * Wake RAIL from sleep and restart the RAIL timer.
+ *
+ * @param[in] elapsedTime Add the sleep duration to the RAIL timer
+ * before restarting the RAIL timer.
+ *
+ * @return Status code indicating success of the function call.
+ *
+ * If timer sync was enabled by \ref RAIL_ConfigSleep, synchronize the RAIL
+ * timer using an alternate timer. Otherwise, add elapsedTime to the RAIL
+ * timer.
*/
+RAIL_Status_t RAIL_Wake(uint32_t elapsedTime);
+
+/** @} */ // end of group System_Timing
+
+/******************************************************************************
+ * Events
+ *****************************************************************************/
+/**
+ * @addtogroup Events
+ * @brief APIs related to events
+ * @{
+ */
+
+/**
+ * Configures radio events.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] mask Bitmask containing which events should be modified.
+ * @param[in] events Define which events should trigger \ref RAIL_Config_t::eventsCallback
+ * The full list of available callbacks can be found by looking at the
+ * RAIL_EVENT_* set of defines.
+ * @return Status code indicating success of the function call.
+ *
+ * Sets up which radio interrupts generate a RAIL event. The full list of
+ * options is in \ref RAIL_Events_t.
+ */
+RAIL_Status_t RAIL_ConfigEvents(RAIL_Handle_t railHandle,
+ RAIL_Events_t mask,
+ RAIL_Events_t events);
+
+/** @} */ // end of group Events
/******************************************************************************
* Data Management
*****************************************************************************/
/**
- * @addtogroup Data_Management
+ * @addtogroup Data_Management Data Management
* @brief Data management functions
*
* These functions allow the application to choose how data is presented to the
- * application. There are two methods for RAIL to provide data, in a packet
- * based method leveraging \ref Memory_Management callbacks or in a FIFO based
+ * application. RAIL provides data in a packet-based method or in a FIFO-based
* method which gives the application more granularity and responsibility in
- * managing transmit and receive data.
+ * managing transmit and receive data, and allows packet sizes larger than
+ * the RX or TX FIFO buffers.
*
- * The application can configure RAIL data mangement through RAIL_DataConfig();
- * this function allows the application to specify the type of radio data (\ref
- * RAIL_TxDataSource_t and \ref RAIL_RxDataSource_t) and the method of
- * interacting with this data (\ref RAIL_DataMethod_t). By default, RAIL
- * configures Tx and Rx both with packet data source and packet mode.
+ * The application can configure RAIL data management through
+ * RAIL_ConfigData().
+ * This function allows the application to specify the type of radio data
+ * (\ref RAIL_TxDataSource_t and \ref RAIL_RxDataSource_t) and the method of
+ * interacting with data (\ref RAIL_DataMethod_t). By default, RAIL
+ * configures TX and RX both with packet data source and packet mode.
*
* In packet based data management:
- * - Load transmit data with RAIL_TxDataLoad()
- * - Received data is returned in RAILCb_RxPacketReceived()
* - Packet lengths are determined from the Radio Configurator configuration
- * - \ref Memory_Management callbacks will fire to ask for pointers to store
- * data
+ * or after receive packet completion using RAIL_GetRxPacketInfo().
+ * - Load transmit data with RAIL_WriteTxFifo().
+ * - Received packet data is made available on successful packet completion
+ * via \ref RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_RX_PACKET_RECEIVED
+ * which can then use RAIL_GetRxPacketInfo() and RAIL_GetRxPacketDetails() to
+ * access packet information, and RAIL_PeekRxPacket() to access packet
+ * data.
+ * - Filtered, Aborted, or FrameError received packet data is automatically
+ * dropped without the application needing to worry about consuming it.
+ * The application can choose to not even be bothered with the events
+ * related to such packets: \ref RAIL_EVENT_RX_ADDRESS_FILTERED,
+ * \ref RAIL_EVENT_RX_PACKET_ABORTED, or \ref RAIL_EVENT_RX_FRAME_ERROR.
*
* In FIFO based data management:
- * - Load transmit data with RAIL_WriteTxFifo()
- * - Received data is retrieved through RAIL_ReadRxFifo()
* - Packet Lengths are determined from the Radio Configurator configuration
- * - Set fifo thresholds through RAIL_SetTxFifoThreshold() and
- * RAIL_SetRxFifoThreshold() which fires RAILCb_RxFifoAlmostFull() and
- * RAILCb_TxFifoAlmostEmpty().
- * - Get fifo count information through RAIL_GetRxFifoBytesAvailable()
- * and RAIL_GetTxFifoSpaceAvailable()
- * - Reset fifos with RAIL_ResetFifo()
- * - CRC Error acceptance is on by default
+ * or by application knowledge of packet payload structure.
+ * - Load transmit data with RAIL_WriteTxFifo() with reset set to false.
+ * - Received data can be retrieved prior to packet completion through
+ * RAIL_ReadRxFifo(), and is never dropped on Filtered, Aborted, or
+ * FrameError packets. The application should enable and handle these
+ * events so it can flush any packet data it's already retrieved.
+ * - After packet completion, remaining packet data for Filtered, Aborted,
+ * or FrameError packets can be either flushed automatically by RAIL
+ * or consumed by the application just like a successfully received packet,
+ * as determined from RAIL_GetRxPacketInfo(). RAIL_GetRxPacketDetails()
+ * provides packet detailed information only for successfully received
+ * packets.
+ * - Set the TX FIFO threshold through RAIL_SetTxFifoThreshold(). The
+ * \ref RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY
+ * will occur telling the application to load more TX packet data, if needed
+ * lest a \ref RAIL_EVENT_TX_UNDERFLOW event occurs.
+ * - Set the RX FIFO threshold through RAIL_SetRxFifoThreshold(). The
+ * \ref RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL
+ * will occur telling the application to consume some RX packet data lest a
+ * \ref RAIL_EVENT_RX_FIFO_OVERFLOW event occurs.
+ * - Get RX FIFO count information through
+ * RAIL_GetRxPacketInfo(\ref RAIL_RX_PACKET_HANDLE_NEWEST)
+ * (or RAIL_GetRxFifoBytesAvailable()).
+ * - Get TX FIFO count information through RAIL_GetTxFifoSpaceAvailable().
+ * - Reset RX and/or TX FIFOs with RAIL_ResetFifo().
*
- * Both transmit and receive fifos are the same size; when trying to determine
- * an appropriate threshold, the application can use
- * RAIL_GetTxFifoSpaceAvailable() to query the size of the fifo if it is empty
- * and use that as the size of the receive fifo as well. The transmit fifo is edge
- * based where it only provides an interrupt once when the threshold is
- * crossed. The receive fifo is level based where the interrupt will constantly
- * pend if the threshold is exceeded. This normally means that inside
- * RAILCb_RxFifoAlmostFull(), the application should empty enough of the fifo
- * to go under the threshold. If the application wishes to defer reading the
- * fifo to main, it can disable the receive fifo threshold interrupt via
- * RAIL_DisableRxFifoThreshold(). The application can reenable the interrupt
- * via RAIL_EnableRxFifoThreshold().
+ * When trying to determine an appropriate threshold, the application needs
+ * to know each FIFO's size. The receive FIFO is internal to RAIL and its
+ * size is 512 bytes. The receive FIFO is level-based in that the \ref
+ * RAIL_EVENT_RX_FIFO_ALMOST_FULL event will constantly pend if the threshold
+ * is exceeded. This normally means that inside this event's callback, the
+ * application should
+ * empty enough of the FIFO to go under the threshold. To defer reading the
+ * FIFO to main context, the application can disable or re-enable the receive
+ * FIFO threshold event using RAIL_ConfigEvents() with the mask
+ * \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL.
*
- * In fifo mode, the fifos can store multiple packets. Depending on traffic,
- * RAIL can receive multiple packets into the receive fifo before the
- * application gets around to reading out the received data from the fifo. If
- * appended info is enabled, make sure to read out the appended info with
- * RAIL_ReadRxFifoAppendedInfo() before attempting to read out the next packet.
- * If the application aborts during packet reception, appended info will not be
- * present in the receive fifo. If a frame error occurs in fifo mode, the
- * contents of the receive fifo is unreliable and should be flushed.
+ * The transmit FIFO is specified by the application and its actual size is
+ * the value returned from the most recent call to RAIL_SetTxFifo(),
+ * The transmit FIFO is edge-based in that it only provides the \ref
+ * RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event once when the threshold is crossed
+ * in the emptying direction.
*
- * When calling RAIL_DataConfig() for fifo mode, RAIL will set \ref
- * RAIL_IGNORE_CRC_ERRORS. Otherwise for packet mode, RAIL will set \ref
- * RAIL_IGNORE_NO_ERRORS. It is highly suggested that the application maintains
- * \ref RAIL_IGNORE_CRC_ERRORS in fifo mode if using hardware crc checking.
+ * In FIFO mode, the FIFOs can store multiple packets. Depending on the
+ * traffic, RAIL can receive multiple packets into the receive FIFO before the
+ * application gets around to reading out the received data from the FIFO.
+ * RAIL_ReadRxFifo() won't allow reading beyond a packet boundary so
+ * process packet completion events promptly. Keep in mind that in FIFO mode,
+ * packet data already read from packets that are subsequently aborted,
+ * frameerror, or filtered should be flushed.
*
* While RAIL defaults to packet mode, the application can explicitly
* initialize RAIL for packet mode in the following manner:
@@ -485,20 +623,18 @@
* .rxMethod = PACKET_MODE,
* };
*
- * status = RAIL_DataConfig(&railDataConfig);
+ * status = RAIL_ConfigData(&railDataConfig);
*
- * // Callbacks that occur in Packet Mode
- * void RAILCb_TxPacketSent(RAIL_TxPacketInfo_t *txPacketInfo);
- * void RAILCb_RxPacketReceived(void *rxPacketHandle);
- * void *RAILCb_AllocateMemory(uint32_t size);
- * void RAILCb_FreeMemory(void *handle);
- * void *RAILCb_BeginWriteMemory(void *handle,
- * uint32_t offset,
- * uint32_t *available);
- * void RAILCb_EndWriteMemory(void *handle, uint32_t offset, uint32_t size);
+ * // Events that can occur in Packet Mode:
+ * RAIL_EVENT_TX_PACKET_SENT
+ * RAIL_EVENT_RX_PACKET_RECEIVED
+ * and optionally (packet data automatically dropped):
+ * RAIL_EVENT_RX_ADDRESS_FILTERED
+ * RAIL_EVENT_RX_PACKET_ABORTED
+ * RAIL_EVENT_RX_FRAME_ERROR
* @endcode
*
- * Initializing RAIL for Fifo Mode requires a few more function calls:
+ * Initializing RAIL for FIFO Mode requires a few more function calls:
* @code{.c}
* static const RAIL_DataConfig_t railDataConfig = {
* .txSource = TX_PACKET_DATA,
@@ -507,36 +643,42 @@
* .rxMethod = FIFO_MODE,
* };
*
- * status = RAIL_DataConfig(&railDataConfig);
+ * status = RAIL_ConfigData(&railDataConfig);
*
- * // Get the size of the fifos
- * // The transmit and receive fifos are the same size
+ * // Gets the size of the FIFOs.
+ * // The transmit and receive FIFOs are the same size
* uint16_t fifoSize = RAIL_GetTxFifoSpaceAvailable();
*
- * // Set the transmit and receive fifo thresholds
- * // For this example, set the threshold in the middle of each fifo
+ * // Sets the transmit and receive FIFO thresholds.
+ * // For this example, set the threshold in the middle of each FIFO
* RAIL_SetRxFifoThreshold(fifoSize / 2);
* RAIL_SetTxFifoThreshold(fifoSize / 2);
*
- * //Callbacks that occur in Fifo mode
- * void RAILCb_TxPacketSent(RAIL_TxPacketInfo_t *txPacketInfo);
- * void RAILCb_RxPacketReceived(void *rxPacketHandle);
- * void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable);
- * void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable);
+ * // Events that can occur in FIFO mode:
+ * RAIL_EVENT_TX_FIFO_ALMOST_EMPTY
+ * RAIL_EVENT_TX_UNDERFLOW
+ * RAIL_EVENT_TXACK_UNDERFLOW
+ * RAIL_EVENT_TX_PACKET_SENT
+ * RAIL_EVENT_RX_FIFO_ALMOST_FULL
+ * RAIL_EVENT_RX_FIFO_OVERFLOW
+ * RAIL_EVENT_RX_ADDRESS_FILTERED
+ * RAIL_EVENT_RX_PACKET_ABORTED
+ * RAIL_EVENT_RX_FRAME_ERROR
+ * RAIL_EVENT_RX_PACKET_RECEIVED
* @endcode
*
- * On receive, there are multiple data sources that an application can use that
- * are only compatible with the fifo method of data delivery. All that differs
- * from the fifo mode example above is the RAIL_DataConfig_t::rxSource setting.
+ * On receive, an application can use multiple data sources that
+ * are only compatible with the FIFO method of data delivery. All that differs
+ * from the FIFO mode example above is the RAIL_DataConfig_t::rxSource setting.
* IQ data samples are taken at the hardware's oversample rate and the amount
- * of data can easily overwhelm CPU processing time. The sample rate depends on
- * the chosen PHY as is determined by the data rate as well as the decimation
+ * of data can easily overwhelm the CPU processing time. The sample rate
+ * depends on the chosen PHY, as determined by the data rate and the decimation
* chain. It is <b>not</b> recommended to use the IQ data source with sample
- * rates above 300k samples/second as the CPU might not be able to keep up with
- * the data. Depending on the application and needed CPU bandwidth, slower
+ * rates above 300 k samples/second as the CPU might not be able to keep up
+ * with the data. Depending on the application and needed CPU bandwidth, slower
* data rates may be required.
* @code{.c}
- * // IQ data is provided into the receive fifo
+ * // IQ data is provided into the receive FIFO
* static const RAIL_DataConfig_t railDataConfig = {
* .txSource = TX_PACKET_DATA,
* .rxSource = RX_IQDATA_FILTLSB,
@@ -544,487 +686,368 @@
* .rxMethod = FIFO_MODE,
* };
*
- * // When reading IQ data out of the fifo, it comes in the following format:
+ * // When reading IQ data out of the FIFO, it comes in the following format:
* //------------------------------------
* // I[LSB] | I[MSB] | Q[LSB] | Q[MSB] |
* //------------------------------------
* @endcode
*
* @note \ref RAIL_DataConfig_t.txMethod and \ref RAIL_DataConfig_t.rxMethod
- * must have the same \ref RAIL_DataMethod_t configuration.
+ * must have the same \ref RAIL_DataMethod_t configuration.
*
- * @warning Do not call RAIL fifo functions while in \ref
- * RAIL_DataMethod_t::PACKET_MODE.
+ * @warning Do not call RAIL_ReadRxFifo() function while in
+ * \ref RAIL_DataMethod_t::PACKET_MODE.
* @{
*/
/**
* RAIL data management configuration
*
- * @param[in] dataConfig RAIL data configuration structure
- * @return RAIL Status of configuration
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] dataConfig RAIL data configuration structure.
+ * @return Status code indicating success of the function call.
*
* This function configures how RAIL manages data. The application can
- * configure RAIL to receive data in a packet based or FIFO based format. When
- * configuring tx or rx for fifo mode, this function will reset the configured
- * fifos.
+ * configure RAIL to receive data in a packet-based or FIFO-based format.
+ * FIFO mode is necessary to support packets larger than the radio's
+ * FIFO buffers.
*
- * If \ref RAIL_DataConfig_t.rxMethod is set to \ref
- * RAIL_DataMethod_t.PACKET_MODE, the radio will filter packets with invalid
- * CRCs by default. This is similar to setting the <b>ignoreErrors</b>
- * parameter in RAIL_SetRxTransitions() to \ref RAIL_IGNORE_NO_ERRORS.
+ * With FIFO mode, the application sets appropriate FIFO thresholds via
+ * RAIL_SetTxFifoThreshold() and RAIL_SetRxFifoThreshold(), and then
+ * enables and handles the \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event
+ * callback (to feed more packet data via RAIL_WriteTxFifo() before the
+ * FIFO underflows), and the \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL event
+ * callback (to consume packet data via RAIL_ReadRxFifo() before the
+ * RX FIFO overflows).
+ *
+ * When configuring TX or RX for FIFO mode, this function resets the configured
+ * FIFOs. When configuring TX or RX for Packet mode, this function will reset
+ * the corresponding FIFO thresholds such that they won't trigger the
+ * \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL or \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY
+ * events.
*
- * If \ref RAIL_DataConfig_t.rxMethod is set to \ref
- * RAIL_DataMethod_t.FIFO_MODE, the radio will accept packets with CRCs as
- * 'valid' packets by default. This is meant to treat 'fully received' packets
- * the same way regardless if CRC passes or fails. The application can parse
- * CRC errors via appended info obtained from RAIL_ReadRxFifoAppendedInfo().
- * This is similar to setting the <b>ignoreErrors</b> parameter in
- * RAIL_SetRxTransitions() to \ref RAIL_IGNORE_CRC_ERRORS.
+ * When \ref RAIL_DataConfig_t.rxMethod is set to \ref
+ * RAIL_DataMethod_t.FIFO_MODE, the radio won't drop packet data of
+ * aborted or CRC error packets, but will present it to the application
+ * to deal with accordingly. On completion of such erroneous packets, the
+ * \ref RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_RX_PACKET_ABORTED,
+ * \ref RAIL_EVENT_RX_FRAME_ERROR, or \ref RAIL_EVENT_RX_ADDRESS_FILTERED will
+ * tell the application it can drop any data it read via RAIL_ReadRxFifo() during reception.
+ * For CRC error packets when the \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS
+ * RX option is in effect, the application would check for that from the
+ * \ref RAIL_RxPacketStatus_t obtained by calling RAIL_GetRxPacketInfo().
+ * RAIL will automatically flush any remaining packet data after reporting
+ * one of these packet completion events, or the application can explicitly
+ * flush it by calling RAIL_ReleaseRxPacket().
*
- * In either situation, the application can set <b>ignoreErrors</b> as needed;
- * in fifo mode, appended info will not be present for frame errors. The
- * defaults defined above are the recommended setting.
+ * When \ref RAIL_DataConfig_t.rxMethod is set to \ref
+ * RAIL_DataMethod_t.PACKET_MODE, the radio will drop all packet data
+ * associated with aborted packets including those with CRC errors (unless
+ * configured to ignore CRC errors via the
+ * \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS RX option). The application will
+ * never be bothered to deal with packet data from such packets.
+ *
+ * In either mode, the application can set RX options as needed, and
+ * packet details are not available for aborted packets.
*/
-RAIL_Status_t RAIL_DataConfig(RAIL_DataConfig_t *dataConfig);
-
-/**
- * Write data to the transmit fifo
- *
- * @param[in] dataPtr Application provided pointer to transmit data
- * @param[in] writeLength Number of bytes to write to the transmit fifo
- *
- * @return The number of bytes written to the transmit fifo
- *
- * This function reads data from the provided dataPtr and writes it to the TX
- * Fifo. If the requested writeLength exceeds the current number of bytes open
- * in the transmit fifo, the function will only write until the transmit fifo
- * is full. The function returns the number of bytes written to the transmit
- * fifo.
- *
- * @note This function does not create a critical section but depending on the
- * application a critical section could be appropriate.
- */
-uint16_t RAIL_WriteTxFifo(uint8_t *dataPtr, uint16_t writeLength);
+RAIL_Status_t RAIL_ConfigData(RAIL_Handle_t railHandle,
+ const RAIL_DataConfig_t *dataConfig);
/**
- * Read data from the receive fifo
- *
- * @param[out] dataPtr Application provided pointer to store data
- * @param[in] readLength Number of bytes to read from the fifo
- *
- * @return The number of bytes read from the receive fifo
- *
- * This function reads data from the receive fifo and writes it to the provided
- * dataPtr. If the requested readLength exceeds the current number of bytes in
- * the receive fifo, the function will only read the current amount of bytes
- * available.
+ * Writes data to the transmit FIFO.
*
- * This function does not have a critical section, so either use it only in one
- * context or make sure function calls are protected to prevent buffer
- * corruption.
- */
-uint16_t RAIL_ReadRxFifo(uint8_t *dataPtr, uint16_t readLength);
-
-/**
- * Read appended info from the receive fifo
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] dataPtr Application provided pointer to transmit data
+ * @param[in] writeLength Number of bytes to write to the transmit FIFO
+ * @param[in] reset If true resets TX FIFO before writing the data.
+ * @return The number of bytes written to the transmit FIFO.
*
- * @param[out] appendedInfo Application provided pointer to store RAIL_AppendedInfo_t
- * @return void
- *
- * This function reads appended info from the receive fifo and writes it to the
- * provided pointer; appended info is added to the receive fifo once a packet is
- * received. Using this function while not at the end of a packet can corrupt
- * your buffer by processing receive data as appended info.
+ * This function reads data from the provided dataPtr and writes it to the TX
+ * FIFO. If the requested writeLength exceeds the current number of bytes open
+ * in the transmit FIFO, the function only writes until the transmit FIFO
+ * is full. The function returns the number of bytes written to the transmit
+ * FIFO, and returns zero if railHandle is NULL or if the TX FIFO is full.
*
- * @note The following fields in appended info are not implemented in fifo mode and
- * do not contain valid info:
- * - RAIL_AppendedInfo_t.isAck
- * - RAIL_AppendedInfo_t.lqi
- * - RAIL_AppendedInfo_t.frameCodingStatus (will reflect the last received packet)
- */
-void RAIL_ReadRxFifoAppendedInfo(RAIL_AppendedInfo_t *appendedInfo);
-
-/**
- * Configure the RAIL transmit fifo almost empty threshold
+ * @note It is the protocol's packet configuration, as set up by the radio
+ * configurator or via RAIL_SetFixedLength(), that determines how many
+ * bytes of data are consumed from the TX FIFO for a successful transmit
+ * operation, not the writeLength value passed in. If not enough data has
+ * been put into the TX FIFO, a \ref RAIL_EVENT_TX_UNDERFLOW event will
+ * occur. If too much data, the extra data will either become the first bytes
+ * sent in a subsequent packet, or will be thrown away if the FIFO gets
+ * reset prior to the next transmit. In general, the proper number of
+ * packet bytes to put into the TX FIFO are all payload bytes except for
+ * any CRC bytes which the packet configuration would cause to be sent
+ * automatically.
*
- * @param[in] txThreshold Threshold once fallen under
- * will fire RAILCb_TxFifoAlmostEmpty()
- * @return Configured transmit fifo threshold value
- *
- * This function configures the threshold for the transmit fifo. When the count
- * of the transmit fifo is less than the configured threshold,
- * RAILCb_TxFifoAlmostEmpty() will fire. A value of 0 is invalid and will not
- * change the current configuration.
+ * @note This function does not create a critical section but, depending on the
+ * application, a critical section could be appropriate.
*/
-uint16_t RAIL_SetTxFifoThreshold(uint16_t txThreshold);
-
-/**
- * Configure the RAIL receive fifo almost full threshold
- *
- * @param[in] rxThreshold Threshold once exceeded will fire
- * RAILCb_RxFifoAlmostFull()
- * @return Configured receive fifo threshold value
- *
- * This function configures the threshold for the transmit fifo. When the count
- * of the receive fifo is greater than the configured threshold,
- * RAILCb_RxFifoAlmostFull() will fire. A value of 0xFFFF is invalid and will
- * not change the current configuration. Depending on the hardware the maximum
- * value can vary. If the rxThreshold value exceeds the capability of the
- * hardware, the rx threshold will be configured so that it fires only when the
- * FIFO is one byte away from being full.
- *
- */
-uint16_t RAIL_SetRxFifoThreshold(uint16_t rxThreshold);
+uint16_t RAIL_WriteTxFifo(RAIL_Handle_t railHandle,
+ const uint8_t *dataPtr,
+ uint16_t writeLength,
+ bool reset);
/**
- * Get the RAIL transmit fifo almost empty threshold value
+ * Set the address of the TX FIFO, a circular buffer used for TX data
*
- * @return Configured Tx Threshold value
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in,out] txBufPtr Pointer to a read-write memory location in RAM
+ * used as the TX FIFO. This memory must persist until the next call to
+ * this function.
+ * @param[in] initLength Number of initial bytes already in the TX FIFO.
+ * @param[in] size Desired size of the TX FIFO in bytes.
+ * @return Returns the FIFO size in bytes that has been set.
*
- * Retrieve the configured tx threshold value
- */
-uint16_t RAIL_GetTxFifoThreshold(void);
-
-/**
- * Get the RAIL receive fifo almost full threshold value
+ * This function is used to set the memory location for the TX FIFO. This
+ * function must be called at least once before any transmit operations occur.
*
- * @return Configured Rx Threshold value
+ * The FIFO size can be determined by the return value of this function. The
+ * chosen size is determined based on the available FIFO sizes supported by
+ * the hardware. For more on supported FIFO sizes see chip-specific
+ * documentation, such as \ref efr32_main. The returned FIFO size will be the
+ * closest allowed size less than or equal to the passed in size parameter,
+ * unless the size parameter is smaller than the minimum FIFO size. If the
+ * initLength parameter is larger than the returned size, than the FIFO will be
+ * full up to its size.
*
- * Retrieve the configured rx threshold value
+ * User may write to the custom memory location directly before calling this
+ * function, or use \ref RAIL_WriteTxFifo to write to the memory location after
+ * calling this function. For previously-written memory to be set in the TX
+ * FIFO, user must specify its initLength.
+ *
+ * This function reserves the block of RAM starting at txBufPtr with a length
+ * of the returned FIFO size. That RAM block is used internally as a circular
+ * buffer for the transmit FIFO. The FIFO must be able to hold the entire FIFO
+ * size. The caller must guarantee the custom FIFO remains intact and unchanged
+ * (except via calls to \ref RAIL_WriteTxFifo) until the next call to this
+ * function.
+ *
+ * @note It is the protocol's packet configuration, as set up by the radio
+ * configurator or via RAIL_SetFixedLength(), that determines how many
+ * bytes of data are consumed from the TX FIFO for a successful transmit
+ * operation, not the initLength value passed in. If not enough data has
+ * been put into the TX FIFO, a \ref RAIL_EVENT_TX_UNDERFLOW event will
+ * occur. If too much data, the extra data will either become the first bytes
+ * sent in a subsequent packet, or will be thrown away if the FIFO gets
+ * reset prior to the next transmit. In general, the proper number of
+ * packet bytes to put into the TX FIFO are all payload bytes except for
+ * any CRC bytes which the packet configuration would cause to be sent
+ * automatically.
*/
-uint16_t RAIL_GetRxFifoThreshold(void);
-
-/**
- * Enable the RAIL receive fifo threshold interrupt
- *
- * @return void
- *
- * Enable the RAIL receive fifo threshold interrupt.
- */
-void RAIL_EnableRxFifoThreshold(void);
+uint16_t RAIL_SetTxFifo(RAIL_Handle_t railHandle,
+ uint8_t *txBufPtr,
+ uint16_t initLength,
+ uint16_t size);
/**
- * Disable the RAIL receive fifo threshold interrupt
- *
- * @return void
+ * Reads packet data from RAIL's internal receive FIFO buffer.
+ * This function can be used in any RX mode, though in Packet
+ * mode it can only be used on the oldest unreleased packet whose
+ * RAIL_RxPacketStatus_t is among the RAIL_RX_PACKET_READY_ set.
*
- * Disable the RAIL receive fifo threshold interrupt. This is useful if the
- * application wishes to defer reading the receive fifo into another context.
- */
-void RAIL_DisableRxFifoThreshold(void);
-
-/**
- * Reset the RAIL Fifos
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[out] dataPtr An application-provided pointer to store data.
+ * If NULL, the data is thrown away rather than copied out.
+ * @param[in] readLength A number of packet bytes to read from the FIFO.
+ * @return The number of packet bytes read from the receive FIFO.
*
- * @param[in] txFifo If true, reset the transmit fifo
- * @param[in] rxFifo If true, reset the receive fifo
- * @return void
+ * This function reads packet data from the head of receive FIFO and
+ * writes it to the provided dataPtr. It does not permit reading more
+ * data than is available in the FIFO, nor does it permit reading more
+ * data than remains in the oldest unreleased packet.
*
- * This function can reset each fifo. The application should not reset the Rx
- * Fifo while receiving a frame.
+ * Because this function does not have a critical section, either use it
+ * only in one context or make sure function calls are protected to prevent
+ * buffer corruption.
*/
-//@TODO interrupt protect when clearing; need to check race conditions with hw team
-void RAIL_ResetFifo(bool txFifo, bool rxFifo);
-
-/**
- * Get the number of bytes in the receive fifo
- *
- * @return Number of bytes in the receive fifo
- *
- * Get the number of bytes in the receive fifo
- */
-uint16_t RAIL_GetRxFifoBytesAvailable(void);
+uint16_t RAIL_ReadRxFifo(RAIL_Handle_t railHandle,
+ uint8_t *dataPtr,
+ uint16_t readLength);
/**
- * Get the number of bytes open in the transmit fifo
+ * Configures the RAIL transmit FIFO almost empty threshold.
*
- * @return Number of bytes open in the transmit fifo
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] txThreshold The threshold once fallen under will fire \ref RAIL_Config_t::eventsCallback
+ * with \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY set.
+ * @return Configured transmit FIFO threshold value.
*
- * Get the number of bytes open in the transmit fifo
+ * This function configures the threshold for the transmit FIFO. When the count
+ * of the transmit FIFO is less than the configured threshold, \ref RAIL_Config_t::eventsCallback
+ * will fire with \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY set. A value of
+ * 0 is invalid and will not change the current configuration.
*/
-uint16_t RAIL_GetTxFifoSpaceAvailable(void);
+uint16_t RAIL_SetTxFifoThreshold(RAIL_Handle_t railHandle,
+ uint16_t txThreshold);
/**
- * Callback that fires when the receive fifo exceeds the configured threshold
- * value
+ * Configures the RAIL receive FIFO almost full threshold.
*
- * @param[in] bytesAvailable Number of bytes available in the receive fifo at
- * the time of the callback dispatch
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] rxThreshold The threshold once exceeded will fire \ref RAIL_Config_t::eventsCallback
+ * with \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL set.
+ * @return Configured receive FIFO threshold value.
*
- * @return void
- * @warning You must implement a stub for this in your RAIL application.
+ * This function configures the threshold for the receive FIFO. When the count
+ * of the receive FIFO is greater than the configured threshold,
+ * \ref RAIL_Config_t::eventsCallback will fire with \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL set.
+ * A value of 0xFFFF is invalid and will not change the current configuration.
+ * Depending on the size of the receive FIFO hardware, the maximum value can
+ * vary. If the rxThreshold value exceeds the capability of the hardware, the
+ * RX threshold will be configured so that it fires only when the FIFO is one
+ * byte away from being full.
+ */
+uint16_t RAIL_SetRxFifoThreshold(RAIL_Handle_t railHandle,
+ uint16_t rxThreshold);
+
+/**
+ * Gets the RAIL transmit FIFO almost empty threshold value.
*
- * Callback that fires when the receive fifo exceeds the configured threshold
- * value. Provides the number of bytes available in the receive fifo at the
- * time of the callback dispatch.
+ * @param[in] railHandle A RAIL instance handle.
+ * @return Configured TX Threshold value.
+ *
+ * Retrieves the configured TX threshold value.
*/
-void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable);
+uint16_t RAIL_GetTxFifoThreshold(RAIL_Handle_t railHandle);
/**
- * Callback that fires when the transmit fifo falls under the configured
- * threshold value
+ * Gets the RAIL receive FIFO almost full threshold value.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return Configured RX Threshold value.
*
- * @param[in] spaceAvailable Number of bytes open in the transmit fifo at the
- * time of the callback dispatch
+ * Retrieves the configured RX threshold value.
+ */
+uint16_t RAIL_GetRxFifoThreshold(RAIL_Handle_t railHandle);
+
+/**
+ * Resets the RAIL FIFOs.
*
- * @return void
- * @warning You must implement a stub for this in your RAIL application.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] txFifo If true, reset the transmit FIFO.
+ * @param[in] rxFifo If true, reset the receive FIFO.
+ * @return void.
*
- * Callback that fires when the transmit fifo falls under the configured
- * threshold value. It only fires if a rising edge occurs across this
- * threshold. This callback will not fire on initailization nor after resetting
- * the transmit fifo with RAIL_ResetFifo().
+ * This function can reset each FIFO. The application should not reset the RX
+ * FIFO while receiving a frame.
+ */
+void RAIL_ResetFifo(RAIL_Handle_t railHandle, bool txFifo, bool rxFifo);
+
+/**
+ * Get the number of bytes available in the receive FIFO.
+ * This function should only be used in RX FIFO mode; apps should
+ * probably be using RAIL_GetRxPacketInfo() instead.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return Number of raw bytes in the receive FIFO.
*
- * Provides the number of bytes open in the transmit fifo at the time of the
- * callback dispatch.
+ * @note The number of bytes returned may not just reflect the current
+ * packet's data but could also include raw appended info bytes added
+ * after successful packet reception and bytes from subsequently received
+ * packets.
*/
-void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable);
+uint16_t RAIL_GetRxFifoBytesAvailable(RAIL_Handle_t railHandle);
+
/**
- * @}
+ * Gets the number of bytes open in the transmit FIFO.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return Number of bytes open in the transmit FIFO.
+ *
+ * Gets the number of bytes open in the transmit FIFO.
*/
+uint16_t RAIL_GetTxFifoSpaceAvailable(RAIL_Handle_t railHandle);
+
+/** @} */ // end of group Data_Management
/******************************************************************************
- * Timing Information
+ * State Transitions
*****************************************************************************/
/**
- * @addtogroup System_Timing
- * @brief Functionality related to the RAIL timer and general system time.
- *
- * These functions can be used to get information about the current system time
- * or to manipulate the RAIL timer.
- *
- * The system time returned by RAIL_GetTime() is in the same timebase that is
- * used throughout RAIL. Any callbacks that return a timestamp (like
- * RAILCb_RxPacketReceived()) will use this same timebase as will any APIs that
- * accept an absolute time for scheduling their action. Throughout this
- * documentation the timebase used for this will be referred to as the RAIL
- * timebase. This is currently a value in microseconds from chip boot time. This
- * means that it will wrap every 1.19 hours
- * (`(2^32 - 1) / (3600 sec/hr * 1000000 us/sec)`).
- *
- * The provided timer is hardware backed and interrupt driven. It can be used
- * for timing any event in your system, but will be especially helpful for
- * timing protocol based state machines and other systems that interact with
- * the radio. If you do not want to process the expiration in interrupt context
- * you can leave the RAILCb_TimerExpired() callback empty and poll for
- * expiration with the RAIL_TimerExpired() function.
- *
+ * @addtogroup State_Transitions State Transitions
* @{
*/
/**
- * Get the current RAIL time
- *
- * @return Returns the RAIL timebase in microseconds. Note that this wraps after
- * around 1.19 hours since it's stored in a 32bit value.
+ * Configures RAIL automatic state transitions after RX.
*
- * Return the current time in the RAIL timebase (microseconds). This can be
- * used to compare with packet timestamps or to schedule transmits.
- */
-uint32_t RAIL_GetTime(void);
-
-/**
- * Set the current RAIL time
- *
- * @param[in] time Set the RAIL timebase to this value in microseconds.
- * @return Returns RAIL_STATUS_NO_ERROR on success and
- * RAIL_STATUS_INVALID_STATE if the time could not be set.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] transitions The state transitions to apply after reception.
+ * @return Status code indicating success of the function call.
*
- * Set the current time in the RAIL timebase in microseconds.
+ * This function fails if unsupported transitions are passed in or if the
+ * radio is currently in the RX state. Success can transition to TX, RX, or
+ * IDLE, while error can transition to RX or IDLE.
*/
-RAIL_Status_t RAIL_SetTime(uint32_t time);
-
-/**
- * Set a timer via the RAIL timebase
- *
- * @param[in] time The time to delay for in the RAIL timebase.
- * @param[in] mode The timer mode can be relative to now or an absolute time.
- * @return Returns RAIL_STATUS_NO_ERROR on success and
- * RAIL_STATUS_INVALID_PARAMETER if the timer could not be scheduled.
- *
- * Configure a timer to fire after some period in the RAIL timebase. This timer
- * can be used to implement low level protocol features.
- */
-RAIL_Status_t RAIL_TimerSet(uint32_t time, RAIL_TimeMode_t mode);
+RAIL_Status_t RAIL_SetRxTransitions(RAIL_Handle_t railHandle,
+ const RAIL_StateTransitions_t *transitions);
/**
- * Return the absolute time that the RAIL timer is configured to fire at.
- *
- * @return The absolute time that this timer is set to go off at.
+ * Configures RAIL automatic state transitions after TX.
*
- * This will give the absolute time regardless of the \ref RAIL_TimeMode_t that
- * was passed into \ref RAIL_TimerSet. The return value is undefined if the
- * timer was never set.
- */
-uint32_t RAIL_TimerGet(void);
-
-/**
- * Stop the currently scheduled RAIL timer.
- *
- * @return void
- *
- * Cancels the timer. If this is called before the timer fires, then
- * RAILCb_TimerExpired will never be called.
- */
-void RAIL_TimerCancel(void);
-
-/**
- * Check to see if the RAIL timer has expired
- *
- * @return True if the previously scheduled timer has fired and false otherwise.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] transitions The state transitions to apply after transmission.
+ * @return Status code indicating a success of the function call.
*
- * This is cleared on RAIL_TimerSet() and will be set when the delay expires.
- * This function can be used as an alternative to RAILCb_TimerExpired using
- * polling. If this is the case, implement RAILCb_TimerExpired as a stub.
- */
-bool RAIL_TimerExpired(void);
-
-/**
- * See if the RAIL timer is currently running
- *
- * @return Returns true if the timer is running and false otherwise
- *
- * Will return false if the timer was never set or has expired.
+ * This function fails if unsupported transitions are passed in or if the
+ * radio is currently in the TX state. Success and error can each transition
+ * to RX or IDLE.
*/
-bool RAIL_TimerIsRunning(void);
-
-/**
- * This function is called when the RAIL timer expires
- *
- * @return void
- *
- * You must implement a stub for this in your RAIL application even if you
- * don't use the timer. You can use this callback for low-level protocol
- * features.
- */
-void RAILCb_TimerExpired(void);
+RAIL_Status_t RAIL_SetTxTransitions(RAIL_Handle_t railHandle,
+ const RAIL_StateTransitions_t *transitions);
/**
- * @}
- */
-
-/******************************************************************************
- * Radio Configuration
- *****************************************************************************/
-/**
- * @addtogroup Radio_Configuration
- * @brief Routines for setting up and querying radio configuration information.
+ * Configures RAIL automatic state transition timing.
*
- * All of these routines allow for runtime flexibility in your radio
- * configuration. Some of the parameters, however, are meant to be generated
- * from the radio calculator in Simplicity Studio. The basic code to configure
- * the radio from this calculator output looks like the example below.
- *
- * @code{.c}
- * // Apply the selected RADIO configuration
- * if (RAIL_RadioConfig((void*)configList[0])) {
- * // Error: Could not apply the radio configuration
- * while(1);
- * }
- *
- * // Configure the packet configuration for this PHY
- * RAIL_PacketLengthConfigFrameType(frameTypeConfigList[0]);
- *
- * // Set up the channel configuration for this PHY
- * RAIL_ChannelConfig(channelConfigs[0]);
- * @endcode
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in,out] timings The timings used to configure the RAIL state
+ * machine. This structure is overwritten with the actual times that were
+ * set, if an input timing is invalid.
+ * @return Status code indicating a success of the function call.
*
- * For more information about the types of parameters that can be changed in
- * the other functions and how to use them see their individual documentation.
- *
- * @{
+ * The timings given are close to the actual transition time. However,
+ * a still uncharacterized software overhead occurs. Also, timings are not
+ * always adhered to when using an automatic transition after an error, due to
+ * the cleanup required to recover from the error.
*/
-
-/**
- * Load a static radio configuration
- *
- * @param[in] radioConfig Pointer to a radio configuration array
- * @return A non-zero value on failure and zero on success
- *
- * The radioConfig passed into this function should be generated for you, and
- * not created or edited by hand.
- */
-uint8_t RAIL_RadioConfig(void *radioConfig);
-
-/**
- * Configure the length to use for received packets to be variable based on an
- * implicit length field in payload bytes
- *
- * @param[in] frameType Frame type configuration structure.
- *
- * Currently the frame type passed in only handles packet length decoding. If
- * NULL is passed into this function, it will clear any currently configured
- * frame type settings.
- */
-void RAIL_PacketLengthConfigFrameType(const RAIL_FrameType_t *frameType);
+RAIL_Status_t RAIL_SetStateTiming(RAIL_Handle_t railHandle,
+ RAIL_StateTiming_t *timings);
/**
- * Configure the channels supported by this device
- *
- * @param[in] config A pointer to the channel configuration for your device.
- * This pointer will be cached in the library so it must be something that
- * will exist for the runtime of the application. Typically this should be
- * what is stored in Flash by the configuration tool.
- * @return Returns first available channel in config.
+ * Places the radio into an idle state.
*
- * When configuring channels on the EFR32, the Synth will be reconfigured based
- * on the frequency and channel spacing in config.
-*/
-uint8_t RAIL_ChannelConfig(const RAIL_ChannelConfig_t * config);
-
-/**
- * Check to see if the channel exists in RAIL
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] mode The method for shutting down the radio.
+ * @param[in] wait Whether this function should wait for the radio to reach
+ * idle before returning.
+ * @return void.
*
- * @param[in] channel Channel number to check
- * @return Returns 1 on failure, returns 0 on channel exists
- *
- * Will return 1 if the given channel does not exist in the channel config
- * currently being used, and 0 if the channel is valid.
+ * This function is used to remove the radio from TX and RX states.
*/
-RAIL_Status_t RAIL_ChannelExists(uint8_t channel);
+void RAIL_Idle(RAIL_Handle_t railHandle,
+ RAIL_IdleMode_t mode,
+ bool wait);
/**
- * Return the symbol rate for the current PHY
- *
- * @return The symbol rate in symbols per second
+ * Gets the current radio state.
*
- * The symbol rate is the rate of symbol changes over the air. For non-DSSS
- * PHYs this is the same as the baudrate. For DSSS PHYs it is the baudrate
- * divided by the length of a chipping sequence. For more information on this
- * consult the modem calculator documentation.
- */
-uint32_t RAIL_SymbolRateGet(void);
-
-/**
- * Return the bit rate for the current PHY
- *
- * @return The bit rate in bits per second
+ * @param[in] railHandle A RAIL instance handle.
+ * @return An enumeration for the current radio state.
*
- * The bit rate is the effective over the air data rate. It does not account
- * for extra spreading you may do for things like forward error correction, but
- * will account for modulation schemes, DSSS, and other configurations. For more
- * information on this consult the modem calculator documentation.
+ * Returns the state of the radio as a bitmask containing:
+ * \ref RAIL_RF_STATE_IDLE, \ref RAIL_RF_STATE_RX, \ref RAIL_RF_STATE_TX,
+ * and \ref RAIL_RF_STATE_ACTIVE. \ref RAIL_RF_STATE_IDLE, \ref
+ * RAIL_RF_STATE_RX, and \ref RAIL_RF_STATE_TX bits are mutually exclusive.
+ * The radio can transition through intermediate states,
+ * which are not reported but are instead bucketed into the state
+ * being transitioned into. For example, when the transmitter is in the
+ * process of shutting down, this function will return TX, as if the
+ * shutdown process hadn't started yet.
*/
-uint32_t RAIL_BitRateGet(void);
+RAIL_RadioState_t RAIL_GetRadioState(RAIL_Handle_t railHandle);
-/**
- * Set the PA capacitor tune value for transmit and receive
- *
- * @param[in] txPaCtuneValue PA Ctune value for TX mode
- * @param[in] rxPaCtuneValue PA Ctune value for RX mode
- *
- * @return returns RAIL_STATUS_NO_ERROR if successful
- *
- * Provides the ability to tune the impedance of the transmit
- * and receive modes by changing the amount of capacitance at
- * the PA output.
- */
-RAIL_Status_t RAIL_PaCtuneSet(uint8_t txPaCtuneValue, uint8_t rxPaCtuneValue);
-
-/**
- * @}
- */
+/** @} */ // end of group State_Transitions
/******************************************************************************
* Transmit
@@ -1036,248 +1059,564 @@
*/
/**
- * Set the radio transmit power level
- *
- * @param[in] powerLevel TX Power Level defined in deci dBm (10 * dBm)
- * @return TX Power Level in deci dBm (10 * dBm)
- *
- * Not all values of powerLevel are achievable, but this function will set the
- * power output to be close to the given powerLevel, and return the value that
- * was set as the power.
- */
-int32_t RAIL_TxPowerSet(int32_t powerLevel);
-
-/**
- * Get the radio transmit power level
+ * @addtogroup PA Power Amplifier (PA)
+ * @brief APIs for interacting with one of the on chip PAs.
*
- * @return TX Power Level defined in deci dBm (10 * dBm)
- *
- * This will return what the power output was actually set to, not just the
- * value passed into RAIL_TxPowerSet.
- */
-int32_t RAIL_TxPowerGet(void);
-
-/**
- * Configure which radio transmit actions trigger callbacks
- *
- * @param[in] cbToEnable Define which callbacks to trigger for transmit events.
- * The full list of available callabcks can be found by looking at the
- * RAIL_TX_CONFIG_* set of defines.
- * @return Return 0 for success or an error code
+ * These APIs let you configure the on chip PA to get the appropriate output
+ * power.
*
- * Setup which receive interrupts will generate a RAILCb_TxRadioStatus()
- * callback. The full list of options is any define that starts with
- * RAIL_TX_CONFIG_. Before this function is called, the actions which will
- * generate callbacks are:
- * - \ref RAIL_TX_CONFIG_BUFFER_UNDERFLOW
- * - \ref RAIL_TX_CONFIG_CHANNEL_BUSY
- * - \ref RAIL_TX_CONFIG_TX_ABORTED
- * - \ref RAIL_TX_CONFIG_TX_BLOCKED
- */
-RAIL_Status_t RAIL_TxConfig(uint32_t cbToEnable);
-
-/**
- * Load payload to transmit.
- *
- * @param[in] txData Pointer to a RAIL_TxData_t structure which defines the
- * payload bytes and the number of bytes to write into the transmit buffer.
- * @return Returns 0 on success and an error code on fail.
+ * There a few types of functions that are found here
+ * 1) Configuration functions: These functions set and get configuration
+ * for the PA. In this case, "configuration" refers to a) indicating
+ * which PA to use, b) the voltage supplied by your board to the PA,
+ * and c) the ramp time over which to ramp the PA up to its full
+ * power.
+ * 2) Power-setting functions: These functions consume the actual
+ * values written to the PA registers, and write them appropriately.
+ * These values are referred to as "(raw) power levels". The range of
+ * acceptable values for these functions depends on which PA is
+ * currently active. The higher the power level set, the higher
+ * the dBm power actually output by the chip. However, the mapping
+ * between dBm and these power levels can vary greatly between
+ * modules/boards.
+ * 3) Conversion functions: These functions do the work of converting
+ * between the "power levels" discussed previously and the actual
+ * dBm values output by the chip. Continue reading for more details
+ * on how to handle unit conversion.
*
- * This function will overwrite current TX data held by RAIL, and will return
- * an error if called during transmit operations. RAIL_TxData_t.dataLength
- * defines the number of bytes to load into the transmit buffer from
- * RAIL_TxData_t.dataPtr while the number of bytes transmitted is determined by
- * the packet configuration defined in the radio configuration.
- *
- * @note This function creates a critical section while writing to the transmit
- * buffer.
- */
-uint8_t RAIL_TxDataLoad(RAIL_TxData_t *txData);
-
-/**
- * Non-blocking Transmit
- *
- * @param[in] channel Define the channel to transmit on.
- * @param[in] preTxOp Function to use for any pre-transmit operation (e.g. for
- * scheduled transmit, CSMA, LBT, etc.), or NULL for an immediate transmit.
- * @param[in] preTxOpParams Pointer to the pre-transmit operation's
- * configuration parameters, or NULL if none.
- * @return Returns 0 on successfully initiating the transmit process, or an
- * error code on failure. If successfully initiated, transmit completion
- * or failure will be reported by later callbacks RAILCb_TxPacketSent()
- * (success) or RAILCb_TxRadioStatus() (failure).
+ * The accuracy of the chip output power in dBm will vary from application to
+ * to application. For some protocols or channels the protocol itself or
+ * legal limitations will require applications to know exactly what power
+ * they're transmitting at, in dBm. Other applications will not have
+ * these restrictions, and users will simply find some power level(s)
+ * that fit their criteria for the trade-off between radio range and
+ * power savings, regardless of what dBm power that maps to.
*
- * Begins transmission of the payload previously loaded via RAIL_TxDataLoad().
- * Will begin transmitting after a received packet if currently receiving a
- * packet. Returns error if the radio is active and the channel needs to be
- * changed.
- */
-uint8_t RAIL_TxStart(uint8_t channel,
- RAIL_PreTxOp_t preTxOp,
- void *preTxOpParams);
-
-/**
- * Non-blocking Transmit with options
- *
- * @param[in] channel Define the channel to transmit on.
- * @param[in] options Defines options that apply for this transmit
- * @param[in] preTxOp Function to use for any pre-transmit operation (e.g. for
- * scheduled transmit, CSMA, LBT, etc.), or NULL for an immediate transmit.
- * @param[in] preTxOpParams Pointer to the pre-transmit operation's
- * configuration parameters, or NULL if none.
- * @return Returns 0 on successfully initiating the transmit process, or an
- * error code on failure. If successfully initiated, transmit completion
- * or failure will be reported by later callbacks RAILCb_TxPacketSent()
- * (success) or RAILCb_TxRadioStatus() (failure).
- *
- * This is an extension of RAIL_TxStart where the transmit is modified by the
- * options defined in RAIL_TxOptions_t. If using a pre-tx operation, the
- * transmit options will only be configured if the preTxOp is successful.
- *
- * Begins transmission of the payload previously loaded via RAIL_TxDataLoad().
- * Will begin transmitting after a received packet if currently receiving a
- * packet. Returns error if the radio is active and the channel needs to be
- * changed.
- */
-uint8_t RAIL_TxStartWithOptions(uint8_t channel,
- RAIL_TxOptions_t *options,
- RAIL_PreTxOp_t preTxOp,
- void *preTxOpParams);
-
-/**
- * Interrupt level callback to signify when the packet was sent
- *
- * @param txPacketInfo Information about the packet that was transmitted.
- * @note that this structure is only valid during the timeframe of the
- * callback.
+ * In order to provide a solution that fits all these applications,
+ * Silicon Labs has provided a great deal of flexibility in
+ * \ref RAIL_ConvertRawToDbm and \ref RAIL_ConvertDbmToRaw, the two functions
+ * that do the conversion between the dBm power and the raw power levels.
+ * Those levels of customizability are outlined below
+ * 1) No customizability needed: for a given dBm value, the result
+ * of RAIL_ConvertDbmToRaw provides an appropriate
+ * raw power level that, when written to the registers via
+ * RAIL_SetPowerLevel, causes the chip to actually output at that
+ * dBm power. In this case, no action is needed by the user,
+ * the WEAK versions of the conversion functions can be used,
+ * and the default include paths in pa_conversions_efr32.h can
+ * be used.
+ * 2) The mapping of power level to dBm is not good, but the
+ * level of precision is sufficient: In pa_conversions_efr32.c
+ * the WEAK versions of the conversion functions work by using
+ * 8-segment piecewise linear curves to convert between dBm
+ * and power levels for PA's with hundreds of power levels
+ * and simple mapping tables for use with PA's with only a few
+ * levels. If this method is sufficiently precise, but the mapping
+ * between power levels and dBm is wrong, Silicon Labs recommends
+ * copying pa_curves_efr32.h into a new file, updating the segments
+ * to form a better fit (_DCDC_CURVES or _VBAT_CURVES defines), and
+ * then adding the RAIL_PA_CURVES define to your build with the path
+ * to the new file.
+ * 3) A different level of precision is needed and the fit is bad:
+ * If the piecewise-linear line segment fit is not appropriate for
+ * your solution, the functions in pa_conversions_efr32.c can be
+ * totally rewritten, as long as RAIL_ConvertDbmToRaw and
+ * RAIL_ConvertRawToDbm have the same signatures. It is completely
+ * acceptable to re-write these in a way that makes the
+ * pa_curves_efr32.h and pa_curve_types_efr32.h files referenced in
+ * pa_conversions_efr32.h unnecessary. Those files are needed solely
+ * for the conversion methods that Silicon Labs provides.
+ * 4) dBm values are not necessary: If your application does not require
+ * dBm values at all, Silicon Labs recommends overwriting
+ * RAIL_ConvertDbmToRaw and RAIL_ConvertRawToDbm with smaller functions
+ * (i.e. return 0 or whatever was input). These functions are called
+ * from within the RAIL library, so they can never be deadstripped,
+ * but making them as small as possible is the best way to reduce code
+ * size. From there, you can simply call RAIL_SetTxPower, without
+ * converting from a dBm value. If you never want the library to coerce the
+ * power based on channels, RAIL_ConvertRawToDbm should be overwritten
+ * to always return 0 and RAIL_ConvertDbmToRaw should be overwritten to
+ * always return 255.
*
- * Currently the RAIL_TxPacketInfo_t only contains the time when the packet
- * was transmitted.
- */
-void RAILCb_TxPacketSent(RAIL_TxPacketInfo_t *txPacketInfo);
-
-/**
- * Callback to indicate an error with a transmission
+ * The following is example code on how to initialize your PA
+ * @code{.c}
+ *
+ * #include "pa_conversions_efr32.h"
+ *
+ * // Helper macro to declare all the curve structures used by the Silicon Labs-provided
+ * // conversion functions
+ * RAIL_DECLARE_TX_POWER_VBAT_CURVES(piecewiseSegments, curvesSg, curves24Hp, curves24Lp);
*
- * @param[in] status A bit field that defines what event caused the callback
+ * // Put the variables declared above into the appropriate structure
+ * RAIL_TxPowerCurvesConfig_t txPowerCurvesConfig = { curves24Hp, curvesSg, curves24Lp, piecewiseSegments };
*
- * This interrupt level callback allows the user finer granularity in handling
- * TX radio errors.
+ * // In the Silicon Labs implementation, the user is required to save those curves into
+ * // to be referenced when the conversion functions are called
+ * RAIL_InitTxPowerCurves(&txPowerCurvesConfig);
+ *
+ * // Declare the structure used to configure the PA
+ * RAIL_TxPowerConfig_t txPowerConfig = { RAIL_TX_POWER_MODE_2P4_HP, 3300, 10 };
*
- * Radio Statuses:
- * - \ref RAIL_TX_CONFIG_BUFFER_UNDERFLOW
- * - \ref RAIL_TX_CONFIG_CHANNEL_BUSY
- * - \ref RAIL_TX_CONFIG_TX_ABORTED
- * - \ref RAIL_TX_CONFIG_TX_BLOCKED
- * - \ref RAIL_TX_CONFIG_CHANNEL_CLEAR
- * - \ref RAIL_TX_CONFIG_CCA_RETRY
- * - \ref RAIL_TX_CONFIG_START_CCA
- */
-void RAILCb_TxRadioStatus(uint8_t status);
-
-
-/******************************************************************************
- * Pre-Transmit Operations
- *****************************************************************************/
-/**
- * @addtogroup Pre-Transmit
- * @brief APIs for pre-transmit operations (Scheduling, CSMA, LBT, ...)
+ * // And then init the PA. Here, it is assumed that 'railHandle' is a valid RAIL_Handle_t
+ * // that has already been initialized.
+ * RAIL_ConfigTxPower(railHandle, &txPowerConfig);
+ *
+ * // Pick a dBm power to use: 100 deci-dBm = 10 dBm. See docs on RAIL_TxPower_t
+ * RAIL_TxPower_t power = 100;
+ *
+ * // Get the config written by RAIL_ConfigTxPower to confirm what was actually set
+ * RAIL_GetTxPowerConfig(railHandle, &txPowerConfig);
*
- * There are many operation that you can want to happen before a transmit. In
- * RAIL these are configurable via Pre-Transmit hooks. You are free to use your
- * own custom hooks, but there are several provided hooks to help with common
- * use cases. The provided hooks will use the hardware as efficiently as
- * possible which typically means that they do not introduce any software
- * time overhead.
+ * // RAIL_ConvertDbmToRaw will be the weak version provided by Silicon Labs
+ * // by default, or the customer version, if overwritten.
+ * RAIL_TxPowerLevel_t powerLevel = RAIL_ConvertDbmToRaw(railHandle,
+ * txPowerConfig.mode,
+ * power);
*
- * Here's a simple example of how to use a scheduled transmit to send a packet
- * 1 ms after right now.
+ * // Write the result of the conversion to the PA power registers in terms
+ * // of raw power levels
+ * RAIL_SetTxPower(railHandle, powerLevel);
+ * @endcode
*
- * @code{.c}
- * RAIL_ScheduleTxConfig_t nextPacketTxTime = { 1000, RAIL_TIME_DELAY };
- * txStatus = RAIL_TxStart(channel, &RAIL_ScheduleTx, &nextPacketTxTime);
- * @endcode
+ * @note: all the lines following "RAIL_TxPower_t power = 100;" can be
+ * replaced with the provided utility function, \ref RAIL_SetTxPowerDbm.
+ * However, the full example here was provided for clarity. See the
+ * documentation on \ref RAIL_SetTxPowerDbm for more details.
*
* @{
*/
/**
- * Send a packet on a schedule, instead of immediately
+ * Initialize TxPower Settings
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] config Instance which contains desired initial settings
+ * for the TX amplifier.
+ * @return RAIL_Status_t indicating success or an error.
+ *
+ * These settings include the selection between the multiple TX amplifiers,
+ * voltage supplied to the TX power amplifier, and ramp times. This must
+ * be called before any transmit occurs, or \ref RAIL_SetTxPower is called.
+ * While we recommend always calling this function during initialization,
+ * it can also be called anytime if these settings need to change to adapt
+ * to a different application/protocol. This API will also reset TX Power to
+ * its minimum value, so \ref RAIL_SetTxPower must be called after calling this.
+ *
+ * At times, certain combinations of configurations cannot be achieved.
+ * This API attempts to get as close as possible to the requested settings. The
+ * following "RAIL_Get..." API can be used to determine what values were set.
+ */
+RAIL_Status_t RAIL_ConfigTxPower(RAIL_Handle_t railHandle,
+ const RAIL_TxPowerConfig_t *config);
+
+/**
+ * Get the TX power settings currently used in the amplifier
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[out] config Pointer to memory allocated to hold current TxPower
+ * configuration structure.
+ * @return RAIL_TxPowerConfig_t RAIL status variable indicating whether
+ * or not the get was successful.
*
- * @param[in] params A pointer to the RAIL_ScheduleTxConfig_t
- * structure containing when the transmit should occur.
- * @return - Returns 0 on success and anything else on error.
+ * Note, this API does not return the current TX power - that is separately
+ * managed by the \ref RAIL_GetTxPower/\ref RAIL_SetTxPower API's. This API
+ * should be used to know exactly which values were set as a result of
+ * \ref RAIL_ConfigTxPower.
+ */
+RAIL_Status_t RAIL_GetTxPowerConfig(RAIL_Handle_t railHandle,
+ RAIL_TxPowerConfig_t *config);
+
+/**
+ * Set the TX power in units of raw units (see \ref rail_chip_specific.h for
+ * value ranges).
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] powerLevel Power in chip specific \ref RAIL_TxPowerLevel_t units.
+ * @return RAIL_Status_t indicating success or an error.
+ *
+ * In order to convert between decibels and the integer values that the
+ * registers take, call \ref RAIL_ConvertDbmToRaw. Silicon Labs provides
+ * a weak version of this function which works well with our boards. However
+ * a customer using his/her own custom board will want to characterize
+ * chip operation on that board and override the function to do the conversion
+ * appropriately from the desired dB values to raw integer values.
+ *
+ * Depending on the configuration used in \ref RAIL_ConfigTxPower, not all
+ * power levels are achievable. This API will get as close as possible to
+ * the desired power without exceeding it, and calling \ref RAIL_GetTxPower is
+ * the only way to know the exact value written.
+ *
+ * Calling this function before configuring the PA (i.e. before a successful
+ * call to \ref RAIL_ConfigTxPower) will cause an error to be returned.
+ */
+RAIL_Status_t RAIL_SetTxPower(RAIL_Handle_t railHandle,
+ RAIL_TxPowerLevel_t powerLevel);
+
+/**
+ * Returns the current power setting of the PA.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return The chip specific \ref RAIL_TxPowerLevel_t value of the current
+ * transmit power.
*
- * A RAIL_PreTxOp_t function that schedules the transmit to occur at the
- * specified absolute or relative time within a RAIL_TxStart() transmit
- * operation. If RAIL is receiving a packet at the scheduled time, the transmit
- * will be delayed until after the packet is received. To guarantee the time of
- * the outgoing transmit, only call this function while the radio is idle.
+ * This API returns the raw value that was actually set by \ref RAIL_SetTxPower.
+ * Silicon Labs provides a weak version of \ref RAIL_ConvertRawToDbm that works
+ * with our boards to convert these raw values into actual output dBm values.
+ * However, if a customer is using a custom board, we recommend that he/she re-
+ * characterizes the relationship between raw and decibel values, and overrides
+ * the provided function with one more that more accurately reflects the actual
+ * relationship.
+ *
+ * Calling this function before configuring the PA (i.e. before a successful
+ * call to \ref RAIL_ConfigTxPower) will cause an error to be returned
+ * (RAIL_TX_POWER_LEVEL_INVALID).
+ */
+RAIL_TxPowerLevel_t RAIL_GetTxPower(RAIL_Handle_t railHandle);
+
+/**
+ * Converts raw values written to registers to decibel value (in units of
+ * deci-dBm).
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] mode PA mode for which to do the conversion.
+ * @param[in] powerLevel Raw amplifier register value to be converted to
+ * deci-dBm.
+ * @return raw amplifier values converted to units of deci-dBm.
+ *
+ * A weak version of this function is provided by Silicon Labs that is tuned
+ * to provide accurate values for our boards. If the customer intends to use
+ * a custom board, the relationship between what is written to the Tx amplifier
+ * and the actual output power should be re-characterized and implemented in an
+ * overriding version of \ref RAIL_ConvertRawToDbm. For minimum code size and
+ * best speed use only raw values with the TxPower API and override this
+ * function with a smaller function. In the weak version provided with the RAIL
+ * library, railHandle is only used to indicate to the user from where the
+ * function was called, so it is OK to use either a real protocol handle, or one
+ * of the chip specific ones, such as \ref RAIL_EFR32_HANDLE.
+ *
+ * Although the definitions of this function may change, the signature
+ * must be as declared here.
*/
-uint8_t RAIL_ScheduleTx(void *params);
+RAIL_TxPower_t RAIL_ConvertRawToDbm(RAIL_Handle_t railHandle,
+ RAIL_TxPowerMode_t mode,
+ RAIL_TxPowerLevel_t powerLevel);
+
+/**
+ * Converts the desired decibel value (in units of deci-dBm)
+ * to raw integer values used by the TX amplifier registers.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] mode PA mode for which to do the conversion.
+ * @param[in] power Desired dBm values in units of deci-dBm.
+ * @return deci-dBm value converted to a raw
+ * integer value that can be used directly with \ref RAIL_SetTxPower.
+ *
+ * A weak version of this function is provided by Silicon Labs that is tuned
+ * to provide accurate values for our boards. If the customer intends to use
+ * a custom board, the relationship between what is written to the TX amplifier
+ * and the actual output power should be characterized and implemented in an
+ * overriding version of \ref RAIL_ConvertDbmToRaw. For minimum code size and
+ * best speed use only raw values with the TxPower API and override this
+ * function with a smaller function. In the weak version provided with the RAIL
+ * library, railHandle is only used to indicate to the user from where the
+ * function was called, so it is OK to use either a real protocol handle, or one
+ * of the chip specific ones, such as \ref RAIL_EFR32_HANDLE.
+ *
+ * Although the definitions of this function may change, the signature
+ * must be as declared here.
+ *
+ * @note This function is called from within the RAIL library for
+ * comparison between channel limitations and current power. It will
+ * throw an assert if you haven't called RAIL_InitTxPowerCurves
+ * which initializes the mappings between raw power levels and
+ * actual dBm powers. To avoid this assert, ensure that the
+ * maxPower of all channel config entries is \ref RAIL_TX_POWER_MAX
+ * or above, or override this function to always return 255.
+ */
+RAIL_TxPowerLevel_t RAIL_ConvertDbmToRaw(RAIL_Handle_t railHandle,
+ RAIL_TxPowerMode_t mode,
+ RAIL_TxPower_t power);
+
+/** @} */ // end of group PA
/**
- * Use CSMA instead of ignoring current usage of the channel
+ * Sets the TX power in terms of deci-dBm instead of raw power level.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] power Desired deci-dBm power to be set.
+ * @return RAIL Status variable indicate whether setting the
+ * power was successful.
+ *
+ * This is a utility function crafted for user convenience. Normally, to set TX
+ * power in dBm, the user would have to do the following:
*
- * @param[in] params A pointer to the RAIL_CsmaConfig_t structure containing
- * the CSMA parameters to use.
- * @return - Returns 0 on success and anything else on error.
+ * @code{.c}
+ * RAIL_TxPower_t power = 100; // 100 deci-dBm, 10 dBm
+ * RAIL_TxPowerConfig_t txPowerConfig;
+ * RAIL_GetTxPowerConfig(railHandle, &txPowerConfig);
+ * // RAIL_ConvertDbmToRaw will be the weak version provided by Silicon Labs
+ * // by default, or the customer version, if overwritten.
+ * RAIL_TxPowerLevel_t powerLevel = RAIL_ConvertDbmToRaw(railHandle,
+ * txPowerConfig.mode,
+ * power);
+ * RAIL_SetTxPower(railHandle, powerLevel);
+ * @endcode
+ *
+ * This function wraps all those calls in a single function with power passed in
+ * as a parameter.
+ */
+RAIL_Status_t RAIL_SetTxPowerDbm(RAIL_Handle_t railHandle,
+ RAIL_TxPower_t power);
+
+/**
+ * Gets the TX power in terms of deci-dBm instead of raw power level.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return The current output power in deci-dBm
+ *
+ * This is a utility function crafted for user convenience. Normally, to get TX
+ * power in dBm, the user would have to do the following:
*
- * A RAIL_PreTxOp_t function that performs the CSMA algorithm when specified
- * within a RAIL_TxStart() transmit operation. Packets can be received during
- * CSMA backoff periods if receive is active throughout the CSMA process. This
- * will happen either by starting the CSMA process while receive is already
- * active, or if the ccaBackoff time in the RAIL_CsmaConfig_t is less than the
- * idleToRx time (set by RAIL_SetStateTimings). If the ccaBackoff time is
- * greater than the idleToRx time, then receive will only be active during the
- * clear channel assessments.
+ * @code{.c}
+ * RAIL_TxPowerLevel_t powerLevel = RAIL_GetTxPower(railHandle);
+ * RAIL_TxPowerConfig_t txPowerConfig;
+ * RAIL_GetTxPowerConfig(railHandle, &txPowerConfig);
+ * // RAIL_ConvertRawToDbm will be the weak version provided by Silicon Labs
+ * // by default, or the customer version, if overwritten.
+ * RAIL_TxPower_t power = RAIL_ConvertRawToDbm(railHandle,
+ * txPowerConfig.mode,
+ * power);
+ * return power;
+ * @endcode
+ *
+ * This function wraps all those calls in a single function with power returned
+ * as the result.
*/
+RAIL_TxPower_t RAIL_GetTxPowerDbm(RAIL_Handle_t railHandle);
-uint8_t RAIL_CcaCsma(void *params);
+/**
+ * Start a non-blocking transmit
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] channel Define the channel to transmit on.
+ * @param[in] options TX options to be applied to this transmit only.
+ * @param[in] schedulerInfo Information to allow the radio scheduler to place
+ * this transmit appropriately. This is only used in multiprotocol version of
+ * RAIL and may be set to NULL in all other versions.
+ * @return Status code indicating success of the function call. If successfully
+ * initiated, transmit completion or failure will be reported by a later
+ * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t.
+ *
+ * Will begin transmission of the payload previously loaded via
+ * \ref RAIL_WriteTxFifo() immediately, or right after a packet currently being
+ * received is completed.
+ *
+ * Returns an error if a previous transmit is still in progress.
+ * If changing channels, any ongoing packet reception is aborted.
+ *
+ * In multiprotocol you must ensure that you properly yield the radio after this
+ * operation completes. See \ref rail_radio_scheduler_yield for more details.
+ */
+RAIL_Status_t RAIL_StartTx(RAIL_Handle_t railHandle,
+ uint16_t channel,
+ RAIL_TxOptions_t options,
+ const RAIL_SchedulerInfo_t *schedulerInfo);
/**
- * Listen to the channel before sending a message
+ * Send a packet on a schedule, instead of immediately
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] channel Define the channel to transmit on.
+ * @param[in] options TX options to be applied to this transmit only.
+ * @param[in] config A pointer to the \ref RAIL_ScheduleTxConfig_t
+ * structure containing when the transmit should occur.
+ * @param[in] schedulerInfo Information to allow the radio scheduler to place
+ * this transmit appropriately. This is only used in multiprotocol version of
+ * RAIL and may be set to NULL in all other versions.
+ * @return Status code indicating success of the function call. If successfully
+ * initiated, a transmit completion or failure will be reported by a later
+ * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t.
+ *
+ * Will begin transmission of the payload previously loaded via
+ * \ref RAIL_WriteTxFifo() at the scheduled time.
+ * The time (in microseconds) as well as whether that time is absolute or
+ * relative, is specified using the \ref RAIL_ScheduleTxConfig_t structure.
+ * Also specified in this structure is what to do if a scheduled transmit
+ * fires in the midst of receiving a packet.
+ *
+ * Returns an error if a previous transmit is still in progress.
+ * If changing channels, any ongoing packet reception is aborted.
*
- * @param[in] params A pointer to the RAIL_LbtConfig_t structure containing
- * the LBT parameters to use.
- * @return Returns 0 on success and anything else on error.
+ * In multiprotocol you must ensure that you properly yield the radio after this
+ * operation completes. See \ref rail_radio_scheduler_yield for more details.
+ */
+RAIL_Status_t RAIL_StartScheduledTx(RAIL_Handle_t railHandle,
+ uint16_t channel,
+ RAIL_TxOptions_t options,
+ const RAIL_ScheduleTxConfig_t *config,
+ const RAIL_SchedulerInfo_t *schedulerInfo);
+
+/**
+ * Start a non-blocking Transmit using CSMA
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] channel Define the channel to transmit on.
+ * @param[in] options TX options to be applied to this transmit only.
+ * @param[in] csmaConfig A pointer to the RAIL_CsmaConfig_t structure
+ * describing the CSMA parameters to use for this transmit.
+ * @param[in] schedulerInfo Information to allow the radio scheduler to place
+ * this transmit appropriately. This is only used in multiprotocol version of
+ * RAIL and may be set to NULL in all other versions.
+ * @return Status code indicating success of the function call. If successfully
+ * initiated, a transmit completion or failure will be reported by a later
+ * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t.
*
- * A RAIL_PreTxOp_t function that performs the LBT algorithm when specified
- * within a RAIL_TxStart() transmit operation. Packets can be received during
- * CSMA backoff periods if receive is active throughout the LBT process. This
- * will happen either by starting the LBT process while receive is already
- * active, or if the lbtBackoff time in the RAIL_LbtConfig_t is less than the
- * idleToRx time (set by RAIL_SetStateTimings). If the lbtBackoff time is
- * greater than the idleToRx time, then receive will only be active during the
- * clear channel assessments.
+ * First performs the Carrier Sense Multiple Access (CSMA) algorithm and if
+ * the channel is deemed clear (RSSI below the specified threshold) it will
+ * commence transmission of the payload previously loaded via
+ * RAIL_WriteTxFifo().
+ * Packets can be received during CSMA backoff periods if receive is active
+ * throughout the CSMA process. This will happen either by starting the CSMA
+ * process while receive is already active, or if the csmaBackoff time in
+ * the \ref RAIL_CsmaConfig_t is less than the idleToRx time (set by
+ * RAIL_SetStateTiming()). If the csmaBackoff time is greater than the
+ * idleToRx time, then receive will only be active during CSMA's clear channel
+ * assessments.
+ *
+ * If the CSMA algorithm deems the channel busy, the \ref RAIL_Config_t::eventsCallback
+ * occurs with \ref RAIL_EVENT_TX_CHANNEL_BUSY, and the contents
+ * of the TX FIFO remain intact, untouched.
+ *
+ * Returns an error if a previous transmit is still in progress.
+ * If changing channels, any ongoing packet reception is aborted.
+ *
+ * In multiprotocol you must ensure that you properly yield the radio after this
+ * operation completes. See \ref rail_radio_scheduler_yield for more details.
*/
-uint8_t RAIL_CcaLbt(void *params);
+RAIL_Status_t RAIL_StartCcaCsmaTx(RAIL_Handle_t railHandle,
+ uint16_t channel,
+ RAIL_TxOptions_t options,
+ const RAIL_CsmaConfig_t *csmaConfig,
+ const RAIL_SchedulerInfo_t *schedulerInfo);
+
+/**
+ * Start a non-blocking Transmit using LBT
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] channel Define the channel to transmit on.
+ * @param[in] options TX options to be applied to this transmit only.
+ * @param[in] lbtConfig A pointer to the RAIL_LbtConfig_t structure
+ * describing the LBT parameters to use for this transmit.
+ * @param[in] schedulerInfo Information to allow the radio scheduler to place
+ * this transmit appropriately. This is only used in multiprotocol version of
+ * RAIL and may be set to NULL in all other versions.
+ * @return Status code indicating success of the function call. If successfully
+ * initiated, a transmit completion or failure will be reported by a later
+ * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t.
+ *
+ * First performs the Listen Before Talk (LBT) algorithm and if the channel
+ * is deemed clear (RSSI below the specified threshold) it will commence
+ * transmission of the payload previously loaded via RAIL_WriteTxFifo().
+ * Packets can be received during LBT backoff periods if receive is active
+ * throughout the LBT process. This will happen either by starting the LBT
+ * process while receive is already active, or if the lbtBackoff time in
+ * the \ref RAIL_LbtConfig_t is less than the idleToRx time (set by
+ * RAIL_SetStateTiming()). If the lbtBackoff time is greater than the
+ * idleToRx time, then receive will only be active during LBT's clear channel
+ * assessments.
+ *
+ * If the LBT algorithm deems the channel busy, the \ref RAIL_Config_t::eventsCallback occurs with
+ * \ref RAIL_EVENT_TX_CHANNEL_BUSY, and the contents
+ * of the TX FIFO remain intact, untouched.
+ *
+ * Returns an error if a previous transmit is still in progress.
+ * If changing channels, any ongoing packet reception is aborted.
+ *
+ * In multiprotocol you must ensure that you properly yield the radio after this
+ * operation completes. See \ref rail_radio_scheduler_yield for more details.
+ */
+RAIL_Status_t RAIL_StartCcaLbtTx(RAIL_Handle_t railHandle,
+ uint16_t channel,
+ RAIL_TxOptions_t options,
+ const RAIL_LbtConfig_t *lbtConfig,
+ const RAIL_SchedulerInfo_t *schedulerInfo);
/**
* Sets the CCA threshold in dBm
*
- * @param[in] ccaThresholdDbm CCA threshold in dBm.
- * @return \ref RAIL_STATUS_NO_ERROR on success.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] ccaThresholdDbm The CCA threshold in dBm.
+ * @return Status code indicating success of the function call.
*
- * A RAIL_PreTxOp_t function will normally set CCA threshold, assuming it is
- * enabled either in LBT or CSMA mode. Unlike RAIL_CcaCsma and RAIL_CcaLbt,
- * which are called as RAIL_PreTxOp_t functions, this function only modifies
- * CCA threshold. A possible usecase for this function is to set CCA threshold
- * to invalid RSSI of -128 which disables transmission by canceling
- * the current CCA check.
- *
+ * Unlike RAIL_StartCcaCsmaTx() or RAIL_StartCcaLbtTx(), which can cause a
+ * transmit, this function only modifies the CCA threshold. A possible
+ * use case for this function is to set the CCA threshold to invalid RSSI
+ * of -128 which blocks transmission by preventing clear channel assessments
+ * from succeeding.
*/
-RAIL_Status_t RAIL_SetCcaThreshold(int8_t ccaThresholdDbm);
+RAIL_Status_t RAIL_SetCcaThreshold(RAIL_Handle_t railHandle,
+ int8_t ccaThresholdDbm);
/**
- * end of group Pre-Transmit
- * @}
+ * Gets detailed information about the last packet transmitted.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in,out] pPacketDetails An application-provided pointer to store
+ * RAIL_TxPacketDetails_t corresponding to the transmit event.
+ * The isAck and timeSent fields totalPacketBytes and timePosition
+ * must be initialized prior to each call:
+ * - isAck true to obtain details about the most recent ACK transmit,
+ * false to obtain details about the most recent app-initiated transmit.
+ * - totalPacketBytes with the total number of bytes of the transmitted
+ * packet for RAIL to use when calculating the specified timestamp.
+ * This should account for all bytes sent over the air after the
+ * Preamble and Sync word(s), including CRC bytes.
+ * - timePosition with a \ref RAIL_PacketTimePosition_t value specifying
+ * the packet position to put in the timeSent field on return.
+ * This field will also be updated with the actual position corresponding
+ * to the timeSent value filled in.
+ * @return \ref RAIL_STATUS_NO_ERROR if pPacketDetails was filled in,
+ * or an appropriate error code otherwise.
+ *
+ * This function can only be called from callback context for either
+ * \ref RAIL_EVENT_TX_PACKET_SENT or \ref RAIL_EVENT_TXACK_PACKET_SENT
+ * events.
*/
+RAIL_Status_t RAIL_GetTxPacketDetails(RAIL_Handle_t railHandle,
+ RAIL_TxPacketDetails_t *pPacketDetails);
+/**
+ * Prevent the radio from starting a transmit.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] enable Enable/Disable TX hold off.
+ * @return void.
+ *
+ * Enable TX hold off to prevent the radio from starting any transmits.
+ * Disable TX hold off to allow the radio to transmit again.
+ * Attempting to transmit with the TX hold off enabled will result in
+ * \ref RAIL_EVENT_TX_BLOCKED and/or \ref RAIL_EVENT_TXACK_BLOCKED
+ * events.
+ *
+ * @note This function does not affect a transmit that has already started.
+ * To stop an already-started transmission, use RAIL_Idle() with
+ * \ref RAIL_IDLE_ABORT.
+ */
+void RAIL_EnableTxHoldOff(RAIL_Handle_t railHandle, bool enable);
/**
- * end of group Transmit
- * @}
+ * Check whether or not TX hold off is enabled.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return Returns true if TX hold off is enabled, false otherwise.
+ *
+ * TX hold off can be enabled/disabled using \ref RAIL_EnableTxHoldOff.
+ * Attempting to transmit with the TX hold off enabled will block the
+ * transmission and result in \ref RAIL_EVENT_TX_BLOCKED
+ * and/or \ref RAIL_EVENT_TXACK_BLOCKED events.
*/
+bool RAIL_IsTxHoldOffEnabled(RAIL_Handle_t railHandle);
+
+/** @} */ // end of group Transmit
/******************************************************************************
* Receive
@@ -1289,221 +1628,279 @@
*/
/**
- * Configure radio receive actions
+ * Configures receive options.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] mask A bitmask containing which options should be modified.
+ * @param[in] options A bitmask containing desired configuration settings.
+ * Bit positions for each option are found in the \ref RAIL_RxOptions_t.
+ * @return Status code indicating success of the function call.
*
- * @param[in] cbToEnable Define which callbacks to trigger for receive events.
- * The full list of available callabcks can be found by looking at the
- * RAIL_RX_CONFIG_* set of defines.
- * @param[in] appendedInfoEnable Enable/Disable appended info (not implemented)
- * @return Return 0 for success or an error code
+ * Configures the radio receive flow based on the list of available options.
+ * Only the options indicated by the mask parameter will be affected. Pass
+ * \ref RAIL_RX_OPTIONS_ALL to set all parameters.
+ * The previous settings may affect the current frame if a packet is
+ * received during this configuration.
+ */
+RAIL_Status_t RAIL_ConfigRxOptions(RAIL_Handle_t railHandle,
+ RAIL_RxOptions_t mask,
+ RAIL_RxOptions_t options);
+
+/**
+ * Start the receiver on a specific channel.
*
- * Setup which receive interrupts will generate a RAILCb_RxRadioStatus()
- * callback. The full list of options is any define that starts with
- * RAIL_RX_CONFIG_.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] channel The channel to listen on.
+ * @param[in] schedulerInfo Information to allow the radio scheduler to place
+ * this receive appropriately. This is only used in multiprotocol version of
+ * RAIL and may be set to NULL in all other versions.
+ * @return Status code indicating success of the function call.
+ *
+ * This is a non-blocking function. Whenever a packet is received \ref RAIL_Config_t::eventsCallback
+ * will fire with \ref RAIL_EVENT_RX_PACKET_RECEIVED set. If you call
+ * this while not idle but with a different channel we will abort any ongoing
+ * receive or transmit operation.
*/
-uint8_t RAIL_RxConfig(uint32_t cbToEnable, bool appendedInfoEnable);
+RAIL_Status_t RAIL_StartRx(RAIL_Handle_t railHandle,
+ uint16_t channel,
+ const RAIL_SchedulerInfo_t *schedulerInfo);
/**
- * Configure receive options
+ * Schedules a receive window for some future time.
*
- * @param[in] options Bitfield of options which affect recieve. The available
- * options begin with RAIL_RX_OPTION.
- * @return Return 0 for success or an error code
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] channel A channel to listen on.
+ * @param[in] cfg The configuration structure to define the receive window.
+ * @param[in] schedulerInfo Information to allow the radio scheduler to place
+ * this receive appropriately. This is only used in multiprotocol version of
+ * RAIL and may be set to NULL in all other versions.
+ * @return Status code indicating success of the function call.
*
- * Configure the radio receive flow, based on the list of available options.
- * This will fail with RAIL_STATUS_INVALID_STATE if a packet is being received
- * during this configuration.
+ * This API immediately changes the channel and schedules receive to start
+ * at the specified time and end at the given end time. If you do not specify
+ * an end time, you may call this API later with an end time as long as you set
+ * the start time to disabled. You can also terminate the receive
+ * operation immediately using the RAIL_Idle() function. Note that relative
+ * end times are always relative to the start unless no start time is
+ * specified. If changing channels, aborts any ongoing packet transmission or
+ * reception.
+ *
+ * In multiprotocol you must ensure that you properly yield the radio after this
+ * call. See \ref rail_radio_scheduler_yield for more details.
*/
-RAIL_Status_t RAIL_SetRxOptions(uint32_t options);
+RAIL_Status_t RAIL_ScheduleRx(RAIL_Handle_t railHandle,
+ uint16_t channel,
+ const RAIL_ScheduleRxConfig_t *cfg,
+ const RAIL_SchedulerInfo_t *schedulerInfo);
/**
- * Listen on a channel for a packet
- *
- * @param[in] channel Channel to listen on
- * @return Return 0 for success or an error code
+ * Get basic information about a pending or received packet.
+ * This function can be used in any RX mode; it does not free up any
+ * internal resources.
*
- * This is a non-blocking function. RAILCb_RxPacketReceived() will be called
- * when a packet has been received. Returns an error if currently transmitting
- * or receiving.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] packetHandle A packet handle for the unreleased packet as
+ * returned from a previous call, or sentinel values
+ * \ref RAIL_RX_PACKET_HANDLE_OLDEST or \ref RAIL_RX_PACKET_HANDLE_NEWEST.
+ * @param[out] pPacketInfo An application-provided pointer to store
+ * \ref RAIL_RxPacketInfo_t for the requested packet.
+ * @return The packet handle for the requested packet:
+ * if packetHandle was one of the sentinel values, returns the actual
+ * packet handle for that packet, otherwise returns packetHandle.
+ * It may return \ref RAIL_RX_PACKET_HANDLE_INVALID to indicate an error.
*/
-uint8_t RAIL_RxStart(uint8_t channel);
+RAIL_RxPacketHandle_t RAIL_GetRxPacketInfo(RAIL_Handle_t railHandle,
+ RAIL_RxPacketHandle_t packetHandle,
+ RAIL_RxPacketInfo_t *pPacketInfo);
+
+/**
+ * Get detailed information about a ready packet received (one whose
+ * \ref RAIL_RxPacketStatus_t is among the RAIL_RX_PACKET_READY_ set).
+ * This function can be used in any RX mode; it does not free up any
+ * internal resources.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] packetHandle A packet handle for the unreleased packet as
+ * returned from a previous call to RAIL_GetRxPacketInfo() or
+ * RAIL_HoldRxPacket(), or sentinel values \ref RAIL_RX_PACKET_HANDLE_OLDEST
+ * or \ref RAIL_RX_PACKET_HANDLE_NEWEST.
+ * @param[in,out] pPacketDetails An application-provided pointer to store
+ * \ref RAIL_RxPacketDetails_t for the requested packet.
+ * The timeReceived fields totalPacketBytes and timePosition must be
+ * initialized prior to each call:
+ * - totalPacketBytes with the total number of bytes of the received
+ * packet for RAIL to use when calculating the specified timestamp.
+ * This should account for all bytes received over the air after the
+ * Preamble and Sync word(s), including CRC bytes.
+ * - timePosition with a \ref RAIL_PacketTimePosition_t value specifying
+ * the packet position to put in the timeReceived field on return.
+ * This field will also be updated with the actual position corresponding
+ * to the timeReceived value filled in.
+ * @return \ref RAIL_STATUS_NO_ERROR if pPacketDetails was filled in,
+ * or an appropriate error code otherwise.
+ */
+RAIL_Status_t RAIL_GetRxPacketDetails(RAIL_Handle_t railHandle,
+ RAIL_RxPacketHandle_t packetHandle,
+ RAIL_RxPacketDetails_t *pPacketDetails);
/**
- * Schedule a receive window for some time in the future.
- *
- * @param[in] channel Channel to listen on
- * @param[in] cfg The configuation struct to define the receive window.
- * @return Return 0 on success or an error code
+ * Place a temporary hold on this packet's data and information resources
+ * within RAIL.
+ * This shall only be called from within RAIL callback context.
+ * This function can be used in any RX mode.
*
- * This API will immediately change your channel and schedule receive to start
- * at the specified time and end at the given end time. If you do not specify an
- * end time then you may call this API later with an end time as long as you set
- * the start time to disabled. You can also terminate the whole receive
- * operation immediately using the RAIL_RfIdle() function. Note that relative
- * end times are always relative to the start unless there is no start time
- * specified.
+ * Normally when RAIL issues its callback indicating a packet is ready
+ * or aborted, it expects the application's callback to retrieve and
+ * copy (or discard) the packet's information and data, and will free up
+ * its internal packet data after the callback returns. This function
+ * tells RAIL to hold onto those resources after the callback returns in
+ * case the application wants to defer processing the packet to a later
+ * time, e.g. outside of callback context.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return The packet handle for the packet associated with the callback,
+ * or \ref RAIL_RX_PACKET_HANDLE_INVALID if no such packet yet exists.
*/
-uint8_t RAIL_ScheduleRx(uint8_t channel, RAIL_ScheduleRxConfig_t *cfg);
+RAIL_RxPacketHandle_t RAIL_HoldRxPacket(RAIL_Handle_t railHandle);
/**
- * Return the current raw RSSI
- *
- * @return Return \ref RAIL_RSSI_INVALID if the receiver is disabled and we are
- * unable to get an RSSI value, otherwise, return the RSSI in quarter dBm,
- * dbm*4.
+ * Copies 'len' bytes of packet data starting from 'offset' from the
+ * receive FIFO. Those bytes remain valid for re-peeking.
*
- * Get the current RSSI value. This value represents the current energy of the
- * channel, so it can change rapidly, and will be low if there is no RF energy
- * in your current channel. The function from the value reported to dBm is an
- * offset dependent on the PHY and the PCB layout. Users should characterize the
- * RSSI received on their hardware and apply an offset in the application to
- * account for board and PHY parameters.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] packetHandle A packet handle as returned from a previous
+ * RAIL_GetRxPacketInfo() or RAIL_HoldRxPacket() call, or
+ * sentinel values \ref RAIL_RX_PACKET_HANDLE_OLDEST
+ * or \ref RAIL_RX_PACKET_HANDLE_NEWEST.
+ * @param[out] pDst A pointer to the location where the received bytes will
+ * be copied. If NULL, no copying occurs.
+ * @param[in] len A number of packet data bytes to copy.
+ * @param[in] offset A byte offset within remaining packet data from which
+ * to copy.
+ * @return Number of packet bytes copied.
+ *
+ * @note Peek does not permit peeking beyond the requested packet's
+ * available packet data, nor peeking into already-consumed data read by
+ * RAIL_ReadRxFifo(). len and offset are relative to the remaining data
+ * available in the packet, if any was already consumed by RAIL_ReadRxFifo().
*/
-int16_t RAIL_RxGetRSSI(void);
+uint16_t RAIL_PeekRxPacket(RAIL_Handle_t railHandle,
+ RAIL_RxPacketHandle_t packetHandle,
+ uint8_t *pDst,
+ uint16_t len,
+ uint16_t offset);
/**
- * Compute the average RSSI over a specified time in us
- *
- * @param[in] averageTimeUs Averaging time in microseconds.
- * @return Return \ref RAIL_RSSI_INVALID if the receiver is disabled and we are
- * unable to get an RSSI value, otherwise, return the RSSI in quarter dBm,
- * dbm*4.
+ * Release RAIL's internal resources for the packet.
+ * This must be called for any packet previously held via
+ * RAIL_HoldRxPacket(), and may optionally be called within
+ * callback context to release RAIL resources sooner than at
+ * callback completion time when not holding the packet.
+ * This function can be used in any RX mode.
*
- * This blocking function will poll the hardware for RSSI values and compute
- * the average RSSI over the requested time period. If no valid readings have
- * been made function will return \ref RAIL_RSSI_INVALID reading. Receiving a
- * packet during the averaging will cause invalid reading(s). However, invalid
- * readings during the averaging will not be included in the average. Number of
- * RSSI readings per baud depends on the phy.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] packetHandle A packet handle as returned from a previous
+ * RAIL_HoldRxPacket() call, or sentinel values
+ * \ref RAIL_RX_PACKET_HANDLE_OLDEST or \ref RAIL_RX_PACKET_HANDLE_NEWEST.
+ * The latter might be used within RAIL callback context to explicitly
+ * release the packet associated with the callback early, before it would
+ * be released automatically by RAIL on callback return (unless explicitly
+ * held).
+ * @return \ref RAIL_STATUS_NO_ERROR if the held packet was released
+ * or an appropriate error code otherwise.
*/
-int16_t RAIL_PollAverageRSSI(uint32_t averageTimeUs);
+RAIL_Status_t RAIL_ReleaseRxPacket(RAIL_Handle_t railHandle,
+ RAIL_RxPacketHandle_t packetHandle);
/**
- * Start the RSSI averaging over specified time in us
+ * Returns the current raw RSSI.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] wait if false returns instant RSSI with no checks.
+ * @return \ref RAIL_RSSI_INVALID if the receiver is disabled and an RSSI
+ * value can't be obtained. Otherwise, return the RSSI in quarter dBm, dbm*4.
*
- * @param[in] channel The physical channel to set
+ * Gets the current RSSI value. This value represents the current energy of the
+ * channel, it can change rapidly, and will be low if no RF energy is
+ * in the current channel. The function from the value reported to dBm is an
+ * offset dependent on the PHY and the PCB layout. Users should characterize the
+ * RSSI received on their hardware and apply an offset in the application to
+ * account for board and PHY parameters. 'Wait' argument doesn't guarantee
+ * a valid RSSI reading.'Wait' being true gives assurance that that the RSSI is
+ * current and not stale value from previous radio state. If GetRssi is called
+ * during RX-to-RX, RX-to-IDLE or RX-to-TX transition the RSSI is considered
+ * stale and \ref RAIL_RSSI_INVALID is returned if wait=true. 'Wait' being false
+ * will return either current RSSI or stale RSSI measurement (if called during
+ * RX-to-RX, RX-to-IDLE or RX-to-TX transition). \ref RAIL_RSSI_INVALID is
+ * returned if radio hasn't been in RX longer than 'idleToRx' time
+ * (see \ref RAIL_StateTiming_t), regardless of wait argument.
+ *
+ * In multiprotocol, this function returns \ref RAIL_RSSI_INVALID
+ * immediately if railHandle is not the current active \ref RAIL_Handle_t.
+ * Additionally 'wait' should never be set 'true' in multiprotocol
+ * as the wait time is not consistent, so scheduling a scheduler
+ * slot cannot be done accurately.
+ */
+int16_t RAIL_GetRssi(RAIL_Handle_t railHandle, bool wait);
+
+/**
+ * Starts the RSSI averaging over a specified time in us.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] channel The physical channel to set.
* @param[in] averagingTimeUs Averaging time in microseconds.
- * @return Returns 0 on success, error code on error.
+ * @param[in] schedulerInfo Information to allow the radio scheduler to place
+ * this operation appropriately. This is only used in multiprotocol version of
+ * RAIL and may be set to NULL in all other versions.
+ * @return Status code indicating success of the function call.
*
- * Start a non-blocking hardware based RSSI averaging mechanism. Only a single
+ * Starts a non-blocking hardware-based RSSI averaging mechanism. Only a single
* instance of RSSI averaging can be run at any time and the radio must be idle
* to start.
+ *
+ * In multiprotocol, this is a scheduled event. It will start when railHandle
+ * becomes active, and railHandle will need to stay active until the averaging
+ * completes. If the averaging is interrupted, calls to
+ * \ref RAIL_GetAverageRssi will return \ref RAIL_RSSI_INVALID.
+ *
+ * Also in multiprotocol, the user is required to call \ref RAIL_YieldRadio
+ * after this event completes (i.e. when \ref RAIL_EVENT_RSSI_AVERAGE_DONE
+ * occurs).
*/
-RAIL_Status_t RAIL_StartAverageRSSI(uint8_t channel, uint32_t averagingTimeUs);
+RAIL_Status_t RAIL_StartAverageRssi(RAIL_Handle_t railHandle,
+ uint16_t channel,
+ uint32_t averagingTimeUs,
+ const RAIL_SchedulerInfo_t *schedulerInfo);
/**
- * Queries whether the RSSI averaging is done
+ * Queries whether the RSSI averaging is done.
*
+ * @param[in] railHandle A RAIL instance handle.
* @return Returns true if done and false otherwise.
*
- * This function can be used to poll for completion of the RSSI averaging so
- * that you do not have to rely on an interrupt based callback.
- */
-bool RAIL_AverageRSSIReady(void);
-
-/**
- * Get the RSSI averaged over specified time in us
- *
- * @return Return \ref RAIL_RSSI_INVALID if the receiver is disabled and we are
- * unable to get an RSSI value, otherwise, return the RSSI in quarter dBm,
- * dbm*4.
- *
- * Get the hardware RSSI average after issuing RAIL_StartAverageRSSI. Should be
- * used after RAIL_StartAverageRSSI.
+ * This function can be used to poll for completion of the RSSI averaging
+ * to avoid relying on an interrupt-based callback.
*/
-int16_t RAIL_GetAverageRSSI(void);
-
-/**
- * Callback for when AGC averaged RSSI is done
- *
- * @param avgRssi Contains the the RSSI in quarter dBm (dbm*4) on success and
- * returns \ref RAIL_RSSI_INVALID if there was a problem computing the result.
- *
- * Called in response to RAIL_StartAverageRSSI() to indicate that the hardware
- * has completed averaging. If you would like you can instead use the
- * RAIL_AverageRSSIReady() to wait for completion and RAIL_GetAverageRSSI() to
- * get the result.
- */
-void RAILCb_RssiAverageDone(int16_t avgRssi);
-
-/**
- * Receive packet callback.
- *
- * @param[in] rxPacketHandle Contains a handle that points to the memory that
- * the packet was stored in. This handle will be the same as something
- * returned by the RAILCb_AllocateMemory() API. This handle will hold a
- * RAIL_RxPacketInfo_t structure starting at offset 0 in the buffer.
- *
- * This function is called whenever a packet is received and returns to you the
- * memory handle for where this received packet and its appended information was
- * stored. After this callback is done we will release the memory handle so you
- * must somehow increment a reference count or copy the data out within this
- * function.
- *
- * If \ref RAIL_IGNORE_CRC_ERRORS is set, this callback will fire for packets
- * with crc errors as well.
- */
-void RAILCb_RxPacketReceived(void *rxPacketHandle);
+bool RAIL_IsAverageRssiReady(RAIL_Handle_t railHandle);
/**
- * Called whenever an enabled radio status event occurs
- *
- * @param[in] status The event that triggered this callback
- *
- * The triggers that cause this function to be called can be enabled using the
- * RAIL_RxConfig() function.
+ * Gets the RSSI averaged over specified time in us.
*
- * @note This function will return only the first 8 of all possible triggers.
- * For accessing all triggers see the new RAILCb_RxRadioStatusExt() API. If you
- * implement RAILCb_RxRadioStatusExt() this callback will no longer be used by
- * the RAIL library. In RAIL 2.0 this API will be merged with the
- * RAILCb_RxRadioStatusExt() for one clean interface.
+ * @param[in] railHandle A RAIL instance handle.
+ * @return Return \ref RAIL_RSSI_INVALID if the receiver is disabled
+ * an RSSI value can't be obtained. Otherwise, return the RSSI in
+ * quarter dBm,dbm*4.
*
- * Triggers:
- * - \ref RAIL_RX_CONFIG_PREAMBLE_DETECT
- * - \ref RAIL_RX_CONFIG_SYNC1_DETECT
- * - \ref RAIL_RX_CONFIG_SYNC2_DETECT
- * - \ref RAIL_RX_CONFIG_FRAME_ERROR
- * - \ref RAIL_RX_CONFIG_BUFFER_OVERFLOW
- * - \ref RAIL_RX_CONFIG_ADDRESS_FILTERED
- * - \ref RAIL_RX_CONFIG_RF_SENSED
+ * Gets the hardware RSSI average after issuing RAIL_StartAverageRssi.
+ * It should be used after \ref RAIL_StartAverageRssi.
*/
-void RAILCb_RxRadioStatus(uint8_t status);
-
-/**
- * Called whenever an enabled radio status event occurs
- *
- * @param[in] status The event or events that triggered this callback
- *
- * The triggers that cause this function to be called can be enabled using the
- * RAIL_RxConfig() function. This function is the same as RAILCb_RxRadioStatus()
- * with an extended set of triggers. For backwards compatibility this function
- * is weakly defined in the RAIL library to call RAILCb_RxRadioStatus() with the
- * subset of valid events. If you need more events you must implement this
- * version which will stop the old one from being called.
- *
- * @note In RAIL 2.0 this API will be merged with the RAILCb_RxRadioStatus() for
- * one clean interface.
- *
- * Triggers:
- * - \ref RAIL_RX_CONFIG_PREAMBLE_DETECT
- * - \ref RAIL_RX_CONFIG_SYNC1_DETECT
- * - \ref RAIL_RX_CONFIG_SYNC2_DETECT
- * - \ref RAIL_RX_CONFIG_FRAME_ERROR
- * - \ref RAIL_RX_CONFIG_BUFFER_OVERFLOW
- * - \ref RAIL_RX_CONFIG_ADDRESS_FILTERED
- * - \ref RAIL_RX_CONFIG_RF_SENSED
- * - \ref RAIL_RX_CONFIG_TIMEOUT
- * - \ref RAIL_RX_CONFIG_SCHEDULED_RX_END
- * - \ref RAIL_RX_CONFIG_PACKET_ABORTED
- */
-void RAILCb_RxRadioStatusExt(uint32_t status);
+int16_t RAIL_GetAverageRssi(RAIL_Handle_t railHandle);
/******************************************************************************
- * Address Filtering (Rx)
+ * Address Filtering (RX)
*****************************************************************************/
/**
- * @addtogroup Address_Filtering
+ * @addtogroup Address_Filtering Address Filtering
* @brief Configuration APIs for receive packet address filtering.
*
* The address filtering code examines the packet as follows.
@@ -1514,34 +1911,34 @@
*
* In the above structure, anything listed as DataN is an optional section of
* bytes that RAIL will not process for address filtering. The FieldN segments
- * reference the specific sections in the packet that will each be interpreted
- * as an address during address filtering. The application may submit up to four
- * addresses to attempt to match each field segment and each address may have a
- * size of up to 8 bytes. To setup
- * address filtering you must first configure where the addresses are in your
- * packet and how long they are. Next, you need to configure what combinations
- * of matches in Field0 and Field1 should constitute an address match. Lastly,
- * you need to enter addresses into the tables for each field and enable them.
- * The first two of these are part of the RAIL_AddrConfig_t structure while the
- * second part is configured at runtime using the RAIL_AddressFilterSetAddress()
- * API. A brief description of each of these configurations is listed below.
+ * reference-specific sections in the packet that will each be interpreted
+ * as an address during address filtering. The application may submit up to
+ * four addresses to attempt to match each field segment and each address may
+ * have a size of up to 8 bytes. To set up address filtering, first configure
+ * the locations and length of the addresses in the packet. Next, configure
+ * which combinations of matches in Field0 and Field1 should constitute an
+ * address match. Lastly, enter addresses into tables for each field and
+ * enable them. The first two of these are part of the \ref RAIL_AddrConfig_t
+ * structure while the second part is configured at runtime using the
+ * RAIL_SetAddressFilterAddress() API. A brief description of each
+ * configuration is listed below.
*
- * For the first piece of configuration, the offsets and sizes of the fields are
- * assumed to be fixed for the RAIL address filter. To set them you must specify
+ * For the first piece of configuration, the offsets and sizes of the fields
+ * are assumed fixed for the RAIL address filter. To set them, specify
* arrays for these values in the sizes and offsets entries in the
- * RAIL_AddrConfig_t struct. A size of zero will indicate that a field is
- * disabled. The start offset for a field is relative to the previous start
- * offset and if you're using FrameType decoding the first start offset is
+ * \ref RAIL_AddrConfig_t structure. A size of zero indicates that a field is
+ * disabled. The start offset for a field is relative to the previous start
+ * offset and, if you're using FrameType decoding, the first start offset is
* relative to the end of the byte containing the frame type.
*
- * Configuring which combinations of Field0 and Field1 constitute a match is the
- * most complex portion of the address filter. The easiest way to think about
- * this is with a truth table. If you consider each of the four possible address
- * entries in a field then you can have a match on any one of those or a match
- * for none of them. We can represent this as a 4 bit mask where a 1 indicates a
- * match and a 0 indicates no match. If we then show the Field0 match options as
- * rows and the Field1 options as columns we get a truth table like the one
- * shown below.
+ * Configuring which combinations of Field0 and Field1 constitute a match is
+ * the most complex portion of the address filter. The easiest way to think
+ * about this is with a truth table. If you consider each of the four possible
+ * address entries in a field, you can have a match on any one of those or a
+ * match for none of them. This can be represented as a 4-bit mask where 1
+ * indicates a match and 0 indicates no match. Representing the Field0 match
+ * options as rows and the Field1 options as columns results in a truth table
+ * as shown below.
*
* | | 0000 | 0001 | 0010 | 0100 | 1000 |
* |----------|------|------|------|------|------|
@@ -1551,398 +1948,366 @@
* | __0100__ | bit15| bit16| bit17| bit18| bit19|
* | __1000__ | bit20| bit21| bit22| bit23| bit24|
*
- * Since this is only 25 bits it can be represented in one 32bit integer where a
- * 1 indicates filter pass and a 0 indicates filter fail. This is the matchTable
- * parameter in the configuration struct and it is what's used during filtering.
- * For common simple configurations we provide two defines, the truth tables for
- * which are shown below. The first is \ref
- * ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD and it can be used if you're only using
- * one address field (either field). If you're using two fields and want to
- * force in the same address entry in each field you can use second define: \ref
- * ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD. For more complex systems you'll have to
- * create a valid table on your own.
+ * Because this is only 25 bits, it can be represented in one 32-bit integer
+ * where 1 indicates a filter pass and 0 indicates a filter fail. This is the
+ * matchTable parameter in the configuration struct and is used during
+ * filtering. For common simple configurations two defines are provided with
+ * the truth tables as shown below. The first is \ref
+ * ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD, which can be used if only using
+ * one address field (either field). If using two fields and want to
+ * force in the same address entry in each field, use the second define: \ref
+ * ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD. For more complex systems,
+ * create a valid custom table.
*
- * @note Address filtering does not function properly with PHYs that use a data
- * rate greater than 500kbps. If you require this you must filter in software
- * for the time being.
+ * @note Address filtering does not function reliably with PHYs that use a data
+ * rate greater than 500 kbps. If this is a requirement, filter in software
+ * for the time being.
*
* @{
*/
/**
- * Configure address filtering.
+ * Configures address filtering.
*
- * @param addrConfig The configuration structure which defines how addresses
- * are setup in your packets.
- * @return True if we were able to configure address filtering and false
- * otherwise.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] addrConfig The configuration structure, which defines how
+ * addresses are setup in your packets.
+ * @return Status code indicating success of the function call.
*
- * This function must be called to setup address filtering. You may call this
- * multiple times, but all previous information is wiped out each time you call
- * it so any configured addresses must be reset.
+ * This function must be called to set up address filtering. You may call it
+ * multiple times but all previous information is wiped out each time you call
+ * and any configured addresses must be reset.
*/
-bool RAIL_AddressFilterConfig(RAIL_AddrConfig_t *addrConfig);
-
-/**
- * Enable address filtering.
- *
- * @return True if address filtering was enabled to start with and false
- * otherwise
- *
- * Only allow packets through that pass the current address filtering
- * configuration. This will not reset or change the configuration so you can
- * set that up before turning this feature on.
- */
-bool RAIL_AddressFilterEnable(void);
+RAIL_Status_t RAIL_ConfigAddressFilter(RAIL_Handle_t railHandle,
+ const RAIL_AddrConfig_t *addrConfig);
/**
- * Disable address filtering.
- *
- * @return True if address filtering was enabled to start with and false
- * otherwise
+ * Enables address filtering.
*
- * Allow all packets through regardless of addressing information. This will not
- * reset or change the current configuration.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] enable An argument to indicate whether or not to enable address
+ * filtering.
+ * @return True if address filtering was enabled to start with and false
+ * otherwise.
+ *
+ * Only allow packets through that pass the current address filtering
+ * configuration. This does not reset or change the configuration so you can
+ * set that up before turning on this feature.
*/
-bool RAIL_AddressFilterDisable(void);
+bool RAIL_EnableAddressFilter(RAIL_Handle_t railHandle, bool enable);
/**
- * Return whether address filtering is currently enabled.
+ * Returns whether address filtering is currently enabled.
*
- * @return True if address filtering is enabled and false otherwise
+ * @param[in] railHandle A RAIL instance handle.
+ * @return True if address filtering is enabled and false otherwise.
*/
-bool RAIL_AddressFilterIsEnabled(void);
-
-/**
- * Reset the address filtering configuration.
- *
- * Reset all structures related to address filtering. This will not disable
- * address fitlering. It will leave the radio in a state where no packets will
- * pass filtering.
- */
-void RAIL_AddressFilterReset(void);
+bool RAIL_IsAddressFilterEnabled(RAIL_Handle_t railHandle);
/**
- * Set an address for filtering in hardware.
+ * Resets the address filtering configuration.
*
- * @param field Which address field you want to use for this address
- * @param index Which match entry you want to place this address in for the
- * given field.
- * @param value A pointer to the address data. This must be at least as long
- * as the size specified in RAIL_AddressFilterConfig().
- * @param enable A boolean to indicate whether this address should be enabled
- * immediately.
- * @return True if we were able to set this address and false otherwise.
+ * @param[in] railHandle A RAIL instance handle.
+ * @return void.
*
- * This function will load the given address into hardware for filtering and
- * start filtering on it if you set the enable parameter to true. Otherwise,
- * you must call RAIL_AddressFilterEnableAddress() to turn it on later.
+ * Resets all structures related to address filtering. This does not disable
+ * address filtering. It leaves the radio in a state where no packets
+ * pass filtering.
*/
-bool RAIL_AddressFilterSetAddress(uint8_t field,
- uint8_t index,
- uint8_t *value,
- bool enable);
-
-/**
- * Enable address filtering for the specified address
- *
- * @param field Which address field you want to enable the address within
- * @param index Which match entry in the given field you want to enable
- * @return True if we were able to enable filtering for this address and false
- * otherwise.
- */
-bool RAIL_AddressFilterEnableAddress(uint8_t field, uint8_t index);
+void RAIL_ResetAddressFilter(RAIL_Handle_t railHandle);
/**
- * Disable address filtering for the specified address
- *
- * @param field Which address field you want to disable the address within
- * @param index Which match entry in the given field you want to disable
- * @return True if this address disabled successfully and false otherwise.
+ * Sets an address for filtering in hardware.
*
- * This will clear the matchMask set in the RAIL_AddressFilterEnableAddress()
- * function and make sure that this address is marked as valid. To use it in
- * filtering again you must enable this address again.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] field Which address field you want to use for this address.
+ * @param[in] index Which match entry you want to place this address in for a
+ * given field.
+ * @param[in] value A pointer to the address data. This must be at least as
+ * long as the size specified in RAIL_ConfigAddressFilter().
+ * @param[in] enable A boolean to indicate whether this address should be
+ * enabled immediately.
+ * @return Status code indicating success of the function call.
+ *
+ * This function loads the given address into hardware for filtering and
+ * starts filtering if you set the enable parameter to true. Otherwise,
+ * call RAIL_EnableAddressFilterAddress() to turn it on later.
*/
-bool RAIL_AddressFilterDisableAddress(uint8_t field, uint8_t index);
+RAIL_Status_t RAIL_SetAddressFilterAddress(RAIL_Handle_t railHandle,
+ uint8_t field,
+ uint8_t index,
+ const uint8_t *value,
+ bool enable);
/**
- * Configure address filtering based on frame type
- *
- * @param validFrames The frames on which to enable address filtering. Each bit
- * corresponds to a frame, where a 1 means to enable address filtering during
- * that frame, and a 0 means to ignore addresses during that frame. The least
- * significant bit corresponds to frame 0, and the most significant bit to
- * frame 7.
- * @return True if configuration was set properly, false otherwise
- *
- * This function only takes effect if frame type length decoding and address
- * filtering are both being used. In that case, this function gives the ability
- * to only enable address filtering on certain types of frames.
+ * Enables address filtering for the specified address.
*
- * @note This function must be called after RAIL_AddressFilterConfig for it to
- * take effect.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] enable An argument to indicate whether or not to enable address
+ * filtering.
+ * @param[in] field Which address field you want to enable the address in.
+ * @param[in] index Which match entry in the given field you want to enable.
+ * @return Status code indicating success of the function call.
*/
-bool RAIL_AddressFilterByFrameType(uint8_t validFrames);
+RAIL_Status_t RAIL_EnableAddressFilterAddress(RAIL_Handle_t railHandle,
+ bool enable,
+ uint8_t field,
+ uint8_t index);
-/**
- * end of group Address_Filtering
- * @}
- */
+/** @} */ // end of group Address_Filtering
-/**
- * end of group Receive
- * @}
- */
+/** @} */ // end of group Receive
/******************************************************************************
* Auto Acking
*****************************************************************************/
/**
- * @addtogroup Auto_Ack
- * @brief APIs for configuring Auto-Ack functionality
+ * @addtogroup Auto_Ack Auto ACK
+ * @brief APIs for configuring auto ACK functionality
*
- * These APIs are used to configure the radio for auto acknowledgement
- * features. Auto ack inherently changes how the underlying state machine
+ * These APIs are used to configure the radio for auto acknowledgment
+ * features. Auto ACK inherently changes how the underlying state machine
* behaves so users should not modify RAIL_SetRxTransitions() and
- * RAIL_SetTxTransitions() while using auto ack features.
+ * RAIL_SetTxTransitions() while using auto ACK features.
*
* @code{.c}
- * // Go to RX after ack operation, 100 us idle->rx/tx,
- * // 192 us rx->tx/tx->rx, 1000 us ack timeout
- * RAIL_AutoAckConfig_t autoAckConfig = { RAIL_RF_STATE_RX, 100, 192, 1000};
+ * // Go to RX after ACK operation
+ * RAIL_AutoAckConfig_t autoAckConfig = {
+ * .enable = true,
+ * .ackTimeout = 1000,
+ * // "error" param ignored
+ * .rxTransitions = { RAIL_RF_STATE_RX, RAIL_RF_STATE_RX},
+ * // "error" param ignored
+ * .txTransitions = { RAIL_RF_STATE_RX, RAIL_RF_STATE_RX}
+ * };
*
- * RAIL_Status_t status = RAIL_AutoAckConfig(&autoAckConfig);
+ * RAIL_Status_t status = RAIL_ConfigAutoAck(railHandle, &autoAckConfig);
*
- * uint8_t ackPayload[] = {0x05, 0x02, 0x10, 0x00};
- * RAIL_AutoAckData_t ackData = {ackPayload, sizeof(ackPayload)};
+ * uint8_t ackData[] = {0x05, 0x02, 0x10, 0x00};
*
- * RAIL_Status_t status = RAIL_AutoAckLoadBuffer(&ackData);
+ * RAIL_Status_t status = RAIL_WriteAutoAckFifo(ackData, sizeof(ackData));
* @endcode
*
- * The acknowledgement will transmit based on the frame format configured via
+ * The acknowledgment transmits based on the frame format configured via
* the Radio Configurator. For example, if the frame format is using a variable
- * length scheme, the ack will be sent according to that scheme. If a 10 byte
- * packet is loaded into the ack, but the variable length field of the ack
- * payload specifies a length of 5, only 5 bytes will transmit for the ack.
+ * length scheme, the ACK will be sent according to that scheme. If a 10-byte
+ * packet is loaded into the ACK, but the variable length field of the ACK
+ * payload specifies a length of 5, only 5 bytes will transmit for the ACK.
* The converse is also true, if the frame length is configured to be a fixed
- * 10 byte packet but only 5 bytes are loaded into the ack buffer then a TX
- * underflow will occur during the ack transmit.
- *
- * When auto ack is enabled, the default operation is to transmit the ack after
- * a receive and wait for an ack after a transmit. After the ack operation
- * completes, the radio will transition to the configured defaultState. If
- * there is a desire to not auto acknowledge a series of packets after transmit
- * or receive, call RAIL_AutoAckTxPause() and RAIL_AutoAckRxPause(). When
- * auto acking is paused, after successfully receiving or transmitting a
- * packet, the radio will transition to the defaultState. To get out of a
- * paused state and resume auto acking, call RAIL_AutoAckTxResume() or
- * RAIL_AutoAckRxResume().
- *
- * Applications can cancel the transmission of an ack with
- * RAIL_AutoAckCancelAck(). Conversly, applications can control if a transmit
- * operation should wait for an ack after transmitting by using
- * RAIL_TxStartWithOptions() and populating the waitForAck field in
- * \ref RAIL_TxOptions_t.
- *
- * @code{.c}
- * void RAILCb_RxPacketReceived(void *rxPacketHandle)
- * {
- * RAIL_RxPacketInfo_t rxPacketInfo = (RAIL_RxPacketInfo_t)rxPacketHandle;
+ * 10-byte packet but only 5 bytes are loaded into the ACK buffer, a TX
+ * underflow occurs during the ACK transmit.
*
- * // If we have just received an ACK, don't respond with an ACK
- * if (rxPacketInfo->dataPtr[2] == 0xF1)
- * {
- * RAIL_AutoAckCancelAck();
- * }
- * }
- *
- * void transmitAndWaitForAck (void)
- * {
- * RAIL_TxOptions_t txOption;
- * txOption.waitForAck = true;
- * RAIL_Status_t status = RAIL_TxStartWithOptions(0, &txOption, NULL, NULL);
- * }
- * @endcode
+ * Unlike in non-ACK mode, ACK mode will always return to a single
+ * state after all ACK sequences complete, regardless of whether
+ * the ACK was successfully received/sent or not. Read the documentation
+ * of RAIL_ConfigAutoAck for more detail on how that is configured. To
+ * not auto acknowledge a series of packets after transmit
+ * or receive, call RAIL_PauseTxAutoAck(true) or RAIL_PauseRxAutoAck(true).
+ * When auto acking is paused, after receiving or transmitting (also
+ * regardless of success) a packet, the radio transitions to the same single
+ * state it always defaults to while acking. To return to
+ * normal state transition logic outside of acking, you must call
+ * RAIL_ConfigAutoAck with the "enable" field false, and specify the
+ * desired transitions in the rxTransitions and txTransitions fields.
+ * To simply get out of a paused state and resume auto acking, call
+ * RAIL_PauseTxAutoAck(false) or RAIL_PauseRxAutoAck(false).
*
- * If the ack payload is dynamic, the application must call
- * RAIL_AutoAckLoadBuffer() with the appropriate ack payload after the
- * application processes the receive. RAIL can auto ack from the normal
- * transmit buffer if RAIL_AutoAckUseTxBuffer() is called before the radio
- * transmits the ack. Make sure the transmit buffer contains data loaded by
- * RAIL_TxDataLoad().
+ * Applications can cancel the transmission of an ACK with
+ * RAIL_CancelAutoAck(). Conversely, applications can control if a transmit
+ * operation should wait for an ACK after transmitting by using
+ * the \ref RAIL_TX_OPTION_WAIT_FOR_ACK bit.
*
- * Standards based protocols that contain auto ack functionality are normally
- * configured in the protocol specific config function. For example,
- * RAIL_IEEE802154_Init() provides auto ack configuration parameters in \ref
+ * If the ACK payload is dynamic, the application must call
+ * RAIL_WriteAutoAckFifo() with the appropriate ACK payload after the
+ * application processes the receive. RAIL can auto ACK from the normal
+ * transmit buffer if RAIL_UseTxFifoForAutoAck() is called before the radio
+ * transmits the ACK. Ensure the transmit buffer contains data loaded by
+ * RAIL_WriteTxFifo().
+ *
+ * Standard-based protocols that contain auto ACK functionality are normally
+ * configured in the protocol-specific configuration function. For example,
+ * RAIL_IEEE802154_Init() provides auto ACK configuration parameters in \ref
* RAIL_IEEE802154_Config_t and should only be configured through that
- * function. It is unadvised to call both RAIL_IEEE802154_Init() and
- * RAIL_AutoAckConfig(). However, ack modification functions are still valid to
- * use with protocol specific acks. To cancel a IEEE 802.15.4 ack transmit, use
- * RAIL_AutoAckCancelAck().
+ * function. It is not advisable to call both RAIL_IEEE802154_Init() and
+ * RAIL_ConfigAutoAck(). However, ACK modification functions are still valid to
+ * use with protocol-specific ACKs. To cancel a IEEE 802.15.4 ACK transmit, use
+ * RAIL_CancelAutoAck().
*
* @{
*/
/**
- * Disable Automatic Acknowledgement
- *
- * @return if function successfully disabled auto acking
- *
- * Disable auto ack functionality. All state transitions are reverted to IDLE,
- * IDLE.
- */
-RAIL_Status_t RAIL_AutoAckDisable(void);
-
-/**
- * Return the enable status of the auto ack feature
+ * Configures and enable auto acknowledgment.
*
- * @return true if Auto Ack is enabled, false if disabled
- */
-bool RAIL_AutoAckIsEnabled(void);
-
-/**
- * Configure and enable Auto Acknowledgement
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] config Auto ACK configuration structure.
+ * @return Status code indicating success of the function call.
*
- * @param[in] config Auto ack config structure
- * @return If autoack is successfully enabled
- *
- * Configures the RAIL state machine to for hardware accelerated auto
- * acknowledgement. Ack timing parameters are defined in the configuration
+ * Configures the RAIL state machine to for hardware-accelerated auto
+ * acknowledgment. ACK timing parameters are defined in the configuration
* structure.
*
- * While auto acking is enabled do not call the following RAIL functions:
+ * While auto acking is enabled, do not call the following RAIL functions:
* - RAIL_SetRxTransitions()
* - RAIL_SetTxTransitions()
- * - RAIL_SetStateTiming()
+ *
+ * Note, that if you are enabling auto ACK (i.e. "enable" field is true)
+ * The "error" fields of rxTransitions and txTransitions are ignored.
+ * After all ACK sequences, (success or fail) the state machine will return
+ * the radio to the "success" state. If you need information about the
+ * actual success of the ACK sequence, you can use RAIL events such as
+ * \ref RAIL_EVENT_TXACK_PACKET_SENT to make sure an ACK was sent, or
+ * \ref RAIL_EVENT_RX_ACK_TIMEOUT to make sure that an ACK was received
+ * within the specified timeout.
+ *
+ * If you wish to set a certain turnaround time (i.e. txToRx and rxToTx
+ * in \ref RAIL_StateTiming_t), we recommend that you make txToRx lower than
+ * desired, in order to ensure you get to RX in time to receive the ACK.
+ * Silicon Labs recommends setting 10us lower than desired:
+ *
+ * @code{.c}
+ * void setAutoAckStateTimings()
+ * {
+ * RAIL_StateTiming_t timings;
+ *
+ * // User is already in auto ACK and wants a turnaround of 192us
+ * timings.rxToTx = 192;
+ * timings.txToRx = 192 - 10;
+ *
+ * // Set other fields of timings...
+ * timings.idleToRx = 100;
+ * timings.idleToTx = 100;
+ * timings.rxSearchTimeout = 0;
+ * timings.txToRxSearchTimeout = 0;
+ *
+ * RAIL_SetStateTiming(railHandle, &timings);
+ * }
+ * @endcode
+ *
+ * As opposed to an explicit "Disable" API, simply set the "enable"
+ * field of the RAIL_AutoAckConfig_t to false. Then, auto ACK will be
+ * disabled and state transitions will be returned to the values set
+ * in \ref RAIL_AutoAckConfig_t. During this disable, the "ackTimeout" field
+ * isn't used.
*/
-RAIL_Status_t RAIL_AutoAckConfig(RAIL_AutoAckConfig_t *config);
+RAIL_Status_t RAIL_ConfigAutoAck(RAIL_Handle_t railHandle,
+ const RAIL_AutoAckConfig_t *config);
/**
- * Load Auto Ack buffer with ack data
+ * Returns the enable status of the auto ACK feature.
*
- * @param[in] ackData Pointer to ack data to transmit
- * @return \ref RAIL_STATUS_INVALID_CALL if called while ACK buffer is being
- * used by the radio
- *
- * If the ack buffer is available to be updated, load the ack buffer with data.
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if auto ACK is enabled, false if disabled.
*/
-RAIL_Status_t RAIL_AutoAckLoadBuffer(RAIL_AutoAckData_t *ackData);
+bool RAIL_IsAutoAckEnabled(RAIL_Handle_t railHandle);
/**
- * Pause RX Auto Ack functionality.
- *
- * @return void
- *
- * When RX Auto Acking is paused, the radio will transition to the defaultState
- * after receiving a packet and will not transmit an ack.
- *
- */
-void RAIL_AutoAckRxPause(void);
-
-/**
- * Resume Rx Auto Ack functionality.
+ * Loads the auto ACK buffer with ACK data.
*
- * @return void
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] dataPtr A pointer to ACK data to transmit.
+ * @param[in] dataLength Number of bytes of ACK data.
+ * @return Status code indicating success of the function call.
*
- * When Rx Auto Ack is resumed, the radio will resume automatically acking
- * every successfully received packet.
+ * If the ACK buffer is available for updates, load the ACK buffer with data.
*/
-void RAIL_AutoAckRxResume(void);
-
-/**
- * Return if Rx Auto Ack is paused
- *
- * @return true if Rx Auto Ack is paused, false if not paused
- */
-bool RAIL_AutoAckRxIsPaused(void);
+RAIL_Status_t RAIL_WriteAutoAckFifo(RAIL_Handle_t railHandle,
+ const uint8_t *dataPtr,
+ uint8_t dataLength);
/**
- * Resume Tx Auto Ack functionality.
+ * Pauses/resumes RX auto ACK functionality.
*
- * @return void
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] pause Pause or resume RX auto acking.
+ * @return void.
*
- * When Tx Auto Ack is resumed, the radio will resume automatically waiting for
- * an ack after a successful transmit.
+ * When RX auto acking is paused, the radio transitions to default
+ * state after receiving a packet and does not transmit an ACK.
+ * When RX auto ACK is resumed, the radio resumes automatically acking
+ * every successfully received packet.
*/
-void RAIL_AutoAckTxResume(void);
+void RAIL_PauseRxAutoAck(RAIL_Handle_t railHandle,
+ bool pause);
+
+/**
+ * Returns whether the RX auto ACK is paused.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if RX auto ACK is paused, false if not paused.
+ */
+bool RAIL_IsRxAutoAckPaused(RAIL_Handle_t railHandle);
/**
- * Pause TX Auto Ack functionality.
+ * Pauses/resumes TX auto ACK functionality.
*
- * @return void
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] pause Pause or resume TX auto acking.
+ * @return void.
*
- * When TX Auto Acking is paused, the radio will transition to the defaultState
- * after transmitting a packet and will not wait for an ack.
- *
+ * When TX auto acking is paused, the radio transitions to a default
+ * state after transmitting a packet and does not wait for an ACK. When TX
+ * auto ACK is resumed, the radio resumes automatically waiting for
+ * an ACK after a successful transmit.
*/
-void RAIL_AutoAckTxPause(void);
+void RAIL_PauseTxAutoAck(RAIL_Handle_t railHandle, bool pause);
/**
- * Return if Tx Auto Ack is paused
+ * Returns whether the TX auto ACK is paused.
*
- * @return true if Tx Auto Ack is paused, false if not paused
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if TX auto ACK is paused, false if not paused.
*/
-bool RAIL_AutoAckTxIsPaused(void);
+bool RAIL_IsTxAutoAckPaused(RAIL_Handle_t railHandle);
/**
- * Modify the upcoming ack to use the TX Buffer
+ * Modifies the upcoming ACK to use the TX Buffer.
*
- * @return True if the ack is modified to send from TX buffer, false if it is
- * too late to switch to tx buffer or if the function call is not valid
+ * @param[in] railHandle A RAIL instance handle.
+ * @return Status code indicating success of the function call. This call will
+ * fail if it is too late to modify the outgoing ACK.
*
* This function allows the application to use the normal TX buffer as the data
- * source for the upcoming ack. The ack modification to use the TX buffer only
- * applies to one ack transmission.
+ * source for the upcoming ACK. The ACK modification to use the TX buffer only
+ * applies to one ACK transmission.
*
- * This function will only return true if the following conditions are met:
- * - Radio has not already decided to use the ack buffer AND
- * - Radio is either looking for sync, receiving the packet after sync or in
- * the Rx2Tx turnaround before the ack is sent.
+ * This function only returns true if the following conditions are met:
+ * - Radio has not already decided to use the ACK buffer AND
+ * - Radio is either looking for sync, receiving the packet after sync, or in
+ * the Rx2Tx turnaround before the ACK is sent.
*/
-bool RAIL_AutoAckUseTxBuffer(void);
+RAIL_Status_t RAIL_UseTxFifoForAutoAck(RAIL_Handle_t railHandle);
/**
- * Cancel the upcoming ack
+ * Cancels the upcoming ACK.
*
- * @return True if the ack is successfully cancelled, false if it is
- * too late to cancel the ack or if the function call is not valid
+ * @param[in] railHandle A RAIL instance handle.
+ * @return Status code indicating success of the function call. This call will
+ * fail if it is too late to modify the outgoing ACK.
*
- * This function allows the application to use cancel the upcoming automatic
- * acknowledgement.
+ * This function allows the application to cancel the upcoming automatic
+ * acknowledgment.
*
- * This function will only return true if the following conditions are met:
- * - Radio has not already decided to transmit the ack AND
+ * This function only returns true if the following conditions are met:
+ * - Radio has not already decided to transmit the ACK AND
* - Radio is either looking for sync, receiving the packet after sync or in
- * the Rx2Tx turnaround before the ack is sent.
+ * the Rx2Tx turnaround before the ACK is sent.
*/
-bool RAIL_AutoAckCancelAck(void);
+RAIL_Status_t RAIL_CancelAutoAck(RAIL_Handle_t railHandle);
/**
- * Return if the radio is currently waiting for an ack
- *
- * @return True if radio is waiting for ack, False if radio is not waiting for
- * an ack
+ * Returns whether the radio is currently waiting for an ACK.
*
- * This function allows the application to query if the radio is currently
- * waiting for an ack after a transmit operation.
+ * @param[in] railHandle A RAIL instance handle.
+ * @return True if radio is waiting for ACK, false if radio is not waiting for
+ * an ACK.
+ *
+ * This function allows the application to query whether the radio is currently
+ * waiting for an ACK after a transmit operation.
*/
-bool RAIL_AutoAckWaitingForAck(void);
+bool RAIL_IsAutoAckWaitingForAck(RAIL_Handle_t railHandle);
-/**
- * Callback that notifies the application when searching for an ACK has timed
- * out.
- *
- * @return void
- *
- * This callback function is called whenever the timeout for searching for an
- * ack is exceeded.
- */
-void RAILCb_RxAckTimeout(void);
-
-/**
- * @} endof Auto_Acking
- */
+/** @} */ // end of group Auto_Ack
/******************************************************************************
* Calibration
@@ -1952,9 +2317,9 @@
* @brief APIs for calibrating the radio
* @{
*
- * These APIs can be used to calibrate the radio. The RAIL library will
- * determine what calibrations are necessary to be performed. Calibrations can
- * be enabled/disabled in RAIL_Init_t.calEnable.
+ * These APIs can be used to calibrate the radio. The RAIL library
+ * determines which calibrations are necessary. Calibrations can
+ * be enabled/disabled with the RAIL_CalMask_t parameter.
*
* Some calibrations produce values that can be saved and reapplied to
* save repetition of the calibration process. RAIL_CalValues_t is the
@@ -1964,69 +2329,176 @@
/**
* Initialize RAIL Calibration
*
- * @param[in] railCalInit The initialization structure to be used for setting
- * up calibration procedures.
- * @return Returns zero on success and an error code on error.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] calEnable A bitmask of which calibrations to enable for callback
+ * notification. The exact meaning of these bits is chip specific.
+ * @return Status code indicating success of the function call.
*
* Calibration initialization provides the calibration settings that
* correspond to the current radio configuration.
*/
-uint8_t RAIL_CalInit(const RAIL_CalInit_t *railCalInit);
+RAIL_Status_t RAIL_ConfigCal(RAIL_Handle_t railHandle,
+ RAIL_CalMask_t calEnable);
/**
- * Start the calibration process
+ * Starts the calibration process.
*
- * @param[in] calValues Calibration Values to apply. To force the calibration
- * algorithm to run set the value to \ref RAIL_CAL_INVALID_VALUE.
- * @param[in] calForce Mask to force certain calibration(s) to execute. These
- * will run even if not enabled during initialization. If specified, only forced
- * calibrations will be run.
- * @param[in] calSave If true, we will update any invalid values in calValues
- * with their computed value. You can use this to save calibrations across runs.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in,out] calValues Calibration values to apply. If the calibration
+ * value is \ref RAIL_CAL_INVALID_VALUE, that value will be updated to a
+ * valid value. If the calValues pointer is NULL, the specified
+ * calibration will still occur, but the valid calibration value will
+ * not be returned.
+ * @param[in] calForce A mask to force specific calibration(s) to execute.
+ * To run all pending calibrations, use the value \ref RAIL_CAL_ALL_PENDING.
+ * Only the calibrations specified will run, even if not enabled during
+ * initialization.
+ * @return Status code indicating success of the function call.
*
* This function begins the calibration process while determining which
* calibrations should be performed. The possible list of calibration options
- * are configured in RAIL_Init_t.calEnable parameter.
+ * is configured with the RAIL_CalMask_t parameter.
*
* If the calibration was performed previously and the application saves off
- * the calibration value, it can be passed into function and applied to the
- * chip. If the calibration value provided is \ref RAIL_CAL_INVALID_VALUE then
- * the calibration will be performed to set this value. If calSave is set, the
- * calibration output will update the pointer's value. If a NULL pointer is
- * passed in all calibrations requested/required will be performed and the
- * results will not be saved regardless of the calSave parameter.
+ * the calibration value, it can be passed into the function and applied to the
+ * chip. If the calibration value provided is \ref RAIL_CAL_INVALID_VALUE,
+ * the calibration is performed, and the calibration output updates the
+ * structure passed in. If a NULL pointer is passed, all calibrations
+ * requested/required are performed, and the results are not returned.
+ *
+ * If multiple protocols are used, this function will return
+ * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is
+ * not active. The caller must attempt to re-call this function later, in that
+ * case.
*
* @note Some calibrations should only be executed when the radio is IDLE. See
- * chip-specific documentation for more detail.
+ * chip-specific documentation for more details.
+ */
+RAIL_Status_t RAIL_Calibrate(RAIL_Handle_t railHandle,
+ RAIL_CalValues_t *calValues,
+ RAIL_CalMask_t calForce);
+
+/**
+ * Returns the current set of pending calibrations.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return A mask of all pending calibrations that the user has been asked to
+ * perform.
+ *
+ * This function returns a full set of pending calibrations. The only way
+ * to clear pending calibrations is to perform them using the \ref
+ * RAIL_Calibrate() API with the appropriate list of calibrations.
*/
-void RAIL_CalStart(RAIL_CalValues_t *calValues, RAIL_CalMask_t calForce, bool calSave);
+RAIL_CalMask_t RAIL_GetPendingCal(RAIL_Handle_t railHandle);
+
+/**
+ * Enable/Disable PA calibration
+ *
+ * @param[in] enable Enables/Disables PA calibration
+ * @return void.
+ *
+ * Enabling this will ensure that the PA power remains constant chip to chip.
+ * By default this feature is disabled after reset.
+ *
+ * @note this function should be called before \ref RAIL_ConfigTxPower() if this
+ * feature is desired.
+ */
+void RAIL_EnablePaCal(bool enable);
+
+/** @} */ // end of group Calibration
+
+/******************************************************************************
+ * RF Sense Structures
+ *****************************************************************************/
+/**
+ * @addtogroup Rf_Sense RF Sense
+ * @{
+ */
/**
- * Returns the current set of pending calibrations
+ * Starts/stops RF Sense functionality for use during low-energy sleep modes.
*
- * @return A mask of all pending calibrations that the user has been asked to
- * perform.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] band The frequency band(s) on which to sense the RF energy.
+ * To stop RF Sense, specify \ref RAIL_RFSENSE_OFF.
+ * @param[in] senseTime The time (in microseconds) the RF energy must be
+ * continually detected to be considered "sensed".
+ * @param[in] cb \ref RAIL_RfSense_CallbackPtr_t is called when the RF is
+ * sensed. Set null if polling via \ref RAIL_IsRfSensed().
+ * @return The actual senseTime used, which may be different than
+ * requested due to limitations of the hardware. If 0, RF sense was
+ * disabled or could not be enabled (no callback will be issued).
*
- * This function will return a full set of pending calibrations. The only way
- * to clear pending calibrations is to perform them using the \ref RAIL_CalStart()
- * API with the appropriate list of calibrations.
+ * The EFR32 has the ability to sense the presence of RF Energy above -20 dBm
+ * within either or both the 2.4 GHz and Sub-GHz bands and trigger an event
+ * if that energy is continuously present for certain durations of time.
+ *
+ * @note After RF energy has been sensed, the RF Sense is automatically
+ * disabled. RAIL_StartRfSense() must be called again to reactivate it.
+ *
+ * @warning RF Sense functionality is only guaranteed from 0 to 85 degrees
+ * Celsius. RF Sense should be disabled outside of this temperature range.
*/
-RAIL_CalMask_t RAIL_CalPendingGet(void);
+uint32_t RAIL_StartRfSense(RAIL_Handle_t railHandle,
+ RAIL_RfSenseBand_t band,
+ uint32_t senseTime,
+ RAIL_RfSense_CallbackPtr_t cb);
/**
- * Callback that notifies the application that a calibration is needed.
+ * Checks if the RF was sensed.
*
- * @return void
+ * @param[in] railHandle A RAIL instance handle.
+ * @return true if RF was sensed since the last call to \ref RAIL_StartRfSense.
+ * False otherwise.
*
- * This callback function is called whenever the RAIL library detects that a
- * calibration is needed. It is up to the application to determine a valid
- * window to call \ref RAIL_CalStart().
+ * This function is useful if \ref RAIL_StartRfSense is called with a null
+ * callback. It is generally used after EM4 reboot but can be used any time.
*/
-void RAILCb_CalNeeded(void);
+bool RAIL_IsRfSensed(RAIL_Handle_t railHandle);
+
+/** @} */ // end of group Rf_Sense
+
+/******************************************************************************
+ * Multiprotocol Structures
+ *****************************************************************************/
+/**
+ * @addtogroup Multiprotocol
+ * @brief Multiprotocol scheduler APIs to support multiple time-sliced PHYs.
+ * @{
+ */
/**
- * @}
+ * Yields the radio to other configurations
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return void.
+ *
+ * This function is used to indicate that the previous transmit or scheduled
+ * receive operation has completed. It must be used in multiprotocol RAIL since
+ * the scheduler assumes that any transmit or receive operation that is started
+ * by you can go on infinitely based on state transitions and your protocol.
+ * RAIL will not allow a new transmit or scheduled receive until this is called
+ * and will not run lower priority tasks from other instances. You may also
+ * simply call the \ref RAIL_Idle() API to terminate the operation too. In
+ * single protocol RAIL this API does nothing but may be called to keep your
+ * code multiprotocol ready if desired.
+ *
+ * See \ref rail_radio_scheduler_yield for more details.
*/
+void RAIL_YieldRadio(RAIL_Handle_t railHandle);
+
+/**
+ * Get the status of the RAIL scheduler.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @return \ref RAIL_SchedulerStatus_t status.
+ *
+ * This function should be checked after the \ref RAIL_EVENT_SCHEDULER_STATUS
+ * event occurs.
+ */
+RAIL_SchedulerStatus_t RAIL_GetSchedulerStatus(RAIL_Handle_t railHandle);
+
+/** @} */ // end of group Multiprotocol
/******************************************************************************
* Diagnostic
@@ -2038,131 +2510,122 @@
*/
/**
- * Enable or disable direct mode for RAIL.
+ * Enables or disables direct mode for RAIL.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] enable Whether or not to enable direct mode.
+ * @return \ref RAIL_STATUS_NO_ERROR on success and an error code on failure.
*
- * @param[in] enable Whether to turn direct mode on or off. At some point this
- * will include a configuration structure.
- * @warning This API configures fixed pins for tx data in, rx data out, rx clock
- * out. There should be more control over these pins in the future but they are
- * currently fixed.
+ * @warning This API configures fixed pins for TX data in, RX data out,
+ * RX clock out. There should be more control over these pins in the
+ * future but they are currently fixed. Also, this API is not safe to
+ * use in a true multiprotocol app.
*
- * In this mode packets will be output and input directly to the radio via GPIO
- * and RAIL packet handling will be ignored. On the EFR32, the DIN pin in TX is
+ * In this mode packets are output and input directly to the radio via GPIO
+ * and RAIL packet handling is ignored. On the EFR32, the DIN pin in TX is
* EFR32_PC10, which corresponds to EXP_HEADER15/WSTKP12, and the DOUT pin in
* RX is EFR32_PC11, which corresponds to EXP_HEADER16/WSTKP13.
*/
-void RAIL_DirectModeConfig(bool enable);
-
-/**
- * Set the crystal tuning
- *
- * @param[in] tune Chip dependent crystal capacitor bank tuning parameter
- *
- * Tune the crystal that the radio depends on, to change the location of the
- * center frequency for transmitting and receiving.
- */
-void RAIL_SetTune(uint32_t tune);
-
-/**
- * Get the crystal tuning
- *
- * @return Chip dependent crystal capacitor bank tuning parameter
- *
- * Retrieve the current tuning value used by the crystal that the radio
- * depends on.
- */
-uint32_t RAIL_GetTune(void);
+RAIL_Status_t RAIL_EnableDirectMode(RAIL_Handle_t railHandle,
+ bool enable);
/**
- * Starts transmitting a tone on a certain channel
+ * Sets the crystal tuning.
*
- * @param[in] channel Define the channel to emit a tone
- * @return Returns 0 on success and 1 on error
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] tune A chip-dependent crystal capacitor bank tuning parameter.
+ * @return Status code indicating success of the function call.
*
- * Transmits a continuous wave, or tone, at the given channel, as defined by
- * the channel configuration passed to RAIL_ChannelConfig().
+ * Tunes the crystal that the radio depends on to change the location of the
+ * center frequency for transmitting and receiving. This function will only
+ * succeed if the radio is idle at the time of the call.
+ *
+ * @note This function proportionally affects the entire chip's timing
+ * across all its peripherals, including radio tuning and channel spacing.
+ * A separate function, \ref RAIL_SetFreqOffset(), can be used to adjust
+ * just the radio tuner without disturbing channel spacing or other chip
+ * peripheral timing.
*/
-uint8_t RAIL_TxToneStart(uint8_t channel);
+RAIL_Status_t RAIL_SetTune(RAIL_Handle_t railHandle, uint32_t tune);
/**
- * Stop tone transmission
+ * Gets the crystal tuning.
*
- * @return Returns 0 on success and 1 on error
+ * @param[in] railHandle A RAIL instance handle.
+ * @return A chip-dependent crystal capacitor bank tuning parameter.
*
- * Halt the transmission started by RAIL_TxToneStart().
+ * Retrieves the current tuning value used by the crystal that the radio
+ * depends on.
*/
-uint8_t RAIL_TxToneStop(void);
-
-/**
- * Start transmitting a stream on a certain channel
- *
- * @param[in] channel Channel on which to emit a stream
- * @param[in] mode Choose the stream mode (PN9, etc)
- * @return Returns 0 on success and 1 on error
- *
- * Emits an encoded stream of bits on the given channel, from either a PN9 or
- * pseudo-random source.
- */
-uint8_t RAIL_TxStreamStart(uint8_t channel, RAIL_StreamMode_t mode);
+uint32_t RAIL_GetTune(RAIL_Handle_t railHandle);
/**
- * Stop stream transmission
+ * Gets the frequency offset.
*
- * @return Returns 0 on success and 1 on error
+ * @param[in] railHandle A RAIL instance handle.
+ * @return Returns the measured frequency offset on a received packet.
+ * The units are described in the \ref RAIL_FrequencyOffset_t
+ * documentation. If this returns \ref RAIL_FREQUENCY_OFFSET_INVALID
+ * it was called while the radio wasn't active and there is no way
+ * to get the frequency offset.
*
- * Halt the transmission started by RAIL_TxStreamStart().
+ * Retrieves the measured frequency offset used during the previous
+ * received packet, which includes the current radio frequency offset
+ * (see \ref RAIL_SetFreqOffset()). If the chip has not been in RX,
+ * it returns the nominal radio frequency offset.
*/
-uint8_t RAIL_TxStreamStop(void);
-
-/**
- * Configure BER test
- *
- * @param[in] berConfig BER test parameters to apply.
- *
- * Configure settings specific to bit error rate (BER) testing.
- * During BER test mode, this device will expect to receive a standard PN9
- * signal (x^9 + x^5 + 1). In order to use this BER test, the selection
- * for BER mode should be enabled from the radio configurator.
- * This function has been deprecated.
- */
-void RAIL_BerConfigSet(RAIL_BerConfig_t *berConfig);
+RAIL_FrequencyOffset_t RAIL_GetRxFreqOffset(RAIL_Handle_t railHandle);
/**
- * Start BER test
+ * Sets the nominal radio frequency offset.
*
- * @return void
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] freqOffset \ref RAIL_FrequencyOffset_t parameter (signed, 2's
+ * complement).
+ * @return Status code indicating success of the function call.
*
- * Enter BER receive with the settings specified by RAIL_BerConfigSet().
- * This also resets the BER status.
- * This function has been deprecated.
+ * This is used to adjust the radio's tuning frequency slightly up or down.
+ * It might be used in conjunction with \ref RAIL_GetRxFreqOffset() after
+ * receiving a packet from a peer to adjust the tuner to better match the
+ * peer's tuned frequency.
+ *
+ * @note Unlike \ref RAIL_SetTune(), which affects the entire chip's
+ * timing including radio tuning and channel spacing, this function
+ * only affects radio tuning without disturbing channel spacing or
+ * other chip peripheral timing.
*/
-void RAIL_BerRxStart(void);
+RAIL_Status_t RAIL_SetFreqOffset(RAIL_Handle_t railHandle,
+ RAIL_FrequencyOffset_t freqOffset);
/**
- * Stop BER test
+ * Starts transmitting a stream on a certain channel.
*
- * @return void
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] channel A channel on which to emit a stream.
+ * @param[in] mode Choose the stream mode (PN9, and so on).
+ * @return Status code indicating success of the function call.
*
- * Halt a test early, or exit infinite BER receive mode.
- * This function has been deprecated.
+ * Begins streaming onto the given channel. The sources can either be an
+ * unmodulated carrier wave, or an encoded stream of bits from a PN9 source.
+ * All ongoing radio operations will be stopped before transmission begins.
*/
-void RAIL_BerRxStop(void);
+RAIL_Status_t RAIL_StartTxStream(RAIL_Handle_t railHandle,
+ uint16_t channel,
+ RAIL_StreamMode_t mode);
/**
- * Get BER test status
+ * Stops stream transmission.
*
- * @param[out] status Statistics pertaining to the latest BER test.
- * @return void
+ * @param[in] railHandle A RAIL instance handle.
+ * @return Status code indicating success of the function call.
*
- * Get status of latest BER test.
- * This function has been deprecated.
+ * Halts the transmission started by RAIL_StartTxStream().
*/
-void RAIL_BerStatusGet(RAIL_BerStatus_t *status);
+RAIL_Status_t RAIL_StopTxStream(RAIL_Handle_t railHandle);
-/**
- * @}
- */
+/** @} */ // end of group Diagnostic
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
/******************************************************************************
* Debug
@@ -2173,61 +2636,74 @@
* @{
*/
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
/**
- * Configure Debug callbacks (all are optional)
- *
- * @param[in] cbToEnable Define statuses that force TxRadioStatus callback
+ * Configures the debug mode for the radio library. Do not use this function
+ * unless instructed by Silicon Labs.
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] debugMode Debug mode to enter.
+ * @return Status code indicating success of the function call.
*/
-void RAIL_DebugCbConfig(uint32_t cbToEnable);
+RAIL_Status_t RAIL_SetDebugMode(RAIL_Handle_t railHandle, uint32_t debugMode);
/**
- * Configure the debug mode for the radio library. Do not use this function
- * unless instructed to by Silicon Labs.
- * @param debugMode The debug mode to enter
- * @return Whether this command ran successfully or not.
+ * Returns the debug mode for the radio library. Do not use this function
+ * unless instructed by Silicon Labs.
+ * @param[in] railHandle A RAIL instance handle.
+ * @return Debug mode for the radio library.
*/
-RAIL_Status_t RAIL_DebugModeSet(uint32_t debugMode);
-
-uint32_t RAIL_DebugModeGet(void);
+uint32_t RAIL_GetDebugMode(RAIL_Handle_t railHandle);
/**
- * Override the radio base frequency
+ * Overrides the radio base frequency.
*
- * @param[in] freq Desired frequency in Hz
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] freq A desired frequency in Hz.
+ * @return Status code indicating success of the function call.
*
* Sets the radio to transmit at the frequency given. This function can only
- * be used while in RAIL_DEBUG_MODE_FREQ_OVERRIDE. The given frequency needs
- * to be close to the base frequency of the current PHY.
+ * be used while in \ref RAIL_DEBUG_MODE_FREQ_OVERRIDE. The given frequency
+ * needs to be close to the base frequency of the current PHY.
*/
-RAIL_Status_t RAIL_DebugFrequencyOverride(uint32_t freq);
-#endif
+RAIL_Status_t RAIL_OverrideDebugFrequency(RAIL_Handle_t railHandle,
+ uint32_t freq);
+
+/** @} */ // end of group Debug
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
+/******************************************************************************
+ * Assertion Callback
+ *****************************************************************************/
/**
- * Callback function to signify when the radio changes state.
- *
- * @param[in] state Current state of the radio. Exact values are for internal
- * use only.
+ * @addtogroup Assertions
+ * @brief Callbacks called by assertions
*
- * This is for debug and __NOT__ for application use. It is not called by
- * default but is required for the linking process.
- *
- * Create an empty function for this callback as shown below.
+ * This assertion framework was implemented for the purpose of not only being
+ * able to assert that certain conditions be true in a block of code, but also
+ * to be able to handle them more appropriately. In previous implementations,
+ * the behavior upon a failed assert would be to hang in a while(1) loop.
+ * However, with the callback, each assert is given a unique error code so that
+ * they can be handled on a more case-by-case basis. For documentation on each
+ * of the errors, please see the rail_assert_error_codes.h file.
+ * RAIL_ASSERT_ERROR_MESSAGES[errorCode] gives the explanation of the error.
+ * With asserts built into the library, customers can choose how to handle each
+ * error inside the callback.
*
- * @code{.c}
- * RAILCb_RadioStateChanged(uint8_t state) {
- * }
- * @endcode
- */
-void RAILCb_RadioStateChanged(uint8_t state);
-
-/**
- * @}
+ * @{
*/
/**
- * end of RAIL_API
- * @}
+ * Callback called upon failed assertion.
+ *
+ * @param[in] railHandle A RAIL instance handle.
+ * @param[in] errorCode Value passed in by the calling assertion API indicating
+ * the RAIL error that is indicated by the failing assertion.
+ * @return void.
*/
+void RAILCb_AssertFailed(RAIL_Handle_t railHandle, uint32_t errorCode);
+
+/** @} */ // end of group Assertions
+
+/** @} */ // end of group RAIL_API
#endif // __RAIL_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_assert_error_codes.h Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,145 @@
+/***************************************************************************//**
+ * @file rail_assert_error_codes.h
+ * @brief Definition of error codes that occur in rail for use in
+ RAILCb_AssertFailed. This file is purely informational and optional -
+ it need not be included even if rail_assert libraries are included.
+
+ * @copyright Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
+ ******************************************************************************/
+
+#include "rail_types.h"
+
+/**
+ * @addtogroup Assertions
+ * @{
+ */
+
+#ifndef _RAIL_ASSERT_ERROR_CODES_
+
+#define _RAIL_ASSERT_ERROR_CODES_
+
+/**
+ * Enumeration of all possible error codes from RAIL_ASSERT
+ */
+RAIL_ENUM(RAIL_AssertErrorCodes_t)
+{
+ RAIL_ASSERT_FAILED_APPENDED_INFO_MISSING,
+ RAIL_ASSERT_FAILED_RX_FIFO_BYTES,
+ RAIL_ASSERT_FAILED_RX_FIFO_ZERO_BYTES_READ,
+ RAIL_ASSERT_FAILED_ILLEGAL_RXLEN_ENTRY_STATUS,
+ RAIL_ASSERT_FAILED_BAD_PACKET_LENGTH,
+ RAIL_ASSERT_FAILED_SYNTH_DIVCTRL_ENUM_CONVERSION_ERROR, //5
+ RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RX_FIFO,
+ RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO,
+ RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO,
+ RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO,
+ RAIL_ASSERT_FAILED_PBUFFER_NOT_DEFINED, //10
+ RAIL_ASSERT_FAILED_INSUFFICIENT_BYTES_IN_RX_PACKET,
+ RAIL_ASSERT_FAILED_CLOCK_PRESCALER,
+ RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP,
+ RAIL_ASSERT_FAILED_SYNTH_VCO_FREQUENCY,
+ RAIL_ASSERT_FAILED_RAC_STATE, //15
+ RAIL_ASSERT_FAILED_RETIME_LIMIT,
+ RAIL_ASSERT_FAILED_NESTED_SEQUENCER_LOCK,
+ RAIL_ASSERT_FAILED_RSSI_AVERAGE_DONE,
+ RAIL_ASSERT_FAILED_DFL_BITS_SIZE,
+ RAIL_ASSERT_FAILED_PROTIMER_RANDOM_SEED, //20
+ RAIL_ASSERT_FAILED_EFR32XG1_REGISTER_SIZE,
+ RAIL_ASSERT_FAILED_PROTIMER_CHANNEL,
+ RAIL_ASSERT_FAILED_TIMER_REQUIRES_WRAP,
+ RAIL_ASSERT_FAILED_BASECNTTOP,
+ RAIL_ASSERT_FAILED_DEPRECATED_LBTRETRY, //25
+ RAIL_ASSERT_FAILED_RTCC_SYNC_MISSED,
+ RAIL_ASSERT_FAILED_CLOCK_SOURCE_NOT_READY,
+ RAIL_ASSERT_FAILED_TIMINGS_INVALID,
+ RAIL_ASSERT_NULL_HANDLE,
+ RAIL_ASSERT_FAILED_TMRDRV_SCHED_TIMER_NOT_RUNNING, //30
+ RAIL_ASSERT_FAILED_NO_ACTIVE_CONFIG,
+ RAIL_ASSERT_FAILED_NO_ACTIVE_HANDLE_SWITCH,
+ RAIL_ASSERT_FAILED_RFINIT,
+ RAIL_ASSERT_FAILED_NO_ACTIVE_HANDLE_SCHEDRX,
+ RAIL_ASSERT_FAILED_INVALID_HANDLE_SCHEDTX, //35
+ RAIL_ASSERT_FAILED_INACTIVE_HANDLE_SCHEDTX,
+ RAIL_ASSERT_FAILED_CONFIG_INDEX_INVALID,
+ RAIL_ASSERT_FAILED_NO_ACTIVE_HANDLE_SINGLEPROTOCOL,
+ RAIL_ASSERT_DEPRECATED_FUNCTION,
+ RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT, //40
+ RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED,
+ RAIL_ASSERT_CONVERSION_CURVES_NOT_INITIALIZED,
+};
+
+/**
+ * Use this define to create an array of error messages that map to the codes
+ * in \ref RAIL_AssertErrorCodes_t. You can use these to print slightly more
+ * detailed error strings related to a particular assert error code if desired.
+ * For example, you could implement your assert failed callback as follows to
+ * make use of this.
+ *
+ * @code{.c}
+ * void RAILCb_AssertFailed(RAIL_Handle_t railHandle, uint32_t errorCode)
+ * {
+ * static const char* railErrorMessages[] = RAIL_ASSERT_ERROR_MESSAGES;
+ * const char *errorMessage = "Unknown";
+ *
+ * // If this error code is within the range of known error messages then use
+ * // the appropriate error message.
+ * if (errorCode < (sizeof(railErrorMessages) / sizeof(char*))) {
+ * errorMessage = railErrorMessages[errorCode];
+ * }
+ * printf(errorMessage);
+ *
+ * // Reset the chip since an assert is a fatal error
+ * NVIC_SystemReset();
+ * }
+ * @endcode
+ */
+#define RAIL_ASSERT_ERROR_MESSAGES { \
+ "Appended info missing from Rx packet", \
+ "Payload bytes missing from Rx packet", \
+ "Error reading back packet payload", \
+ "Receive fifo entry has invalid status", \
+ "Receive fifo entry bad packet length", \
+ "Unable to configure radio for IR calibration", \
+ "Reached unexpected state while handling Rx fifo events", \
+ "Reached unexpected state while handling RXLEN fifo events", \
+ "Reached unexpected state while handling Tx fifo events", \
+ "Reached unexpected state while handling Tx ACK fifo events", \
+ "No memory to store receive packet", \
+ "Packet length longer than the receive FIFO size", \
+ "Invalid radio clock prescaler", \
+ "Error synchronizing the RAIL timebase after sleep", \
+ "VCO frequency outside supported range", \
+ "Radio active while changing channels", \
+ "Unable to configure DCDC retiming", \
+ "Nested attempt to lock the sequencer", \
+ "RSSI averaging enabled without a valid callback", \
+ "Invalid dynamic frame length setting provided (dflBits)", \
+ "Unable to seed radio pseudo random number generator", \
+ "Timeout exceeds EFR32XG1 register size", \
+ "Invalid timer channel specified", \
+ "Timer value larger than RAIL timebase", \
+ "LBT config exceeds EFR32XG1 register size", \
+ "Deprecated CSMA/LBT retry callback unexpectedly called", \
+ "Could not synchronize RAIL timebase with the RTC", \
+ "Clock source not ready", \
+ "Attempted to set RAIL timings to invalid value", \
+ "NULL was supplied as a RAIL_Handle_t argument", \
+ "Scheduled timer not running", \
+ "No active config to switch from", \
+ "No active handle after switch", \
+ "RfInit failed to configure active state", \
+ "No active handle for scheduled rx", \
+ "Invalid handle for scheduled tx", \
+ "Inactive handle for scheduled tx", \
+ "Invalid config index to switch to", \
+ "No active handle for single protocol", \
+ "This function is deprecated and must not be called", \
+ "Multiprotocol task started with no event to run", \
+ "Invalid interrupt enabled", \
+ "Power conversion functions called before curves were initialized", \
+}
+
+#endif
+/**
+ * @}
+ */
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_chip_specific.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_chip_specific.h Thu Dec 07 14:01:42 2017 +0000
@@ -13,18 +13,36 @@
#include <stdbool.h>
#include <stddef.h>
+#include "em_gpio.h"
+
+#include "rail_types.h"
+
+// -----------------------------------------------------------------------------
+// Multiprotocol
+// -----------------------------------------------------------------------------
+/**
+ * @addtogroup Multiprotocol_EFR32 EFR32
+ * @{
+ * @brief EFR32 Specific multiprotocol support defines
+ * @ingroup Multiprotocol
+ */
+
+/**
+ * Placeholder for a chip specific RAIL handle. Using NULL as a RAIL handle is
+ * frowned upon, so we use another value that can't be de-referenced.
+ */
+#define RAIL_EFR32_HANDLE ((RAIL_Handle_t)0xFFFFFFFFUL)
+
+/** @} */ // end of group Multiprotocol_EFR32
+
// -----------------------------------------------------------------------------
// Calibration
// -----------------------------------------------------------------------------
/**
- * @addtogroup Calibration
- * @{
- */
-
-/**
- * @addtogroup EFR32
+ * @addtogroup Calibration_EFR32 EFR32
* @{
* @brief EFR32 Specific Calibrations
+ * @ingroup Calibration
*
* The EFR32 has two supported calibrations. There is the Image Rejection (IR)
* calibration and a temperature dependent calibration. The IR calibration is
@@ -38,11 +56,31 @@
* calibration exceeds 70C while sitting in receive. RAIL will run VCO
* calibration automatically upon entering receive state so the application can
* omit this calibration if the stack will re-enter receive with enough
- * frequency to not hit this temperature delta. If the application does not
+ * frequency to not hit this temperature delta. If the application does not
* calibrate for temperature, it's possible to miss receive packets due to
* drift in the carrier frequency.
*/
+/** EFR32 specific temperature calibration bit */
+#define RAIL_CAL_TEMP_VCO (0x00000001)
+/** EFR32 specific IR calibration bit */
+#define RAIL_CAL_ONETIME_IRCAL (0x00010000)
+
+/** Mask to run temperature dependent calibrations */
+#define RAIL_CAL_TEMP (RAIL_CAL_TEMP_VCO)
+/** Mask to run one time calibrations */
+#define RAIL_CAL_ONETIME (RAIL_CAL_ONETIME_IRCAL)
+/** Mask to run optional performance calibrations */
+#define RAIL_CAL_PERF (0)
+/** Mask for calibrations that require the radio to be off */
+#define RAIL_CAL_OFFLINE (RAIL_CAL_ONETIME_IRCAL)
+/** Mask to run all possible calibrations for this chip */
+#define RAIL_CAL_ALL (RAIL_CAL_TEMP | RAIL_CAL_ONETIME)
+/** Mask to run all pending calibrations */
+#define RAIL_CAL_ALL_PENDING (0x00000000)
+/** Invalid calibration value */
+#define RAIL_CAL_INVALID_VALUE (0xFFFFFFFF)
+
/**
* @struct RAIL_CalValues_t
* @brief Calibration value structure
@@ -56,40 +94,221 @@
uint32_t imageRejection; /**< Image Rejection (IR) calibration value */
} RAIL_CalValues_t;
-/** Invalid calibration value */
-#define RAIL_CAL_INVALID_VALUE (0xFFFFFFFF)
-
/**
* A define to set all RAIL_CalValues_t values to uninitialized.
*
* This define can be used when you have no data to pass to the calibration
* routines but wish to compute and save all possible calibrations.
*/
-#define RAIL_CALVALUES_UNINIT { \
- RAIL_CAL_INVALID_VALUE, \
+#define RAIL_CALVALUES_UNINIT (RAIL_CalValues_t){ \
+ RAIL_CAL_INVALID_VALUE, \
}
-/** EFR32 specific temperature calibration bit */
-#define RAIL_CAL_TEMP_VCO (0x00000001)
-/** EFR32 specific IR calibration bit */
-#define RAIL_CAL_ONETIME_IRCAL (0x00010000)
+/** @} */ // end of group Calibration_EFR32
+
+// -----------------------------------------------------------------------------
+// Diagnostic
+// -----------------------------------------------------------------------------
+/**
+ * @addtogroup Diagnostic_EFR32 EFR32
+ * @{
+ * @brief Types specific to the EFR32 for the diagnostic routines.
+ * @ingroup Diagnostic
+ */
+
+/**
+ * @typedef RAIL_FrequencyOffset_t
+ * @brief Chip-specific type that represents the number of Frequency Offset
+ * units. It is used with \ref RAIL_GetRxFreqOffset() and
+ * \ref RAIL_SetFreqOffset().
+ *
+ * The units on this chip are radio synthesizer resolution steps (synthTicks).
+ * On EFR32 (at least for now), the frequency offset is limited to 15 bits
+ * (size of SYNTH_CALOFFSET). A value of \ref RAIL_FREQUENCY_OFFSET_INVALID
+ * means that this value is invalid.
+ */
+typedef int16_t RAIL_FrequencyOffset_t;
+
+/**
+ * Specifies an invalid frequency offset value. This will be returned if you
+ * call \ref RAIL_GetRxFreqOffset() at an invalid time.
+ */
+#define RAIL_FREQUENCY_OFFSET_INVALID ((int16_t)0xFFFF)
+
+/** @} */ // end of group Diagnostic_EFR32
-/** Mask to run temperature dependent calibrations */
-#define RAIL_CAL_TEMP (RAIL_CAL_TEMP_VCO)
-/** Mask to run one time calibrations */
-#define RAIL_CAL_ONETIME (RAIL_CAL_ONETIME_IRCAL)
-/** Mask to run optional performance calibrations */
-#define RAIL_CAL_PERF ()
-/** Mask for calibrations that require the radio to be off */
-#define RAIL_CAL_OFFLINE (RAIL_CAL_ONETIME_IRCAL)
-/** Mask to run all possible calibrations for this chip */
-#define RAIL_CAL_ALL (RAIL_CAL_TEMP | RAIL_CAL_ONETIME)
-/** Mask to run all pending calibrations */
-#define RAIL_CAL_ALL_PENDING (0x00000000)
+// -----------------------------------------------------------------------------
+// Radio Configuration
+// -----------------------------------------------------------------------------
+/**
+ * @addtogroup Radio_Configuration_EFR32 EFR32
+ * @{
+ * @ingroup Radio_Configuration
+ * @brief Types specific to the EFR32 for radio configuration.
+ */
+
+/**
+ * @brief Radio Configuration structure
+ *
+ * The radio configuration is generated in order to properly configure the
+ * radio for operation on a protocol. These configurations should not be
+ * created or edited by hand.
+ */
+typedef const uint32_t *RAIL_RadioConfig_t;
+
+/** @} */ // end of group Radio_Configuration_EFR32
+
+// -----------------------------------------------------------------------------
+// Transmit
+// -----------------------------------------------------------------------------
+/**
+ * @addtogroup PA_EFR32 EFR32
+ * @{
+ * @ingroup PA
+ * @brief Types specific to the EFR32 for dealing with the on chip PAs.
+ */
+
+/**
+ * Raw power levels used directly by the RAIL_Get/SetTxPower API where a higher
+ * numerical value corresponds to a higher output power. These are referred to
+ * as 'raw (values/units)'. On the EFR32 they can range from one of \ref
+ * RAIL_TX_POWER_LEVEL_LP_MIN, \ref RAIL_TX_POWER_LEVEL_HP_MIN, or
+ * \ref RAIL_TX_POWER_LEVEL_SUBGIG_MIN to one of \ref
+ * RAIL_TX_POWER_LEVEL_LP_MAX, \ref RAIL_TX_POWER_LEVEL_HP_MAX, and \ref
+ * RAIL_TX_POWER_LEVEL_SUBGIG_MAX, respectively, depending on the selected \ref
+ * RAIL_TxPowerMode_t.
+ */
+typedef uint8_t RAIL_TxPowerLevel_t;
/**
- * @}
- * @}
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_LP_MAX 7
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_HP_MAX 252
+/**
+ * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_MAX 248
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4_LP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_HP_MIN 0
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_2P4_HP mode.
+ */
+#define RAIL_TX_POWER_LEVEL_LP_MIN 1
+/**
+ * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref
+ * RAIL_TX_POWER_MODE_SUBGIG mode.
+ */
+#define RAIL_TX_POWER_LEVEL_SUBGIG_MIN 0
+/**
+ * Invalid RAIL_TxPowerLevel_t value returned when there is an error
+ * with RAIL_GetTxPower
+ */
+#define RAIL_TX_POWER_LEVEL_INVALID 255
+
+/**
+ * @enum RAIL_TxPowerMode_t
+ * @brief Enumeration of the EFR32 power modes.
+ *
+ * The power modes on the EFR32 correspond to the different on-chip PA's that
+ * are available. For more information about the power and performance
+ * characteristics of a given amplifier, please consult the data sheet.
+ */
+RAIL_ENUM(RAIL_TxPowerMode_t) {
+ /** High power amplifier, up to 20dBm, raw values: 0-252 */
+ RAIL_TX_POWER_MODE_2P4_HP,
+ /** Low power amplifier, up to 0dBm, raw values: 1-7 */
+ RAIL_TX_POWER_MODE_2P4_LP,
+ /** SubGig amplifier, up to 20dBm, raw values: 0-248 */
+ RAIL_TX_POWER_MODE_SUBGIG,
+ /** Invalid amplifier Selection */
+ RAIL_TX_POWER_MODE_NONE
+};
+
+/**
+ * @struct RAIL_TxPowerConfig_t
+ *
+ * @brief Structure containing values used to initialize the power amplifiers.
+ */
+typedef struct RAIL_TxPowerConfig {
+ /** Tx power mode */
+ RAIL_TxPowerMode_t mode;
+ /** Power amplifier supply voltage in mV, generally:
+ * DCDC supply ~ 1800mV (1.8V)
+ * Battery supply ~ 3300mV (3.3V)
+ */
+ uint16_t voltage;
+ /** The amount of time to spend ramping for Tx in uS. */
+ uint16_t rampTime;
+} RAIL_TxPowerConfig_t;
+
+/** @} */ // end of group PA_EFR32
+
+// -----------------------------------------------------------------------------
+// PTI
+// -----------------------------------------------------------------------------
+/**
+ * @addtogroup PTI_EFR32 EFR32
+ * @{
+ * @brief EFR32 PTI functionality
+ * @ingroup PTI
+ *
+ * These enums and structures are used with RAIL PTI API. EFR32 supports
+ * SPI and UART PTI, and is configurable in terms of baud rates and pin PTI
+ * pin locations.
*/
+/** Channel type enumeration. */
+RAIL_ENUM(RAIL_PtiMode_t) {
+ /** Turn PTI off entirely */
+ RAIL_PTI_MODE_DISABLED,
+ /** SPI mode. */
+ RAIL_PTI_MODE_SPI,
+ /** UART mode. */
+ RAIL_PTI_MODE_UART,
+ /** 9bit UART mode. */
+ RAIL_PTI_MODE_UART_ONEWIRE
+};
+
+/**
+ * @struct RAIL_PtiConfig_t
+ * @brief Configuration for PTI.
+ */
+typedef struct RAIL_PtiConfig {
+ /** Packet Trace mode (UART or SPI) */
+ RAIL_PtiMode_t mode;
+ /** Output baudrate for PTI in Hz */
+ uint32_t baud;
+ /** Data output (DOUT) location for pin/port */
+ uint8_t doutLoc;
+ /** Data output (DOUT) GPIO port */
+ GPIO_Port_TypeDef doutPort;
+ /** Data output (DOUT) GPIO pin */
+ uint8_t doutPin;
+ /** Data clock (DCLK) location for pin/port. Only used in SPI mode */
+ uint8_t dclkLoc;
+ /** Data clock (DCLK) GPIO port. Only used in SPI mode */
+ GPIO_Port_TypeDef dclkPort;
+ /** Data clock (DCLK) GPIO pin. Only used in SPI mode */
+ uint8_t dclkPin;
+ /** Data frame (DFRAME) location for pin/port. Only used for */
+ uint8_t dframeLoc;
+ /** Data frame (DFRAME) GPIO port */
+ GPIO_Port_TypeDef dframePort;
+ /** Data frame (DFRAME) GPIO pin */
+ uint8_t dframePin;
+} RAIL_PtiConfig_t;
+
+/** @} */ // end of group PTI_EFR32
+
#endif
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_types.h Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_types.h Thu Dec 07 14:01:42 2017 +0000
@@ -1,9 +1,9 @@
-/***************************************************************************//**
+/**************************************************************************//**
* @file rail_types.h
* @brief This file contains the type definitions for RAIL structures, enums,
* and other types.
- * @copyright Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com
- ******************************************************************************/
+ * @copyright Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
+ *****************************************************************************/
#ifndef __RAIL_TYPES_H__
#define __RAIL_TYPES_H__
@@ -13,47 +13,485 @@
#include <stdbool.h>
#include <stddef.h>
-#include "rail_chip_specific.h"
+#ifdef DOXYGEN_SHOULD_SKIP_THIS
+/// The RAIL library does not use enums because the ARM EABI leaves their
+/// size ambiguous. This ambiguity causes problems if the application is built
+/// with different flags than the library. Instead, uint8_t typedefs
+/// are used in compiled code for all enums. For documentation purposes this is
+/// converted to an actual enum since it's much easier to read in Doxygen.
+#define RAIL_ENUM(name) enum name
+/// This macro is a more generic version of the \ref RAIL_ENUM() macro that
+/// allows the size of the type to be overridden instead of forcing the use of
+/// a uint8_t. See \ref RAIL_ENUM() for more information about why RAIL enums
+/// are defined using these.
+#define RAIL_ENUM_GENERIC(name, type) enum name
+#else
+/// Define used for the RAIL library, which sets each enum to a uint8_t
+/// typedef and creates a named enum structure for the enumeration values.
+#define RAIL_ENUM(name) typedef uint8_t name; enum name##_enum
+#define RAIL_ENUM_GENERIC(name, type) typedef type name; enum name##_enum
+// For debugging use the following define to turn this back into a proper enum
+// #define RAIL_ENUM(name) typedef enum name##_enum name; enum name##_enum
+#endif
/**
* @addtogroup RAIL_API
* @{
*/
-// -----------------------------------------------------------------------------
-// Calibration Structures
-// -----------------------------------------------------------------------------
+/******************************************************************************
+ * Multiprotocol Structures
+ *****************************************************************************/
+/**
+ * @addtogroup Multiprotocol
+ * @{
+ */
+
+/**
+ * @def RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE
+ * @brief The size in 32-bit words of RAIL_SchedulerStateBuffer_t to store
+ * RAIL multiprotocol internal state.
+ */
+#define RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE 25
+
+/**
+ * @typedef RAIL_SchedulerStateBuffer_t
+ * @brief Buffer used to store multiprotocol scheduler internal state.
+ *
+ * This buffer must be allocated in application global read-write memory
+ * that persists for the duration of RAIL usage. It cannot be allocated
+ * in read-only memory or on the call stack.
+ */
+typedef uint32_t RAIL_SchedulerStateBuffer_t[RAIL_SCHEDULER_STATE_UINT32_BUFFER_SIZE];
+
+/**
+ * @struct RAILSched_Config_t
+ * @brief Multiprotocol scheduler configuration and internal state.
+ *
+ * This buffer must be allocated in application global read-write memory
+ * that persists for the duration of RAIL usage. It cannot be allocated
+ * in read-only memory or on the call stack.
+ */
+typedef struct RAILSched_Config {
+ RAIL_SchedulerStateBuffer_t buffer; /**< Internal state buffer. */
+} RAILSched_Config_t;
+
+/**
+ * @struct RAIL_SchedulerInfo_t
+ * @brief A structure to hold information used by the scheduler.
+ *
+ * For multiprotocol versions of RAIL this can be used to control how a receive
+ * or transmit operation is run. In single protocol applications it's not
+ * necessary.
+ */
+typedef struct RAIL_SchedulerInfo {
+ /**
+ * The priority for this operation in the scheduler. This priority is used to
+ * preempt a long running lower priority task to ensure higher priority
+ * operations complete in time. A lower numerical value represents a higher
+ * logical priority meaning 0 is the highest priority and 255 is the lowest.
+ */
+ uint8_t priority;
+ /**
+ * The amount of time in us that this operation can slip by into the future
+ * and still be run. This time is relative to the start time which may be
+ * the current time for relative transmits. If we cannot start by this time
+ * the operation will be considered a failure.
+ */
+ uint32_t slipTime;
+ /**
+ * The transaction time in us for this operation. Since transaction times may
+ * not be known exactly you will likely want to use a minimum or expected
+ * guess for this time. The scheduler will use the value entered here to look
+ * for overlaps between low priority and high priority tasks and attempt to
+ * find a schedule where all tasks get to run.
+ */
+ uint32_t transactionTime;
+} RAIL_SchedulerInfo_t;
+
/**
- * @addtogroup Calibration
+ * @enum RAIL_SchedulerStatus_t
+ * @brief Multiprotocol scheduler status returned by RAIL_GetSchedulerStatus().
+ */
+RAIL_ENUM(RAIL_SchedulerStatus_t) {
+ /** Multiprotocol scheduler reports no error */
+ RAIL_SCHEDULER_STATUS_NO_ERROR,
+ /**
+ * The scheduler is disabled or the requested scheduler operation is
+ * unsupported.
+ */
+ RAIL_SCHEDULER_STATUS_UNSUPPORTED,
+ /**
+ * The scheduled event was started but was interrupted by a higher priority
+ * event before it could be completed.
+ */
+ RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED,
+ /**
+ * This task could not be scheduled given its priority and the other tasks
+ * running on the system.
+ */
+ RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL,
+ /**
+ * Calling the scheduled transmit function returned an error code. See
+ * RAIL_StartScheduledTx() for more information about possible errors.
+ */
+ RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL,
+ /**
+ * Calling the start transmit function returned an error code. See
+ * RAIL_StartTx() for more information about possible errors.
+ */
+ RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL,
+ /**
+ * Calling the CSMA transmit function returned an error code. See
+ * RAIL_StartCcaCsmaTx() for more information about possible errors.
+ */
+ RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL,
+ /**
+ * Calling the LBT transmit function returned an error code. See
+ * RAIL_StartCcaLbtTx() for more information about possible errors.
+ */
+ RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL,
+ /**
+ * Calling the scheduled receive function returned an error code. This likely
+ * means that we were a little too late and could not setup the hardware in
+ * time to do this receive.
+ */
+ RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL,
+ /**
+ * Calling the stream transmit function returned an error code. See
+ * RAIL_StartTxStream() for more information about possible errors.
+ */
+ RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL,
+ /**
+ * RSSI averaging failed. If this scheduler status occurs
+ * RAIL_GetAverageRssi will return \ref RAIL_RSSI_INVALID until
+ * a RAIL_StartAverageRssi completes successfully.
+ */
+ RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL,
+ /**
+ * There was an internal error in the scheduler data structures. This should
+ * not happen and indicates a problem if seen.
+ */
+ RAIL_SCHEDULER_STATUS_INTERNAL_ERROR,
+};
+
+/** @} */ // end of group Multiprotocol
+
+/******************************************************************************
+ * Event Structures
+ *****************************************************************************/
+/**
+ * @addtogroup Events
* @{
*/
/**
- * @typedef RAIL_CalMask_t
- * @brief Calibration mask type
- *
- * This type is a bitmask of different RAIL calibration values. The exact
- * meaning of these bits depends on what your particular chip supports.
+ * @enum RAIL_Events_t
+ * @brief RAIL events passed to event callback. More than one event may be
+ * indicated due to interrupt latency.
*/
-typedef uint32_t RAIL_CalMask_t;
+RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) {
+ /** Value representing no events */
+ RAIL_EVENTS_NONE = 0,
+
+ // RX Event Bit Shifts
+
+ /** Shift position of \ref RAIL_EVENT_RSSI_AVERAGE_DONE bit */
+ RAIL_EVENT_RSSI_AVERAGE_DONE_SHIFT = 0,
+ /** Shift position of \ref RAIL_EVENT_RX_ACK_TIMEOUT bit */
+ RAIL_EVENT_RX_ACK_TIMEOUT_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL bit */
+ RAIL_EVENT_RX_FIFO_ALMOST_FULL_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_RX_PACKET_RECEIVED bit */
+ RAIL_EVENT_RX_PACKET_RECEIVED_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_RX_PREAMBLE_DETECT bit */
+ RAIL_EVENT_RX_PREAMBLE_DETECT_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_RX_SYNC1_DETECT bit */
+ RAIL_EVENT_RX_SYNC1_DETECT_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_RX_SYNC2_DETECT bit */
+ RAIL_EVENT_RX_SYNC2_DETECT_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_RX_FRAME_ERROR bit */
+ RAIL_EVENT_RX_FRAME_ERROR_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_RX_FIFO_OVERFLOW bit */
+ RAIL_EVENT_RX_FIFO_OVERFLOW_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_RX_ADDRESS_FILTERED bit */
+ RAIL_EVENT_RX_ADDRESS_FILTERED_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_RX_TIMEOUT bit */
+ RAIL_EVENT_RX_TIMEOUT_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_RX_SCHEDULED_RX_END bit */
+ RAIL_EVENT_RX_SCHEDULED_RX_END_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_RX_PACKET_ABORTED bit */
+ RAIL_EVENT_RX_PACKET_ABORTED_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_RX_FILTER_PASSED bit */
+ RAIL_EVENT_RX_FILTER_PASSED_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_RX_TIMING_LOST bit */
+ RAIL_EVENT_RX_TIMING_LOST_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_RX_TIMING_DETECT bit */
+ RAIL_EVENT_RX_TIMING_DETECT_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND bit */
+ RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT,
+
+ // TX Event Bit Shifts
+
+ /** Shift position of \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY bit */
+ RAIL_EVENT_TX_FIFO_ALMOST_EMPTY_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_TX_PACKET_SENT bit */
+ RAIL_EVENT_TX_PACKET_SENT_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_TXACK_PACKET_SENT bit */
+ RAIL_EVENT_TXACK_PACKET_SENT_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_TX_ABORTED bit */
+ RAIL_EVENT_TX_ABORTED_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_TXACK_ABORTED bit */
+ RAIL_EVENT_TXACK_ABORTED_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_TX_BLOCKED bit */
+ RAIL_EVENT_TX_BLOCKED_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_TXACK_BLOCKED bit */
+ RAIL_EVENT_TXACK_BLOCKED_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_TX_UNDERFLOW bit */
+ RAIL_EVENT_TX_UNDERFLOW_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_TXACK_UNDERFLOW bit */
+ RAIL_EVENT_TXACK_UNDERFLOW_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_TX_CHANNEL_CLEAR bit */
+ RAIL_EVENT_TX_CHANNEL_CLEAR_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_TX_CHANNEL_BUSY bit */
+ RAIL_EVENT_TX_CHANNEL_BUSY_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_TX_CCA_RETRY bit */
+ RAIL_EVENT_TX_CCA_RETRY_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_TX_START_CCA bit */
+ RAIL_EVENT_TX_START_CCA_SHIFT,
+
+ // Scheduler Event Bit Shifts
+
+ /** Shift position of \ref RAIL_EVENT_CONFIG_UNSCHEDULED bit */
+ RAIL_EVENT_CONFIG_UNSCHEDULED_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_CONFIG_SCHEDULED bit */
+ RAIL_EVENT_CONFIG_SCHEDULED_SHIFT,
+ /** Shift position of \ref RAIL_EVENT_SCHEDULER_STATUS bit */
+ RAIL_EVENT_SCHEDULER_STATUS_SHIFT,
+
+ // Other Event Bit Shifts
+
+ /** Shift position of \ref RAIL_EVENT_CAL_NEEDED bit */
+ RAIL_EVENT_CAL_NEEDED_SHIFT,
+
+ // RX Event Bitmasks
+
+ /**
+ * Occurs when the AGC averaged RSSI is done.
+ * It occurs in response to RAIL_StartAverageRssi() to indicate that the
+ * hardware has completed averaging. Call \ref RAIL_GetAverageRssi to get the
+ * result.
+ */
+ RAIL_EVENT_RSSI_AVERAGE_DONE
+ = (1ull << RAIL_EVENT_RSSI_AVERAGE_DONE_SHIFT),
+ /**
+ * Notifies the application when searching for an ACK has timed
+ * out. This event occurs whenever the timeout for searching for an
+ * ACK is exceeded.
+ */
+ RAIL_EVENT_RX_ACK_TIMEOUT
+ = (1ull << RAIL_EVENT_RX_ACK_TIMEOUT_SHIFT),
+ /**
+ * Occurs when the receive FIFO exceeds the configured threshold
+ * value. Call \ref RAIL_GetRxFifoBytesAvailable to get the number of bytes
+ * available.
+ */
+ RAIL_EVENT_RX_FIFO_ALMOST_FULL
+ = (1ull << RAIL_EVENT_RX_FIFO_ALMOST_FULL_SHIFT),
+ /**
+ * Occurs whenever a packet is received.
+ * Call RAIL_GetRxPacketInfo() to get basic packet information along
+ * with a handle to this packet for subsequent use with
+ * RAIL_PeekRxPacket(), RAIL_GetRxPacketDetails(),
+ * RAIL_HoldRxPacket(), and RAIL_ReleaseRxPacket() as needed.
+ *
+ * If \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS is set, this event also occurs
+ * for packets with CRC errors.
+ */
+ RAIL_EVENT_RX_PACKET_RECEIVED
+ = (1ull << RAIL_EVENT_RX_PACKET_RECEIVED_SHIFT),
+ /** Event for preamble detection */
+ RAIL_EVENT_RX_PREAMBLE_DETECT
+ = (1ull << RAIL_EVENT_RX_PREAMBLE_DETECT_SHIFT),
+ /** Event for detection of the first sync word */
+ RAIL_EVENT_RX_SYNC1_DETECT
+ = (1ull << RAIL_EVENT_RX_SYNC1_DETECT_SHIFT),
+ /** Event for detection of the second sync word */
+ RAIL_EVENT_RX_SYNC2_DETECT
+ = (1ull << RAIL_EVENT_RX_SYNC2_DETECT_SHIFT),
+ /** Event for detection of frame errors
+ *
+ * For efr32xg1x parts, frame errors include violations of variable length
+ * minimum/maximum limits, frame coding errors, and CRC errors. If \ref
+ * RAIL_RX_OPTION_IGNORE_CRC_ERRORS is set, \ref RAIL_EVENT_RX_FRAME_ERROR
+ * will not occur for CRC errors.
+ */
+ RAIL_EVENT_RX_FRAME_ERROR
+ = (1ull << RAIL_EVENT_RX_FRAME_ERROR_SHIFT),
+ /** Occurs when RX buffer is full */
+ RAIL_EVENT_RX_FIFO_OVERFLOW
+ = (1ull << RAIL_EVENT_RX_FIFO_OVERFLOW_SHIFT),
+ /** Occurs when a packet is address filtered */
+ RAIL_EVENT_RX_ADDRESS_FILTERED
+ = (1ull << RAIL_EVENT_RX_ADDRESS_FILTERED_SHIFT),
+ /** Occurs when an RX event times out */
+ RAIL_EVENT_RX_TIMEOUT
+ = (1ull << RAIL_EVENT_RX_TIMEOUT_SHIFT),
+ /** Occurs when the scheduled RX window ends */
+ RAIL_EVENT_RX_SCHEDULED_RX_END
+ = (1ull << RAIL_EVENT_RX_SCHEDULED_RX_END_SHIFT),
+ /** An event for an aborted packet. It is triggered when a more specific
+ * reason isn't known for why the packet was aborted (e.g.
+ * \ref RAIL_EVENT_RX_ADDRESS_FILTERED). */
+ RAIL_EVENT_RX_PACKET_ABORTED
+ = (1ull << RAIL_EVENT_RX_PACKET_ABORTED_SHIFT),
+ /**
+ * Occurs when the packet has passed any configured address and frame
+ * filtering options.
+ */
+ RAIL_EVENT_RX_FILTER_PASSED
+ = (1ull << RAIL_EVENT_RX_FILTER_PASSED_SHIFT),
+ /** Occurs when modem timing is lost */
+ RAIL_EVENT_RX_TIMING_LOST
+ = (1ull << RAIL_EVENT_RX_TIMING_LOST_SHIFT),
+ /** Occurs when modem timing is detected */
+ RAIL_EVENT_RX_TIMING_DETECT
+ = (1ull << RAIL_EVENT_RX_TIMING_DETECT_SHIFT),
+ /**
+ * Indicates a Data Request is being received when using IEEE 802.15.4
+ * functionality. This occurs when the command byte of an incoming frame is
+ * for a data request, which requests an ACK. This callback is called before
+ * the packet is fully received to allow the node to have more time to decide
+ * whether to set the frame pending in the outgoing ACK. This event only ever
+ * occurs if the RAIL IEEE 802.15.4 functionality is enabled.
+ *
+ * Call \ref RAIL_IEEE802154_GetAddress to get the source address of the
+ * packet.
+ */
+ RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND
+ = (1ull << RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT),
+
+ // TX Event Bitmasks
+
+ /**
+ * Occurs when the transmit FIFO falls under the configured
+ * threshold value. It only occurs if a rising edge occurs across this
+ * threshold. This event does not occur on initailization or after resetting
+ * the transmit FIFO with RAIL_ResetFifo().
+ * Call \ref RAIL_GetTxFifoSpaceAvailable to get the number of bytes
+ * available in the transmit FIFO at the time of the callback dispatch.
+ */
+ RAIL_EVENT_TX_FIFO_ALMOST_EMPTY
+ = (1ull << RAIL_EVENT_TX_FIFO_ALMOST_EMPTY_SHIFT),
+ /**
+ * Interrupt level event to signify when the packet was sent.
+ * Call RAIL_GetTxPacketDetails() to get information about the packet
+ * that was transmitted.
+ * @note that this structure is only valid during the timeframe of the
+ * \ref RAIL_Config_t::eventsCallback.
+ */
+ RAIL_EVENT_TX_PACKET_SENT
+ = (1ull << RAIL_EVENT_TX_PACKET_SENT_SHIFT),
+ /**
+ * An interrupt level event to signify when the packet was sent.
+ * Call RAIL_GetTxPacketDetails() to get information about the packet
+ * that was transmitted.
+ * @note This structure is only valid during the timeframe of the
+ * \ref RAIL_Config_t::eventsCallback.
+ */
+ RAIL_EVENT_TXACK_PACKET_SENT
+ = (1ull << RAIL_EVENT_TXACK_PACKET_SENT_SHIFT),
+ /** Occurs when a TX is aborted by the user */
+ RAIL_EVENT_TX_ABORTED
+ = (1ull << RAIL_EVENT_TX_ABORTED_SHIFT),
+ /** Occurs when a TX ACK is aborted by the user */
+ RAIL_EVENT_TXACK_ABORTED
+ = (1ull << RAIL_EVENT_TXACK_ABORTED_SHIFT),
+ /** Occurs when a TX is blocked by something like PTA or RHO */
+ RAIL_EVENT_TX_BLOCKED
+ = (1ull << RAIL_EVENT_TX_BLOCKED_SHIFT),
+ /** Occurs when a TX ACK is blocked by something like PTA or RHO */
+ RAIL_EVENT_TXACK_BLOCKED
+ = (1ull << RAIL_EVENT_TXACK_BLOCKED_SHIFT),
+ /** Occurs when the TX buffer underflows */
+ RAIL_EVENT_TX_UNDERFLOW
+ = (1ull << RAIL_EVENT_TX_UNDERFLOW_SHIFT),
+ /** Occurs when the buffer used for TX acking underflows */
+ RAIL_EVENT_TXACK_UNDERFLOW
+ = (1ull << RAIL_EVENT_TXACK_UNDERFLOW_SHIFT),
+ /** Occurs when CCA/CSMA/LBT succeeds */
+ RAIL_EVENT_TX_CHANNEL_CLEAR
+ = (1ull << RAIL_EVENT_TX_CHANNEL_CLEAR_SHIFT),
+ /** Occurs when CCA/CSMA/LBT fails */
+ RAIL_EVENT_TX_CHANNEL_BUSY
+ = (1ull << RAIL_EVENT_TX_CHANNEL_BUSY_SHIFT),
+ /** Occurs when a CCA check is being retried */
+ RAIL_EVENT_TX_CCA_RETRY
+ = (1ull << RAIL_EVENT_TX_CCA_RETRY_SHIFT),
+ /** Occurs when a clear channel assessment (CCA) is begun */
+ RAIL_EVENT_TX_START_CCA
+ = (1ull << RAIL_EVENT_TX_START_CCA_SHIFT),
+
+ // Scheduler Event Bitmasks
+
+ /** Event for when the scheduler switches away from this configuration */
+ RAIL_EVENT_CONFIG_UNSCHEDULED
+ = (1ull << RAIL_EVENT_CONFIG_UNSCHEDULED_SHIFT),
+ /** Event for when the scheduler switches to this configuration */
+ RAIL_EVENT_CONFIG_SCHEDULED
+ = (1ull << RAIL_EVENT_CONFIG_SCHEDULED_SHIFT),
+ /** Event for when the status of the scheduler changes */
+ RAIL_EVENT_SCHEDULER_STATUS
+ = (1ull << RAIL_EVENT_SCHEDULER_STATUS_SHIFT),
+
+ // Other Event Bitmasks
+
+ /**
+ * Notifies the application that a calibration is needed.
+ * It occurs whenever the RAIL library detects that a
+ * calibration is needed. An application determines a valid
+ * window to call \ref RAIL_Calibrate().
+ */
+ RAIL_EVENT_CAL_NEEDED
+ = (1ull << RAIL_EVENT_CAL_NEEDED_SHIFT),
+
+ /** Value representing all possible events */
+ RAIL_EVENTS_ALL = 0xFFFFFFFFFFFFFFFFULL
+};
+
+/** @} */ // end of group Events
/**
- * @struct RAIL_CalInit_t
- * @brief Initialization structure for RAIL calibrations.
+ * @addtogroup PA Power Amplifier (PA)
+ * @ingroup Transmit
+ * @{
*/
-typedef struct RAIL_CalInit {
- RAIL_CalMask_t calEnable; /**< Mask that defines calibrations to perform in RAIL. */
- const uint8_t *irCalSettings; /**< Pointer to image rejection calibration settings. */
-} RAIL_CalInit_t;
/**
- * @}
+ * The transmit power in deci-dBm units (e.g. 4.5dBm -> 45 deci-dBm). These
+ * values are used by the conversion functions to convert a \ref
+ * RAIL_TxPowerLevel_t to deci-dBm for application consumption. On the EFR32
+ * they can range from \ref RAIL_TX_POWER_MIN to \ref RAIL_TX_POWER_MAX.
*/
+typedef int16_t RAIL_TxPower_t;
+/** The maximum valid value for a \ref RAIL_TxPower_t. */
+#define RAIL_TX_POWER_MAX ((RAIL_TxPower_t)0x7FFF)
+/** The minimum valid value for a \ref RAIL_TxPower_t. */
+#define RAIL_TX_POWER_MIN ((RAIL_TxPower_t)0x8000)
-// -----------------------------------------------------------------------------
-// Radio Configuration Structures
-// -----------------------------------------------------------------------------
+/// mV are used for all TX power voltage values
+/// TX power voltages take and return voltages multiplied by this factor
+#define RAIL_TX_POWER_VOLTAGE_SCALING_FACTOR 1000
+/// deci-dBm are used for all TX power dBm values
+/// All dBm inputs to TX power functions take dBm power times this factor
+#define RAIL_TX_POWER_DBM_SCALING_FACTOR 10
+
+/** @} */ // PA Power Amplifier (PA)
+
+/******************************************************************************
+ * General Structures
+ *****************************************************************************/
/**
* @addtogroup General
* @{
@@ -61,112 +499,601 @@
/**
* @struct RAIL_Version_t
- * @brief Contains RAIL Library Version Information
+ * @brief Contains RAIL Library Version Information.
+ * It is filled in by RAIL_GetVersion().
*/
typedef struct RAIL_Version {
- uint32_t hash; /**< Git hash */
- uint8_t major; /**< Major number */
- uint8_t minor; /**< Minor number */
- uint8_t rev; /**< Revision number */
- uint8_t build; /**< Build number */
- uint8_t flags; /**< Build flags */
+ uint32_t hash; /**< Git hash */
+ uint8_t major; /**< Major number */
+ uint8_t minor; /**< Minor number */
+ uint8_t rev; /**< Revision number */
+ uint8_t build; /**< Build number */
+ uint8_t flags; /**< Build flags */
+ /** Boolean to indicate whether this is a multiprotocol library or not. */
+ bool multiprotocol;
} RAIL_Version_t;
/**
- * @struct RAIL_Init_t
- * @brief Initialization structure for the RAIL library.
+ * @typedef RAIL_Handle_t
+ * @brief Handle of a RAIL instance, as returned from RAIL_Init().
+ */
+typedef void *RAIL_Handle_t;
+
+/**
+ * @enum RAIL_Status_t
+ * @brief Status returned by many RAIL API calls indicating their success or
+ * failure.
+ */
+RAIL_ENUM(RAIL_Status_t) {
+ RAIL_STATUS_NO_ERROR, /**< RAIL function reports no error */
+ RAIL_STATUS_INVALID_PARAMETER, /**< Call to RAIL function threw an error
+ because of an invalid parameter */
+ RAIL_STATUS_INVALID_STATE, /**< Call to RAIL function threw an error
+ because it was called during an invalid
+ radio state */
+ RAIL_STATUS_INVALID_CALL, /**< The function is called in an invalid order */
+};
+
+/**
+ * @def RAIL_STATE_UINT32_BUFFER_SIZE
+ * @brief The size, in 32-bit words, of RAIL_StateBuffer_t to store RAIL
+ * internal state.
+ */
+#define RAIL_STATE_UINT32_BUFFER_SIZE 54
+
+/**
+ * @typedef RAIL_StateBuffer_t
+ * @brief A buffer to store RAIL internal state.
+ */
+typedef uint32_t RAIL_StateBuffer_t[RAIL_STATE_UINT32_BUFFER_SIZE];
+
+/**
+ * @struct RAIL_Config_t
+ * @brief RAIL configuration and internal state structure.
+ *
+ * This structure must be allocated in application global read-write memory
+ * that persists for the duration of RAIL usage. It cannot be allocated
+ * in read-only memory or on the call stack.
+ */
+typedef struct RAIL_Config {
+ /**
+ * Pointer to function called whenever a RAIL event occurs.
+ *
+ * @param[in] railHandle A handle for RAIL instance.
+ * @param[in] events A bit mask of RAIL events.
+ * @return void.
+ *
+ * See the \ref RAIL_Events_t documentation for the list of RAIL events.
+ */
+ void (*eventsCallback)(RAIL_Handle_t railHandle, RAIL_Events_t events);
+ /**
+ * Pointer to a protocol-specific state structure allocated in global
+ * read-write memory and initialized to all zeros.
+ * For the BLE protocol this should point to a RAIL_BLE_State_t
+ * structure. For IEEE802154 this should be NULL.
+ */
+ void *protocol;
+ /**
+ * Pointer to a RAIL scheduler state object allocated in global read-write
+ * memory and initialized to all zeros. When not using a multiprotocol
+ * scheduler, this should be NULL.
+ */
+ RAILSched_Config_t *scheduler;
+ /**
+ * A structure for RAIL to maintain its internal state, which must be
+ * initialized to all zeros.
+ */
+ RAIL_StateBuffer_t buffer;
+} RAIL_Config_t;
+
+/**
+ * A pointer to init complete callback function
+ *
+ * @param[in] railHandle A handle for RAIL instance.
+ * @return void.
+ *
+ */
+typedef void (*RAIL_InitCompleteCallbackPtr_t)(RAIL_Handle_t railHandle);
+
+/** @} */ // end of group General
+
+/******************************************************************************
+ * Radio Configuration Structures
+ *****************************************************************************/
+/**
+ * @addtogroup Radio_Configuration
+ * @{
+ */
+
+/**
+ * @struct RAIL_FrameType_t
+ * @brief Configure if there is a frame type in your frame and the lengths of
+ * each frame. The number of bits set in the mask determines the number of
+ * elements in frameLen. A maximum of 8 different frame types may be specified.
+ */
+typedef struct RAIL_FrameType {
+ /**
+ * Pointer to array of frame lengths for each frame type. The length of this
+ * array should be equal to the number of frame types. The array that
+ * frameLen points to should not change location or be modified.
+ */
+ uint16_t *frameLen;
+ /**
+ * Zero-indexed location of the byte containing the frame type field.
+ */
+ uint8_t offset;
+ /**
+ * Bit mask of the frame type field. Determines number of frames expected
+ * based on the number of bits set. No more than 3 bits can be set in mask.
+ * Must be contiguous ones. For example, if the highest three bits of the byte
+ * specified by offset constitute the frame type, then mask should be 0xE0,
+ * which has 3 bits set, indicating 8 possible frame types.
+ */
+ uint8_t mask;
+ /**
+ * Bitmask that marks if each frame is valid or should be filtered. Frame type
+ * 0 corresponds to the lowest bit in isValid. If the frame is filtered, a
+ * RAIL_EVENT_RX_PACKET_ABORTED will be raised.
+ */
+ uint8_t isValid;
+ /**
+ * Bitmask that marks if each frame should have the address filter applied.
+ * Frame type 0 corresponds to the least significant bit in addressFilter.
+ */
+ uint8_t addressFilter;
+} RAIL_FrameType_t;
+
+/**
+ * @def RAIL_SETFIXEDLENGTH_INVALID
+ * @brief Invalid return value when calling RAIL_SetFixedLength()
+ *
+ * Invalid return value when calling RAIL_SetFixedLength() while the radio is
+ * not in fixed-length mode.
+ */
+#define RAIL_SETFIXEDLENGTH_INVALID (0xFFFF)
+
+/**
+ * @struct RAIL_ChannelConfigEntryAttr_t
+ * @brief Channel configuration entry attribute structure. Items listed
+ * here are designed to be altered and updated during run-time.
+ */
+typedef struct RAIL_ChannelConfigEntryAttr {
+ uint32_t calValues[1]; /**< Attributes specific to each channel config
+ entry. */
+} RAIL_ChannelConfigEntryAttr_t;
+
+/**
+ * @struct RAIL_ChannelConfigEntry_t
+ * @brief Channel configuration entry structure, which defines a channel range
+ * and parameters across which a corresponding radio configuration is valid.
+ *
+ * operating frequency = baseFrequency
+ * + channelSpacing * (channel - physicalChannelOffset);
*/
-typedef struct RAIL_Init {
- uint16_t maxPacketLength; /**< The maximum number of bytes in a packet. UNUSED! */
- const uint32_t rfXtalFreq; /**< The xtal frequency of the radio. */
- RAIL_CalMask_t calEnable; /**< Mask that defines calibrations to perform in RAIL. */
-} RAIL_Init_t;
+typedef struct RAIL_ChannelConfigEntry {
+ const uint32_t *phyConfigDeltaAdd; /**< Minimum radio config to apply to base
+ config for this channel set. */
+ uint32_t baseFrequency; /**< Base frequency in Hz of this channel set. */
+ uint32_t channelSpacing; /**< Channel spacing in Hz of this channel set. */
+ uint16_t physicalChannelOffset; /**< The offset to subtract from the logical
+ channel to align them with the zero
+ based physical channels which are
+ relative to baseFrequency.
+ (i.e. By default ch 0 = base freq, but
+ if offset = 11, ch 11 = base freq.) */
+ uint16_t channelNumberStart; /**< The first valid RAIL channel number for this
+ channel set. */
+ uint16_t channelNumberEnd; /**< The last valid RAIL channel number for this
+ channel set. */
+ RAIL_TxPower_t maxPower; /**< The max power allowed in this channel set. */
+ RAIL_ChannelConfigEntryAttr_t *attr; /**< A pointer to a structure containing
+ attributes specific to this
+ channel set. */
+} RAIL_ChannelConfigEntry_t;
+
+/**
+ * @struct RAIL_ChannelConfig_t
+ * @brief Channel configuration structure, which defines the channel meaning
+ * when a channel number is passed into a RAIL function, e.g., RAIL_StartTx()
+ * and RAIL_StartRx().
+ *
+ * A RAIL_ChannelConfig_t structure defines the channel scheme that an
+ * application uses when registered in RAIL_ConfigChannels().
+ *
+ * A few examples of different channel configurations:
+ * @code{.c}
+ * // 21 channels starting at 2.45GHz with channel spacing of 1MHz
+ * // ... generated by Simplicity Studio (i.e. rail_config.c) ...
+ * const uint32_t generated[] = { ... };
+ * RAIL_ChannelConfigEntryAttr_t generated_entryAttr = { ... };
+ * const RAIL_ChannelConfigEntry_t generated_channels[] = {
+ * {
+ * .phyConfigDeltaAdd = NULL, // Add this to default config for this entry
+ * .baseFrequency = 2450000000,
+ * .channelSpacing = 1000000,
+ * .physicalChannelOffset = 0,
+ * .channelNumberStart = 0,
+ * .channelNumberEnd = 20,
+ * .maxPower = RAIL_TX_POWER_MAX,
+ * .attr = &generated_entryAttr
+ * },
+ * };
+ * const RAIL_ChannelConfig_t generated_channelConfig = {
+ * .phyConfigBase = generated, // Default radio config for all entries
+ * .phyConfigDeltaSubtract = NULL, // Subtract this to restore default config
+ * .configs = generated_channels,
+ * .length = 1 // There are this many channel config entries
+ * };
+ * const RAIL_ChannelConfig_t *channelConfigs[] = {
+ * &generated_channelConfig,
+ * NULL
+ * };
+ * // ... in main code ...
+ * // Associate a specific channel config with a particular rail instance.
+ * RAIL_ConfigChannels(railHandle, channelConfigs[0]);
+ *
+ * // 4 nonlinear channels
+ * // ... in rail_config.c ...
+ * const uint32_t generated[] = { ... };
+ * RAIL_ChannelConfigEntryAttr_t generated_entryAttr = { ... };
+ * const RAIL_ChannelConfigEntry_t generated_channels[] = {
+ * {
+ * .phyConfigDeltaAdd = NULL, // Add this to default config for this entry
+ * .baseFrequency = 910123456,
+ * .channelSpacing = 0,
+ * .physicalChannelOffset = 0,
+ * .channelNumberStart = 0,
+ * .channelNumberEnd = 0,
+ * .maxPower = RAIL_TX_POWER_MAX,
+ * .attr = &generated_entryAttr
+ * },
+ * {
+ * .phyConfigDeltaAdd = NULL,
+ * .baseFrequency = 911654789,
+ * .channelSpacing = 0,
+ * .physicalChannelOffset = 0, // Since ch spacing = 0, offset can be 0
+ * .channelNumberStart = 1,
+ * .channelNumberEnd = 1,
+ * .maxPower = RAIL_TX_POWER_MAX,
+ * .attr = &generated_entryAttr
+ * },
+ * {
+ * .phyConfigDeltaAdd = NULL,
+ * .baseFrequency = 912321456,
+ * .channelSpacing = 100000,
+ * .physicalChannelOffset = 2, // Since ch spacing != 0, offset = 2
+ * .channelNumberStart = 2, // We want ch 2 = baseFrequency
+ * .channelNumberEnd = 2,
+ * .maxPower = RAIL_TX_POWER_MAX,
+ * .attr = &generated_entryAttr
+ * },
+ * {
+ * .phyConfigDeltaAdd = NULL,
+ * .baseFrequency = 913147852,
+ * .channelSpacing = 0,
+ * .physicalChannelOffset = 0,
+ * .channelNumberStart = 3,
+ * .channelNumberEnd = 3,
+ * .maxPower = RAIL_TX_POWER_MAX,
+ * .attr = &generated_entryAttr
+ * },
+ * };
+ * const RAIL_ChannelConfig_t generated_channelConfig = {
+ * .phyConfigBase = generated, // Default radio config for all entries
+ * .phyConfigDeltaSubtract = NULL, // Subtract this to restore default config
+ * .configs = generated_channels,
+ * .length = 4 // There are this many channel config entries
+ * };
+ * const RAIL_ChannelConfig_t *channelConfigs[] = {
+ * &generated_channelConfig,
+ * NULL
+ * };
+ * // ... in main code ...
+ * // Associate a specific channel config with a particular rail instance.
+ * RAIL_ConfigChannels(railHandle, channelConfigs[0]);
+ *
+ * // Multiple radio configurations
+ * // ... in rail_config.c ...
+ * const uint32_t generated0[] = { ... };
+ * RAIL_ChannelConfigEntryAttr_t generated0_entryAttr = { ... };
+ * const RAIL_ChannelConfigEntry_t generated0_channels[] = {
+ * {
+ * .phyConfigDeltaAdd = NULL, // Add this to default config for this entry
+ * .baseFrequency = 2450000000,
+ * .channelSpacing = 1000000,
+ * .physicalChannelOffset = 0,
+ * .channelNumberStart = 0,
+ * .channelNumberEnd = 20,
+ * .maxPower = RAIL_TX_POWER_MAX,
+ * .attr = &generated0_entryAttr
+ * },
+ * };
+ * const RAIL_ChannelConfig_t generated0_channelConfig = {
+ * .phyConfigBase = generated0, // Default radio config for all entries
+ * .phyConfigDeltaSubtract = NULL, // Subtract this to restore default config
+ * .configs = generated0_channels,
+ * .length = 1 // There are this many channel config entries
+ * };
+ * const uint32_t generated1[] = { ... };
+ * RAIL_ChannelConfigEntryAttr_t generated1_entryAttr = { ... };
+ * const RAIL_ChannelConfigEntry_t generated1_channels[] = {
+ * {
+ * .phyConfigDeltaAdd = NULL,
+ * .baseFrequency = 2450000000,
+ * .channelSpacing = 1000000,
+ * .physicalChannelOffset = 0,
+ * .channelNumberStart = 0,
+ * .channelNumberEnd = 20,
+ * .maxPower = -100, // Use this entry when TX power <= -10dBm
+ * .attr = &generated1_entryAttr
+ * },
+ * {
+ * .phyConfigDeltaAdd = NULL,
+ * .baseFrequency = 2450000000,
+ * .channelSpacing = 1000000,
+ * .physicalChannelOffset = 0,
+ * .channelNumberStart = 0,
+ * .channelNumberEnd = 20,
+ * .maxPower = 15, // Use this entry when TX power > -10dBm
+ * // and TX power <= 1.5dBm
+ * .attr = &generated1_entryAttr
+ * },
+ * {
+ * .phyConfigDeltaAdd = NULL,
+ * .baseFrequency = 2450000000,
+ * .channelSpacing = 1000000,
+ * .physicalChannelOffset = 0,
+ * .channelNumberStart = 0,
+ * .channelNumberEnd = 20,
+ * .maxPower = RAIL_TX_POWER_MAX, // Use this entry when TX power > 1.5dBm
+ * .attr = &generated1_entryAttr
+ * },
+ * };
+ * const RAIL_ChannelConfig_t generated1_channelConfig = {
+ * .phyConfigBase = generated1,
+ * .phyConfigDeltaSubtract = NULL,
+ * .configs = generated1_channels,
+ * .length = 3
+ * };
+ * const uint32_t generated2[] = { ... };
+ * RAIL_ChannelConfigEntryAttr_t generated2_entryAttr = { ... };
+ * const RAIL_ChannelConfigEntry_t generated2_channels[] = {
+ * {
+ * .phyConfigDeltaAdd = NULL,
+ * .baseFrequency = 2450000000,
+ * .channelSpacing = 1000000,
+ * .physicalChannelOffset = 0,
+ * .channelNumberStart = 0,
+ * .channelNumberEnd = 20,
+ * .maxPower = RAIL_TX_POWER_MAX,
+ * .attr = &generated2_entryAttr
+ * },
+ * };
+ * const RAIL_ChannelConfig_t generated2_channelConfig = {
+ * .phyConfigBase = generated2,
+ * .phyConfigDeltaSubtract = NULL,
+ * .configs = generated2_channels,
+ * .length = 1
+ * };
+ * const RAIL_ChannelConfig_t *channelConfigs[] = {
+ * &generated0_channelConfig,
+ * &generated1_channelConfig,
+ * &generated2_channelConfig,
+ * NULL
+ * };
+ * // ... in main code ...
+ * // Create a unique RAIL handle for each unique channel config.
+ * railHandle0 = RAIL_Init(&railCfg0, &RAILCb_RfReady0);
+ * railHandle1 = RAIL_Init(&railCfg1, &RAILCb_RfReady1);
+ * railHandle2 = RAIL_Init(&railCfg2, &RAILCb_RfReady2);
+ * // Associate each channel config with its corresponding RAIL handle.
+ * RAIL_ConfigChannels(railHandle0, channelConfigs[0]);
+ * RAIL_ConfigChannels(railHandle1, channelConfigs[1]);
+ * RAIL_ConfigChannels(railHandle2, channelConfigs[2]);
+ * // Use a RAIL handle and channel to access the desired channel config entry.
+ * RAIL_SetTxPowerDbm(railHandle1, 100); // set 10.0 dBm TX power
+ * RAIL_StartRx(railHandle1, 0, &schedInfo); // RX using generated1_channels[2]
+ * RAIL_SetTxPowerDbm(railHandle1, 0); // set 0 dBm TX power
+ * RAIL_StartRx(railHandle1, 0, &schedInfo); // RX using generated1_channels[1]
+ * RAIL_StartRx(railHandle2, 0, &schedInfo); // RX using generated2_channels[0]
+ * @endcode
+ */
+typedef struct RAIL_ChannelConfig {
+ const uint32_t *phyConfigBase; /**< Base radio config for the corresponding
+ channel config entries. */
+ const uint32_t *phyConfigDeltaSubtract; /**< Minimum radio config to restore
+ channel entries back to base
+ config. */
+ const RAIL_ChannelConfigEntry_t *configs; /**< Pointer to an array of
+ RAIL_ChannelConfigEntry_t
+ entries. */
+ uint32_t length; /**< Number of RAIL_ChannelConfigEntry_t entries. */
+} RAIL_ChannelConfig_t;
+
+/**
+ * @typedef RAIL_RadioConfigChangedCallback_t
+ * @brief Pointer to function called whenever a radio configuration change occurs.
+ *
+ * @param[in] railHandle A handle for RAIL instance.
+ * @param[in] entry The radio configuration entry being changed to.
+ */
+typedef void (*RAIL_RadioConfigChangedCallback_t)(RAIL_Handle_t railHandle,
+ const RAIL_ChannelConfigEntry_t *entry);
+/** @} */ // end of group Radio_Configuration
+
+/******************************************************************************
+ * Packet Trace Interface (PTI) Structures
+ *****************************************************************************/
+/**
+ * @addtogroup PTI
+ * @{
+ */
/**
* @enum RAIL_PtiProtocol_t
- * @brief The protocol that RAIL outputs via the Packet Trace Interface (PTI)
+ * @brief The protocol that RAIL outputs via the Packet Trace Interface (PTI).
*/
-typedef enum RAIL_PtiProtocol {
+RAIL_ENUM(RAIL_PtiProtocol_t) {
RAIL_PTI_PROTOCOL_CUSTOM = 0, /**< PTI output for a custom protocol */
RAIL_PTI_PROTOCOL_THREAD = 2, /**< PTI output for the Thread protocol */
RAIL_PTI_PROTOCOL_BLE = 3, /**< PTI output for the Bluetooth Smart protocol */
RAIL_PTI_PROTOCOL_CONNECT = 4, /**< PTI output for the Connect protocol */
- RAIL_PTI_PROTOCOL_ZIGBEE = 5, /**< PTI output for the Zigbee protocol */
-} RAIL_PtiProtocol_t;
+ RAIL_PTI_PROTOCOL_ZIGBEE = 5, /**< PTI output for the zigbee protocol */
+};
+
+/** @} */ // end of group PTI
+
+/******************************************************************************
+ * System Timing Structures
+ *****************************************************************************/
+/**
+ * @addtogroup System_Timing
+ * @{
+ */
/**
- * @enum RAIL_RadioState_t
- * @brief The current state of the radio
+ * Pointer to callback called when the RAIL timer expires.
+ *
+ * @param[in] cbArg The argument passed to the callback.
+ * @return void.
*/
-typedef enum RAIL_RadioState {
- RAIL_RF_STATE_IDLE, /**< Radio is idle */
- RAIL_RF_STATE_RX, /**< Radio is in receive */
- RAIL_RF_STATE_TX, /**< Radio is in transmit */
-} RAIL_RadioState_t;
+typedef void (*RAIL_TimerCallback_t)(RAIL_Handle_t cbArg);
/**
- * @enum RAIL_Status_t
- * @brief The available status options
+ * @enum RAIL_TimeMode_t
+ * @brief Specifies a time offset in RAIL APIs.
+ *
+ * Different APIs use the same constants and may provide more specifics about
+ * how they're used but the general use for each is described below.
*/
-typedef enum RAIL_Status {
- RAIL_STATUS_NO_ERROR, /**< RAIL function reports no error */
- RAIL_STATUS_INVALID_PARAMETER, /**< Call to RAIL function errored because of an invalid parameter */
- RAIL_STATUS_INVALID_STATE, /**< Call to RAIL function errored because called during an invalid radio state */
- RAIL_STATUS_INVALID_CALL, /**< The function is called in an invalid order */
-} RAIL_Status_t;
+RAIL_ENUM(RAIL_TimeMode_t) {
+ /**
+ * The time specified is an exact time in the RAIL timebase. The given
+ * event should happen at exactly that time. If this time is already in the
+ * past, an error is returned. Because the RAIL timebase wraps at 32
+ * bits, there is no real 'past'. Instead, any event greater than
+ * 3/4 of the way into the future is considered to be in the past.
+ */
+ RAIL_TIME_ABSOLUTE,
+ /**
+ * The time specified is relative to the current time. The event should occur
+ * that many ticks in the future. Delays are only guaranteed at least as long
+ * as the value specified. An overhead may occur between the time when the
+ * API is called and when the delay starts. As a result, using this for
+ * operations that must happen at an exact given time is not recommended.
+ * For that, you must use \ref RAIL_TIME_ABSOLUTE delays.
+ *
+ * Note that, if you specify a delay 0, that event is triggered as soon as
+ * possible. This is different than specifying an absolute time of now which
+ * would return an error unless it was possible.
+ */
+ RAIL_TIME_DELAY,
+ /**
+ * The specified time is invalid and should be ignored. For some APIs this
+ * can also indicate that any previously stored delay should be invalidated
+ * and disabled.
+ */
+ RAIL_TIME_DISABLED
+};
/**
- * @enum RAIL_RfSenseBand_t
- * @brief Enumeration for specifying Rf Sense frequency band.
+ * @enum RAIL_SleepConfig_t
+ * @brief The config
*/
-typedef enum {
- RAIL_RFSENSE_OFF, /**< RFSense is disabled */
- RAIL_RFSENSE_2_4GHZ, /**< RFSense is in 2.4G band */
- RAIL_RFSENSE_SUBGHZ, /**< RFSense is in subgig band */
- RAIL_RFSENSE_ANY, /**< RfSense is in both bands */
- RAIL_RFSENSE_MAX // Must be last
-} RAIL_RfSenseBand_t;
+RAIL_ENUM(RAIL_SleepConfig_t) {
+ RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED, /**< Disable timer sync before and after sleep */
+ RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED, /**< Enable timer sync before and after sleep */
+};
/**
- * @enum RAIL_RfIdleMode_t
- * @brief Enumeration for the different types of idle modes we support. These
- * vary how quickly and destructively we will put the radio into idle.
+ * @enum RAIL_PacketTimePosition_t
+ * @brief The available packet timestamp position choices
*/
-typedef enum {
+RAIL_ENUM(RAIL_PacketTimePosition_t) {
+ /**
+ * Indicates timestamp is not to be, or was not, provided.
+ * Useful if the application doesn't care about packet timestamps
+ * and doesn't want RAIL to spend time calculating one.
+ */
+ RAIL_PACKET_TIME_INVALID = 0,
/**
- * Idle the radio by turning off receive and canceling any future scheduled
- * receive or transmit operations. This will not abort a receive or
- * transmit that is in progress.
+ * Requests the choice most expedient for RAIL to calculate,
+ * which may depend on the radio and/or its configuration.
+ * The actual choice would always be reflected in the timePosition
+ * field of \ref RAIL_RxPacketDetails_t or \ref RAIL_TxPacketDetails_t
+ * returned, and would never be one of the _USED_TOTAL values.
*/
- RAIL_IDLE,
+ RAIL_PACKET_TIME_DEFAULT = 1,
/**
- * Idle the radio by turning off receive and any scheduled events. This will
- * also abort any receive, transmit, or scheduled events in progress.
+ * Requests the timestamp corresponding to the first preamble bit
+ * sent or received.
+ * Indicates that timestamp did not require using totalPacketBytes.
*/
- RAIL_IDLE_ABORT,
+ RAIL_PACKET_TIME_AT_PREAMBLE_START = 2,
/**
- * Force the radio into a shutdown mode as quickly as possible. This will
- * abort all current operations and cancel any pending scheduled operations.
- * It may also corrupt receive or transmit buffers and end up clearing them.
+ * Requests the timestamp corresponding to the first preamble bit
+ * sent or received.
+ * Indicates that timestamp did require using totalPacketBytes.
*/
- RAIL_IDLE_FORCE_SHUTDOWN,
+ RAIL_PACKET_TIME_AT_PREAMBLE_START_USED_TOTAL = 3,
+ /**
+ * Requests the timestamp corresponding to right after its last
+ * SYNC word bit has been sent or received.
+ * Indicates that timestamp did not require using totalPacketBytes.
+ */
+ RAIL_PACKET_TIME_AT_SYNC_END = 4,
/**
- * Similar to the \ref RAIL_IDLE_FORCE_SHUTDOWN command this will quickly
- * put the radio into the idle state. In addition to this it will clear any
- * pending receive or transmit callbacks and clear both the receive and
- * transmit storage.
+ * Requests the timestamp corresponding to right after its last
+ * SYNC word bit has been sent or received.
+ * Indicates that timestamp did require using totalPacketBytes.
+ */
+ RAIL_PACKET_TIME_AT_SYNC_END_USED_TOTAL = 5,
+ /**
+ * Reqeusts the timestamp corresponding to right after its last
+ * bit has been sent or received.
+ * Indicates that timestamp did not require using totalPacketBytes.
*/
- RAIL_IDLE_FORCE_SHUTDOWN_CLEAR_FLAGS
-} RAIL_RfIdleMode_t;
+ RAIL_PACKET_TIME_AT_PACKET_END = 6,
+ /**
+ * Reqeusts the timestamp corresponding to right after its last
+ * bit has been sent or received.
+ * Indicates that timestamp did require using totalPacketBytes.
+ */
+ RAIL_PACKET_TIME_AT_PACKET_END_USED_TOTAL = 7,
+ RAIL_PACKET_TIME_COUNT /**< Count of the choices in this enum */
+};
/**
- * @}
+ * @struct RAIL_PacketTimeStamp_t
+ * @brief Information needed to calculate and represent a packet timestamp.
*/
+typedef struct RAIL_PacketTimeStamp {
+ /**
+ * Timestamp of the packet in the RAIL timebase.
+ */
+ uint32_t packetTime;
+ /**
+ * A value specifying the total length in bytes of the packet for
+ * use when calculating the packetTime requested by the timePosition
+ * field. This should account for all bytes sent over the air after
+ * the Preamble and Sync word(s), including any CRC bytes.
+ */
+ uint32_t totalPacketBytes;
+ /**
+ * A RAIL_PacketTimePosition_t value specifying the packet position
+ * to return in the packetTime field.
+ * If this is \ref RAIL_PACKET_TIME_DEFAULT then this field will be
+ * updated with the actual position corresponding to the packetTime
+ * value filled in by a call using this structure.
+ */
+ RAIL_PacketTimePosition_t timePosition;
+} RAIL_PacketTimeStamp_t;
-// -----------------------------------------------------------------------------
-// Data Management Structures
-// -----------------------------------------------------------------------------
+/** @} */ // end of group System_Timing
+/******************************************************************************
+ * Data Management Structures
+ *****************************************************************************/
/**
* @addtogroup Data_Management
* @{
@@ -176,36 +1103,38 @@
* @enum RAIL_TxDataSource_t
* @brief Transmit data sources supported by RAIL.
*/
-typedef enum{
- TX_PACKET_DATA, /**< Use the frame hardware to packetize data */
-} RAIL_TxDataSource_t;
+RAIL_ENUM(RAIL_TxDataSource_t) {
+ TX_PACKET_DATA, /**< Uses the frame hardware to packetize data */
+};
/**
* @enum RAIL_RxDataSource_t
* @brief Receive data sources supported by RAIL.
*/
-typedef enum{
- RX_PACKET_DATA, /**< Use the frame hardware to packetize data */
- RX_DEMOD_DATA, /**< Get 8-bit data output from the demodulator */
- RX_IQDATA_FILTLSB, /**< Get lower 16 bits of I/Q data provided to demodulator */
- RX_IQDATA_FILTMSB /**< Get highest 16 bits of I/Q data provided to demodulator */
-} RAIL_RxDataSource_t;
+RAIL_ENUM(RAIL_RxDataSource_t) {
+ RX_PACKET_DATA, /**< Uses the frame hardware to packetize data */
+ RX_DEMOD_DATA, /**< Gets 8-bit data output from the demodulator */
+ RX_IQDATA_FILTLSB, /**< Gets lower 16 bits of I/Q data provided to the
+ demodulator */
+ RX_IQDATA_FILTMSB /**< Gets highest 16 bits of I/Q data provided to the
+ demodulator */
+};
/**
* @enum RAIL_DataMethod_t
- * @brief Methods for the application to provide and retreive data from RAIL.
+ * @brief Methods for the application to provide and retrieve data from RAIL.
*/
-typedef enum{
- PACKET_MODE, /**< Packet based data method */
- FIFO_MODE, /**< FIFO based data method */
-} RAIL_DataMethod_t;
+RAIL_ENUM(RAIL_DataMethod_t) {
+ PACKET_MODE, /**< Packet-based data method */
+ FIFO_MODE, /**< FIFO-based data method */
+};
/**
* @struct RAIL_DataConfig_t
* @brief RAIL data configuration structure
*
- * This structure is used to select the transmit/receive data sources, and the
- * method the application uses to provide/retreive data from RAIL.
+ * Selects the transmit/receive data sources and the
+ * method the application uses to provide/retrieve data from RAIL.
*/
typedef struct {
RAIL_TxDataSource_t txSource; /**< Source of TX Data */
@@ -214,291 +1143,212 @@
RAIL_DataMethod_t rxMethod; /**< Method of retrieving receive data */
} RAIL_DataConfig_t;
-/**
- * @def RAIL_SETFIXEDLENGTH_INVALID
- * @brief Invalid return value when calling RAIL_SetFixedLength()
- *
- * Invalid return value when calling RAIL_SetFixedLength() while the radio is
- * not in fixed length mode.
- */
-#define RAIL_SETFIXEDLENGTH_INVALID (0xFFFF)
+/** @} */ // end of group Data Management
+/******************************************************************************
+ * State Transitions
+ *****************************************************************************/
/**
- * @}
- */
-
-// -----------------------------------------------------------------------------
-// PHY Configuration Structures
-// -----------------------------------------------------------------------------
-
-/**
- * @addtogroup Radio_Configuration
+ * @addtogroup State_Transitions
* @{
*/
/**
+ * @enum RAIL_RadioState_t
+ * @brief The state of the radio.
+ */
+RAIL_ENUM(RAIL_RadioState_t) {
+ RAIL_RF_STATE_INACTIVE = 0u, /**< Phy is inactive */
+ RAIL_RF_STATE_ACTIVE = (1u << 0), /**< Radio is idle, receiving, or
+ transmitting a frame */
+ RAIL_RF_STATE_RX = (1u << 1), /**< Radio is in receive */
+ RAIL_RF_STATE_TX = (1u << 2), /**< Radio is in transmit */
+ RAIL_RF_STATE_IDLE = (RAIL_RF_STATE_ACTIVE), /**< Radio is idle */
+ /** Radio is actively receiving a frame */
+ RAIL_RF_STATE_RX_ACTIVE = (RAIL_RF_STATE_RX | RAIL_RF_STATE_ACTIVE),
+ /** Radio is actively transmitting a frame */
+ RAIL_RF_STATE_TX_ACTIVE = (RAIL_RF_STATE_TX | RAIL_RF_STATE_ACTIVE)
+};
+
+/**
+ * @struct RAIL_StateTransitions_t
+ * @brief Used to specify radio states to transition to on success or failure.
+ */
+typedef struct RAIL_StateTransitions {
+ /**
+ * Indicates the state the radio should return to after a successful action.
+ */
+ RAIL_RadioState_t success;
+ /**
+ * Indicates the state the radio should return to after an error.
+ */
+ RAIL_RadioState_t error;
+} RAIL_StateTransitions_t;
+
+/**
* @struct RAIL_StateTiming_t
- * @brief Timing configuration structure for the RAIL State Machine
+ * @brief Timing configuration structure for the RAIL State Machine.
*
- * This is used to configure the timings of the radio state transitions for
- * common situations. All of the listed timings are in us. Timing values cannot
- * exceed 13ms. Transitions to IDLE always happen as fast as possible.
+ * Configures the timings of the radio state transitions for
+ * common situations. All of the listed timings are in µs.
+ * Timing values cannot exceed 13 ms.
+ * Transitions to IDLE always happen as fast as possible.
*/
typedef struct RAIL_StateTiming {
- uint16_t idleToRx; /**<Transition time from IDLE to RX */
- uint16_t txToRx; /**<Transition time from TX to RX */
- uint16_t idleToTx; /**<Transition time from IDLE to RX */
- uint16_t rxToTx; /**<Transition time from RX to TX */
+ uint16_t idleToRx; /**< Transition time from IDLE to RX */
+ uint16_t txToRx; /**< Transition time from TX to RX */
+ uint16_t idleToTx; /**< Transition time from IDLE to RX */
+ uint16_t rxToTx; /**< Transition time from RX to TX */
+ uint16_t rxSearchTimeout; /**< Time radio looks for packets when coming from
+ idle, value of zero disables this feature */
+ uint16_t txToRxSearchTimeout; /**< Time to look for packets when coming from
+ tx, value of zero disables this feature */
} RAIL_StateTiming_t;
/**
- * @struct RAIL_FrameType_t
- * @brief Configure if there is a frame type in your frame and the lengths of each frame.
- * The number of bits set in the mask determines the number of elements in frameLen
- * If your packet does not have frame types but instead are of fixed length, set the mask
- * and offset to 0. RAIL will use the value at frameLen to determine the packet length.
- * If each frame type has a different location for the addres, variableAddrLoc should be True.
- */
-typedef struct RAIL_FrameType {
- uint8_t offset; /**< Zero-based location of the frame type field in packet. */
- uint8_t mask; /**< Bit mask of the frame type field. Determines number of frames expected. Must be contiguous ones. */
- uint16_t *frameLen; /**< Pointer to array of frame lengths for each frame type. */
- uint8_t *isValid; /**< Pointer to array that marks if each frame is valid or should be filtered. */
- bool variableAddrLoc; /**< If true, address location varies per frame type. */
-} RAIL_FrameType_t;
-
-/**
- * @struct RAIL_ChannelConfigEntry_t
- * @brief Channel configuration entry structure. Defines a base frequency and
- * channel space and the channel indexes that are valid within this range.
- *
- * * frequency = baseFrequency + channelSpacing * (channel - channelNumberStart);
- *
- * Each RAIL_ChannelConfigEntry_t should not span more than 64 channels.
+ * @enum RAIL_IdleMode_t
+ * @brief Enumeration for the different types of supported idle modes. These
+ * vary how quickly and destructively they put the radio into idle.
*/
-typedef struct RAIL_ChannelConfigEntry {
- uint16_t channelNumberStart; /**< RAIL Channel number in which this channel set begins.*/
- uint16_t channelNumberEnd; /**< The last valid RAIL channel number for this channel set. */
- uint32_t channelSpacing; /**< Channel spacing in Hz of this channel set. */
- uint32_t baseFrequency; /**< Base frequency in Hz of this channel set. */
-} RAIL_ChannelConfigEntry_t;
-
-/**
- * @struct RAIL_ChannelConfig_t
- * @brief Channel configuration structure which defines the channel meaning when
- * a channel number is passed into a RAIL function, eg. RAIL_TxStart(), RAIL_RxStart()
- *
- * A RAIL_ChannelConfig_t structure defines the channel scheme that an
- * application uses when registered in RAIL_ChannelConfig(). A channel scheme
- * must be in the same band, it can not span across frequencies that would
- * change the divider.
- *
- * A few examples of different channel schemes:
- * @code{.c}
- * // Ten channels starting a 915 Mhz with a channel spacing of 1 Mhz
- * RAIL_ChannelConfigEntry_t channels = {
- * 0, 9, 1000000, 915000000
- * };
- * RAIL_ChannelConfig_t channelScheme = {
- * channels,
- * 1
- * };
- *
- * // 120 channels starting at 915Mhz with channel spacing of 100KHz
- * RAIL_ChannelConfigEntry_t channels[] = {
- * {0, 63, 100000, 910000000},
- * {64, 119, 100000, 916400000},
- * };
- * RAIL_ChannelConfig_t channelScheme = {
- * channels,
- * 2
- * };
- *
- * // 5 nonlinear channels
- * RAIL_ChannelConfigEntry_t channels[] = {
- * {0, 0, 0, 910123456},
- * {1, 1, 0, 911654789},
- * {2, 2, 0, 912321456},
- * {3, 3, 0, 913147852},
- * {4, 4, 0, 914567890}
- * };
- * RAIL_ChannelConfig_t channelScheme = {
- * channels,
- * 5
- * };
- * @endcode
- */
-typedef struct RAIL_ChannelConfig {
- RAIL_ChannelConfigEntry_t *configs; /**< Pointer to an array of RAIL_ChannelConfigEntry_t entries.*/
- uint32_t length; /**< Number of RAIL_ChannelConfigEntry_t entries. */
-} RAIL_ChannelConfig_t;
-
-/**
- * @}
- */
+RAIL_ENUM(RAIL_IdleMode_t) {
+ /**
+ * Idles the radio by turning off receive and canceling any future scheduled
+ * receive or transmit operations. It does not abort a receive or
+ * transmit in progress.
+ */
+ RAIL_IDLE,
+ /**
+ * Idles the radio by turning off receive and any scheduled events. It
+ * also aborts any receive, transmit, or scheduled events in progress.
+ */
+ RAIL_IDLE_ABORT,
+ /**
+ * Forces the radio into a shutdown mode as quickly as possible. It
+ * aborts all current operations and cancels any pending scheduled
+ * operations.
+ * It may also corrupt receive or transmit buffers and end up clearing them.
+ */
+ RAIL_IDLE_FORCE_SHUTDOWN,
+ /**
+ * Similar to the \ref RAIL_IDLE_FORCE_SHUTDOWN command, it quickly
+ * puts the radio into idle state. Additionally, it clears any
+ * pending receive or transmit callbacks and clear both the receive and
+ * transmit storage.
+ */
+ RAIL_IDLE_FORCE_SHUTDOWN_CLEAR_FLAGS
+};
-// -----------------------------------------------------------------------------
-// Address Filtering Configuration Structures
-// -----------------------------------------------------------------------------
-/**
- * @addtogroup Address_Filtering
- * @{
- */
-
-/// Default address filtering match table for configurations that use only one
-/// address field. The truth table for address matching is below.
-///
-/// | | 0000 | 0001 | 0010 | 0100 | 1000 |
-/// |----------|------|------|------|------|------|
-/// | __0000__ | 0 | 1 | 1 | 1 | 1 |
-/// | __0001__ | 1 | 1 | 1 | 1 | 1 |
-/// | __0010__ | 1 | 1 | 1 | 1 | 1 |
-/// | __0100__ | 1 | 1 | 1 | 1 | 1 |
-/// | __1000__ | 1 | 1 | 1 | 1 | 1 |
-///
-#define ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD (0x1fffffe)
-/// Default address filtering match table for configurations that use two
-/// address fields and just want to match the same index in each. The truth
-/// table for address matching is shown below.
-///
-/// | | 0000 | 0001 | 0010 | 0100 | 1000 |
-/// |----------|------|------|------|------|------|
-/// | __0000__ | 0 | 0 | 0 | 0 | 0 |
-/// | __0001__ | 0 | 1 | 0 | 0 | 0 |
-/// | __0010__ | 0 | 0 | 1 | 0 | 0 |
-/// | __0100__ | 0 | 0 | 0 | 1 | 0 |
-/// | __1000__ | 0 | 0 | 0 | 0 | 1 |
-#define ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD (0x1041040)
-
-/**
- * @struct RAIL_AddrConfig_t
- * @brief A structure to configure the address filtering functionality in RAIL.
- */
-typedef struct RAIL_AddrConfig {
- /** The number of fields to configure. You cannot have more than 2. */
- uint8_t numFields;
+/** @} */ // end of group State_Transitions
- /**
- * A list of the start offsets for each field
- *
- * These offsets are specified relative to the previous field's end. In the
- * case of the first field it's relative to either the beginning of the packet
- * or the end of the frame type byte if frame type decoding is enabled.
- */
- uint8_t *offsets;
-
- /**
- * A list of the address field sizes
- *
- * These sizes are specified in bytes and can be from 0 to 8. If you choose a
- * size of 0 this field is effectively disabled.
- */
- uint8_t *sizes;
-
- /**
- * The truth table to determine how the two fields combine to create a match
- *
- * For detailed information about how this truth table is formed see the
- * detailed description of @ref Address_Filtering.
- *
- * For simple predefined configurations you can use the following defines.
- * - ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD
- * - For filtering that only uses a single address field
- * - ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD for two field filtering where you
- * - For filtering that uses two address fields in a configurations where
- * you want the following logic `((Field0, Index0) && (Field1, Index0)) ||
- * ((Field0, Index1) && (Field1, Index1)) || ...`
- */
- uint32_t matchTable;
-} RAIL_AddrConfig_t;
-
+/******************************************************************************
+ * TX/RX Configuration Structures
+ *****************************************************************************/
/**
- * @}
- */
-
-// -----------------------------------------------------------------------------
-// System Timing Structures
-// -----------------------------------------------------------------------------
-/**
- * @addtogroup System_Timing
+ * @addtogroup Transmit
* @{
*/
/**
- * @enum RAIL_TimeMode_t
- * @brief This type is used to specifying a time offset in RAIL APIs.
- *
- * Different APIs use these same constants and may provide more specifics of how
- * they're used but the general philosophy for each is described below.
+ * @enum RAIL_TxOptions_t
+ * @brief Transmit options, in reality a bitmask.
*/
-typedef enum RAIL_TimeMode {
+RAIL_ENUM_GENERIC(RAIL_TxOptions_t, uint32_t) {
+ /** Value representing no options enabled. */
+ RAIL_TX_OPTIONS_NONE = 0,
+ /** Default is all options disabled. */
+ RAIL_TX_OPTIONS_DEFAULT = RAIL_TX_OPTIONS_NONE,
+
+ /** Shift position of \ref RAIL_TX_OPTION_WAIT_FOR_ACK bit */
+ RAIL_TX_OPTION_WAIT_FOR_ACK_SHIFT = 0,
+ /** Shift position of \ref RAIL_TX_OPTION_REMOVE_CRC bit */
+ RAIL_TX_OPTION_REMOVE_CRC_SHIFT,
+ /** Shift position of \ref RAIL_TX_OPTION_SYNC_WORD_ID bit */
+ RAIL_TX_OPTION_SYNC_WORD_ID_SHIFT,
+
/**
- * The time specified is an exact time in the RAIL timebase and the given
- * event should happen at exactly that time. If this time is already in the
- * past we will return an error and fail. Since the RAIL timebase wraps at 32
- * bits there is no real 'past' so we instead consider any event greater than
- * 3/4 of the way into the future to be in the past.
+ * Option to configure whether or not the TX'ing node will listen for an ACK.
+ * If this is false, the isAck flag in RAIL_RxPacketDetails_t of a received
+ * packet will always be false.
*/
- RAIL_TIME_ABSOLUTE,
- /**
- * The time specified is relative to now and the event should occur that many
- * ticks in the future. Delays are only guaranteed to be at least as long as
- * the value specified. There may be some overhead between when the API is
- * called and when the delay starts so we _do not_ recommend using this for
- * operations that must happen at exactly a given time. For that you must use
- * \ref RAIL_TIME_ABSOLUTE delays.
- *
- * Note that if you specify a delay of 0 we will trigger that event as soon as
- * possible. This is different than specifying an absolute time of now which
- * would return an error unless it was possible.
- */
- RAIL_TIME_DELAY,
+ RAIL_TX_OPTION_WAIT_FOR_ACK = (1ul << RAIL_TX_OPTION_WAIT_FOR_ACK_SHIFT),
+ /**
+ * Option to remove crc bytes from tx packets. If you want to be able to
+ * receive packets with this option set as true, you'll need to set
+ * the IGNORE_CRC_ERRORS option on the receive side.
+ */
+ RAIL_TX_OPTION_REMOVE_CRC = (1ul << RAIL_TX_OPTION_REMOVE_CRC_SHIFT),
/**
- * The specified time is invalid and should be ignored. For some APIs this can
- * also indicate that any previously stored delay should be invalidated and
- * disabled.
+ * Option to select which sync word to send (0 or 1). Note that this does
+ * not set the actual sync words, it just picks which of the two will be
+ * sent with the packet.
*/
- RAIL_TIME_DISABLED
-} RAIL_TimeMode_t;
+ RAIL_TX_OPTION_SYNC_WORD_ID = (1ul << RAIL_TX_OPTION_SYNC_WORD_ID_SHIFT),
+
+ /** Value representing all possible options */
+ RAIL_TX_OPTIONS_ALL = 0xFFFFFFFFul
+};
/**
- * @}
+ * @struct RAIL_TxPacketDetails_t
+ * @brief Detailed information requested and about the packet that was just
+ * transmitted.
*/
-
-// -----------------------------------------------------------------------------
-// Pre-Tx Configuration Structures
-// -----------------------------------------------------------------------------
-/**
- * @addtogroup Pre-Transmit
- * @{
- */
+typedef struct RAIL_TxPacketDetails {
+ /**
+ * Timestamp of the transmitted packet in the RAIL timebase,
+ * filled in by RAIL_GetTxPacketDetails().
+ */
+ RAIL_PacketTimeStamp_t timeSent;
+ /**
+ * Indicates whether the transmitted packet was an ACK. An 'ACK' is defined
+ * as a packet sent in response to a received ACK-requesting frame when
+ * auto ACK is enabled. Set to false for not an ACK, and true for an ACK.
+ * It should always be set false if auto ACK is not enabled.
+ */
+ bool isAck;
+} RAIL_TxPacketDetails_t;
/**
- * @typedef RAIL_PreTxOp_t
- * @brief Generic type used for all configurable pre-transmit operation
- * functions.
+ * @enum RAIL_ScheduledTxDuringRx_t
+ * @brief Enumerates the possible outcomes of what will occur if a
+ * scheduled TX ends up firing during RX. Because RX and TX can't
+ * happen at the same time, it is up to the user how the TX should be
+ * handled. This enumeration is passed into RAIL_StartScheduledTx()
+ * as part of \ref RAIL_ScheduleTxConfig_t.
*/
-typedef uint8_t (*RAIL_PreTxOp_t)(void *params);
+RAIL_ENUM(RAIL_ScheduledTxDuringRx_t) {
+ /**
+ * The scheduled TX will be postponed until RX completes and then sent.
+ */
+ RAIL_SCHEDULED_TX_DURING_RX_POSTPONE_TX,
+ /**
+ * The scheduled TX will be aborted and a TX aborted event will fire.
+ */
+ RAIL_SCHEDULED_TX_DURING_RX_ABORT_TX
+};
/**
* @struct RAIL_ScheduleTxConfig_t
- * @brief This structure is used to configure the Scheduled Tx algorithm.
- * When using the built-in RAIL_PreTxSchedule() algorithm as your
- * pre-transmit hook within RAIL_TxStart(), an instance of this structure
- * must be passed as its argument.
+ * @brief Configuration structure for a scheduled transmit.
*/
typedef struct RAIL_ScheduleTxConfig {
/**
- * When to transmit this packet. The exact interpretation of this value
- * depends on the mode specified below.
+ * The time when to transmit this packet. The exact interpretation of
+ * this value depends on the mode specified below.
*/
uint32_t when;
/**
- * They type of delay to use. See the \ref RAIL_TimeMode_t documentation for
- * more information. Be sure to use \ref RAIL_TIME_ABSOLUTE delays for time
- * critical protocols.
+ * The type of delay. See the \ref RAIL_TimeMode_t documentation for
+ * more information. Be sure to use \ref RAIL_TIME_ABSOLUTE delays for
+ * time-critical protocols.
*/
RAIL_TimeMode_t mode;
+ /**
+ * Which action to take with a scheduled TX if it occurs during RX.
+ * See \ref RAIL_ScheduledTxDuringRx_t structure for more information on
+ * potential options.
+ */
+ RAIL_ScheduledTxDuringRx_t txDuringRx;
} RAIL_ScheduleTxConfig_t;
/**
@@ -509,10 +1359,7 @@
/**
* @struct RAIL_CsmaConfig_t
- * @brief This structure is used to configure the CSMA algorithm. When using
- * the built-in RAIL_PreTxCsma() algorithm as your pre-transmit hook within
- * RAIL_TxStart(), an instance of this structure must be passed as its
- * argument.
+ * @brief Configuration structure for the CSMA transmit algorithm.
*/
typedef struct RAIL_CsmaConfig {
/**
@@ -524,9 +1371,9 @@
*/
uint8_t csmaMaxBoExp;
/**
- * Number of CCA failures before report CCA_FAIL. With a maximum value defined
- * in @ref RAIL_MAX_LBT_TRIES). A value of 0 will perform no CCA assessments,
- * and always transmit immediately.
+ * A number of CCA failures before report CCA_FAIL with a maximum value
+ * defined in @ref RAIL_MAX_LBT_TRIES). A value 0 performs no CCA assessments
+ * and always transmits immediately.
*/
uint8_t csmaTries;
/**
@@ -535,11 +1382,11 @@
*/
int8_t ccaThreshold;
/**
- * The backoff unit period, in RAIL's microsecond time base. This is
- * mulitiplied by the random backoff exponential controlled by @ref
+ * The backoff unit period in RAIL's microsecond time base. It is
+ * multiplied by the random backoff exponential controlled by @ref
* csmaMinBoExp and @ref csmaMaxBoExp to determine the overall backoff
* period. For random backoffs, any value above 511 microseconds will
- * be truncated; for fixed backoffs it can go up to 65535 microseconds.
+ * be truncated. For fixed backoffs it can go up to 65535 microseconds.
*/
uint16_t ccaBackoff;
/**
@@ -547,53 +1394,50 @@
*/
uint16_t ccaDuration;
/**
- * An overall timeout, in RAIL's microsecond time base, for the operation. If
- * transmission doesn't start before this timeout expires, the transmission
- * will fail. A value of 0 means no timeout is imposed.
+ * An overall timeout, in RAIL's microsecond time base, for the operation.
+ * If the transmission doesn't start before this timeout expires, the
+ * transmission will fail. A value 0 means no timeout is imposed.
*/
uint32_t csmaTimeout;
} RAIL_CsmaConfig_t;
/**
* @def RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA
- * @brief RAIL_CsmaConfig_t initializer configuring CSMA per 802.15.4-2003
- * on 2.4 GHz OSPSK, commonly used by ZigBee.
+ * @brief RAIL_CsmaConfig_t initializer configuring CSMA per IEEE 802.15.4-2003
+ * on 2.4 GHz OSPSK, commonly used by ZigBee.
*/
-#define RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA { \
- /* CSMA per 802.15.4-2003 on 2.4 GHz OSPSK, commonly used by ZigBee */ \
- /* csmaMinBoExp */ 3, /* 2^3-1 for 0..7 backoffs on 1st try */ \
- /* csmaMaxBoExp */ 5, /* 2^5-1 for 0..31 backoffs on 3rd+ tries */ \
- /* csmaTries */ 5, /* 5 tries overall (4 re-tries) */ \
- /* ccaThreshold */ -75, /* 10 dB above sensitivity */ \
- /* ccaBackoff */ 320, /* 20 symbols at 16 us/symbol */ \
- /* ccaDuration */ 128, /* 8 symbols at 16 us/symbol */ \
- /* csmaTimeout */ 0, /* no timeout */ \
+#define RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA { \
+ /* CSMA per 802.15.4-2003 on 2.4 GHz OSPSK, commonly used by ZigBee */ \
+ /* csmaMinBoExp */ 3, /* 2^3-1 for 0..7 backoffs on 1st try */ \
+ /* csmaMaxBoExp */ 5, /* 2^5-1 for 0..31 backoffs on 3rd+ tries */ \
+ /* csmaTries */ 5, /* 5 tries overall (4 re-tries) */ \
+ /* ccaThreshold */ -75, /* 10 dB above sensitivity */ \
+ /* ccaBackoff */ 320, /* 20 symbols at 16 us/symbol */ \
+ /* ccaDuration */ 128, /* 8 symbols at 16 us/symbol */ \
+ /* csmaTimeout */ 0, /* no timeout */ \
}
/**
* @def RAIL_CSMA_CONFIG_SINGLE_CCA
- * @brief RAIL_CsmaConfig_t initializer configuring a single CCA prior to Tx.
- * Can be used to as a basis for implementing other channel access schemes
- * with custom backoff delays. User can override ccaBackoff with a fixed
- * delay on each use.
+ * @brief RAIL_CsmaConfig_t initializer configuring a single CCA prior to TX.
+ * It can be used to as a basis for implementing other channel access schemes
+ * with custom backoff delays. User can override ccaBackoff with a fixed
+ * delay on each use.
*/
-#define RAIL_CSMA_CONFIG_SINGLE_CCA { \
- /* Perform a single CCA after 'fixed' delay */ \
- /* csmaMinBoExp */ 0, /* Used for fixed backoff */ \
- /* csmaMaxBoExp */ 0, /* Used for fixed backoff */ \
- /* csmaTries */ 1, /* Single try */ \
- /* ccaThreshold */ -75, /* Override if not desired choice */ \
- /* ccaBackoff */ 0, /* No backoff (override with fixed value) */ \
- /* ccaDuration */ 128, /* Override if not desired length */ \
- /* csmaTimeout */ 0, /* no timeout */ \
+#define RAIL_CSMA_CONFIG_SINGLE_CCA { \
+ /* Perform a single CCA after 'fixed' delay */ \
+ /* csmaMinBoExp */ 0, /* Used for fixed backoff */ \
+ /* csmaMaxBoExp */ 0, /* Used for fixed backoff */ \
+ /* csmaTries */ 1, /* Single try */ \
+ /* ccaThreshold */ -75, /* Override if not desired choice */ \
+ /* ccaBackoff */ 0, /* No backoff (override with fixed value) */ \
+ /* ccaDuration */ 128, /* Override if not desired length */ \
+ /* csmaTimeout */ 0, /* no timeout */ \
}
/**
* @struct RAIL_LbtConfig_t
- * @brief This structure is used to configure the LBT algorithm. When using
- * the built-in RAIL_PreTxLbt() algorithm as your pre-transmit hook within
- * RAIL_TxStart(), an instance of this structure must be passed as its
- * argument.
+ * @brief Configuration structure for the LBT transmit algorithm.
*/
typedef struct RAIL_LbtConfig {
/**
@@ -605,9 +1449,9 @@
*/
uint8_t lbtMaxBoRand;
/**
- * Number of CCA failures before report CCA_FAIL. With a maximum value defined
- * in @ref RAIL_MAX_LBT_TRIES). A value of 0 will perform no CCA assessments,
- * and always transmit immediately.
+ * The number of CCA failures before reporting CCA_FAIL. The maximum
+ * supported value for this field is defined in \ref RAIL_MAX_LBT_TRIES.
+ * A value 0 performs no CCA assessments and always transmits immediately.
*/
uint8_t lbtTries;
/**
@@ -616,11 +1460,11 @@
*/
int8_t lbtThreshold;
/**
- * The backoff unit period, in RAIL's microsecond time base. This is
- * mulitiplied by the random backoff multiplier controlled by @ref
+ * The backoff unit period, in RAIL's microsecond time base. It is
+ * multiplied by the random backoff multiplier controlled by @ref
* lbtMinBoRand and @ref lbtMaxBoRand to determine the overall backoff
* period. For random backoffs, any value above 511 microseconds will
- * be truncated; for fixed backoffs it can go up to 65535 microseconds.
+ * be truncated. For fixed backoffs, it can go up to 65535 microseconds.
*/
uint16_t lbtBackoff;
/**
@@ -629,10 +1473,10 @@
uint16_t lbtDuration;
/**
* An overall timeout, in RAIL's microsecond time base, for the
- * operation. If transmission doesn't start before this timeout expires, the
+ * operation. If transmission doesn't start before this timeout expires, the
* transmission will fail. This is important for limiting LBT due to LBT's
* unbounded requirement that if the channel is busy, the next try must wait
- * for the channel to clear. A value of 0 means no timeout is imposed.
+ * for the channel to clear. A value 0 means no timeout is imposed.
*/
uint32_t lbtTimeout;
} RAIL_LbtConfig_t;
@@ -640,245 +1484,100 @@
/**
* @def RAIL_LBT_CONFIG_ETSI_EN_300_220_1_V2_4_1
* @brief RAIL_LbtConfig_t initializer configuring LBT per ETSI 300 220-1
- * V2.4.1 for a typical Sub-GHz band. To be practical, user should override
- * lbtTries and/or lbtTimeout so channel access failure will be reported in a
- * reasonable timeframe rather than the unbounded timeframe ETSI defined.
+ * V2.4.1 for a typical Sub-GHz band. To be practical, users should override
+ * lbtTries and/or lbtTimeout so channel access failure will be reported in a
+ * reasonable time frame rather than the unbounded time frame ETSI defined.
*/
-#define RAIL_LBT_CONFIG_ETSI_EN_300_220_1_V2_4_1 { \
- /* LBT per ETSI 300 220-1 V2.4.1 */ \
- /* LBT time = random backoff of 0-5ms in 0.5ms increments plus 5ms fixed */ \
- /* lbtMinBoRand */ 0, /* */ \
- /* lbtMaxBoRand */ 10, /* */ \
- /* lbtTries */ RAIL_MAX_LBT_TRIES, /* the maximum supported */ \
- /* lbtThreshold */ -87, /* */ \
- /* lbtBackoff */ 500, /* 0.5 ms */ \
- /* lbtDuration */ 5000, /* 5 ms */ \
- /* lbtTimeout */ 0, /* no timeout (recommend user override) */ \
+#define RAIL_LBT_CONFIG_ETSI_EN_300_220_1_V2_4_1 { \
+ /* LBT per ETSI 300 220-1 V2.4.1 */ \
+ /* LBT time = random backoff of 0-5ms in .5ms increments plus 5ms fixed */ \
+ /* lbtMinBoRand */ 0, /* */ \
+ /* lbtMaxBoRand */ 10, /* */ \
+ /* lbtTries */ RAIL_MAX_LBT_TRIES, /* the maximum supported */ \
+ /* lbtThreshold */ -87, /* */ \
+ /* lbtBackoff */ 500, /* 0.5 ms */ \
+ /* lbtDuration */ 5000, /* 5 ms */ \
+ /* lbtTimeout */ 0, /* no timeout (recommend user override) */ \
}
-/**
- * @}
- */
-
-// -----------------------------------------------------------------------------
-// Tx/Rx Configuration Structures
-// -----------------------------------------------------------------------------
-
-/**
- * @addtogroup Transmit
- * @{
- */
-
-// Tx Config Callback Defines
-/** Callback for a transmit buffer overflow event */
-#define RAIL_TX_CONFIG_BUFFER_OVERFLOW (0x01 << 0)
-/** Callback for a transmit buffer underflow event */
-#define RAIL_TX_CONFIG_BUFFER_UNDERFLOW (0x01 << 1)
-/** Callback for CCA/CSMA/LBT failure */
-#define RAIL_TX_CONFIG_CHANNEL_BUSY (0x01 << 2)
-/** Callback for when a Tx is aborted by the user */
-#define RAIL_TX_CONFIG_TX_ABORTED (0x01 << 3)
-/** Callback for when a Tx is blocked by something like PTA or RHO */
-#define RAIL_TX_CONFIG_TX_BLOCKED (0x01 << 4)
-/** Callback for CCA/CSMA/LBT success */
-#define RAIL_TX_CONFIG_CHANNEL_CLEAR (0x01 << 5)
-/** Callback for when an CCA check is being retried */
-#define RAIL_TX_CONFIG_CCA_RETRY (0x01 << 6)
-/** Callback for when a clear channel assessment (CCA) is begun */
-#define RAIL_TX_CONFIG_START_CCA (0x01 << 7)
-
-/**
- * @struct RAIL_TxData_t
- * @brief This structure is used to define the data to transmit. The data is copied
- * into an RAIL space buffer so after RAIL_TxLoadData returns, the pointer
- * can be deallocated or reused.
- */
-typedef struct RAIL_TxData {
- uint8_t *dataPtr; /**< Pointer to data to transmit */
- uint16_t dataLength; /**< Number of bytes to load into transmit buffer */
-} RAIL_TxData_t;
-
-/**
- * @struct RAIL_TxPacketInfo_t
- * @brief Information about the packet that was just transmitted.
- */
-typedef struct RAIL_TxPacketInfo {
- /**
- * Timestamp of the transmitted packet in the RAIL timebase of microseconds.
- * The time is the end of the last bit of the transmitted packet.
- */
- uint32_t timeUs;
- } RAIL_TxPacketInfo_t;
-
-/**
- * @struct RAIL_TxOptions_t
- * @brief Tx Option structure that modifies the transmit. Only applies to one
- * transmit.
- */
-typedef struct RAIL_TxOptions {
- /**
- * Configure if radio should wait for ack after transmit. waitForAck is only
- * honored if Auto Ack is enabled and if Auto Ack Tx is not paused
- */
- bool waitForAck;
-} RAIL_TxOptions_t;
-
-/**
- * @}
- */
+/** @} */ // end of group Transmit
/**
* @addtogroup Receive
* @{
*/
-// Rx Config Callback Defines
-/** Callback for when more is read from the Rx buffer than is available */
-#define RAIL_RX_CONFIG_BUFFER_UNDERFLOW (0x01 << 0)
-/** Callback for preamble detection */
-#define RAIL_RX_CONFIG_PREAMBLE_DETECT (0x01 << 1)
-/** Callback for detection of the first sync word */
-#define RAIL_RX_CONFIG_SYNC1_DETECT (0x01 << 2)
-/** Callback for detection of the second sync word */
-#define RAIL_RX_CONFIG_SYNC2_DETECT (0x01 << 3)
-/** Callback for detection of frame errors
- *
- * For efr32xg1x parts, frame errors include violations of variable length
- * min/max limits, frame coding errors, and crc errors. If \ref
- * RAIL_IGNORE_CRC_ERRORS are set, \ref RAIL_RX_CONFIG_FRAME_ERROR will not be
- * asserted for crc errors.
+/**
+ * @enum RAIL_RxOptions_t
+ * @brief Receive options, in reality a bitmask.
*/
-#define RAIL_RX_CONFIG_FRAME_ERROR (0x01 << 4)
-/** Callback for when we run out of Rx buffer space */
-#define RAIL_RX_CONFIG_BUFFER_OVERFLOW (0x01 << 5)
-/** Callback for when a packet is address filtered */
-#define RAIL_RX_CONFIG_ADDRESS_FILTERED (0x01 << 6)
-/** Callback for RF Sensed */
-#define RAIL_RX_CONFIG_RF_SENSED (0x01 << 7)
-/** Callback for when an Rx event times out */
-#define RAIL_RX_CONFIG_TIMEOUT (0x01 << 8)
-/** Callback for when the scheduled Rx window ends */
-#define RAIL_RX_CONFIG_SCHEDULED_RX_END (0x01 << 9)
-/** Callback for an aborted packet. This is triggered when a more specific
- * reason the packet was aborted, such as RAIL_RX_CONFIG_ADDRESS_FILTERED, is
- * not known. */
-#define RAIL_RX_CONFIG_PACKET_ABORTED (0x01 << 10)
-/**
- * Callback for when the packet has passed any configured address and frame
- * filtering options.
- */
-#define RAIL_RX_CONFIG_FILTER_PASSED (0x01 << 11)
-
-/** To maintain backwards compatibility with RAIL 1.1,
- * RAIL_RX_CONFIG_INVALID_CRC is the same as RAIL_RX_CONFIG_FRAME_ERROR
- */
-#define RAIL_RX_CONFIG_INVALID_CRC RAIL_RX_CONFIG_FRAME_ERROR
+RAIL_ENUM_GENERIC(RAIL_RxOptions_t, uint32_t) {
+ /** Value representing no options enabled. */
+ RAIL_RX_OPTIONS_NONE = 0,
+ /** Default is all options disabled. */
+ RAIL_RX_OPTIONS_DEFAULT = RAIL_RX_OPTIONS_NONE,
-// Rx Option Defines
-/** Option to configure whether the CRC portion of the packet is included in
- * the dataPtr field of the RAIL_RxPacketInfo_t passed via
- * RAILCb_RxPacketReceived(). Defaults to false. */
-#define RAIL_RX_OPTION_STORE_CRC (1 << 0)
-
-// Rx Config Ignore Error Defines
-/**
- * Ignore no errors.
- *
- * Drop all packets with errors. With this setting, crc errors will generate a
- * RAILCb_RxRadioStatus() with \ref RAIL_RX_CONFIG_FRAME_ERROR.
- */
-#define RAIL_IGNORE_NO_ERRORS (0x00)
-/**
- * Hardware ignores CRC errors.
- *
- * When this setting is enabled and a CRC error occurs, RAILCb_RxRadioStatus()
- * with \ref RAIL_RX_CONFIG_FRAME_ERROR will not occur. Instead packets with crc
- * errors will generate RAILCb_RxPacketReceived().
- */
-#define RAIL_IGNORE_CRC_ERRORS (0x01 << 0)
-/** Ignore all possible errors. Receive all possible packets */
-#define RAIL_IGNORE_ALL_ERRORS (0xFF)
-
-/** The value returned by RAIL for an invalid RSSI: (-128 * 4) quarter dBm */
-#define RAIL_RSSI_INVALID ((int16_t)(-128 * 4))
+ /** Shift position of \ref RAIL_RX_OPTION_STORE_CRC bit */
+ RAIL_RX_OPTION_STORE_CRC_SHIFT = 0,
+ /** Shift position of \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS bit */
+ RAIL_RX_OPTION_IGNORE_CRC_ERRORS_SHIFT,
+ /** Shift position of \ref RAIL_RX_OPTION_ENABLE_DUALSYNC bit */
+ RAIL_RX_OPTION_ENABLE_DUALSYNC_SHIFT,
+ /** Shift position of \ref RAIL_RX_OPTION_TRACK_ABORTED_FRAMES bit */
+ RAIL_RX_OPTION_TRACK_ABORTED_FRAMES_SHIFT,
+ /** Shift position of \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO bit */
+ RAIL_RX_OPTION_REMOVE_APPENDED_INFO_SHIFT,
-/**
- * @struct RAIL_AppendedInfo_t
- * @brief Appended info structure that is returned in the RAILCb_RxPacketReceived
- * callback
- *
- * @todo Define where the rssi latch point is. Is it configurable?
- */
-typedef struct RAIL_AppendedInfo {
/**
- * Timestamp of the received packet in the RAIL timebase of microseconds. The
- * time is the end of the sync word of the received packet.
- */
- uint32_t timeUs;
- /**
- * Indicates whether the CRC passed or failed for the receive packet. This
- * will be set to 0 for fail and 1 for pass.
+ * Option to configure whether the CRC portion of the packet is included in
+ * the packet payload exposed to the app on packet reception.
+ * Defaults to false.
*/
- bool crcStatus:1;
- /**
- * Indicates whether frame coding found any errors in the receive packet.
- * This will be set to 0 for fail and 1 for pass.
- */
- bool frameCodingStatus:1;
+ RAIL_RX_OPTION_STORE_CRC
+ = (1ul << RAIL_RX_OPTION_STORE_CRC_SHIFT),
/**
- * Indicates if the received packet is an ack. An 'ack' is defined as a
- * packet received during the rx ack window when autoack is enabled.
- * Set to 0 for not an ack, and 1 for is an ack. Will always be 0 if
- * autoack is not enabled.
+ * Option to configure whether CRC errors will be ignored
+ * if this is set, RX will still be successful, even if
+ * the CRC does not pass the check. Defaults to false.
*/
- bool isAck:1;
+ RAIL_RX_OPTION_IGNORE_CRC_ERRORS
+ = (1ul << RAIL_RX_OPTION_IGNORE_CRC_ERRORS_SHIFT),
/**
- * RSSI of the received packet in integer dBm. This is latched when the sync
- * word is detected for this packet.
+ * Option to configure which out of SYNC0 and SYNC1
+ * will be sent as the sync word during transmit.
+ * Defaults to false (SYNC0).
*/
- int8_t rssiLatch;
+ RAIL_RX_OPTION_ENABLE_DUALSYNC
+ = (1ul << RAIL_RX_OPTION_ENABLE_DUALSYNC_SHIFT),
/**
- * Link quality indicator of the received packet. This is calculated as the
- * average correlation for the first 8 symbols in a frame.
+ * Option to configure whether frames which are aborted during reception
+ * should continue to be tracked. Setting this option allows viewing Packet
+ * Trace information for frames which get discarded. Defaults to false.
*/
- uint8_t lqi;
+ RAIL_RX_OPTION_TRACK_ABORTED_FRAMES
+ = (1ul << RAIL_RX_OPTION_TRACK_ABORTED_FRAMES_SHIFT),
/**
- * For radios and PHY configurations that support multiple sync words this
- * number will be the ID of the sync word that was used for this packet.
+ * Option to configure whether appended info is included after received
+ * frames. Default is false.
*/
- uint8_t syncWordId;
-} RAIL_AppendedInfo_t;
+ RAIL_RX_OPTION_REMOVE_APPENDED_INFO
+ = (1ul << RAIL_RX_OPTION_REMOVE_APPENDED_INFO_SHIFT),
-/**
- * @struct RAIL_RxPacketInfo_t
- * @brief Receive packet information structure
- *
- * The structure used to pass an over the air packet and some associated
- * information up to the application code. The memory handle that you receive
- * in the call to RAILCb_RxPacketReceived() will contain this data structure.
- */
-typedef struct RAIL_RxPacketInfo {
- /**
- * A structure containing the extra information associated with this received
- * packet.
- */
- RAIL_AppendedInfo_t appendedInfo;
- /**
- * The number of bytes that are in the dataPtr array.
- */
- uint16_t dataLength;
- /**
- * A variable length array holding the receive packet data bytes.
- */
- uint8_t dataPtr[];
-} RAIL_RxPacketInfo_t;
+ /** Value representing all possible options */
+ RAIL_RX_OPTIONS_ALL = 0xFFFFFFFFul
+};
+
+/** The value returned by RAIL for an invalid RSSI, in dBm */
+#define RAIL_RSSI_INVALID_DBM (-128)
+/** The value returned by RAIL for an invalid RSSI: in quarter dBm */
+#define RAIL_RSSI_INVALID ((int16_t)(RAIL_RSSI_INVALID_DBM * 4))
/**
* @struct RAIL_ScheduleRxConfig_t
- * @brief This structure is used to configure the Scheduled Rx algorithm.
+ * @brief Configures the scheduled RX algorithm.
*
- * It allows you to define the start and end times of the receive window created
- * for scheduled receive. If either start or end times are disabled then they
+ * Defines the start and end times of the receive window created
+ * for a scheduled receive. If either start or end times are disabled, they
* will be ignored.
*/
typedef struct RAIL_ScheduleRxConfig {
@@ -891,7 +1590,8 @@
* How to interpret the time value specified in the start parameter. See the
* \ref RAIL_TimeMode_t documentation for more information. Use
* \ref RAIL_TIME_ABSOLUTE for absolute times, \ref RAIL_TIME_DELAY for times
- * relative to now, and \ref RAIL_TIME_DISABLED to ignore the start time.
+ * relative to the current time, and \ref RAIL_TIME_DISABLED to ignore the
+ * start time.
*/
RAIL_TimeMode_t startMode;
/**
@@ -901,34 +1601,231 @@
uint32_t end;
/**
* How to interpret the time value specified in the end parameter. See the
- * \ref RAIL_TimeMode_t documentation for more information. Note that in this
- * API if you specify a \ref RAIL_TIME_DELAY it will be relative to the start
- * time if given and relative to now if none is specified. Also, using \ref
- * RAIL_TIME_DISABLED means that this window will not end unless you
+ * \ref RAIL_TimeMode_t documentation for more information. Note that, in
+ * this API, if you specify a \ref RAIL_TIME_DELAY, it is relative to the
+ * start time if given and relative to now if none is specified. Also, using
+ * \ref RAIL_TIME_DISABLED means that this window will not end unless you
* explicitly call RAIL_RfIdle() or add an end event through a future update
* to this configuration.
*/
RAIL_TimeMode_t endMode;
/**
- * While in scheduled Rx you are still able to control the radio state via
- * state transitions. This option allows you to configure whether a transition
- * to Rx goes back to scheduled Rx or to the normal Rx state. Once in the
- * normal Rx state you will effectively end the scheduled Rx window and can
- * continue to receive indefinitely depending on your state transitions. Set
- * this to 1 to transition to normal Rx and 0 to stay in scheduled Rx.
+ * While in scheduled RX, you can still control the radio state via
+ * state transitions. This option configures whether a transition
+ * to RX goes back to scheduled RX or to the normal RX state. Once in the
+ * normal RX state, you will effectively end the scheduled RX window and can
+ * continue to receive indefinitely depending on the state transitions. Set
+ * to 1 to transition to normal RX and 0 to stay in the scheduled RX.
*/
uint8_t rxTransitionEndSchedule;
/**
- * If set to 0 this will allow any packets being received when the window end
- * event occurs to complete. If set to anything else we will force an abort of
- * any packets being received when the window end occurs.
+ * If set to 0, this will allow any packets, which are received when the
+ * window end event occurs, to complete. If set to anything else, an abort
+ * of any packets received when the window end occurs is forced.
*/
uint8_t hardWindowEnd;
} RAIL_ScheduleRxConfig_t;
/**
- * @}
+ * @enum RAIL_RxPacketStatus_t
+ * @brief The packet status code associated with a packet received or
+ * currently being received.
+ *
+ * @note RECEIVING implies some packet data may be available, but
+ * is untrustworthy (not CRC-verified) and might disappear if the packet
+ * is rolled back on error.
+ * @note In RX FIFO mode, ABORT statuses imply some packet data may be
+ * available, but it's incomplete and not trustworthy.
+ * @note READY statuses indicate all packet data is available, including
+ * packet details (if enabled), but only \ref RAIL_RX_PACKET_READY_SUCCESS
+ * indicates the packet data is trustworthy.
+ */
+RAIL_ENUM(RAIL_RxPacketStatus_t) {
+ RAIL_RX_PACKET_NONE = 0, /**< Radio is idle or searching for a packet. */
+ RAIL_RX_PACKET_ABORT_FORMAT, /**< Format/Length error. */
+ RAIL_RX_PACKET_ABORT_FILTERED, /**< Filtering error (address). */
+ RAIL_RX_PACKET_ABORT_ABORTED, /**< Aborted error. */
+ RAIL_RX_PACKET_ABORT_OVERFLOW, /**< Receive overflowed buffer. */
+ RAIL_RX_PACKET_ABORT_CRC_ERROR, /**< CRC error aborted. */
+ RAIL_RX_PACKET_READY_CRC_ERROR, /**< CRC error accepted (details available). */
+ RAIL_RX_PACKET_READY_SUCCESS, /**< Success (details available). */
+ RAIL_RX_PACKET_RECEIVING, /**< Receiving in progress. */
+};
+
+/**
+ * @typedef RAIL_RxPacketHandle_t
+ * @brief A handle used to reference a packet during reception processing.
+ * There are several sentinel handle values that pertain to certain
+ * circumstances: \ref RAIL_RX_PACKET_HANDLE_INVALID, \ref
+ * RAIL_RX_PACKET_HANDLE_OLDEST and \ref RAIL_RX_PACKET_HANDLE_NEWEST.
+ */
+typedef const void *RAIL_RxPacketHandle_t;
+
+/** Invalid RX packet handle value */
+#define RAIL_RX_PACKET_HANDLE_INVALID (NULL)
+/** Special RX packet handle to refer to the oldest unreleased packet */
+#define RAIL_RX_PACKET_HANDLE_OLDEST ((RAIL_RxPacketHandle_t) 1)
+/** Special RX packet handle to refer to the newest unreleased packet
+ * when in callback context. For a callback involving a completed
+ * receive event, this refers to the packet just completed. For
+ * other callback events, this refers to the next packet to be
+ * completed, which might be in-progress or might not have even
+ * started yet.
+ */
+#define RAIL_RX_PACKET_HANDLE_NEWEST ((RAIL_RxPacketHandle_t) 2)
+
+/**
+ * @struct RAIL_RxPacketInfo_t
+ * @brief Basic information about a packet being received or already
+ * completed and awaiting processing, including memory pointers to
+ * its data in the circular RX FIFO buffer. This packet information
+ * refers to remaining packet data that has not already been consumed
+ * by RAIL_ReadRxFifo().
+ * @note Because the RX FIFO buffer is circular, a packet might start
+ * near the end of the buffer and wrap around to the beginning of
+ * the buffer to finish, hence the distinction between the first
+ * and last portions. Packets that fit without wrapping only have
+ * a first portion (firstPortionBytes == packetBytes).
+ */
+typedef struct RAIL_RxPacketInfo {
+ RAIL_RxPacketStatus_t packetStatus; /**< Packet status of this packet. */
+ uint16_t packetBytes; /**< Number of packet data bytes
+ available to read in this packet. */
+ uint16_t firstPortionBytes; /**< Number of bytes in first portion. */
+ uint8_t *firstPortionData; /**< Pointer to first portion of packet
+ data containing firstPortionBytes
+ number of bytes. */
+ uint8_t *lastPortionData; /**< Pointer to last portion of
+ packet (if any). The number of
+ bytes in this portion is
+ packetBytes - firstPortionBytes. */
+} RAIL_RxPacketInfo_t;
+
+/**
+ * @struct RAIL_RxPacketDetails_t
+ * @brief Successfully received packet details obtained via
+ * RAIL_GetRxPacketDetails().
+ *
*/
+typedef struct RAIL_RxPacketDetails {
+ /**
+ * Timestamp of the received packet in the RAIL timebase. The
+ * time is the end of the sync word of the received packet.
+ */
+ RAIL_PacketTimeStamp_t timeReceived;
+ /**
+ * Indicates whether the CRC passed or failed for the receive packet. It
+ * is set to 0 for fail and 1 for pass.
+ */
+ bool crcPassed;
+ /**
+ * Indicates whether the received packet is an ACK. An 'ACK' is defined as a
+ * packet received during the RX ACK window when auto ACK is enabled.
+ * Set to 0 if not an ACK, and 1 for an ACK. It is always 0 if
+ * auto ACK is not enabled.
+ */
+ bool isAck;
+ /**
+ * RSSI of the received packet in integer dBm. It is latched when the sync
+ * word is detected for the packet.
+ */
+ int8_t rssi;
+ /**
+ * Link quality indicator of the received packet. It is calculated as the
+ * average correlation for the first 8 symbols in a frame.
+ */
+ uint8_t lqi;
+ /**
+ * For radios and PHY configurations that support multiple sync words, this
+ * number is the ID of the sync word that was used for this packet.
+ */
+ uint8_t syncWordId;
+ /**
+ * In configurations where the radio has the option of receiving a given
+ * packet in multiple ways, indicates which of the sub-PHY options
+ * was used to receive the packet. Most radio configurations do not have
+ * this ability, and the subPhy is set to 0 in those cases.
+ */
+ uint8_t subPhyId;
+} RAIL_RxPacketDetails_t;
+
+/**
+ * @addtogroup Address_Filtering
+ * @{
+ */
+
+/// Default address filtering match table for configurations that use only one
+/// address field. The truth table for address matching is shown below.
+///
+/// | | 0000 | 0001 | 0010 | 0100 | 1000 |
+/// |----------|------|------|------|------|------|
+/// | __0000__ | 0 | 1 | 1 | 1 | 1 |
+/// | __0001__ | 1 | 1 | 1 | 1 | 1 |
+/// | __0010__ | 1 | 1 | 1 | 1 | 1 |
+/// | __0100__ | 1 | 1 | 1 | 1 | 1 |
+/// | __1000__ | 1 | 1 | 1 | 1 | 1 |
+///
+#define ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD (0x1fffffe)
+/// Default address filtering match table for configurations that use two
+/// address fields and want to match the same index in each. The truth
+/// table for address matching is shown below.
+///
+/// | | 0000 | 0001 | 0010 | 0100 | 1000 |
+/// |----------|------|------|------|------|------|
+/// | __0000__ | 0 | 0 | 0 | 0 | 0 |
+/// | __0001__ | 0 | 1 | 0 | 0 | 0 |
+/// | __0010__ | 0 | 0 | 1 | 0 | 0 |
+/// | __0100__ | 0 | 0 | 0 | 1 | 0 |
+/// | __1000__ | 0 | 0 | 0 | 0 | 1 |
+#define ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD (0x1041040)
+
+/// The maximum number of address fields that can be used by the address
+/// filtering logic.
+#define ADDRCONFIG_MAX_ADDRESS_FIELDS (2)
+
+/**
+ * @struct RAIL_AddrConfig_t
+ * @brief A structure to configure the address filtering functionality in RAIL.
+ */
+typedef struct RAIL_AddrConfig {
+ /**
+ * A list of the start offsets for each field.
+ *
+ * These offsets are specified relative to the previous field's end. In the
+ * case of the first field it's relative to either the beginning of the packet
+ * or the end of the frame type byte if frame type decoding is enabled. If a
+ * field is unused, it's offset should be set to 0.
+ */
+ uint8_t offsets[ADDRCONFIG_MAX_ADDRESS_FIELDS];
+
+ /**
+ * A list of the address field sizes.
+ *
+ * These sizes are specified in bytes from 0 to 8. If you choose a
+ * size of 0, this field is effectively disabled.
+ */
+ uint8_t sizes[ADDRCONFIG_MAX_ADDRESS_FIELDS];
+
+ /**
+ * The truth table to determine how the two fields combine to create a match.
+ *
+ * For detailed information about how this truth table is formed see the
+ * detailed description of @ref Address_Filtering.
+ *
+ * For simple predefined configurations you can use the following defines.
+ * - ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD
+ * - For filtering that only uses a single address field
+ * - ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD for two field filtering where you
+ * - For filtering that uses two address fields in a configurations where
+ * you want the following logic `((Field0, Index0) && (Field1, Index0))
+ * || ((Field0, Index1) && (Field1, Index1)) || ...`
+ */
+ uint32_t matchTable;
+} RAIL_AddrConfig_t;
+
+/** @} */ // end of group Address_Filtering
+
+/** @} */ // end of group Receive
/**
* @addtogroup Auto_Ack
@@ -936,59 +1833,98 @@
*/
/**
* @struct RAIL_AutoAckConfig_t
- * @brief This structure is used to configure the Auto Ack algorithm. The
- * structure provides a defaultState for the radio to return to once an ack
- * operation occurs (transmitting or attempting to receive an ack). Regardless
- * if the ack operation was successful, the radio will return to the specified
+ * @brief Enables/disables the auto ACK algorithm, based on "enable". The
+ * structure provides a default state (the "success" of tx/rxTransitions
+ * when acking is being enabled) for the radio to return to after an ACK
+ * operation occurs (transmitting or attempting to receive an ACK), or normal
+ * state transitions to return to in the case that acking is being
+ * disabled. Regardless whether the ACK operation was successful, the
+ * radio returns to the specified success state.
+ *
+ * ackTimeout specifies how long to stay in receive and wait for an ACK
+ * before issuing a RAIL_EVENT_RX_ACK_TIMEOUT event and return to the
* default state.
- *
- * The other parameters configure auto ack timing. The application can specify
- * timing from when the radio is idle to TX/RX, the turnaround time from TX->RX
- * and RX->TX, and finally the total amount of time to look for an ack. All of
- * these timing parameters are in microseconds.
*/
typedef struct RAIL_AutoAckConfig {
/**
- * Default state once auto ack sequence completes or errors. Can only be
- * RAIL_RF_STATE_RX or RAIL_RF_STATE_IDLE.
- */
- RAIL_RadioState_t defaultState;
- /**
- * Define the time from idleToTx and idleToRx in us. Limited to a max of
- * 13ms.
+ * Indicate whether auto-acking should be enabled or disabled.
*/
- uint16_t idleTiming;
+ bool enable;
/**
- * Define the ack turnaround time in us. Limited to a max of 13ms.
- */
- uint16_t turnaroundTime;
- /**
- * Define the rx ack timeout duration in us. Limited to a max of 65.535ms.
+ * Define the RX ACK timeout duration in µs. Limited to a maximum 65.535 ms.
+ * Only applied when auto acking is enabled. Triggers a
+ * RAIL_EVENT_RX_ACK_TIMEOUT event if this threshold is exceeded.
*/
uint16_t ackTimeout;
+ /**
+ * State transitions to do after receiving a packet. When auto acking is
+ * enabled, the "error" transition is always ignored and the radio will
+ * return to the "success" state after any acking sequence. See
+ * \ref RAIL_ConfigAutoAck for more details on this.
+ */
+ RAIL_StateTransitions_t rxTransitions;
+ /**
+ * State transitions to do after transmitting a packet. When auto acking is
+ * enabled, the "error" transition is always ignored and the radio will
+ * return to the "success" state after any acking sequence. See
+ * \ref RAIL_ConfigAutoAck for more details on this.
+ */
+ RAIL_StateTransitions_t txTransitions;
} RAIL_AutoAckConfig_t;
+/// Acknowledgment packets cannot be longer than 64 bytes.
+#define RAIL_AUTOACK_MAX_LENGTH 64
+
+/** @} */ // end of group Auto_Ack
+
+/******************************************************************************
+ * Calibration Structures
+ *****************************************************************************/
+/**
+ * @addtogroup Calibration
+ * @{
+ */
+
/**
- * @struct RAIL_AutoAckData_t
- * @brief This structure is used to define the data to use during auto
- * acknowledgement. The data is copied into an RAIL space buffer so after
- * RAIL_AutoAckLoadBuffer returns, the pointer can be deallocated or reused.
+ * @typedef RAIL_CalMask_t
+ * @brief Calibration mask type
*
- * Size limited to \ref RAIL_AUTOACK_MAX_LENGTH.
+ * This type is a bitmask of different RAIL calibration values. The exact
+ * meaning of these bits depends on what a particular chip supports.
+ */
+typedef uint32_t RAIL_CalMask_t;
+
+/** @} */ // end of group Calibration
+
+/******************************************************************************
+ * RF Sense Structures
+ *****************************************************************************/
+/**
+ * @addtogroup Rf_Sense
+ * @{
*/
-typedef struct RAIL_AutoAckData {
- uint8_t *dataPtr; /**< Pointer to ack data to transmit */
- uint8_t dataLength; /**< Number of ack bytes to transmit */
-} RAIL_AutoAckData_t;
+
+/**
+ * A pointer to an rfsense callback function.
+ */
+typedef void (*RAIL_RfSense_CallbackPtr_t)(void);
-/// Acknowledgement packets cannot be longer than 64 bytes.
-#define RAIL_AUTOACK_MAX_LENGTH 64
/**
- * @}
- * endofgroup AutoAck
+ * @enum RAIL_RfSenseBand_t
+ * @brief Enumeration for specifying Rf Sense frequency band.
*/
+RAIL_ENUM(RAIL_RfSenseBand_t) {
+ RAIL_RFSENSE_OFF, /**< RFSense is disabled */
+ RAIL_RFSENSE_2_4GHZ, /**< RFSense is in 2.4 G band */
+ RAIL_RFSENSE_SUBGHZ, /**< RFSense is in subgig band */
+ RAIL_RFSENSE_ANY, /**< RfSense is in both bands */
+ RAIL_RFSENSE_MAX // Must be last
+};
+
+/** @} */ // end of group Rf_Sense
+
/******************************************************************************
- * Version
+ * Diagnositc Structures
*****************************************************************************/
/**
* @addtogroup Diagnostic
@@ -999,67 +1935,48 @@
* @enum RAIL_StreamMode_t
* @brief Possible stream output modes.
*/
-typedef enum RAIL_StreamMode {
- PSEUDO_RANDOM_STREAM, /**< Pseudo random stream of bytes */
- PN9_STREAM /**< PN9 byte sequence */
-} RAIL_StreamMode_t;
+RAIL_ENUM(RAIL_StreamMode_t) {
+ RAIL_STREAM_CARRIER_WAVE = 0, /**< Unmodulated carrier wave */
+ RAIL_STREAM_PN9_STREAM = 1, /**< PN9 byte sequence */
+};
-/**
- * @struct RAIL_BerConfig_t
- * @brief BER test parameters.
- */
-typedef struct RAIL_BerConfig
-{
- uint32_t bytesToTest; /**< Number of bytes to test */
-} RAIL_BerConfig_t;
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
-/**
- * @struct RAIL_BerStatus_t
- * @brief The status of the latest bit error rate (BER) test.
- */
-typedef struct RAIL_BerStatus
-{
- uint32_t bitsTotal; /**< Number of bits to receive */
- uint32_t bitsTested; /**< Number of bits currently tested */
- uint32_t bitErrors; /**< Number of bits errors detected */
- int8_t rssi; /**< Latched RSSI value at pattern detect */
-} RAIL_BerStatus_t;
+typedef struct RAIL_DirectModeConfig {
+ bool enable; /**< Indicates whether to enable direct mode. */
+} RAIL_DirectModeConfig_t;
-/**
- * @}
- */
+#endif//DOXYGEN_SHOULD_SKIP_THIS
+
+/** @} */ // end of group Diagnostic
#ifndef DOXYGEN_SHOULD_SKIP_THIS
/******************************************************************************
- * Debug
+ * Debug Structures
*****************************************************************************/
/**
* @addtogroup Debug
* @{
*/
-// Debug Config Callback Defines
-/** Callback for radio state change */
-#define RAIL_DEBUG_CONFIG_STATE_CHANGE (0x01 << 1)
-
/**
* @def RAIL_DEBUG_MODE_FREQ_OVERRIDE
- * @brief A bitmask to enable the frequency override debug mode where you can
+ * @brief A bitmask to enable the frequency override debug mode to
* manually tune to a specified frequency. Note that this should only be used
* for testing and is not as tuned as frequencies from the calculator.
*/
#define RAIL_DEBUG_MODE_FREQ_OVERRIDE 0x00000001UL
+
/**
* @def RAIL_DEBUG_MODE_VALID_MASK
* @brief Any debug mode bits outside of this mask are invalid and ignored.
*/
#define RAIL_DEBUG_MODE_VALID_MASK (!(RAIL_DEBUG_MODE_FREQ_OVERRIDE))
-/**
- * @}
- */
-#endif
+/** @} */ // end of group Debug
+
+#endif//DOXYGEN_SHOULD_SKIP_THIS
/**
* @}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/timing_state.h Thu Dec 07 14:01:42 2017 +0000
@@ -0,0 +1,56 @@
+/***************************************************************************//**
+ * @file timing_state.h
+ * @brief RADIO API Abstraction layer for setting state timing information
+ * @version INTERNAL
+ *******************************************************************************
+ * @section License
+ * <b>(C) Copyright 2017 Silicon Labs, http://silabs.com</b>
+ ******************************************************************************/
+#ifndef __TIMING_STATE_H
+#define __TIMING_STATE_H
+
+#include <stdint.h>
+#include "em_device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ ******************************* STRUCTS ***********************************
+ ******************************************************************************/
+
+// All the timing information for state transitions
+typedef struct StateTimings {
+ int32_t rxChainDelayNs;
+#if (_SILICON_LABS_32B_SERIES_1_CONFIG == 1) \
+ || (_SILICON_LABS_32B_SERIES_1_CONFIG == 4)
+ // On Dumbo the RX2TX time is based on the RXDONE time, which is stable enough
+ // for our purposes. However, the timestamp is still based on FRAMEDET, so we
+ // need two delays, one for the chain delay (FRAMEDET delay), and the second
+ // for the RXDONE delay, which we use for RX2TX transitions only.
+
+ // On Nixi the RX2TX time and the timestamp are based on RXDONE. The chain
+ // delay for RX only calculates how long we need to stay in RX to get SYNC,
+ // which does not need to be precise. (And hard to measure.)
+ int32_t rxDoneDelayNs;
+#endif
+ int32_t txChainDelayNs;
+ uint16_t rxSearch;
+ uint16_t txToRxSearch;
+ uint16_t rxWarm;
+ uint16_t rxToTx;
+ uint16_t rxFrameToTx;
+ uint16_t txWarm;
+ uint16_t txToRx;
+ uint16_t txToTx;
+} StateTimings_t;
+
+/** @} (end addtogroup TIMING) */
+/** @} (end addtogroup RF_Library) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIMING_STATE_H */
--- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/mbed_lib.json Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/mbed_lib.json Thu Dec 07 14:01:42 2017 +0000
@@ -8,7 +8,7 @@
"PTI": true,
"has-2p4": false,
"has-subgig": false,
- "pti-mode": "RADIO_PTI_MODE_UART",
+ "pti-mode": "RAIL_PTI_MODE_UART",
"pti-baudrate" : 1600000,
"pti-dout-location": 6,
"pti-dout-port": "gpioPortB",
--- a/targets/targets.json Thu Nov 23 11:57:25 2017 +0000
+++ b/targets/targets.json Thu Dec 07 14:01:42 2017 +0000
@@ -731,12 +731,14 @@
"inherits": ["Target"],
"detect_code": ["1056"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "features": ["LWIP"],
"release_versions": ["2", "5"],
"device_name" : "LPC54618J512ET180"
},
"FF_LPC546XX": {
"inherits": ["LPC546XX"],
"extra_labels_remove" : ["LPCXpresso"],
+ "features_remove": ["LWIP"],
"supported_form_factors": [""],
"detect_code": ["8081"]
},
@@ -1379,7 +1381,7 @@
}
},
"detect_code": ["0770"],
- "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "CAN", "TRNG", "FLASH"],
+ "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "CAN", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32L432KC"
},
@@ -1505,7 +1507,7 @@
"core": "Cortex-M4F",
"extra_labels_add": ["STM32F4", "STM32F407", "STM32F407xG", "STM32F407VG"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
- "macros_add": ["USB_STM_HAL"],
+ "macros_add": ["RTC_LSI=1", "USB_STM_HAL"],
"device_has_add": ["ANALOGOUT"],
"device_name": "STM32F407VG"
},
@@ -1525,10 +1527,11 @@
"macro_name": "CLOCK_SOURCE_USB"
}
},
- "macros_add": ["RTC_LSI=1", "USBHOST_OTHER"],
+ "macros_add": ["RTC_LSI=1", "USB_STM_HAL", "USBHOST_OTHER"],
"device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
- "device_name": "STM32F429ZI"
+ "device_name": "STM32F429ZI",
+ "bootloader_supported": true
},
"DISCO_F469NI": {
"inherits": ["FAMILY_STM32"],
@@ -1570,7 +1573,6 @@
"core": "Cortex-M0+",
"extra_labels_add": ["STM32L0", "STM32L072CZ", "STM32L072xx"],
"supported_form_factors": ["ARDUINO", "MORPHO"],
- "macros": ["RTC_LSI=1"],
"config": {
"clock_source": {
"help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
@@ -1593,6 +1595,10 @@
"help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
"value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
"macro_name": "CLOCK_SOURCE"
+ },
+ "usb_speed": {
+ "help": "Select the USB speed/connector (0=FullSpeed, 1=HighSpeed)",
+ "value": "1"
}
},
"detect_code": ["0815"],
@@ -2761,7 +2767,7 @@
},
"EFR32MG1P132F256GM48": {
"inherits": ["EFM32"],
- "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"],
+ "extra_labels_add": ["EFR32MG1", "EFR32_1", "256K", "SL_RAIL", "SL_CRYPTO"],
"core": "Cortex-M4F",
"macros_add": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
"supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
@@ -2772,7 +2778,7 @@
},
"EFR32MG1P233F256GM48": {
"inherits": ["EFM32"],
- "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"],
+ "extra_labels_add": ["EFR32MG1", "EFR32_1", "256K", "SL_RAIL", "SL_CRYPTO"],
"core": "Cortex-M4F",
"macros_add": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
"supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
@@ -2914,7 +2920,7 @@
},
"EFR32MG12P332F1024GL125": {
"inherits": ["EFM32"],
- "extra_labels_add": ["EFR32MG12", "1024K", "SL_RAIL", "SL_CRYPTO"],
+ "extra_labels_add": ["EFR32MG12", "EFR32_12", "1024K", "SL_RAIL", "SL_CRYPTO"],
"core": "Cortex-M4F",
"macros_add": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
"supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
@@ -3192,7 +3198,7 @@
"inherits": ["Target"],
"core": "Cortex-M4F",
"macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
- "device_has": ["STCLK_OFF_DURING_SLEEP"],
+ "device_has": ["STCLK_OFF_DURING_SLEEP"],
"extra_labels": ["NORDIC", "MCU_NRF52840", "NRF5", "SDK13", "NRF52_COMMON"],
"OUTPUT_EXT": "hex",
"is_disk_virtual": true,
@@ -3521,5 +3527,22 @@
"device_name": "TMPM066FWUG",
"detect_code": ["7011"],
"release_versions": ["5"]
+ },
+ "SAKURAIO_EVB_01": {
+ "inherits": ["FAMILY_STM32"],
+ "supported_form_factors": [],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F411xE", "STM32F411RE"],
+ "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+ "value": "USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "device_has_add": ["LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+ "release_versions": ["2"],
+ "device_name": "STM32F411RE"
}
}
