mbed official
USBHost library. NOTE: This library is only officially supported on the LPC1768 platform. For more information, please see the handbook page.
Dependencies: FATFileSystem mbed-rtos
Dependents: BTstack WallbotWii SD to Flash Data Transfer USBHost-MSD_HelloWorld ... more
Legacy Warning
This is an mbed 2 library. To learn more about mbed OS 5, visit the docs.
Pull requests against this repository are no longer supported. Please raise against mbed OS 5 as documented above.
Revision 27:4206883f4cb7, committed 2015-01-19
- Comitter:
- mbed_official
- Date:
- Mon Jan 19 14:30:37 2015 +0000
- Parent:
- 26:607951c26872
- Child:
- 28:8e62b6403505
- Commit message:
- Synchronized with git revision 0ab8d2e6b3d884137dcb5c62d29a07abe132bac7
Full URL: https://github.com/mbedmicro/mbed/commit/0ab8d2e6b3d884137dcb5c62d29a07abe132bac7/
RZ_A1H - Implement some USB functions and fix some bugs about USBHost common codes.
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_host_api.h Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,332 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : devdrv_usb_host_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB_HOST_API_H
+#define USB_HOST_API_H
+
+#include "r_typedefs.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define USB_HOST_PORTNUM (2)
+
+#define USB_HOST_ELT_INTERRUPT_LEVEL (9)
+
+#define USBHCLOCK_X1_48MHZ (0x0000u) /* USB_X1_48MHz */
+#define USBHCLOCK_EXTAL_12MHZ (0x0004u) /* EXTAL_12MHz */
+
+#define USB_HOST_MAX_DEVICE (10)
+
+#define USB_HOST_ON (1)
+#define USB_HOST_OFF (0)
+#define USB_HOST_YES (1)
+#define USB_HOST_NO (0)
+
+#define USB_HOST_NON_SPEED (0)
+#define USB_HOST_LOW_SPEED (1)
+#define USB_HOST_FULL_SPEED (2)
+#define USB_HOST_HIGH_SPEED (3)
+
+/* DEVDRV_SUCCESS(0) & DEVDRV_ERROR(-1) is dev_drv.h */
+#define DEVDRV_USBH_STALL (-2)
+#define DEVDRV_USBH_TIMEOUT (-3)
+#define DEVDRV_USBH_NAK_TIMEOUT (-4)
+#define DEVDRV_USBH_DETACH_ERR (-5)
+#define DEVDRV_USBH_SETUP_ERR (-6)
+#define DEVDRV_USBH_CTRL_COM_ERR (-7)
+#define DEVDRV_USBH_COM_ERR (-8)
+#define DEVDRV_USBH_DEV_ADDR_ERR (-9)
+
+#define USB_HOST_ATTACH (1)
+#define USB_HOST_DETACH (0)
+
+#define USB_HOST_MAX_PIPE_NO (9u)
+#define USB_HOST_PIPE0 (0)
+#define USB_HOST_PIPE1 (1)
+#define USB_HOST_PIPE2 (2)
+#define USB_HOST_PIPE3 (3)
+#define USB_HOST_PIPE4 (4)
+#define USB_HOST_PIPE5 (5)
+#define USB_HOST_PIPE6 (6)
+#define USB_HOST_PIPE7 (7)
+#define USB_HOST_PIPE8 (8)
+#define USB_HOST_PIPE9 (9)
+
+#define USB_HOST_ISO (0xc000u)
+#define USB_HOST_INTERRUPT (0x8000u)
+#define USB_HOST_BULK (0x4000u)
+
+#define USB_HOST_PIPE_IDLE (0x00)
+#define USB_HOST_PIPE_WAIT (0x01)
+#define USB_HOST_PIPE_DONE (0x02)
+#define USB_HOST_PIPE_NORES (0x03)
+#define USB_HOST_PIPE_STALL (0x04)
+#define USB_HOST_PIPE_ERROR (0x05)
+
+#define USB_HOST_NONE (0x0000u)
+#define USB_HOST_BFREFIELD (0x0400u)
+#define USB_HOST_BFREON (0x0400u)
+#define USB_HOST_BFREOFF (0x0000u)
+#define USB_HOST_DBLBFIELD (0x0200u)
+#define USB_HOST_DBLBON (0x0200u)
+#define USB_HOST_DBLBOFF (0x0000u)
+#define USB_HOST_CNTMDFIELD (0x0100u)
+#define USB_HOST_CNTMDON (0x0100u)
+#define USB_HOST_CNTMDOFF (0x0000u)
+#define USB_HOST_SHTNAKON (0x0080u)
+#define USB_HOST_SHTNAKOFF (0x0000u)
+#define USB_HOST_DIRFIELD (0x0010u)
+#define USB_HOST_DIR_H_OUT (0x0010u)
+#define USB_HOST_DIR_H_IN (0x0000u)
+#define USB_HOST_EPNUMFIELD (0x000fu)
+
+#define USB_HOST_CUSE (0)
+#define USB_HOST_D0USE (1)
+#define USB_HOST_D0DMA (2)
+#define USB_HOST_D1USE (3)
+#define USB_HOST_D1DMA (4)
+
+#define USB_HOST_CFIFO_USE (0x0000)
+#define USB_HOST_D0FIFO_USE (0x1000)
+#define USB_HOST_D1FIFO_USE (0x2000)
+#define USB_HOST_D0FIFO_DMA (0x5000)
+#define USB_HOST_D1FIFO_DMA (0x6000)
+
+#define USB_HOST_BUF2FIFO (0)
+#define USB_HOST_FIFO2BUF (1)
+
+#define USB_HOST_DRV_DETACHED (0x0000)
+#define USB_HOST_DRV_ATTACHED (0x0001)
+#define USB_HOST_DRV_GET_DEVICE_DESC_64 (0x0002)
+#define USB_HOST_DRV_POWERED (0x0003)
+#define USB_HOST_DRV_DEFAULT (0x0004)
+#define USB_HOST_DRV_SET_ADDRESS (0x0005)
+#define USB_HOST_DRV_ADDRESSED (0x0006)
+#define USB_HOST_DRV_GET_DEVICE_DESC_18 (0x0007)
+#define USB_HOST_DRV_GET_CONGIG_DESC_9 (0x0008)
+#define USB_HOST_DRV_GET_CONGIG_DESC (0x0009)
+#define USB_HOST_DRV_SET_CONFIG (0x000a)
+#define USB_HOST_DRV_CONFIGURED (0x000b)
+#define USB_HOST_DRV_SUSPEND (0x1000)
+#define USB_HOST_DRV_NORES (0x0100)
+#define USB_HOST_DRV_STALL (0x0200)
+
+#define USB_HOST_TESTMODE_FORCE (0x000du)
+#define USB_HOST_TESTMODE_TESTPACKET (0x000cu)
+#define USB_HOST_TESTMODE_SE0_NAK (0x000bu)
+#define USB_HOST_TESTMODE_K (0x000au)
+#define USB_HOST_TESTMODE_J (0x0009u)
+#define USB_HOST_TESTMODE_NORMAL (0x0000u)
+
+#define USB_HOST_DT_DEVICE (0x01)
+#define USB_HOST_DT_CONFIGURATION (0x02)
+#define USB_HOST_DT_STRING (0x03)
+#define USB_HOST_DT_INTERFACE (0x04)
+#define USB_HOST_DT_ENDPOINT (0x05)
+#define USB_HOST_DT_DEVICE_QUALIFIER (0x06)
+#define USB_HOST_DT_OTHER_SPEED_CONFIGURATION (0x07)
+#define USB_HOST_DT_INTERFACE_POWER (0x08)
+
+#define USB_HOST_IF_CLS_NOT (0x00)
+#define USB_HOST_IF_CLS_AUDIO (0x01)
+#define USB_HOST_IF_CLS_CDC_CTRL (0x02)
+#define USB_HOST_IF_CLS_HID (0x03)
+#define USB_HOST_IF_CLS_PHYSICAL (0x05)
+#define USB_HOST_IF_CLS_IMAGE (0x06)
+#define USB_HOST_IF_CLS_PRINTER (0x07)
+#define USB_HOST_IF_CLS_MASS (0x08)
+#define USB_HOST_IF_CLS_HUB (0x09)
+#define USB_HOST_IF_CLS_CDC_DATA (0x0a)
+#define USB_HOST_IF_CLS_CRAD (0x0b)
+#define USB_HOST_IF_CLS_CONTENT (0x0d)
+#define USB_HOST_IF_CLS_VIDEO (0x0e)
+#define USB_HOST_IF_CLS_DIAG (0xdc)
+#define USB_HOST_IF_CLS_WIRELESS (0xe0)
+#define USB_HOST_IF_CLS_APL (0xfe)
+#define USB_HOST_IF_CLS_VENDOR (0xff)
+#define USB_HOST_IF_CLS_HELE (0xaa)
+
+#define USB_HOST_EP_DIR_MASK (0x80)
+#define USB_HOST_EP_OUT (0x00)
+#define USB_HOST_EP_IN (0x80)
+#define USB_HOST_EP_TYPE (0x03)
+#define USB_HOST_EP_CNTRL (0x00)
+#define USB_HOST_EP_ISO (0x01)
+#define USB_HOST_EP_BULK (0x02)
+#define USB_HOST_EP_INT (0x03)
+#define USB_HOST_EP_NUM_MASK (0x0f)
+
+#define USB_HOST_PIPE_IN (0)
+#define USB_HOST_PIPE_OUT (1)
+
+#define USB_END_POINT_ERROR (0xffff)
+
+#define USB_HOST_REQ_GET_STATUS (0x0000)
+#define USB_HOST_REQ_CLEAR_FEATURE (0x0100)
+#define USB_HOST_REQ_RESERVED2 (0x0200)
+#define USB_HOST_REQ_SET_FEATURE (0x0300)
+#define USB_HOST_REQ_RESERVED4 (0x0400)
+#define USB_HOST_REQ_SET_ADDRESS (0x0500)
+#define USB_HOST_REQ_GET_DESCRIPTOR (0x0600)
+#define USB_HOST_REQ_SET_DESCRIPTOR (0x0700)
+#define USB_HOST_REQ_GET_CONFIGURATION (0x0800)
+#define USB_HOST_REQ_SET_CONFIGURATION (0x0900)
+#define USB_HOST_REQ_GET_INTERFACE (0x0a00)
+#define USB_HOST_REQ_SET_INTERFACE (0x0b00)
+#define USB_HOST_REQ_SYNCH_FRAME (0x0c00)
+
+#define USB_HOST_REQTYPE_HOST_TO_DEVICE (0x0000)
+#define USB_HOST_REQTYPE_DEVICE_TO_HOST (0x0080)
+#define USB_HOST_REQTYPE_STANDARD (0x0020)
+#define USB_HOST_REQTYPE_CLASS (0x0040)
+#define USB_HOST_REQTYPE_VENDOR (0x0060)
+#define USB_HOST_REQTYPE_DEVICE (0x0000)
+#define USB_HOST_REQTYPE_INTERFACE (0x0001)
+#define USB_HOST_REQTYPE_ENDPOINT (0x0002)
+#define USB_HOST_REQTYPE_OTHER (0x0003)
+
+#define USB_HOST_DESCTYPE_DEVICE (0x0100)
+#define USB_HOST_DESCTYPE_CONFIGURATION (0x0200)
+#define USB_HOST_DESCTYPE_STRING (0x0300)
+#define USB_HOST_DESCTYPE_INTERFACE (0x0400)
+#define USB_HOST_DESCTYPE_ENDPOINT (0x0500)
+#define USB_HOST_DESCTYPE_DEVICE_QUALIFIER (0x0600)
+#define USB_HOST_DESCTYPE_OTHER_SPEED_CONFIGURATION (0x0700)
+#define USB_HOST_DESCTYPE_INTERFACE_POWER (0x0800)
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+typedef struct
+{
+ uint16_t pipe_number;
+ uint16_t pipe_cfg;
+ uint16_t pipe_buf;
+ uint16_t pipe_max_pktsize;
+ uint16_t pipe_cycle;
+ uint16_t fifo_port;
+} USB_HOST_CFG_PIPETBL_t;
+
+typedef struct
+{
+ uint32_t fifo;
+ uint32_t buffer;
+ uint32_t bytes;
+ uint32_t dir;
+ uint32_t size;
+} USB_HOST_DMA_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+uint16_t R_USB_api_host_init(uint16_t root, uint8_t int_level, uint16_t mode, uint16_t clockmode);
+int32_t R_USB_api_host_enumeration(uint16_t root, uint16_t devadr);
+int32_t R_USB_api_host_detach(uint16_t root);
+int32_t R_USB_api_host_data_in(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t R_USB_api_host_data_in2(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf, uint32_t *bytes);
+int32_t R_USB_api_host_data_out(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t R_USB_api_host_control_transfer(uint16_t root, uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+int32_t R_USB_api_host_set_endpoint(uint16_t root, uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor);
+int32_t R_USB_api_host_clear_endpoint(uint16_t root, USB_HOST_CFG_PIPETBL_t *user_table);
+int32_t R_USB_api_host_clear_endpoint_pipe(uint16_t root, uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table);
+uint16_t R_USB_api_host_SetEndpointTable(uint16_t root, uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t* Table);
+
+int32_t R_USB_api_host_GetDeviceDescriptor(uint16_t root, uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t R_USB_api_host_GetConfigDescriptor(uint16_t root, uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t R_USB_api_host_SetConfig(uint16_t root, uint16_t devadr, uint16_t confignum);
+int32_t R_USB_api_host_SetInterface(uint16_t root, uint16_t devadr, uint16_t interface_alt, uint16_t interface_index);
+int32_t R_USB_api_host_ClearStall(uint16_t root, uint16_t devadr, uint16_t ep_dir);
+uint16_t R_USB_api_host_GetUsbDeviceState(uint16_t root);
+
+void R_USB_api_host_elt_clocksel(uint16_t clockmode);
+void R_USB_api_host_elt_4_4(uint16_t root);
+void R_USB_api_host_elt_4_5(uint16_t root);
+void R_USB_api_host_elt_4_6(uint16_t root);
+void R_USB_api_host_elt_4_7(uint16_t root);
+void R_USB_api_host_elt_4_8(uint16_t root);
+void R_USB_api_host_elt_4_9(uint16_t root);
+void R_USB_api_host_elt_get_desc(uint16_t root);
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host_api.h"
+#if(1) /* ohci_wrapp */
+#else
+#include "usb1_host_api.h"
+#endif
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+#ifdef USB0_HOST_API_H
+uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid(void);
+void Userdef_USB_usb0_host_attach(void);
+void Userdef_USB_usb0_host_detach(void);
+void Userdef_USB_usb0_host_delay_1ms(void);
+void Userdef_USB_usb0_host_delay_xms(uint32_t msec);
+void Userdef_USB_usb0_host_delay_10us(uint32_t usec);
+void Userdef_USB_usb0_host_delay_500ns(void);
+void Userdef_USB_usb0_host_start_dma(USB_HOST_DMA_t * dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb0_host_stop_dma0(void);
+uint32_t Userdef_USB_usb0_host_stop_dma1(void);
+void Userdef_USB_usb0_host_notice(const char * format);
+void Userdef_USB_usb0_host_user_rdy(const char * format, uint16_t data);
+#endif
+
+#ifdef USB1_HOST_API_H
+uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid(void);
+void Userdef_USB_usb1_host_attach(void);
+void Userdef_USB_usb1_host_detach(void);
+void Userdef_USB_usb1_host_delay_1ms(void);
+void Userdef_USB_usb1_host_delay_xms(uint32_t msec);
+void Userdef_USB_usb1_host_delay_10us(uint32_t usec);
+void Userdef_USB_usb1_host_delay_500ns(void);
+void Userdef_USB_usb1_host_start_dma(USB_HOST_DMA_t * dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb1_host_stop_dma0(void);
+uint32_t Userdef_USB_usb1_host_stop_dma1(void);
+void Userdef_USB_usb1_host_notice(const char * format);
+void Userdef_USB_usb1_host_user_rdy(const char * format, uint16_t data);
+#endif
+
+#endif /* USB_HOST_API_H */
+
+/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host.h Mon Jan 19 14:30:37 2015 +0000 @@ -0,0 +1,156 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB0_HOST_H +#define USB0_HOST_H + +/******************************************************************************* +Includes <System Includes> , "Project Includes" +*******************************************************************************/ +#include "devdrv_usb_host_api.h" +#include "usb_host.h" + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +extern const uint16_t g_usb0_host_bit_set[]; +extern uint32_t g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1]; +extern uint8_t *g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1]; + +extern uint16_t g_usb0_host_PipeIgnore[]; +extern uint16_t g_usb0_host_PipeTbl[]; +extern uint16_t g_usb0_host_pipe_status[]; +extern uint32_t g_usb0_host_PipeDataSize[]; + +extern USB_HOST_DMA_t g_usb0_host_DmaInfo[]; +extern uint16_t g_usb0_host_DmaPipe[]; +extern uint16_t g_usb0_host_DmaBval[]; +extern uint16_t g_usb0_host_DmaStatus[]; + +extern uint16_t g_usb0_host_driver_state; +extern uint16_t g_usb0_host_ConfigNum; +extern uint16_t g_usb0_host_CmdStage; +extern uint16_t g_usb0_host_bchg_flag; +extern uint16_t g_usb0_host_detach_flag; +extern uint16_t g_usb0_host_attach_flag; + +extern uint16_t g_usb0_host_UsbAddress; +extern uint16_t g_usb0_host_setUsbAddress; +extern uint16_t g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1]; +extern uint16_t g_usb0_host_UsbDeviceSpeed; +extern uint16_t g_usb0_host_SupportUsbDeviceSpeed; + +extern uint16_t g_usb0_host_SavReq; +extern uint16_t g_usb0_host_SavVal; +extern uint16_t g_usb0_host_SavIndx; +extern uint16_t g_usb0_host_SavLen; + +extern uint16_t g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1]; +extern uint16_t g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1]; +extern uint16_t g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1]; +extern uint16_t g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1]; + +/******************************************************************************* +Functions Prototypes +*******************************************************************************/ +/* ==== common ==== */ +void usb0_host_dma_stop_d0(uint16_t pipe, uint32_t remain); +void usb0_host_dma_stop_d1(uint16_t pipe, uint32_t remain); +uint16_t usb0_host_is_hispeed(void); +uint16_t usb0_host_is_hispeed_enable(void); +uint16_t usb0_host_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +uint16_t usb0_host_write_buffer(uint16_t pipe); +uint16_t usb0_host_write_buffer_c(uint16_t pipe); +uint16_t usb0_host_write_buffer_d0(uint16_t pipe); +uint16_t usb0_host_write_buffer_d1(uint16_t pipe); +void usb0_host_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data); +uint16_t usb0_host_read_buffer(uint16_t pipe); +uint16_t usb0_host_read_buffer_c(uint16_t pipe); +uint16_t usb0_host_read_buffer_d0(uint16_t pipe); +uint16_t usb0_host_read_buffer_d1(uint16_t pipe); +uint16_t usb0_host_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); +void usb0_host_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw); +void usb0_host_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc); +uint16_t usb0_host_get_mbw(uint32_t trncount, uint32_t dtptr); +uint16_t usb0_host_read_dma(uint16_t pipe); +void usb0_host_stop_transfer(uint16_t pipe); +void usb0_host_brdy_int(uint16_t status, uint16_t int_enb); +void usb0_host_nrdy_int(uint16_t status, uint16_t int_enb); +void usb0_host_bemp_int(uint16_t status, uint16_t int_enb); +void usb0_host_setting_interrupt(uint8_t level); +void usb0_host_reset_module(uint16_t clockmode); +uint16_t usb0_host_get_buf_size(uint16_t pipe); +uint16_t usb0_host_get_mxps(uint16_t pipe); +void usb0_host_enable_brdy_int(uint16_t pipe); +void usb0_host_disable_brdy_int(uint16_t pipe); +void usb0_host_clear_brdy_sts(uint16_t pipe); +void usb0_host_enable_bemp_int(uint16_t pipe); +void usb0_host_disable_bemp_int(uint16_t pipe); +void usb0_host_clear_bemp_sts(uint16_t pipe); +void usb0_host_enable_nrdy_int(uint16_t pipe); +void usb0_host_disable_nrdy_int(uint16_t pipe); +void usb0_host_clear_nrdy_sts(uint16_t pipe); +void usb0_host_set_pid_buf(uint16_t pipe); +void usb0_host_set_pid_nak(uint16_t pipe); +void usb0_host_set_pid_stall(uint16_t pipe); +void usb0_host_clear_pid_stall(uint16_t pipe); +uint16_t usb0_host_get_pid(uint16_t pipe); +void usb0_host_set_sqclr(uint16_t pipe); +void usb0_host_set_sqset(uint16_t pipe); +void usb0_host_set_csclr(uint16_t pipe); +void usb0_host_aclrm(uint16_t pipe); +void usb0_host_set_aclrm(uint16_t pipe); +void usb0_host_clr_aclrm(uint16_t pipe); +uint16_t usb0_host_get_sqmon(uint16_t pipe); +uint16_t usb0_host_get_inbuf(uint16_t pipe); + +/* ==== host ==== */ +void usb0_host_init_pipe_status(void); +int32_t usb0_host_CtrlTransStart(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf); +void usb0_host_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len); +void usb0_host_CtrlReadStart(uint32_t Bsize, uint8_t *Table); +uint16_t usb0_host_CtrlWriteStart(uint32_t Bsize, uint8_t *Table); +void usb0_host_StatusStage(void); +void usb0_host_get_devadd(uint16_t addr, uint16_t *devadd); +void usb0_host_set_devadd(uint16_t addr, uint16_t *devadd); +void usb0_host_InitModule(void); +uint16_t usb0_host_CheckAttach(void); +void usb0_host_UsbDetach(void); +void usb0_host_UsbDetach2(void); +void usb0_host_UsbAttach(void); +uint16_t usb0_host_UsbBusReset(void); +int32_t usb0_host_UsbResume(void); +int32_t usb0_host_UsbSuspend(void); +void usb0_host_Enable_DetachINT(void); +void usb0_host_Disable_DetachINT(void); +void usb0_host_UsbStateManager(void); + + +#endif /* USB0_HOST_H */ + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_api.h Mon Jan 19 14:30:37 2015 +0000 @@ -0,0 +1,112 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb0_host_api.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ +#ifndef USB0_HOST_API_H +#define USB0_HOST_API_H + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Variable Externs +*******************************************************************************/ + + +/******************************************************************************* +Functions Prototypes +*******************************************************************************/ +void usb0_host_interrupt(uint32_t int_sense); +void usb0_host_dma_interrupt_d0fifo(uint32_t int_sense); +void usb0_host_dma_interrupt_d1fifo(uint32_t int_sense); + +uint16_t usb0_api_host_init(uint8_t int_level, uint16_t mode, uint16_t clockmode); +int32_t usb0_api_host_enumeration(uint16_t devadr); +int32_t usb0_api_host_detach(void); +int32_t usb0_api_host_data_in(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf); +int32_t usb0_api_host_data_out(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf); +int32_t usb0_api_host_control_transfer(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf); +int32_t usb0_api_host_set_endpoint(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor); +int32_t usb0_api_host_clear_endpoint(USB_HOST_CFG_PIPETBL_t *user_table); +int32_t usb0_api_host_clear_endpoint_pipe(uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table); +uint16_t usb0_api_host_SetEndpointTable(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t* Table); +int32_t usb0_api_host_data_count(uint16_t pipe, uint32_t *data_count); + +int32_t usb0_api_host_GetDeviceDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf); +int32_t usb0_api_host_GetConfigDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf); +int32_t usb0_api_host_SetConfig(uint16_t devadr, uint16_t confignum); +int32_t usb0_api_host_SetInterface(uint16_t devadr, uint16_t interface_alt, uint16_t interface_index); +int32_t usb0_api_host_ClearStall(uint16_t devadr, uint16_t ep_dir); +uint16_t usb0_api_host_GetUsbDeviceState(void); + +void usb0_api_host_elt_4_4(void); +void usb0_api_host_elt_4_5(void); +void usb0_api_host_elt_4_6(void); +void usb0_api_host_elt_4_7(void); +void usb0_api_host_elt_4_8(void); +void usb0_api_host_elt_4_9(void); +void usb0_api_host_elt_get_desc(void); + +void usb0_host_EL_ModeInit(void); +void usb0_host_EL_SetUACT(void); +void usb0_host_EL_ClearUACT(void); +void usb0_host_EL_SetTESTMODE(uint16_t mode); +void usb0_host_EL_ClearNRDYSTS(uint16_t pipe); +uint16_t usb0_host_EL_GetINTSTS1(void); +void usb0_host_EL_UsbBusReset(void); +void usb0_host_EL_UsbAttach(void); +void usb0_host_EL_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len); +void usb0_host_EL_StatusStage(void); +void usb0_host_EL_CtrlReadStart(uint32_t Bsize, uint8_t *Table); +int32_t usb0_host_EL_UsbSuspend(void); +int32_t usb0_host_EL_UsbResume(void); + +#if 0 /* prototype in devdrv_usb_host_api.h */ +uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid(void); +uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid(void); +void Userdef_USB_usb0_host_attach(void); +void Userdef_USB_usb0_host_detach(void); +void Userdef_USB_usb0_host_delay_1ms(void); +void Userdef_USB_usb0_host_delay_xms(uint32_t msec); +void Userdef_USB_usb0_host_delay_10us(uint32_t usec); +void Userdef_USB_usb0_host_delay_500ns(void); +void Userdef_USB_usb0_host_start_dma(USB_HOST_DMA_t *dma, uint16_t dfacc); +uint32_t Userdef_USB_usb0_host_stop_dma0(void); +uint32_t Userdef_USB_usb0_host_stop_dma1(void); +#endif + +#endif /* USB0_HOST_API_H */ + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb0_host_dmacdrv.h Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,139 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_dmacdrv.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_HOST_DMACDRV_H
+#define USB0_HOST_DMACDRV_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef struct dmac_transinfo
+{
+ uint32_t src_addr; /* Transfer source address */
+ uint32_t dst_addr; /* Transfer destination address */
+ uint32_t count; /* Transfer byte count */
+ uint32_t src_size; /* Transfer source data size */
+ uint32_t dst_size; /* Transfer destination data size */
+ uint32_t saddr_dir; /* Transfer source address direction */
+ uint32_t daddr_dir; /* Transfer destination address direction */
+} dmac_transinfo_t;
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+/* ==== Transfer specification of the sample program ==== */
+#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */
+#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */
+
+/* ==== DMA modes ==== */
+#define DMAC_MODE_REGISTER (0) /* Register mode */
+#define DMAC_MODE_LINK (1) /* Link mode */
+
+/* ==== Transfer requests ==== */
+#define DMAC_REQ_MODE_EXT (0) /* External request */
+#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */
+#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */
+
+/* ==== DMAC transfer sizes ==== */
+#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */
+#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */
+#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */
+#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */
+#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */
+#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */
+#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */
+#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */
+
+/* ==== Address increment for transferring ==== */
+#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */
+#define DMAC_TRANS_ADR_INC (0) /* Increment */
+
+/* ==== Method for detecting DMA request ==== */
+#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */
+#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */
+#define DMAC_REQ_DET_LOW (2) /* Low level detection */
+#define DMAC_REQ_DET_HIGH (3) /* High level detection */
+
+/* ==== Request Direction ==== */
+#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */
+#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */
+
+/* ==== Descriptors ==== */
+#define DMAC_DESC_HEADER (0) /* Header */
+#define DMAC_DESC_SRC_ADDR (1) /* Source Address */
+#define DMAC_DESC_DST_ADDR (2) /* Destination Address */
+#define DMAC_DESC_COUNT (3) /* Transaction Byte */
+#define DMAC_DESC_CHCFG (4) /* Channel Confg */
+#define DMAC_DESC_CHITVL (5) /* Channel Interval */
+#define DMAC_DESC_CHEXT (6) /* Channel Extension */
+#define DMAC_DESC_LINK_ADDR (7) /* Link Address */
+
+/* ==== On-chip peripheral module requests ===== */
+typedef enum dmac_request_factor
+{
+ DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */
+ DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */
+ DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */
+ DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */
+} dmac_request_factor_t;
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void usb0_host_DMAC1_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb0_host_DMAC1_Open(uint32_t req);
+void usb0_host_DMAC1_Close(uint32_t * remain);
+void usb0_host_DMAC1_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+void usb0_host_DMAC2_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb0_host_DMAC2_Open(uint32_t req);
+void usb0_host_DMAC2_Close(uint32_t * remain);
+void usb0_host_DMAC2_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+#endif /* USB0_HOST_DMACDRV_H */
+
+/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host.h Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,201 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb_host.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB_HOST_H
+#define USB_HOST_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define USB_HOST_DEVICE_0 (0u)
+#define USB_HOST_DEVICE_1 (1u)
+#define USB_HOST_DEVICE_2 (2u)
+#define USB_HOST_DEVICE_3 (3u)
+#define USB_HOST_DEVICE_4 (4u)
+#define USB_HOST_DEVICE_5 (5u)
+#define USB_HOST_DEVICE_6 (6u)
+#define USB_HOST_DEVICE_7 (7u)
+#define USB_HOST_DEVICE_8 (8u)
+#define USB_HOST_DEVICE_9 (9u)
+#define USB_HOST_DEVICE_10 (10u)
+
+#define USB_HOST_ENDPOINT_DESC (0x05)
+
+#define USB_HOST_BITUPLLE (0x0002u)
+#define USB_HOST_BITUCKSEL (0x0004u)
+#define USB_HOST_BITBWAIT (0x003fu)
+
+#define USB_HOST_BUSWAIT_02 (0x0000u)
+#define USB_HOST_BUSWAIT_03 (0x0001u)
+#define USB_HOST_BUSWAIT_04 (0x0002u)
+#define USB_HOST_BUSWAIT_05 (0x0003u)
+#define USB_HOST_BUSWAIT_06 (0x0004u)
+#define USB_HOST_BUSWAIT_07 (0x0005u)
+#define USB_HOST_BUSWAIT_08 (0x0006u)
+#define USB_HOST_BUSWAIT_09 (0x0007u)
+#define USB_HOST_BUSWAIT_10 (0x0008u)
+#define USB_HOST_BUSWAIT_11 (0x0009u)
+#define USB_HOST_BUSWAIT_12 (0x000au)
+#define USB_HOST_BUSWAIT_13 (0x000bu)
+#define USB_HOST_BUSWAIT_14 (0x000cu)
+#define USB_HOST_BUSWAIT_15 (0x000du)
+#define USB_HOST_BUSWAIT_16 (0x000eu)
+#define USB_HOST_BUSWAIT_17 (0x000fu)
+
+#define USB_HOST_FS_JSTS (0x0001u)
+#define USB_HOST_LS_JSTS (0x0002u)
+
+#define USB_HOST_BITRST (0x0040u)
+#define USB_HOST_BITRESUME (0x0020u)
+#define USB_HOST_BITUACT (0x0010u)
+#define USB_HOST_HSPROC (0x0004u)
+#define USB_HOST_HSMODE (0x0003u)
+#define USB_HOST_FSMODE (0x0002u)
+#define USB_HOST_LSMODE (0x0001u)
+#define USB_HOST_UNDECID (0x0000u)
+
+#define USB_HOST_BITRCNT (0x8000u)
+#define USB_HOST_BITDREQE (0x1000u)
+#define USB_HOST_BITMBW (0x0c00u)
+#define USB_HOST_BITMBW_8 (0x0000u)
+#define USB_HOST_BITMBW_16 (0x0400u)
+#define USB_HOST_BITMBW_32 (0x0800u)
+#define USB_HOST_BITBYTE_LITTLE (0x0000u)
+#define USB_HOST_BITBYTE_BIG (0x0100u)
+#define USB_HOST_BITISEL (0x0020u)
+#define USB_HOST_BITCURPIPE (0x000fu)
+
+#define USB_HOST_CFIFO_READ (0x0000u)
+#define USB_HOST_CFIFO_WRITE (0x0020u)
+
+#define USB_HOST_BITBVAL (0x8000u)
+#define USB_HOST_BITBCLR (0x4000u)
+#define USB_HOST_BITFRDY (0x2000u)
+#define USB_HOST_BITDTLN (0x0fffu)
+
+#define USB_HOST_BITBEMPE (0x0400u)
+#define USB_HOST_BITNRDYE (0x0200u)
+#define USB_HOST_BITBRDYE (0x0100u)
+#define USB_HOST_BITBEMP (0x0400u)
+#define USB_HOST_BITNRDY (0x0200u)
+#define USB_HOST_BITBRDY (0x0100u)
+
+#define USB_HOST_BITBCHGE (0x4000u)
+#define USB_HOST_BITDTCHE (0x1000u)
+#define USB_HOST_BITATTCHE (0x0800u)
+#define USB_HOST_BITEOFERRE (0x0040u)
+#define USB_HOST_BITBCHG (0x4000u)
+#define USB_HOST_BITDTCH (0x1000u)
+#define USB_HOST_BITATTCH (0x0800u)
+#define USB_HOST_BITEOFERR (0x0040u)
+
+#define USB_HOST_BITSIGNE (0x0020u)
+#define USB_HOST_BITSACKE (0x0010u)
+#define USB_HOST_BITSIGN (0x0020u)
+#define USB_HOST_BITSACK (0x0010u)
+
+#define USB_HOST_BITSUREQ (0x4000u)
+#define USB_HOST_BITSQSET (0x0080u)
+#define USB_HOST_PID_STALL2 (0x0003u)
+#define USB_HOST_PID_STALL (0x0002u)
+#define USB_HOST_PID_BUF (0x0001u)
+#define USB_HOST_PID_NAK (0x0000u)
+
+#define USB_HOST_PIPExBUF (64u)
+
+#define USB_HOST_D0FIFO (0)
+#define USB_HOST_D1FIFO (1)
+#define USB_HOST_DMA_READY (0)
+#define USB_HOST_DMA_BUSY (1)
+#define USB_HOST_DMA_BUSYEND (2)
+
+#define USB_HOST_FIFO_USE (0x7000)
+
+#define USB_HOST_FIFOERROR (0xffff)
+#define USB_HOST_WRITEEND (0)
+#define USB_HOST_WRITESHRT (1)
+#define USB_HOST_WRITING (2)
+#define USB_HOST_WRITEDMA (3)
+#define USB_HOST_READEND (0)
+#define USB_HOST_READSHRT (1)
+#define USB_HOST_READING (2)
+#define USB_HOST_READOVER (3)
+#define USB_HOST_READZERO (4)
+
+#define USB_HOST_CMD_IDLE (0x0000)
+#define USB_HOST_CMD_DOING (0x0001)
+#define USB_HOST_CMD_DONE (0x0002)
+#define USB_HOST_CMD_NORES (0x0003)
+#define USB_HOST_CMD_STALL (0x0004)
+#define USB_HOST_CMD_FIELD (0x000f)
+
+#if 0
+#define USB_HOST_CHG_CMDFIELD( r, v ) do { r &= ( ~USB_HOST_CMD_FIELD ); \
+ r |= v; } while(0)
+#endif
+
+#define USB_HOST_MODE_WRITE (0x0100)
+#define USB_HOST_MODE_READ (0x0200)
+#define USB_HOST_MODE_NO_DATA (0x0300)
+#define USB_HOST_MODE_FIELD (0x0f00)
+
+#define USB_HOST_STAGE_SETUP (0x0010)
+#define USB_HOST_STAGE_DATA (0x0020)
+#define USB_HOST_STAGE_STATUS (0x0030)
+#define USB_HOST_STAGE_FIELD (0x00f0)
+
+#if 0
+#define USB_HOST_CHG_STAGEFIELD( r, v ) do { r &= ( ~USB_HOST_STAGE_FIELD ); \
+ r |= v; } while(0)
+#endif
+
+#define USB_HOST_DEVADD_MASK (0x7fc0)
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern uint16_t g_usb_host_elt_clockmode;
+
+#endif /* USB_HOST_H */
+
+/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host_version.h Mon Jan 19 14:30:37 2015 +0000 @@ -0,0 +1,32 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb_host_version.h +* $Rev: 1116 $ +* $Date:: 2014-07-09 16:29:19 +0900#$ +* Description : RZ/A1H R7S72100 USB Sample Program +*******************************************************************************/ + +#define USB_HOST_LOCAL_Rev "VER080_140709" + +/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,1051 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include <string.h>
+#include "cmsis.h"
+#include "cmsis_os.h"
+#include "ohci_wrapp_RZ_A1.h"
+#include "ohci_wrapp_RZ_A1_local.h"
+
+#include "rza_io_regrw.h"
+#include "usb0_host.h"
+
+/* ------------------ HcControl Register --------------------- */
+#define OR_CONTROL_PLE (0x00000004)
+#define OR_CONTROL_CLE (0x00000010)
+#define OR_CONTROL_BLE (0x00000020)
+/* ----------------- HcCommandStatus Register ----------------- */
+#define OR_CMD_STATUS_HCR (0x00000001)
+#define OR_CMD_STATUS_CLF (0x00000002)
+#define OR_CMD_STATUS_BLF (0x00000004)
+#define OR_CMD_STATUS_OCR (0x00000008)
+/* --------------- HcInterruptStatus Register ----------------- */
+#define OR_INTR_STATUS_WDH (0x00000002)
+#define OR_INTR_STATUS_RHSC (0x00000040)
+/* --------------- HcInterruptEnable Register ----------------- */
+#define OR_INTR_ENABLE_WDH (0x00000002)
+#define OR_INTR_ENABLE_RHSC (0x00000040)
+/* -------------- HcRhPortStatus[1:NDP] Register -------------- */
+#define OR_RH_PORT_CSC (0x00010000)
+#define OR_RH_PORT_LSDA (0x00000200)
+#define OR_RH_PORT_PRS (0x00000010)
+#define OR_RH_PORT_POCI (0x00000008)
+#define OR_RH_PORT_CCS (0x00000001)
+
+#define ED_SKIP (0x00004000) /* Skip this ep in queue */
+#define ED_TOGLE_CARRY (0x00000002)
+#define ED_HALTED (0x00000001)
+
+#define TD_SETUP (0x00000000) /* Direction of Setup Packet */
+#define TD_OUT (0x00080000) /* Direction Out */
+#define TD_TOGGLE_0 (0x02000000) /* Toggle 0 */
+#define TD_TOGGLE_1 (0x03000000) /* Toggle 1 */
+
+/* -------------- USB Standard Requests -------------- */
+#define GET_STATUS (0x00)
+#define SET_FEATURE (0x03)
+#define SET_ADDRESS (0x05)
+
+#define TD_CTL_MSK_DP (0x00180000)
+#define TD_CTL_MSK_T (0x03000000)
+#define TD_CTL_MSK_CC (0xF0000000)
+#define TD_CTL_MSK_EC (0x0C000000)
+#define TD_CTL_SHFT_CC (28)
+#define TD_CTL_SHFT_EC (26)
+#define TD_CTL_SHFT_T (24)
+#define ED_SHFT_TOGLE_CARRY (1)
+#define SIG_GEN_LIST_REQ (1)
+
+#define CTL_TRANS_TIMEOUT (1000)
+#define BLK_TRANS_TIMEOUT (5)
+#define INT_TRANS_MAX_NUM (4) /* min:1 max:4 */
+#define TOTAL_SEM_NUM (5 + (2 * INT_TRANS_MAX_NUM))
+
+#define PORT_LOW_SPEED (0x00000200)
+#define PORT_HIGH_SPEED (0x00000400)
+#define PORT_NUM (16 + 1) /* num + root(1) */
+
+typedef struct tag_hctd {
+ uint32_t control; /* Transfer descriptor control */
+ uint8_t *currBufPtr; /* Physical address of current buffer pointer */
+ struct tag_hctd *nextTD; /* Physical pointer to next Transfer Descriptor */
+ uint8_t *bufEnd; /* Physical address of end of buffer */
+} hctd_t;
+
+typedef struct tag_hced {
+ uint32_t control; /* Endpoint descriptor control */
+ hctd_t *tailTD; /* Physical address of tail in Transfer descriptor list */
+ hctd_t *headTD; /* Physcial address of head in Transfer descriptor list */
+ struct tag_hced *nextED; /* Physical address of next Endpoint descriptor */
+} hced_t;
+
+typedef struct tag_hcca {
+ uint32_t IntTable[32]; /* Interrupt Table */
+ uint32_t FrameNumber; /* Frame Number */
+ uint32_t DoneHead; /* Done Head */
+ volatile uint8_t Reserved[116]; /* Reserved for future use */
+ volatile uint8_t Unknown[4]; /* Unused */
+} hcca_t;
+
+typedef struct tag_usb_ohci_reg {
+ volatile uint32_t HcRevision;
+ volatile uint32_t HcControl;
+ volatile uint32_t HcCommandStatus;
+ volatile uint32_t HcInterruptStatus;
+ volatile uint32_t HcInterruptEnable;
+ volatile uint32_t HcInterruptDisable;
+ volatile uint32_t HcHCCA;
+ volatile uint32_t HcPeriodCurrentED;
+ volatile uint32_t HcControlHeadED;
+ volatile uint32_t HcControlCurrentED;
+ volatile uint32_t HcBulkHeadED;
+ volatile uint32_t HcBulkCurrentED;
+ volatile uint32_t HcDoneHead;
+ volatile uint32_t HcFmInterval;
+ volatile uint32_t HcFmRemaining;
+ volatile uint32_t HcFmNumber;
+ volatile uint32_t HcPeriodicStart;
+ volatile uint32_t HcLSThreshold;
+ volatile uint32_t HcRhDescriptorA;
+ volatile uint32_t HcRhDescriptorB;
+ volatile uint32_t HcRhStatus;
+ volatile uint32_t HcRhPortStatus1;
+} usb_ohci_reg_t;
+
+typedef struct tag_genelal_ed {
+ osThreadId tskid;
+ osSemaphoreId semid_wait;
+ osSemaphoreId semid_list;
+ hctd_t *p_curr_td;
+ hced_t *p_curr_ed;
+ uint32_t pipe_no;
+ uint32_t trans_wait;
+ uint32_t cycle_time;
+ uint8_t *p_start_buf;
+} genelal_ed_t;
+
+typedef struct tag_tdinfo {
+ uint32_t count;
+ uint32_t direction;
+ uint32_t msp;
+ uint16_t devadr;
+ uint16_t speed; /* 1:Speed = Low */
+ uint8_t endpoint_no;
+} tdinfo_t;
+
+typedef struct tag_split_trans {
+ uint16_t root_devadr;
+ uint16_t get_port;
+ uint16_t port_speed;
+ uint16_t reset_port;
+ uint32_t seq_cnt;
+ uint32_t port_sts_bits[PORT_NUM];
+} split_trans_t;
+
+static void callback_task(void const * argument);
+static void control_ed_task(void const * argument);
+static void bulk_ed_task(void const * argument);
+static void int_ed_task(void const * argument);
+static int32_t int_trans_doing(hced_t *p_ed, uint32_t index);
+static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed);
+static void chk_td_done(genelal_ed_t *p_g_ed);
+static void chk_split_trans_setting(genelal_ed_t *p_g_ed);
+static void set_split_trans_setting(void);
+static void control_trans(genelal_ed_t *p_g_ed);
+static void bulk_trans(genelal_ed_t *p_g_ed);
+static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index);
+static uint32_t chk_cycle(hced_t *p_ed);
+static void int_trans(genelal_ed_t *p_g_ed);
+static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info);
+static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed);
+static void connect_check(void);
+
+extern USB_HOST_CFG_PIPETBL_t usb0_host_blk_ep_tbl1[];
+extern USB_HOST_CFG_PIPETBL_t usb0_host_int_ep_tbl1[];
+
+static usb_ohci_reg_t usb_reg;
+static usb_ohci_reg_t *p_usb_reg = &usb_reg;
+static usbisr_fnc_t *p_usbisr_cb = NULL;
+static osSemaphoreId semid_cb = NULL;
+static uint32_t connect_change = 0xFFFFFFFF;
+static uint32_t init_end = 0;
+static genelal_ed_t ctl_ed;
+static genelal_ed_t blk_ed;
+static genelal_ed_t int_ed[INT_TRANS_MAX_NUM];
+static split_trans_t split_ctl;
+
+osSemaphoreDef(ohciwrapp_sem_01);
+osSemaphoreDef(ohciwrapp_sem_02);
+osSemaphoreDef(ohciwrapp_sem_03);
+osSemaphoreDef(ohciwrapp_sem_04);
+osSemaphoreDef(ohciwrapp_sem_05);
+osSemaphoreDef(ohciwrapp_sem_06);
+osSemaphoreDef(ohciwrapp_sem_07);
+#if (INT_TRANS_MAX_NUM >= 2)
+osSemaphoreDef(ohciwrapp_sem_08);
+osSemaphoreDef(ohciwrapp_sem_09);
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+osSemaphoreDef(ohciwrapp_sem_10);
+osSemaphoreDef(ohciwrapp_sem_11);
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+osSemaphoreDef(ohciwrapp_sem_12);
+osSemaphoreDef(ohciwrapp_sem_13);
+#endif
+
+osThreadDef(callback_task, osPriorityHigh, 512);
+osThreadDef(control_ed_task, osPriorityNormal, 512);
+osThreadDef(bulk_ed_task, osPriorityNormal, 512);
+osThreadDef(int_ed_task, osPriorityAboveNormal, 512);
+
+void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc, uint32_t hi_speed) {
+ static const osSemaphoreDef_t * const sem_def_tbl[TOTAL_SEM_NUM] = {
+ osSemaphore(ohciwrapp_sem_01), osSemaphore(ohciwrapp_sem_02), osSemaphore(ohciwrapp_sem_03)
+ , osSemaphore(ohciwrapp_sem_04), osSemaphore(ohciwrapp_sem_05), osSemaphore(ohciwrapp_sem_06)
+ , osSemaphore(ohciwrapp_sem_07)
+#if (INT_TRANS_MAX_NUM >= 2)
+ , osSemaphore(ohciwrapp_sem_08), osSemaphore(ohciwrapp_sem_09)
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+ , osSemaphore(ohciwrapp_sem_10), osSemaphore(ohciwrapp_sem_11)
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+ , osSemaphore(ohciwrapp_sem_12), osSemaphore(ohciwrapp_sem_13)
+#endif
+ };
+ uint32_t cnt;
+ uint32_t index = 0;
+
+ /* Disables interrupt for usb */
+ GIC_DisableIRQ(USBI0_IRQn);
+
+ /* P4_1(USB0_EN) */
+ GPIOP4 &= ~0x0002; /* Outputs low level */
+ GPIOPMC4 &= ~0x0002; /* Port mode */
+ GPIOPM4 &= ~0x0002; /* Output mode */
+
+ p_usbisr_cb = p_usbisr_fnc;
+ if (hi_speed == 0) {
+ g_usb0_host_SupportUsbDeviceSpeed = USB_HOST_FULL_SPEED;
+ } else {
+ g_usb0_host_SupportUsbDeviceSpeed = USB_HOST_HIGH_SPEED;
+ }
+ p_usb_reg->HcRevision = 0x00000010;
+ p_usb_reg->HcControl = 0x00000000;
+ p_usb_reg->HcCommandStatus = 0x00000000;
+ p_usb_reg->HcInterruptStatus = 0x00000000;
+ p_usb_reg->HcInterruptEnable = 0x00000000;
+ p_usb_reg->HcInterruptDisable = 0x00000000;
+ p_usb_reg->HcHCCA = 0x00000000;
+ p_usb_reg->HcPeriodCurrentED = 0x00000000;
+ p_usb_reg->HcControlHeadED = 0x00000000;
+ p_usb_reg->HcControlCurrentED = 0x00000000;
+ p_usb_reg->HcBulkHeadED = 0x00000000;
+ p_usb_reg->HcBulkCurrentED = 0x00000000;
+ p_usb_reg->HcDoneHead = 0x00000000;
+ p_usb_reg->HcFmInterval = 0x00002EDF;
+ p_usb_reg->HcFmRemaining = 0x00002EDF;
+ p_usb_reg->HcFmNumber = 0x00000000;
+ p_usb_reg->HcPeriodicStart = 0x00000000;
+ p_usb_reg->HcLSThreshold = 0x00000628;
+ p_usb_reg->HcRhDescriptorA = 0xFF000901;
+ p_usb_reg->HcRhDescriptorB = 0x00020000;
+ p_usb_reg->HcRhStatus = 0x00000000;
+ p_usb_reg->HcRhPortStatus1 = 0x00000000;
+
+ GPIOP4 |= 0x0002; /* P4_1 Outputs high level */
+ osDelay(5);
+ GPIOP4 &= ~0x0002; /* P4_1 Outputs low level */
+ osDelay(10);
+
+ if (init_end == 0) {
+ (void)memset(&ctl_ed, 0, sizeof(ctl_ed));
+ (void)memset(&blk_ed, 0, sizeof(blk_ed));
+ (void)memset(&int_ed[0], 0, sizeof(int_ed));
+
+ /* callback */
+ semid_cb = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ (void)osThreadCreate(osThread(callback_task), 0);
+
+ /* control transfer */
+ ctl_ed.semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ ctl_ed.semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ ctl_ed.tskid = osThreadCreate(osThread(control_ed_task), 0);
+
+ /* bulk transfer */
+ blk_ed.semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ blk_ed.semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ blk_ed.tskid = osThreadCreate(osThread(bulk_ed_task), 0);
+
+ /* interrupt transfer */
+ for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
+ int_ed[cnt].semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ int_ed[cnt].semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ int_ed[cnt].tskid = osThreadCreate(osThread(int_ed_task), (void *)cnt);
+ }
+ init_end = 1;
+ }
+}
+
+uint32_t ohciwrapp_reg_r(uint32_t reg_ofs) {
+ if (init_end == 0) {
+ return 0;
+ }
+
+ return *(uint32_t *)((uint8_t *)p_usb_reg + reg_ofs);
+}
+
+void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data) {
+ uint32_t cnt;
+ uint32_t last_data;
+ hcca_t *p_hcca;
+
+ if (init_end == 0) {
+ return;
+ }
+
+ switch (reg_ofs) {
+ case OHCI_REG_CONTROL:
+ last_data = p_usb_reg->HcControl;
+ p_usb_reg->HcControl = (set_data & 0x000007FF);
+ if ((last_data & OR_CONTROL_CLE) != (set_data & OR_CONTROL_CLE)) {
+ /* change CLE */
+ if ((set_data & OR_CONTROL_CLE) != 0) {
+ (void)osSemaphoreRelease(ctl_ed.semid_list);
+ } else {
+ if (ctl_ed.trans_wait == 1) {
+ ctl_ed.trans_wait = 0;
+ (void)osSemaphoreRelease(ctl_ed.semid_wait);
+ }
+ (void)osSemaphoreWait(ctl_ed.semid_list, osWaitForever);
+ }
+ }
+ if ((last_data & OR_CONTROL_BLE) != (set_data & OR_CONTROL_BLE)) {
+ /* change BLE */
+ if ((set_data & OR_CONTROL_BLE) != 0) {
+ (void)osSemaphoreRelease(blk_ed.semid_list);
+ } else {
+ if (blk_ed.trans_wait == 1) {
+ blk_ed.trans_wait = 0;
+ (void)osSemaphoreRelease(blk_ed.semid_wait);
+ }
+ (void)osSemaphoreWait(blk_ed.semid_list, osWaitForever);
+ }
+ }
+ if ((last_data & OR_CONTROL_PLE) != (set_data & OR_CONTROL_PLE)) {
+ /* change PLE */
+ for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
+ if ((set_data & OR_CONTROL_PLE) != 0) {
+ (void)osSemaphoreRelease(int_ed[cnt].semid_list);
+ } else {
+ if (int_ed[cnt].trans_wait == 1) {
+ int_ed[cnt].trans_wait = 0;
+ (void)osSemaphoreRelease(int_ed[cnt].semid_wait);
+ }
+ (void)osSemaphoreWait(int_ed[cnt].semid_list, osWaitForever);
+ }
+ }
+ }
+ break;
+ case OHCI_REG_COMMANDSTATUS:
+ if ((set_data & OR_CMD_STATUS_HCR) != 0) { /* HostController Reset */
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_HCR;
+ if (usb0_api_host_init(16, g_usb0_host_SupportUsbDeviceSpeed, USBHCLOCK_X1_48MHZ) == USB_HOST_ATTACH) {
+ ohciwrapp_loc_Connect(1);
+ }
+ p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_HCR;
+ }
+ if ((set_data & OR_CMD_STATUS_CLF) != 0) {
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_CLF;
+ osSignalSet(ctl_ed.tskid, SIG_GEN_LIST_REQ);
+ }
+ if ((set_data & OR_CMD_STATUS_BLF) != 0) {
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_BLF;
+ osSignalSet(blk_ed.tskid, SIG_GEN_LIST_REQ);
+ }
+ if ((set_data & OR_CMD_STATUS_OCR) != 0) {
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_OCR;
+ } else {
+ p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_OCR;
+ }
+ break;
+ case OHCI_REG_INTERRUPTSTATUS:
+ if (((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) != 0)
+ && ((set_data & OR_INTR_STATUS_WDH) != 0)) {
+ if (p_usb_reg->HcDoneHead != 0x00000000) {
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+ p_hcca->DoneHead = p_usb_reg->HcDoneHead;
+ p_usb_reg->HcDoneHead = 0x00000000;
+ p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
+ (void)osSemaphoreRelease(semid_cb);
+ } else {
+ p_usb_reg->HcInterruptStatus &= ~OR_INTR_STATUS_WDH;
+ }
+ }
+ if ((set_data & OR_INTR_STATUS_RHSC) != 0) {
+ p_usb_reg->HcInterruptStatus &= ~OR_INTR_STATUS_RHSC;
+ }
+ break;
+ case OHCI_REG_INTERRUPTENABLE:
+ case OHCI_REG_INTERRUPTDISABLE:
+ case OHCI_REG_HCCA:
+ case OHCI_REG_CONTROLHEADED:
+ case OHCI_REG_CONTROLCURRENTED:
+ case OHCI_REG_BULKHEADED:
+ case OHCI_REG_BULKCURRENTED:
+ case OHCI_REG_FMINTERVAL:
+ case OHCI_REG_FMREMAINING:
+ case OHCI_REG_PERIODICSTART:
+ case OHCI_REG_LSTHRESHOLD:
+ case OHCI_REG_RHDESCRIPTORA:
+ case OHCI_REG_RHDESCRIPTORB:
+ case OHCI_REG_RHSTATUS:
+ *(uint32_t *)((uint8_t *)p_usb_reg + reg_ofs) = set_data;
+ break;
+ case OHCI_REG_RHPORTSTATUS1:
+ p_usb_reg->HcRhPortStatus1 &= ~(set_data & 0xFFFF0000);
+ if ((set_data & OR_RH_PORT_PRS) != 0) { /* Set Port Reset */
+ p_usb_reg->HcRhPortStatus1 |= OR_RH_PORT_PRS;
+ usb0_host_UsbBusReset();
+ p_usb_reg->HcRhPortStatus1 &= ~OR_RH_PORT_PRS;
+ }
+ break;
+ case OHCI_REG_REVISION:
+ case OHCI_REG_PERIODCURRENTED:
+ case OHCI_REG_DONEHEADED:
+ case OHCI_REG_FMNUMBER:
+ default:
+ /* Do Nothing */
+ break;
+ }
+}
+
+static void callback_task(void const * argument) {
+ usbisr_fnc_t *p_wk_cb = p_usbisr_cb;
+
+ if (p_wk_cb == NULL) {
+ return;
+ }
+
+ while (1) {
+ osSemaphoreWait(semid_cb, osWaitForever);
+ if (connect_change != 0xFFFFFFFF) {
+ connect_change = 0xFFFFFFFF;
+ connect_check();
+ }
+ p_wk_cb();
+ }
+}
+
+static void control_ed_task(void const * argument) {
+ while (1) {
+ osSignalWait(SIG_GEN_LIST_REQ, osWaitForever);
+ (void)osSemaphoreWait(ctl_ed.semid_list, osWaitForever);
+ while ((p_usb_reg->HcControl & OR_CONTROL_CLE) != 0) {
+ if ((p_usb_reg->HcControlCurrentED == 0)
+ && ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_CLF) != 0)) {
+ p_usb_reg->HcControlCurrentED = p_usb_reg->HcControlHeadED;
+ p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_CLF;
+ }
+ if (p_usb_reg->HcControlCurrentED != 0) {
+ ctl_ed.p_curr_ed = (hced_t *)p_usb_reg->HcControlCurrentED;
+ if (chk_genelal_ed(&ctl_ed) != 0) {
+ control_trans(&ctl_ed);
+ chk_split_trans_setting(&ctl_ed);
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_CLF;
+ chk_td_done(&ctl_ed);
+ }
+ p_usb_reg->HcControlCurrentED = (uint32_t)ctl_ed.p_curr_ed->nextED;
+ } else {
+ break;
+ }
+ }
+ if ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_CLF) != 0) {
+ osSignalSet(ctl_ed.tskid, SIG_GEN_LIST_REQ);
+ }
+ (void)osSemaphoreRelease(ctl_ed.semid_list);
+ }
+}
+
+static void bulk_ed_task(void const * argument) {
+ while (1) {
+ osSignalWait(SIG_GEN_LIST_REQ, osWaitForever);
+ (void)osSemaphoreWait(blk_ed.semid_list, osWaitForever);
+ while ((p_usb_reg->HcControl & OR_CONTROL_BLE) != 0) {
+ if ((p_usb_reg->HcBulkCurrentED == 0)
+ && ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_BLF) != 0)) {
+ p_usb_reg->HcBulkCurrentED = p_usb_reg->HcBulkHeadED;
+ p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_BLF;
+ }
+ if (p_usb_reg->HcBulkCurrentED != 0) {
+ blk_ed.p_curr_ed = (hced_t *)p_usb_reg->HcBulkCurrentED;
+ if (chk_genelal_ed(&blk_ed) != 0) {
+ bulk_trans(&blk_ed);
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_BLF;
+ chk_td_done(&blk_ed);
+ }
+ p_usb_reg->HcBulkCurrentED = (uint32_t)blk_ed.p_curr_ed->nextED;
+ } else {
+ break;
+ }
+ }
+ if ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_BLF) != 0) {
+ osSignalSet(blk_ed.tskid, SIG_GEN_LIST_REQ);
+ }
+ (void)osSemaphoreRelease(blk_ed.semid_list);
+ }
+}
+
+static void int_ed_task(void const * argument) {
+ genelal_ed_t *p_int_ed = &int_ed[(uint32_t)argument];
+ uint32_t cnt;
+ uint32_t wait_cnt = 0;
+ hcca_t *p_hcca;
+ hced_t *p_ed;
+
+ while (1) {
+ (void)osSemaphoreWait(p_int_ed->semid_list, osWaitForever);
+ if (p_int_ed->p_curr_ed == NULL) {
+ for (cnt = 0; (cnt < 32) && ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0)
+ && (p_int_ed->p_curr_ed == NULL); cnt++) {
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+ p_ed = (hced_t *)p_hcca->IntTable[cnt];
+ while ((p_ed != NULL) && ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0)
+ && (p_int_ed->p_curr_ed == NULL)) {
+ if (int_trans_doing(p_ed, (uint32_t)argument) == 0) {
+ p_int_ed->p_curr_ed = p_ed;
+ if (chk_genelal_ed(p_int_ed) != 0) {
+ int_trans_setting(p_int_ed, (uint32_t)argument);
+ } else {
+ p_int_ed->p_curr_ed = NULL;
+ }
+ }
+ p_ed = p_ed->nextED;
+ }
+ }
+ }
+ if (p_int_ed->p_curr_ed != NULL) {
+ while ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0) {
+ if (chk_genelal_ed(p_int_ed) != 0) {
+ int_trans(p_int_ed);
+ chk_td_done(p_int_ed);
+ wait_cnt = p_int_ed->cycle_time;
+ } else {
+ if (wait_cnt > 0) {
+ wait_cnt--;
+ } else {
+ p_int_ed->p_curr_ed = NULL;
+ }
+ break;
+ }
+ }
+ }
+ (void)osSemaphoreRelease(p_int_ed->semid_list);
+ if (p_int_ed->p_curr_ed == NULL) {
+ osDelay(10);
+ } else {
+ osDelay(1);
+ }
+ }
+}
+
+static int32_t int_trans_doing(hced_t *p_ed, uint32_t index) {
+ uint32_t cnt;
+ int32_t ret = 0;
+
+ for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
+ if ((index != cnt) && (int_ed[cnt].p_curr_ed == p_ed)) {
+ ret = 1;
+ }
+ }
+
+ return ret;
+}
+
+static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed){
+ int32_t ret = 0;
+ hced_t *p_ed = p_g_ed->p_curr_ed;
+
+ if (((p_ed->control & ED_SKIP) != 0)
+ || (((uint32_t)p_ed->headTD & ED_HALTED) != 0)
+ || (((uint32_t)p_ed->tailTD & 0xFFFFFFF0) == ((uint32_t)p_ed->headTD & 0xFFFFFFF0))) {
+ /* Do Nothing */
+ } else if ((p_ed->control & 0x0000007F) > 10) {
+ p_ed->headTD = (hctd_t *)((uint32_t)p_ed->headTD | ED_HALTED);
+ } else {
+ p_g_ed->p_curr_td = (hctd_t *)((uint32_t)p_ed->headTD & 0xFFFFFFF0);
+ if (p_g_ed->p_curr_td == NULL) {
+ p_ed->headTD = (hctd_t *)((uint32_t)p_ed->headTD | ED_HALTED);
+ } else {
+ p_g_ed->p_start_buf = p_g_ed->p_curr_td->currBufPtr;
+ ret = 1;
+ }
+ }
+
+ return ret;
+}
+
+static void chk_td_done(genelal_ed_t *p_g_ed) {
+ hcca_t *p_hcca;
+ uint32_t ConditionCode = RZA_IO_RegRead_32(&p_g_ed->p_curr_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+
+ if ((ConditionCode != TD_CC_NOT_ACCESSED_1) && (ConditionCode != TD_CC_NOT_ACCESSED_2)) {
+ p_g_ed->p_curr_ed->headTD = (hctd_t *)(((uint32_t)p_g_ed->p_curr_td->nextTD & 0xFFFFFFF0)
+ | ((uint32_t)p_g_ed->p_curr_ed->headTD & 0x0000000F));
+ p_g_ed->p_curr_td->nextTD = (hctd_t *)p_usb_reg->HcDoneHead;
+ p_usb_reg->HcDoneHead = (uint32_t)p_g_ed->p_curr_td;
+ if ((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) == 0) {
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+ p_hcca->DoneHead = p_usb_reg->HcDoneHead;
+ p_usb_reg->HcDoneHead = 0x00000000;
+ p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
+ (void)osSemaphoreRelease(semid_cb);
+ }
+ }
+}
+
+static void chk_split_trans_setting(genelal_ed_t *p_g_ed) {
+ uint8_t *p_buf;
+ tdinfo_t td_info;
+
+ /* Hi-Speed mode only */
+ if (g_usb0_host_UsbDeviceSpeed != USB_HOST_HIGH_SPEED) {
+ return;
+ }
+
+ if (RZA_IO_RegRead_32(&p_g_ed->p_curr_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC) != TD_CC_NOERROR) {
+ return;
+ }
+
+ get_td_info(p_g_ed, &td_info);
+ p_buf = p_g_ed->p_start_buf;
+
+ if (td_info.direction == 0) {
+ uint8_t bRequest = p_buf[1];
+ uint16_t wValue = (p_buf[3] << 8) + p_buf[2];
+ uint16_t wIndx = (p_buf[5] << 8) + p_buf[4];
+ uint16_t devadd;
+
+ if ((td_info.devadr == 0) && (bRequest == SET_ADDRESS)) {
+ /* SET_ADDRESS */
+ usb0_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
+ usb0_host_set_devadd(wValue, &devadd);
+ if (split_ctl.root_devadr == 0) {
+ split_ctl.root_devadr = wValue; /* New Address */
+ }
+ } else if ((td_info.devadr == split_ctl.root_devadr) && (bRequest == SET_FEATURE)
+ && (wValue == 0x0004) && (split_ctl.root_devadr != 0)) {
+ /* SET_FEATURE PORT_RESET */
+ split_ctl.reset_port = (wIndx & 0x00FF);
+ } else if ((td_info.devadr == split_ctl.root_devadr) && (bRequest == GET_STATUS)) {
+ /* GET_STATUS */
+ split_ctl.get_port = wIndx;
+ split_ctl.seq_cnt = 1;
+ } else {
+ /* Do Nothing */
+ }
+ } else if (td_info.direction == 2) {
+ if ((td_info.devadr == split_ctl.root_devadr) && (split_ctl.seq_cnt == 1)) {
+ if (split_ctl.get_port < PORT_NUM) {
+ split_ctl.port_sts_bits[split_ctl.get_port] = (p_buf[1] << 8) + p_buf[0];
+ }
+ split_ctl.seq_cnt = 0;
+ }
+ } else {
+ /* Do Nothing */
+ }
+}
+
+static void set_split_trans_setting(void) {
+ uint16_t port_speed;
+ uint16_t devadd;
+
+ if ((split_ctl.root_devadr != 0) && (split_ctl.reset_port != 0) && (split_ctl.reset_port < PORT_NUM)) {
+ usb0_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
+ RZA_IO_RegWrite_16(&devadd, split_ctl.root_devadr, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB);
+ RZA_IO_RegWrite_16(&devadd, split_ctl.reset_port, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT);
+ if ((split_ctl.port_sts_bits[split_ctl.reset_port] & PORT_HIGH_SPEED) != 0) {
+ port_speed = USB_HOST_HIGH_SPEED;
+ } else if ((split_ctl.port_sts_bits[split_ctl.reset_port] & PORT_LOW_SPEED) != 0) {
+ port_speed = USB_HOST_LOW_SPEED;
+ } else {
+ port_speed = USB_HOST_FULL_SPEED;
+ }
+ RZA_IO_RegWrite_16(&devadd, port_speed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+ usb0_host_set_devadd(USB_HOST_DEVICE_0, &devadd);
+ split_ctl.reset_port = 0;
+ }
+}
+
+static void control_trans(genelal_ed_t *p_g_ed) {
+ hctd_t *p_td = p_g_ed->p_curr_td;
+ tdinfo_t td_info;
+ uint16_t devadd;
+
+ get_td_info(p_g_ed, &td_info);
+
+ if (g_usb0_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
+ if (td_info.devadr == 0) {
+ set_split_trans_setting();
+ }
+ } else {
+ /* When a non-Hi-Speed, the communication speed is determined from the TD. */
+ usb0_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
+ if (td_info.speed == 1) {
+ RZA_IO_RegWrite_16(&devadd, USB_HOST_LOW_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+ } else {
+ RZA_IO_RegWrite_16(&devadd, USB_HOST_FULL_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+ }
+ usb0_host_set_devadd(td_info.devadr, &devadd);
+ }
+
+ USB200.DCPMAXP = (td_info.devadr << 12) + td_info.msp;
+ if (td_info.direction == 0) {
+ g_usb0_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
+ } else if (td_info.count != 0) {
+ g_usb0_host_CmdStage = (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE);
+ } else {
+ g_usb0_host_CmdStage = (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE);
+ }
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT;
+ p_g_ed->pipe_no = USB_HOST_PIPE0;
+
+ p_g_ed->trans_wait = 1;
+
+ if (td_info.direction == 0) {
+ uint16_t Req = (p_td->currBufPtr[1] << 8) + p_td->currBufPtr[0];
+ uint16_t Val = (p_td->currBufPtr[3] << 8) + p_td->currBufPtr[2];
+ uint16_t Indx = (p_td->currBufPtr[5] << 8) + p_td->currBufPtr[4];
+ uint16_t Len = (p_td->currBufPtr[7] << 8) + p_td->currBufPtr[6];
+
+ g_usb0_host_data_pointer[USB_HOST_PIPE0] = p_td->bufEnd;
+ usb0_host_SetupStage(Req, Val, Indx, Len);
+ } else if (td_info.direction == 1) {
+ usb0_host_CtrlWriteStart(td_info.count, p_td->currBufPtr);
+ } else {
+ usb0_host_CtrlReadStart(td_info.count, p_td->currBufPtr);
+ }
+
+ (void)osSemaphoreWait(p_g_ed->semid_wait, CTL_TRANS_TIMEOUT);
+ if (p_g_ed->trans_wait == 1) {
+ p_g_ed->trans_wait = 0;
+ RZA_IO_RegWrite_32(&p_td->control, TD_CC_DEVICENOTRESPONDING, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+ }
+
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
+}
+
+static void bulk_trans(genelal_ed_t *p_g_ed) {
+ hctd_t *p_td = p_g_ed->p_curr_td;
+ hced_t *p_ed = p_g_ed->p_curr_ed;
+ tdinfo_t td_info;
+ USB_HOST_CFG_PIPETBL_t *user_table = &usb0_host_blk_ep_tbl1[0];
+ uint8_t wk_table[6];
+
+ get_td_info(p_g_ed, &td_info);
+
+ wk_table[0] = 0;
+ wk_table[1] = USB_HOST_ENDPOINT_DESC;
+ wk_table[2] = td_info.endpoint_no;
+ if (td_info.direction == 2) {
+ wk_table[2] |= USB_HOST_EP_IN;
+ }
+ wk_table[3] = USB_HOST_EP_BULK;
+ wk_table[4] = (uint8_t)td_info.msp;
+ wk_table[5] = (uint8_t)(td_info.msp >> 8);
+ p_g_ed->pipe_no = user_table->pipe_number;
+ usb0_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
+
+ set_togle(p_g_ed->pipe_no, p_td, p_ed);
+
+ p_g_ed->trans_wait = 1;
+ if (td_info.direction == 1) {
+ usb0_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+ } else {
+ usb0_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+ }
+
+ (void)osSemaphoreWait(p_g_ed->semid_wait, BLK_TRANS_TIMEOUT);
+ usb0_host_stop_transfer(p_g_ed->pipe_no);
+}
+
+static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) {
+ hctd_t *p_td = p_g_ed->p_curr_td;
+ hced_t *p_ed = p_g_ed->p_curr_ed;
+ tdinfo_t td_info;
+ USB_HOST_CFG_PIPETBL_t *user_table = &usb0_host_int_ep_tbl1[index];
+ uint8_t wk_table[6];
+ uint32_t cycle_time;
+ uint16_t devadd;
+
+ get_td_info(p_g_ed, &td_info);
+
+ wk_table[0] = 0;
+ wk_table[1] = USB_HOST_ENDPOINT_DESC;
+ wk_table[2] = td_info.endpoint_no;
+ if (td_info.direction == 2) {
+ wk_table[2] |= USB_HOST_EP_IN;
+ }
+ wk_table[3] = USB_HOST_EP_INT;
+ wk_table[4] = (uint8_t)td_info.msp;
+ wk_table[5] = (uint8_t)(td_info.msp >> 8);
+ cycle_time = chk_cycle(p_ed);
+ p_g_ed->cycle_time = cycle_time;
+ user_table->pipe_cycle = 0;
+ while (cycle_time > 1) {
+ cycle_time >>= 1;
+ user_table->pipe_cycle++;
+ }
+ if (g_usb0_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
+ usb0_host_get_devadd(td_info.devadr, &devadd);
+ if (RZA_IO_RegRead_16(&devadd, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD) == USB_HOST_HIGH_SPEED) {
+ user_table->pipe_cycle += 3;
+ if (user_table->pipe_cycle > 7) {
+ user_table->pipe_cycle = 7;
+ }
+ }
+ }
+
+ p_g_ed->pipe_no = user_table->pipe_number;
+ usb0_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
+
+ set_togle(p_g_ed->pipe_no, p_td, p_ed);
+}
+
+static uint32_t chk_cycle(hced_t *p_ed) {
+ uint32_t cnt;
+ uint32_t hit_cnt = 0;
+ uint32_t cycle_time = 1;
+ hcca_t *p_hcca;
+ hced_t *p_wk_ed;
+
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+
+ for (cnt = 0; cnt < 32; cnt++) {
+ p_wk_ed = (hced_t *)p_hcca->IntTable[cnt];
+ while (p_wk_ed != NULL) {
+ if (p_wk_ed == p_ed) {
+ hit_cnt++;
+ break;
+ }
+ p_wk_ed = p_wk_ed->nextED;
+ }
+ }
+ if (hit_cnt < 2) {
+ cycle_time = 32;
+ } else if (hit_cnt < 4) {
+ cycle_time = 16;
+ } else if (hit_cnt < 8) {
+ cycle_time = 8;
+ } else if (hit_cnt < 16) {
+ cycle_time = 4;
+ } else if (hit_cnt < 32) {
+ cycle_time = 2;
+ } else{
+ cycle_time = 1;
+ }
+
+ return cycle_time;
+}
+
+static void int_trans(genelal_ed_t *p_g_ed) {
+ hctd_t *p_td = p_g_ed->p_curr_td;
+ tdinfo_t td_info;
+
+ get_td_info(p_g_ed, &td_info);
+ p_g_ed->trans_wait = 1;
+ if (td_info.direction == 1) {
+ usb0_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+ } else {
+ usb0_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+ }
+ (void)osSemaphoreWait(p_g_ed->semid_wait, osWaitForever);
+ usb0_host_stop_transfer(p_g_ed->pipe_no);
+}
+
+static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info) {
+ hctd_t *p_td = p_g_ed->p_curr_td;
+ hced_t *p_ed = p_g_ed->p_curr_ed;
+
+ p_td_info->endpoint_no = (uint8_t)((p_ed->control >> 7) & 0x0000000F);
+ p_td_info->msp = (p_ed->control >> 16) & 0x000007FF;
+ p_td_info->devadr = p_ed->control & 0x0000000F;
+ p_td_info->speed = (p_ed->control >> 13) & 0x00000001;
+ p_td_info->direction = (p_ed->control >> 11) & 0x00000003;
+ if ((p_td_info->direction == 0) || (p_td_info->direction == 3)) {
+ if ((p_td->control & TD_CTL_MSK_DP) == TD_SETUP) {
+ p_td_info->direction = 0;
+ } else if ((p_td->control & TD_CTL_MSK_DP) == TD_OUT) {
+ p_td_info->direction = 1;
+ } else {
+ p_td_info->direction = 2;
+ }
+ }
+ if (p_td->currBufPtr != NULL) {
+ p_td_info->count = (uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1;
+ } else {
+ p_td_info->count = 0;
+ }
+}
+
+static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed) {
+ if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_0) {
+ usb0_host_set_sqclr(pipe);
+ } else if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_1) {
+ usb0_host_set_sqset(pipe);
+ } else if (((uint32_t)p_ed->headTD & ED_TOGLE_CARRY) == 0) {
+ usb0_host_set_sqclr(pipe);
+ } else {
+ usb0_host_set_sqset(pipe);
+ }
+}
+
+static void connect_check(void) {
+ uint32_t cnt;
+ uint32_t type = 0;
+ uint16_t stat;
+ uint16_t devadd = 0;
+ uint32_t wk_HcRhPortStatus1 = p_usb_reg->HcRhPortStatus1;
+
+ if (usb0_host_CheckAttach() == USB_HOST_ATTACH) {
+ type = 1;
+ }
+
+ if ((((wk_HcRhPortStatus1 & OR_RH_PORT_CCS) == 0) && (type == 0))
+ || (((wk_HcRhPortStatus1 & OR_RH_PORT_CCS) != 0) && (type != 0))) {
+ return;
+ }
+
+ if (type == 0) {
+ usb0_host_UsbDetach();
+ wk_HcRhPortStatus1 &= ~OR_RH_PORT_CCS;
+ } else {
+ usb0_host_UsbAttach();
+ stat = usb0_host_UsbBusReset();
+ RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB);
+ RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT);
+ if (stat == USB_HOST_HSMODE) {
+ wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA;
+ RZA_IO_RegWrite_16(&USB200.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
+ g_usb0_host_UsbDeviceSpeed = USB_HOST_HIGH_SPEED;
+ } else if (stat == USB_HOST_FSMODE) {
+ wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA;
+ RZA_IO_RegWrite_16(&USB200.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
+ g_usb0_host_UsbDeviceSpeed = USB_HOST_FULL_SPEED;
+ } else {
+ wk_HcRhPortStatus1 |= OR_RH_PORT_LSDA;
+ RZA_IO_RegWrite_16(&USB200.SOFCFG, 1, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
+ g_usb0_host_UsbDeviceSpeed = USB_HOST_LOW_SPEED;
+ }
+ RZA_IO_RegWrite_16(&devadd, g_usb0_host_UsbDeviceSpeed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+ usb0_host_init_pipe_status();
+ usb0_host_set_devadd(USB_HOST_DEVICE_0, &devadd);
+ wk_HcRhPortStatus1 |= OR_RH_PORT_CCS;
+ }
+ wk_HcRhPortStatus1 |= OR_RH_PORT_CSC;
+ p_usb_reg->HcRhPortStatus1 = wk_HcRhPortStatus1;
+ p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_RHSC;
+ (void)memset(&split_ctl, 0, sizeof(split_ctl));
+
+ if (type == 0) {
+ if (ctl_ed.trans_wait == 1) {
+ ohciwrapp_loc_TransEnd(ctl_ed.pipe_no, TD_CC_DEVICENOTRESPONDING);
+ }
+ if (blk_ed.trans_wait == 1) {
+ ohciwrapp_loc_TransEnd(blk_ed.pipe_no, TD_CC_DEVICENOTRESPONDING);
+ }
+ for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) {
+ if (int_ed[cnt].trans_wait == 1) {
+ ohciwrapp_loc_TransEnd(int_ed[cnt].pipe_no, TD_CC_DEVICENOTRESPONDING);
+ }
+ }
+ }
+}
+
+void ohciwrapp_loc_Connect(uint32_t type) {
+ connect_change = type;
+ (void)osSemaphoreRelease(semid_cb);
+}
+
+void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode) {
+ uint32_t cnt;
+ uint32_t sqmon;
+ hctd_t *p_td;
+ hced_t *p_ed;
+ genelal_ed_t *p_wait_ed = NULL;
+
+ if (ctl_ed.pipe_no == pipe) {
+ p_wait_ed = &ctl_ed;
+ } else if (blk_ed.pipe_no == pipe) {
+ p_wait_ed = &blk_ed;
+ } else {
+ for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) {
+ if (int_ed[cnt].pipe_no == pipe) {
+ p_wait_ed = &int_ed[cnt];
+ break;
+ }
+ }
+ }
+ if (p_wait_ed == NULL) {
+ return;
+ }
+
+ p_td = p_wait_ed->p_curr_td;
+ p_ed = p_wait_ed->p_curr_ed;
+ if ((p_td == NULL) || (p_ed == NULL)) {
+ return;
+ }
+
+ if (ConditionCode == TD_CC_NOERROR) {
+ /* ErrorCount */
+ RZA_IO_RegWrite_32(&p_td->control, 0, TD_CTL_SHFT_EC, TD_CTL_MSK_EC);
+
+ /* CurrentBufferPointer */
+ p_td->currBufPtr += ((uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1) - g_usb0_host_data_count[pipe];
+ } else {
+ /* ErrorCount */
+ RZA_IO_RegWrite_32(&p_td->control, 3, TD_CTL_SHFT_EC, TD_CTL_MSK_EC);
+ }
+
+ /* DataToggle */
+ sqmon = usb0_host_get_sqmon(pipe);
+ RZA_IO_RegWrite_32(&p_td->control, sqmon, TD_CTL_SHFT_T, TD_CTL_MSK_T);
+ if (sqmon == 0) {
+ p_ed->headTD = (hctd_t *)((uint32_t)p_ed->headTD & ~ED_TOGLE_CARRY);
+ } else {
+ p_ed->headTD = (hctd_t *)((uint32_t)p_ed->headTD | ED_TOGLE_CARRY);
+ }
+
+ /* ConditionCode */
+ RZA_IO_RegWrite_32(&p_td->control, ConditionCode, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+
+ p_wait_ed->trans_wait = 0;
+
+ (void)osSemaphoreRelease(p_wait_ed->semid_wait);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,60 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef OHCI_WRAPP_RZ_A1_H
+#define OHCI_WRAPP_RZ_A1_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define OHCI_REG_REVISION (0x00)
+#define OHCI_REG_CONTROL (0x04)
+#define OHCI_REG_COMMANDSTATUS (0x08)
+#define OHCI_REG_INTERRUPTSTATUS (0x0C)
+#define OHCI_REG_INTERRUPTENABLE (0x10)
+#define OHCI_REG_INTERRUPTDISABLE (0x14)
+#define OHCI_REG_HCCA (0x18)
+#define OHCI_REG_PERIODCURRENTED (0x1C)
+#define OHCI_REG_CONTROLHEADED (0x20)
+#define OHCI_REG_CONTROLCURRENTED (0x24)
+#define OHCI_REG_BULKHEADED (0x28)
+#define OHCI_REG_BULKCURRENTED (0x2C)
+#define OHCI_REG_DONEHEADED (0x30)
+#define OHCI_REG_FMINTERVAL (0x34)
+#define OHCI_REG_FMREMAINING (0x38)
+#define OHCI_REG_FMNUMBER (0x3C)
+#define OHCI_REG_PERIODICSTART (0x40)
+#define OHCI_REG_LSTHRESHOLD (0x44)
+#define OHCI_REG_RHDESCRIPTORA (0x48)
+#define OHCI_REG_RHDESCRIPTORB (0x4C)
+#define OHCI_REG_RHSTATUS (0x50)
+#define OHCI_REG_RHPORTSTATUS1 (0x54)
+
+typedef void (usbisr_fnc_t)(void);
+
+extern void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc, uint32_t hi_speed);
+extern uint32_t ohciwrapp_reg_r(uint32_t reg_ofs);
+extern void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data);
+extern void ohciwrapp_interrupt(uint32_t int_sense);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* OHCI_WRAPP_RZ_A1_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1_local.h Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,49 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef OHCI_WRAPP_RZ_A1_LOCAL_H
+#define OHCI_WRAPP_RZ_A1_LOCAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ConditionCode */
+#define TD_CC_NOERROR (0)
+#define TD_CC_CRC (1)
+#define TD_CC_BITSTUFFING (2)
+#define TD_CC_DATATOGGLEMISMATCH (3)
+#define TD_CC_STALL (4)
+#define TD_CC_DEVICENOTRESPONDING (5)
+#define TD_CC_PIDCHECKFAILURE (6)
+#define TD_CC_UNEXPECTEDPID (7)
+#define TD_CC_DATAOVERRUN (8)
+#define TD_CC_DATAUNDERRUN (9)
+#define TD_CC_BUFFEROVERRUN (12)
+#define TD_CC_BUFFERUNDERRUN (13)
+#define TD_CC_NOT_ACCESSED_1 (14)
+#define TD_CC_NOT_ACCESSED_2 (15)
+
+extern void ohciwrapp_loc_Connect(uint32_t type);
+extern void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* OHCI_WRAPP_RZ_A1_LOCAL_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dataio.c Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,2835 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_dataio.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static uint16_t g_usb0_host_mbw[(USB_HOST_MAX_PIPE_NO + 1)];
+
+static void usb0_host_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_host_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_host_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_host_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_host_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static uint16_t usb0_host_read_dma_d0(uint16_t pipe);
+static uint16_t usb0_host_read_dma_d1(uint16_t pipe);
+static uint16_t usb0_host_write_dma_d0(uint16_t pipe);
+static uint16_t usb0_host_write_dma_d1(uint16_t pipe);
+
+static void usb0_host_read_c_fifo(uint16_t pipe, uint16_t count);
+static void usb0_host_write_c_fifo(uint16_t Pipe, uint16_t count);
+static void usb0_host_read_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb0_host_write_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb0_host_read_d1_fifo(uint16_t pipe, uint16_t count);
+static void usb0_host_write_d1_fifo(uint16_t pipe, uint16_t count);
+
+static void usb0_host_clear_transaction_counter(uint16_t pipe);
+static void usb0_host_set_transaction_counter(uint16_t pipe, uint32_t count);
+
+static uint32_t usb0_host_com_get_dmasize(uint32_t trncount, uint32_t dtptr);
+
+static uint16_t usb0_host_set_dfacc_d0(uint16_t mbw, uint32_t count);
+static uint16_t usb0_host_set_dfacc_d1(uint16_t mbw, uint32_t count);
+
+
+/*******************************************************************************
+* Function Name: usb0_host_start_send_transfer
+* Description : Starts the USB data communication using pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data data Address
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+ uint16_t usefifo;
+ uint16_t mbw;
+
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ usb0_host_clear_bemp_sts(pipe);
+ usb0_host_clear_brdy_sts(pipe);
+ usb0_host_clear_nrdy_sts(pipe);
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+
+ usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ case USB_HOST_D0FIFO_DMA:
+ usefifo = USB_HOST_D0USE;
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ case USB_HOST_D1FIFO_DMA:
+ usefifo = USB_HOST_D1USE;
+ break;
+
+ default:
+ usefifo = USB_HOST_CUSE;
+ break;
+ };
+
+ usb0_host_set_curpipe(USB_HOST_PIPE0, usefifo, USB_HOST_NO, mbw);
+
+ usb0_host_clear_transaction_counter(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ status = usb0_host_write_buffer(pipe);
+
+ if (status != USB_HOST_FIFOERROR)
+ {
+ usb0_host_set_pid_buf(pipe);
+ }
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer
+* Description : Writes data in the buffer allocated in the pipe specified by
+* : the argument. The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer (uint16_t pipe)
+{
+ uint16_t status;
+ uint16_t usefifo;
+
+ g_usb0_host_PipeIgnore[pipe] = 0;
+ usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ status = usb0_host_write_buffer_d0(pipe);
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ status = usb0_host_write_buffer_d1(pipe);
+ break;
+
+ case USB_HOST_D0FIFO_DMA:
+ status = usb0_host_write_dma_d0(pipe);
+ break;
+
+ case USB_HOST_D1FIFO_DMA:
+ status = usb0_host_write_dma_d1(pipe);
+ break;
+
+ default:
+ status = usb0_host_write_buffer_c(pipe);
+ break;
+ };
+
+ switch (status)
+ {
+ case USB_HOST_WRITING: /* Continue of data write */
+ usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ usb0_host_enable_brdy_int(pipe); /* Enable Ready Interrupt */
+ break;
+
+ case USB_HOST_WRITEEND: /* End of data write */
+ case USB_HOST_WRITESHRT: /* End of data write */
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+
+ usb0_host_clear_nrdy_sts(pipe);
+ usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+
+ /* for last transfer */
+ usb0_host_enable_bemp_int(pipe); /* Enable Empty Interrupt */
+ break;
+
+ case USB_HOST_WRITEDMA: /* DMA write */
+ usb0_host_clear_nrdy_sts(pipe);
+ usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access status */
+ default:
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ usb0_host_disable_bemp_int(pipe); /* Disable Empty Interrupt */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer_c
+* Description : Writes data in the buffer allocated in the pipe specified in
+* : the argument. Writes data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+
+ if (pipe == USB_HOST_PIPE0)
+ {
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_CFIFO_WRITE, mbw);
+ }
+ else
+ {
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+ }
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] <= (uint32_t)size)
+ {
+ status = USB_HOST_WRITEEND; /* write continues */
+ count = g_usb0_host_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = USB_HOST_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb0_host_write_c_fifo(pipe, (uint16_t)count);
+
+ if (g_usb0_host_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb0_host_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB200.CFIFOCTR,
+ USB_CFIFOCTR_BVAL_SHIFT,
+ USB_CFIFOCTR_BVAL) == 0)
+ {
+ USB200.CFIFOCTR = USB_HOST_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb0_host_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] <= (uint32_t)size)
+ {
+ status = USB_HOST_WRITEEND; /* write continues */
+ count = g_usb0_host_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = USB_HOST_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb0_host_write_d0_fifo(pipe, (uint16_t)count);
+
+ if (g_usb0_host_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb0_host_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb0_host_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] <= (uint32_t)size)
+ {
+ status = USB_HOST_WRITEEND; /* write continues */
+ count = g_usb0_host_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = USB_HOST_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb0_host_write_d1_fifo(pipe, (uint16_t)count);
+
+ if (g_usb0_host_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb0_host_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb0_host_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D0FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND : Write end
+* : USB_HOST_WRITESHRT : short data
+* : USB_HOST_WRITING : Continue of data write
+* : USB_HOST_WRITEDMA : Write DMA
+* : USB_HOST_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_write_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb0_host_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe;
+
+ if ((count % size) != 0)
+ {
+ g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 1;
+ }
+ else
+ {
+ g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0;
+ }
+
+ dfacc = usb0_host_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA;
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_BUF2FIFO;
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes = count;
+
+ Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+ usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+
+ g_usb0_host_data_count[pipe] = 0;
+ g_usb0_host_data_pointer[pipe] += count;
+
+ status = USB_HOST_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_dma_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D1FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND : Write end
+* : USB_HOST_WRITESHRT : short data
+* : USB_HOST_WRITING : Continue of data write
+* : USB_HOST_WRITEDMA : Write DMA
+* : USB_HOST_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_write_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb0_host_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe;
+
+ if ((count % size) != 0)
+ {
+ g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 1;
+ }
+ else
+ {
+ g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0;
+ }
+
+ dfacc = usb0_host_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA;
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_BUF2FIFO;
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes = count;
+
+ Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+ usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+
+ g_usb0_host_data_count[pipe] = 0;
+ g_usb0_host_data_pointer[pipe] += count;
+
+ status = USB_HOST_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_transfer
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb0_host_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t usefifo;
+
+ usb0_host_clear_bemp_sts(pipe);
+ usb0_host_clear_brdy_sts(pipe);
+ usb0_host_clear_nrdy_sts(pipe);
+
+ usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ usb0_host_start_receive_trns_d0(pipe, size, data);
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ usb0_host_start_receive_trns_d1(pipe, size, data);
+ break;
+
+ case USB_HOST_D0FIFO_DMA:
+ usb0_host_start_receive_dma_d0(pipe, size, data);
+ break;
+
+ case USB_HOST_D1FIFO_DMA:
+ usb0_host_start_receive_dma_d1(pipe, size, data);
+ break;
+
+ default:
+ usb0_host_start_receive_trns_c(pipe, size, data);
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_trns_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* : When storing data in the buffer allocated in the pipe specified in the
+* : argument, BRDY interrupt is generated to read data
+* : in the interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ g_usb0_host_PipeDataSize[pipe] = size;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_CFIFO_READ, mbw);
+ USB200.CFIFOCTR = USB_HOST_BITBCLR;
+
+ usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+
+ usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_trns_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data in the
+* : interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ g_usb0_host_PipeDataSize[pipe] = size;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+
+ usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_trns_d1
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ g_usb0_host_PipeDataSize[pipe] = size;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+
+ usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_dma_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ g_usb0_host_PipeDataSize[pipe] = 0;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb0_host_read_dma(pipe);
+
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+ }
+
+ usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_dma_d1
+* Description : Read data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ g_usb0_host_PipeDataSize[pipe] = 0;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb0_host_read_dma(pipe);
+
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+ }
+
+ usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Uses FIF0 set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+ {
+ status = usb0_host_read_buffer_d0(pipe);
+ }
+ else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+ {
+ status = usb0_host_read_buffer_d1(pipe);
+ }
+ else
+ {
+ status = usb0_host_read_buffer_c(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb0_host_disable_brdy_int(pipe);
+ g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#else
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+#endif
+ g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access status */
+ default:
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb0_host_data_count[pipe];
+ }
+ else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb0_host_read_c_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb0_host_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer_d0
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb0_host_data_count[pipe];
+ }
+ else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb0_host_read_d0_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb0_host_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer_d1
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb0_host_data_count[pipe];
+ }
+ else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) !=0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb0_host_read_d1_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb0_host_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_dma
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO or D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READZERO ; zero data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_dma (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+ {
+ status = usb0_host_read_dma_d0(pipe);
+ }
+ else
+ {
+ status = usb0_host_read_dma_d1(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READZERO: /* End of data read */
+ usb0_host_disable_brdy_int(pipe);
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb0_host_disable_brdy_int(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+ }
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+ }
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#else
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+#endif
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access status */
+ default:
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READZERO ; zero data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_read_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb0_host_data_count[pipe];
+ status = USB_HOST_READING;
+ }
+ else
+ {
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ count = g_usb0_host_data_count[pipe];
+ }
+ else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear B_CLR */
+ status = USB_HOST_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb0_host_set_curpipe(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb0_host_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe; /* not use in read operation */
+ g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0; /* not use in read operation */
+
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA;
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_FIFO2BUF;
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes = count;
+
+ if (status == USB_HOST_READING)
+ {
+ g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSY;
+ }
+ else
+ {
+ g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+ usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb0_host_data_count[pipe] -= count;
+ g_usb0_host_data_pointer[pipe] += count;
+ g_usb0_host_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_dma_d1
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by DMA transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READZERO ; zero data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_read_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb0_host_data_count[pipe];
+ status = USB_HOST_READING;
+ }
+ else
+ {
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ count = g_usb0_host_data_count[pipe];
+ }
+ else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ status = USB_HOST_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb0_host_set_curpipe(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb0_host_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe; /* not use in read operation */
+ g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0; /* not use in read operation */
+
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA;
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_FIFO2BUF;
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes = count;
+
+ if (status == USB_HOST_READING)
+ {
+ g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSY;
+ }
+ else
+ {
+ g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+ usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb0_host_data_count[pipe] -= count;
+ g_usb0_host_data_pointer[pipe] += count;
+ g_usb0_host_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_change_fifo_port
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument. After allocating FIF0, waits in the software
+* : till the corresponding pipe becomes ready.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : USB_HOST_FIFOERROR ; Error
+* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value
+*******************************************************************************/
+uint16_t usb0_host_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ usb0_host_set_curpipe(pipe, fifosel, isel, mbw);
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ switch (fifosel)
+ {
+ case USB_HOST_CUSE:
+ buffer = USB200.CFIFOCTR;
+ break;
+
+ case USB_HOST_D0USE:
+ case USB_HOST_D0DMA:
+ buffer = USB200.D0FIFOCTR;
+ break;
+
+ case USB_HOST_D1USE:
+ case USB_HOST_D1DMA:
+ buffer = USB200.D1FIFOCTR;
+ break;
+
+ default:
+ buffer = 0;
+ break;
+ }
+
+ if ((buffer & USB_HOST_BITFRDY) == USB_HOST_BITFRDY)
+ {
+ return buffer;
+ }
+
+ loop2 = 25;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ return USB_HOST_FIFOERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_curpipe
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ g_usb0_host_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_HOST_CUSE:
+ buffer = USB200.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D0DMA:
+ case USB_HOST_D0USE:
+ buffer = USB200.D0FIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D1DMA:
+ case USB_HOST_D1USE:
+ buffer = USB200.D1FIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_curpipe2
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.(DFACC)
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* : uint16_t dfacc ; DFACC Access mode
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc)
+{
+ uint16_t buffer;
+ uint32_t loop;
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ uint32_t dummy;
+#endif
+ volatile uint32_t loop2;
+
+ g_usb0_host_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_HOST_CUSE:
+ buffer = USB200.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D0DMA:
+ case USB_HOST_D0USE:
+ buffer = USB200.D0FIFOSEL;
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB200.D0FIFO.UINT32;
+ }
+#endif
+
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D1DMA:
+ case USB_HOST_D1USE:
+ buffer = USB200.D1FIFOSEL;
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB200.D1FIFO.UINT32;
+ loop = dummy; // avoid warning.
+ }
+#endif
+
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_c_fifo
+* Description : Writes data in CFIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_write_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB200.CFIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB200.CFIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB200.CFIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_c_fifo
+* Description : Reads data from CFIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_read_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb0_host_data_pointer[pipe] = USB200.CFIFO.UINT8[HH];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT16[H];
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT32;
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_d0_fifo
+* Description : Writes data in D0FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_write_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB200.D0FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB200.D0FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB200.D0FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_d0_fifo
+* Description : Reads data from D0FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating DOFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_host_mbw[].
+* Arguments : uint16_t Pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_read_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb0_host_data_pointer[pipe] = USB200.D0FIFO.UINT8[HH];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT16[H];
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT32;
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_d1_fifo
+* Description : Writes data in D1FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_write_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB200.D1FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB200.D1FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB200.D1FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_d1_fifo
+* Description : Reads data from D1FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_read_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb0_host_data_pointer[pipe] = USB200.D1FIFO.UINT8[HH];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT16[H];
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT32;
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_com_get_dmasize
+* Description : Calculates access width of DMA transfer by the argument to
+ return as the Return Value.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : DMA transfer size : 0 8bit
+* : : 1 16bit
+* : : 2 32bit
+*******************************************************************************/
+static uint32_t usb0_host_com_get_dmasize (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+
+ if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0))
+ {
+ /* When transfer byte count is odd */
+ /* or transfer data area is 8-bit alignment */
+ size = 0; /* 8bit */
+ }
+ else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0))
+ {
+ /* When the transfer byte count is multiples of 2 */
+ /* or the transfer data area is 16-bit alignment */
+ size = 1; /* 16bit */
+ }
+ else
+ {
+ /* When the transfer byte count is multiples of 4 */
+ /* or the transfer data area is 32-bit alignment */
+ size = 2; /* 32bit */
+ }
+
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_mbw
+* Description : Calculates access width of DMA to return the value set in MBW.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : FIFO transfer size : USB_HOST_BITMBW_8 8bit
+* : : USB_HOST_BITMBW_16 16bit
+* : : USB_HOST_BITMBW_32 32bit
+*******************************************************************************/
+uint16_t usb0_host_get_mbw (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+ uint16_t mbw;
+
+ size = usb0_host_com_get_dmasize(trncount, dtptr);
+
+ if (size == 0)
+ {
+ /* 8bit */
+ mbw = USB_HOST_BITMBW_8;
+ }
+ else if (size == 1)
+ {
+ /* 16bit */
+ mbw = USB_HOST_BITMBW_16;
+ }
+ else
+ {
+ /* 32bit */
+ mbw = USB_HOST_BITMBW_32;
+ }
+
+ return mbw;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_transaction_counter
+* Description : Sets transaction counter by the argument(PIPEnTRN).
+* : Clears transaction before setting to enable transaction counter setting.
+* Arguments : uint16_t pipe ; Pipe number
+* : uint32_t bsize : Data transfer size
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_set_transaction_counter (uint16_t pipe, uint32_t bsize)
+{
+ uint16_t mxps;
+ uint16_t cnt;
+
+ if (bsize == 0)
+ {
+ return;
+ }
+
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if ((bsize % mxps) == 0)
+ {
+ cnt = (uint16_t)(bsize / mxps);
+ }
+ else
+ {
+ cnt = (uint16_t)((bsize / mxps) + 1);
+ }
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE1TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE2TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE3TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE4TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE5TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE9TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_transaction_counter
+* Description : Clears the transaction counter by the argument.
+* : After executing this function, the transaction counter is invalid.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_transaction_counter (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_stop_transfer
+* Description : Stops the USB transfer in the pipe specified by the argument.
+* : After stopping the USB transfer, clears the buffer allocated in
+* : the pipe.
+* : After executing this function, allocation in FIF0 becomes USB_HOST_PIPE0;
+* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt
+* : in the corresponding pipe becomes invalid. Sequence bit is also
+* : cleared.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_stop_transfer (uint16_t pipe)
+{
+ uint16_t usefifo;
+ uint32_t remain;
+
+ usb0_host_set_pid_nak(pipe);
+
+ usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ usb0_host_clear_transaction_counter(pipe);
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ usb0_host_clear_transaction_counter(pipe);
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ case USB_HOST_D0FIFO_DMA:
+ remain = Userdef_USB_usb0_host_stop_dma0();
+ usb0_host_dma_stop_d0(pipe, remain);
+ usb0_host_clear_transaction_counter(pipe);
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ case USB_HOST_D1FIFO_DMA:
+ remain = Userdef_USB_usb0_host_stop_dma1();
+ usb0_host_dma_stop_d1(pipe, remain);
+ usb0_host_clear_transaction_counter(pipe);
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ default:
+ usb0_host_clear_transaction_counter(pipe);
+ USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+ }
+
+ /* Interrupt of pipe set is disabled */
+ usb0_host_disable_brdy_int(pipe);
+ usb0_host_disable_nrdy_int(pipe);
+ usb0_host_disable_bemp_int(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+ usb0_host_set_csclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_dfacc_d0
+* Description : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb0_host_set_dfacc_d0 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+
+ return dfacc;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_dfacc_d1
+* Description : Sets the DFACC setting value in D1FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb0_host_set_dfacc_d1 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+
+ return dfacc;
+}
+
+/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_dma.c Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,355 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_dma.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+/* #include "usb0_host_dmacdrv.h" */
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static void usb0_host_dmaint(uint16_t fifo);
+static void usb0_host_dmaint_buf2fifo(uint16_t pipe);
+static void usb0_host_dmaint_fifo2buf(uint16_t pipe);
+
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_stop_d0
+* Description : D0FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_stop_d0 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB200.D0FBCFG,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+ {
+ buffer = USB200.D0FIFOCTR;
+ dtln = (buffer & USB_HOST_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain);
+ g_usb0_host_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_stop_d1
+* Description : D1FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_stop_d1 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB200.D1FBCFG,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+ {
+ buffer = USB200.D1FIFOCTR;
+ dtln = (buffer & USB_HOST_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain);
+ g_usb0_host_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_interrupt_d0fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb1_host_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_HOST_D0FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_interrupt_d0fifo (uint32_t int_sense)
+{
+ usb0_host_dmaint(USB_HOST_D0FIFO);
+ g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_interrupt_d1fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb0_host_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_HOST_D1FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_interrupt_d1fifo (uint32_t int_sense)
+{
+ usb0_host_dmaint(USB_HOST_D1FIFO);
+ g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dmaint
+* Description : This function is DMA transfer end interrupt
+* Arguments : uint16_t fifo ; fifo number
+* : ; USB_HOST_D0FIFO
+* : ; USB_HOST_D1FIFO
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_dmaint (uint16_t fifo)
+{
+ uint16_t pipe;
+
+ pipe = g_usb0_host_DmaPipe[fifo];
+
+ if (g_usb0_host_DmaInfo[fifo].dir == USB_HOST_BUF2FIFO)
+ {
+ usb0_host_dmaint_buf2fifo(pipe);
+ }
+ else
+ {
+ usb0_host_dmaint_fifo2buf(pipe);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dmaint_fifo2buf
+* Description : Executes read completion from FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_dmaint_fifo2buf (uint16_t pipe)
+{
+ uint32_t remain;
+ uint16_t useport;
+
+ if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+ {
+ useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ if (useport == USB_HOST_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb0_host_stop_dma0();
+ usb0_host_dma_stop_d0(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] == USB_HOST_DMA_BUSYEND)
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ else
+ {
+ usb0_host_enable_brdy_int(pipe);
+ }
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb0_host_stop_dma1();
+ usb0_host_dma_stop_d1(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] == USB_HOST_DMA_BUSYEND)
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ else
+ {
+ usb0_host_enable_brdy_int(pipe);
+ }
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dmaint_buf2fifo
+* Description : Executes write completion in FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_dmaint_buf2fifo (uint16_t pipe)
+{
+ uint16_t useport;
+ uint32_t remain;
+
+ useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ if (useport == USB_HOST_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb0_host_stop_dma0();
+ usb0_host_dma_stop_d0(pipe, remain);
+
+ if (g_usb0_host_DmaBval[USB_HOST_D0FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb0_host_stop_dma1();
+ usb0_host_dma_stop_d1(pipe, remain);
+
+ if (g_usb0_host_DmaBval[USB_HOST_D1FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+
+ usb0_host_enable_bemp_int(pipe);
+}
+
+/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_intrn.c Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,285 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_intrn.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_brdy_int
+* Description : Executes BRDY interrupt(USB_HOST_PIPE1-9).
+* : According to the pipe that interrupt is generated in,
+* : reads/writes buffer allocated in the pipe.
+* : This function is executed in the BRDY interrupt handler.
+* : This function clears BRDY interrupt status and BEMP interrupt
+* : status.
+* Arguments : uint16_t status ; BRDYSTS Register Value
+* : uint16_t int_enb ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_brdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint32_t int_sense = 0;
+ uint16_t pipe;
+ uint16_t pipebit;
+
+ for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+ {
+ pipebit = g_usb0_host_bit_set[pipe];
+
+ if ((status & pipebit) && (int_enb & pipebit))
+ {
+ USB200.BRDYSTS = (uint16_t)~pipebit;
+ USB200.BEMPSTS = (uint16_t)~pipebit;
+
+ if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+ {
+ if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] != USB_HOST_DMA_READY)
+ {
+ usb0_host_dma_interrupt_d0fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb0_host_read_dma(pipe);
+ usb0_host_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ }
+ else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_DMA)
+ {
+ if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] != USB_HOST_DMA_READY)
+ {
+ usb0_host_dma_interrupt_d1fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb0_host_read_dma(pipe);
+ usb0_host_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+ {
+ usb0_host_read_buffer(pipe);
+ }
+ else
+ {
+ usb0_host_write_buffer(pipe);
+ }
+ }
+#if(1) /* ohci_wrapp */
+ switch (g_usb0_host_pipe_status[pipe])
+ {
+ case USB_HOST_PIPE_DONE:
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+ break;
+ case USB_HOST_PIPE_NORES:
+ case USB_HOST_PIPE_STALL:
+ case USB_HOST_PIPE_ERROR:
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+ break;
+ default:
+ /* Do Nothing */
+ break;
+ }
+#endif
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_nrdy_int
+* Description : Executes NRDY interrupt(USB_HOST_PIPE1-9).
+* : Checks NRDY interrupt cause by PID. When the cause if STALL,
+* : regards the pipe state as STALL and ends the processing.
+* : Then the cause is not STALL, increments the error count to
+* : communicate again. When the error count is 3, determines
+* : the pipe state as USB_HOST_PIPE_NORES and ends the processing.
+* : This function is executed in the NRDY interrupt handler.
+* : This function clears NRDY interrupt status.
+* Arguments : uint16_t status ; NRDYSTS Register Value
+* : uint16_t int_enb ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_nrdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB200.NRDYSTS = (uint16_t)~status;
+
+ for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe])
+ {
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM) == 1)
+ {
+ if (g_usb0_host_pipe_status[pipe] == USB_HOST_PIPE_WAIT)
+ {
+ pid = usb0_host_get_pid(pipe);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#else
+ g_usb0_host_PipeIgnore[pipe]++;
+
+ if (g_usb0_host_PipeIgnore[pipe] == 3)
+ {
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+ }
+ else
+ {
+ usb0_host_set_pid_buf(pipe);
+ }
+#endif
+ }
+ }
+ }
+ else
+ {
+ /* USB Function */
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_bemp_int
+* Description : Executes BEMP interrupt(USB_HOST_PIPE1-9).
+* Arguments : uint16_t status ; BEMPSTS Register Value
+* : uint16_t int_enb ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_bemp_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+ uint16_t inbuf;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB200.BEMPSTS = (uint16_t)~status;
+
+ for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe])
+ {
+ pid = usb0_host_get_pid(pipe);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+ inbuf = usb0_host_get_inbuf(pipe);
+
+ if (inbuf == 0)
+ {
+ usb0_host_disable_bemp_int(pipe);
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+#endif
+ }
+ }
+ }
+ }
+}
+
+/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/common/usb0_host_lib.c Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,1580 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_lib.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#if(1) /* ohci_wrapp */
+#include "MBRZA1H.h" /* INTC Driver Header */
+#else
+#include "devdrv_intc.h" /* INTC Driver Header */
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_brdy_int
+* Description : Enables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_enable_brdy_int (uint16_t pipe)
+{
+ /* enable brdy interrupt */
+ USB200.BRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_disable_brdy_int
+* Description : Disables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_disable_brdy_int (uint16_t pipe)
+{
+ /* disable brdy interrupt */
+ USB200.BRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_brdy_sts
+* Description : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_brdy_sts (uint16_t pipe)
+{
+ /* clear brdy status */
+ USB200.BRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_bemp_int
+* Description : Enables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_enable_bemp_int (uint16_t pipe)
+{
+ /* enable bemp interrupt */
+ USB200.BEMPENB |= (uint16_t)g_usb0_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_disable_bemp_int
+* Description : Disables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_disable_bemp_int (uint16_t pipe)
+{
+ /* disable bemp interrupt */
+ USB200.BEMPENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_bemp_sts
+* Description : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_bemp_sts (uint16_t pipe)
+{
+ /* clear bemp status */
+ USB200.BEMPSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_nrdy_int
+* Description : Enables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : NRDY. Enables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_enable_nrdy_int (uint16_t pipe)
+{
+ /* enable nrdy interrupt */
+ USB200.NRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_disable_nrdy_int
+* Description : Disables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : NRDY. Disables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_disable_nrdy_int (uint16_t pipe)
+{
+ /* disable nrdy interrupt */
+ USB200.NRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_nrdy_sts
+* Description : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_nrdy_sts (uint16_t pipe)
+{
+ /* clear nrdy status */
+ USB200.NRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_is_hispeed
+* Description : Returns the result of USB reset hand shake (RHST) as
+* : return value.
+* Arguments : none
+* Return Value : USB_HOST_HIGH_SPEED ; Hi-Speed
+* : USB_HOST_FULL_SPEED ; Full-Speed
+* : USB_HOST_LOW_SPEED ; Low-Speed
+* : USB_HOST_NON_SPEED ; error
+*******************************************************************************/
+uint16_t usb0_host_is_hispeed (void)
+{
+ uint16_t rhst;
+ uint16_t speed;
+
+ rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0,
+ USB_DVSTCTR0_RHST_SHIFT,
+ USB_DVSTCTR0_RHST);
+ if (rhst == USB_HOST_HSMODE)
+ {
+ speed = USB_HOST_HIGH_SPEED;
+ }
+ else if (rhst == USB_HOST_FSMODE)
+ {
+ speed = USB_HOST_FULL_SPEED;
+ }
+ else if (rhst == USB_HOST_LSMODE)
+ {
+ speed = USB_HOST_LOW_SPEED;
+ }
+ else
+ {
+ speed = USB_HOST_NON_SPEED;
+ }
+
+ return speed;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_is_hispeed_enable
+* Description : Returns the USB High-Speed connection enabled status as
+* : return value.
+* Arguments : none
+* Return Value : USB_HOST_YES : Hi-Speed Enable
+* : USB_HOST_NO : Hi-Speed Disable
+*******************************************************************************/
+uint16_t usb0_host_is_hispeed_enable (void)
+{
+ uint16_t ret;
+
+ ret = USB_HOST_NO;
+
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE) == 1)
+ {
+ ret = USB_HOST_YES;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_pid_buf
+* Description : Enables communicaqtion in the pipe specified by the argument
+* : (BUF).
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_pid_buf (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb0_host_get_pid(pipe);
+
+ if (pid == USB_HOST_PID_STALL2)
+ {
+ usb0_host_set_pid_nak(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ USB_HOST_PID_BUF,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_pid_nak
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* : When the pipe status was enabling communication (BUF) before
+* : executing before executing this function, waits in the software
+* : until the pipe becomes ready after setting disabled.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_pid_nak (uint16_t pipe)
+{
+ uint16_t pid;
+ uint16_t pbusy;
+ uint32_t loop;
+
+ pid = usb0_host_get_pid(pipe);
+
+ if (pid == USB_HOST_PID_STALL2)
+ {
+ usb0_host_set_pid_stall(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ USB_HOST_PID_NAK,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+
+ if (pid == USB_HOST_PID_BUF)
+ {
+ for (loop = 0; loop < 200; loop++)
+ {
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ pbusy = RZA_IO_RegRead_16(&USB200.DCPCTR,
+ USB_DCPCTR_PBUSY_SHIFT,
+ USB_DCPCTR_PBUSY);
+ break;
+
+ case USB_HOST_PIPE1:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE2:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE3:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE4:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE5:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE6:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_HOST_PIPE7:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_HOST_PIPE8:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_HOST_PIPE9:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_PBUSY_SHIFT,
+ USB_PIPEnCTR_9_PBUSY);
+ break;
+
+ default:
+ pbusy = 1;
+ break;
+ }
+
+ if (pbusy == 0)
+ {
+ break;
+ }
+
+ Userdef_USB_usb0_host_delay_500ns();
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_pid_stall
+* Description : Disables communication (STALL) in the pipe specified by the
+* : argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_pid_stall (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb0_host_get_pid(pipe);
+
+ if (pid == USB_HOST_PID_BUF)
+ {
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ USB_HOST_PID_STALL2,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ USB_HOST_PID_STALL,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_pid_stall
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_pid_stall (uint16_t pipe)
+{
+ usb0_host_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_pid
+* Description : Returns the pipe state specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb0_host_get_pid (uint16_t pipe)
+{
+ uint16_t pid;
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ pid = RZA_IO_RegRead_16(&USB200.DCPCTR,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ pid = 0;
+ break;
+ }
+
+ return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_csclr
+* Description : CSPLIT status clear setting of sprit transaction in specified
+* : pipe is performed.
+* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+* : in DCPCTR register are continuously changed (when the sequence
+* : toggle bit of data PID is continuously changed over two or more pipes),
+* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+* : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+* : In addition, both bits should be operated after PID is set to NAK.
+* : However, when it is set to the isochronous transfer as the transfer type
+* : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_csclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ 1,
+ USB_DCPCTR_CSCLR_SHIFT,
+ USB_DCPCTR_CSCLR);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_CSCLR_SHIFT,
+ USB_PIPEnCTR_9_CSCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_sqclr
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA0.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_sqclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ 1,
+ USB_DCPCTR_SQCLR_SHIFT,
+ USB_DCPCTR_SQCLR);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQCLR_SHIFT,
+ USB_PIPEnCTR_9_SQCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_sqset
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA1.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_sqset (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ 1,
+ USB_DCPCTR_SQSET_SHIFT,
+ USB_DCPCTR_SQSET);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQSET_SHIFT,
+ USB_PIPEnCTR_9_SQSET);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_sqmon
+* Description : Toggle bit of specified pipe is obtained
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : sqmon
+*******************************************************************************/
+uint16_t usb0_host_get_sqmon (uint16_t pipe)
+{
+ uint16_t sqmon;
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ sqmon = RZA_IO_RegRead_16(&USB200.DCPCTR,
+ USB_DCPCTR_SQMON_SHIFT,
+ USB_DCPCTR_SQMON);
+ break;
+
+ case USB_HOST_PIPE1:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE2:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE3:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE4:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE5:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE6:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_HOST_PIPE7:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_HOST_PIPE8:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_HOST_PIPE9:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_SQMON_SHIFT,
+ USB_PIPEnCTR_9_SQMON);
+ break;
+
+ default:
+ sqmon = 0;
+ break;
+ }
+
+ return sqmon;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_aclrm
+* Description : The buffer of specified pipe is initialized
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_host_aclrm (uint16_t pipe)
+{
+ usb0_host_set_aclrm(pipe);
+ usb0_host_clr_aclrm(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clr_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clr_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 0,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_inbuf
+* Description : Returns INBUFM of the pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : inbuf
+*******************************************************************************/
+uint16_t usb0_host_get_inbuf (uint16_t pipe)
+{
+ uint16_t inbuf;
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE1:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE2:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE3:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE4:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE5:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE6:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE7:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE8:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE9:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_INBUFM_SHIFT,
+ USB_PIPEnCTR_9_INBUFM);
+ break;
+
+ default:
+ inbuf = 0;
+ break;
+ }
+
+ return inbuf;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_setting_interrupt
+* Description : Sets the USB module interrupt level.
+* Arguments : uint8_t level ; interrupt level
+* Return Value : none
+*******************************************************************************/
+void usb0_host_setting_interrupt (uint8_t level)
+{
+#if(1) /* ohci_wrapp */
+ IRQn_Type d0fifo_dmaintid;
+ IRQn_Type d1fifo_dmaintid;
+
+ InterruptHandlerRegister(USBI0_IRQn, usb0_host_interrupt);
+ GIC_SetPriority(USBI0_IRQn, level);
+ GIC_EnableIRQ(USBI0_IRQn);
+
+ d0fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d0fifo_dmaintid();
+
+ if (d0fifo_dmaintid != 0xFFFF)
+ {
+ InterruptHandlerRegister(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo);
+ GIC_SetPriority(d0fifo_dmaintid, level);
+ GIC_EnableIRQ(d0fifo_dmaintid);
+ }
+
+ d1fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d1fifo_dmaintid();
+
+ if (d1fifo_dmaintid != 0xFFFF)
+ {
+ InterruptHandlerRegister(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo);
+ GIC_SetPriority(d1fifo_dmaintid, level);
+ GIC_EnableIRQ(d1fifo_dmaintid);
+ }
+#else
+ uint16_t d0fifo_dmaintid;
+ uint16_t d1fifo_dmaintid;
+
+ R_INTC_RegistIntFunc(INTC_ID_USBI0, usb0_host_interrupt);
+ R_INTC_SetPriority(INTC_ID_USBI0, level);
+ R_INTC_Enable(INTC_ID_USBI0);
+
+ d0fifo_dmaintid = Userdef_USB_usb0_host_d0fifo_dmaintid();
+
+ if (d0fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo);
+ R_INTC_SetPriority(d0fifo_dmaintid, level);
+ R_INTC_Enable(d0fifo_dmaintid);
+ }
+
+ d1fifo_dmaintid = Userdef_USB_usb0_host_d1fifo_dmaintid();
+
+ if (d1fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo);
+ R_INTC_SetPriority(d1fifo_dmaintid, level);
+ R_INTC_Enable(d1fifo_dmaintid);
+ }
+#endif
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_reset_module
+* Description : Initializes the USB module.
+* : Enables providing clock to the USB module.
+* : Sets USB bus wait register.
+* Arguments : uint16_t clockmode ; 48MHz ; USBHCLOCK_X1_48MHZ
+* : ; 12MHz ; USBHCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+void usb0_host_reset_module (uint16_t clockmode)
+{
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+ USB_SYSCFG_UPLLE_SHIFT,
+ USB_SYSCFG_UPLLE) == 1)
+ {
+ if ((USB200.SYSCFG0 & USB_HOST_BITUCKSEL) != clockmode)
+ {
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+ Userdef_USB_usb0_host_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ Userdef_USB_usb0_host_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+ Userdef_USB_usb0_host_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+
+ USB200.BUSWAIT = (uint16_t)(USB_HOST_BUSWAIT_05 & USB_HOST_BITBWAIT);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_buf_size
+* Description : Obtains pipe buffer size specified by the argument and
+* : maximum packet size of the USB device in use.
+* : When USB_HOST_PIPE0 is specified by the argument, obtains the maximum
+* : packet size of the USB device using the corresponding pipe.
+* : For the case that USB_HOST_PIPE0 is not assigned by the argument, when the
+* : corresponding pipe is in continuous transfer mode,
+* : obtains the buffer size allocated in the corresponcing pipe,
+* : when incontinuous transfer, obtains maximum packet size.
+* Arguments : uint16_t ; pipe Number
+* Return Value : Maximum packet size or buffer size
+*******************************************************************************/
+uint16_t usb0_host_get_buf_size (uint16_t pipe)
+{
+ uint16_t size;
+ uint16_t bufsize;
+
+ if (pipe == USB_HOST_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1)
+ {
+ bufsize = RZA_IO_RegRead_16(&g_usb0_host_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE);
+ size = (uint16_t)((bufsize + 1) * USB_HOST_PIPExBUF);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+ }
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_mxps
+* Description : Obtains maximum packet size of the USB device using the pipe
+* : specified by the argument.
+* Arguments : uint16_t ; Pipe Number
+* Return Value : Max Packet Size
+*******************************************************************************/
+uint16_t usb0_host_get_mxps (uint16_t pipe)
+{
+ uint16_t size;
+
+ if (pipe == USB_HOST_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+
+ return size;
+}
+
+/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_controlrw.c Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,434 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_controlrw.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_CtrlTransStart
+* Description : Executes USB control transfer.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Req ; bmRequestType & bRequest
+* : uint16_t Val ; wValue
+* : uint16_t Indx ; wIndex
+* : uint16_t Len ; wLength
+* : uint8_t *Buf ; Data buffer
+* Return Value : DEVDRV_SUCCESS ; SUCCESS
+* : DEVDRV_ERROR ; ERROR
+*******************************************************************************/
+int32_t usb0_host_CtrlTransStart (uint16_t devadr, uint16_t Req, uint16_t Val,
+ uint16_t Indx, uint16_t Len, uint8_t * Buf)
+{
+ if (g_usb0_host_UsbDeviceSpeed == USB_HOST_LOW_SPEED)
+ {
+ RZA_IO_RegWrite_16(&USB200.SOFCFG,
+ 1,
+ USB_SOFCFG_TRNENSEL_SHIFT,
+ USB_SOFCFG_TRNENSEL);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SOFCFG,
+ 0,
+ USB_SOFCFG_TRNENSEL_SHIFT,
+ USB_SOFCFG_TRNENSEL);
+ }
+
+ USB200.DCPMAXP = (uint16_t)((uint16_t)(devadr << 12) + g_usb0_host_default_max_packet[devadr]);
+
+ if (g_usb0_host_pipe_status[USB_HOST_PIPE0] == USB_HOST_PIPE_IDLE)
+ {
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT;
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
+ g_usb0_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
+
+ if (Len == 0)
+ {
+ g_usb0_host_CmdStage |= USB_HOST_MODE_NO_DATA; /* No-data Control */
+ }
+ else
+ {
+ if ((Req & 0x0080) != 0)
+ {
+ g_usb0_host_CmdStage |= USB_HOST_MODE_READ; /* Control Read */
+ }
+ else
+ {
+ g_usb0_host_CmdStage |= USB_HOST_MODE_WRITE; /* Control Write */
+ }
+ }
+
+ g_usb0_host_SavReq = Req; /* save request */
+ g_usb0_host_SavVal = Val;
+ g_usb0_host_SavIndx = Indx;
+ g_usb0_host_SavLen = Len;
+ }
+ else
+ {
+ if ((g_usb0_host_SavReq != Req) || (g_usb0_host_SavVal != Val)
+ || (g_usb0_host_SavIndx != Indx) || (g_usb0_host_SavLen != Len))
+ {
+ return DEVDRV_ERROR;
+ }
+ }
+
+ switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ /* --------------- SETUP STAGE --------------- */
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE):
+ usb0_host_SetupStage(Req, Val, Indx, Len);
+ break;
+
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DOING):
+ /* do nothing */
+ break;
+
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DONE): /* goto next stage */
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
+ switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
+ {
+ case USB_HOST_MODE_WRITE:
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA;
+ break;
+
+ case USB_HOST_MODE_READ:
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA;
+ break;
+
+ case USB_HOST_MODE_NO_DATA:
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ break;
+
+ default:
+ break;
+ }
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+ break;
+
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_NORES):
+ if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+ {
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ }
+ else
+ {
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+ }
+ break;
+
+ /* --------------- DATA STAGE --------------- */
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE):
+ switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
+ {
+ case USB_HOST_MODE_WRITE:
+ usb0_host_CtrlWriteStart((uint32_t)Len, Buf);
+ break;
+
+ case USB_HOST_MODE_READ:
+ usb0_host_CtrlReadStart((uint32_t)Len, Buf);
+ break;
+
+ default:
+ break;
+ }
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ /* do nothing */
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DONE): /* goto next stage */
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_NORES):
+ if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+ {
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ }
+ else
+ {
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+ usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+ usb0_host_set_pid_buf(USB_HOST_PIPE0);
+ }
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_STALL):
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
+ break;
+
+ /* --------------- STATUS STAGE --------------- */
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE):
+ usb0_host_StatusStage();
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ /* do nothing */
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DONE): /* end of Control transfer */
+ usb0_host_set_pid_nak(USB_HOST_PIPE0);
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_DONE; /* exit DONE */
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_NORES):
+ if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+ {
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ }
+ else
+ {
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+ usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+ usb0_host_set_pid_buf(USB_HOST_PIPE0);
+ }
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_STALL):
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
+ break;
+
+ default:
+ break;
+ }
+
+ if (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT)
+ {
+ RZA_IO_RegWrite_16(&USB200.SOFCFG,
+ 0,
+ USB_SOFCFG_TRNENSEL_SHIFT,
+ USB_SOFCFG_TRNENSEL);
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_SetupStage
+* Description : Executes USB control transfer/set up stage.
+* Arguments : uint16_t Req ; bmRequestType & bRequest
+* : uint16_t Val ; wValue
+* : uint16_t Indx ; wIndex
+* : uint16_t Len ; wLength
+* Return Value : none
+*******************************************************************************/
+void usb0_host_SetupStage (uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len)
+{
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+
+ USB200.INTSTS1 = (uint16_t)~(USB_HOST_BITSACK | USB_HOST_BITSIGN); /* Status Clear */
+ USB200.USBREQ = Req;
+ USB200.USBVAL = Val;
+ USB200.USBINDX = Indx;
+ USB200.USBLENG = Len;
+ USB200.DCPCTR = USB_HOST_BITSUREQ; /* PID=NAK & Send Setup */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_StatusStage
+* Description : Executes USB control transfer/status stage.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_StatusStage (void)
+{
+ uint8_t Buf1[16];
+
+ switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
+ {
+ case USB_HOST_MODE_READ:
+ usb0_host_CtrlWriteStart((uint32_t)0, (uint8_t *)&Buf1);
+ break;
+
+ case USB_HOST_MODE_WRITE:
+ usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1);
+ break;
+
+ case USB_HOST_MODE_NO_DATA:
+ usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_CtrlWriteStart
+* Description : Executes USB control transfer/data stage(write).
+* Arguments : uint32_t Bsize ; Data Size
+* : uint8_t *Table ; Data Table Address
+* Return Value : USB_HOST_WRITESHRT ; End of data write
+* : USB_HOST_WRITEEND ; End of data write (not null)
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_FIFOERROR ; FIFO access error
+*******************************************************************************/
+uint16_t usb0_host_CtrlWriteStart (uint32_t Bsize, uint8_t * Table)
+{
+ uint16_t EndFlag_K;
+ uint16_t mbw;
+
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+
+ usb0_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */
+ g_usb0_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */
+ g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */
+
+ USB200.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+ Userdef_USB_usb0_host_delay_10us(3);
+#endif
+ RZA_IO_RegWrite_16(&USB200.DCPCFG,
+ 1,
+ USB_DCPCFG_DIR_SHIFT,
+ USB_DCPCFG_DIR);
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_BITISEL, mbw);
+ USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+
+ usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+ EndFlag_K = usb0_host_write_buffer_c(USB_HOST_PIPE0);
+ /* Host Control sequence */
+ switch (EndFlag_K)
+ {
+ case USB_HOST_WRITESHRT: /* End of data write */
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
+ usb0_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */
+ break;
+
+ case USB_HOST_WRITEEND: /* End of data write (not null) */
+ case USB_HOST_WRITING: /* Continue of data write */
+ usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
+ usb0_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ break;
+
+ default:
+ break;
+ }
+ usb0_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */
+ return (EndFlag_K); /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_CtrlReadStart
+* Description : Executes USB control transfer/data stage(read).
+* Arguments : uint32_t Bsize ; Data Size
+* : uint8_t *Table ; Data Table Address
+* Return Value : none
+*******************************************************************************/
+void usb0_host_CtrlReadStart (uint32_t Bsize, uint8_t * Table)
+{
+ uint16_t mbw;
+
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+
+ usb0_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */
+ g_usb0_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */
+ g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */
+
+ USB200.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+ Userdef_USB_usb0_host_delay_10us(3);
+#endif
+ RZA_IO_RegWrite_16(&USB200.DCPCFG,
+ 0,
+ USB_DCPCFG_DIR_SHIFT,
+ USB_DCPCFG_DIR);
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, mbw);
+ USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+
+ usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
+ usb0_host_enable_brdy_int(USB_HOST_PIPE0); /* Ok */
+ usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+ usb0_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */
+}
+
+/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_drv_api.c Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,889 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_drv_api.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_resetEP(USB_HOST_CFG_PIPETBL_t *tbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_api_host_init
+* Description : Initializes USB module in the USB host mode.
+* : USB connection is executed when executing this function in
+* : the states that USB device isconnected to the USB port.
+* Arguments : uint8_t int_level : USB Module interrupt level
+* : USBU16 mode : USB_HOST_HIGH_SPEED
+* : USB_HOST_FULL_SPEED
+* : uint16_t clockmode : USB Clock mode
+* Return Value : USB detach or attach
+* : USB_HOST_ATTACH
+* : USB_HOST_DETACH
+*******************************************************************************/
+uint16_t usb0_api_host_init (uint8_t int_level, uint16_t mode, uint16_t clockmode)
+{
+ uint16_t connect;
+ volatile uint8_t dummy_buf;
+
+ CPG.STBCR7 &= 0xfd; /*The clock of USB0 modules is permitted */
+ dummy_buf = CPG.STBCR7; /* (Dummy read) */
+
+ g_usb0_host_SupportUsbDeviceSpeed = mode;
+
+ usb0_host_setting_interrupt(int_level);
+ usb0_host_reset_module(clockmode);
+
+ g_usb0_host_bchg_flag = USB_HOST_NO;
+ g_usb0_host_detach_flag = USB_HOST_NO;
+ g_usb0_host_attach_flag = USB_HOST_NO;
+
+ g_usb0_host_driver_state = USB_HOST_DRV_DETACHED;
+ g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+ usb0_host_InitModule();
+
+ connect = usb0_host_CheckAttach();
+
+ if (connect == USB_HOST_ATTACH)
+ {
+ g_usb0_host_attach_flag = USB_HOST_YES;
+ }
+ else
+ {
+ usb0_host_UsbDetach2();
+ }
+
+ return connect;
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb0_api_host_enumeration
+* Description : Initializes USB module in the USB host mode.
+* : USB connection is executed when executing this function in
+* : the states that USB device isconnected to the USB port.
+* Arguments : uint16_t devadr : device address
+* Return Value : DEVDRV_USBH_DETACH_ERR : device detach
+* : DEVDRV_SUCCESS : device enumeration success
+* : DEVDRV_ERROR : device enumeration error
+*******************************************************************************/
+int32_t usb0_api_host_enumeration (uint16_t devadr)
+{
+ int32_t ret;
+ uint16_t driver_sts;
+
+ g_usb0_host_setUsbAddress = devadr;
+
+ while (1)
+ {
+ driver_sts = usb0_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ ret = DEVDRV_USBH_DETACH_ERR;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+ {
+ ret = DEVDRV_SUCCESS;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_STALL)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+
+ if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ while (1)
+ {
+ driver_sts = usb0_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_detach
+* Description : USB detach routine
+* Arguments : none
+* Return Value : USB_HOST_DETACH : USB detach
+* : USB_HOST_ATTACH : USB attach
+* : DEVDRV_ERROR : error
+*******************************************************************************/
+int32_t usb0_api_host_detach (void)
+{
+ int32_t ret;
+ uint16_t driver_sts;
+
+ while (1)
+ {
+ driver_sts = usb0_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ ret = USB_HOST_DETACH;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+ {
+ ret = USB_HOST_ATTACH;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_STALL)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+
+ if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ while (1)
+ {
+ driver_sts = usb0_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_data_in
+* Description : Executes USB transfer as data-in in the argument specified pipe.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Pipe ; Pipe Number
+* : uint32_t Size ; Data Size
+* : uint8_t *data_buf ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_data_in (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+ int32_t ret;
+
+ if (Pipe == USB_HOST_PIPE0)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 1)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+ {
+ usb0_host_start_receive_transfer(Pipe, Size, data_buf);
+ }
+ else
+ {
+ return DEVDRV_ERROR; /* Now pipe is busy */
+ }
+
+ /* waiting for completing routine */
+ do
+ {
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ break;
+ }
+
+ if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+ {
+ break;
+ }
+
+ } while (1);
+
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ return DEVDRV_USBH_DETACH_ERR;
+ }
+
+ switch (g_usb0_host_pipe_status[Pipe])
+ {
+ case USB_HOST_PIPE_DONE:
+ ret = DEVDRV_SUCCESS;
+ break;
+
+ case USB_HOST_PIPE_STALL:
+ ret = DEVDRV_USBH_STALL;
+ break;
+
+ case USB_HOST_PIPE_NORES:
+ ret = DEVDRV_USBH_COM_ERR;
+ break;
+
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ usb0_host_stop_transfer(Pipe);
+
+ g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_data_out
+* Description : Executes USB transfer as data-out in the argument specified pipe.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Pipe ; Pipe Number
+* : uint32_t Size ; Data Size
+* : uint8_t *data_buf ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_data_out (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+ int32_t ret;
+
+ if (Pipe == USB_HOST_PIPE0)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+ {
+ usb0_host_start_send_transfer(Pipe, Size, data_buf);
+ }
+ else
+ {
+ return DEVDRV_ERROR; /* Now pipe is busy */
+ }
+
+ /* waiting for completing routine */
+ do
+ {
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ break;
+ }
+
+ if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+ {
+ break;
+ }
+
+ } while (1);
+
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ return DEVDRV_USBH_DETACH_ERR;
+ }
+
+ switch (g_usb0_host_pipe_status[Pipe])
+ {
+ case USB_HOST_PIPE_DONE:
+ ret = DEVDRV_SUCCESS;
+ break;
+
+ case USB_HOST_PIPE_STALL:
+ ret = DEVDRV_USBH_STALL;
+ break;
+
+ case USB_HOST_PIPE_NORES:
+ ret = DEVDRV_USBH_COM_ERR;
+ break;
+
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ usb0_host_stop_transfer(Pipe);
+
+ g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_control_transfer
+* Description : Executes USB control transfer.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Req ; bmRequestType & bRequest
+* : uint16_t Val ; wValue
+* : uint16_t Indx ; wIndex
+* : uint16_t Len ; wLength
+* : uint8_t *buf ; Buffer
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_USBH_DETACH_ERR ; device detach
+* : DEVDRV_USBH_CTRL_COM_ERR ; device no response
+* : DEVDRV_USBH_STALL ; STALL
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_control_transfer (uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx,
+ uint16_t Len, uint8_t * Buf)
+{
+ int32_t ret;
+
+ do
+ {
+ ret = usb0_host_CtrlTransStart(devadr, Req, Val, Indx, Len, Buf);
+
+ if (ret == DEVDRV_SUCCESS)
+ {
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ break;
+ }
+
+ if ((g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_IDLE)
+ && (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT))
+ {
+ break;
+ }
+ }
+ else
+ {
+ return DEVDRV_ERROR;
+ }
+ } while (1);
+
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ return DEVDRV_USBH_DETACH_ERR;
+ }
+
+ switch (g_usb0_host_pipe_status[USB_HOST_PIPE0])
+ {
+ case USB_HOST_PIPE_DONE:
+ ret = DEVDRV_SUCCESS;
+ break;
+
+ case USB_HOST_PIPE_STALL:
+ ret = DEVDRV_USBH_STALL;
+ break;
+
+ case USB_HOST_PIPE_NORES:
+ ret = DEVDRV_USBH_CTRL_COM_ERR;
+ break;
+
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_set_endpoint
+* Description : Sets end point on the information specified in the argument.
+* Arguments : uint16_t devadr ; device address
+* : uint8_t *configdescriptor ; device configration descriptor
+* : USB_HOST_CFG_PIPETBL_t *user_table ; pipe table
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_set_endpoint (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * configdescriptor)
+{
+ uint16_t ret;
+ uint32_t end_point;
+ uint32_t offset;
+ uint32_t totalLength;
+ USB_HOST_CFG_PIPETBL_t * pipe_table;
+
+ /* End Point Search */
+ end_point = 0;
+ offset = configdescriptor[0];
+ totalLength = (uint16_t)(configdescriptor[2] + ((uint16_t)configdescriptor[3] << 8));
+
+ do
+ {
+ if (configdescriptor[offset + 1] == USB_HOST_ENDPOINT_DESC)
+ {
+ pipe_table = &user_table[end_point];
+
+ if (pipe_table->pipe_number == 0xffff)
+ {
+ break;
+ }
+
+ ret = usb0_api_host_SetEndpointTable(devadr, pipe_table, (uint8_t *)&configdescriptor[offset]);
+
+ if ((ret != USB_HOST_PIPE_IN) && (ret != USB_HOST_PIPE_OUT))
+ {
+ return DEVDRV_ERROR;
+ }
+
+ ++end_point;
+ }
+
+ /* Next End Point Search */
+ offset += configdescriptor[offset];
+
+ } while (offset < totalLength);
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_clear_endpoint
+* Description : Clears the pipe definition table specified in the argument.
+* Arguments : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_clear_endpoint (USB_HOST_CFG_PIPETBL_t * user_table)
+{
+ uint16_t pipe;
+
+ for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+ {
+ if (user_table->pipe_number == 0xffff)
+ {
+ break;
+ }
+ user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+ user_table->pipe_max_pktsize = 0;
+ user_table->pipe_cycle = 0;
+
+ user_table++;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_clear_endpoint_pipe
+* Description : Clears the pipe definition table specified in the argument.
+* Arguments : uint16_t pipe_sel : Pipe Number
+* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_clear_endpoint_pipe (uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t * user_table)
+{
+ uint16_t pipe;
+
+ for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+ {
+ if (user_table->pipe_number == 0xffff)
+ {
+ break;
+ }
+
+ if (user_table->pipe_number == pipe_sel)
+ {
+ user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+ user_table->pipe_max_pktsize = 0;
+ user_table->pipe_cycle = 0;
+ break;
+ }
+
+ user_table++;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_api_host_SetEndpointTable
+* Description : Sets the end point on the information specified by the argument.
+* Arguments : uint16_t devadr : device address
+* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* : uint8_t *Table : Endpoint descriptor
+* Return Value : USB_HOST_DIR_H_IN ; IN endpoint
+* : USB_HOST_DIR_H_OUT ; OUT endpoint
+* : USB_END_POINT_ERROR ; error
+*******************************************************************************/
+uint16_t usb0_api_host_SetEndpointTable (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * Table)
+{
+ uint16_t PipeCfg;
+ uint16_t PipeMaxp;
+ uint16_t pipe_number;
+ uint16_t ret;
+ uint16_t ret_flag = 0; // avoid warning.
+
+ pipe_number = user_table->pipe_number;
+
+ if (Table[1] != USB_HOST_ENDPOINT_DESC)
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ switch (Table[3] & USB_HOST_EP_TYPE)
+ {
+ case USB_HOST_EP_CNTRL:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+
+ case USB_HOST_EP_ISO:
+ if ((pipe_number != USB_HOST_PIPE1) && (pipe_number != USB_HOST_PIPE2))
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ PipeCfg = USB_HOST_ISO;
+ break;
+
+ case USB_HOST_EP_BULK:
+ if ((pipe_number < USB_HOST_PIPE1) || (pipe_number > USB_HOST_PIPE5))
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ PipeCfg = USB_HOST_BULK;
+ break;
+
+ case USB_HOST_EP_INT:
+ if ((pipe_number < USB_HOST_PIPE6) || (pipe_number > USB_HOST_PIPE9))
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ PipeCfg = USB_HOST_INTERRUPT;
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+
+ /* Set pipe configuration table */
+ if ((Table[2] & USB_HOST_EP_DIR_MASK) == USB_HOST_EP_IN) /* IN(receive) */
+ {
+ if (PipeCfg == USB_HOST_ISO)
+ {
+ /* Transfer Type is ISO*/
+ PipeCfg |= USB_HOST_DIR_H_IN;
+
+ switch (user_table->fifo_port)
+ {
+ case USB_HOST_CUSE:
+ case USB_HOST_D0USE:
+ case USB_HOST_D1USE:
+ case USB_HOST_D0DMA:
+ case USB_HOST_D1DMA:
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+ }
+ else
+ {
+ /* Transfer Type is BULK or INT */
+ PipeCfg |= (USB_HOST_SHTNAKON | USB_HOST_DIR_H_IN); /* Compulsory SHTNAK */
+
+ switch (user_table->fifo_port)
+ {
+ case USB_HOST_CUSE:
+ case USB_HOST_D0USE:
+ case USB_HOST_D1USE:
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+ break;
+
+ case USB_HOST_D0DMA:
+ case USB_HOST_D1DMA:
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+#ifdef __USB_DMA_BFRE_ENABLE__
+ /* this routine cannnot be perfomred if read operation is executed in buffer size */
+ PipeCfg |= USB_HOST_BFREON;
+#endif
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+ }
+ ret = USB_HOST_PIPE_IN;
+ }
+ else /* OUT(send) */
+ {
+ if (PipeCfg == USB_HOST_ISO)
+ {
+ /* Transfer Type is ISO*/
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+ }
+ else
+ {
+ /* Transfer Type is BULK or INT */
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+ }
+ PipeCfg |= USB_HOST_DIR_H_OUT;
+ ret = USB_HOST_PIPE_OUT;
+ }
+
+ switch (user_table->fifo_port)
+ {
+ case USB_HOST_CUSE:
+ g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_CFIFO_USE;
+ break;
+
+ case USB_HOST_D0USE:
+ g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_USE;
+ break;
+
+ case USB_HOST_D1USE:
+ g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_USE;
+ break;
+
+ case USB_HOST_D0DMA:
+ g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_DMA;
+ break;
+
+ case USB_HOST_D1DMA:
+ g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_DMA;
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+
+ /* Endpoint number set */
+ PipeCfg |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+ g_usb0_host_PipeTbl[pipe_number] |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+
+ /* Max packet size set */
+ PipeMaxp = (uint16_t)((uint16_t)Table[4] | (uint16_t)((uint16_t)Table[5] << 8));
+
+ if (PipeMaxp == 0u)
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ /* Set device address */
+ PipeMaxp |= (uint16_t)(devadr << 12);
+
+ user_table->pipe_cfg = PipeCfg;
+ user_table->pipe_max_pktsize = PipeMaxp;
+
+ usb0_host_resetEP(user_table);
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_resetEP
+* Description : Sets the end point on the information specified by the argument.
+* Arguments : USB_HOST_CFG_PIPETBL_t *tbl : pipe table
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_resetEP (USB_HOST_CFG_PIPETBL_t * tbl)
+{
+
+ uint16_t pipe;
+
+ /* Host pipe */
+ /* The pipe number of pipe definition table is obtained */
+ pipe = (uint16_t)(tbl->pipe_number & USB_HOST_BITCURPIPE); /* Pipe Number */
+
+ /* FIFO port access pipe is set to initial value */
+ /* The connection with FIFO should be cut before setting the pipe */
+ if (RZA_IO_RegRead_16(&USB200.CFIFOSEL,
+ USB_CFIFOSEL_CURPIPE_SHIFT,
+ USB_CFIFOSEL_CURPIPE) == pipe)
+ {
+ usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, USB_HOST_BITMBW_16);
+ }
+
+ if (RZA_IO_RegRead_16(&USB200.D0FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+ }
+
+ if (RZA_IO_RegRead_16(&USB200.D1FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+ }
+
+ /* Interrupt of pipe set is disabled */
+ usb0_host_disable_brdy_int(pipe);
+ usb0_host_disable_nrdy_int(pipe);
+ usb0_host_disable_bemp_int(pipe);
+
+ /* Pipe to set is set to NAK */
+ usb0_host_set_pid_nak(pipe);
+
+ /* Pipe is set */
+ USB200.PIPESEL = pipe;
+
+ USB200.PIPECFG = tbl->pipe_cfg;
+ USB200.PIPEBUF = tbl->pipe_buf;
+ USB200.PIPEMAXP = tbl->pipe_max_pktsize;
+ USB200.PIPEPERI = tbl->pipe_cycle;
+
+ g_usb0_host_pipecfg[pipe] = tbl->pipe_cfg;
+ g_usb0_host_pipebuf[pipe] = tbl->pipe_buf;
+ g_usb0_host_pipemaxp[pipe] = tbl->pipe_max_pktsize;
+ g_usb0_host_pipeperi[pipe] = tbl->pipe_cycle;
+
+ /* Sequence bit clear */
+ usb0_host_set_sqclr(pipe);
+
+ usb0_host_aclrm(pipe);
+ usb0_host_set_csclr(pipe);
+
+ /* Pipe window selection is set to unused */
+ USB200.PIPESEL = USB_HOST_PIPE0;
+
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb0_api_host_data_count
+* Description : Get g_usb0_host_data_count[pipe]
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t *data_count ; return g_usb0_data_count[pipe]
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_data_count (uint16_t pipe, uint32_t * data_count)
+{
+ if (pipe > USB_HOST_MAX_PIPE_NO)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ *data_count = g_usb0_host_PipeDataSize[pipe];
+
+ return DEVDRV_SUCCESS;
+}
+#endif
+
+/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_global.c Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,137 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_global.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+const uint16_t g_usb0_host_bit_set[16] =
+{
+ 0x0001, 0x0002, 0x0004, 0x0008,
+ 0x0010, 0x0020, 0x0040, 0x0080,
+ 0x0100, 0x0200, 0x0400, 0x0800,
+ 0x1000, 0x2000, 0x4000, 0x8000
+};
+
+uint32_t g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+uint8_t * g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+uint16_t g_usb0_host_PipeIgnore[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb0_host_PipeTbl[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb0_host_pipe_status[USB_HOST_MAX_PIPE_NO + 1];
+uint32_t g_usb0_host_PipeDataSize[USB_HOST_MAX_PIPE_NO + 1];
+
+USB_HOST_DMA_t g_usb0_host_DmaInfo[2];
+
+uint16_t g_usb0_host_DmaPipe[2];
+uint16_t g_usb0_host_DmaBval[2];
+uint16_t g_usb0_host_DmaStatus[2];
+
+uint16_t g_usb0_host_driver_state;
+uint16_t g_usb0_host_ConfigNum;
+uint16_t g_usb0_host_CmdStage;
+uint16_t g_usb0_host_bchg_flag;
+uint16_t g_usb0_host_detach_flag;
+uint16_t g_usb0_host_attach_flag;
+
+uint16_t g_usb0_host_UsbAddress;
+uint16_t g_usb0_host_setUsbAddress;
+uint16_t g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+uint16_t g_usb0_host_UsbDeviceSpeed;
+uint16_t g_usb0_host_SupportUsbDeviceSpeed;
+
+uint16_t g_usb0_host_SavReq;
+uint16_t g_usb0_host_SavVal;
+uint16_t g_usb0_host_SavIndx;
+uint16_t g_usb0_host_SavLen;
+
+uint16_t g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_init_pipe_status
+* Description : Initialize pipe status.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_init_pipe_status (void)
+{
+ uint16_t loop;
+
+ g_usb0_host_ConfigNum = 0;
+
+ for (loop = 0; loop < (USB_HOST_MAX_PIPE_NO + 1); ++loop)
+ {
+ g_usb0_host_pipe_status[loop] = USB_HOST_PIPE_IDLE;
+ g_usb0_host_PipeDataSize[loop] = 0;
+
+ /* pipe configuration in usb0_host_resetEP() */
+ g_usb0_host_pipecfg[loop] = 0;
+ g_usb0_host_pipebuf[loop] = 0;
+ g_usb0_host_pipemaxp[loop] = 0;
+ g_usb0_host_pipeperi[loop] = 0;
+ }
+}
+
+/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbint.c Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,496 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_usbint.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_interrupt1(void);
+static void usb0_host_BRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb0_host_NRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb0_host_BEMPInterrupt(uint16_t Status, uint16_t Int_enbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_interrupt
+* Description : Executes USB interrupt.
+* : Register this function in the USB interrupt handler.
+* : Set CFIF0 in the pipe set before the interrupt after executing
+* : this function.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_host_interrupt (uint32_t int_sense)
+{
+ uint16_t savepipe1;
+ uint16_t savepipe2;
+ uint16_t buffer;
+
+ savepipe1 = USB200.CFIFOSEL;
+ savepipe2 = USB200.PIPESEL;
+ usb0_host_interrupt1();
+
+ /* Control transmission changes ISEL within interruption processing. */
+ /* For this reason, write return of ISEL cannot be performed. */
+ buffer = USB200.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+ buffer |= (uint16_t)(savepipe1 & USB_HOST_BITCURPIPE);
+ USB200.CFIFOSEL = buffer;
+ USB200.PIPESEL = savepipe2;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_interrupt1
+* Description : Execue the USB interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_interrupt1 (void)
+{
+ uint16_t intsts0;
+ uint16_t intsts1;
+ uint16_t intenb0;
+ uint16_t intenb1;
+ uint16_t brdysts;
+ uint16_t nrdysts;
+ uint16_t bempsts;
+ uint16_t brdyenb;
+ uint16_t nrdyenb;
+ uint16_t bempenb;
+ volatile uint16_t dumy_sts;
+
+ intsts0 = USB200.INTSTS0;
+ intsts1 = USB200.INTSTS1;
+ intenb0 = USB200.INTENB0;
+ intenb1 = USB200.INTENB1;
+
+ if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE))
+ {
+ USB200.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG;
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_BCHGE_SHIFT,
+ USB_INTENB1_BCHGE);
+ g_usb0_host_bchg_flag = USB_HOST_YES;
+ }
+ else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE))
+ {
+ USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSACK;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+#else
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+#endif
+ }
+ else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE))
+ {
+ USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN;
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#else
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_NORES;
+#endif
+ }
+ else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH)
+ && ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE))
+ {
+ USB200.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH;
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_DTCHE_SHIFT,
+ USB_INTENB1_DTCHE);
+ g_usb0_host_detach_flag = USB_HOST_YES;
+
+ Userdef_USB_usb0_host_detach();
+
+ usb0_host_UsbDetach2();
+ }
+ else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH)
+ && ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE))
+ {
+ USB200.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH;
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_ATTCHE_SHIFT,
+ USB_INTENB1_ATTCHE);
+ g_usb0_host_attach_flag = USB_HOST_YES;
+
+ Userdef_USB_usb0_host_attach();
+
+ usb0_host_UsbAttach();
+ }
+ else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY)))
+ {
+ brdysts = USB200.BRDYSTS;
+ nrdysts = USB200.NRDYSTS;
+ bempsts = USB200.BEMPSTS;
+ brdyenb = USB200.BRDYENB;
+ nrdyenb = USB200.NRDYENB;
+ bempenb = USB200.BEMPENB;
+
+ if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb))
+ {
+ usb0_host_BRDYInterrupt(brdysts, brdyenb);
+ }
+ else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb))
+ {
+ usb0_host_BEMPInterrupt(bempsts, bempenb);
+ }
+ else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb))
+ {
+ usb0_host_NRDYInterrupt(nrdysts, nrdyenb);
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* Three dummy read for clearing interrupt requests */
+ dumy_sts = USB200.INTSTS0;
+ dumy_sts = USB200.INTSTS1;
+
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_BRDYInterrupt
+* Description : Executes USB BRDY interrupt.
+* Arguments : uint16_t Status ; BRDYSTS Register Value
+* : uint16_t Int_enbl ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_BRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+ uint16_t buffer;
+ volatile uint16_t dumy_sts;
+
+ if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
+ {
+ USB200.BRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
+
+#if(1) /* ohci_wrapp */
+ switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+ switch (buffer)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ USB200.CFIFOCTR = USB_HOST_BITBCLR;
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ default:
+ break;
+ }
+#else
+ switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ case (USB_HOST_MODE_NO_DATA | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case (USB_HOST_MODE_READ | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+
+ switch (buffer)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ USB200.CFIFOCTR = USB_HOST_BITBCLR;
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ default:
+ break;
+ }
+#endif
+ }
+ else
+ {
+ usb0_host_brdy_int(Status, Int_enbl);
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB200.BRDYSTS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_NRDYInterrupt
+* Description : Executes USB NRDY interrupt.
+* Arguments : uint16_t Status ; NRDYSTS Register Value
+* : uint16_t Int_enbl ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_NRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+ uint16_t pid;
+ volatile uint16_t dumy_sts;
+
+ if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
+ {
+ USB200.NRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
+ pid = usb0_host_get_pid(USB_HOST_PIPE0);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+ }
+ else if (pid == USB_HOST_PID_NAK)
+ {
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_NORES;
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+ else
+ {
+ usb0_host_nrdy_int(Status, Int_enbl);
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB200.NRDYSTS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_BEMPInterrupt
+* Description : Executes USB BEMP interrupt.
+* Arguments : uint16_t Status ; BEMPSTS Register Value
+* : uint16_t Int_enbl ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_BEMPInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+ uint16_t buffer;
+ uint16_t pid;
+ volatile uint16_t dumy_sts;
+
+ if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
+ {
+ USB200.BEMPSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
+ pid = usb0_host_get_pid(USB_HOST_PIPE0);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+#if(1) /* ohci_wrapp */
+ switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb0_host_write_buffer(USB_HOST_PIPE0);
+ switch (buffer)
+ {
+ case USB_HOST_WRITING: /* Continue of data write */
+ case USB_HOST_WRITEEND: /* End of data write (zero-length) */
+ break;
+
+ case USB_HOST_WRITESHRT: /* End of data write */
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ default:
+ /* do nothing */
+ break;
+ }
+#else
+ switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_MODE_READ | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb0_host_write_buffer(USB_HOST_PIPE0);
+ switch (buffer)
+ {
+ case USB_HOST_WRITING: /* Continue of data write */
+ case USB_HOST_WRITEEND: /* End of data write (zero-length) */
+ break;
+
+ case USB_HOST_WRITESHRT: /* End of data write */
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+ break;
+
+ default:
+ /* do nothing */
+ break;
+ }
+#endif
+ }
+ }
+ else
+ {
+ usb0_host_bemp_int(Status, Int_enbl);
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB200.BEMPSTS;
+}
+
+/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/host/usb0_host_usbsig.c Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,637 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_usbsig.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_EnableINT_Module(void);
+static void usb0_host_Enable_AttachINT(void);
+static void usb0_host_Disable_AttachINT(void);
+static void usb0_host_Disable_BchgINT(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_InitModule
+* Description : Initializes the USB module in USB host module.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_InitModule (void)
+{
+ uint16_t buf1;
+ uint16_t buf2;
+ uint16_t buf3;
+
+ usb0_host_init_pipe_status();
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM); /* HOST mode */
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_DRPD_SHIFT,
+ USB_SYSCFG_DRPD); /* PORT0 D+, D- setting */
+
+ do
+ {
+ buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb0_host_delay_xms(50);
+ buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb0_host_delay_xms(50);
+ buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+
+ } while ((buf1 != buf2) || (buf1 != buf3));
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE);
+
+ USB200.CFIFOSEL = (uint16_t)(USB_HOST_BITRCNT | USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+ USB200.D0FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+ USB200.D1FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_CheckAttach
+* Description : Returns the USB device connection state.
+* Arguments : none
+* Return Value : uint16_t ; USB_HOST_ATTACH : Attached
+* : ; USB_HOST_DETACH : not Attached
+*******************************************************************************/
+uint16_t usb0_host_CheckAttach (void)
+{
+ uint16_t buf1;
+ uint16_t buf2;
+ uint16_t buf3;
+ uint16_t rhst;
+
+ do
+ {
+ buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb0_host_delay_xms(50);
+ buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb0_host_delay_xms(50);
+ buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+
+ } while ((buf1 != buf2) || (buf1 != buf3));
+
+ rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0,
+ USB_DVSTCTR0_RHST_SHIFT,
+ USB_DVSTCTR0_RHST);
+ if (rhst == USB_HOST_UNDECID)
+ {
+ if (buf1 == USB_HOST_FS_JSTS)
+ {
+ if (g_usb0_host_SupportUsbDeviceSpeed == USB_HOST_HIGH_SPEED)
+ {
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ }
+ return USB_HOST_ATTACH;
+ }
+ else if (buf1 == USB_HOST_LS_JSTS)
+ {
+ /* Low Speed Device */
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ return USB_HOST_ATTACH;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+ else if ((rhst == USB_HOST_HSMODE) || (rhst == USB_HOST_FSMODE))
+ {
+ return USB_HOST_ATTACH;
+ }
+ else if (rhst == USB_HOST_LSMODE)
+ {
+ return USB_HOST_ATTACH;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ return USB_HOST_DETACH;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbAttach
+* Description : Connects the USB device.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_UsbAttach (void)
+{
+ usb0_host_EnableINT_Module();
+ usb0_host_Disable_BchgINT();
+ usb0_host_Disable_AttachINT();
+ usb0_host_Enable_DetachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbDetach
+* Description : Disconnects the USB device.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_UsbDetach (void)
+{
+ uint16_t pipe;
+ uint16_t devadr;
+
+ g_usb0_host_driver_state = USB_HOST_DRV_DETACHED;
+
+ /* Terminate all the pipes in which communications on port */
+ /* are currently carried out */
+ for (pipe = 0; pipe < (USB_HOST_MAX_PIPE_NO + 1); ++pipe)
+ {
+ if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_IDLE)
+ {
+ if (pipe == USB_HOST_PIPE0)
+ {
+ devadr = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+ USB_DCPMAXP_DEVSEL_SHIFT,
+ USB_DCPMAXP_DEVSEL);
+ }
+ else
+ {
+ devadr = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL);
+ }
+
+ if (devadr == g_usb0_host_UsbAddress)
+ {
+ usb0_host_stop_transfer(pipe);
+ }
+
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_IDLE;
+ }
+ }
+
+ g_usb0_host_ConfigNum = 0;
+ g_usb0_host_UsbAddress = 0;
+ g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+ usb0_host_UsbDetach2();
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbDetach2
+* Description : Disconnects the USB device.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_UsbDetach2 (void)
+{
+ usb0_host_Disable_DetachINT();
+ usb0_host_Disable_BchgINT();
+ usb0_host_Enable_AttachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbBusReset
+* Description : Issues the USB bus reset signal.
+* Arguments : none
+* Return Value : uint16_t ; RHST
+*******************************************************************************/
+uint16_t usb0_host_UsbBusReset (void)
+{
+ uint16_t buffer;
+ uint16_t loop;
+
+ RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+ 1,
+ USB_DVSTCTR0_USBRST_SHIFT,
+ USB_DVSTCTR0_USBRST);
+ RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+ 0,
+ USB_DVSTCTR0_UACT_SHIFT,
+ USB_DVSTCTR0_UACT);
+
+ Userdef_USB_usb0_host_delay_xms(50);
+
+ buffer = USB200.DVSTCTR0;
+ buffer &= (uint16_t)(~(USB_HOST_BITRST));
+ buffer |= USB_HOST_BITUACT;
+ USB200.DVSTCTR0 = buffer;
+
+ Userdef_USB_usb0_host_delay_xms(20);
+
+ for (loop = 0, buffer = USB_HOST_HSPROC; loop < 3; ++loop)
+ {
+ buffer = RZA_IO_RegRead_16(&USB200.DVSTCTR0,
+ USB_DVSTCTR0_RHST_SHIFT,
+ USB_DVSTCTR0_RHST);
+ if (buffer == USB_HOST_HSPROC)
+ {
+ Userdef_USB_usb0_host_delay_xms(10);
+ }
+ else
+ {
+ break;
+ }
+ }
+
+ return buffer;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbResume
+* Description : Issues the USB resume signal.
+* Arguments : none
+* Return Value : int32_t ; DEVDRV_SUCCESS
+* : ; DEVDRV_ERROR
+*******************************************************************************/
+int32_t usb0_host_UsbResume (void)
+{
+ uint16_t buf;
+
+ if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) == 0)
+ {
+ /* not SUSPEND */
+ return DEVDRV_ERROR;
+ }
+
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_BCHGE_SHIFT,
+ USB_INTENB1_BCHGE);
+ RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+ 1,
+ USB_DVSTCTR0_RESUME_SHIFT,
+ USB_DVSTCTR0_RESUME);
+ Userdef_USB_usb0_host_delay_xms(20);
+
+ buf = USB200.DVSTCTR0;
+ buf &= (uint16_t)(~(USB_HOST_BITRESUME));
+ buf |= USB_HOST_BITUACT;
+ USB200.DVSTCTR0 = buf;
+
+ g_usb0_host_driver_state &= (uint16_t)~USB_HOST_DRV_SUSPEND;
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbSuspend
+* Description : Issues the USB suspend signal.
+* Arguments : none
+* Return Value : int32_t ; DEVDRV_SUCCESS :not SUSPEND
+* : ; DEVDRV_ERROR :SUSPEND
+*******************************************************************************/
+int32_t usb0_host_UsbSuspend (void)
+{
+ uint16_t buf;
+
+ if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) != 0)
+ {
+ /* SUSPEND */
+ return DEVDRV_ERROR;
+ }
+
+ RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+ 0,
+ USB_DVSTCTR0_UACT_SHIFT,
+ USB_DVSTCTR0_UACT);
+
+ Userdef_USB_usb0_host_delay_xms(5);
+
+ buf = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ if ((buf != USB_HOST_FS_JSTS) && (buf != USB_HOST_LS_JSTS))
+ {
+ usb0_host_UsbDetach();
+ }
+ else
+ {
+ g_usb0_host_driver_state |= USB_HOST_DRV_SUSPEND;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Enable_DetachINT
+* Description : Enables the USB disconnection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Enable_DetachINT (void)
+{
+ USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 1,
+ USB_INTENB1_DTCHE_SHIFT,
+ USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Disable_DetachINT
+* Description : Disables the USB disconnection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Disable_DetachINT (void)
+{
+ USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_DTCHE_SHIFT,
+ USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Enable_AttachINT
+* Description : Enables the USB connection detection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Enable_AttachINT (void)
+{
+ USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 1,
+ USB_INTENB1_ATTCHE_SHIFT,
+ USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Disable_AttachINT
+* Description : Disables the USB connection detection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Disable_AttachINT (void)
+{
+ USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_ATTCHE_SHIFT,
+ USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Disable_BchgINT
+* Description : Disables the USB bus change detection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Disable_BchgINT (void)
+{
+ USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITBCHG));
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_BCHGE_SHIFT,
+ USB_INTENB1_BCHGE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_devadd
+* Description : DEVADDn register is set by specified value
+* Arguments : uint16_t addr : Device address
+* : uint16_t *devadd : Set value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_devadd (uint16_t addr, uint16_t * devadd)
+{
+ uint16_t * ptr;
+ uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning.
+
+ switch (addr)
+ {
+ case USB_HOST_DEVICE_0:
+ ptr = (uint16_t *)&USB200.DEVADD0;
+ break;
+
+ case USB_HOST_DEVICE_1:
+ ptr = (uint16_t *)&USB200.DEVADD1;
+ break;
+
+ case USB_HOST_DEVICE_2:
+ ptr = (uint16_t *)&USB200.DEVADD2;
+ break;
+
+ case USB_HOST_DEVICE_3:
+ ptr = (uint16_t *)&USB200.DEVADD3;
+ break;
+
+ case USB_HOST_DEVICE_4:
+ ptr = (uint16_t *)&USB200.DEVADD4;
+ break;
+
+ case USB_HOST_DEVICE_5:
+ ptr = (uint16_t *)&USB200.DEVADD5;
+ break;
+
+ case USB_HOST_DEVICE_6:
+ ptr = (uint16_t *)&USB200.DEVADD6;
+ break;
+
+ case USB_HOST_DEVICE_7:
+ ptr = (uint16_t *)&USB200.DEVADD7;
+ break;
+
+ case USB_HOST_DEVICE_8:
+ ptr = (uint16_t *)&USB200.DEVADD8;
+ break;
+
+ case USB_HOST_DEVICE_9:
+ ptr = (uint16_t *)&USB200.DEVADD9;
+ break;
+
+ case USB_HOST_DEVICE_10:
+ ptr = (uint16_t *)&USB200.DEVADDA;
+ break;
+
+ default:
+ ret_flag = DEVDRV_FLAG_OFF;
+ break;
+ }
+
+ if (ret_flag == DEVDRV_FLAG_ON)
+ {
+ *ptr = (uint16_t)(*devadd & USB_HOST_DEVADD_MASK);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_devadd
+* Description : DEVADDn register is obtained
+* Arguments : uint16_t addr : Device address
+* : uint16_t *devadd : USB_HOST_DEVADD register value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_get_devadd (uint16_t addr, uint16_t * devadd)
+{
+ uint16_t * ptr;
+ uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning.
+
+ switch (addr)
+ {
+ case USB_HOST_DEVICE_0:
+ ptr = (uint16_t *)&USB200.DEVADD0;
+ break;
+
+ case USB_HOST_DEVICE_1:
+ ptr = (uint16_t *)&USB200.DEVADD1;
+ break;
+
+ case USB_HOST_DEVICE_2:
+ ptr = (uint16_t *)&USB200.DEVADD2;
+ break;
+
+ case USB_HOST_DEVICE_3:
+ ptr = (uint16_t *)&USB200.DEVADD3;
+ break;
+
+ case USB_HOST_DEVICE_4:
+ ptr = (uint16_t *)&USB200.DEVADD4;
+ break;
+
+ case USB_HOST_DEVICE_5:
+ ptr = (uint16_t *)&USB200.DEVADD5;
+ break;
+
+ case USB_HOST_DEVICE_6:
+ ptr = (uint16_t *)&USB200.DEVADD6;
+ break;
+
+ case USB_HOST_DEVICE_7:
+ ptr = (uint16_t *)&USB200.DEVADD7;
+ break;
+
+ case USB_HOST_DEVICE_8:
+ ptr = (uint16_t *)&USB200.DEVADD8;
+ break;
+
+ case USB_HOST_DEVICE_9:
+ ptr = (uint16_t *)&USB200.DEVADD9;
+ break;
+
+ case USB_HOST_DEVICE_10:
+ ptr = (uint16_t *)&USB200.DEVADDA;
+ break;
+
+ default:
+ ret_flag = DEVDRV_FLAG_OFF;
+ break;
+ }
+
+ if (ret_flag == DEVDRV_FLAG_ON)
+ {
+ *devadd = *ptr;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_EnableINT_Module
+* Description : Enables BEMP/NRDY/BRDY interrupt and SIGN/SACK interrupt.
+* : Enables NRDY/BEMP interrupt in the pipe0.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_EnableINT_Module (void)
+{
+ uint16_t buf;
+
+ buf = USB200.INTENB0;
+ buf |= (USB_HOST_BITBEMPE | USB_HOST_BITNRDYE | USB_HOST_BITBRDYE);
+ USB200.INTENB0 = buf;
+
+ buf = USB200.INTENB1;
+ buf |= (USB_HOST_BITSIGNE | USB_HOST_BITSACKE);
+ USB200.INTENB1 = buf;
+
+ usb0_host_enable_nrdy_int(USB_HOST_PIPE0);
+ usb0_host_enable_bemp_int(USB_HOST_PIPE0);
+}
+
+/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_dmacdrv.c Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,698 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_dmacdrv.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+#include "usb0_host_dmacdrv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
+
+/* ==== Request setting information for on-chip peripheral module ==== */
+typedef enum dmac_peri_req_reg_type
+{
+ DMAC_REQ_MID,
+ DMAC_REQ_RID,
+ DMAC_REQ_AM,
+ DMAC_REQ_LVL,
+ DMAC_REQ_REQD
+} dmac_peri_req_reg_type_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+/* ==== Prototype declaration ==== */
+
+/* ==== Global variable ==== */
+/* On-chip peripheral module request setting table */
+static const uint8_t usb0_host_dmac_peri_req_init_table[8][5] =
+{
+ /* MID,RID, AM,LVL,REQD */
+ { 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
+ { 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
+ { 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
+ { 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
+ { 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
+ { 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
+ { 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
+ { 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
+};
+
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 1.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 1 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
+* : : register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous
+* : : transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module
+* : : request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction : Setting value of CHCFG_n register
+* : : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC1_CHCFG_n_DAD_SHIFT,
+ DMAC1_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC1_CHCFG_n_SAD_SHIFT,
+ DMAC1_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->dst_size,
+ DMAC1_CHCFG_n_DDS_SHIFT,
+ DMAC1_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->src_size,
+ DMAC1_CHCFG_n_SDS_SHIFT,
+ DMAC1_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_DMS_SHIFT,
+ DMAC1_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_RSEL_SHIFT,
+ DMAC1_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_SBE_SHIFT,
+ DMAC1_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_DEM_SHIFT,
+ DMAC1_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_REN_SHIFT,
+ DMAC1_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_RSW_SHIFT,
+ DMAC1_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_REN_SHIFT,
+ DMAC1_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_RSW_SHIFT,
+ DMAC1_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_TM_SHIFT,
+ DMAC1_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_SEL_SHIFT,
+ DMAC1_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_HIEN_SHIFT,
+ DMAC1_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_LOEN_SHIFT,
+ DMAC1_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC1_CHCFG_n_AM_SHIFT,
+ DMAC1_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC1_CHCFG_n_LVL_SHIFT,
+ DMAC1_CHCFG_n_LVL);
+ if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC1_CHCFG_n_REQD_SHIFT,
+ DMAC1_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ req_direction,
+ DMAC1_CHCFG_n_REQD_SHIFT,
+ DMAC1_CHCFG_n_REQD);
+ }
+ RZA_IO_RegWrite_32(&DMAC01.DMARS,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC01_DMARS_CH1_RID_SHIFT,
+ DMAC01_DMARS_CH1_RID);
+ RZA_IO_RegWrite_32(&DMAC01.DMARS,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC01_DMARS_CH1_MID_SHIFT,
+ DMAC01_DMARS_CH1_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_Open
+* Description : Enables DMAC channel 1 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb0_host_DMAC1_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_EN_SHIFT,
+ DMAC1_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_TACT_SHIFT,
+ DMAC1_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_SWRST_SHIFT,
+ DMAC1_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n,
+ DMAC1_CHCTRL_n_SWRST_SHIFT,
+ DMAC1_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_SETEN_SHIFT,
+ DMAC1_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_STG_SHIFT,
+ DMAC1_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_Close
+* Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC1_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_CLREN_SHIFT,
+ DMAC1_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_TACT_SHIFT,
+ DMAC1_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_EN_SHIFT,
+ DMAC1_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC1.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 1 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 1 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_SR_SHIFT,
+ DMAC1_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC1.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC1.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC1.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC1.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 2.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 2 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
+* : : register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous
+* : : transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module
+* : : request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction : Setting value of CHCFG_n register
+* : : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC2_CHCFG_n_DAD_SHIFT,
+ DMAC2_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC2_CHCFG_n_SAD_SHIFT,
+ DMAC2_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->dst_size,
+ DMAC2_CHCFG_n_DDS_SHIFT,
+ DMAC2_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->src_size,
+ DMAC2_CHCFG_n_SDS_SHIFT,
+ DMAC2_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_DMS_SHIFT,
+ DMAC2_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_RSEL_SHIFT,
+ DMAC2_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_SBE_SHIFT,
+ DMAC2_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_DEM_SHIFT,
+ DMAC2_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 1,
+ DMAC2_CHCFG_n_REN_SHIFT,
+ DMAC2_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 1,
+ DMAC2_CHCFG_n_RSW_SHIFT,
+ DMAC2_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_REN_SHIFT,
+ DMAC2_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_RSW_SHIFT,
+ DMAC2_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_TM_SHIFT,
+ DMAC2_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 2,
+ DMAC2_CHCFG_n_SEL_SHIFT,
+ DMAC2_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 1,
+ DMAC2_CHCFG_n_HIEN_SHIFT,
+ DMAC2_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_LOEN_SHIFT,
+ DMAC2_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC2_CHCFG_n_AM_SHIFT,
+ DMAC2_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC2_CHCFG_n_LVL_SHIFT,
+ DMAC2_CHCFG_n_LVL);
+ if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC2_CHCFG_n_REQD_SHIFT,
+ DMAC2_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ req_direction,
+ DMAC2_CHCFG_n_REQD_SHIFT,
+ DMAC2_CHCFG_n_REQD);
+ }
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC23_DMARS_CH2_RID_SHIFT,
+ DMAC23_DMARS_CH2_RID);
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC23_DMARS_CH2_MID_SHIFT,
+ DMAC23_DMARS_CH2_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_Open
+* Description : Enables DMAC channel 2 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb0_host_DMAC2_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_EN_SHIFT,
+ DMAC2_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_TACT_SHIFT,
+ DMAC2_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_SWRST_SHIFT,
+ DMAC2_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n,
+ DMAC2_CHCTRL_n_SWRST_SHIFT,
+ DMAC2_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_SETEN_SHIFT,
+ DMAC2_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_STG_SHIFT,
+ DMAC2_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_Close
+* Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC2_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_CLREN_SHIFT,
+ DMAC2_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_TACT_SHIFT,
+ DMAC2_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_EN_SHIFT,
+ DMAC2_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC2.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 2 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 2 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_SR_SHIFT,
+ DMAC2_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC2.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC2.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC2.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC2.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_ohci_wrapp_pipe.c Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,156 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_host_api.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/********************************************************************************************************/
+/* Endpoint Configuration Data Format */
+/********************************************************************************************************/
+/* LINE1: Pipe Window Select Register */
+/* CPU Access PIPE : PIPE1 to PIPE9 [ ### SET ### ] */
+/* LINE2: Pipe Configuration Register */
+/* Transfer Type : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* Buffer Ready interrupt : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* Double Buffer Mode : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */
+/* Continuous Transmit: : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */
+/* Short NAK : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* Transfer Direction : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* Endpoint Number : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* LINE3: Pipe Buffer Configuration Register */
+/* Buffer Size : (uint16_t)((uint16_t)(((x) / 64) - 1) << 10) */
+/* [ ### SET ### ] */
+/* Buffer Top Number : (uint16_t)(x) [ ### SET ### ] */
+/* LINE4: Pipe Maxpacket Size Register */
+/* Max Packet Size : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* LINE5: Pipe Cycle Configuration Register (0x6C) */
+/* ISO Buffer Flush Mode : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* ISO Interval Value : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* LINE6: use FIFO port */
+/* : USB_HOST_CUSE [ ### SET ### ] */
+/* : USB_HOST_D0USE / USB_HOST_D1USE */
+/* : USB_HOST_D0DMA / USB_HOST_D0DMA */
+/* LINE7: use FIFO port Endian : USB_HOST_FIFO_BIG / USB_HOST_FIFO_LITTLE [ #SET# ] */
+/********************************************************************************************************/
+
+/* Device Address 1 */
+USB_HOST_CFG_PIPETBL_t usb0_host_blk_ep_tbl1[ ] =
+{
+ {
+ USB_HOST_PIPE1,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(8),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D0USE
+ },
+
+ {
+ /* Pipe end */
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ }
+};
+
+USB_HOST_CFG_PIPETBL_t usb0_host_int_ep_tbl1[ ] =
+{
+ {
+ USB_HOST_PIPE6,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(40),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ USB_HOST_PIPE7,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(41),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ USB_HOST_PIPE8,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(42),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ USB_HOST_PIPE9,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(43),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ /* Pipe end */
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ }
+};
+
+/* End of File */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/src/userdef/usb0_host_userdef.c Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,770 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_userdef.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "cmsis_os.h"
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "devdrv_usb_host_api.h"
+#include "usb0_host.h"
+#include "MBRZA1H.h" /* INTC Driver Header */
+#include "usb0_host_dmacdrv.h"
+#include "ohci_wrapp_RZ_A1_local.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DUMMY_ACCESS (*(volatile unsigned long *)(OSTM0CNT))
+
+/* #define CACHE_WRITEBACK */
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern int32_t io_cwb(unsigned long start, unsigned long end);
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void usb0_host_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void Userdef_USB_usb0_host_delay_10us_2(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_d0fifo_dmaintid
+* Description : get D0FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D0FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid (void)
+{
+ return DMAINT1_IRQn;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_d1fifo_dmaintid
+* Description : get D1FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D1FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid (void)
+{
+ return DMAINT2_IRQn;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_attach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_attach (void)
+{
+// printf("\n");
+// printf("channel 0 attach device\n");
+// printf("\n");
+ ohciwrapp_loc_Connect(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_detach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_detach (void)
+{
+// printf("\n");
+// printf("channel 0 detach device\n");
+// printf("\n");
+ ohciwrapp_loc_Connect(0);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_1ms
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_1ms (void)
+{
+ osDelay(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_xms
+* Description : Wait for the software in the period of time specified by the
+* : argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t msec ; Wait Time (msec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_xms (uint32_t msec)
+{
+ osDelay(msec);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_10us
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t usec ; Wait Time(x 10usec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_10us (uint32_t usec)
+{
+ volatile int i;
+
+ /* Wait 10us (Please change for your MCU) */
+ for (i = 0; i < usec; ++i)
+ {
+ Userdef_USB_usb0_host_delay_10us_2();
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_10us_2
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+static void Userdef_USB_usb0_host_delay_10us_2 (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 1us (Please change for your MCU) */
+ for (i = 0; i < 14; ++i)
+ {
+ tmp = DUMMY_ACCESS;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_500ns
+* Description : Wait for software for 500ns.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_500ns (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 500ns (Please change for your MCU) */
+ /* Wait 500ns I clock 266MHz */
+ tmp = DUMMY_ACCESS;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_start_dma
+* Description : Enables DMA transfer on the information specified by the argument.
+* : Set DMAC register by this function to enable DMA transfer.
+* : After executing this function, USB module is set to start DMA
+* : transfer. DMA transfer should not wait for DMA transfer complete.
+* Arguments : USB_HOST_DMA_t *dma : DMA parameter
+* : typedef struct{
+* : uint32_t fifo; FIFO for using
+* : uint32_t buffer; Start address of transfer source/destination
+* : uint32_t bytes; Transfer size(Byte)
+* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer)
+* : uint32_t size; DMA transfer size
+* : } USB_HOST_DMA_t;
+* : uint16_t dfacc ; 0 : cycle steal mode
+* : 1 : 16byte continuous mode
+* : 2 : 32byte continuous mode
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_start_dma (USB_HOST_DMA_t * dma, uint16_t dfacc)
+{
+ uint32_t trncount;
+ uint32_t src;
+ uint32_t dst;
+ uint32_t size;
+ uint32_t dir;
+#ifdef CACHE_WRITEBACK
+ uint32_t ptr;
+#endif
+
+ trncount = dma->bytes;
+ dir = dma->dir;
+
+ if (dir == USB_HOST_FIFO2BUF)
+ {
+ /* DxFIFO determination */
+ dst = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ src += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ src += 3; /* byte access */
+ }
+#endif
+ }
+ else
+ {
+ /* DxFIFO determination */
+ src = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ dst += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ dst += 3; /* byte access */
+ }
+#endif
+ }
+
+#ifdef CACHE_WRITEBACK
+ ptr = (uint32_t)dma->buffer;
+ if ((ptr & 0x20000000ul) == 0)
+ {
+ io_cwb((uint32_t)ptr,(uint32_t)(ptr)+trncount);
+ }
+#endif
+
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ usb0_host_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+ else
+ {
+ usb0_host_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_dmac0
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_HOST_FIFO2BUF)
+ {
+ request_factor = DMAC_REQ_USB0_DMA0_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_HOST_BUF2FIFO)
+ {
+ request_factor = DMAC_REQ_USB0_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb0_host_DMAC1_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC1_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb0_host_DMAC1_Open(DMAC_REQ_MODE_PERI);
+
+ if (ret != 0)
+ {
+// printf("DMAC1 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_dmac1
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_HOST_FIFO2BUF)
+ {
+ request_factor =DMAC_REQ_USB0_DMA1_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_HOST_BUF2FIFO)
+ {
+ request_factor =DMAC_REQ_USB0_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb0_host_DMAC2_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC2_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb0_host_DMAC2_Open(DMAC_REQ_MODE_PERI);
+
+ if (ret != 0)
+ {
+// printf("DMAC2 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_stop_dma0
+* Description : Disables DMA transfer.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+* Notice : This function should be executed to DMAC executed at the time
+* : of specification of D0_FIF0_DMA in dma->fifo.
+*******************************************************************************/
+uint32_t Userdef_USB_usb0_host_stop_dma0 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb0_host_DMAC1_Close(&remain);
+
+ return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_stop_dma1
+* Description : Disables DMA transfer.
+* : This function should be executed to DMAC executed at the time
+* : of specification of D1_FIF0_DMA in dma->fifo.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb0_host_stop_dma1 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb0_host_DMAC2_Close(&remain);
+
+ return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_notice
+* Description : Notice of USER
+* Arguments : const char *format
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_notice (const char * format)
+{
+// printf(format);
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_user_rdy
+* Description : This function notify a user and wait for trigger
+* Arguments : const char *format
+* : uint16_t data
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_user_rdy (const char * format, uint16_t data)
+{
+// printf(format, data);
+ getchar();
+
+ return;
+}
+
+/* End of File */
--- a/USBHost/USBHALHost.cpp Mon Aug 18 13:45:26 2014 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,322 +0,0 @@
-/* mbed USBHost Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "mbed.h"
-#include "USBHALHost.h"
-#include "dbg.h"
-
-// bits of the USB/OTG clock control register
-#define HOST_CLK_EN (1<<0)
-#define DEV_CLK_EN (1<<1)
-#define PORTSEL_CLK_EN (1<<3)
-#define AHB_CLK_EN (1<<4)
-
-// bits of the USB/OTG clock status register
-#define HOST_CLK_ON (1<<0)
-#define DEV_CLK_ON (1<<1)
-#define PORTSEL_CLK_ON (1<<3)
-#define AHB_CLK_ON (1<<4)
-
-// we need host clock, OTG/portsel clock and AHB clock
-#define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
-
-#define HCCA_SIZE sizeof(HCCA)
-#define ED_SIZE sizeof(HCED)
-#define TD_SIZE sizeof(HCTD)
-
-#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
-
-static volatile uint8_t usb_buf[TOTAL_SIZE] __attribute((section("AHBSRAM1"),aligned(256))); //256 bytes aligned!
-
-USBHALHost * USBHALHost::instHost;
-
-USBHALHost::USBHALHost() {
- instHost = this;
- memInit();
- memset((void*)usb_hcca, 0, HCCA_SIZE);
- for (int i = 0; i < MAX_ENDPOINT; i++) {
- edBufAlloc[i] = false;
- }
- for (int i = 0; i < MAX_TD; i++) {
- tdBufAlloc[i] = false;
- }
-}
-
-void USBHALHost::init() {
- NVIC_DisableIRQ(USB_IRQn);
-
- //Cut power
- LPC_SC->PCONP &= ~(1UL<<31);
- wait_ms(100);
-
- // turn on power for USB
- LPC_SC->PCONP |= (1UL<<31);
-
- // Enable USB host clock, port selection and AHB clock
- LPC_USB->USBClkCtrl |= CLOCK_MASK;
-
- // Wait for clocks to become available
- while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK);
-
- // it seems the bits[0:1] mean the following
- // 0: U1=device, U2=host
- // 1: U1=host, U2=host
- // 2: reserved
- // 3: U1=host, U2=device
- // NB: this register is only available if OTG clock (aka "port select") is enabled!!
- // since we don't care about port 2, set just bit 0 to 1 (U1=host)
- LPC_USB->OTGStCtrl |= 1;
-
- // now that we've configured the ports, we can turn off the portsel clock
- LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
-
- // configure USB D+/D- pins
- // P0[29] = USB_D+, 01
- // P0[30] = USB_D-, 01
- LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
- LPC_PINCON->PINSEL1 |= ((1<<26) | (1<<28));
-
- LPC_USB->HcControl = 0; // HARDWARE RESET
- LPC_USB->HcControlHeadED = 0; // Initialize Control list head to Zero
- LPC_USB->HcBulkHeadED = 0; // Initialize Bulk list head to Zero
-
- // Wait 100 ms before apply reset
- wait_ms(100);
-
- // software reset
- LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
-
- // Write Fm Interval and Largest Data Packet Counter
- LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL;
- LPC_USB->HcPeriodicStart = FI * 90 / 100;
-
- // Put HC in operational state
- LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
- // Set Global Power
- LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC;
-
- LPC_USB->HcHCCA = (uint32_t)(usb_hcca);
-
- // Clear Interrrupt Status
- LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus;
-
- LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
-
- // Enable the USB Interrupt
- NVIC_SetVector(USB_IRQn, (uint32_t)(_usbisr));
- LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
- LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
-
- NVIC_EnableIRQ(USB_IRQn);
-
- // Check for any connected devices
- if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
- //Device connected
- wait_ms(150);
- USB_DBG("Device connected (%08x)\n\r", LPC_USB->HcRhPortStatus1);
- deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
- }
-}
-
-uint32_t USBHALHost::controlHeadED() {
- return LPC_USB->HcControlHeadED;
-}
-
-uint32_t USBHALHost::bulkHeadED() {
- return LPC_USB->HcBulkHeadED;
-}
-
-uint32_t USBHALHost::interruptHeadED() {
- return usb_hcca->IntTable[0];
-}
-
-void USBHALHost::updateBulkHeadED(uint32_t addr) {
- LPC_USB->HcBulkHeadED = addr;
-}
-
-
-void USBHALHost::updateControlHeadED(uint32_t addr) {
- LPC_USB->HcControlHeadED = addr;
-}
-
-void USBHALHost::updateInterruptHeadED(uint32_t addr) {
- usb_hcca->IntTable[0] = addr;
-}
-
-
-void USBHALHost::enableList(ENDPOINT_TYPE type) {
- switch(type) {
- case CONTROL_ENDPOINT:
- LPC_USB->HcCommandStatus = OR_CMD_STATUS_CLF;
- LPC_USB->HcControl |= OR_CONTROL_CLE;
- break;
- case ISOCHRONOUS_ENDPOINT:
- break;
- case BULK_ENDPOINT:
- LPC_USB->HcCommandStatus = OR_CMD_STATUS_BLF;
- LPC_USB->HcControl |= OR_CONTROL_BLE;
- break;
- case INTERRUPT_ENDPOINT:
- LPC_USB->HcControl |= OR_CONTROL_PLE;
- break;
- }
-}
-
-
-bool USBHALHost::disableList(ENDPOINT_TYPE type) {
- switch(type) {
- case CONTROL_ENDPOINT:
- if(LPC_USB->HcControl & OR_CONTROL_CLE) {
- LPC_USB->HcControl &= ~OR_CONTROL_CLE;
- return true;
- }
- return false;
- case ISOCHRONOUS_ENDPOINT:
- return false;
- case BULK_ENDPOINT:
- if(LPC_USB->HcControl & OR_CONTROL_BLE){
- LPC_USB->HcControl &= ~OR_CONTROL_BLE;
- return true;
- }
- return false;
- case INTERRUPT_ENDPOINT:
- if(LPC_USB->HcControl & OR_CONTROL_PLE) {
- LPC_USB->HcControl &= ~OR_CONTROL_PLE;
- return true;
- }
- return false;
- }
- return false;
-}
-
-
-void USBHALHost::memInit() {
- usb_hcca = (volatile HCCA *)usb_buf;
- usb_edBuf = usb_buf + HCCA_SIZE;
- usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
-}
-
-volatile uint8_t * USBHALHost::getED() {
- for (int i = 0; i < MAX_ENDPOINT; i++) {
- if ( !edBufAlloc[i] ) {
- edBufAlloc[i] = true;
- return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
- }
- }
- perror("Could not allocate ED\r\n");
- return NULL; //Could not alloc ED
-}
-
-volatile uint8_t * USBHALHost::getTD() {
- int i;
- for (i = 0; i < MAX_TD; i++) {
- if ( !tdBufAlloc[i] ) {
- tdBufAlloc[i] = true;
- return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
- }
- }
- perror("Could not allocate TD\r\n");
- return NULL; //Could not alloc TD
-}
-
-
-void USBHALHost::freeED(volatile uint8_t * ed) {
- int i;
- i = (ed - usb_edBuf) / ED_SIZE;
- edBufAlloc[i] = false;
-}
-
-void USBHALHost::freeTD(volatile uint8_t * td) {
- int i;
- i = (td - usb_tdBuf) / TD_SIZE;
- tdBufAlloc[i] = false;
-}
-
-
-void USBHALHost::resetRootHub() {
- // Initiate port reset
- LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS;
-
- while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS);
-
- // ...and clear port reset signal
- LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
-}
-
-
-void USBHALHost::_usbisr(void) {
- if (instHost) {
- instHost->UsbIrqhandler();
- }
-}
-
-void USBHALHost::UsbIrqhandler() {
- if( LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable ) //Is there something to actually process?
- {
-
- uint32_t int_status = LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable;
-
- // Root hub status change interrupt
- if (int_status & OR_INTR_STATUS_RHSC) {
- if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
- if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
- // When DRWE is on, Connect Status Change
- // means a remote wakeup event.
- } else {
-
- //Root device connected
- if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
-
- // wait 150ms to avoid bounce
- wait_ms(150);
-
- //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
- deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
- }
-
- //Root device disconnected
- else {
-
- if (!(int_status & OR_INTR_STATUS_WDH)) {
- usb_hcca->DoneHead = 0;
- }
-
- // wait 200ms to avoid bounce
- wait_ms(200);
-
- deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
-
- if (int_status & OR_INTR_STATUS_WDH) {
- usb_hcca->DoneHead = 0;
- LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
- }
- }
- }
- LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
- }
- if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
- LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
- }
- LPC_USB->HcInterruptStatus = OR_INTR_STATUS_RHSC;
- }
-
- // Writeback Done Head interrupt
- if (int_status & OR_INTR_STATUS_WDH) {
- transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
- LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
- }
- }
-}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/USBHALHost_LPC17.cpp Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,325 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(TARGET_LPC1768)
+
+#include "mbed.h"
+#include "USBHALHost.h"
+#include "dbg.h"
+
+// bits of the USB/OTG clock control register
+#define HOST_CLK_EN (1<<0)
+#define DEV_CLK_EN (1<<1)
+#define PORTSEL_CLK_EN (1<<3)
+#define AHB_CLK_EN (1<<4)
+
+// bits of the USB/OTG clock status register
+#define HOST_CLK_ON (1<<0)
+#define DEV_CLK_ON (1<<1)
+#define PORTSEL_CLK_ON (1<<3)
+#define AHB_CLK_ON (1<<4)
+
+// we need host clock, OTG/portsel clock and AHB clock
+#define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
+
+#define HCCA_SIZE sizeof(HCCA)
+#define ED_SIZE sizeof(HCED)
+#define TD_SIZE sizeof(HCTD)
+
+#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
+
+static volatile uint8_t usb_buf[TOTAL_SIZE] __attribute((section("AHBSRAM1"),aligned(256))); //256 bytes aligned!
+
+USBHALHost * USBHALHost::instHost;
+
+USBHALHost::USBHALHost() {
+ instHost = this;
+ memInit();
+ memset((void*)usb_hcca, 0, HCCA_SIZE);
+ for (int i = 0; i < MAX_ENDPOINT; i++) {
+ edBufAlloc[i] = false;
+ }
+ for (int i = 0; i < MAX_TD; i++) {
+ tdBufAlloc[i] = false;
+ }
+}
+
+void USBHALHost::init() {
+ NVIC_DisableIRQ(USB_IRQn);
+
+ //Cut power
+ LPC_SC->PCONP &= ~(1UL<<31);
+ wait_ms(100);
+
+ // turn on power for USB
+ LPC_SC->PCONP |= (1UL<<31);
+
+ // Enable USB host clock, port selection and AHB clock
+ LPC_USB->USBClkCtrl |= CLOCK_MASK;
+
+ // Wait for clocks to become available
+ while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK);
+
+ // it seems the bits[0:1] mean the following
+ // 0: U1=device, U2=host
+ // 1: U1=host, U2=host
+ // 2: reserved
+ // 3: U1=host, U2=device
+ // NB: this register is only available if OTG clock (aka "port select") is enabled!!
+ // since we don't care about port 2, set just bit 0 to 1 (U1=host)
+ LPC_USB->OTGStCtrl |= 1;
+
+ // now that we've configured the ports, we can turn off the portsel clock
+ LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
+
+ // configure USB D+/D- pins
+ // P0[29] = USB_D+, 01
+ // P0[30] = USB_D-, 01
+ LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
+ LPC_PINCON->PINSEL1 |= ((1<<26) | (1<<28));
+
+ LPC_USB->HcControl = 0; // HARDWARE RESET
+ LPC_USB->HcControlHeadED = 0; // Initialize Control list head to Zero
+ LPC_USB->HcBulkHeadED = 0; // Initialize Bulk list head to Zero
+
+ // Wait 100 ms before apply reset
+ wait_ms(100);
+
+ // software reset
+ LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
+
+ // Write Fm Interval and Largest Data Packet Counter
+ LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL;
+ LPC_USB->HcPeriodicStart = FI * 90 / 100;
+
+ // Put HC in operational state
+ LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
+ // Set Global Power
+ LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC;
+
+ LPC_USB->HcHCCA = (uint32_t)(usb_hcca);
+
+ // Clear Interrrupt Status
+ LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus;
+
+ LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
+
+ // Enable the USB Interrupt
+ NVIC_SetVector(USB_IRQn, (uint32_t)(_usbisr));
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+
+ NVIC_EnableIRQ(USB_IRQn);
+
+ // Check for any connected devices
+ if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
+ //Device connected
+ wait_ms(150);
+ USB_DBG("Device connected (%08x)\n\r", LPC_USB->HcRhPortStatus1);
+ deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
+ }
+}
+
+uint32_t USBHALHost::controlHeadED() {
+ return LPC_USB->HcControlHeadED;
+}
+
+uint32_t USBHALHost::bulkHeadED() {
+ return LPC_USB->HcBulkHeadED;
+}
+
+uint32_t USBHALHost::interruptHeadED() {
+ return usb_hcca->IntTable[0];
+}
+
+void USBHALHost::updateBulkHeadED(uint32_t addr) {
+ LPC_USB->HcBulkHeadED = addr;
+}
+
+
+void USBHALHost::updateControlHeadED(uint32_t addr) {
+ LPC_USB->HcControlHeadED = addr;
+}
+
+void USBHALHost::updateInterruptHeadED(uint32_t addr) {
+ usb_hcca->IntTable[0] = addr;
+}
+
+
+void USBHALHost::enableList(ENDPOINT_TYPE type) {
+ switch(type) {
+ case CONTROL_ENDPOINT:
+ LPC_USB->HcCommandStatus = OR_CMD_STATUS_CLF;
+ LPC_USB->HcControl |= OR_CONTROL_CLE;
+ break;
+ case ISOCHRONOUS_ENDPOINT:
+ break;
+ case BULK_ENDPOINT:
+ LPC_USB->HcCommandStatus = OR_CMD_STATUS_BLF;
+ LPC_USB->HcControl |= OR_CONTROL_BLE;
+ break;
+ case INTERRUPT_ENDPOINT:
+ LPC_USB->HcControl |= OR_CONTROL_PLE;
+ break;
+ }
+}
+
+
+bool USBHALHost::disableList(ENDPOINT_TYPE type) {
+ switch(type) {
+ case CONTROL_ENDPOINT:
+ if(LPC_USB->HcControl & OR_CONTROL_CLE) {
+ LPC_USB->HcControl &= ~OR_CONTROL_CLE;
+ return true;
+ }
+ return false;
+ case ISOCHRONOUS_ENDPOINT:
+ return false;
+ case BULK_ENDPOINT:
+ if(LPC_USB->HcControl & OR_CONTROL_BLE){
+ LPC_USB->HcControl &= ~OR_CONTROL_BLE;
+ return true;
+ }
+ return false;
+ case INTERRUPT_ENDPOINT:
+ if(LPC_USB->HcControl & OR_CONTROL_PLE) {
+ LPC_USB->HcControl &= ~OR_CONTROL_PLE;
+ return true;
+ }
+ return false;
+ }
+ return false;
+}
+
+
+void USBHALHost::memInit() {
+ usb_hcca = (volatile HCCA *)usb_buf;
+ usb_edBuf = usb_buf + HCCA_SIZE;
+ usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
+}
+
+volatile uint8_t * USBHALHost::getED() {
+ for (int i = 0; i < MAX_ENDPOINT; i++) {
+ if ( !edBufAlloc[i] ) {
+ edBufAlloc[i] = true;
+ return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
+ }
+ }
+ perror("Could not allocate ED\r\n");
+ return NULL; //Could not alloc ED
+}
+
+volatile uint8_t * USBHALHost::getTD() {
+ int i;
+ for (i = 0; i < MAX_TD; i++) {
+ if ( !tdBufAlloc[i] ) {
+ tdBufAlloc[i] = true;
+ return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
+ }
+ }
+ perror("Could not allocate TD\r\n");
+ return NULL; //Could not alloc TD
+}
+
+
+void USBHALHost::freeED(volatile uint8_t * ed) {
+ int i;
+ i = (ed - usb_edBuf) / ED_SIZE;
+ edBufAlloc[i] = false;
+}
+
+void USBHALHost::freeTD(volatile uint8_t * td) {
+ int i;
+ i = (td - usb_tdBuf) / TD_SIZE;
+ tdBufAlloc[i] = false;
+}
+
+
+void USBHALHost::resetRootHub() {
+ // Initiate port reset
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS;
+
+ while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS);
+
+ // ...and clear port reset signal
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+}
+
+
+void USBHALHost::_usbisr(void) {
+ if (instHost) {
+ instHost->UsbIrqhandler();
+ }
+}
+
+void USBHALHost::UsbIrqhandler() {
+ if( LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable ) //Is there something to actually process?
+ {
+
+ uint32_t int_status = LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable;
+
+ // Root hub status change interrupt
+ if (int_status & OR_INTR_STATUS_RHSC) {
+ if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
+ if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
+ // When DRWE is on, Connect Status Change
+ // means a remote wakeup event.
+ } else {
+
+ //Root device connected
+ if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
+
+ // wait 150ms to avoid bounce
+ wait_ms(150);
+
+ //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
+ deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
+ }
+
+ //Root device disconnected
+ else {
+
+ if (!(int_status & OR_INTR_STATUS_WDH)) {
+ usb_hcca->DoneHead = 0;
+ }
+
+ // wait 200ms to avoid bounce
+ wait_ms(200);
+
+ deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
+
+ if (int_status & OR_INTR_STATUS_WDH) {
+ usb_hcca->DoneHead = 0;
+ LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
+ }
+ }
+ }
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
+ }
+ if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+ }
+ LPC_USB->HcInterruptStatus = OR_INTR_STATUS_RHSC;
+ }
+
+ // Writeback Done Head interrupt
+ if (int_status & OR_INTR_STATUS_WDH) {
+ transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
+ LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
+ }
+ }
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/USBHost/USBHALHost_RZ_A1.cpp Mon Jan 19 14:30:37 2015 +0000
@@ -0,0 +1,293 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(TARGET_RZ_A1H)
+
+#include "mbed.h"
+#include "USBHALHost.h"
+#include "dbg.h"
+
+#include "ohci_wrapp_RZ_A1.h"
+
+
+#define HCCA_SIZE sizeof(HCCA)
+#define ED_SIZE sizeof(HCED)
+#define TD_SIZE sizeof(HCTD)
+
+#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
+#define ALIGNE_MSK (0x0000000F)
+
+static volatile uint8_t usb_buf[TOTAL_SIZE + ALIGNE_MSK]; //16 bytes aligned!
+
+USBHALHost * USBHALHost::instHost;
+
+USBHALHost::USBHALHost() {
+ instHost = this;
+ memInit();
+ memset((void*)usb_hcca, 0, HCCA_SIZE);
+ for (int i = 0; i < MAX_ENDPOINT; i++) {
+ edBufAlloc[i] = false;
+ }
+ for (int i = 0; i < MAX_TD; i++) {
+ tdBufAlloc[i] = false;
+ }
+}
+
+void USBHALHost::init() {
+ ohciwrapp_init(&_usbisr, 1);
+
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, 1); // HARDWARE RESET
+ ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, 0); // Initialize Control list head to Zero
+ ohciwrapp_reg_w(OHCI_REG_BULKHEADED, 0); // Initialize Bulk list head to Zero
+
+ // Wait 100 ms before apply reset
+ wait_ms(100);
+
+ // software reset
+ ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_HCR);
+
+ // Write Fm Interval and Largest Data Packet Counter
+ ohciwrapp_reg_w(OHCI_REG_FMINTERVAL, DEFAULT_FMINTERVAL);
+ ohciwrapp_reg_w(OHCI_REG_PERIODICSTART, FI * 90 / 100);
+
+ // Put HC in operational state
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, (ohciwrapp_reg_r(OHCI_REG_CONTROL) & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER);
+ // Set Global Power
+ ohciwrapp_reg_w(OHCI_REG_RHSTATUS, OR_RH_STATUS_LPSC);
+
+ ohciwrapp_reg_w(OHCI_REG_HCCA, (uint32_t)(usb_hcca));
+
+ // Clear Interrrupt Status
+ ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS));
+
+ ohciwrapp_reg_w(OHCI_REG_INTERRUPTENABLE, OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC);
+
+ // Enable the USB Interrupt
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC);
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
+
+ // Check for any connected devices
+ if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) {
+ //Device connected
+ wait_ms(150);
+ USB_DBG("Device connected (%08x)\n\r", ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1));
+ deviceConnected(0, 1, ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA);
+ }
+}
+
+uint32_t USBHALHost::controlHeadED() {
+ return ohciwrapp_reg_r(OHCI_REG_CONTROLHEADED);
+}
+
+uint32_t USBHALHost::bulkHeadED() {
+ return ohciwrapp_reg_r(OHCI_REG_BULKHEADED);
+}
+
+uint32_t USBHALHost::interruptHeadED() {
+ return usb_hcca->IntTable[0];
+}
+
+void USBHALHost::updateBulkHeadED(uint32_t addr) {
+ ohciwrapp_reg_w(OHCI_REG_BULKHEADED, addr);
+}
+
+
+void USBHALHost::updateControlHeadED(uint32_t addr) {
+ ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, addr);
+}
+
+void USBHALHost::updateInterruptHeadED(uint32_t addr) {
+ usb_hcca->IntTable[0] = addr;
+}
+
+
+void USBHALHost::enableList(ENDPOINT_TYPE type) {
+ uint32_t wk_data;
+
+ switch(type) {
+ case CONTROL_ENDPOINT:
+ ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_CLF);
+ wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_CLE);
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ break;
+ case ISOCHRONOUS_ENDPOINT:
+ break;
+ case BULK_ENDPOINT:
+ ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_BLF);
+ wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_BLE);
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ break;
+ case INTERRUPT_ENDPOINT:
+ wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_PLE);
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ break;
+ }
+}
+
+
+bool USBHALHost::disableList(ENDPOINT_TYPE type) {
+ uint32_t wk_data;
+
+ switch(type) {
+ case CONTROL_ENDPOINT:
+ wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
+ if(wk_data & OR_CONTROL_CLE) {
+ wk_data &= ~OR_CONTROL_CLE;
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ return true;
+ }
+ return false;
+ case ISOCHRONOUS_ENDPOINT:
+ return false;
+ case BULK_ENDPOINT:
+ wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
+ if(wk_data & OR_CONTROL_BLE) {
+ wk_data &= ~OR_CONTROL_BLE;
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ return true;
+ }
+ return false;
+ case INTERRUPT_ENDPOINT:
+ wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
+ if(wk_data & OR_CONTROL_PLE) {
+ wk_data &= ~OR_CONTROL_PLE;
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ return true;
+ }
+ return false;
+ }
+ return false;
+}
+
+
+void USBHALHost::memInit() {
+ volatile uint8_t *p_wk_buf = (uint8_t *)(((uint32_t)usb_buf + ALIGNE_MSK) & ~ALIGNE_MSK);
+
+ usb_hcca = (volatile HCCA *)p_wk_buf;
+ usb_edBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE);
+ usb_tdBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE));
+}
+
+volatile uint8_t * USBHALHost::getED() {
+ for (int i = 0; i < MAX_ENDPOINT; i++) {
+ if ( !edBufAlloc[i] ) {
+ edBufAlloc[i] = true;
+ return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
+ }
+ }
+ perror("Could not allocate ED\r\n");
+ return NULL; //Could not alloc ED
+}
+
+volatile uint8_t * USBHALHost::getTD() {
+ int i;
+ for (i = 0; i < MAX_TD; i++) {
+ if ( !tdBufAlloc[i] ) {
+ tdBufAlloc[i] = true;
+ return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
+ }
+ }
+ perror("Could not allocate TD\r\n");
+ return NULL; //Could not alloc TD
+}
+
+
+void USBHALHost::freeED(volatile uint8_t * ed) {
+ int i;
+ i = (ed - usb_edBuf) / ED_SIZE;
+ edBufAlloc[i] = false;
+}
+
+void USBHALHost::freeTD(volatile uint8_t * td) {
+ int i;
+ i = (td - usb_tdBuf) / TD_SIZE;
+ tdBufAlloc[i] = false;
+}
+
+
+void USBHALHost::resetRootHub() {
+ // Initiate port reset
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRS);
+
+ while (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRS);
+
+ // ...and clear port reset signal
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
+}
+
+
+void USBHALHost::_usbisr(void) {
+ if (instHost) {
+ instHost->UsbIrqhandler();
+ }
+}
+
+void USBHALHost::UsbIrqhandler() {
+ uint32_t int_status = ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS) & ohciwrapp_reg_r(OHCI_REG_INTERRUPTENABLE);
+
+ if (int_status != 0) { //Is there something to actually process?
+ // Root hub status change interrupt
+ if (int_status & OR_INTR_STATUS_RHSC) {
+ if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CSC) {
+ if (ohciwrapp_reg_r(OHCI_REG_RHSTATUS) & OR_RH_STATUS_DRWE) {
+ // When DRWE is on, Connect Status Change
+ // means a remote wakeup event.
+ } else {
+
+ //Root device connected
+ if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) {
+
+ // wait 150ms to avoid bounce
+ wait_ms(150);
+
+ //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
+ deviceConnected(0, 1, ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA);
+ }
+
+ //Root device disconnected
+ else {
+
+ if (!(int_status & OR_INTR_STATUS_WDH)) {
+ usb_hcca->DoneHead = 0;
+ }
+
+ // wait 200ms to avoid bounce
+ wait_ms(200);
+
+ deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
+
+ if (int_status & OR_INTR_STATUS_WDH) {
+ usb_hcca->DoneHead = 0;
+ ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH);
+ }
+ }
+ }
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC);
+ }
+ if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRSC) {
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
+ }
+ ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_RHSC);
+ }
+
+ // Writeback Done Head interrupt
+ if (int_status & OR_INTR_STATUS_WDH) {
+ transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
+ ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH);
+ }
+ }
+}
+#endif
--- a/USBHostHID/USBHostMouse.cpp Mon Aug 18 13:45:26 2014 +0100
+++ b/USBHostHID/USBHostMouse.cpp Mon Jan 19 14:30:37 2015 +0000
@@ -47,6 +47,7 @@
}
bool USBHostMouse::connect() {
+ int len_listen;
if (dev_connected) {
return true;
@@ -69,7 +70,11 @@
host->registerDriver(dev, mouse_intf, this, &USBHostMouse::init);
int_in->attach(this, &USBHostMouse::rxHandler);
- host->interruptRead(dev, int_in, report, int_in->getSize(), false);
+ len_listen = int_in->getSize();
+ if (len_listen > sizeof(report)) {
+ len_listen = sizeof(report);
+ }
+ host->interruptRead(dev, int_in, report, len_listen, false);
dev_connected = true;
return true;
@@ -109,6 +114,10 @@
y = report[2];
z = report[3];
+ if (len_listen > sizeof(report)) {
+ len_listen = sizeof(report);
+ }
+
if (dev)
host->interruptRead(dev, int_in, report, len_listen, false);
}
--- a/USBHostHub/USBHostHub.cpp Mon Aug 18 13:45:26 2014 +0100
+++ b/USBHostHub/USBHostHub.cpp Mon Jan 19 14:30:37 2015 +0000
@@ -222,6 +222,9 @@
uint32_t status;
USB_DBG("reset port %d on hub: %p [this: %p]", port, dev, this)
setPortFeature(PORT_RESET_FEATURE, port);
+#if defined(TARGET_RZ_A1H)
+ Thread::wait(50); // Reset release waiting for Hi-Speed check.
+#endif
while(1) {
status = getPortStatus(port);
if (status & (PORT_ENABLE | PORT_RESET))
--- a/USBHostMSD/USBHostMSD.cpp Mon Aug 18 13:45:26 2014 +0100
+++ b/USBHostMSD/USBHostMSD.cpp Mon Jan 19 14:30:37 2015 +0000
@@ -303,7 +303,7 @@
int USBHostMSD::disk_initialize() {
USB_DBG("FILESYSTEM: init");
- U16 i, timeout = 10;
+ uint16_t i, timeout = 10;
getMaxLun();
--- a/USBHostSerial/USBHostSerial.cpp Mon Aug 18 13:45:26 2014 +0100
+++ b/USBHostSerial/USBHostSerial.cpp Mon Jan 19 14:30:37 2015 +0000
@@ -71,6 +71,7 @@
{
USBHostSerialPort::connect(host,d,port_intf,bulk_in, bulk_out);
dev = d;
+ dev_connected = true;
}
}
}
@@ -171,6 +172,7 @@
{
ports[port]->connect(host,d,port_intf[port],bulk_in, bulk_out);
dev = d;
+ dev_connected = true;
}
}
}
@@ -242,7 +244,7 @@
USB_INFO("New Serial device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, serial_intf);
dev->setName("Serial", serial_intf);
host->registerDriver(dev, serial_intf, this, &USBHostSerialPort::init);
- //baud(9600);
+ baud(9600);
size_bulk_in = bulk_in->getSize();
size_bulk_out = bulk_out->getSize();
bulk_in->attach(this, &USBHostSerialPort::rxHandler);
