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dma.cpp
00001 /***************************************************************************** 00002 * dma.c: DMA module file for NXP LPC17xx Family Microprocessors 00003 * 00004 * Copyright(C) 2009, NXP Semiconductor 00005 * All rights reserved. 00006 * 00007 * History 00008 * 2009.05.26 ver 1.00 Prelimnary version, first Release 00009 * 00010 ******************************************************************************/ 00011 #include "mbed.h" 00012 #include "type.h" 00013 #include "i2s.h" 00014 #include "dma.h" 00015 00016 #if I2S_DMA_ENABLED 00017 volatile uint32_t DMATCCount = 0; 00018 volatile uint32_t DMAErrCount = 0; 00019 volatile uint32_t I2SDMA0Done = 0; 00020 volatile uint32_t I2SDMA1Done = 0; 00021 00022 /****************************************************************************** 00023 ** Function name: DMA_IRQHandler 00024 ** 00025 ** Descriptions: DMA interrupt handler 00026 ** 00027 ** parameters: None 00028 ** Returned value: None 00029 ** 00030 ******************************************************************************/ 00031 void DMA_IRQHandler(void) 00032 { 00033 uint32_t regVal; 00034 00035 regVal = LPC_GPDMA->DMACIntTCStat; 00036 if ( regVal ) 00037 { 00038 DMATCCount++; 00039 LPC_GPDMA->DMACIntTCClear |= regVal; 00040 if ( regVal & 0x01 ) 00041 { 00042 I2SDMA0Done = 1; 00043 } 00044 else if ( regVal & 0x02 ) 00045 { 00046 I2SDMA1Done = 1; 00047 } 00048 } 00049 00050 regVal = LPC_GPDMA->DMACIntErrStat; 00051 if ( regVal ) 00052 { 00053 DMAErrCount++; 00054 LPC_GPDMA->DMACIntErrClr |= regVal; 00055 } 00056 00057 } 00058 00059 /****************************************************************************** 00060 ** Function name: DMA_Init 00061 ** 00062 ** Descriptions: 00063 ** 00064 ** parameters: 00065 ** Returned value: 00066 ** 00067 ******************************************************************************/ 00068 uint32_t DMA_Init( uint32_t ChannelNum, uint32_t DMAMode ) 00069 { 00070 if ( ChannelNum == 0 ) 00071 { 00072 LPC_GPDMA->DMACIntTCClear = 0x01; 00073 if ( DMAMode == M2P ) 00074 { 00075 /* Ch0 set for M2P transfer from mempry to I2S TX FIFO. */ 00076 LPC_GPDMACH0->DMACCSrcAddr = DMA_SRC; 00077 LPC_GPDMACH0->DMACCDestAddr = DMA_I2S_TX_FIFO; 00078 /* The burst size is set to 1. Terminal Count Int enable */ 00079 LPC_GPDMACH0->DMACCControl = (DMA_SIZE & 0x0FFF) | (0x00 << 12) | (0x00 << 15) 00080 | (1 << 26) | 0x80000000; 00081 } 00082 else if ( DMAMode == P2M ) 00083 { 00084 /* Ch0 set for P2M transfer from I2S RX FIFO to memory. */ 00085 LPC_GPDMACH0->DMACCSrcAddr = DMA_I2S_RX_FIFO; 00086 LPC_GPDMACH0->DMACCDestAddr = DMA_DST; 00087 /* The burst size is set to 1. Terminal Count Int enable. */ 00088 LPC_GPDMACH0->DMACCControl = (DMA_SIZE & 0x0FFF) | (0x00 << 12) | (0x00 << 15) 00089 | (1 << 27) | 0x80000000; 00090 } 00091 else if ( DMAMode == P2P ) 00092 { 00093 /* Ch0 set for P2P transfer from I2S DAO to I2S DAI. */ 00094 LPC_GPDMACH0->DMACCSrcAddr = DMA_I2S_TX_FIFO; 00095 LPC_GPDMACH0->DMACCDestAddr = DMA_I2S_RX_FIFO; 00096 /* The burst size is set to 32. */ 00097 LPC_GPDMACH0->DMACCControl = (DMA_SIZE & 0x0FFF) | (0x04 << 12) | (0x04 << 15) 00098 | 0x80000000; 00099 } 00100 else 00101 { 00102 return ( FALSE ); 00103 } 00104 } 00105 else if ( ChannelNum == 1 ) 00106 { 00107 LPC_GPDMA->DMACIntTCClear = 0x02; 00108 if ( DMAMode == M2P ) 00109 { 00110 /* Ch1 set for M2P transfer from mempry to I2S TX FIFO. */ 00111 LPC_GPDMACH1->DMACCSrcAddr = DMA_SRC; 00112 LPC_GPDMACH1->DMACCDestAddr = DMA_I2S_TX_FIFO; 00113 /* The burst size is set to 1. Terminal Count Int enable. */ 00114 LPC_GPDMACH1->DMACCControl = (DMA_SIZE & 0x0FFF) | (0x00 << 12) | (0x00 << 15) 00115 | (1 << 26) | 0x80000000; 00116 } 00117 else if ( DMAMode == P2M ) 00118 { 00119 /* Ch1 set for P2M transfer from I2S RX FIFO to memory. */ 00120 LPC_GPDMACH1->DMACCSrcAddr = DMA_I2S_RX_FIFO; 00121 LPC_GPDMACH1->DMACCDestAddr = DMA_DST; 00122 /* The burst size is set to 1. Terminal Count Int enable. */ 00123 LPC_GPDMACH1->DMACCControl = (DMA_SIZE & 0x0FFF) | (0x00 << 12) | (0x00 << 15) 00124 | (1 << 27) | 0x80000000; 00125 } 00126 else if ( DMAMode == P2P ) 00127 { 00128 /* Ch1 set for P2P transfer from I2S DAO to I2S DAI. */ 00129 LPC_GPDMACH1->DMACCSrcAddr = DMA_I2S_TX_FIFO; 00130 LPC_GPDMACH1->DMACCDestAddr = DMA_I2S_RX_FIFO; 00131 /* The burst size is set to 32. */ 00132 LPC_GPDMACH1->DMACCControl = (DMA_SIZE & 0x0FFF) | (0x04 << 12) | (0x04 << 15) 00133 | 0x80000000; 00134 } 00135 else 00136 { 00137 return ( FALSE ); 00138 } 00139 } 00140 else 00141 { 00142 return ( FALSE ); 00143 } 00144 return( TRUE ); 00145 } 00146 00147 #endif /* end if DMA_ENABLED */ 00148 00149 /****************************************************************************** 00150 ** End Of File 00151 ******************************************************************************/
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