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mbed library sources
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mbed official
Revision 625:6502bcae5f2c, committed 2015-09-25
- Comitter:
- mbed_official
- Date:
- Fri Sep 25 12:00:11 2015 +0100
- Parent:
- 624:83778a75d1b4
- Child:
- 626:ba773d547214
- Commit message:
- Synchronized with git revision 724c07935c2d3e3d8a1b3e7274b29ba5dcbed7ad
Full URL: https://github.com/mbedmicro/mbed/commit/724c07935c2d3e3d8a1b3e7274b29ba5dcbed7ad/
Changes contains only "Copyright year information" and "KR styling". Safe to merge.
Changed in this revision
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld Fri Sep 25 12:00:11 2015 +0100
@@ -3,19 +3,17 @@
SEARCH_DIR(.)
/* Memory Spaces Definitions */
-MEMORY
-{
- rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
- ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
-}
+MEMORY {
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+ }
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+ /* The stack size used by the application. NOTE: you need to adjust according to your application. */
+ STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-/* Section Definitions */
-SECTIONS
-{
- .text :
+ /* Section Definitions */
+ SECTIONS {
+.text :
{
. = ALIGN(4);
_sfixed = .;
@@ -66,23 +64,24 @@
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
- .ARM.exidx :
+.ARM.exidx :
{
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
-
- .dvectors (NOLOAD) :
- {
- _sdvectors = .;
- . = . + 0xB0;
- _edvectors = .;
- } > ram
- .relocate : AT (_etext)
+ .dvectors (NOLOAD) :
+ {
+ _sdvectors = .;
+ . = . + 0xB0;
+ _edvectors = .;
+ } > ram
+
+.relocate :
+ AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
@@ -105,12 +104,12 @@
_ezero = .;
} > ram
- .heap (NOLOAD) :
- {
- . = ALIGN(4);
- __end__ = . ;
- . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
- } > ram
+ .heap (NOLOAD) :
+ {
+ . = ALIGN(4);
+ __end__ = . ;
+ . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+ } > ram
/* stack section */
.stack (NOLOAD):
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld Fri Sep 25 12:00:11 2015 +0100
@@ -3,19 +3,17 @@
SEARCH_DIR(.)
/* Memory Spaces Definitions */
-MEMORY
-{
- rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
- ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
-}
+MEMORY {
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+ }
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+ /* The stack size used by the application. NOTE: you need to adjust according to your application. */
+ STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-/* Section Definitions */
-SECTIONS
-{
- .text :
+ /* Section Definitions */
+ SECTIONS {
+.text :
{
. = ALIGN(4);
_sfixed = .;
@@ -66,23 +64,24 @@
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
- .ARM.exidx :
+.ARM.exidx :
{
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
-
- .dvectors (NOLOAD) :
- {
- _sdvectors = .;
- . = . + 0xB0;
- _edvectors = .;
- } > ram
- .relocate : AT (_etext)
+ .dvectors (NOLOAD) :
+ {
+ _sdvectors = .;
+ . = . + 0xB0;
+ _edvectors = .;
+ } > ram
+
+.relocate :
+ AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
@@ -105,12 +104,12 @@
_ezero = .;
} > ram
- .heap (NOLOAD) :
- {
- . = ALIGN(4);
- __end__ = . ;
- . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
- } > ram
+ .heap (NOLOAD) :
+ {
+ . = ALIGN(4);
+ __end__ = . ;
+ . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+ } > ram
/* stack section */
.stack (NOLOAD):
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_IAR/startup_samr21.c Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_IAR/startup_samr21.c Fri Sep 25 12:00:11 2015 +0100
@@ -42,7 +42,10 @@
#include "samr21.h"
typedef void (*intfunc) (void);
-typedef union { intfunc __fun; void * __ptr; } intvec_elem;
+typedef union {
+ intfunc __fun;
+ void * __ptr;
+} intvec_elem;
void __iar_program_start(void);
int __low_level_init(void);
@@ -116,89 +119,89 @@
#pragma section = ".intvec"
#pragma location = ".intvec"
const DeviceVectors __vector_table[] = {
- __sfe("CSTACK"),
- (void*) __iar_program_start,
- (void*) NMI_Handler,
- (void*) HardFault_Handler,
- (void*) (0UL), /* Reserved */
- (void*) (0UL), /* Reserved */
- (void*) (0UL), /* Reserved */
- (void*) (0UL), /* Reserved */
- (void*) (0UL), /* Reserved */
- (void*) (0UL), /* Reserved */
- (void*) (0UL), /* Reserved */
- (void*) SVC_Handler,
- (void*) (0UL), /* Reserved */
- (void*) (0UL), /* Reserved */
- (void*) PendSV_Handler,
- (void*) SysTick_Handler,
+ __sfe("CSTACK"),
+ (void*) __iar_program_start,
+ (void*) NMI_Handler,
+ (void*) HardFault_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) SVC_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) PendSV_Handler,
+ (void*) SysTick_Handler,
- /* Configurable interrupts */
- (void*) PM_Handler, /* 0 Power Manager */
- (void*) SYSCTRL_Handler, /* 1 System Control */
- (void*) WDT_Handler, /* 2 Watchdog Timer */
- (void*) RTC_Handler, /* 3 Real-Time Counter */
- (void*) EIC_Handler, /* 4 External Interrupt Controller */
- (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
- (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
+ /* Configurable interrupts */
+ (void*) PM_Handler, /* 0 Power Manager */
+ (void*) SYSCTRL_Handler, /* 1 System Control */
+ (void*) WDT_Handler, /* 2 Watchdog Timer */
+ (void*) RTC_Handler, /* 3 Real-Time Counter */
+ (void*) EIC_Handler, /* 4 External Interrupt Controller */
+ (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
+ (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
#ifdef ID_USB
- (void*) USB_Handler, /* 7 Universal Serial Bus */
+ (void*) USB_Handler, /* 7 Universal Serial Bus */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
- (void*) EVSYS_Handler, /* 8 Event System Interface */
- (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
- (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
- (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
- (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
+ (void*) EVSYS_Handler, /* 8 Event System Interface */
+ (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
+ (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
+ (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
+ (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
#ifdef ID_SERCOM4
- (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
+ (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
#ifdef ID_SERCOM5
- (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
+ (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
- (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
- (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
- (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
- (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
- (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
- (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
+ (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
+ (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
+ (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
+ (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
+ (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
+ (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
#ifdef ID_TC6
- (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
+ (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
#ifdef ID_TC7
- (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
+ (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
#ifdef ID_ADC
- (void*) ADC_Handler, /* 23 Analog Digital Converter */
+ (void*) ADC_Handler, /* 23 Analog Digital Converter */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
#ifdef ID_AC
- (void*) AC_Handler, /* 24 Analog Comparators */
+ (void*) AC_Handler, /* 24 Analog Comparators */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
#ifdef ID_DAC
- (void*) DAC_Handler, /* 25 Digital Analog Converter */
+ (void*) DAC_Handler, /* 25 Digital Analog Converter */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
#ifdef ID_PTC
- (void*) PTC_Handler, /* 26 Peripheral Touch Controller */
+ (void*) PTC_Handler, /* 26 Peripheral Touch Controller */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
- (void*) I2S_Handler, /* 27 Inter-IC Sound Interface */
- (void*) (0UL), /* Reserved */
+ (void*) I2S_Handler, /* 27 Inter-IC Sound Interface */
+ (void*) (0UL), /* Reserved */
};
/**------------------------------------------------------------------------------
@@ -207,11 +210,11 @@
*------------------------------------------------------------------------------*/
int __low_level_init(void)
{
- uint32_t *pSrc = __section_begin(".intvec");
+ uint32_t *pSrc = __section_begin(".intvec");
- SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
- return 1; /* if return 0, the data sections will not be initialized */
+ return 1; /* if return 0, the data sections will not be initialized */
}
/**------------------------------------------------------------------------------
@@ -220,20 +223,20 @@
*------------------------------------------------------------------------------*/
void Reset_Handler(void)
{
- /* Change default QOS values to have the best performance and correct USB behaviour */
- SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
+ /* Change default QOS values to have the best performance and correct USB behaviour */
+ SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
#if defined(ID_USB)
- USB->DEVICE.QOSCTRL.bit.CQOS = 2;
- USB->DEVICE.QOSCTRL.bit.DQOS = 2;
+ USB->DEVICE.QOSCTRL.bit.CQOS = 2;
+ USB->DEVICE.QOSCTRL.bit.DQOS = 2;
#endif
- DMAC->QOSCTRL.bit.DQOS = 2;
- DMAC->QOSCTRL.bit.FQOS = 2;
- DMAC->QOSCTRL.bit.WRBQOS = 2;
+ DMAC->QOSCTRL.bit.DQOS = 2;
+ DMAC->QOSCTRL.bit.FQOS = 2;
+ DMAC->QOSCTRL.bit.WRBQOS = 2;
- /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
- NVMCTRL->CTRLB.bit.MANW = 1;
+ /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
+ NVMCTRL->CTRLB.bit.MANW = 1;
- __iar_program_start();
+ __iar_program_start();
}
/**
@@ -241,6 +244,6 @@
*/
void Dummy_Handler(void)
{
- while (1) {
- }
+ while (1) {
+ }
}
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,14 +59,14 @@
/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} AC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -87,16 +87,16 @@
/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
- uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
+ uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -115,25 +115,25 @@
/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
- uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
- uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
+ uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
+ uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} AC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -164,20 +164,20 @@
/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
- uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -201,20 +201,20 @@
/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
- uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -238,20 +238,20 @@
/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
- uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN0:1; /*!< bit: 4 Window 0 */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN:1; /*!< bit: 4 Window x */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -275,18 +275,18 @@
/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
- uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -314,17 +314,17 @@
/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
- uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
+ uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -345,18 +345,18 @@
/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
- uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_STATUSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -384,12 +384,12 @@
/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
- uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
+ uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} AC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -414,26 +414,26 @@
/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ENABLE:1; /*!< bit: 0 Enable */
- uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
- uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
- uint32_t :1; /*!< bit: 4 Reserved */
- uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
- uint32_t :1; /*!< bit: 14 Reserved */
- uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
- uint32_t OUT:2; /*!< bit: 16..17 Output */
- uint32_t :1; /*!< bit: 18 Reserved */
- uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ENABLE:1; /*!< bit: 0 Enable */
+ uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
+ uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
+ uint32_t :1; /*!< bit: 4 Reserved */
+ uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
+ uint32_t :1; /*!< bit: 14 Reserved */
+ uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
+ uint32_t OUT:2; /*!< bit: 16..17 Output */
+ uint32_t :1; /*!< bit: 18 Reserved */
+ uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} AC_COMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -519,11 +519,11 @@
/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} AC_SCALER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -538,22 +538,22 @@
/** \brief AC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
- __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
- __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
- __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
- __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
- __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
- __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
- RoReg8 Reserved2[0x1];
- __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
- RoReg8 Reserved3[0x3];
- __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
- RoReg8 Reserved4[0x8];
- __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
+ __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
+ __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
+ __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
+ __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
+ __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
+ __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
+ __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
+ RoReg8 Reserved2[0x1];
+ __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
+ RoReg8 Reserved3[0x3];
+ __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+ RoReg8 Reserved4[0x8];
+ __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
} Ac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,13 +59,13 @@
/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -83,12 +83,12 @@
/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_REFCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -115,12 +115,12 @@
/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
- uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
+ uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_AVGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -160,11 +160,11 @@
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_SAMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -179,17 +179,17 @@
/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
- uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
- uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
- uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
- uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
+ uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
+ uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
+ uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
+ uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -239,11 +239,11 @@
/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -268,12 +268,12 @@
/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
- uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
+ uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_SWTRIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -289,17 +289,17 @@
/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
- uint32_t :3; /*!< bit: 5.. 7 Reserved */
- uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
- uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
- uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
+ uint32_t :3; /*!< bit: 5.. 7 Reserved */
+ uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
+ uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
+ uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} ADC_INPUTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -408,15 +408,15 @@
/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
- uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
- uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
+ uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
+ uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -436,14 +436,14 @@
/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
- uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
- uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -463,14 +463,14 @@
/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
- uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
- uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -490,14 +490,14 @@
/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
- uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
- uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -517,11 +517,11 @@
/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -535,10 +535,10 @@
/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_RESULT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -553,10 +553,10 @@
/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_WINLT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -571,10 +571,10 @@
/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_WINUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -589,11 +589,11 @@
/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_GAINCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -608,11 +608,11 @@
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_OFFSETCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -627,12 +627,12 @@
/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
- uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
+ uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_CALIB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -650,11 +650,11 @@
/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -668,32 +668,32 @@
/** \brief ADC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
- __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
- __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
- __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
- RoReg8 Reserved1[0x2];
- __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
- RoReg8 Reserved2[0x3];
- __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
- RoReg8 Reserved3[0x3];
- __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
- __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
- RoReg8 Reserved4[0x1];
- __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
- __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
- __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
- __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
- __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
- __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
- RoReg8 Reserved5[0x2];
- __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
- RoReg8 Reserved6[0x2];
- __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
- __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
- __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
- __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
+ __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
+ __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
+ __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
+ __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
+ RoReg8 Reserved1[0x2];
+ __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
+ RoReg8 Reserved2[0x3];
+ __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
+ RoReg8 Reserved3[0x3];
+ __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
+ __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
+ RoReg8 Reserved4[0x1];
+ __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
+ __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
+ __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
+ __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
+ __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
+ __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
+ RoReg8 Reserved5[0x2];
+ __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
+ RoReg8 Reserved6[0x2];
+ __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
+ __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
+ __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
+ __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
} Adc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,13 +59,13 @@
/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DAC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -83,16 +83,16 @@
/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
- uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
- uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
- uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
- uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
+ uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
+ uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
+ uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
+ uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DAC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -123,12 +123,12 @@
/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
- uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
+ uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DAC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -144,13 +144,13 @@
/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
- uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
- uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DAC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -168,13 +168,13 @@
/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
- uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
- uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DAC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -192,13 +192,13 @@
/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
- uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
- uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DAC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -216,11 +216,11 @@
/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DAC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -234,10 +234,10 @@
/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DAC_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -252,10 +252,10 @@
/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DAC_DATABUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -270,17 +270,17 @@
/** \brief DAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
- __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
- __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
- RoReg8 Reserved1[0x1];
- __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
- __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
- __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
- __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
- __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
- RoReg8 Reserved2[0x2];
- __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
+ __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
+ __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
+ __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
+ RoReg8 Reserved1[0x1];
+ __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
+ __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
+ __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
+ __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
+ __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
+ RoReg8 Reserved2[0x2];
+ __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
} Dac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,23 +59,23 @@
/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
- uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
- uint16_t :5; /*!< bit: 3.. 7 Reserved */
- uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
- uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
- uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
- uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :8; /*!< bit: 0.. 7 Reserved */
- uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
+ uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
+ uint16_t :5; /*!< bit: 3.. 7 Reserved */
+ uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
+ uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
+ uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
+ uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :8; /*!< bit: 0.. 7 Reserved */
+ uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -104,14 +104,14 @@
/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
- uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
+ uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_CRCCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -146,10 +146,10 @@
/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_CRCDATAIN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -164,10 +164,10 @@
/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_CRCCHKSUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -182,12 +182,12 @@
/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
- uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
+ uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CRCSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -203,11 +203,11 @@
/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -221,13 +221,13 @@
/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
- uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
- uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
+ uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
+ uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_QOSCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -272,26 +272,26 @@
/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
- uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
- uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
- uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
- uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
- uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
- uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
- uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
- uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
- uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
- uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
- uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
+ uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
+ uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
+ uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
+ uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
+ uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
+ uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
+ uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
+ uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
+ uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
+ uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
+ uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_SWTRIGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -330,21 +330,21 @@
/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
- uint32_t :3; /*!< bit: 4.. 6 Reserved */
- uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
- uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
- uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
- uint32_t :3; /*!< bit: 20..22 Reserved */
- uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
- uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
- uint32_t :3; /*!< bit: 28..30 Reserved */
- uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
+ uint32_t :3; /*!< bit: 4.. 6 Reserved */
+ uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
+ uint32_t :3; /*!< bit: 20..22 Reserved */
+ uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
+ uint32_t :3; /*!< bit: 28..30 Reserved */
+ uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_PRICTRL0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -376,18 +376,18 @@
/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t TERR:1; /*!< bit: 8 Transfer Error */
- uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
- uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
- uint16_t :2; /*!< bit: 11..12 Reserved */
- uint16_t FERR:1; /*!< bit: 13 Fetch Error */
- uint16_t BUSY:1; /*!< bit: 14 Busy */
- uint16_t PEND:1; /*!< bit: 15 Pending */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t TERR:1; /*!< bit: 8 Transfer Error */
+ uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
+ uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
+ uint16_t :2; /*!< bit: 11..12 Reserved */
+ uint16_t FERR:1; /*!< bit: 13 Fetch Error */
+ uint16_t BUSY:1; /*!< bit: 14 Busy */
+ uint16_t PEND:1; /*!< bit: 15 Pending */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_INTPEND_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -414,26 +414,26 @@
/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
- uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
- uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
- uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
- uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
- uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
- uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
- uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
- uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
- uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
- uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
- uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
+ uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
+ uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
+ uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
+ uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
+ uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
+ uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
+ uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
+ uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
+ uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
+ uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
+ uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_INTSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -472,26 +472,26 @@
/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
- uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
- uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
- uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
- uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
- uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
- uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
- uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
- uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
- uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
- uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
- uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
+ uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
+ uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
+ uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
+ uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
+ uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
+ uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
+ uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
+ uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
+ uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
+ uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
+ uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_BUSYCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -530,26 +530,26 @@
/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
- uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
- uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
- uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
- uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
- uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
- uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
- uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
- uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
- uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
- uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
- uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
+ uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
+ uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
+ uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
+ uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
+ uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
+ uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
+ uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
+ uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
+ uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
+ uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
+ uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_PENDCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -588,22 +588,22 @@
/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
- uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
- uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
- uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
- uint32_t :2; /*!< bit: 13..14 Reserved */
- uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
- uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
- uint32_t :28; /*!< bit: 4..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
+ uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
+ uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
+ uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
+ uint32_t :2; /*!< bit: 13..14 Reserved */
+ uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
+ uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_ACTIVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -634,10 +634,10 @@
/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_BASEADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -652,10 +652,10 @@
/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_WRBADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -670,11 +670,11 @@
/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -689,12 +689,12 @@
/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -710,19 +710,19 @@
/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
- uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
- uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
- uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t TRIGSRC:6; /*!< bit: 8..13 Peripheral Trigger Source */
- uint32_t :8; /*!< bit: 14..21 Reserved */
- uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
- uint32_t CMD:2; /*!< bit: 24..25 Software Command */
- uint32_t :6; /*!< bit: 26..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
+ uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
+ uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
+ uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TRIGSRC:6; /*!< bit: 8..13 Peripheral Trigger Source */
+ uint32_t :8; /*!< bit: 14..21 Reserved */
+ uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
+ uint32_t CMD:2; /*!< bit: 24..25 Software Command */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_CHCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -789,13 +789,13 @@
/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
- uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
- uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -813,13 +813,13 @@
/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
- uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
- uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -837,13 +837,13 @@
/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TERR:1; /*!< bit: 0 Transfer Error */
- uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */
- uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Transfer Error */
+ uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -861,13 +861,13 @@
/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PEND:1; /*!< bit: 0 Channel Pending */
- uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
- uint8_t FERR:1; /*!< bit: 2 Fetch Error */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PEND:1; /*!< bit: 0 Channel Pending */
+ uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
+ uint8_t FERR:1; /*!< bit: 2 Fetch Error */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -885,18 +885,18 @@
/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
- uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
- uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
- uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
- uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
- uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
- uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
+ uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
+ uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
+ uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
+ uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
+ uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
+ uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_BTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -967,10 +967,10 @@
/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_BTCNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -984,10 +984,10 @@
/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_SRCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1001,10 +1001,10 @@
/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_DSTADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1018,10 +1018,10 @@
/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_DESCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1035,49 +1035,49 @@
/** \brief DMAC APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
- __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
- __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
- __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
- __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
- __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
- __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
- RoReg8 Reserved1[0x1];
- __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
- __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
- RoReg8 Reserved2[0x8];
- __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
- RoReg8 Reserved3[0x2];
- __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
- __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
- __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
- __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
- __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
- __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
- RoReg8 Reserved4[0x3];
- __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
- __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
- RoReg8 Reserved5[0x3];
- __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
- RoReg8 Reserved6[0x4];
- __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
- __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
- __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
- __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
+ __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
+ __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
+ __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
+ __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
+ __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
+ __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
+ __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
+ RoReg8 Reserved1[0x1];
+ __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
+ __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
+ RoReg8 Reserved2[0x8];
+ __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
+ RoReg8 Reserved3[0x2];
+ __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
+ __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
+ __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
+ __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
+ __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
+ __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
+ RoReg8 Reserved4[0x3];
+ __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
+ __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
+ RoReg8 Reserved5[0x3];
+ __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
+ RoReg8 Reserved6[0x4];
+ __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
+ __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
+ __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
+ __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
} Dmac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief DMAC Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
- __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
- __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */
- __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */
- __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
+ __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
+ __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
+ __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */
+ __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */
+ __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
} DmacDescriptor
#ifdef __GNUC__
- __attribute__ ((aligned (8)))
+__attribute__ ((aligned (8)))
#endif
;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,15 +59,15 @@
/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
- uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
- uint8_t CE:1; /*!< bit: 4 Chip Erase */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
+ uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
+ uint8_t CE:1; /*!< bit: 4 Chip Erase */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DSU_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -87,15 +87,15 @@
/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DONE:1; /*!< bit: 0 Done */
- uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
- uint8_t BERR:1; /*!< bit: 2 Bus Error */
- uint8_t FAIL:1; /*!< bit: 3 Failure */
- uint8_t PERR:1; /*!< bit: 4 Protection Error */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DONE:1; /*!< bit: 0 Done */
+ uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
+ uint8_t BERR:1; /*!< bit: 2 Bus Error */
+ uint8_t FAIL:1; /*!< bit: 3 Failure */
+ uint8_t PERR:1; /*!< bit: 4 Protection Error */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DSU_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -117,20 +117,20 @@
/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PROT:1; /*!< bit: 0 Protected */
- uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
- uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
- uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
- uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PROT:1; /*!< bit: 0 Protected */
+ uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
+ uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
+ uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
+ uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} DSU_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -155,11 +155,11 @@
/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t ADDR:30; /*!< bit: 2..31 Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t ADDR:30; /*!< bit: 2..31 Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -174,11 +174,11 @@
/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t LENGTH:30; /*!< bit: 2..31 Length */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t LENGTH:30; /*!< bit: 2..31 Length */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_LENGTH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -193,10 +193,10 @@
/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -211,10 +211,10 @@
/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_DCC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -229,16 +229,16 @@
/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
- uint32_t REVISION:4; /*!< bit: 8..11 Revision */
- uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
- uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
- uint32_t :1; /*!< bit: 22 Reserved */
- uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
- uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
+ uint32_t REVISION:4; /*!< bit: 8..11 Revision */
+ uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
+ uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
+ uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_DID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -267,13 +267,13 @@
/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EPRES:1; /*!< bit: 0 Entry Present */
- uint32_t FMT:1; /*!< bit: 1 Format */
- uint32_t :10; /*!< bit: 2..11 Reserved */
- uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EPRES:1; /*!< bit: 0 Entry Present */
+ uint32_t FMT:1; /*!< bit: 1 Format */
+ uint32_t :10; /*!< bit: 2..11 Reserved */
+ uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_ENTRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -292,10 +292,10 @@
/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t END:32; /*!< bit: 0..31 End Marker */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t END:32; /*!< bit: 0..31 End Marker */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_END_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -310,11 +310,11 @@
/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_MEMTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -328,12 +328,12 @@
/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
- uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
+ uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -351,11 +351,11 @@
/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -370,12 +370,12 @@
/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
- uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
+ uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -393,13 +393,13 @@
/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
- uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
- uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
+ uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
+ uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -419,12 +419,12 @@
/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
- uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
+ uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -442,11 +442,11 @@
/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -461,12 +461,12 @@
/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
- uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
+ uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -484,11 +484,11 @@
/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -503,11 +503,11 @@
/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -522,30 +522,30 @@
/** \brief DSU hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
- __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
- __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
- RoReg8 Reserved1[0x1];
- __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
- __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
- __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
- __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
- __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
- RoReg8 Reserved2[0xFE4];
- __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
- __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
- RoReg8 Reserved3[0xFC0];
- __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
- __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
- RoReg8 Reserved4[0xC];
- __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
- __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
- __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
- __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
- __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
- __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
- __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
- __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
+ __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
+ __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
+ __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
+ RoReg8 Reserved1[0x1];
+ __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
+ __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
+ __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
+ __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
+ __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
+ RoReg8 Reserved2[0xFE4];
+ __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
+ __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
+ RoReg8 Reserved3[0xFC0];
+ __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
+ __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
+ RoReg8 Reserved4[0xC];
+ __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
+ __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
+ __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
+ __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
+ __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
+ __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
+ __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
+ __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
} Dsu;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,12 +59,12 @@
/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -80,11 +80,11 @@
/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -98,12 +98,12 @@
/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
- uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
+ uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_NMICTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -132,11 +132,11 @@
/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_NMIFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -150,30 +150,30 @@
/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
- uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
- uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
- uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
- uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
- uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
- uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
- uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
- uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
- uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
- uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
- uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
- uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
- uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
- uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
- uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
+ uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
+ uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
+ uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
+ uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
+ uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
+ uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
+ uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
+ uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
+ uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
+ uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
+ uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
+ uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
+ uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
+ uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
+ uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -220,30 +220,30 @@
/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
- uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
- uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
- uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
- uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
- uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
- uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
- uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
- uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
- uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
- uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
- uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
- uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
- uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
- uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
- uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -290,30 +290,30 @@
/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
- uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
- uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
- uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
- uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
- uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
- uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
- uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
- uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
- uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
- uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
- uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
- uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
- uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
- uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
- uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -360,30 +360,30 @@
/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
- uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
- uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
- uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
- uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
- uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
- uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
- uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
- uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
- uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
- uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
- uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
- uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
- uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
- uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
- uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -430,30 +430,30 @@
/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
- uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
- uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
- uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
- uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
- uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
- uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
- uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
- uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
- uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
- uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
- uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
- uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
- uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
- uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
- uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
+ uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
+ uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
+ uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
+ uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
+ uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
+ uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
+ uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
+ uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
+ uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
+ uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
+ uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
+ uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
+ uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
+ uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
+ uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_WAKEUP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -500,25 +500,25 @@
/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
- uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
- uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
- uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
- uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
- uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
- uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
- uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
- uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
- uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
- uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
- uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
- uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
- uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
- uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
- uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
+ uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
+ uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
+ uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
+ uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
+ uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
+ uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
+ uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
+ uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
+ uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
+ uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
+ uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
+ uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
+ uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
+ uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
+ uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -666,16 +666,16 @@
/** \brief EIC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
- __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
- __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
- __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
- __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
- __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
- __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
- __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
- __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
- __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
+ __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
+ __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
+ __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
+ __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
+ __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
+ __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
+ __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
+ __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
+ __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
+ __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
} Eic;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,13 +59,13 @@
/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t :3; /*!< bit: 1.. 3 Reserved */
- uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :3; /*!< bit: 1.. 3 Reserved */
+ uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EVSYS_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -81,18 +81,18 @@
/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t SWEVT:1; /*!< bit: 8 Software Event */
- uint32_t :7; /*!< bit: 9..15 Reserved */
- uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
- uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t SWEVT:1; /*!< bit: 8 Software Event */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
+ uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_CHANNEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -132,13 +132,13 @@
/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
- uint16_t :3; /*!< bit: 13..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} EVSYS_USER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -158,43 +158,43 @@
/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
- uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
- uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
- uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
- uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
- uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
- uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
- uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
- uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
- uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
- uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
- uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
- uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
- uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
- uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
- uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
- uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
- uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
- uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
- uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
- uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
- uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
- uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
- uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
- uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
+ uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
+ uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
+ uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
+ uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
+ uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
+ uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
+ uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
+ uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
+ uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
+ uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
+ uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
+ uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
+ uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
+ uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
+ uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
+ uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
+ uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
+ uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
+ uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
+ uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
+ uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
+ uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
+ uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
+ uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -266,43 +266,43 @@
/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
- uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
- uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
- uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
- uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
- uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
- uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
- uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
- uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
- uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
- uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
- uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
- uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
- uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
- uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
- uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
- uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
- uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
- uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
- uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
- uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
- uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
- uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
- uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
- uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -374,43 +374,43 @@
/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
- uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
- uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
- uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
- uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
- uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
- uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
- uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
- uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
- uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
- uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
- uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
- uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
- uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
- uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
- uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
- uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
- uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
- uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
- uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
- uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
- uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
- uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
- uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
- uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -482,43 +482,43 @@
/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
- uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
- uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
- uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
- uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
- uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
- uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
- uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
- uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
- uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
- uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
- uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
- uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
- uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
- uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
- uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
- uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
- uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
- uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
- uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
- uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
- uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
- uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
- uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
- uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -590,15 +590,15 @@
/** \brief EVSYS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
- RoReg8 Reserved1[0x3];
- __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
- __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
- RoReg8 Reserved2[0x2];
- __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
- __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
- __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
- __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
+ __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
+ RoReg8 Reserved1[0x3];
+ __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
+ __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
+ RoReg8 Reserved2[0x2];
+ __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
+ __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
+ __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
+ __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
} Evsys;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,11 +59,11 @@
/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} GCLK_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -77,11 +77,11 @@
/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} GCLK_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -95,15 +95,15 @@
/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
- uint16_t :2; /*!< bit: 12..13 Reserved */
- uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
- uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
+ uint16_t :2; /*!< bit: 12..13 Reserved */
+ uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
+ uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} GCLK_CLKCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -215,20 +215,20 @@
/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t SRC:5; /*!< bit: 8..12 Source Select */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
- uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
- uint32_t OOV:1; /*!< bit: 18 Output Off Value */
- uint32_t OE:1; /*!< bit: 19 Output Enable */
- uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
- uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t SRC:5; /*!< bit: 8..12 Source Select */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
+ uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
+ uint32_t OOV:1; /*!< bit: 18 Output Off Value */
+ uint32_t OE:1; /*!< bit: 19 Output Enable */
+ uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
+ uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} GCLK_GENCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -276,13 +276,13 @@
/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} GCLK_GENDIV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -300,11 +300,11 @@
/** \brief GCLK hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
- __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
- __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
- __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
- __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
+ __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
+ __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
+ __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
+ __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
} Gclk;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,7 +59,7 @@
/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRAS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -71,7 +71,7 @@
/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRBS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -83,10 +83,10 @@
/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} HMATRIXB_SFR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -101,18 +101,18 @@
/** \brief HmatrixbPrs hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
- __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
+ __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
+ __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
} HmatrixbPrs;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief HMATRIXB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- RoReg8 Reserved1[0x80];
- HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
- RoReg8 Reserved2[0x10];
- __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
+ RoReg8 Reserved1[0x80];
+ HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
+ RoReg8 Reserved2[0x10];
+ __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
} Hmatrixb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,22 +59,22 @@
/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
- uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
- uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
- uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
- uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
+ uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
+ uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
+ uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
+ uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} I2S_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -104,26 +104,26 @@
/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
- uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
- uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
- uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
- uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
- uint32_t :2; /*!< bit: 9..10 Reserved */
- uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
- uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
- uint32_t :1; /*!< bit: 17 Reserved */
- uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
- uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
- uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
- uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
- uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
- uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
+ uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
+ uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
+ uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
+ uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
+ uint32_t :2; /*!< bit: 9..10 Reserved */
+ uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
+ uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
+ uint32_t :1; /*!< bit: 17 Reserved */
+ uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
+ uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
+ uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
+ uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
+ uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
+ uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} I2S_CLKCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -200,31 +200,31 @@
/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
- uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
- uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
- uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
- uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} I2S_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -264,31 +264,31 @@
/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
- uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
- uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
- uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
- uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} I2S_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -328,31 +328,31 @@
/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
- uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
- uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
- uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
- uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} I2S_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -392,27 +392,27 @@
/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
- uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
- uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
- uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
- uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
- uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
- uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
- uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
+ uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
+ uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
+ uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
+ uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
+ uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
+ uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} I2S_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -449,37 +449,37 @@
/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
- uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
- uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
- uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
- uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
- uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
- uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
- uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
- uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
- uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
- uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
- uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
- uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
- uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
- uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
- uint32_t MONO:1; /*!< bit: 24 Mono Mode */
- uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
- uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
+ uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
+ uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
+ uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
+ uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
+ uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
+ uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
+ uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
+ uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
+ uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
+ uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
+ uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
+ uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
+ uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
+ uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
+ uint32_t MONO:1; /*!< bit: 24 Mono Mode */
+ uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
+ uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} I2S_SERCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -602,10 +602,10 @@
/* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} I2S_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -620,20 +620,20 @@
/** \brief I2S hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- RoReg8 Reserved1[0x3];
- __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
- __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
- RoReg8 Reserved2[0x2];
- __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
- RoReg8 Reserved3[0x2];
- __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x2];
- __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
- RoReg8 Reserved5[0x6];
- __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
- RoReg8 Reserved6[0x8];
- __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
+ __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ RoReg8 Reserved1[0x3];
+ __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
+ __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
+ RoReg8 Reserved2[0x2];
+ __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
+ RoReg8 Reserved3[0x2];
+ __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x2];
+ __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
+ RoReg8 Reserved5[0x6];
+ __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
+ RoReg8 Reserved6[0x8];
+ __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
} I2s;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,12 +59,12 @@
/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
- uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
+ uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_POSITION_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -80,17 +80,17 @@
/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
- uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
- uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
- uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
- uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
- uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
- uint32_t :21; /*!< bit: 10..30 Reserved */
- uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
+ uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
+ uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
+ uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
+ uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
+ uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
+ uint32_t :21; /*!< bit: 10..30 Reserved */
+ uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_MASTER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -117,13 +117,13 @@
/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
- uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
+ uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_FLOW_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -142,7 +142,7 @@
/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_BASE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -152,7 +152,7 @@
/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_ITCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -162,7 +162,7 @@
/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -172,7 +172,7 @@
/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -182,7 +182,7 @@
/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_LOCKACCESS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -192,7 +192,7 @@
/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_LOCKSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -202,7 +202,7 @@
/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_AUTHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -212,7 +212,7 @@
/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_DEVARCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -222,7 +222,7 @@
/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_DEVID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -232,7 +232,7 @@
/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_DEVTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -242,7 +242,7 @@
/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -252,7 +252,7 @@
/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID5_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -262,7 +262,7 @@
/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID6_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -272,7 +272,7 @@
/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID7_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -282,7 +282,7 @@
/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -292,7 +292,7 @@
/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -302,7 +302,7 @@
/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -312,7 +312,7 @@
/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -322,7 +322,7 @@
/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -332,7 +332,7 @@
/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -342,7 +342,7 @@
/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -352,7 +352,7 @@
/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -362,35 +362,35 @@
/** \brief MTB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
- __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
- __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
- __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
- RoReg8 Reserved1[0xEF0];
- __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
- RoReg8 Reserved2[0x9C];
- __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
- __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
- RoReg8 Reserved3[0x8];
- __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
- __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
- __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
- __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
- RoReg8 Reserved4[0x8];
- __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
- __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
- __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
- __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
- __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
- __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
- __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
- __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
- __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
- __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
- __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
- __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
- __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
- __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
+ __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
+ __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
+ __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
+ __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
+ RoReg8 Reserved1[0xEF0];
+ __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
+ RoReg8 Reserved2[0x9C];
+ __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
+ __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
+ RoReg8 Reserved3[0x8];
+ __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
+ __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
+ __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
+ __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
+ RoReg8 Reserved4[0x8];
+ __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
+ __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
+ __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
+ __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
+ __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
+ __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
+ __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
+ __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
+ __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
+ __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
+ __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
+ __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
+ __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
+ __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
} Mtb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,12 +59,12 @@
/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t CMD:7; /*!< bit: 0.. 6 Command */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t CMD:7; /*!< bit: 0.. 6 Command */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -114,18 +114,18 @@
/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t MANW:1; /*!< bit: 7 Manual Write */
- uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
- uint32_t :6; /*!< bit: 10..15 Reserved */
- uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
- uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t MANW:1; /*!< bit: 7 Manual Write */
+ uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
+ uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -168,13 +168,13 @@
/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
- uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
- uint32_t :1; /*!< bit: 19 Reserved */
- uint32_t RWWEEP:12; /*!< bit: 20..31 RWW EEPROM Pages */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
+ uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
+ uint32_t :1; /*!< bit: 19 Reserved */
+ uint32_t RWWEEP:12; /*!< bit: 20..31 RWW EEPROM Pages */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} NVMCTRL_PARAM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -211,12 +211,12 @@
/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
- uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -232,12 +232,12 @@
/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
- uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -253,12 +253,12 @@
/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t READY:1; /*!< bit: 0 NVM Ready */
- uint8_t ERROR:1; /*!< bit: 1 Error */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready */
+ uint8_t ERROR:1; /*!< bit: 1 Error */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -274,17 +274,17 @@
/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
- uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
- uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
- uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
- uint16_t NVME:1; /*!< bit: 4 NVM Error */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t SB:1; /*!< bit: 8 Security Bit Status */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
+ uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
+ uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
+ uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
+ uint16_t NVME:1; /*!< bit: 4 NVM Error */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t SB:1; /*!< bit: 8 Security Bit Status */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} NVMCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -308,11 +308,11 @@
/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} NVMCTRL_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -327,10 +327,10 @@
/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} NVMCTRL_LOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -344,20 +344,20 @@
/** \brief NVMCTRL APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- RoReg8 Reserved1[0x2];
- __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
- __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
- __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- RoReg8 Reserved2[0x3];
- __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
- RoReg8 Reserved3[0x3];
- __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x3];
- __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
- RoReg8 Reserved5[0x2];
- __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
- __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
+ __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ RoReg8 Reserved1[0x2];
+ __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
+ __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
+ __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ RoReg8 Reserved2[0x3];
+ __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
+ RoReg8 Reserved3[0x3];
+ __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x3];
+ __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
+ RoReg8 Reserved5[0x2];
+ __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
+ __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
} Nvmctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_NVMCTRL_CAL
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,11 +59,11 @@
/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PAC_WPCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -78,11 +78,11 @@
/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PAC_WPSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -97,8 +97,8 @@
/** \brief PAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
- __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
+ __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
+ __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
} Pac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,7 +59,7 @@
/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint8_t reg; /*!< Type used for register access */
+ uint8_t reg; /*!< Type used for register access */
} PM_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -71,11 +71,11 @@
/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_SLEEP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -96,11 +96,11 @@
/* -------- PM_EXTCTRL : (PM Offset: 0x02) (R/W 8) External Reset Controller -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SETDIS:1; /*!< bit: 0 External Reset Disable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SETDIS:1; /*!< bit: 0 External Reset Disable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_EXTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -114,11 +114,11 @@
/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_CPUSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -149,11 +149,11 @@
/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_APBASEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -184,11 +184,11 @@
/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_APBBSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -219,11 +219,11 @@
/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_APBCSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -254,17 +254,17 @@
/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
- uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
- uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
- uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
- uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
- uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
- uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
- uint32_t :25; /*!< bit: 7..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
+ uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
+ uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
+ uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
+ uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
+ uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
+ uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_AHBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -290,17 +290,17 @@
/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
- uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
- uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
- uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
- uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
- uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
- uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
- uint32_t :25; /*!< bit: 7..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
+ uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
+ uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
+ uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
+ uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
+ uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
+ uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_APBAMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -326,17 +326,17 @@
/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
- uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
- uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
- uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
- uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
- uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
- uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
- uint32_t :25; /*!< bit: 7..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
+ uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
+ uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
+ uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
+ uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
+ uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
+ uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_APBBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -362,33 +362,33 @@
/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
- uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
- uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
- uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
- uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
- uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
- uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
- uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
- uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
- uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
- uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
- uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
- uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
- uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
- uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */
- uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */
- uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
- uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
- uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */
- uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
- uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */
- uint32_t AC1_:1; /*!< bit: 21 AC1 APB Clock Enable */
- uint32_t LINCTRL_:1; /*!< bit: 22 LINCTRL APB Clock Enable */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
+ uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
+ uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
+ uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
+ uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
+ uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
+ uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
+ uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
+ uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
+ uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
+ uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
+ uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
+ uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
+ uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
+ uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */
+ uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */
+ uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
+ uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
+ uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */
+ uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
+ uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */
+ uint32_t AC1_:1; /*!< bit: 21 AC1 APB Clock Enable */
+ uint32_t LINCTRL_:1; /*!< bit: 22 LINCTRL APB Clock Enable */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_APBCMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -446,11 +446,11 @@
/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -464,11 +464,11 @@
/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -482,11 +482,11 @@
/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -500,17 +500,17 @@
/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t POR:1; /*!< bit: 0 Power On Reset */
- uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
- uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t EXT:1; /*!< bit: 4 External Reset */
- uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
- uint8_t SYST:1; /*!< bit: 6 System Reset Request */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t POR:1; /*!< bit: 0 Power On Reset */
+ uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
+ uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EXT:1; /*!< bit: 4 External Reset */
+ uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
+ uint8_t SYST:1; /*!< bit: 6 System Reset Request */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_RCAUSE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -534,25 +534,25 @@
/** \brief PM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
- __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
- __IO PM_EXTCTRL_Type EXTCTRL; /**< \brief Offset: 0x02 (R/W 8) External Reset Controller */
- RoReg8 Reserved1[0x5];
- __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
- __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
- __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
- __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
- RoReg8 Reserved2[0x8];
- __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
- __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
- __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
- __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
- RoReg8 Reserved3[0x10];
- __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
- __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
- __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x1];
- __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
+ __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
+ __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
+ __IO PM_EXTCTRL_Type EXTCTRL; /**< \brief Offset: 0x02 (R/W 8) External Reset Controller */
+ RoReg8 Reserved1[0x5];
+ __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
+ __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
+ __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
+ __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
+ RoReg8 Reserved2[0x8];
+ __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
+ __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
+ __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
+ __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
+ RoReg8 Reserved3[0x10];
+ __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
+ __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
+ __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
} Pm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,10 +59,10 @@
/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -77,10 +77,10 @@
/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIRCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -95,10 +95,10 @@
/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIRSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -113,10 +113,10 @@
/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIRTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -131,10 +131,10 @@
/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -149,10 +149,10 @@
/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUTCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -167,10 +167,10 @@
/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUTSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -185,10 +185,10 @@
/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUTTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -203,10 +203,10 @@
/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_IN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -221,10 +221,10 @@
/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -239,21 +239,21 @@
/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
- uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
- uint32_t INEN:1; /*!< bit: 17 Input Enable */
- uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
- uint32_t :3; /*!< bit: 19..21 Reserved */
- uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
- uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
- uint32_t :1; /*!< bit: 29 Reserved */
- uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
- uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
+ uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
+ uint32_t INEN:1; /*!< bit: 17 Input Enable */
+ uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
+ uint32_t :3; /*!< bit: 19..21 Reserved */
+ uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
+ uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
+ uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_WRCONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -285,11 +285,11 @@
/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
- uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
+ uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PORT_PMUX_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -339,15 +339,15 @@
/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
- uint8_t INEN:1; /*!< bit: 1 Input Enable */
- uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
- uint8_t :3; /*!< bit: 3.. 5 Reserved */
- uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
+ uint8_t INEN:1; /*!< bit: 1 Input Enable */
+ uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PORT_PINCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -367,28 +367,28 @@
/** \brief PortGroup hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
- __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
- __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
- __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
- __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
- __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
- __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
- __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
- __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
- __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
- __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
- RoReg8 Reserved1[0x4];
- __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
- __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
- RoReg8 Reserved2[0x20];
+ __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
+ __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
+ __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
+ __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
+ __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
+ __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
+ __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
+ __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
+ __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
+ __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
+ __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
+ RoReg8 Reserved1[0x4];
+ __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
+ __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
+ RoReg8 Reserved2[0x20];
} PortGroup;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief PORT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
+ PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
} Port;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_PORT_IOBUS
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,16 +59,16 @@
/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
- uint16_t :3; /*!< bit: 4.. 6 Reserved */
- uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
- uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :3; /*!< bit: 4.. 6 Reserved */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE0_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -120,15 +120,15 @@
/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -178,17 +178,17 @@
/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
- uint16_t :2; /*!< bit: 4.. 5 Reserved */
- uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
- uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
- uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :2; /*!< bit: 4.. 5 Reserved */
+ uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE2_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -242,13 +242,13 @@
/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
- uint16_t :8; /*!< bit: 6..13 Reserved */
- uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
- uint16_t RREQ:1; /*!< bit: 15 Read Request */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
+ uint16_t :8; /*!< bit: 6..13 Reserved */
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_READREQ_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -267,25 +267,25 @@
/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
- uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
- uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
- uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
- uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
- uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
- uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
- uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
- uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
- uint16_t :6; /*!< bit: 9..14 Reserved */
- uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
- uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE0_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -323,26 +323,26 @@
/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
- uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
- uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
- uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
- uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
- uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
- uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
- uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
- uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
- uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
- uint16_t :5; /*!< bit: 10..14 Reserved */
- uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
- uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
+ uint16_t :5; /*!< bit: 10..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -382,25 +382,25 @@
/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
- uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
- uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
- uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
- uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
- uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
- uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
- uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
- uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
- uint16_t :6; /*!< bit: 9..14 Reserved */
- uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
- uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE2_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -438,17 +438,17 @@
/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -469,18 +469,18 @@
/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -503,17 +503,17 @@
/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -534,17 +534,17 @@
/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -565,18 +565,18 @@
/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -599,17 +599,17 @@
/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -630,17 +630,17 @@
/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
- uint8_t OVF:1; /*!< bit: 7 Overflow */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:1; /*!< bit: 0 Compare x */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -661,18 +661,18 @@
/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
- uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
- uint8_t OVF:1; /*!< bit: 7 Overflow */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -695,17 +695,17 @@
/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
- uint8_t OVF:1; /*!< bit: 7 Overflow */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t ALARM:1; /*!< bit: 0 Alarm x */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -726,11 +726,11 @@
/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -744,11 +744,11 @@
/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -762,11 +762,11 @@
/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
- uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
+ uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_FREQCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -783,10 +783,10 @@
/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE0_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -801,10 +801,10 @@
/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -819,15 +819,15 @@
/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
- uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
- uint32_t HOUR:5; /*!< bit: 12..16 Hour */
- uint32_t DAY:5; /*!< bit: 17..21 Day */
- uint32_t MONTH:4; /*!< bit: 22..25 Month */
- uint32_t YEAR:6; /*!< bit: 26..31 Year */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE2_CLOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -859,10 +859,10 @@
/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PER:16; /*!< bit: 0..15 Counter Period */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PER:16; /*!< bit: 0..15 Counter Period */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -877,10 +877,10 @@
/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE0_COMP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -895,10 +895,10 @@
/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_COMP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -913,15 +913,15 @@
/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
- uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
- uint32_t HOUR:5; /*!< bit: 12..16 Hour */
- uint32_t DAY:5; /*!< bit: 17..21 Day */
- uint32_t MONTH:4; /*!< bit: 22..25 Month */
- uint32_t YEAR:6; /*!< bit: 26..31 Year */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE2_ALARM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -951,11 +951,11 @@
/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_MASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -984,79 +984,79 @@
/** \brief RtcMode2Alarm hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
- __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
- RoReg8 Reserved1[0x3];
+ __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
+ __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
+ RoReg8 Reserved1[0x3];
} RtcMode2Alarm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE0 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter with Single 32-bit Compare */
- __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
- __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
- __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
- __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
- __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
- __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
- __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
- RoReg8 Reserved2[0x3];
- __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
- RoReg8 Reserved3[0x4];
- __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
+ __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
+ __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
+ __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
+ __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
} RtcMode0;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE1 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter with Two 16-bit Compares */
- __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
- __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
- __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
- __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
- __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
- __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
- __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
- RoReg8 Reserved2[0x3];
- __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
- RoReg8 Reserved3[0x2];
- __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
- RoReg8 Reserved4[0x2];
- __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
+ __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
+ __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
+ __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
+ __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
+ RoReg8 Reserved3[0x2];
+ __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
+ RoReg8 Reserved4[0x2];
+ __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
} RtcMode1;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE2 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* Clock/Calendar with Alarm */
- __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
- __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
- __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
- __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
- __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
- __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
- __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
- RoReg8 Reserved2[0x3];
- __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
- RoReg8 Reserved3[0x4];
- RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
+ __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
+ __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
+ __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
+ __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
+ RoReg8 Reserved3[0x4];
+ RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
} RtcMode2;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
- RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
- RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
+ RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
+ RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
+ RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
} Rtc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,26 +59,26 @@
/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
- uint32_t :3; /*!< bit: 17..19 Reserved */
- uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
- uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
- uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
- uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
- uint32_t :1; /*!< bit: 26 Reserved */
- uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
- uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
- uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -130,26 +130,26 @@
/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
- uint32_t :3; /*!< bit: 17..19 Reserved */
- uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
- uint32_t :1; /*!< bit: 22 Reserved */
- uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
- uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
- uint32_t :1; /*!< bit: 26 Reserved */
- uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
- uint32_t :2; /*!< bit: 28..29 Reserved */
- uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -196,25 +196,25 @@
/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
- uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
- uint32_t :7; /*!< bit: 9..15 Reserved */
- uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
- uint32_t :2; /*!< bit: 18..19 Reserved */
- uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
- uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
- uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
- uint32_t DORD:1; /*!< bit: 30 Data Order */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -264,26 +264,26 @@
/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
- uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
- uint32_t :4; /*!< bit: 9..12 Reserved */
- uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
- uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
- uint32_t :2; /*!< bit: 18..19 Reserved */
- uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
- uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
- uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
- uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
- uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
- uint32_t DORD:1; /*!< bit: 30 Data Order */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :4; /*!< bit: 9..12 Reserved */
+ uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
+ uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
+ uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_USART_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -339,16 +339,16 @@
/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
- uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
- uint32_t :6; /*!< bit: 10..15 Reserved */
- uint32_t CMD:2; /*!< bit: 16..17 Command */
- uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -369,18 +369,18 @@
/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
- uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
- uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
- uint32_t :3; /*!< bit: 11..13 Reserved */
- uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
- uint32_t CMD:2; /*!< bit: 16..17 Command */
- uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
+ uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
+ uint32_t :3; /*!< bit: 11..13 Reserved */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -406,20 +406,20 @@
/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
- uint32_t :3; /*!< bit: 3.. 5 Reserved */
- uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
- uint32_t :2; /*!< bit: 7.. 8 Reserved */
- uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
- uint32_t :3; /*!< bit: 10..12 Reserved */
- uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
- uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
- uint32_t :1; /*!< bit: 16 Reserved */
- uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
+ uint32_t :2; /*!< bit: 7.. 8 Reserved */
+ uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
+ uint32_t :3; /*!< bit: 10..12 Reserved */
+ uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -445,22 +445,22 @@
/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
- uint32_t :3; /*!< bit: 3.. 5 Reserved */
- uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
- uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
- uint32_t ENC:1; /*!< bit: 10 Encoding Format */
- uint32_t :2; /*!< bit: 11..12 Reserved */
- uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
- uint32_t :2; /*!< bit: 14..15 Reserved */
- uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
- uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
+ uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
+ uint32_t ENC:1; /*!< bit: 10 Encoding Format */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_USART_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -489,13 +489,13 @@
/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
- uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
- uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
- uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
+ uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
+ uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_BAUD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -519,10 +519,10 @@
/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_BAUD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -537,21 +537,21 @@
/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
- } bit; /*!< Structure used for bit access */
- struct { // FRAC mode
- uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
- uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
- } FRAC; /*!< Structure used for FRAC */
- struct { // FRACFP mode
- uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
- uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
- } FRACFP; /*!< Structure used for FRACFP */
- struct { // USARTFP mode
- uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
- } USARTFP; /*!< Structure used for USARTFP */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ struct { // FRAC mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRAC; /*!< Structure used for FRAC */
+ struct { // FRACFP mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRACFP; /*!< Structure used for FRACFP */
+ struct { // USARTFP mode
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } USARTFP; /*!< Structure used for USARTFP */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_USART_BAUD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -590,10 +590,10 @@
/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_RXPL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -608,13 +608,13 @@
/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
- uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -632,14 +632,14 @@
/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
- uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
- uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -659,15 +659,15 @@
/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
- uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -689,17 +689,17 @@
/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
- uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
- uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
- uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
- uint8_t :1; /*!< bit: 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -725,13 +725,13 @@
/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
- uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -749,14 +749,14 @@
/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
- uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
- uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -776,15 +776,15 @@
/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
- uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -806,17 +806,17 @@
/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
- uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
- uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
- uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
- uint8_t :1; /*!< bit: 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -842,13 +842,13 @@
/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
- uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -866,14 +866,14 @@
/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
- uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
- uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -893,15 +893,15 @@
/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
- uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -923,17 +923,17 @@
/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
- uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
- uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
- uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
- uint8_t :1; /*!< bit: 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -959,20 +959,20 @@
/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
- uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
- uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
- uint16_t :1; /*!< bit: 3 Reserved */
- uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
- uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
- uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
- uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
- uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
- uint16_t LENERR:1; /*!< bit: 10 Length Error */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t LENERR:1; /*!< bit: 10 Length Error */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_I2CM_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1003,21 +1003,21 @@
/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
- uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
- uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
- uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
- uint16_t SR:1; /*!< bit: 4 Repeated Start */
- uint16_t :1; /*!< bit: 5 Reserved */
- uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
- uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
- uint16_t :1; /*!< bit: 8 Reserved */
- uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
- uint16_t HS:1; /*!< bit: 10 High Speed */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
+ uint16_t SR:1; /*!< bit: 4 Repeated Start */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t :1; /*!< bit: 8 Reserved */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t HS:1; /*!< bit: 10 High Speed */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_I2CS_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1047,12 +1047,12 @@
/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
- uint16_t :13; /*!< bit: 3..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t :13; /*!< bit: 3..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_SPI_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1066,16 +1066,16 @@
/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PERR:1; /*!< bit: 0 Parity Error */
- uint16_t FERR:1; /*!< bit: 1 Frame Error */
- uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
- uint16_t CTS:1; /*!< bit: 3 Clear To Send */
- uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
- uint16_t COLL:1; /*!< bit: 5 Collision Detected */
- uint16_t :10; /*!< bit: 6..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PERR:1; /*!< bit: 0 Parity Error */
+ uint16_t FERR:1; /*!< bit: 1 Frame Error */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t CTS:1; /*!< bit: 3 Clear To Send */
+ uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
+ uint16_t COLL:1; /*!< bit: 5 Collision Detected */
+ uint16_t :10; /*!< bit: 6..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_USART_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1099,13 +1099,13 @@
/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1123,12 +1123,12 @@
/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1144,13 +1144,13 @@
/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1168,13 +1168,13 @@
/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_USART_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1192,16 +1192,16 @@
/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
- uint32_t :2; /*!< bit: 11..12 Reserved */
- uint32_t LENEN:1; /*!< bit: 13 Length Enable */
- uint32_t HS:1; /*!< bit: 14 High Speed Mode */
- uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
- uint32_t LEN:8; /*!< bit: 16..23 Length */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t LENEN:1; /*!< bit: 13 Length Enable */
+ uint32_t HS:1; /*!< bit: 14 High Speed Mode */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t LEN:8; /*!< bit: 16..23 Length */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1225,16 +1225,16 @@
/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
- uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
- uint32_t :4; /*!< bit: 11..14 Reserved */
- uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
- uint32_t :1; /*!< bit: 16 Reserved */
- uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
+ uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
+ uint32_t :4; /*!< bit: 11..14 Reserved */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1256,13 +1256,13 @@
/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1280,10 +1280,10 @@
/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1298,10 +1298,10 @@
/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1316,11 +1316,11 @@
/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */
- uint32_t :23; /*!< bit: 9..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */
+ uint32_t :23; /*!< bit: 9..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1335,11 +1335,11 @@
/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_USART_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1354,11 +1354,11 @@
/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1372,11 +1372,11 @@
/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1390,11 +1390,11 @@
/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1408,101 +1408,101 @@
/** \brief SERCOM_I2CM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* I2C Master Mode */
- __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
- __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
- RoReg8 Reserved1[0x4];
- __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
- RoReg8 Reserved2[0x4];
- __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
- RoReg8 Reserved5[0x1];
- __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
- __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
- RoReg8 Reserved6[0x4];
- __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
- __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
- RoReg8 Reserved7[0x7];
- __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
+ __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
+ __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
+ RoReg8 Reserved2[0x4];
+ __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
+ __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
+ __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
+ RoReg8 Reserved7[0x7];
+ __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
} SercomI2cm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief SERCOM_I2CS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* I2C Slave Mode */
- __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
- __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
- RoReg8 Reserved1[0xC];
- __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
- RoReg8 Reserved2[0x1];
- __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
- __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
- RoReg8 Reserved5[0x4];
- __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
- __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
+ __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
+ __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
+ RoReg8 Reserved1[0xC];
+ __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
+ RoReg8 Reserved2[0x1];
+ __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
+ __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
+ RoReg8 Reserved5[0x4];
+ __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
+ __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
} SercomI2cs;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief SERCOM_SPI hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* SPI Mode */
- __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
- __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
- RoReg8 Reserved1[0x4];
- __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
- RoReg8 Reserved2[0x7];
- __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
- RoReg8 Reserved5[0x1];
- __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
- __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
- RoReg8 Reserved6[0x4];
- __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
- __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
- RoReg8 Reserved7[0x4];
- __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
+ __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
+ __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
+ RoReg8 Reserved2[0x7];
+ __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
+ __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
+ __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
+ RoReg8 Reserved7[0x4];
+ __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
} SercomSpi;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief SERCOM_USART hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USART Mode */
- __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
- __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
- RoReg8 Reserved1[0x4];
- __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
- __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
- RoReg8 Reserved2[0x5];
- __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
- RoReg8 Reserved5[0x1];
- __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
- __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
- RoReg8 Reserved6[0x8];
- __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
- RoReg8 Reserved7[0x6];
- __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
+ __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
+ __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
+ __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
+ RoReg8 Reserved2[0x5];
+ __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
+ __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
+ RoReg8 Reserved6[0x8];
+ __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
+ RoReg8 Reserved7[0x6];
+ __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
} SercomUsart;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
- SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
- SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
- SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
+ SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
+ SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
+ SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
+ SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
} Sercom;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,26 +59,26 @@
/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
- uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
- uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
- uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
- uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
- uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
- uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
- uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
- uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
- uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
- uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
- uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
- uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
- uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -120,26 +120,26 @@
/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
- uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
- uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
- uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
- uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
- uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
- uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
- uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
- uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
- uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
- uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
- uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
- uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
- uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -181,26 +181,26 @@
/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
- uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
- uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
- uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
- uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
- uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
- uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
- uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
- uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
- uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
- uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
- uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
- uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
- uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -242,26 +242,26 @@
/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
- uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
- uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
- uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
- uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
- uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
- uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
- uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
- uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
- uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
- uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
- uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
- uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
- uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_PCLKSR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -303,18 +303,18 @@
/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
- uint16_t :3; /*!< bit: 3.. 5 Reserved */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
- uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
- uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t :3; /*!< bit: 3.. 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
+ uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
+ uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_XOSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -352,21 +352,21 @@
/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
- uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
- uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
- uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
- uint16_t :1; /*!< bit: 11 Reserved */
- uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
- uint16_t :3; /*!< bit: 13..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
+ uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
+ uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_XOSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -397,22 +397,22 @@
/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
- uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
- uint32_t :2; /*!< bit: 4.. 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
+ uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
+ uint32_t :2; /*!< bit: 4.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_OSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -442,12 +442,12 @@
/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
- uint8_t :2; /*!< bit: 5.. 6 Reserved */
- uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */
+ uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_OSCULP32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -464,19 +464,19 @@
/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint32_t :4; /*!< bit: 2.. 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
- uint32_t :6; /*!< bit: 10..15 Reserved */
- uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
- uint32_t :2; /*!< bit: 28..29 Reserved */
- uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t :4; /*!< bit: 2.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_OSC8M_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -519,22 +519,22 @@
/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
- uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
- uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
- uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
- uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
- uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
- uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
- uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
+ uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
+ uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
+ uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
+ uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
+ uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
+ uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
+ uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -568,12 +568,12 @@
/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
- uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
- uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
+ uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
+ uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLVAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -594,12 +594,12 @@
/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
- uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
- uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
+ uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
+ uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLMUL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -620,11 +620,11 @@
/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t READREQ:1; /*!< bit: 7 Read Request */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t READREQ:1; /*!< bit: 7 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLSYNC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -638,22 +638,22 @@
/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t HYST:1; /*!< bit: 2 Hysteresis */
- uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
- uint32_t :1; /*!< bit: 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t MODE:1; /*!< bit: 8 Operation Mode */
- uint32_t CEN:1; /*!< bit: 9 Clock Enable */
- uint32_t :2; /*!< bit: 10..11 Reserved */
- uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
- uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t HYST:1; /*!< bit: 2 Hysteresis */
+ uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MODE:1; /*!< bit: 8 Operation Mode */
+ uint32_t CEN:1; /*!< bit: 9 Clock Enable */
+ uint32_t :2; /*!< bit: 10..11 Reserved */
+ uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
+ uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_BOD33_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -722,14 +722,14 @@
/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :6; /*!< bit: 0.. 5 Reserved */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t :6; /*!< bit: 7..12 Reserved */
- uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :6; /*!< bit: 0.. 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t :6; /*!< bit: 7..12 Reserved */
+ uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_VREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -745,15 +745,15 @@
/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
- uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
- uint32_t :13; /*!< bit: 3..15 Reserved */
- uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
+ uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
+ uint32_t :13; /*!< bit: 3..15 Reserved */
+ uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_VREF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -772,14 +772,14 @@
/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -797,13 +797,13 @@
/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLRATIO_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -821,20 +821,20 @@
/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
- uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
- uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
- uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
- uint32_t :2; /*!< bit: 6.. 7 Reserved */
- uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
+ uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
+ uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
+ uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -888,14 +888,14 @@
/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
- uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
- uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
- uint8_t DIV:1; /*!< bit: 3 Divider Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
+ uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
+ uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
+ uint8_t DIV:1; /*!< bit: 3 Divider Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -915,34 +915,34 @@
/** \brief SYSCTRL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
- __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
- __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
- __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
- __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
- RoReg8 Reserved1[0x2];
- __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
- RoReg8 Reserved2[0x2];
- __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
- __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
- RoReg8 Reserved3[0x3];
- __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
- __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
- RoReg8 Reserved4[0x2];
- __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
- __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
- __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
- RoReg8 Reserved5[0x3];
- __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
- RoReg8 Reserved6[0x4];
- __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
- RoReg8 Reserved7[0x2];
- __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
- __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
- RoReg8 Reserved8[0x3];
- __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
- __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
- __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
+ __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+ __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+ __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+ __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
+ __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
+ RoReg8 Reserved1[0x2];
+ __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
+ RoReg8 Reserved2[0x2];
+ __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
+ __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+ RoReg8 Reserved3[0x3];
+ __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
+ __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
+ RoReg8 Reserved4[0x2];
+ __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
+ __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
+ __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
+ RoReg8 Reserved5[0x3];
+ __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
+ RoReg8 Reserved6[0x4];
+ __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
+ RoReg8 Reserved7[0x2];
+ __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
+ __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
+ RoReg8 Reserved8[0x3];
+ __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
+ __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
+ __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
} Sysctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,19 +59,19 @@
/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
- uint16_t :1; /*!< bit: 4 Reserved */
- uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
- uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
- uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -137,13 +137,13 @@
/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
- uint16_t :9; /*!< bit: 5..13 Reserved */
- uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
- uint16_t RREQ:1; /*!< bit: 15 Read Request */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
+ uint16_t :9; /*!< bit: 5..13 Reserved */
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_READREQ_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -162,14 +162,14 @@
/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t :3; /*!< bit: 3.. 5 Reserved */
- uint8_t CMD:2; /*!< bit: 6.. 7 Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -194,14 +194,14 @@
/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t :3; /*!< bit: 3.. 5 Reserved */
- uint8_t CMD:2; /*!< bit: 6.. 7 Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -226,21 +226,21 @@
/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
- uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
- uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
+ uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
+ uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_CTRLC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -266,11 +266,11 @@
/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -284,24 +284,24 @@
/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
- uint16_t :1; /*!< bit: 3 Reserved */
- uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
- uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
- uint16_t :3; /*!< bit: 9..11 Reserved */
- uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
- uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :12; /*!< bit: 0..11 Reserved */
- uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
+ uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
+ uint16_t :3; /*!< bit: 9..11 Reserved */
+ uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
+ uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :12; /*!< bit: 0..11 Reserved */
+ uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -341,21 +341,21 @@
/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :1; /*!< bit: 2 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
- uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -380,21 +380,21 @@
/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :1; /*!< bit: 2 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
- uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -419,21 +419,21 @@
/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t OVF:1; /*!< bit: 0 Overflow */
- uint8_t ERR:1; /*!< bit: 1 Error */
- uint8_t :1; /*!< bit: 2 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
- uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
- uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow */
+ uint8_t ERR:1; /*!< bit: 1 Error */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -458,14 +458,14 @@
/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :3; /*!< bit: 0.. 2 Reserved */
- uint8_t STOP:1; /*!< bit: 3 Stop */
- uint8_t SLAVE:1; /*!< bit: 4 Slave */
- uint8_t :2; /*!< bit: 5.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :3; /*!< bit: 0.. 2 Reserved */
+ uint8_t STOP:1; /*!< bit: 3 Stop */
+ uint8_t SLAVE:1; /*!< bit: 4 Slave */
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -483,10 +483,10 @@
/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -501,10 +501,10 @@
/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -519,10 +519,10 @@
/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -537,10 +537,10 @@
/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -555,10 +555,10 @@
/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -573,10 +573,10 @@
/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -591,10 +591,10 @@
/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -609,76 +609,76 @@
/** \brief TC_COUNT8 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 8-bit Counter Mode */
- __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
- RoReg8 Reserved1[0x1];
- __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
- RoReg8 Reserved2[0x1];
- __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
- __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
- __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
- __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
- __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
- RoReg8 Reserved3[0x3];
- __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
- RoReg8 Reserved4[0x3];
- __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
+ RoReg8 Reserved3[0x3];
+ __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
+ RoReg8 Reserved4[0x3];
+ __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
} TcCount8;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT16 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter Mode */
- __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
- RoReg8 Reserved1[0x1];
- __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
- RoReg8 Reserved2[0x1];
- __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
- __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
- __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
- __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
- __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
- RoReg8 Reserved3[0x6];
- __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
+ RoReg8 Reserved3[0x6];
+ __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
} TcCount16;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT32 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter Mode */
- __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
- RoReg8 Reserved1[0x1];
- __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
- RoReg8 Reserved2[0x1];
- __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
- __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
- __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
- __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
- __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
- RoReg8 Reserved3[0x4];
- __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
} TcCount32;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
- TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
- TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
+ TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
+ TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
+ TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
} Tc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,29 +59,29 @@
/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t :3; /*!< bit: 2.. 4 Reserved */
- uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
- uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
- uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
- uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
- uint32_t :9; /*!< bit: 15..23 Reserved */
- uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
- uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
- uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
- uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :24; /*!< bit: 0..23 Reserved */
- uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :3; /*!< bit: 2.. 4 Reserved */
+ uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
+ uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
+ uint32_t :9; /*!< bit: 15..23 Reserved */
+ uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
+ uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
+ uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
+ uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :24; /*!< bit: 0..23 Reserved */
+ uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -151,14 +151,14 @@
/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
- uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -200,14 +200,14 @@
/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
- uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -249,37 +249,37 @@
/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
- uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
- uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
- uint32_t STATUS:1; /*!< bit: 3 Status Busy */
- uint32_t COUNT:1; /*!< bit: 4 Count Busy */
- uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
- uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
- uint32_t PER:1; /*!< bit: 7 Period busy */
- uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
- uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
- uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
- uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
- uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
- uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
- uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
- uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
- uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
- uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
- uint32_t :7; /*!< bit: 12..18 Reserved */
- uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
+ uint32_t STATUS:1; /*!< bit: 3 Status Busy */
+ uint32_t COUNT:1; /*!< bit: 4 Count Busy */
+ uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
+ uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
+ uint32_t PER:1; /*!< bit: 7 Period busy */
+ uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
+ uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
+ uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
+ uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
+ uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
+ uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
+ uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
+ uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
+ uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
+ uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
+ uint32_t :7; /*!< bit: 12..18 Reserved */
+ uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -335,22 +335,22 @@
/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
- uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
- uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
- uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
- uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
- uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
- uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
- uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_FCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -435,22 +435,22 @@
/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
- uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
- uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
- uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
- uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
- uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
- uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
- uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_FCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -535,23 +535,23 @@
/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
- uint32_t :6; /*!< bit: 2.. 7 Reserved */
- uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
- uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
- uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
- uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
- uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
+ uint32_t :6; /*!< bit: 2.. 7 Reserved */
+ uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
+ uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
+ uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
+ uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
+ uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WEXCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -583,41 +583,41 @@
/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
- uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
- uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
- uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
- uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
- uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
- uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
- uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
- uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
- uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
- uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
- uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
- uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
- uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
- uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
- uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
- uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
- uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
- uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
- uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
- uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
- uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
- uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
- uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
- uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
- uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
- uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
- uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
+ uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
+ uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
+ uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
+ uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
+ uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
+ uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
+ uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
+ uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
+ uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
+ uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
+ uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
+ uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
+ uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
+ uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
+ uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
+ uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
+ uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
+ uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
+ uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
+ uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
+ uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
+ uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
+ uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
+ uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
+ uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
+ uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
+ uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_DRVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -692,13 +692,13 @@
/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -714,39 +714,39 @@
/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
- uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
- uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
- uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
- uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
- uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
- uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
- uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
- uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
- uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
- uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
- uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
- uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
- uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
- uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
- uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :12; /*!< bit: 0..11 Reserved */
- uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
- uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
- uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
+ uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
+ uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
+ uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
+ uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
+ uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
+ uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
+ uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
+ uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
+ uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
+ uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
+ uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
+ uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
+ uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
+ uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
+ uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :12; /*!< bit: 0..11 Reserved */
+ uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
+ uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
+ uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -847,29 +847,29 @@
/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
- uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
- uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
- uint32_t :7; /*!< bit: 4..10 Reserved */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -910,29 +910,29 @@
/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
- uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
- uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
- uint32_t :7; /*!< bit: 4..10 Reserved */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -973,29 +973,29 @@
/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow */
- uint32_t TRG:1; /*!< bit: 1 Retrigger */
- uint32_t CNT:1; /*!< bit: 2 Counter */
- uint32_t ERR:1; /*!< bit: 3 Error */
- uint32_t :7; /*!< bit: 4..10 Reserved */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger */
+ uint32_t CNT:1; /*!< bit: 2 Counter */
+ uint32_t ERR:1; /*!< bit: 3 Error */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1036,42 +1036,42 @@
/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t STOP:1; /*!< bit: 0 Stop */
- uint32_t IDX:1; /*!< bit: 1 Ramp */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
- uint32_t SLAVE:1; /*!< bit: 4 Slave */
- uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
- uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
- uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
- uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
- uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
- uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
- uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
- uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
- uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
- uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
- uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
- uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
- uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
- uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t STOP:1; /*!< bit: 0 Stop */
+ uint32_t IDX:1; /*!< bit: 1 Ramp */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
+ uint32_t SLAVE:1; /*!< bit: 4 Slave */
+ uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
+ uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
+ uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
+ uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
+ uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
+ uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
+ uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
+ uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
+ uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
+ uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
+ uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
+ uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
+ uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
+ uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1135,26 +1135,26 @@
/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t :4; /*!< bit: 0.. 3 Reserved */
- uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t :5; /*!< bit: 0.. 4 Reserved */
- uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t :6; /*!< bit: 0.. 5 Reserved */
- uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t :4; /*!< bit: 0.. 3 Reserved */
+ uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t :6; /*!< bit: 0.. 5 Reserved */
+ uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1187,29 +1187,29 @@
/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
- uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
- uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
- uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
- uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
- uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
- uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
- uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
- uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
- uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
- uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
- uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
- uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
- uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
- uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
- uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
- uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
+ uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
+ uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
+ uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
+ uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
+ uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
+ uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
+ uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
+ uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
+ uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
+ uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
+ uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
+ uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
+ uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
+ uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
+ uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
+ uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TCC_PATT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1259,38 +1259,38 @@
/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
- uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
- uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
- uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
- uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
- uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
- uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
- uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
- uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
- uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
- uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
+ uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
+ uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
+ uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
+ uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
+ uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
+ uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
+ uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
+ uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
+ uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
+ uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WAVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1363,26 +1363,26 @@
/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
- uint32_t PER:20; /*!< bit: 4..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
- uint32_t PER:19; /*!< bit: 5..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
- uint32_t PER:18; /*!< bit: 6..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t PER:24; /*!< bit: 0..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t PER:20; /*!< bit: 4..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t PER:19; /*!< bit: 5..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t PER:18; /*!< bit: 6..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PER:24; /*!< bit: 0..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1424,26 +1424,26 @@
/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
- uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
- uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
- uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1485,29 +1485,29 @@
/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
- uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
- uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
- uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
- uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
- uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
- uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
- uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
- uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
- uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
- uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
- uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
- uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
- uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
- uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
- uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
- uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
+ uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
+ uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
+ uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
+ uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
+ uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
+ uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
+ uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
+ uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
+ uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
+ uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
+ uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
+ uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
+ uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
+ uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
+ uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
+ uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TCC_PATTB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1557,38 +1557,38 @@
/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
- uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
- uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
- uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
- uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
- uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
- uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
- uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
- uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
- uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
- uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
+ uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
+ uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
+ uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
+ uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
+ uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
+ uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
+ uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
+ uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
+ uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
+ uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WAVEB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1661,26 +1661,26 @@
/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
- uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
- uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
- uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_PERB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1722,26 +1722,26 @@
/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
- uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
- uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
- uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CCB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1783,35 +1783,35 @@
/** \brief TCC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
- __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- RoReg8 Reserved1[0x2];
- __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
- __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
- __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
- __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
- __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
- RoReg8 Reserved2[0x2];
- __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
- RoReg8 Reserved3[0x1];
- __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
- __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
- __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
- __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
- __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
- __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
- __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
- RoReg8 Reserved4[0x2];
- __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
- __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
- __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
- RoReg8 Reserved5[0x10];
- __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
- RoReg8 Reserved6[0x2];
- __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
- __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
- __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+ __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ RoReg8 Reserved1[0x2];
+ __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
+ __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+ __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+ __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+ __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+ RoReg8 Reserved2[0x2];
+ __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
+ RoReg8 Reserved3[0x1];
+ __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
+ __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+ __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+ __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+ __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
+ __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
+ __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
+ RoReg8 Reserved4[0x2];
+ __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+ __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
+ __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+ RoReg8 Reserved5[0x10];
+ __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+ RoReg8 Reserved6[0x2];
+ __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
+ __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+ __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
} Tcc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,29 +56,29 @@
/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t :3; /*!< bit: 2.. 4 Reserved */
- uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
- uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
- uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
- uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
- uint32_t :9; /*!< bit: 15..23 Reserved */
- uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
- uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
- uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
- uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :24; /*!< bit: 0..23 Reserved */
- uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :3; /*!< bit: 2.. 4 Reserved */
+ uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
+ uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
+ uint32_t :9; /*!< bit: 15..23 Reserved */
+ uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
+ uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
+ uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
+ uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :24; /*!< bit: 0..23 Reserved */
+ uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -148,14 +148,14 @@
/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
- uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -197,14 +197,14 @@
/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
- uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -246,37 +246,37 @@
/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
- uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
- uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
- uint32_t STATUS:1; /*!< bit: 3 Status Busy */
- uint32_t COUNT:1; /*!< bit: 4 Count Busy */
- uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
- uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
- uint32_t PER:1; /*!< bit: 7 Period busy */
- uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
- uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
- uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
- uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
- uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
- uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
- uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
- uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
- uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
- uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
- uint32_t :7; /*!< bit: 12..18 Reserved */
- uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
+ uint32_t STATUS:1; /*!< bit: 3 Status Busy */
+ uint32_t COUNT:1; /*!< bit: 4 Count Busy */
+ uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
+ uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
+ uint32_t PER:1; /*!< bit: 7 Period busy */
+ uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
+ uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
+ uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
+ uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
+ uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
+ uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
+ uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
+ uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
+ uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
+ uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
+ uint32_t :7; /*!< bit: 12..18 Reserved */
+ uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -332,22 +332,22 @@
/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
- uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
- uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
- uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
- uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
- uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
- uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
- uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_FCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -434,22 +434,22 @@
/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
- uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
- uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
- uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
- uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
- uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
- uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
- uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_FCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -536,23 +536,23 @@
/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
- uint32_t :6; /*!< bit: 2.. 7 Reserved */
- uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
- uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
- uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
- uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
- uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
+ uint32_t :6; /*!< bit: 2.. 7 Reserved */
+ uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
+ uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
+ uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
+ uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
+ uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WEXCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -584,41 +584,41 @@
/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
- uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
- uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
- uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
- uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
- uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
- uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
- uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
- uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
- uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
- uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
- uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
- uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
- uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
- uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
- uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
- uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
- uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
- uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
- uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
- uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
- uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
- uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
- uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
- uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
- uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
- uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
- uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
+ uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
+ uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
+ uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
+ uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
+ uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
+ uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
+ uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
+ uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
+ uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
+ uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
+ uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
+ uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
+ uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
+ uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
+ uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
+ uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
+ uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
+ uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
+ uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
+ uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
+ uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
+ uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
+ uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
+ uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
+ uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
+ uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
+ uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_DRVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -693,13 +693,13 @@
/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -715,39 +715,39 @@
/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
- uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
- uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
- uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
- uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
- uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
- uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
- uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
- uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
- uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
- uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
- uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
- uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
- uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
- uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
- uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :12; /*!< bit: 0..11 Reserved */
- uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
- uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
- uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
+ uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
+ uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
+ uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
+ uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
+ uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
+ uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
+ uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
+ uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
+ uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
+ uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
+ uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
+ uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
+ uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
+ uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
+ uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :12; /*!< bit: 0..11 Reserved */
+ uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
+ uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
+ uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -850,30 +850,30 @@
/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
- uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
- uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
- uint32_t :6; /*!< bit: 4.. 9 Reserved */
- uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :6; /*!< bit: 4.. 9 Reserved */
+ uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -916,30 +916,30 @@
/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
- uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
- uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
- uint32_t :6; /*!< bit: 4.. 9 Reserved */
- uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :6; /*!< bit: 4.. 9 Reserved */
+ uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -982,30 +982,30 @@
/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow */
- uint32_t TRG:1; /*!< bit: 1 Retrigger */
- uint32_t CNT:1; /*!< bit: 2 Counter */
- uint32_t ERR:1; /*!< bit: 3 Error */
- uint32_t :6; /*!< bit: 4.. 9 Reserved */
- uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger */
+ uint32_t CNT:1; /*!< bit: 2 Counter */
+ uint32_t ERR:1; /*!< bit: 3 Error */
+ uint32_t :6; /*!< bit: 4.. 9 Reserved */
+ uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1048,42 +1048,42 @@
/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t STOP:1; /*!< bit: 0 Stop */
- uint32_t IDX:1; /*!< bit: 1 Ramp */
- uint32_t UFS:1; /*!< bit: 2 Non-Recoverable Update Fault State */
- uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
- uint32_t SLAVE:1; /*!< bit: 4 Slave */
- uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
- uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
- uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
- uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
- uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
- uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
- uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
- uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
- uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
- uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
- uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
- uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
- uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
- uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t STOP:1; /*!< bit: 0 Stop */
+ uint32_t IDX:1; /*!< bit: 1 Ramp */
+ uint32_t UFS:1; /*!< bit: 2 Non-Recoverable Update Fault State */
+ uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
+ uint32_t SLAVE:1; /*!< bit: 4 Slave */
+ uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
+ uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
+ uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
+ uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
+ uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
+ uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
+ uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
+ uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
+ uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
+ uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
+ uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
+ uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
+ uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
+ uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1149,26 +1149,26 @@
/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t :4; /*!< bit: 0.. 3 Reserved */
- uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t :5; /*!< bit: 0.. 4 Reserved */
- uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t :6; /*!< bit: 0.. 5 Reserved */
- uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t :4; /*!< bit: 0.. 3 Reserved */
+ uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t :6; /*!< bit: 0.. 5 Reserved */
+ uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1201,29 +1201,29 @@
/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
- uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
- uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
- uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
- uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
- uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
- uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
- uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
- uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
- uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
- uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
- uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
- uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
- uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
- uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
- uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
- uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
+ uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
+ uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
+ uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
+ uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
+ uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
+ uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
+ uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
+ uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
+ uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
+ uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
+ uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
+ uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
+ uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
+ uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
+ uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
+ uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TCC_PATT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1273,38 +1273,38 @@
/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
- uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
- uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
- uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
- uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
- uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
- uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
- uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
- uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
- uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
- uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
+ uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
+ uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
+ uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
+ uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
+ uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
+ uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
+ uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
+ uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
+ uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
+ uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WAVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1379,26 +1379,26 @@
/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
- uint32_t PER:20; /*!< bit: 4..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
- uint32_t PER:19; /*!< bit: 5..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
- uint32_t PER:18; /*!< bit: 6..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t PER:24; /*!< bit: 0..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t PER:20; /*!< bit: 4..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t PER:19; /*!< bit: 5..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t PER:18; /*!< bit: 6..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PER:24; /*!< bit: 0..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1440,26 +1440,26 @@
/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
- uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
- uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
- uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1501,29 +1501,29 @@
/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
- uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
- uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
- uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
- uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
- uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
- uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
- uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
- uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
- uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
- uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
- uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
- uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
- uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
- uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
- uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
- uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
+ uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
+ uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
+ uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
+ uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
+ uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
+ uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
+ uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
+ uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
+ uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
+ uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
+ uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
+ uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
+ uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
+ uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
+ uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
+ uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TCC_PATTB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1573,38 +1573,38 @@
/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
- uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
- uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
- uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
- uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
- uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
- uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
- uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
- uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
- uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
- uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
+ uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
+ uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
+ uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
+ uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
+ uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
+ uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
+ uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
+ uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
+ uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
+ uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WAVEB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1679,26 +1679,26 @@
/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
- uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
- uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
- uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_PERB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1740,26 +1740,26 @@
/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
- uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
- uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
- uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CCB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1801,35 +1801,35 @@
/** \brief TCC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
- __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- RoReg8 Reserved1[0x2];
- __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
- __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
- __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
- __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
- __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
- RoReg8 Reserved2[0x2];
- __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
- RoReg8 Reserved3[0x1];
- __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
- __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
- __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
- __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
- __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
- __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
- __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
- RoReg8 Reserved4[0x2];
- __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
- __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
- __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
- RoReg8 Reserved5[0x10];
- __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
- RoReg8 Reserved6[0x2];
- __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
- __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
- __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+ __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ RoReg8 Reserved1[0x2];
+ __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
+ __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+ __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+ __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+ __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+ RoReg8 Reserved2[0x2];
+ __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
+ RoReg8 Reserved3[0x1];
+ __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
+ __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+ __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+ __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+ __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
+ __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
+ __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
+ RoReg8 Reserved4[0x2];
+ __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+ __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
+ __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+ RoReg8 Reserved5[0x10];
+ __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+ RoReg8 Reserved6[0x2];
+ __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
+ __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+ __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
} Tcc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,14 +59,14 @@
/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t MODE:1; /*!< bit: 7 Operating Mode */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t MODE:1; /*!< bit: 7 Operating Mode */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -90,12 +90,12 @@
/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -111,12 +111,12 @@
/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */
- uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */
+ uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_QOSCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -150,20 +150,20 @@
/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DETACH:1; /*!< bit: 0 Detach */
- uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
- uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
- uint16_t NREPLY:1; /*!< bit: 4 No Reply */
- uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
- uint16_t TSTK:1; /*!< bit: 6 Test mode K */
- uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
- uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
- uint16_t GNAK:1; /*!< bit: 9 Global NAK */
- uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DETACH:1; /*!< bit: 0 Detach */
+ uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
+ uint16_t NREPLY:1; /*!< bit: 4 No Reply */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
+ uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
+ uint16_t GNAK:1; /*!< bit: 9 Global NAK */
+ uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -213,21 +213,21 @@
/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
- uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
- uint16_t :1; /*!< bit: 4 Reserved */
- uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
- uint16_t TSTK:1; /*!< bit: 6 Test mode K */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
- uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
- uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
- uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
+ uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
+ uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
+ uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -260,11 +260,11 @@
/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
- uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
+ uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_DADD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -281,12 +281,12 @@
/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_HSOFC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -303,13 +303,13 @@
/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
- uint8_t :2; /*!< bit: 4.. 5 Reserved */
- uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -339,13 +339,13 @@
/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
- uint8_t :2; /*!< bit: 4.. 5 Reserved */
- uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -363,11 +363,11 @@
/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_FSMSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -396,13 +396,13 @@
/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
- uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
- uint16_t :1; /*!< bit: 14 Reserved */
- uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :1; /*!< bit: 14 Reserved */
+ uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_FNUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -422,12 +422,12 @@
/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
- uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_FNUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -445,10 +445,10 @@
/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_FLENHIGH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -463,20 +463,20 @@
/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
- uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
- uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
- uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
- uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
- uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
- uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -508,19 +508,19 @@
/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
- uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
- uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
- uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
- uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
+ uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
+ uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -548,20 +548,20 @@
/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
- uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
- uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
- uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
- uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
- uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
- uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -593,19 +593,19 @@
/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
- uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
- uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
- uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
- uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
+ uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -633,20 +633,20 @@
/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
- uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
- uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
- uint16_t EORST:1; /*!< bit: 3 End of Reset */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
- uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
- uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
- uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -678,19 +678,19 @@
/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
- uint16_t RST:1; /*!< bit: 3 Bus Reset */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
- uint16_t DNRSM:1; /*!< bit: 5 Downstream */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
- uint16_t DCONN:1; /*!< bit: 8 Device Connection */
- uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
+ uint16_t RST:1; /*!< bit: 3 Bus Reset */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ uint16_t DNRSM:1; /*!< bit: 5 Downstream */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ uint16_t DCONN:1; /*!< bit: 8 Device Connection */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -718,22 +718,22 @@
/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
- uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
- uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
- uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
- uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
- uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
- uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
- uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTSMRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -764,22 +764,22 @@
/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
- uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
- uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
- uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
- uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
- uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
- uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
- uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_PINTSMRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -810,10 +810,10 @@
/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_DESCADD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -828,15 +828,15 @@
/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
- uint16_t :1; /*!< bit: 5 Reserved */
- uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
- uint16_t :1; /*!< bit: 11 Reserved */
- uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_PADCAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -857,13 +857,13 @@
/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
- uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
+ uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -883,13 +883,13 @@
/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
- uint8_t BK:1; /*!< bit: 2 Pipe Bank */
- uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
+ uint8_t BK:1; /*!< bit: 2 Pipe Bank */
+ uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -909,10 +909,10 @@
/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_BINTERVAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -927,22 +927,22 @@
/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
- uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
- uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
- uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPSTATUSCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -971,17 +971,17 @@
/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PSTATUSCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1003,22 +1003,22 @@
/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
- uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
- uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPSTATUSSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1047,17 +1047,17 @@
/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PSTATUSSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1079,22 +1079,22 @@
/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
- uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
- uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1123,17 +1123,17 @@
/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1155,24 +1155,24 @@
/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
- uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
- uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
- uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
- uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
- uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
- uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
- uint8_t :1; /*!< bit: 4 Reserved */
- uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
- uint8_t :1; /*!< bit: 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1207,20 +1207,20 @@
/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
- uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
- uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
- uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
- uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
+ uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1247,24 +1247,24 @@
/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
- uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
- uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
- uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
- uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
- uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
- uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
- uint8_t :1; /*!< bit: 4 Reserved */
- uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1299,20 +1299,20 @@
/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
- uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
- uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
- uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
- uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Disable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Disable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1339,24 +1339,24 @@
/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
- uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
- uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
- uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
- uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
- uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
- uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
- uint8_t :1; /*!< bit: 4 Reserved */
- uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1391,20 +1391,20 @@
/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
- uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
- uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
- uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
- uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1431,10 +1431,10 @@
/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_DEVICE_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1448,10 +1448,10 @@
/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_HOST_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1465,13 +1465,13 @@
/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
- uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
- uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
- uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_DEVICE_PCKSIZE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1493,13 +1493,13 @@
/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
- uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
- uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
- uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_HOST_PCKSIZE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1521,12 +1521,12 @@
/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
- uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_EXTREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1543,12 +1543,12 @@
/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
- uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_EXTREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1565,12 +1565,12 @@
/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
- uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_STATUS_BK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1585,12 +1585,12 @@
/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
- uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_STATUS_BK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1605,13 +1605,13 @@
/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
- uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
+ uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_CTRL_PIPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1632,16 +1632,16 @@
/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
- uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
- uint16_t PIDER:1; /*!< bit: 2 PID Error */
- uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
- uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
- uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
+ uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
+ uint16_t PIDER:1; /*!< bit: 2 PID Error */
+ uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
+ uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
+ uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_STATUS_PIPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1665,140 +1665,140 @@
/** \brief UsbDeviceDescBank SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
- __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
- __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
- __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
- RoReg8 Reserved1[0x5];
+ __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+ __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+ __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
+ __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+ RoReg8 Reserved1[0x5];
} UsbDeviceDescBank;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief UsbHostDescBank SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
- __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
- __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
- __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
- RoReg8 Reserved1[0x1];
- __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
- __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
+ __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+ __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
+ __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
+ __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
+ RoReg8 Reserved1[0x1];
+ __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
+ __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
} UsbHostDescBank;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief UsbDeviceEndpoint hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
- RoReg8 Reserved1[0x3];
- __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
- __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
- __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
- __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
- __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
- __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
- RoReg8 Reserved2[0x16];
+ __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
+ RoReg8 Reserved1[0x3];
+ __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
+ __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
+ __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
+ __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
+ __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+ __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+ RoReg8 Reserved2[0x16];
} UsbDeviceEndpoint;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief UsbHostPipe hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
- RoReg8 Reserved1[0x2];
- __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
- __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
- __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
- __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
- __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
- __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
- __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
- RoReg8 Reserved2[0x16];
+ __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
+ RoReg8 Reserved1[0x2];
+ __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
+ __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
+ __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
+ __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
+ __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
+ __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
+ __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
+ RoReg8 Reserved2[0x16];
} UsbHostPipe;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_DEVICE APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Device */
- __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
- RoReg8 Reserved1[0x1];
- __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
- __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
- RoReg8 Reserved2[0x4];
- __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
- __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
- RoReg8 Reserved3[0x1];
- __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
- __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
- RoReg8 Reserved4[0x2];
- __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
- RoReg8 Reserved5[0x2];
- __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
- RoReg8 Reserved6[0x2];
- __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
- RoReg8 Reserved7[0x2];
- __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
- RoReg8 Reserved8[0x2];
- __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
- RoReg8 Reserved9[0x2];
- __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
- __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
- RoReg8 Reserved10[0xD6];
- UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
+ __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
+ RoReg8 Reserved3[0x1];
+ __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
+ RoReg8 Reserved5[0x2];
+ __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
} UsbDevice;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_HOST hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Host */
- __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
- RoReg8 Reserved1[0x1];
- __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
- __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
- RoReg8 Reserved2[0x4];
- __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
- __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
- RoReg8 Reserved3[0x1];
- __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
- __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
- RoReg8 Reserved4[0x2];
- __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
- __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
- RoReg8 Reserved5[0x1];
- __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
- RoReg8 Reserved6[0x2];
- __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
- RoReg8 Reserved7[0x2];
- __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
- RoReg8 Reserved8[0x2];
- __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
- RoReg8 Reserved9[0x2];
- __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
- __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
- RoReg8 Reserved10[0xD6];
- UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
+ __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
+ RoReg8 Reserved3[0x1];
+ __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
+ __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
+ RoReg8 Reserved5[0x1];
+ __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */
} UsbHost;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_DEVICE Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Device */
- UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
+ UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
} UsbDeviceDescriptor;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_HOST Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Host */
- UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
+ UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
} UsbHostDescriptor;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_USB_DESCRIPTOR
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
- UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
+ UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
+ UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
} Usb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,14 +59,14 @@
/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -84,11 +84,11 @@
/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
- uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
+ uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -154,11 +154,11 @@
/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_EWCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -197,11 +197,11 @@
/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -215,11 +215,11 @@
/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -233,11 +233,11 @@
/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EW:1; /*!< bit: 0 Early Warning */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -251,11 +251,11 @@
/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -269,10 +269,10 @@
/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_CLEAR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -289,15 +289,15 @@
/** \brief WDT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
- __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
- __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
- RoReg8 Reserved1[0x1];
- __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
- __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
- __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
- __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
- __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
+ __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
+ __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
+ RoReg8 Reserved1[0x1];
+ __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
+ __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
+ __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
+ __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
+ __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
} Wdt;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h Fri Sep 25 12:00:11 2015 +0100 @@ -84,7 +84,7 @@ #define AC_CMP_NUM 2 // Number of comparators #define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog #define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital -#define AC_NUM_CMP 2 +#define AC_NUM_CMP 2 #define AC_PAIRS 1 // Number of pairs of comparators #endif /* _SAMD21_AC_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h Fri Sep 25 12:00:11 2015 +0100 @@ -81,7 +81,7 @@ #define AC1_CMP_NUM 2 // Number of comparators #define AC1_GCLK_ID_ANA 32 // Index of Generic Clock for analog #define AC1_GCLK_ID_DIG 31 // Index of Generic Clock for digital -#define AC1_NUM_CMP 2 +#define AC1_NUM_CMP 2 #define AC1_PAIRS 1 // Number of pairs of comparators #endif /* _SAMD21_AC1_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h Fri Sep 25 12:00:11 2015 +0100 @@ -63,7 +63,7 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for GCLK peripheral ========== */ -#define GCLK_GENDIV_BITS 16 +#define GCLK_GENDIV_BITS 16 #define GCLK_GEN_NUM 9 // Number of Generic Clock Generators #define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 #define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h Fri Sep 25 12:00:11 2015 +0100 @@ -77,16 +77,16 @@ #define NVMCTRL_AUX3_ADDRESS 0x0080A000 #define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register #define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF -#define NVMCTRL_FLASH_SIZE 65536 +#define NVMCTRL_FLASH_SIZE 65536 #define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 -#define NVMCTRL_PAGES 1024 -#define NVMCTRL_PAGE_HW 32 -#define NVMCTRL_PAGE_SIZE 64 -#define NVMCTRL_PAGE_W 16 -#define NVMCTRL_PMSB 3 -#define NVMCTRL_PSZ_BITS 6 -#define NVMCTRL_ROW_PAGES 4 -#define NVMCTRL_ROW_SIZE 256 +#define NVMCTRL_PAGES 1024 +#define NVMCTRL_PAGE_HW 32 +#define NVMCTRL_PAGE_SIZE 64 +#define NVMCTRL_PAGE_W 16 +#define NVMCTRL_PMSB 3 +#define NVMCTRL_PSZ_BITS 6 +#define NVMCTRL_ROW_PAGES 4 +#define NVMCTRL_ROW_SIZE 256 #define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 #define NVMCTRL_USER_PAGE_OFFSET 0x00800000 #define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h Fri Sep 25 12:00:11 2015 +0100 @@ -83,10 +83,10 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for PM peripheral ========== */ -#define PM_CTRL_MCSEL_DFLL48M 3 -#define PM_CTRL_MCSEL_GCLK 0 -#define PM_CTRL_MCSEL_OSC8M 1 -#define PM_CTRL_MCSEL_XOSC 2 -#define PM_PM_CLK_APB_NUM 2 +#define PM_CTRL_MCSEL_DFLL48M 3 +#define PM_CTRL_MCSEL_GCLK 0 +#define PM_CTRL_MCSEL_OSC8M 1 +#define PM_CTRL_MCSEL_XOSC 2 +#define PM_PM_CLK_APB_NUM 2 #endif /* _SAMD21_PM_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h Fri Sep 25 12:00:11 2015 +0100 @@ -149,7 +149,7 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for SBMATRIX peripheral ========== */ -#define SBMATRIX_DEFINED +#define SBMATRIX_DEFINED /* ========== Instance parameters for SBMATRIX ========== */ #define SBMATRIX_SLAVE_FLASH 0 #define SBMATRIX_SLAVE_HPB0 1
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h Fri Sep 25 12:00:11 2015 +0100 @@ -141,6 +141,6 @@ #define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger #define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core #define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM0_INT_MSB 6 +#define SERCOM0_INT_MSB 6 #endif /* _SAMD21_SERCOM0_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h Fri Sep 25 12:00:11 2015 +0100 @@ -141,6 +141,6 @@ #define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger #define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core #define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM1_INT_MSB 6 +#define SERCOM1_INT_MSB 6 #endif /* _SAMD21_SERCOM1_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h Fri Sep 25 12:00:11 2015 +0100 @@ -141,6 +141,6 @@ #define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger #define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core #define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM2_INT_MSB 6 +#define SERCOM2_INT_MSB 6 #endif /* _SAMD21_SERCOM2_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h Fri Sep 25 12:00:11 2015 +0100 @@ -141,6 +141,6 @@ #define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger #define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core #define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM3_INT_MSB 6 +#define SERCOM3_INT_MSB 6 #endif /* _SAMD21_SERCOM3_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h Fri Sep 25 12:00:11 2015 +0100 @@ -141,6 +141,6 @@ #define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger #define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core #define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM4_INT_MSB 6 +#define SERCOM4_INT_MSB 6 #endif /* _SAMD21_SERCOM4_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h Fri Sep 25 12:00:11 2015 +0100 @@ -141,6 +141,6 @@ #define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger #define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core #define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM5_INT_MSB 6 +#define SERCOM5_INT_MSB 6 #endif /* _SAMD21_SERCOM5_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h Fri Sep 25 12:00:11 2015 +0100 @@ -93,31 +93,31 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for SYSCTRL peripheral ========== */ -#define SYSCTRL_BGAP_CALIB_MSB 11 -#define SYSCTRL_BOD33_CALIB_MSB 5 -#define SYSCTRL_DFLL48M_COARSE_MSB 5 -#define SYSCTRL_DFLL48M_FINE_MSB 9 +#define SYSCTRL_BGAP_CALIB_MSB 11 +#define SYSCTRL_BOD33_CALIB_MSB 5 +#define SYSCTRL_DFLL48M_COARSE_MSB 5 +#define SYSCTRL_DFLL48M_FINE_MSB 9 #define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 #define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL #define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K -#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 -#define SYSCTRL_POR33_ENTEST_MSB 1 -#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 -#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 -#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 -#define SYSCTRL_VREF_CONTROL_MSB 48 -#define SYSCTRL_VREF_STATUS_MSB 7 -#define SYSCTRL_VREG_LEVEL_MSB 2 -#define SYSCTRL_BOD12_VERSION 0x111 -#define SYSCTRL_BOD33_VERSION 0x111 -#define SYSCTRL_DFLL48M_VERSION 0x301 -#define SYSCTRL_FDPLL_VERSION 0x111 -#define SYSCTRL_OSCULP32K_VERSION 0x111 -#define SYSCTRL_OSC8M_VERSION 0x120 -#define SYSCTRL_OSC32K_VERSION 0x112 -#define SYSCTRL_VREF_VERSION 0x201 -#define SYSCTRL_VREG_VERSION 0x201 -#define SYSCTRL_XOSC_VERSION 0x114 -#define SYSCTRL_XOSC32K_VERSION 0x113 +#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 +#define SYSCTRL_POR33_ENTEST_MSB 1 +#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 +#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 +#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 +#define SYSCTRL_VREF_CONTROL_MSB 48 +#define SYSCTRL_VREF_STATUS_MSB 7 +#define SYSCTRL_VREG_LEVEL_MSB 2 +#define SYSCTRL_BOD12_VERSION 0x111 +#define SYSCTRL_BOD33_VERSION 0x111 +#define SYSCTRL_DFLL48M_VERSION 0x301 +#define SYSCTRL_FDPLL_VERSION 0x111 +#define SYSCTRL_OSCULP32K_VERSION 0x111 +#define SYSCTRL_OSC8M_VERSION 0x120 +#define SYSCTRL_OSC32K_VERSION 0x112 +#define SYSCTRL_VREF_VERSION 0x201 +#define SYSCTRL_VREG_VERSION 0x201 +#define SYSCTRL_XOSC_VERSION 0x114 +#define SYSCTRL_XOSC32K_VERSION 0x113 #endif /* _SAMD21_SYSCTRL_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h Fri Sep 25 12:00:11 2015 +0100 @@ -106,7 +106,7 @@ #define TC3_DMAC_ID_MC_SIZE 2 #define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger #define TC3_GCLK_ID 27 // Index of Generic Clock -#define TC3_MASTER 0 +#define TC3_MASTER 0 #define TC3_OW_NUM 2 // Number of Output Waveforms #define TC3_PERIOD_EXT 0 // Period feature implemented #define TC3_SHADOW_EXT 0 // Shadow feature implemented
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h Fri Sep 25 12:00:11 2015 +0100 @@ -106,7 +106,7 @@ #define TC4_DMAC_ID_MC_SIZE 2 #define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger #define TC4_GCLK_ID 28 // Index of Generic Clock -#define TC4_MASTER 1 +#define TC4_MASTER 1 #define TC4_OW_NUM 2 // Number of Output Waveforms #define TC4_PERIOD_EXT 0 // Period feature implemented #define TC4_SHADOW_EXT 0 // Shadow feature implemented
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h Fri Sep 25 12:00:11 2015 +0100 @@ -106,7 +106,7 @@ #define TC5_DMAC_ID_MC_SIZE 2 #define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger #define TC5_GCLK_ID 28 // Index of Generic Clock -#define TC5_MASTER 0 +#define TC5_MASTER 0 #define TC5_OW_NUM 2 // Number of Output Waveforms #define TC5_PERIOD_EXT 0 // Period feature implemented #define TC5_SHADOW_EXT 0 // Shadow feature implemented
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h Fri Sep 25 12:00:11 2015 +0100 @@ -106,7 +106,7 @@ #define TC6_DMAC_ID_MC_SIZE 2 #define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger #define TC6_GCLK_ID 29 // Index of Generic Clock -#define TC6_MASTER 1 +#define TC6_MASTER 1 #define TC6_OW_NUM 2 // Number of Output Waveforms #define TC6_PERIOD_EXT 0 // Period feature implemented #define TC6_SHADOW_EXT 0 // Shadow feature implemented
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h Fri Sep 25 12:00:11 2015 +0100 @@ -106,7 +106,7 @@ #define TC7_DMAC_ID_MC_SIZE 2 #define TC7_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger #define TC7_GCLK_ID 29 // Index of Generic Clock -#define TC7_MASTER 0 +#define TC7_MASTER 0 #define TC7_OW_NUM 2 // Number of Output Waveforms #define TC7_PERIOD_EXT 0 // Period feature implemented #define TC7_SHADOW_EXT 0 // Shadow feature implemented
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h Fri Sep 25 12:00:11 2015 +0100 @@ -124,11 +124,11 @@ #define TCC0_DTI 1 // Dead-Time-Insertion feature implemented #define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1) #define TCC0_GCLK_ID 26 // Index of Generic Clock -#define TCC0_MASTER 0 +#define TCC0_MASTER 0 #define TCC0_OTMX 1 // Output Matrix feature implemented #define TCC0_OW_NUM 8 // Number of Output Waveforms #define TCC0_PG 1 // Pattern Generation feature implemented -#define TCC0_SIZE 24 +#define TCC0_SIZE 24 #define TCC0_SWAP 1 // DTI outputs swap feature implemented #define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h Fri Sep 25 12:00:11 2015 +0100 @@ -112,11 +112,11 @@ #define TCC1_DTI 0 // Dead-Time-Insertion feature implemented #define TCC1_EXT 24 // Coding of implemented extended features #define TCC1_GCLK_ID 26 // Index of Generic Clock -#define TCC1_MASTER 1 +#define TCC1_MASTER 1 #define TCC1_OTMX 0 // Output Matrix feature implemented #define TCC1_OW_NUM 4 // Number of Output Waveforms #define TCC1_PG 1 // Pattern Generation feature implemented -#define TCC1_SIZE 24 +#define TCC1_SIZE 24 #define TCC1_SWAP 0 // DTI outputs swap feature implemented #define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h Fri Sep 25 12:00:11 2015 +0100 @@ -108,11 +108,11 @@ #define TCC2_DTI 0 // Dead-Time-Insertion feature implemented #define TCC2_EXT 0 // Coding of implemented extended features #define TCC2_GCLK_ID 27 // Index of Generic Clock -#define TCC2_MASTER 0 +#define TCC2_MASTER 0 #define TCC2_OTMX 0 // Output Matrix feature implemented #define TCC2_OW_NUM 2 // Number of Output Waveforms #define TCC2_PG 0 // Pattern Generation feature implemented -#define TCC2_SIZE 16 +#define TCC2_SIZE 16 #define TCC2_SWAP 0 // DTI outputs swap feature implemented #define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h Fri Sep 25 12:00:11 2015 +0100 @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /* - * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> - */ +/* +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ #ifndef _SAMD21G17AU_PIO_ #define _SAMD21G17AU_PIO_
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h Fri Sep 25 12:00:11 2015 +0100 @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /* - * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> - */ +/* +* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> +*/ #ifndef _SAMD21G18AU_PIO_ #define _SAMD21G18AU_PIO_
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21.h Fri Sep 25 12:00:11 2015 +0100 @@ -53,55 +53,55 @@ */ #if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__) - #include "samd21e15a.h" +#include "samd21e15a.h" #elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__) - #include "samd21e16a.h" +#include "samd21e16a.h" #elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__) - #include "samd21e17a.h" +#include "samd21e17a.h" #elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__) - #include "samd21e18a.h" +#include "samd21e18a.h" #elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__) - #include "samd21g15a.h" +#include "samd21g15a.h" #elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__) - #include "samd21g16a.h" +#include "samd21g16a.h" #elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__) - #include "samd21g17a.h" +#include "samd21g17a.h" #elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__) - #include "samd21g17au.h" +#include "samd21g17au.h" #elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__) - #include "samd21g18a.h" +#include "samd21g18a.h" #elif defined (__SAMD21G18AU__) || defined(__ATSAMD21G18AU__) - #include "samd21g18au.h" +#include "samd21g18au.h" #elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__) - #include "samd21j15a.h" +#include "samd21j15a.h" #elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__) - #include "samd21j16a.h" +#include "samd21j16a.h" #elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__) - #include "samd21j17a.h" +#include "samd21j17a.h" #elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__) - #include "samd21j18a.h" +#include "samd21j18a.h" #elif defined(__SAMD21E15B__) || defined(__ATSAMD21E15B__) - #include "samd21e15b.h" +#include "samd21e15b.h" #elif defined(__SAMD21E15BU__) || defined(__ATSAMD21E15BU__) - #include "samd21e15bu.h" +#include "samd21e15bu.h" #elif defined(__SAMD21E15L__) || defined(__ATSAMD21E15L__) - #include "samd21e15l.h" +#include "samd21e15l.h" #elif defined(__SAMD21E16B__) || defined(__ATSAMD21E16B__) - #include "samd21e16b.h" +#include "samd21e16b.h" #elif defined(__SAMD21E16BU__) || defined(__ATSAMD21E16BU__) - #include "samd21e16bu.h" +#include "samd21e16bu.h" #elif defined(__SAMD21E16L__) || defined(__ATSAMD21E16L__) - #include "samd21e16l.h" +#include "samd21e16l.h" #elif defined(__SAMD21G15B__) || defined(__ATSAMD21G15B__) - #include "samd21g15b.h" +#include "samd21g15b.h" #elif defined(__SAMD21G16B__) || defined(__ATSAMD21G16B__) - #include "samd21g16b.h" +#include "samd21g16b.h" #elif defined(__SAMD21J15B__) || defined(__ATSAMD21J15B__) - #include "samd21j15b.h" +#include "samd21j15b.h" #elif defined(__SAMD21J16B__) || defined(__ATSAMD21J16B__) - #include "samd21j16b.h" +#include "samd21j16b.h" #else - #error Library does not support the specified device. +#error Library does not support the specified device. #endif #endif /* _SAMD21_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,94 +93,92 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E15A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E15A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -221,7 +219,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,95 +90,93 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E15B-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E15B Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E15B System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E15B Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E15B Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E15B External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E15B Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E15B Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E15B Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E15B Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E15B Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E15B Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E15B Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E15B Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E15B Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E15B Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E15B Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E15B Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E15B Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E15B Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E15B Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E15B Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E15B Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E15B Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E15B Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E15B-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E15B Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E15B System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E15B Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E15B Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E15B External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E15B Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E15B Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E15B Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E15B Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E15B Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E15B Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E15B Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E15B Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E15B Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E15B Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E15B Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E15B Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E15B Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E15B Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E15B Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E15B Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E15B Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E15B Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E15B Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -219,7 +217,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,95 +90,93 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E15BU-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E15BU Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E15BU System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E15BU Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E15BU Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E15BU External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E15BU Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E15BU Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E15BU Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E15BU Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E15BU Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E15BU Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E15BU Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E15BU Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E15BU Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E15BU Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E15BU Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E15BU Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E15BU Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E15BU Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E15BU Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E15BU Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E15BU Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E15BU Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E15BU Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E15BU-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E15BU Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E15BU System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E15BU Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E15BU Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E15BU External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E15BU Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E15BU Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E15BU Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E15BU Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E15BU Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E15BU Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E15BU Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E15BU Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E15BU Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E15BU Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E15BU Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E15BU Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E15BU Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E15BU Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E15BU Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E15BU Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E15BU Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E15BU Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E15BU Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -219,7 +217,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,93 +90,91 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E15L-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E15L Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E15L System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E15L Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E15L Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E15L External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E15L Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E15L Direct Memory Access Controller (DMAC) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E15L Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E15L Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E15L Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E15L Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E15L Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E15L Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E15L Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E15L Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E15L Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E15L Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E15L Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E15L Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E15L Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E15L Digital Analog Converter (DAC) */
- AC1_IRQn = 28, /**< 28 SAMD21E15L Analog Comparators 1 (AC1) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E15L-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E15L Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E15L System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E15L Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E15L Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E15L External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E15L Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E15L Direct Memory Access Controller (DMAC) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E15L Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E15L Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E15L Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E15L Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E15L Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E15L Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E15L Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E15L Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E15L Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E15L Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E15L Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E15L Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E15L Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E15L Digital Analog Converter (DAC) */
+ AC1_IRQn = 28, /**< 28 SAMD21E15L Analog Comparators 1 (AC1) */
- PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnReserved7;
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnReserved26;
- void* pfnReserved27;
- void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnReserved7;
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnReserved26;
+ void* pfnReserved27;
+ void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -215,7 +213,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,94 +93,92 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E16A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -221,7 +219,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,95 +90,93 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E16B-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E16B Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E16B System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E16B Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E16B Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E16B External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E16B Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E16B Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E16B Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E16B Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E16B Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E16B Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E16B Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E16B Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E16B Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E16B Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E16B Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E16B Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E16B Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E16B Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E16B Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E16B Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E16B Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E16B Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E16B Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E16B-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E16B Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E16B System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E16B Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E16B Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E16B External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E16B Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E16B Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E16B Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E16B Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E16B Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E16B Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E16B Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E16B Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E16B Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E16B Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E16B Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E16B Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E16B Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E16B Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E16B Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E16B Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E16B Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E16B Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E16B Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -219,7 +217,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,95 +90,93 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E16BU-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E16BU Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E16BU System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E16BU Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E16BU Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E16BU External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E16BU Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E16BU Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E16BU Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E16BU Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E16BU Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E16BU Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E16BU Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E16BU Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E16BU Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E16BU Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E16BU Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E16BU Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E16BU Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E16BU Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E16BU Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E16BU Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E16BU Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E16BU Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E16BU Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E16BU-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E16BU Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E16BU System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E16BU Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E16BU Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E16BU External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E16BU Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E16BU Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E16BU Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E16BU Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E16BU Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E16BU Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E16BU Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E16BU Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E16BU Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E16BU Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E16BU Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E16BU Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E16BU Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E16BU Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E16BU Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E16BU Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E16BU Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E16BU Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E16BU Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -219,7 +217,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,93 +90,91 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E16L-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E16L Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E16L System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E16L Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E16L Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E16L External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E16L Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E16L Direct Memory Access Controller (DMAC) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E16L Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E16L Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E16L Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E16L Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E16L Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E16L Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E16L Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E16L Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E16L Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E16L Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E16L Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E16L Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E16L Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E16L Digital Analog Converter (DAC) */
- AC1_IRQn = 28, /**< 28 SAMD21E16L Analog Comparators 1 (AC1) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E16L-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E16L Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E16L System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E16L Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E16L Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E16L External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E16L Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E16L Direct Memory Access Controller (DMAC) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E16L Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E16L Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E16L Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E16L Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E16L Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E16L Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E16L Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E16L Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E16L Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E16L Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E16L Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E16L Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E16L Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E16L Digital Analog Converter (DAC) */
+ AC1_IRQn = 28, /**< 28 SAMD21E16L Analog Comparators 1 (AC1) */
- PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnReserved7;
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnReserved26;
- void* pfnReserved27;
- void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnReserved7;
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnReserved26;
+ void* pfnReserved27;
+ void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -215,7 +213,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,94 +93,92 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E17A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -221,7 +219,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,94 +93,92 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E18A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -221,7 +219,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,96 +93,94 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G15A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G15A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -225,7 +223,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,97 +90,95 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G15B-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G15B Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G15B System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G15B Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G15B Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G15B External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G15B Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G15B Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G15B Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G15B Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G15B Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G15B Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G15B Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G15B Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G15B Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G15B Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G15B Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G15B Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G15B Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G15B Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G15B Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G15B Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21G15B Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G15B Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G15B Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G15B Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G15B Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G15B-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G15B Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G15B System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G15B Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G15B Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G15B External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G15B Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G15B Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G15B Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G15B Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G15B Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G15B Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G15B Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G15B Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G15B Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G15B Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G15B Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G15B Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G15B Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G15B Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G15B Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G15B Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G15B Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G15B Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G15B Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G15B Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G15B Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -223,7 +221,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,96 +93,94 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G16A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -225,7 +223,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,97 +90,95 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G16B-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G16B Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G16B System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G16B Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G16B Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G16B External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G16B Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G16B Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G16B Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G16B Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G16B Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G16B Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G16B Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G16B Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G16B Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G16B Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G16B Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G16B Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G16B Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G16B Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G16B Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G16B Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21G16B Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G16B Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G16B Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G16B Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G16B Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G16B-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G16B Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G16B System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G16B Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G16B Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G16B External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G16B Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G16B Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G16B Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G16B Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G16B Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G16B Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G16B Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G16B Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G16B Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G16B Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G16B Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G16B Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G16B Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G16B Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G16B Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G16B Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G16B Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G16B Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G16B Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G16B Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G16B Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -223,7 +221,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,96 +93,94 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G17A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -225,7 +223,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h Fri Sep 25 12:00:11 2015 +0100
@@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
- /*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
+/*
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
#ifndef _SAMD21G17AU_
#define _SAMD21G17AU_
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,99 +93,97 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G17AU-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G17AU-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -230,7 +228,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,96 +93,94 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G18A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -225,7 +223,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h Fri Sep 25 12:00:11 2015 +0100
@@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
- /*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
+/*
+* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+*/
#ifndef _SAMD21G18AU_
#define _SAMD21G18AU_
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,98 +93,96 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G18AU-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G18AU-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -229,7 +227,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,98 +93,96 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21J15A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J15A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -229,7 +227,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21J15B-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21J15B Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21J15B System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21J15B Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21J15B Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21J15B External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21J15B Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21J15B Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21J15B Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21J15B Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21J15B Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21J15B Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21J15B Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21J15B Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21J15B Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21J15B Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21J15B Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21J15B Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21J15B Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21J15B Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21J15B Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21J15B Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21J15B Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21J15B Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21J15B Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21J15B Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21J15B Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21J15B Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21J15B Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J15B-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J15B Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J15B System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J15B Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J15B Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J15B External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J15B Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J15B Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J15B Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J15B Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J15B Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J15B Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J15B Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J15B Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J15B Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J15B Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J15B Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J15B Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J15B Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J15B Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J15B Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J15B Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J15B Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J15B Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J15B Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J15B Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J15B Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J15B Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J15B Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,98 +93,96 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21J16A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -229,7 +227,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21J16B-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21J16B Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21J16B System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21J16B Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21J16B Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21J16B External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21J16B Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21J16B Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21J16B Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21J16B Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21J16B Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21J16B Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21J16B Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21J16B Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21J16B Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21J16B Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21J16B Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21J16B Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21J16B Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21J16B Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21J16B Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21J16B Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21J16B Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21J16B Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21J16B Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21J16B Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21J16B Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21J16B Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21J16B Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J16B-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J16B Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J16B System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J16B Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J16B Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J16B External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J16B Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J16B Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J16B Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J16B Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J16B Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J16B Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J16B Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J16B Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J16B Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J16B Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J16B Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J16B Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J16B Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J16B Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J16B Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J16B Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J16B Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J16B Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J16B Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J16B Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J16B Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J16B Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J16B Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,98 +93,96 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21J17A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -229,7 +227,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h Fri Sep 25 12:00:11 2015 +0100
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,98 +93,96 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21J18A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -229,7 +227,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,14 +56,14 @@
/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} AC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -84,16 +84,16 @@
/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
- uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
+ uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -112,25 +112,25 @@
/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
- uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
- uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
+ uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
+ uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} AC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -161,20 +161,20 @@
/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
- uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -198,20 +198,20 @@
/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
- uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -235,20 +235,20 @@
/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
- __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
- __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
- __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
- __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
- __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
- __I uint8_t WIN:1; /*!< bit: 4 Window x */
- __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
+ __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
+ __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
+ __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
+ __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint8_t WIN:1; /*!< bit: 4 Window x */
+ __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -272,18 +272,18 @@
/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
- uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -311,17 +311,17 @@
/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
- uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
+ uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -342,18 +342,18 @@
/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
- uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_STATUSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -381,12 +381,12 @@
/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
- uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
+ uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} AC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -411,26 +411,26 @@
/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ENABLE:1; /*!< bit: 0 Enable */
- uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
- uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
- uint32_t :1; /*!< bit: 4 Reserved */
- uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
- uint32_t :1; /*!< bit: 14 Reserved */
- uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
- uint32_t OUT:2; /*!< bit: 16..17 Output */
- uint32_t :1; /*!< bit: 18 Reserved */
- uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ENABLE:1; /*!< bit: 0 Enable */
+ uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
+ uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
+ uint32_t :1; /*!< bit: 4 Reserved */
+ uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
+ uint32_t :1; /*!< bit: 14 Reserved */
+ uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
+ uint32_t OUT:2; /*!< bit: 16..17 Output */
+ uint32_t :1; /*!< bit: 18 Reserved */
+ uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} AC_COMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -516,11 +516,11 @@
/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} AC_SCALER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -535,22 +535,22 @@
/** \brief AC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
- __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
- __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
- __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
- __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
- __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
- __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
- RoReg8 Reserved2[0x1];
- __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
- RoReg8 Reserved3[0x3];
- __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
- RoReg8 Reserved4[0x8];
- __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
+ __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
+ __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
+ __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
+ __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
+ __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
+ __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
+ __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
+ RoReg8 Reserved2[0x1];
+ __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
+ RoReg8 Reserved3[0x3];
+ __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+ RoReg8 Reserved4[0x8];
+ __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
} Ac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,13 +56,13 @@
/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -80,12 +80,12 @@
/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_REFCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -112,12 +112,12 @@
/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
- uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
+ uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_AVGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -157,11 +157,11 @@
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_SAMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -176,17 +176,17 @@
/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
- uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
- uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
- uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
- uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
+ uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
+ uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
+ uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
+ uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -236,11 +236,11 @@
/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -265,12 +265,12 @@
/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
- uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
+ uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_SWTRIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -286,17 +286,17 @@
/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
- uint32_t :3; /*!< bit: 5.. 7 Reserved */
- uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
- uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
- uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
+ uint32_t :3; /*!< bit: 5.. 7 Reserved */
+ uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
+ uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
+ uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} ADC_INPUTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -405,15 +405,15 @@
/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
- uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
- uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
+ uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
+ uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -433,14 +433,14 @@
/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
- uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
- uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -460,14 +460,14 @@
/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
- uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
- uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -487,14 +487,14 @@
/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
- __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
- __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
- __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
- __I uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
+ __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
+ __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
+ __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
+ __I uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -514,11 +514,11 @@
/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -532,10 +532,10 @@
/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_RESULT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -550,10 +550,10 @@
/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_WINLT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -568,10 +568,10 @@
/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_WINUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -586,11 +586,11 @@
/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_GAINCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -605,11 +605,11 @@
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_OFFSETCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -624,12 +624,12 @@
/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
- uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
+ uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_CALIB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -647,11 +647,11 @@
/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -665,32 +665,32 @@
/** \brief ADC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
- __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
- __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
- __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
- RoReg8 Reserved1[0x2];
- __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
- RoReg8 Reserved2[0x3];
- __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
- RoReg8 Reserved3[0x3];
- __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
- __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
- RoReg8 Reserved4[0x1];
- __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
- __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
- __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
- __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
- __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
- __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
- RoReg8 Reserved5[0x2];
- __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
- RoReg8 Reserved6[0x2];
- __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
- __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
- __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
- __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
+ __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
+ __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
+ __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
+ __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
+ RoReg8 Reserved1[0x2];
+ __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
+ RoReg8 Reserved2[0x3];
+ __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
+ RoReg8 Reserved3[0x3];
+ __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
+ __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
+ RoReg8 Reserved4[0x1];
+ __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
+ __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
+ __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
+ __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
+ __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
+ __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
+ RoReg8 Reserved5[0x2];
+ __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
+ RoReg8 Reserved6[0x2];
+ __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
+ __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
+ __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
+ __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
} Adc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,23 +56,23 @@
/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
- uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
- uint16_t :5; /*!< bit: 3.. 7 Reserved */
- uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
- uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
- uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
- uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :8; /*!< bit: 0.. 7 Reserved */
- uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
+ uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
+ uint16_t :5; /*!< bit: 3.. 7 Reserved */
+ uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
+ uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
+ uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
+ uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :8; /*!< bit: 0.. 7 Reserved */
+ uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -101,14 +101,14 @@
/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
- uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
+ uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_CRCCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -143,10 +143,10 @@
/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_CRCDATAIN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -161,10 +161,10 @@
/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_CRCCHKSUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -179,12 +179,12 @@
/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
- uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
+ uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CRCSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -200,11 +200,11 @@
/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -218,13 +218,13 @@
/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
- uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
- uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
+ uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
+ uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_QOSCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -269,26 +269,26 @@
/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
- uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
- uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
- uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
- uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
- uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
- uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
- uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
- uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
- uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
- uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
- uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
+ uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
+ uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
+ uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
+ uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
+ uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
+ uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
+ uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
+ uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
+ uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
+ uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
+ uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_SWTRIGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -327,21 +327,21 @@
/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
- uint32_t :3; /*!< bit: 4.. 6 Reserved */
- uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
- uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
- uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
- uint32_t :3; /*!< bit: 20..22 Reserved */
- uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
- uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
- uint32_t :3; /*!< bit: 28..30 Reserved */
- uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
+ uint32_t :3; /*!< bit: 4.. 6 Reserved */
+ uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
+ uint32_t :3; /*!< bit: 20..22 Reserved */
+ uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
+ uint32_t :3; /*!< bit: 28..30 Reserved */
+ uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_PRICTRL0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -373,18 +373,18 @@
/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t TERR:1; /*!< bit: 8 Transfer Error */
- uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
- uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
- uint16_t :2; /*!< bit: 11..12 Reserved */
- uint16_t FERR:1; /*!< bit: 13 Fetch Error */
- uint16_t BUSY:1; /*!< bit: 14 Busy */
- uint16_t PEND:1; /*!< bit: 15 Pending */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t TERR:1; /*!< bit: 8 Transfer Error */
+ uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
+ uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
+ uint16_t :2; /*!< bit: 11..12 Reserved */
+ uint16_t FERR:1; /*!< bit: 13 Fetch Error */
+ uint16_t BUSY:1; /*!< bit: 14 Busy */
+ uint16_t PEND:1; /*!< bit: 15 Pending */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_INTPEND_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -411,26 +411,26 @@
/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
- uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
- uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
- uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
- uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
- uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
- uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
- uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
- uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
- uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
- uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
- uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
+ uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
+ uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
+ uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
+ uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
+ uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
+ uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
+ uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
+ uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
+ uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
+ uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
+ uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_INTSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -469,26 +469,26 @@
/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
- uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
- uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
- uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
- uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
- uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
- uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
- uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
- uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
- uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
- uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
- uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
+ uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
+ uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
+ uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
+ uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
+ uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
+ uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
+ uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
+ uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
+ uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
+ uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
+ uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_BUSYCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -527,26 +527,26 @@
/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
- uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
- uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
- uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
- uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
- uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
- uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
- uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
- uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
- uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
- uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
- uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
+ uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
+ uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
+ uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
+ uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
+ uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
+ uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
+ uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
+ uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
+ uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
+ uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
+ uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_PENDCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -585,22 +585,22 @@
/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
- uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
- uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
- uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
- uint32_t :2; /*!< bit: 13..14 Reserved */
- uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
- uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
- uint32_t :28; /*!< bit: 4..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
+ uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
+ uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
+ uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
+ uint32_t :2; /*!< bit: 13..14 Reserved */
+ uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
+ uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_ACTIVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -631,10 +631,10 @@
/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_BASEADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -649,10 +649,10 @@
/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_WRBADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -667,11 +667,11 @@
/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -686,12 +686,12 @@
/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -707,19 +707,19 @@
/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
- uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
- uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
- uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */
- uint32_t :8; /*!< bit: 14..21 Reserved */
- uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
- uint32_t CMD:2; /*!< bit: 24..25 Software Command */
- uint32_t :6; /*!< bit: 26..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
+ uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
+ uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
+ uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */
+ uint32_t :8; /*!< bit: 14..21 Reserved */
+ uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
+ uint32_t CMD:2; /*!< bit: 24..25 Software Command */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_CHCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -786,13 +786,13 @@
/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
- uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
- uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -810,13 +810,13 @@
/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
- uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
- uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -834,13 +834,13 @@
/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
- __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
- __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
- __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
+ __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
+ __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
+ __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -858,13 +858,13 @@
/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PEND:1; /*!< bit: 0 Channel Pending */
- uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
- uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PEND:1; /*!< bit: 0 Channel Pending */
+ uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
+ uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -882,18 +882,18 @@
/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
- uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
- uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
- uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
- uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
- uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
- uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
+ uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
+ uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
+ uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
+ uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
+ uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
+ uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_BTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -965,10 +965,10 @@
/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_BTCNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -982,10 +982,10 @@
/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_SRCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -999,10 +999,10 @@
/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_DSTADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1016,10 +1016,10 @@
/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_DESCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1033,49 +1033,49 @@
/** \brief DMAC APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
- __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
- __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
- __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
- __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
- __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
- __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
- RoReg8 Reserved1[0x1];
- __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
- __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
- RoReg8 Reserved2[0x8];
- __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
- RoReg8 Reserved3[0x2];
- __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
- __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
- __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
- __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
- __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
- __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
- RoReg8 Reserved4[0x3];
- __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
- __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
- RoReg8 Reserved5[0x3];
- __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
- RoReg8 Reserved6[0x4];
- __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
- __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
- __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
- __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
+ __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
+ __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
+ __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
+ __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
+ __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
+ __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
+ __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
+ RoReg8 Reserved1[0x1];
+ __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
+ __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
+ RoReg8 Reserved2[0x8];
+ __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
+ RoReg8 Reserved3[0x2];
+ __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
+ __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
+ __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
+ __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
+ __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
+ __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
+ RoReg8 Reserved4[0x3];
+ __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
+ __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
+ RoReg8 Reserved5[0x3];
+ __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
+ RoReg8 Reserved6[0x4];
+ __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
+ __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
+ __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
+ __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
} Dmac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief DMAC Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
- __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
- __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
- __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
- __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
+ __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
+ __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
+ __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
+ __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
+ __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
} DmacDescriptor
#ifdef __GNUC__
- __attribute__ ((aligned (8)))
+__attribute__ ((aligned (8)))
#endif
;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,15 +56,15 @@
/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
- uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
- uint8_t CE:1; /*!< bit: 4 Chip Erase */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
+ uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
+ uint8_t CE:1; /*!< bit: 4 Chip Erase */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DSU_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -84,15 +84,15 @@
/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DONE:1; /*!< bit: 0 Done */
- uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
- uint8_t BERR:1; /*!< bit: 2 Bus Error */
- uint8_t FAIL:1; /*!< bit: 3 Failure */
- uint8_t PERR:1; /*!< bit: 4 Protection Error */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DONE:1; /*!< bit: 0 Done */
+ uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
+ uint8_t BERR:1; /*!< bit: 2 Bus Error */
+ uint8_t FAIL:1; /*!< bit: 3 Failure */
+ uint8_t PERR:1; /*!< bit: 4 Protection Error */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DSU_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -114,20 +114,20 @@
/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PROT:1; /*!< bit: 0 Protected */
- uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
- uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
- uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
- uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PROT:1; /*!< bit: 0 Protected */
+ uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
+ uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
+ uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
+ uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} DSU_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -152,11 +152,11 @@
/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t ADDR:30; /*!< bit: 2..31 Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t ADDR:30; /*!< bit: 2..31 Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -171,11 +171,11 @@
/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t LENGTH:30; /*!< bit: 2..31 Length */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t LENGTH:30; /*!< bit: 2..31 Length */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_LENGTH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -190,10 +190,10 @@
/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -208,10 +208,10 @@
/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_DCC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -226,16 +226,16 @@
/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
- uint32_t REVISION:4; /*!< bit: 8..11 Revision */
- uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
- uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
- uint32_t :1; /*!< bit: 22 Reserved */
- uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
- uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
+ uint32_t REVISION:4; /*!< bit: 8..11 Revision */
+ uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
+ uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
+ uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_DID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -264,13 +264,13 @@
/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EPRES:1; /*!< bit: 0 Entry Present */
- uint32_t FMT:1; /*!< bit: 1 Format */
- uint32_t :10; /*!< bit: 2..11 Reserved */
- uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EPRES:1; /*!< bit: 0 Entry Present */
+ uint32_t FMT:1; /*!< bit: 1 Format */
+ uint32_t :10; /*!< bit: 2..11 Reserved */
+ uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_ENTRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -289,10 +289,10 @@
/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t END:32; /*!< bit: 0..31 End Marker */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t END:32; /*!< bit: 0..31 End Marker */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_END_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -307,11 +307,11 @@
/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_MEMTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -325,12 +325,12 @@
/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
- uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
+ uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -348,11 +348,11 @@
/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -367,12 +367,12 @@
/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
- uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
+ uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -390,13 +390,13 @@
/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
- uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
- uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
+ uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
+ uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -416,12 +416,12 @@
/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
- uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
+ uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -439,11 +439,11 @@
/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -458,12 +458,12 @@
/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
- uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
+ uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -481,11 +481,11 @@
/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -500,11 +500,11 @@
/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -519,30 +519,30 @@
/** \brief DSU hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
- __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
- __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
- RoReg8 Reserved1[0x1];
- __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
- __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
- __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
- __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
- __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
- RoReg8 Reserved2[0xFE4];
- __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
- __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
- RoReg8 Reserved3[0xFC0];
- __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
- __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
- RoReg8 Reserved4[0xC];
- __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
- __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
- __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
- __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
- __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
- __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
- __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
- __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
+ __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
+ __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
+ __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
+ RoReg8 Reserved1[0x1];
+ __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
+ __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
+ __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
+ __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
+ __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
+ RoReg8 Reserved2[0xFE4];
+ __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
+ __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
+ RoReg8 Reserved3[0xFC0];
+ __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
+ __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
+ RoReg8 Reserved4[0xC];
+ __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
+ __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
+ __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
+ __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
+ __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
+ __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
+ __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
+ __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
} Dsu;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,12 +56,12 @@
/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -77,11 +77,11 @@
/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -95,12 +95,12 @@
/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
- uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
+ uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_NMICTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -129,11 +129,11 @@
/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_NMIFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -147,30 +147,30 @@
/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
- uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
- uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
- uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
- uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
- uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
- uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
- uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
- uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
- uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
- uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
- uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
- uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
- uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
- uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
- uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
+ uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
+ uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
+ uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
+ uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
+ uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
+ uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
+ uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
+ uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
+ uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
+ uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
+ uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
+ uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
+ uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
+ uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
+ uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -217,30 +217,30 @@
/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
- uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
- uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
- uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
- uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
- uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
- uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
- uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
- uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
- uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
- uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
- uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
- uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
- uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
- uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
- uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -287,30 +287,30 @@
/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
- uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
- uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
- uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
- uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
- uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
- uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
- uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
- uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
- uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
- uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
- uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
- uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
- uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
- uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
- uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -357,30 +357,30 @@
/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
- __I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
- __I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
- __I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
- __I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
- __I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
- __I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
- __I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
- __I uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
- __I uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
- __I uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
- __I uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
- __I uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
- __I uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
- __I uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
- __I uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
- __I uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
- __I uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ __I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
+ __I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
+ __I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
+ __I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
+ __I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
+ __I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
+ __I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
+ __I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
+ __I uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
+ __I uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
+ __I uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
+ __I uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
+ __I uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
+ __I uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
+ __I uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
+ __I uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
+ __I uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
+ __I uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -427,30 +427,30 @@
/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
- uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
- uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
- uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
- uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
- uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
- uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
- uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
- uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
- uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
- uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
- uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
- uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
- uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
- uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
- uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
+ uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
+ uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
+ uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
+ uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
+ uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
+ uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
+ uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
+ uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
+ uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
+ uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
+ uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
+ uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
+ uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
+ uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
+ uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_WAKEUP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -497,25 +497,25 @@
/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
- uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
- uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
- uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
- uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
- uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
- uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
- uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
- uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
- uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
- uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
- uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
- uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
- uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
- uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
- uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
+ uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
+ uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
+ uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
+ uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
+ uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
+ uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
+ uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
+ uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
+ uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
+ uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
+ uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
+ uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
+ uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
+ uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
+ uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -663,16 +663,16 @@
/** \brief EIC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
- __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
- __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
- __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
- __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
- __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
- __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
- __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
- __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
- __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
+ __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
+ __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
+ __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
+ __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
+ __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
+ __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
+ __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
+ __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
+ __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
+ __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
} Eic;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,13 +56,13 @@
/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t :3; /*!< bit: 1.. 3 Reserved */
- uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :3; /*!< bit: 1.. 3 Reserved */
+ uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EVSYS_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -78,18 +78,18 @@
/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t SWEVT:1; /*!< bit: 8 Software Event */
- uint32_t :7; /*!< bit: 9..15 Reserved */
- uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
- uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t SWEVT:1; /*!< bit: 8 Software Event */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
+ uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_CHANNEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -129,13 +129,13 @@
/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
- uint16_t :3; /*!< bit: 13..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} EVSYS_USER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -155,43 +155,43 @@
/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
- uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
- uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
- uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
- uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
- uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
- uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
- uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
- uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
- uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
- uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
- uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
- uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
- uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
- uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
- uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
- uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
- uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
- uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
- uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
- uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
- uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
- uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
- uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
- uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
+ uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
+ uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
+ uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
+ uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
+ uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
+ uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
+ uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
+ uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
+ uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
+ uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
+ uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
+ uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
+ uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
+ uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
+ uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
+ uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
+ uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
+ uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
+ uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
+ uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
+ uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
+ uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
+ uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
+ uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -263,43 +263,43 @@
/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
- uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
- uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
- uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
- uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
- uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
- uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
- uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
- uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
- uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
- uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
- uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
- uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
- uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
- uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
- uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
- uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
- uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
- uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
- uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
- uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
- uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
- uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
- uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
- uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -371,43 +371,43 @@
/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
- uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
- uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
- uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
- uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
- uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
- uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
- uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
- uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
- uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
- uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
- uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
- uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
- uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
- uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
- uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
- uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
- uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
- uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
- uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
- uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
- uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
- uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
- uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
- uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -479,43 +479,43 @@
/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
- __I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
- __I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
- __I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
- __I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
- __I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
- __I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
- __I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
- __I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
- __I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
- __I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
- __I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
- __I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
- __I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
- __I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
- __I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
- __I uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
- __I uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
- __I uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
- __I uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
- __I uint32_t :4; /*!< bit: 20..23 Reserved */
- __I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
- __I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
- __I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
- __I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
- __I uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
- __I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
- __I uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
- __I uint32_t :4; /*!< bit: 20..23 Reserved */
- __I uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
- __I uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ __I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
+ __I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
+ __I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
+ __I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
+ __I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
+ __I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
+ __I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
+ __I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
+ __I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
+ __I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
+ __I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
+ __I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
+ __I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
+ __I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
+ __I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
+ __I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
+ __I uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
+ __I uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
+ __I uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
+ __I uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
+ __I uint32_t :4; /*!< bit: 20..23 Reserved */
+ __I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
+ __I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
+ __I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
+ __I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
+ __I uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
+ __I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
+ __I uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
+ __I uint32_t :4; /*!< bit: 20..23 Reserved */
+ __I uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
+ __I uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -587,15 +587,15 @@
/** \brief EVSYS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
- RoReg8 Reserved1[0x3];
- __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
- __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
- RoReg8 Reserved2[0x2];
- __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
- __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
- __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
- __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
+ __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
+ RoReg8 Reserved1[0x3];
+ __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
+ __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
+ RoReg8 Reserved2[0x2];
+ __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
+ __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
+ __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
+ __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
} Evsys;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,11 +56,11 @@
/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} GCLK_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -74,11 +74,11 @@
/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} GCLK_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -92,15 +92,15 @@
/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
- uint16_t :2; /*!< bit: 12..13 Reserved */
- uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
- uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
+ uint16_t :2; /*!< bit: 12..13 Reserved */
+ uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
+ uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} GCLK_CLKCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -212,20 +212,20 @@
/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t SRC:5; /*!< bit: 8..12 Source Select */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
- uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
- uint32_t OOV:1; /*!< bit: 18 Output Off Value */
- uint32_t OE:1; /*!< bit: 19 Output Enable */
- uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
- uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t SRC:5; /*!< bit: 8..12 Source Select */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
+ uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
+ uint32_t OOV:1; /*!< bit: 18 Output Off Value */
+ uint32_t OE:1; /*!< bit: 19 Output Enable */
+ uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
+ uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} GCLK_GENCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -273,13 +273,13 @@
/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} GCLK_GENDIV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -297,11 +297,11 @@
/** \brief GCLK hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
- __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
- __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
- __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
- __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
+ __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
+ __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
+ __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
+ __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
} Gclk;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRAS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -68,7 +68,7 @@
/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRBS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -80,10 +80,10 @@
/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} HMATRIXB_SFR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -98,18 +98,18 @@
/** \brief HmatrixbPrs hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
- __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
+ __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
+ __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
} HmatrixbPrs;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief HMATRIXB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- RoReg8 Reserved1[0x80];
- HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
- RoReg8 Reserved2[0x10];
- __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
+ RoReg8 Reserved1[0x80];
+ HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
+ RoReg8 Reserved2[0x10];
+ __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
} Hmatrixb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,12 +56,12 @@
/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
- uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
+ uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_POSITION_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -77,17 +77,17 @@
/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
- uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
- uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
- uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
- uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
- uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
- uint32_t :21; /*!< bit: 10..30 Reserved */
- uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
+ uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
+ uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
+ uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
+ uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
+ uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
+ uint32_t :21; /*!< bit: 10..30 Reserved */
+ uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_MASTER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -114,13 +114,13 @@
/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
- uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
+ uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_FLOW_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -139,7 +139,7 @@
/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_BASE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -149,7 +149,7 @@
/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_ITCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -159,7 +159,7 @@
/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -169,7 +169,7 @@
/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -179,7 +179,7 @@
/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_LOCKACCESS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -189,7 +189,7 @@
/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_LOCKSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -199,7 +199,7 @@
/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_AUTHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -209,7 +209,7 @@
/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_DEVARCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -219,7 +219,7 @@
/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_DEVID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -229,7 +229,7 @@
/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_DEVTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -239,7 +239,7 @@
/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -249,7 +249,7 @@
/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID5_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -259,7 +259,7 @@
/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID6_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -269,7 +269,7 @@
/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID7_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -279,7 +279,7 @@
/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -289,7 +289,7 @@
/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -299,7 +299,7 @@
/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -309,7 +309,7 @@
/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -319,7 +319,7 @@
/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -329,7 +329,7 @@
/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -339,7 +339,7 @@
/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -349,7 +349,7 @@
/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -359,35 +359,35 @@
/** \brief MTB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
- __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
- __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
- __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
- RoReg8 Reserved1[0xEF0];
- __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
- RoReg8 Reserved2[0x9C];
- __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
- __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
- RoReg8 Reserved3[0x8];
- __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
- __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
- __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
- __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
- RoReg8 Reserved4[0x8];
- __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
- __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
- __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
- __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
- __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
- __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
- __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
- __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
- __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
- __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
- __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
- __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
- __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
- __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
+ __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
+ __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
+ __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
+ __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
+ RoReg8 Reserved1[0xEF0];
+ __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
+ RoReg8 Reserved2[0x9C];
+ __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
+ __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
+ RoReg8 Reserved3[0x8];
+ __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
+ __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
+ __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
+ __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
+ RoReg8 Reserved4[0x8];
+ __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
+ __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
+ __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
+ __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
+ __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
+ __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
+ __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
+ __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
+ __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
+ __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
+ __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
+ __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
+ __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
+ __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
} Mtb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,12 +56,12 @@
/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t CMD:7; /*!< bit: 0.. 6 Command */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t CMD:7; /*!< bit: 0.. 6 Command */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -107,18 +107,18 @@
/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t MANW:1; /*!< bit: 7 Manual Write */
- uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
- uint32_t :6; /*!< bit: 10..15 Reserved */
- uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
- uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t MANW:1; /*!< bit: 7 Manual Write */
+ uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
+ uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -161,12 +161,12 @@
/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
- uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
+ uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} NVMCTRL_PARAM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -200,12 +200,12 @@
/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
- uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -221,12 +221,12 @@
/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
- uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -242,12 +242,12 @@
/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t READY:1; /*!< bit: 0 NVM Ready */
- __I uint8_t ERROR:1; /*!< bit: 1 Error */
- __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t READY:1; /*!< bit: 0 NVM Ready */
+ __I uint8_t ERROR:1; /*!< bit: 1 Error */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -263,17 +263,17 @@
/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
- uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
- uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
- uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
- uint16_t NVME:1; /*!< bit: 4 NVM Error */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t SB:1; /*!< bit: 8 Security Bit Status */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
+ uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
+ uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
+ uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
+ uint16_t NVME:1; /*!< bit: 4 NVM Error */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t SB:1; /*!< bit: 8 Security Bit Status */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} NVMCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -297,11 +297,11 @@
/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} NVMCTRL_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -316,10 +316,10 @@
/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} NVMCTRL_LOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -333,20 +333,20 @@
/** \brief NVMCTRL APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- RoReg8 Reserved1[0x2];
- __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
- __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
- __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- RoReg8 Reserved2[0x3];
- __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
- RoReg8 Reserved3[0x3];
- __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x3];
- __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
- RoReg8 Reserved5[0x2];
- __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
- __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
+ __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ RoReg8 Reserved1[0x2];
+ __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
+ __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
+ __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ RoReg8 Reserved2[0x3];
+ __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
+ RoReg8 Reserved3[0x3];
+ __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x3];
+ __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
+ RoReg8 Reserved5[0x2];
+ __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
+ __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
} Nvmctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_NVMCTRL_CAL
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,11 +56,11 @@
/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PAC_WPCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -75,11 +75,11 @@
/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PAC_WPSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -94,8 +94,8 @@
/** \brief PAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
- __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
+ __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
+ __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
} Pac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint8_t reg; /*!< Type used for register access */
+ uint8_t reg; /*!< Type used for register access */
} PM_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -68,11 +68,11 @@
/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_SLEEP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -93,11 +93,11 @@
/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_CPUSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -128,11 +128,11 @@
/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_APBASEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -163,11 +163,11 @@
/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_APBBSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -198,11 +198,11 @@
/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_APBCSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -233,17 +233,17 @@
/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
- uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
- uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
- uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
- uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
- uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
- uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
- uint32_t :25; /*!< bit: 7..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
+ uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
+ uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
+ uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
+ uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
+ uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
+ uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_AHBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -269,17 +269,17 @@
/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
- uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
- uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
- uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
- uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
- uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
- uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
- uint32_t :25; /*!< bit: 7..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
+ uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
+ uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
+ uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
+ uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
+ uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
+ uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_APBAMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -305,17 +305,17 @@
/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
- uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
- uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
- uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
- uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
- uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
- uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
- uint32_t :25; /*!< bit: 7..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
+ uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
+ uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
+ uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
+ uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
+ uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
+ uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_APBBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -341,31 +341,31 @@
/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
- uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
- uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
- uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
- uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
- uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
- uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
- uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
- uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
- uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
- uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
- uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
- uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
- uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
- uint32_t :2; /*!< bit: 14..15 Reserved */
- uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
- uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
- uint32_t :1; /*!< bit: 18 Reserved */
- uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
- uint32_t :1; /*!< bit: 20 Reserved */
- uint32_t RFCTRL_:1; /*!< bit: 21 RFCTRL APB Clock Enable */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
+ uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
+ uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
+ uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
+ uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
+ uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
+ uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
+ uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
+ uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
+ uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
+ uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
+ uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
+ uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
+ uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
+ uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
+ uint32_t :1; /*!< bit: 18 Reserved */
+ uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
+ uint32_t :1; /*!< bit: 20 Reserved */
+ uint32_t RFCTRL_:1; /*!< bit: 21 RFCTRL APB Clock Enable */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_APBCMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -413,11 +413,11 @@
/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -431,11 +431,11 @@
/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -449,11 +449,11 @@
/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
- __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -467,17 +467,17 @@
/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t POR:1; /*!< bit: 0 Power On Reset */
- uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
- uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t EXT:1; /*!< bit: 4 External Reset */
- uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
- uint8_t SYST:1; /*!< bit: 6 System Reset Request */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t POR:1; /*!< bit: 0 Power On Reset */
+ uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
+ uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EXT:1; /*!< bit: 4 External Reset */
+ uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
+ uint8_t SYST:1; /*!< bit: 6 System Reset Request */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_RCAUSE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -501,24 +501,24 @@
/** \brief PM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
- __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
- RoReg8 Reserved1[0x6];
- __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
- __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
- __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
- __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
- RoReg8 Reserved2[0x8];
- __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
- __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
- __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
- __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
- RoReg8 Reserved3[0x10];
- __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
- __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
- __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x1];
- __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
+ __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
+ __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
+ RoReg8 Reserved1[0x6];
+ __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
+ __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
+ __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
+ __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
+ RoReg8 Reserved2[0x8];
+ __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
+ __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
+ __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
+ __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
+ RoReg8 Reserved3[0x10];
+ __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
+ __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
+ __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
} Pm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,10 +56,10 @@
/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -74,10 +74,10 @@
/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIRCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -92,10 +92,10 @@
/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIRSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -110,10 +110,10 @@
/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIRTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -128,10 +128,10 @@
/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -146,10 +146,10 @@
/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUTCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -164,10 +164,10 @@
/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUTSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -182,10 +182,10 @@
/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUTTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -200,10 +200,10 @@
/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_IN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -218,10 +218,10 @@
/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -236,21 +236,21 @@
/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
- uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
- uint32_t INEN:1; /*!< bit: 17 Input Enable */
- uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
- uint32_t :3; /*!< bit: 19..21 Reserved */
- uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
- uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
- uint32_t :1; /*!< bit: 29 Reserved */
- uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
- uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
+ uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
+ uint32_t INEN:1; /*!< bit: 17 Input Enable */
+ uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
+ uint32_t :3; /*!< bit: 19..21 Reserved */
+ uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
+ uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
+ uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_WRCONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -282,11 +282,11 @@
/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
- uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
+ uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PORT_PMUX_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -336,15 +336,15 @@
/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
- uint8_t INEN:1; /*!< bit: 1 Input Enable */
- uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
- uint8_t :3; /*!< bit: 3.. 5 Reserved */
- uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
+ uint8_t INEN:1; /*!< bit: 1 Input Enable */
+ uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PORT_PINCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -364,28 +364,28 @@
/** \brief PortGroup hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
- __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
- __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
- __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
- __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
- __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
- __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
- __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
- __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
- __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
- __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
- RoReg8 Reserved1[0x4];
- __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
- __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
- RoReg8 Reserved2[0x20];
+ __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
+ __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
+ __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
+ __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
+ __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
+ __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
+ __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
+ __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
+ __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
+ __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
+ __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
+ RoReg8 Reserved1[0x4];
+ __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
+ __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
+ RoReg8 Reserved2[0x20];
} PortGroup;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief PORT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- PortGroup Group[3]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
+ PortGroup Group[3]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
} Port;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_PORT_IOBUS
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,16 +56,16 @@
/* -------- RFCTRL_FECFG : (RFCTRL Offset: 0x0) (R/W 16) Front-end control bus configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */
- uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */
- uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */
- uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */
- uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */
- uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */
+ uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */
+ uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */
+ uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */
+ uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */
+ uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RFCTRL_FECFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -95,7 +95,7 @@
/** \brief RFCTRL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */
+ __IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */
} Rfctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,16 +56,16 @@
/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
- uint16_t :3; /*!< bit: 4.. 6 Reserved */
- uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
- uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :3; /*!< bit: 4.. 6 Reserved */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE0_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -117,15 +117,15 @@
/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -175,17 +175,17 @@
/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
- uint16_t :2; /*!< bit: 4.. 5 Reserved */
- uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
- uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
- uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :2; /*!< bit: 4.. 5 Reserved */
+ uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE2_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -239,13 +239,13 @@
/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
- uint16_t :8; /*!< bit: 6..13 Reserved */
- uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
- uint16_t RREQ:1; /*!< bit: 15 Read Request */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
+ uint16_t :8; /*!< bit: 6..13 Reserved */
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_READREQ_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -264,25 +264,25 @@
/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
- uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
- uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
- uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
- uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
- uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
- uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
- uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
- uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
- uint16_t :6; /*!< bit: 9..14 Reserved */
- uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
- uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE0_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -320,26 +320,26 @@
/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
- uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
- uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
- uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
- uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
- uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
- uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
- uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
- uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
- uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
- uint16_t :5; /*!< bit: 10..14 Reserved */
- uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
- uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
+ uint16_t :5; /*!< bit: 10..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -379,25 +379,25 @@
/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
- uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
- uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
- uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
- uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
- uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
- uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
- uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
- uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
- uint16_t :6; /*!< bit: 9..14 Reserved */
- uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
- uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE2_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -435,17 +435,17 @@
/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -466,18 +466,18 @@
/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -500,17 +500,17 @@
/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -531,17 +531,17 @@
/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -562,18 +562,18 @@
/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -596,17 +596,17 @@
/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -627,17 +627,17 @@
/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
- __I uint8_t :5; /*!< bit: 1.. 5 Reserved */
- __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
- __I uint8_t OVF:1; /*!< bit: 7 Overflow */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t CMP:1; /*!< bit: 0 Compare x */
- __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
+ __I uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ __I uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t CMP:1; /*!< bit: 0 Compare x */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -658,18 +658,18 @@
/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
- __I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
- __I uint8_t :4; /*!< bit: 2.. 5 Reserved */
- __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
- __I uint8_t OVF:1; /*!< bit: 7 Overflow */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
- __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
+ __I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
+ __I uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ __I uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -692,17 +692,17 @@
/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
- __I uint8_t :5; /*!< bit: 1.. 5 Reserved */
- __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
- __I uint8_t OVF:1; /*!< bit: 7 Overflow */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t ALARM:1; /*!< bit: 0 Alarm x */
- __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
+ __I uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ __I uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t ALARM:1; /*!< bit: 0 Alarm x */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -723,11 +723,11 @@
/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -741,11 +741,11 @@
/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -759,11 +759,11 @@
/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
- uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
+ uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_FREQCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -780,10 +780,10 @@
/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE0_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -798,10 +798,10 @@
/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -816,15 +816,15 @@
/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
- uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
- uint32_t HOUR:5; /*!< bit: 12..16 Hour */
- uint32_t DAY:5; /*!< bit: 17..21 Day */
- uint32_t MONTH:4; /*!< bit: 22..25 Month */
- uint32_t YEAR:6; /*!< bit: 26..31 Year */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE2_CLOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -856,10 +856,10 @@
/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PER:16; /*!< bit: 0..15 Counter Period */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PER:16; /*!< bit: 0..15 Counter Period */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -874,10 +874,10 @@
/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE0_COMP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -892,10 +892,10 @@
/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_COMP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -910,15 +910,15 @@
/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
- uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
- uint32_t HOUR:5; /*!< bit: 12..16 Hour */
- uint32_t DAY:5; /*!< bit: 17..21 Day */
- uint32_t MONTH:4; /*!< bit: 22..25 Month */
- uint32_t YEAR:6; /*!< bit: 26..31 Year */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE2_ALARM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -948,11 +948,11 @@
/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_MASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -981,79 +981,79 @@
/** \brief RtcMode2Alarm hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
- __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
- RoReg8 Reserved1[0x3];
+ __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
+ __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
+ RoReg8 Reserved1[0x3];
} RtcMode2Alarm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE0 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter with Single 32-bit Compare */
- __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
- __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
- __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
- __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
- __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
- __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
- __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
- RoReg8 Reserved2[0x3];
- __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
- RoReg8 Reserved3[0x4];
- __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
+ __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
+ __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
+ __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
+ __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
} RtcMode0;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE1 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter with Two 16-bit Compares */
- __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
- __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
- __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
- __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
- __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
- __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
- __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
- RoReg8 Reserved2[0x3];
- __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
- RoReg8 Reserved3[0x2];
- __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
- RoReg8 Reserved4[0x2];
- __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
+ __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
+ __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
+ __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
+ __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
+ RoReg8 Reserved3[0x2];
+ __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
+ RoReg8 Reserved4[0x2];
+ __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
} RtcMode1;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE2 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* Clock/Calendar with Alarm */
- __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
- __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
- __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
- __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
- __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
- __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
- __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
- RoReg8 Reserved2[0x3];
- __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
- RoReg8 Reserved3[0x4];
- RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
+ __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
+ __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
+ __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
+ __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
+ RoReg8 Reserved3[0x4];
+ RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
} RtcMode2;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
- RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
- RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
+ RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
+ RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
+ RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
} Rtc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sercom.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sercom.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,26 +56,26 @@
/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
- uint32_t :3; /*!< bit: 17..19 Reserved */
- uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
- uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
- uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
- uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
- uint32_t :1; /*!< bit: 26 Reserved */
- uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
- uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
- uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -127,26 +127,26 @@
/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
- uint32_t :3; /*!< bit: 17..19 Reserved */
- uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
- uint32_t :1; /*!< bit: 22 Reserved */
- uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
- uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
- uint32_t :1; /*!< bit: 26 Reserved */
- uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
- uint32_t :2; /*!< bit: 28..29 Reserved */
- uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -193,25 +193,25 @@
/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
- uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
- uint32_t :7; /*!< bit: 9..15 Reserved */
- uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
- uint32_t :2; /*!< bit: 18..19 Reserved */
- uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
- uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
- uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
- uint32_t DORD:1; /*!< bit: 30 Data Order */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -261,26 +261,26 @@
/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
- uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
- uint32_t :4; /*!< bit: 9..12 Reserved */
- uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
- uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
- uint32_t :2; /*!< bit: 18..19 Reserved */
- uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
- uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
- uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
- uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
- uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
- uint32_t DORD:1; /*!< bit: 30 Data Order */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :4; /*!< bit: 9..12 Reserved */
+ uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
+ uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
+ uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_USART_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -336,16 +336,16 @@
/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
- uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
- uint32_t :6; /*!< bit: 10..15 Reserved */
- uint32_t CMD:2; /*!< bit: 16..17 Command */
- uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -366,18 +366,18 @@
/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
- uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
- uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
- uint32_t :3; /*!< bit: 11..13 Reserved */
- uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
- uint32_t CMD:2; /*!< bit: 16..17 Command */
- uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
+ uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
+ uint32_t :3; /*!< bit: 11..13 Reserved */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -403,20 +403,20 @@
/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
- uint32_t :3; /*!< bit: 3.. 5 Reserved */
- uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
- uint32_t :2; /*!< bit: 7.. 8 Reserved */
- uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
- uint32_t :3; /*!< bit: 10..12 Reserved */
- uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
- uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
- uint32_t :1; /*!< bit: 16 Reserved */
- uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
+ uint32_t :2; /*!< bit: 7.. 8 Reserved */
+ uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
+ uint32_t :3; /*!< bit: 10..12 Reserved */
+ uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -442,22 +442,22 @@
/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
- uint32_t :3; /*!< bit: 3.. 5 Reserved */
- uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
- uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
- uint32_t ENC:1; /*!< bit: 10 Encoding Format */
- uint32_t :2; /*!< bit: 11..12 Reserved */
- uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
- uint32_t :2; /*!< bit: 14..15 Reserved */
- uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
- uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
+ uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
+ uint32_t ENC:1; /*!< bit: 10 Encoding Format */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_USART_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -486,13 +486,13 @@
/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
- uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
- uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
- uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
+ uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
+ uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_BAUD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -516,10 +516,10 @@
/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_BAUD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -534,21 +534,21 @@
/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
- } bit; /*!< Structure used for bit access */
- struct { // FRAC mode
- uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
- uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
- } FRAC; /*!< Structure used for FRAC */
- struct { // FRACFP mode
- uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
- uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
- } FRACFP; /*!< Structure used for FRACFP */
- struct { // USARTFP mode
- uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
- } USARTFP; /*!< Structure used for USARTFP */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ struct { // FRAC mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRAC; /*!< Structure used for FRAC */
+ struct { // FRACFP mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRACFP; /*!< Structure used for FRACFP */
+ struct { // USARTFP mode
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } USARTFP; /*!< Structure used for USARTFP */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_USART_BAUD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -587,10 +587,10 @@
/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_RXPL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -605,13 +605,13 @@
/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
- uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -629,14 +629,14 @@
/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
- uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
- uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -656,15 +656,15 @@
/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
- uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -686,17 +686,17 @@
/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
- uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
- uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
- uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
- uint8_t :1; /*!< bit: 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -722,13 +722,13 @@
/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
- uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -746,14 +746,14 @@
/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
- uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
- uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -773,15 +773,15 @@
/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
- uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -803,17 +803,17 @@
/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
- uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
- uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
- uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
- uint8_t :1; /*!< bit: 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -839,13 +839,13 @@
/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
- __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
- __I uint8_t :5; /*!< bit: 2.. 6 Reserved */
- __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
+ __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
+ __I uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -863,14 +863,14 @@
/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
- __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
- __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
- __I uint8_t :4; /*!< bit: 3.. 6 Reserved */
- __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
+ __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
+ __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
+ __I uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -890,15 +890,15 @@
/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
- __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
- __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
- __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
- __I uint8_t :3; /*!< bit: 4.. 6 Reserved */
- __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
+ __I uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -920,17 +920,17 @@
/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
- __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
- __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
- __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
- __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
- __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
- __I uint8_t :1; /*!< bit: 6 Reserved */
- __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
+ __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
+ __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
+ __I uint8_t :1; /*!< bit: 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -956,20 +956,20 @@
/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
- uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
- uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
- uint16_t :1; /*!< bit: 3 Reserved */
- uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
- uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
- uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
- uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
- uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
- uint16_t LENERR:1; /*!< bit: 10 Length Error */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t LENERR:1; /*!< bit: 10 Length Error */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_I2CM_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1000,21 +1000,21 @@
/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
- uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
- uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
- uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
- uint16_t SR:1; /*!< bit: 4 Repeated Start */
- uint16_t :1; /*!< bit: 5 Reserved */
- uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
- uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
- uint16_t :1; /*!< bit: 8 Reserved */
- uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
- uint16_t HS:1; /*!< bit: 10 High Speed */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
+ uint16_t SR:1; /*!< bit: 4 Repeated Start */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t :1; /*!< bit: 8 Reserved */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t HS:1; /*!< bit: 10 High Speed */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_I2CS_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1044,12 +1044,12 @@
/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
- uint16_t :13; /*!< bit: 3..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t :13; /*!< bit: 3..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_SPI_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1063,16 +1063,16 @@
/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PERR:1; /*!< bit: 0 Parity Error */
- uint16_t FERR:1; /*!< bit: 1 Frame Error */
- uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
- uint16_t CTS:1; /*!< bit: 3 Clear To Send */
- uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
- uint16_t COLL:1; /*!< bit: 5 Collision Detected */
- uint16_t :10; /*!< bit: 6..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PERR:1; /*!< bit: 0 Parity Error */
+ uint16_t FERR:1; /*!< bit: 1 Frame Error */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t CTS:1; /*!< bit: 3 Clear To Send */
+ uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
+ uint16_t COLL:1; /*!< bit: 5 Collision Detected */
+ uint16_t :10; /*!< bit: 6..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_USART_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1096,13 +1096,13 @@
/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1120,12 +1120,12 @@
/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1141,13 +1141,13 @@
/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1165,13 +1165,13 @@
/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_USART_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1189,16 +1189,16 @@
/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
- uint32_t :2; /*!< bit: 11..12 Reserved */
- uint32_t LENEN:1; /*!< bit: 13 Length Enable */
- uint32_t HS:1; /*!< bit: 14 High Speed Mode */
- uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
- uint32_t LEN:8; /*!< bit: 16..23 Length */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t LENEN:1; /*!< bit: 13 Length Enable */
+ uint32_t HS:1; /*!< bit: 14 High Speed Mode */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t LEN:8; /*!< bit: 16..23 Length */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1222,16 +1222,16 @@
/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
- uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
- uint32_t :4; /*!< bit: 11..14 Reserved */
- uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
- uint32_t :1; /*!< bit: 16 Reserved */
- uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
+ uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
+ uint32_t :4; /*!< bit: 11..14 Reserved */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1253,13 +1253,13 @@
/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1277,10 +1277,10 @@
/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1295,10 +1295,10 @@
/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1313,11 +1313,11 @@
/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */
- uint32_t :23; /*!< bit: 9..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */
+ uint32_t :23; /*!< bit: 9..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1332,11 +1332,11 @@
/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_USART_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1351,11 +1351,11 @@
/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1369,11 +1369,11 @@
/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1387,11 +1387,11 @@
/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1405,101 +1405,101 @@
/** \brief SERCOM_I2CM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* I2C Master Mode */
- __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
- __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
- RoReg8 Reserved1[0x4];
- __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
- RoReg8 Reserved2[0x4];
- __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
- RoReg8 Reserved5[0x1];
- __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
- __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
- RoReg8 Reserved6[0x4];
- __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
- __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
- RoReg8 Reserved7[0x7];
- __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
+ __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
+ __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
+ RoReg8 Reserved2[0x4];
+ __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
+ __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
+ __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
+ RoReg8 Reserved7[0x7];
+ __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
} SercomI2cm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief SERCOM_I2CS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* I2C Slave Mode */
- __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
- __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
- RoReg8 Reserved1[0xC];
- __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
- RoReg8 Reserved2[0x1];
- __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
- __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
- RoReg8 Reserved5[0x4];
- __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
- __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
+ __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
+ __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
+ RoReg8 Reserved1[0xC];
+ __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
+ RoReg8 Reserved2[0x1];
+ __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
+ __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
+ RoReg8 Reserved5[0x4];
+ __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
+ __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
} SercomI2cs;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief SERCOM_SPI hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* SPI Mode */
- __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
- __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
- RoReg8 Reserved1[0x4];
- __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
- RoReg8 Reserved2[0x7];
- __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
- RoReg8 Reserved5[0x1];
- __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
- __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
- RoReg8 Reserved6[0x4];
- __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
- __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
- RoReg8 Reserved7[0x4];
- __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
+ __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
+ __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
+ RoReg8 Reserved2[0x7];
+ __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
+ __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
+ __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
+ RoReg8 Reserved7[0x4];
+ __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
} SercomSpi;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief SERCOM_USART hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USART Mode */
- __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
- __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
- RoReg8 Reserved1[0x4];
- __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
- __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
- RoReg8 Reserved2[0x5];
- __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
- RoReg8 Reserved5[0x1];
- __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
- __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
- RoReg8 Reserved6[0x8];
- __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
- RoReg8 Reserved7[0x6];
- __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
+ __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
+ __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
+ __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
+ RoReg8 Reserved2[0x5];
+ __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
+ __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
+ RoReg8 Reserved6[0x8];
+ __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
+ RoReg8 Reserved7[0x6];
+ __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
} SercomUsart;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
- SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
- SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
- SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
+ SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
+ SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
+ SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
+ SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
} Sercom;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sysctrl.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sysctrl.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,26 +56,26 @@
/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
- uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
- uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
- uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
- uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
- uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
- uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
- uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
- uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
- uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
- uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
- uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
- uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
- uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -117,26 +117,26 @@
/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
- uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
- uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
- uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
- uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
- uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
- uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
- uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
- uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
- uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
- uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
- uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
- uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
- uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -178,26 +178,26 @@
/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
- __I uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
- __I uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
- __I uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
- __I uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
- __I uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
- __I uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
- __I uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
- __I uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
- __I uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
- __I uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
- __I uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
- __I uint32_t :3; /*!< bit: 12..14 Reserved */
- __I uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
- __I uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
- __I uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
- __I uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ __I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
+ __I uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
+ __I uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
+ __I uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
+ __I uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
+ __I uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
+ __I uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
+ __I uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
+ __I uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
+ __I uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
+ __I uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
+ __I uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
+ __I uint32_t :3; /*!< bit: 12..14 Reserved */
+ __I uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
+ __I uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
+ __I uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
+ __I uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -239,26 +239,26 @@
/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
- uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
- uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
- uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
- uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
- uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
- uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
- uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
- uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
- uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
- uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
- uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
- uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
- uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_PCLKSR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -300,18 +300,18 @@
/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
- uint16_t :3; /*!< bit: 3.. 5 Reserved */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
- uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
- uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t :3; /*!< bit: 3.. 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
+ uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
+ uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_XOSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -349,21 +349,21 @@
/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
- uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
- uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
- uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
- uint16_t :1; /*!< bit: 11 Reserved */
- uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
- uint16_t :3; /*!< bit: 13..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
+ uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
+ uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_XOSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -394,22 +394,22 @@
/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
- uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
- uint32_t :2; /*!< bit: 4.. 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
+ uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
+ uint32_t :2; /*!< bit: 4.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_OSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -439,12 +439,12 @@
/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
- uint8_t :2; /*!< bit: 5.. 6 Reserved */
- uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */
+ uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_OSCULP32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -461,19 +461,19 @@
/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint32_t :4; /*!< bit: 2.. 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
- uint32_t :6; /*!< bit: 10..15 Reserved */
- uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
- uint32_t :2; /*!< bit: 28..29 Reserved */
- uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t :4; /*!< bit: 2.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_OSC8M_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -516,22 +516,22 @@
/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
- uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
- uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
- uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
- uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
- uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
- uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
- uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
+ uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
+ uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
+ uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
+ uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
+ uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
+ uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
+ uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -565,12 +565,12 @@
/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
- uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
- uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
+ uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
+ uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLVAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -591,12 +591,12 @@
/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
- uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
- uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
+ uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
+ uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLMUL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -617,11 +617,11 @@
/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t READREQ:1; /*!< bit: 7 Read Request */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t READREQ:1; /*!< bit: 7 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLSYNC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -635,22 +635,22 @@
/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t HYST:1; /*!< bit: 2 Hysteresis */
- uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
- uint32_t :1; /*!< bit: 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t MODE:1; /*!< bit: 8 Operation Mode */
- uint32_t CEN:1; /*!< bit: 9 Clock Enable */
- uint32_t :2; /*!< bit: 10..11 Reserved */
- uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
- uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t HYST:1; /*!< bit: 2 Hysteresis */
+ uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MODE:1; /*!< bit: 8 Operation Mode */
+ uint32_t CEN:1; /*!< bit: 9 Clock Enable */
+ uint32_t :2; /*!< bit: 10..11 Reserved */
+ uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
+ uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_BOD33_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -719,14 +719,14 @@
/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :6; /*!< bit: 0.. 5 Reserved */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t :6; /*!< bit: 7..12 Reserved */
- uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :6; /*!< bit: 0.. 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t :6; /*!< bit: 7..12 Reserved */
+ uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_VREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -742,15 +742,15 @@
/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
- uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
- uint32_t :13; /*!< bit: 3..15 Reserved */
- uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
+ uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
+ uint32_t :13; /*!< bit: 3..15 Reserved */
+ uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_VREF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -769,14 +769,14 @@
/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -794,13 +794,13 @@
/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLRATIO_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -818,20 +818,20 @@
/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
- uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
- uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
- uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
- uint32_t :2; /*!< bit: 6.. 7 Reserved */
- uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
+ uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
+ uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
+ uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -885,14 +885,14 @@
/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
- uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
- uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
- uint8_t DIV:1; /*!< bit: 3 Divider Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
+ uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
+ uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
+ uint8_t DIV:1; /*!< bit: 3 Divider Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -912,34 +912,34 @@
/** \brief SYSCTRL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
- __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
- __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
- __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
- __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
- RoReg8 Reserved1[0x2];
- __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
- RoReg8 Reserved2[0x2];
- __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
- __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
- RoReg8 Reserved3[0x3];
- __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
- __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
- RoReg8 Reserved4[0x2];
- __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
- __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
- __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
- RoReg8 Reserved5[0x3];
- __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
- RoReg8 Reserved6[0x4];
- __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
- RoReg8 Reserved7[0x2];
- __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
- __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
- RoReg8 Reserved8[0x3];
- __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
- __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
- __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
+ __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+ __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+ __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+ __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
+ __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
+ RoReg8 Reserved1[0x2];
+ __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
+ RoReg8 Reserved2[0x2];
+ __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
+ __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+ RoReg8 Reserved3[0x3];
+ __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
+ __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
+ RoReg8 Reserved4[0x2];
+ __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
+ __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
+ __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
+ RoReg8 Reserved5[0x3];
+ __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
+ RoReg8 Reserved6[0x4];
+ __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
+ RoReg8 Reserved7[0x2];
+ __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
+ __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
+ RoReg8 Reserved8[0x3];
+ __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
+ __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
+ __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
} Sysctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tc.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tc.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,19 +56,19 @@
/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
- uint16_t :1; /*!< bit: 4 Reserved */
- uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
- uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
- uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -134,13 +134,13 @@
/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
- uint16_t :9; /*!< bit: 5..13 Reserved */
- uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
- uint16_t RREQ:1; /*!< bit: 15 Read Request */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
+ uint16_t :9; /*!< bit: 5..13 Reserved */
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_READREQ_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -159,14 +159,14 @@
/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t :3; /*!< bit: 3.. 5 Reserved */
- uint8_t CMD:2; /*!< bit: 6.. 7 Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -191,14 +191,14 @@
/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t :3; /*!< bit: 3.. 5 Reserved */
- uint8_t CMD:2; /*!< bit: 6.. 7 Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -223,21 +223,21 @@
/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
- uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
- uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
+ uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
+ uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_CTRLC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -263,11 +263,11 @@
/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -281,24 +281,24 @@
/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
- uint16_t :1; /*!< bit: 3 Reserved */
- uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
- uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
- uint16_t :3; /*!< bit: 9..11 Reserved */
- uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
- uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :12; /*!< bit: 0..11 Reserved */
- uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
+ uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
+ uint16_t :3; /*!< bit: 9..11 Reserved */
+ uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
+ uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :12; /*!< bit: 0..11 Reserved */
+ uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -338,21 +338,21 @@
/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :1; /*!< bit: 2 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
- uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -377,21 +377,21 @@
/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :1; /*!< bit: 2 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
- uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -416,21 +416,21 @@
/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t OVF:1; /*!< bit: 0 Overflow */
- __I uint8_t ERR:1; /*!< bit: 1 Error */
- __I uint8_t :1; /*!< bit: 2 Reserved */
- __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
- __I uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
- __I uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
- __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
- __I uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
- __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t OVF:1; /*!< bit: 0 Overflow */
+ __I uint8_t ERR:1; /*!< bit: 1 Error */
+ __I uint8_t :1; /*!< bit: 2 Reserved */
+ __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
+ __I uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
+ __I uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ __I uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -455,14 +455,14 @@
/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :3; /*!< bit: 0.. 2 Reserved */
- uint8_t STOP:1; /*!< bit: 3 Stop */
- uint8_t SLAVE:1; /*!< bit: 4 Slave */
- uint8_t :2; /*!< bit: 5.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :3; /*!< bit: 0.. 2 Reserved */
+ uint8_t STOP:1; /*!< bit: 3 Stop */
+ uint8_t SLAVE:1; /*!< bit: 4 Slave */
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -480,10 +480,10 @@
/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -498,10 +498,10 @@
/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -516,10 +516,10 @@
/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -534,10 +534,10 @@
/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -552,10 +552,10 @@
/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -570,10 +570,10 @@
/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -588,10 +588,10 @@
/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -606,76 +606,76 @@
/** \brief TC_COUNT8 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 8-bit Counter Mode */
- __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
- RoReg8 Reserved1[0x1];
- __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
- RoReg8 Reserved2[0x1];
- __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
- __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
- __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
- __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
- __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
- RoReg8 Reserved3[0x3];
- __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
- RoReg8 Reserved4[0x3];
- __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
+ RoReg8 Reserved3[0x3];
+ __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
+ RoReg8 Reserved4[0x3];
+ __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
} TcCount8;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT16 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter Mode */
- __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
- RoReg8 Reserved1[0x1];
- __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
- RoReg8 Reserved2[0x1];
- __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
- __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
- __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
- __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
- __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
- RoReg8 Reserved3[0x6];
- __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
+ RoReg8 Reserved3[0x6];
+ __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
} TcCount16;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT32 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter Mode */
- __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
- RoReg8 Reserved1[0x1];
- __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
- RoReg8 Reserved2[0x1];
- __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
- __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
- __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
- __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
- __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
- RoReg8 Reserved3[0x4];
- __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
} TcCount32;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
- TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
- TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
+ TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
+ TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
+ TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
} Tc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tcc.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tcc.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,29 +56,29 @@
/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t :3; /*!< bit: 2.. 4 Reserved */
- uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
- uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
- uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
- uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
- uint32_t :9; /*!< bit: 15..23 Reserved */
- uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
- uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
- uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
- uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :24; /*!< bit: 0..23 Reserved */
- uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :3; /*!< bit: 2.. 4 Reserved */
+ uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
+ uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
+ uint32_t :9; /*!< bit: 15..23 Reserved */
+ uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
+ uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
+ uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
+ uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :24; /*!< bit: 0..23 Reserved */
+ uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -148,14 +148,14 @@
/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
- uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -197,14 +197,14 @@
/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
- uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -246,37 +246,37 @@
/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
- uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
- uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
- uint32_t STATUS:1; /*!< bit: 3 Status Busy */
- uint32_t COUNT:1; /*!< bit: 4 Count Busy */
- uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
- uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
- uint32_t PER:1; /*!< bit: 7 Period busy */
- uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
- uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
- uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
- uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
- uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
- uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
- uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
- uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
- uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
- uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
- uint32_t :7; /*!< bit: 12..18 Reserved */
- uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
+ uint32_t STATUS:1; /*!< bit: 3 Status Busy */
+ uint32_t COUNT:1; /*!< bit: 4 Count Busy */
+ uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
+ uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
+ uint32_t PER:1; /*!< bit: 7 Period busy */
+ uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
+ uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
+ uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
+ uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
+ uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
+ uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
+ uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
+ uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
+ uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
+ uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
+ uint32_t :7; /*!< bit: 12..18 Reserved */
+ uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -332,22 +332,22 @@
/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
- uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
- uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
- uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
- uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
- uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
- uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
- uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_FCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -432,22 +432,22 @@
/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
- uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
- uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
- uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
- uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
- uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
- uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
- uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_FCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -532,23 +532,23 @@
/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
- uint32_t :6; /*!< bit: 2.. 7 Reserved */
- uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
- uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
- uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
- uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
- uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
+ uint32_t :6; /*!< bit: 2.. 7 Reserved */
+ uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
+ uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
+ uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
+ uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
+ uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WEXCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -580,41 +580,41 @@
/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
- uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
- uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
- uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
- uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
- uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
- uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
- uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
- uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
- uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
- uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
- uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
- uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
- uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
- uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
- uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
- uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
- uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
- uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
- uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
- uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
- uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
- uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
- uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
- uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
- uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
- uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
- uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
+ uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
+ uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
+ uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
+ uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
+ uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
+ uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
+ uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
+ uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
+ uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
+ uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
+ uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
+ uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
+ uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
+ uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
+ uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
+ uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
+ uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
+ uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
+ uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
+ uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
+ uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
+ uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
+ uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
+ uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
+ uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
+ uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
+ uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_DRVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -689,13 +689,13 @@
/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -711,39 +711,39 @@
/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
- uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
- uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
- uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
- uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
- uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
- uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
- uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
- uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
- uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
- uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
- uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
- uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
- uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
- uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
- uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :12; /*!< bit: 0..11 Reserved */
- uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
- uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
- uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
+ uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
+ uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
+ uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
+ uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
+ uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
+ uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
+ uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
+ uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
+ uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
+ uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
+ uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
+ uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
+ uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
+ uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
+ uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :12; /*!< bit: 0..11 Reserved */
+ uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
+ uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
+ uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -844,29 +844,29 @@
/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
- uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
- uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
- uint32_t :7; /*!< bit: 4..10 Reserved */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -907,29 +907,29 @@
/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
- uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
- uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
- uint32_t :7; /*!< bit: 4..10 Reserved */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -970,29 +970,29 @@
/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t OVF:1; /*!< bit: 0 Overflow */
- __I uint32_t TRG:1; /*!< bit: 1 Retrigger */
- __I uint32_t CNT:1; /*!< bit: 2 Counter */
- __I uint32_t ERR:1; /*!< bit: 3 Error */
- __I uint32_t :7; /*!< bit: 4..10 Reserved */
- __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
- __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
- __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
- __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
- __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
- __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
- __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
- __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
- __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
- __I uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint32_t :16; /*!< bit: 0..15 Reserved */
- __I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
- __I uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ __I uint32_t OVF:1; /*!< bit: 0 Overflow */
+ __I uint32_t TRG:1; /*!< bit: 1 Retrigger */
+ __I uint32_t CNT:1; /*!< bit: 2 Counter */
+ __I uint32_t ERR:1; /*!< bit: 3 Error */
+ __I uint32_t :7; /*!< bit: 4..10 Reserved */
+ __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
+ __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
+ __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
+ __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
+ __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
+ __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
+ __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
+ __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
+ __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
+ __I uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint32_t :16; /*!< bit: 0..15 Reserved */
+ __I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
+ __I uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1033,42 +1033,42 @@
/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t STOP:1; /*!< bit: 0 Stop */
- uint32_t IDX:1; /*!< bit: 1 Ramp */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
- uint32_t SLAVE:1; /*!< bit: 4 Slave */
- uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
- uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
- uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
- uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
- uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
- uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
- uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
- uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
- uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
- uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
- uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
- uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
- uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
- uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t STOP:1; /*!< bit: 0 Stop */
+ uint32_t IDX:1; /*!< bit: 1 Ramp */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
+ uint32_t SLAVE:1; /*!< bit: 4 Slave */
+ uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
+ uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
+ uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
+ uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
+ uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
+ uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
+ uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
+ uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
+ uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
+ uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
+ uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
+ uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
+ uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
+ uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1132,26 +1132,26 @@
/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t :4; /*!< bit: 0.. 3 Reserved */
- uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t :5; /*!< bit: 0.. 4 Reserved */
- uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t :6; /*!< bit: 0.. 5 Reserved */
- uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t :4; /*!< bit: 0.. 3 Reserved */
+ uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t :6; /*!< bit: 0.. 5 Reserved */
+ uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1184,29 +1184,29 @@
/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
- uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
- uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
- uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
- uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
- uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
- uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
- uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
- uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
- uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
- uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
- uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
- uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
- uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
- uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
- uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
- uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
+ uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
+ uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
+ uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
+ uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
+ uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
+ uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
+ uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
+ uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
+ uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
+ uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
+ uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
+ uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
+ uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
+ uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
+ uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
+ uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TCC_PATT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1256,38 +1256,38 @@
/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
- uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
- uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
- uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
- uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
- uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
- uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
- uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
- uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
- uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
- uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
+ uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
+ uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
+ uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
+ uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
+ uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
+ uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
+ uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
+ uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
+ uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
+ uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WAVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1360,26 +1360,26 @@
/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
- uint32_t PER:20; /*!< bit: 4..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
- uint32_t PER:19; /*!< bit: 5..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
- uint32_t PER:18; /*!< bit: 6..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t PER:24; /*!< bit: 0..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t PER:20; /*!< bit: 4..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t PER:19; /*!< bit: 5..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t PER:18; /*!< bit: 6..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PER:24; /*!< bit: 0..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1421,26 +1421,26 @@
/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
- uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
- uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
- uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1482,29 +1482,29 @@
/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
- uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
- uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
- uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
- uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
- uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
- uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
- uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
- uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
- uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
- uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
- uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
- uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
- uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
- uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
- uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
- uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
+ uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
+ uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
+ uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
+ uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
+ uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
+ uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
+ uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
+ uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
+ uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
+ uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
+ uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
+ uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
+ uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
+ uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
+ uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
+ uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TCC_PATTB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1554,38 +1554,38 @@
/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
- uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
- uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
- uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
- uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
- uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
- uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
- uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
- uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
- uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
- uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
+ uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
+ uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
+ uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
+ uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
+ uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
+ uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
+ uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
+ uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
+ uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
+ uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WAVEB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1658,26 +1658,26 @@
/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
- uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
- uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
- uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_PERB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1719,26 +1719,26 @@
/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
- uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
- uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
- uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CCB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1780,35 +1780,35 @@
/** \brief TCC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
- __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- RoReg8 Reserved1[0x2];
- __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
- __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
- __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
- __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
- __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
- RoReg8 Reserved2[0x2];
- __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
- RoReg8 Reserved3[0x1];
- __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
- __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
- __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
- __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
- __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
- __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
- __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
- RoReg8 Reserved4[0x2];
- __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
- __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
- __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
- RoReg8 Reserved5[0x10];
- __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
- RoReg8 Reserved6[0x2];
- __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
- __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
- __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+ __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ RoReg8 Reserved1[0x2];
+ __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
+ __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+ __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+ __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+ __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+ RoReg8 Reserved2[0x2];
+ __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
+ RoReg8 Reserved3[0x1];
+ __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
+ __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+ __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+ __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+ __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
+ __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
+ __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
+ RoReg8 Reserved4[0x2];
+ __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+ __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
+ __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+ RoReg8 Reserved5[0x10];
+ __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+ RoReg8 Reserved6[0x2];
+ __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
+ __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+ __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
} Tcc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_usb.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_usb.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,14 +56,14 @@
/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t MODE:1; /*!< bit: 7 Operating Mode */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t MODE:1; /*!< bit: 7 Operating Mode */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -87,12 +87,12 @@
/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -108,12 +108,12 @@
/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */
- uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */
+ uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_QOSCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -147,20 +147,20 @@
/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DETACH:1; /*!< bit: 0 Detach */
- uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
- uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
- uint16_t NREPLY:1; /*!< bit: 4 No Reply */
- uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
- uint16_t TSTK:1; /*!< bit: 6 Test mode K */
- uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
- uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
- uint16_t GNAK:1; /*!< bit: 9 Global NAK */
- uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DETACH:1; /*!< bit: 0 Detach */
+ uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
+ uint16_t NREPLY:1; /*!< bit: 4 No Reply */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
+ uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
+ uint16_t GNAK:1; /*!< bit: 9 Global NAK */
+ uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -210,21 +210,21 @@
/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
- uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
- uint16_t :1; /*!< bit: 4 Reserved */
- uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
- uint16_t TSTK:1; /*!< bit: 6 Test mode K */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
- uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
- uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
- uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
+ uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
+ uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
+ uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -257,11 +257,11 @@
/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
- uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
+ uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_DADD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -278,12 +278,12 @@
/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_HSOFC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -300,13 +300,13 @@
/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
- uint8_t :2; /*!< bit: 4.. 5 Reserved */
- uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -336,13 +336,13 @@
/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
- uint8_t :2; /*!< bit: 4.. 5 Reserved */
- uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -360,11 +360,11 @@
/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_FSMSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -393,13 +393,13 @@
/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
- uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
- uint16_t :1; /*!< bit: 14 Reserved */
- uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :1; /*!< bit: 14 Reserved */
+ uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_FNUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -419,12 +419,12 @@
/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
- uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_FNUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -442,10 +442,10 @@
/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_FLENHIGH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -460,20 +460,20 @@
/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
- uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
- uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
- uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
- uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
- uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
- uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -505,19 +505,19 @@
/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
- uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
- uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
- uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
- uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
+ uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
+ uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -545,20 +545,20 @@
/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
- uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
- uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
- uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
- uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
- uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
- uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -590,19 +590,19 @@
/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
- uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
- uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
- uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
- uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
+ uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -630,20 +630,20 @@
/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
- __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
- __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
- __I uint16_t EORST:1; /*!< bit: 3 End of Reset */
- __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
- __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
- __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
- __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
- __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
- __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
- __I uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
+ __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
+ __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
+ __I uint16_t EORST:1; /*!< bit: 3 End of Reset */
+ __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
+ __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
+ __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
+ __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
+ __I uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -675,19 +675,19 @@
/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint16_t :2; /*!< bit: 0.. 1 Reserved */
- __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
- __I uint16_t RST:1; /*!< bit: 3 Bus Reset */
- __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
- __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */
- __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
- __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
- __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */
- __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
- __I uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ __I uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
+ __I uint16_t RST:1; /*!< bit: 3 Bus Reset */
+ __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */
+ __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
+ __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */
+ __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
+ __I uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -715,22 +715,22 @@
/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
- uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
- uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
- uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
- uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
- uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
- uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
- uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTSMRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -761,22 +761,22 @@
/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
- uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
- uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
- uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
- uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
- uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
- uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
- uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_PINTSMRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -807,10 +807,10 @@
/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_DESCADD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -825,15 +825,15 @@
/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
- uint16_t :1; /*!< bit: 5 Reserved */
- uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
- uint16_t :1; /*!< bit: 11 Reserved */
- uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_PADCAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -854,13 +854,13 @@
/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
- uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
+ uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -880,13 +880,13 @@
/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
- uint8_t BK:1; /*!< bit: 2 Pipe Bank */
- uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
+ uint8_t BK:1; /*!< bit: 2 Pipe Bank */
+ uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -906,10 +906,10 @@
/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_BINTERVAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -924,22 +924,22 @@
/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
- uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
- uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
- uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPSTATUSCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -968,17 +968,17 @@
/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PSTATUSCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1000,22 +1000,22 @@
/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
- uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
- uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPSTATUSSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1044,17 +1044,17 @@
/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PSTATUSSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1076,22 +1076,22 @@
/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
- uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
- uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1120,17 +1120,17 @@
/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1152,24 +1152,24 @@
/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
- __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
- __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
- __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
- __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
- __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
- __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
- __I uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
- __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
- __I uint8_t :1; /*!< bit: 4 Reserved */
- __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
- __I uint8_t :1; /*!< bit: 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
+ __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
+ __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
+ __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
+ __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
+ __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
+ __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
+ __I uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
+ __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
+ __I uint8_t :1; /*!< bit: 4 Reserved */
+ __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
+ __I uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1204,20 +1204,20 @@
/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
- __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
- __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
- __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
- __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
- __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
- __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
- __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
+ __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
+ __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
+ __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
+ __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
+ __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1244,24 +1244,24 @@
/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
- uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
- uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
- uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
- uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
- uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
- uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
- uint8_t :1; /*!< bit: 4 Reserved */
- uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1296,20 +1296,20 @@
/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
- uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
- uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
- uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
- uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1336,24 +1336,24 @@
/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
- uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
- uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
- uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
- uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
- uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
- uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
- uint8_t :1; /*!< bit: 4 Reserved */
- uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1388,20 +1388,20 @@
/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
- uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
- uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
- uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
- uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1428,10 +1428,10 @@
/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_DEVICE_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1445,10 +1445,10 @@
/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_HOST_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1462,13 +1462,13 @@
/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
- uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
- uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
- uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_DEVICE_PCKSIZE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1490,13 +1490,13 @@
/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
- uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
- uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
- uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_HOST_PCKSIZE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1518,12 +1518,12 @@
/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
- uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_EXTREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1540,12 +1540,12 @@
/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
- uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_EXTREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1562,12 +1562,12 @@
/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
- uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_STATUS_BK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1582,12 +1582,12 @@
/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
- uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_STATUS_BK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1602,13 +1602,13 @@
/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
- uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
+ uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_CTRL_PIPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1629,16 +1629,16 @@
/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
- uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
- uint16_t PIDER:1; /*!< bit: 2 PID Error */
- uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
- uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
- uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
+ uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
+ uint16_t PIDER:1; /*!< bit: 2 PID Error */
+ uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
+ uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
+ uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_STATUS_PIPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1662,140 +1662,140 @@
/** \brief UsbDeviceDescBank SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
- __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
- __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
- __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
- RoReg8 Reserved1[0x5];
+ __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+ __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+ __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
+ __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+ RoReg8 Reserved1[0x5];
} UsbDeviceDescBank;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief UsbHostDescBank SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
- __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
- __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
- __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
- RoReg8 Reserved1[0x1];
- __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
- __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
+ __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+ __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
+ __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
+ __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
+ RoReg8 Reserved1[0x1];
+ __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
+ __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
} UsbHostDescBank;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief UsbDeviceEndpoint hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
- RoReg8 Reserved1[0x3];
- __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
- __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
- __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
- __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
- __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
- __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
- RoReg8 Reserved2[0x16];
+ __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
+ RoReg8 Reserved1[0x3];
+ __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
+ __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
+ __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
+ __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
+ __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+ __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+ RoReg8 Reserved2[0x16];
} UsbDeviceEndpoint;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief UsbHostPipe hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
- RoReg8 Reserved1[0x2];
- __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
- __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
- __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
- __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
- __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
- __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
- __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
- RoReg8 Reserved2[0x16];
+ __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
+ RoReg8 Reserved1[0x2];
+ __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
+ __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
+ __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
+ __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
+ __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
+ __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
+ __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
+ RoReg8 Reserved2[0x16];
} UsbHostPipe;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_DEVICE APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Device */
- __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
- RoReg8 Reserved1[0x1];
- __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
- __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
- RoReg8 Reserved2[0x4];
- __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
- __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
- RoReg8 Reserved3[0x1];
- __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
- __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
- RoReg8 Reserved4[0x2];
- __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
- RoReg8 Reserved5[0x2];
- __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
- RoReg8 Reserved6[0x2];
- __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
- RoReg8 Reserved7[0x2];
- __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
- RoReg8 Reserved8[0x2];
- __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
- RoReg8 Reserved9[0x2];
- __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
- __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
- RoReg8 Reserved10[0xD6];
- UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
+ __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
+ RoReg8 Reserved3[0x1];
+ __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
+ RoReg8 Reserved5[0x2];
+ __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
} UsbDevice;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_HOST hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Host */
- __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
- RoReg8 Reserved1[0x1];
- __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
- __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
- RoReg8 Reserved2[0x4];
- __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
- __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
- RoReg8 Reserved3[0x1];
- __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
- __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
- RoReg8 Reserved4[0x2];
- __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
- __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
- RoReg8 Reserved5[0x1];
- __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
- RoReg8 Reserved6[0x2];
- __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
- RoReg8 Reserved7[0x2];
- __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
- RoReg8 Reserved8[0x2];
- __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
- RoReg8 Reserved9[0x2];
- __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
- __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
- RoReg8 Reserved10[0xD6];
- UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
+ __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
+ RoReg8 Reserved3[0x1];
+ __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
+ __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
+ RoReg8 Reserved5[0x1];
+ __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */
} UsbHost;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_DEVICE Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Device */
- UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
+ UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
} UsbDeviceDescriptor;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_HOST Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Host */
- UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
+ UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
} UsbHostDescriptor;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_USB_DESCRIPTOR
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
- UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
+ UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
+ UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
} Usb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_wdt.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_wdt.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,14 +56,14 @@
/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -81,11 +81,11 @@
/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
- uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
+ uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -151,11 +151,11 @@
/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_EWCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -194,11 +194,11 @@
/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -212,11 +212,11 @@
/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -230,11 +230,11 @@
/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t EW:1; /*!< bit: 0 Early Warning */
- __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t EW:1; /*!< bit: 0 Early Warning */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -248,11 +248,11 @@
/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -266,10 +266,10 @@
/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_CLEAR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -286,15 +286,15 @@
/** \brief WDT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
- __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
- __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
- RoReg8 Reserved1[0x1];
- __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
- __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
- __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
- __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
- __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
+ __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
+ __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
+ RoReg8 Reserved1[0x1];
+ __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
+ __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
+ __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
+ __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
+ __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
} Wdt;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_ac.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_ac.h Fri Sep 25 12:00:11 2015 +0100 @@ -81,7 +81,7 @@ #define AC_CMP_NUM 2 // Number of comparators #define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog #define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital -#define AC_NUM_CMP 2 +#define AC_NUM_CMP 2 #define AC_PAIRS 1 // Number of pairs of comparators #endif /* _SAMR21_AC_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_gclk.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_gclk.h Fri Sep 25 12:00:11 2015 +0100 @@ -60,20 +60,20 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for GCLK peripheral ========== */ -#define GCLK_GENDIV_BITS 16 +#define GCLK_GENDIV_BITS 16 #define GCLK_GEN_NUM 9 // Number of Generic Clock Generators #define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 #define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 #define GCLK_NUM 37 // Number of Generic Clock Users -#define GCLK_SOURCE_DFLL48M 7 -#define GCLK_SOURCE_FDPLL 8 -#define GCLK_SOURCE_GCLKGEN1 2 -#define GCLK_SOURCE_GCLKIN 1 +#define GCLK_SOURCE_DFLL48M 7 +#define GCLK_SOURCE_FDPLL 8 +#define GCLK_SOURCE_GCLKGEN1 2 +#define GCLK_SOURCE_GCLKIN 1 #define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources -#define GCLK_SOURCE_OSCULP32K 3 -#define GCLK_SOURCE_OSC8M 6 -#define GCLK_SOURCE_OSC32K 4 -#define GCLK_SOURCE_XOSC 0 -#define GCLK_SOURCE_XOSC32K 5 +#define GCLK_SOURCE_OSCULP32K 3 +#define GCLK_SOURCE_OSC8M 6 +#define GCLK_SOURCE_OSC32K 4 +#define GCLK_SOURCE_XOSC 0 +#define GCLK_SOURCE_XOSC32K 5 #endif /* _SAMR21_GCLK_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_nvmctrl.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_nvmctrl.h Fri Sep 25 12:00:11 2015 +0100 @@ -74,16 +74,16 @@ #define NVMCTRL_AUX3_ADDRESS 0x0080A000 #define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register #define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF -#define NVMCTRL_FLASH_SIZE 262144 +#define NVMCTRL_FLASH_SIZE 262144 #define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 -#define NVMCTRL_PAGES 4096 -#define NVMCTRL_PAGE_HW 32 -#define NVMCTRL_PAGE_SIZE 64 -#define NVMCTRL_PAGE_W 16 -#define NVMCTRL_PMSB 3 -#define NVMCTRL_PSZ_BITS 6 -#define NVMCTRL_ROW_PAGES 4 -#define NVMCTRL_ROW_SIZE 256 +#define NVMCTRL_PAGES 4096 +#define NVMCTRL_PAGE_HW 32 +#define NVMCTRL_PAGE_SIZE 64 +#define NVMCTRL_PAGE_W 16 +#define NVMCTRL_PMSB 3 +#define NVMCTRL_PSZ_BITS 6 +#define NVMCTRL_ROW_PAGES 4 +#define NVMCTRL_ROW_SIZE 256 #define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030 #define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 #define NVMCTRL_USER_PAGE_OFFSET 0x00800000
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_pm.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_pm.h Fri Sep 25 12:00:11 2015 +0100 @@ -78,10 +78,10 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for PM peripheral ========== */ -#define PM_CTRL_MCSEL_DFLL48M 3 -#define PM_CTRL_MCSEL_GCLK 0 -#define PM_CTRL_MCSEL_OSC8M 1 -#define PM_CTRL_MCSEL_XOSC 2 -#define PM_PM_CLK_APB_NUM 2 +#define PM_CTRL_MCSEL_DFLL48M 3 +#define PM_CTRL_MCSEL_GCLK 0 +#define PM_CTRL_MCSEL_OSC8M 1 +#define PM_CTRL_MCSEL_XOSC 2 +#define PM_PM_CLK_APB_NUM 2 #endif /* _SAMR21_PM_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_rfctrl.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_rfctrl.h Fri Sep 25 12:00:11 2015 +0100 @@ -52,6 +52,6 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for RFCTRL peripheral ========== */ -#define RFCTRL_FBUSMSB 5 +#define RFCTRL_FBUSMSB 5 #endif /* _SAMR21_RFCTRL_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sbmatrix.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sbmatrix.h Fri Sep 25 12:00:11 2015 +0100 @@ -146,7 +146,7 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for SBMATRIX peripheral ========== */ -#define SBMATRIX_DEFINED +#define SBMATRIX_DEFINED /* ========== Instance parameters for SBMATRIX ========== */ #define SBMATRIX_SLAVE_FLASH 0 #define SBMATRIX_SLAVE_HPB0 1
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom0.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom0.h Fri Sep 25 12:00:11 2015 +0100 @@ -138,6 +138,6 @@ #define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger #define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core #define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM0_INT_MSB 6 +#define SERCOM0_INT_MSB 6 #endif /* _SAMR21_SERCOM0_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom1.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom1.h Fri Sep 25 12:00:11 2015 +0100 @@ -138,6 +138,6 @@ #define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger #define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core #define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM1_INT_MSB 6 +#define SERCOM1_INT_MSB 6 #endif /* _SAMR21_SERCOM1_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom2.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom2.h Fri Sep 25 12:00:11 2015 +0100 @@ -138,6 +138,6 @@ #define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger #define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core #define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM2_INT_MSB 6 +#define SERCOM2_INT_MSB 6 #endif /* _SAMR21_SERCOM2_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom3.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom3.h Fri Sep 25 12:00:11 2015 +0100 @@ -138,6 +138,6 @@ #define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger #define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core #define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM3_INT_MSB 6 +#define SERCOM3_INT_MSB 6 #endif /* _SAMR21_SERCOM3_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom4.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom4.h Fri Sep 25 12:00:11 2015 +0100 @@ -138,6 +138,6 @@ #define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger #define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core #define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM4_INT_MSB 6 +#define SERCOM4_INT_MSB 6 #endif /* _SAMR21_SERCOM4_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom5.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom5.h Fri Sep 25 12:00:11 2015 +0100 @@ -138,6 +138,6 @@ #define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger #define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core #define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM5_INT_MSB 6 +#define SERCOM5_INT_MSB 6 #endif /* _SAMR21_SERCOM5_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sysctrl.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sysctrl.h Fri Sep 25 12:00:11 2015 +0100 @@ -90,31 +90,31 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for SYSCTRL peripheral ========== */ -#define SYSCTRL_BGAP_CALIB_MSB 11 -#define SYSCTRL_BOD33_CALIB_MSB 5 -#define SYSCTRL_DFLL48M_COARSE_MSB 5 -#define SYSCTRL_DFLL48M_FINE_MSB 9 +#define SYSCTRL_BGAP_CALIB_MSB 11 +#define SYSCTRL_BOD33_CALIB_MSB 5 +#define SYSCTRL_DFLL48M_COARSE_MSB 5 +#define SYSCTRL_DFLL48M_FINE_MSB 9 #define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 #define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL #define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K -#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 -#define SYSCTRL_POR33_ENTEST_MSB 1 -#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 -#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 -#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 -#define SYSCTRL_VREF_CONTROL_MSB 48 -#define SYSCTRL_VREF_STATUS_MSB 7 -#define SYSCTRL_VREG_LEVEL_MSB 2 -#define SYSCTRL_BOD12_VERSION 0x111 -#define SYSCTRL_BOD33_VERSION 0x111 -#define SYSCTRL_DFLL48M_VERSION 0x301 -#define SYSCTRL_FDPLL_VERSION 0x111 -#define SYSCTRL_OSCULP32K_VERSION 0x111 -#define SYSCTRL_OSC8M_VERSION 0x120 -#define SYSCTRL_OSC32K_VERSION 0x1101 -#define SYSCTRL_VREF_VERSION 0x200 -#define SYSCTRL_VREG_VERSION 0x201 -#define SYSCTRL_XOSC_VERSION 0x1111 -#define SYSCTRL_XOSC32K_VERSION 0x1111 +#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 +#define SYSCTRL_POR33_ENTEST_MSB 1 +#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 +#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 +#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 +#define SYSCTRL_VREF_CONTROL_MSB 48 +#define SYSCTRL_VREF_STATUS_MSB 7 +#define SYSCTRL_VREG_LEVEL_MSB 2 +#define SYSCTRL_BOD12_VERSION 0x111 +#define SYSCTRL_BOD33_VERSION 0x111 +#define SYSCTRL_DFLL48M_VERSION 0x301 +#define SYSCTRL_FDPLL_VERSION 0x111 +#define SYSCTRL_OSCULP32K_VERSION 0x111 +#define SYSCTRL_OSC8M_VERSION 0x120 +#define SYSCTRL_OSC32K_VERSION 0x1101 +#define SYSCTRL_VREF_VERSION 0x200 +#define SYSCTRL_VREG_VERSION 0x201 +#define SYSCTRL_XOSC_VERSION 0x1111 +#define SYSCTRL_XOSC32K_VERSION 0x1111 #endif /* _SAMR21_SYSCTRL_INSTANCE_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc3.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc3.h Fri Sep 25 12:00:11 2015 +0100 @@ -103,7 +103,7 @@ #define TC3_DMAC_ID_MC_SIZE 2 #define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger #define TC3_GCLK_ID 27 // Index of Generic Clock -#define TC3_MASTER 0 +#define TC3_MASTER 0 #define TC3_OW_NUM 2 // Number of Output Waveforms #define TC3_PERIOD_EXT 0 // Period feature implemented #define TC3_SHADOW_EXT 0 // Shadow feature implemented
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc4.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc4.h Fri Sep 25 12:00:11 2015 +0100 @@ -103,7 +103,7 @@ #define TC4_DMAC_ID_MC_SIZE 2 #define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger #define TC4_GCLK_ID 28 // Index of Generic Clock -#define TC4_MASTER 1 +#define TC4_MASTER 1 #define TC4_OW_NUM 2 // Number of Output Waveforms #define TC4_PERIOD_EXT 0 // Period feature implemented #define TC4_SHADOW_EXT 0 // Shadow feature implemented
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc5.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc5.h Fri Sep 25 12:00:11 2015 +0100 @@ -103,7 +103,7 @@ #define TC5_DMAC_ID_MC_SIZE 2 #define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger #define TC5_GCLK_ID 28 // Index of Generic Clock -#define TC5_MASTER 0 +#define TC5_MASTER 0 #define TC5_OW_NUM 2 // Number of Output Waveforms #define TC5_PERIOD_EXT 0 // Period feature implemented #define TC5_SHADOW_EXT 0 // Shadow feature implemented
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc0.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc0.h Fri Sep 25 12:00:11 2015 +0100 @@ -124,7 +124,7 @@ #define TCC0_OTMX 1 // Output Matrix feature implemented #define TCC0_OW_NUM 8 // Number of Output Waveforms #define TCC0_PG 1 // Pattern Generation feature implemented -#define TCC0_SIZE 24 +#define TCC0_SIZE 24 #define TCC0_SWAP 1 // DTI outputs swap feature implemented #define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc1.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc1.h Fri Sep 25 12:00:11 2015 +0100 @@ -112,7 +112,7 @@ #define TCC1_OTMX 0 // Output Matrix feature implemented #define TCC1_OW_NUM 4 // Number of Output Waveforms #define TCC1_PG 1 // Pattern Generation feature implemented -#define TCC1_SIZE 24 +#define TCC1_SIZE 24 #define TCC1_SWAP 0 // DTI outputs swap feature implemented #define TCC1_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc2.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc2.h Fri Sep 25 12:00:11 2015 +0100 @@ -108,7 +108,7 @@ #define TCC2_OTMX 0 // Output Matrix feature implemented #define TCC2_OW_NUM 2 // Number of Output Waveforms #define TCC2_PG 0 // Pattern Generation feature implemented -#define TCC2_SIZE 16 +#define TCC2_SIZE 16 #define TCC2_SWAP 0 // DTI outputs swap feature implemented #define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21.h Fri Sep 25 12:00:11 2015 +0100 @@ -50,19 +50,19 @@ */ #if defined(__SAMR21E16A__) || defined(__ATSAMR21E16A__) - #include "samr21e16a.h" +#include "samr21e16a.h" #elif defined(__SAMR21E17A__) || defined(__ATSAMR21E17A__) - #include "samr21e17a.h" +#include "samr21e17a.h" #elif defined(__SAMR21E18A__) || defined(__ATSAMR21E18A__) - #include "samr21e18a.h" +#include "samr21e18a.h" #elif defined(__SAMR21G16A__) || defined(__ATSAMR21G16A__) - #include "samr21g16a.h" +#include "samr21g16a.h" #elif defined(__SAMR21G17A__) || defined(__ATSAMR21G17A__) - #include "samr21g17a.h" +#include "samr21g17a.h" #elif defined(__SAMR21G18A__) || defined(__ATSAMR21G18A__) - #include "samr21g18a.h" +#include "samr21g18a.h" #else - #error Library does not support the specified device. +#error Library does not support the specified device. #endif #endif /* _SAMR21_ */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMR21E16A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMR21E16A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMR21E16A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMR21E16A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMR21E16A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMR21E16A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMR21E16A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMR21E16A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMR21E16A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMR21E16A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMR21E16A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMR21E16A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMR21E16A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMR21E16A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMR21E16A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMR21E16A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMR21E16A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMR21E16A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMR21E16A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMR21E16A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMR21E16A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMR21E16A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMR21E16A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMR21E16A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMR21E16A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMR21E16A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMR21E16A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMR21E16A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMR21E16A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMR21E16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMR21E16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMR21E16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMR21E16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMR21E16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMR21E16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMR21E16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMR21E16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMR21E16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMR21E16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMR21E16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMR21E16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMR21E16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMR21E16A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMR21E16A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMR21E16A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMR21E16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMR21E16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMR21E16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMR21E16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMR21E16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMR21E16A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMR21E16A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMR21E16A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMR21E16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMR21E16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMR21E16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMR21E16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMR21E16A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMR21E17A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMR21E17A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMR21E17A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMR21E17A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMR21E17A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMR21E17A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMR21E17A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMR21E17A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMR21E17A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMR21E17A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMR21E17A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMR21E17A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMR21E17A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMR21E17A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMR21E17A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMR21E17A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMR21E17A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMR21E17A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMR21E17A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMR21E17A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMR21E17A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMR21E17A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMR21E17A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMR21E17A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMR21E17A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMR21E17A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMR21E17A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMR21E17A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMR21E17A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMR21E17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMR21E17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMR21E17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMR21E17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMR21E17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMR21E17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMR21E17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMR21E17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMR21E17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMR21E17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMR21E17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMR21E17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMR21E17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMR21E17A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMR21E17A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMR21E17A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMR21E17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMR21E17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMR21E17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMR21E17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMR21E17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMR21E17A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMR21E17A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMR21E17A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMR21E17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMR21E17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMR21E17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMR21E17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMR21E17A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMR21E18A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMR21E18A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMR21E18A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMR21E18A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMR21E18A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMR21E18A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMR21E18A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMR21E18A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMR21E18A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMR21E18A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMR21E18A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMR21E18A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMR21E18A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMR21E18A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMR21E18A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMR21E18A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMR21E18A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMR21E18A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMR21E18A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMR21E18A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMR21E18A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMR21E18A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMR21E18A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMR21E18A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMR21E18A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMR21E18A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMR21E18A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMR21E18A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMR21E18A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMR21E18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMR21E18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMR21E18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMR21E18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMR21E18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMR21E18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMR21E18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMR21E18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMR21E18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMR21E18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMR21E18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMR21E18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMR21E18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMR21E18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMR21E18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMR21E18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMR21E18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMR21E18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMR21E18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMR21E18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMR21E18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMR21E18A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMR21E18A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMR21E18A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMR21E18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMR21E18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMR21E18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMR21E18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMR21E18A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMR21G16A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMR21G16A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMR21G16A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMR21G16A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMR21G16A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMR21G16A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMR21G16A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMR21G16A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMR21G16A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMR21G16A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMR21G16A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMR21G16A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMR21G16A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMR21G16A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMR21G16A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMR21G16A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMR21G16A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMR21G16A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMR21G16A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMR21G16A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMR21G16A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMR21G16A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMR21G16A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMR21G16A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMR21G16A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMR21G16A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMR21G16A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMR21G16A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMR21G16A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMR21G16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMR21G16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMR21G16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMR21G16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMR21G16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMR21G16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMR21G16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMR21G16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMR21G16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMR21G16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMR21G16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMR21G16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMR21G16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMR21G16A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMR21G16A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMR21G16A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMR21G16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMR21G16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMR21G16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMR21G16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMR21G16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMR21G16A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMR21G16A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMR21G16A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMR21G16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMR21G16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMR21G16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMR21G16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMR21G16A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMR21G17A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMR21G17A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMR21G17A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMR21G17A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMR21G17A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMR21G17A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMR21G17A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMR21G17A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMR21G17A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMR21G17A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMR21G17A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMR21G17A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMR21G17A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMR21G17A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMR21G17A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMR21G17A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMR21G17A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMR21G17A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMR21G17A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMR21G17A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMR21G17A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMR21G17A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMR21G17A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMR21G17A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMR21G17A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMR21G17A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMR21G17A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMR21G17A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMR21G17A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMR21G17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMR21G17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMR21G17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMR21G17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMR21G17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMR21G17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMR21G17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMR21G17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMR21G17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMR21G17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMR21G17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMR21G17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMR21G17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMR21G17A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMR21G17A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMR21G17A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMR21G17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMR21G17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMR21G17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMR21G17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMR21G17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMR21G17A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMR21G17A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMR21G17A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMR21G17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMR21G17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMR21G17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMR21G17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMR21G17A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- a/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h Fri Sep 25 11:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h Fri Sep 25 12:00:11 2015 +0100
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMR21G18A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMR21G18A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMR21G18A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMR21G18A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMR21G18A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMR21G18A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMR21G18A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMR21G18A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMR21G18A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMR21G18A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMR21G18A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMR21G18A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMR21G18A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMR21G18A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMR21G18A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMR21G18A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMR21G18A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMR21G18A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMR21G18A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMR21G18A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMR21G18A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMR21G18A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMR21G18A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMR21G18A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMR21G18A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMR21G18A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMR21G18A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMR21G18A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMR21G18A Inter-IC Sound Interface (I2S) */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMR21G18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMR21G18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMR21G18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMR21G18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMR21G18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMR21G18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMR21G18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMR21G18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMR21G18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMR21G18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMR21G18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMR21G18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMR21G18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMR21G18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMR21G18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMR21G18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMR21G18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMR21G18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMR21G18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMR21G18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMR21G18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMR21G18A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMR21G18A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMR21G18A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMR21G18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMR21G18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMR21G18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMR21G18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMR21G18A Inter-IC Sound Interface (I2S) */
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S Fri Sep 25 12:00:11 2015 +0100 @@ -0,0 +1,373 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F411xExx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
+LR_IROM1 0x08000000 0x80000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_MICRO/sys.cpp Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S Fri Sep 25 12:00:11 2015 +0100 @@ -0,0 +1,346 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F411xExx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
+LR_IROM1 0x08000000 0x80000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_STD/sys.cpp Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_GCC_ARM/STM32F411XE.ld Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S Fri Sep 25 12:00:11 2015 +0100 @@ -0,0 +1,459 @@ +/** + ****************************************************************************** + * @file startup_stm32f411xe.s + * @author MCD Application Team + * @version V2.3.0 + * @date 02-March-2015 + * @brief STM32F411xExx Devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_IAR/startup_stm32f411xe.S Fri Sep 25 12:00:11 2015 +0100 @@ -0,0 +1,523 @@ +;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F411xExx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,31 @@
+/* [ROM = 512kb = 0x80000] */
+define symbol __intvec_start__ = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__ = 0x0807FFFF;
+
+/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x20000197; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x20000198;
+define symbol __region_RAM_end__ = 0x2001FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __size_cstack__ = 0x4000;
+define symbol __size_heap__ = 0x8000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/cmsis.h Fri Sep 25 12:00:11 2015 +0100 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/cmsis_nvic.c Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/cmsis_nvic.h Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F411RE
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 86 vectors = 344 bytes from 0x40 to 0x197
+// Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM
+#define NVIC_NUM_VECTORS 102
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/hal_tick.c Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,122 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.c
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#include "hal_tick.h"
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+
+void timer_irq_handler(void) {
+ // Channel 1 for mbed timeout
+ if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
+ us_ticker_irq_handler();
+ }
+
+ // Channel 2 for HAL tick
+ if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
+ __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
+ uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+ if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+ // Increment HAL variable
+ HAL_IncTick();
+ // Prepare next interrupt
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+ PreviousVal = val;
+#if 0 // For DEBUG only
+ HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
+#endif
+ }
+ }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+ // Enable timer clock
+ TIM_MST_RCC;
+
+ // Reset timer
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+
+ // Update the SystemCoreClock variable
+ SystemCoreClockUpdate();
+
+ // Configure time base
+ TimMasterHandle.Instance = TIM_MST;
+ TimMasterHandle.Init.Period = 0xFFFFFFFF;
+ TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
+ TimMasterHandle.Init.ClockDivision = 0;
+ TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ TimMasterHandle.Init.RepetitionCounter = 0;
+ HAL_TIM_OC_Init(&TimMasterHandle);
+
+ NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_IRQ);
+
+ // Channel 1 for mbed timeout
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+ // Channel 2 for HAL tick
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+ PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
+#if 0 // For DEBUG only
+ __GPIOB_CLK_ENABLE();
+ GPIO_InitTypeDef GPIO_InitStruct;
+ GPIO_InitStruct.Pin = GPIO_PIN_6;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/hal_tick.h Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,60 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.h
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __TIM5_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f411xe.h Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,4803 @@
+/**
+ ******************************************************************************
+ * @file stm32f411xe.h
+ * @author MCD Application Team
+ * @version V2.3.0
+ * @date 02-March-2015
+ * @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripherals registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f401xe
+ * @{
+ */
+
+#ifndef __STM32F401xE_H
+#define __STM32F401xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
+ uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
+ __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
+ uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+
+/**
+ * @brief __device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
+ __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
+ uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
+ __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
+ uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
+ uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
+ __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
+ uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
+ uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
+}
+USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
+#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
+#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t )0xE0042000)
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
+
+#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
+#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
+#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
+#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
+#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
+#define USB_OTG_HOST_BASE ((uint32_t )0x400)
+#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
+#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
+#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
+#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
+#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
+#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
+#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
+#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
+#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
+#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
+#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
+#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
+#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
+#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
+#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
+#define DMA_SxCR_ACK ((uint32_t)0x00100000)
+#define DMA_SxCR_CT ((uint32_t)0x00080000)
+#define DMA_SxCR_DBM ((uint32_t)0x00040000)
+#define DMA_SxCR_PL ((uint32_t)0x00030000)
+#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
+#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
+#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
+#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
+#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
+#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
+#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
+#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
+#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
+#define DMA_SxCR_MINC ((uint32_t)0x00000400)
+#define DMA_SxCR_PINC ((uint32_t)0x00000200)
+#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
+#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
+#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
+#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
+#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
+#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
+#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
+#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
+#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
+#define DMA_SxCR_EN ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT ((uint32_t)0x0000FFFF)
+#define DMA_SxNDT_0 ((uint32_t)0x00000001)
+#define DMA_SxNDT_1 ((uint32_t)0x00000002)
+#define DMA_SxNDT_2 ((uint32_t)0x00000004)
+#define DMA_SxNDT_3 ((uint32_t)0x00000008)
+#define DMA_SxNDT_4 ((uint32_t)0x00000010)
+#define DMA_SxNDT_5 ((uint32_t)0x00000020)
+#define DMA_SxNDT_6 ((uint32_t)0x00000040)
+#define DMA_SxNDT_7 ((uint32_t)0x00000080)
+#define DMA_SxNDT_8 ((uint32_t)0x00000100)
+#define DMA_SxNDT_9 ((uint32_t)0x00000200)
+#define DMA_SxNDT_10 ((uint32_t)0x00000400)
+#define DMA_SxNDT_11 ((uint32_t)0x00000800)
+#define DMA_SxNDT_12 ((uint32_t)0x00001000)
+#define DMA_SxNDT_13 ((uint32_t)0x00002000)
+#define DMA_SxNDT_14 ((uint32_t)0x00004000)
+#define DMA_SxNDT_15 ((uint32_t)0x00008000)
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
+#define DMA_SxFCR_FS ((uint32_t)0x00000038)
+#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
+#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
+#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
+#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
+#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
+#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
+#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
+#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
+#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
+#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
+#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
+#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
+#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
+#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
+#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
+#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
+#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
+#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
+#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
+#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
+#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
+#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
+#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
+#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
+#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
+#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
+#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
+#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
+#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
+#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
+#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
+#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
+#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
+#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
+#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
+#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
+#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
+#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
+#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
+#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
+#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
+#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
+#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
+#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
+#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
+#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
+#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
+#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
+#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
+#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
+#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
+#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
+#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
+#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
+#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
+#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
+#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
+#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
+#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
+#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
+#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
+#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
+#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
+#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
+#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
+#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
+#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
+#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
+#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
+#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
+#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
+#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
+#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
+#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
+#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
+#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
+#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
+#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
+#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
+#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
+#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
+#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
+#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
+#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
+#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
+#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
+#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
+#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
+#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
+#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
+#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
+
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
+#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
+#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
+#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
+#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
+#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP ((uint32_t)0x00000001)
+#define FLASH_SR_SOP ((uint32_t)0x00000002)
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
+#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
+#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
+#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
+#define FLASH_SR_BSY ((uint32_t)0x00010000)
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001)
+#define FLASH_CR_SER ((uint32_t)0x00000002)
+#define FLASH_CR_MER ((uint32_t)0x00000004)
+#define FLASH_CR_SNB ((uint32_t)0x000000F8)
+#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
+#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
+#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
+#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
+#define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
+#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
+#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
+#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
+#define FLASH_CR_STRT ((uint32_t)0x00010000)
+#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
+#define FLASH_CR_LOCK ((uint32_t)0x80000000)
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
+#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
+#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
+#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
+#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
+
+#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
+#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
+#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
+#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
+#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
+#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
+#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
+#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
+#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
+#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
+#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
+#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
+#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
+#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
+#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
+#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
+#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
+#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
+#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
+#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
+#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
+#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
+#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
+#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
+#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
+#define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
+#define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
+#define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
+#define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
+#define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
+#define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
+#define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
+#define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
+#define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
+#define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
+#define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
+#define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
+#define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
+#define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
+#define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
+
+#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define PWR_CR_FMSSR ((uint32_t)0x00100000) /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR ((uint32_t)0x00200000) /*!< Flash Interface Stop while System Run */
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
+#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
+#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+#define RCC_CR_CSSON ((uint32_t)0x00080000)
+#define RCC_CR_PLLON ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
+#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
+#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
+#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
+#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
+#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
+#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
+#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
+
+#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
+#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
+#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
+#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
+#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
+#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
+#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
+#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
+#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
+#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
+#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
+#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
+
+#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
+#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
+
+#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
+#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
+#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
+#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
+#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
+#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
+#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
+#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
+#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
+#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
+#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
+#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
+
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
+
+#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
+#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
+#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
+#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
+
+#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
+#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
+#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
+#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
+
+#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
+#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
+#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
+#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
+
+#define RCC_CIR_CSSF ((uint32_t)0x00000080)
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
+#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
+
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
+#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
+
+#define RCC_CIR_CSSC ((uint32_t)0x00800000)
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
+#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
+#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
+#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
+#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
+#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
+#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
+#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
+#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
+#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
+#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
+#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
+#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
+#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
+#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
+#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
+#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
+#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
+#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
+#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
+#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
+#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
+#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
+#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
+#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
+#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
+#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
+#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
+#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
+#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
+#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
+#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
+#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
+#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
+#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
+#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
+#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
+#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
+#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
+#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
+#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
+#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
+#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
+#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
+#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
+#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
+#define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001)
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
+#define RCC_CSR_RMVF ((uint32_t)0x01000000)
+#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
+#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
+#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
+#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
+#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
+#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F)
+#define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)
+#define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)
+#define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)
+#define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)
+#define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)
+#define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020)
+
+#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
+#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
+#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
+#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
+#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
+#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
+#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
+#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
+#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
+#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
+
+#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
+#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_DCE ((uint32_t)0x00000080)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
+#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
+
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
+#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
+
+#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
+#define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
+#define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
+#define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
+#define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
+#define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
+#define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
+#define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
+#define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
+#define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
+#define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
+#define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
+#define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
+#define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
+#define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
+#define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
+
+#define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
+
+#define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
+#define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
+
+#define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
+#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
+
+#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
+#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
+#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
+#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+
+#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
+#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
+#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F411xE_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f4xx.h Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,232 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @version V2.3.0
+ * @date 02-March-2015
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripherals drivers in application code(i.e.
+ * code will be based on direct access to peripherals registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ #define STM32F411xE /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V2.3.0
+ */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_DEVICE_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f4xx_hal_conf.h Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,405 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 26-December-2014
+ * @brief HAL configuration file
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+/* #define HAL_SDRAM_MODULE_ENABLED */
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)32000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 1
+#define INSTRUCTION_CACHE_ENABLE 1
+#define DATA_CACHE_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2
+#define MAC_ADDR1 0
+#define MAC_ADDR2 0
+#define MAC_ADDR3 0
+#define MAC_ADDR4 0
+#define MAC_ADDR5 0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.c Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,711 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.c
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 19-June-2014
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f4xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 16 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 96 | 96
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 96 | 96
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * APB2CLK (MHz) | 96 | 96
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | YES
+ *-----------------------------------------------------------------------------
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Includes
+ * @{
+ */
+
+
+#include "stm32f4xx.h"
+#include "hal_tick.h"
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
+ on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* #define DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
+ #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+ * @{
+ */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+uint32_t SystemCoreClock = 16000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+ /* Configure the Cube driver */
+ SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
+ HAL_Init();
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+
+ /* Reset the timer to avoid issues after the RAM initialization */
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+ * depends on the application requirements), user has to ensure that HSE_VALUE
+ * is same as the real frequency of the crystal used. Otherwise, this function
+ * may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+ SYSCLK = PLL_VCO / PLL_P
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+
+ if (pllsource != 0)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+ SystemCoreClock = pllvco/pllp;
+ break;
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK frequency --------------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK frequency */
+ SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f4xx.s before jump to main.
+ * This function configures the external memories (SRAM/SDRAM)
+ * This SRAM/SDRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined (DATA_IN_ExtSDRAM)
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register uint32_t index;
+
+ /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
+ clock */
+ RCC->AHB1ENR |= 0x000001F8;
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x000000CC;
+ GPIOD->AFR[1] = 0xCC000CCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xA02A000A;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOD->OSPEEDR = 0xA02A000A;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00000CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA800A;
+ /* Configure PEx pins speed to 50 MHz */
+ GPIOE->OSPEEDR = 0xAAAA800A;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0xCCCCCCCC;
+ GPIOF->AFR[1] = 0xCCCCCCCC;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA800AAA;
+ /* Configure PFx pins speed to 50 MHz */
+ GPIOF->OSPEEDR = 0xAA800AAA;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0xCCCCCCCC;
+ GPIOG->AFR[1] = 0xCCCCCCCC;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xAAAAAAAA;
+ /* Configure PGx pins speed to 50 MHz */
+ GPIOG->OSPEEDR = 0xAAAAAAAA;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0x00C0CC00;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAA08A0;
+ /* Configure PHx pins speed to 50 MHz */
+ GPIOH->OSPEEDR = 0xAAAA08A0;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PHx pins */
+ GPIOH->PUPDR = 0x00000000;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0x0028AAAA;
+ /* Configure PIx pins speed to 50 MHz */
+ GPIOI->OSPEEDR = 0x0028AAAA;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PIx pins */
+ GPIOI->PUPDR = 0x00000000;
+
+/*-- FMC Configuration ------------------------------------------------------*/
+ /* Enable the FMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+
+ /* Configure and enable SDRAM bank1 */
+ FMC_Bank5_6->SDCR[0] = 0x000019E0;
+ FMC_Bank5_6->SDTR[0] = 0x01115351;
+
+ /* SDRAM initialization sequence */
+ /* Clock enable command */
+ FMC_Bank5_6->SDCMR = 0x00000011;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index = 0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6->SDCMR = 0x00000012;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Auto refresh command */
+ FMC_Bank5_6->SDCMR = 0x00000073;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* MRD register program */
+ FMC_Bank5_6->SDCMR = 0x00046014;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6->SDRTR;
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6->SDCR[0];
+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+#endif /* DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(DATA_IN_ExtSRAM)
+/*-- GPIOs Configuration -----------------------------------------------------*/
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+ RCC->AHB1ENR |= 0x00000078;
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x00CCC0CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAA0A8A;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0FCF;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00CC0CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA828A;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC3CF;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCC0000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA000AAA;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xFF000FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0x000000C0;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0x00085AAA;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0x000CAFFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+/*-- FMC/FSMC Configuration --------------------------------------------------*/
+ /* Enable the FMC/FSMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001011;
+ FMC_Bank1->BTCR[3] = 0x00000201;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+ /* Configure and enable Bank1_SRAM2 */
+ FSMC_Bank1->BTCR[2] = 0x00001011;
+ FSMC_Bank1->BTCR[3] = 0x00000201;
+ FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+}
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+ #if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+ #endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+ {
+ while(1)
+ {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSE oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0)
+ {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ }
+ else
+ {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
+ //RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
+ //RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
+
+ RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 2 MHz (8 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (2 MHz * 192)
+
+
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+
+ //if (bypass == 0)
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
+ //else
+ // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.h Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @version V2.3.0
+ * @date 02-March-2015
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/PortNames.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/PortNames.h Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PeripheralNames.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PeripheralNames.h Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PeripheralPins.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PeripheralPins.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PeripheralPins.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PeripheralPins.h Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PinNames.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PinNames.h Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/analogout_api.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/analogout_api.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/device.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/device.h Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PeripheralNames.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PeripheralNames.h Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PeripheralPins.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PeripheralPins.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PeripheralPins.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PeripheralPins.h Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PinNames.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PinNames.h Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/device.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/device.h Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/analogin_api.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/analogin_api.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/dma_api.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/dma_api.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/dma_api_HAL.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/dma_api_HAL.h Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/gpio_api.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/gpio_api.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/gpio_irq_api.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/gpio_irq_api.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/gpio_object.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/gpio_object.h Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/i2c_api.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/i2c_api.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/objects.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/objects.h Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pinmap.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pinmap.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pinmap_function.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pinmap_function.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pinmap_function.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pinmap_function.h Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/port_api.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/port_api.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pwmout_api.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pwmout_api.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/rtc_api.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/rtc_api.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/sercom_dma.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/sercom_dma.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/sercom_dma.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/sercom_dma.h Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/serial_api.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/serial_api.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/sleep_api.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/sleep_api.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/spi_api.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/spi_api.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- a/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/us_ticker.c Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/us_ticker.c Fri Sep 25 12:00:11 2015 +0100 @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralNames.h Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+#define STDIO_UART_TX PA_9
+#define STDIO_UART_RX PA_10
+#define STDIO_UART UART_1
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE, ELMO_RF_SPI2 = SPI_1,
+ SPI_2 = (int)SPI2_BASE, ELMO_SPI1 = SPI_2,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE,
+ SPI_5 = (int)SPI5_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralPins.c Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,205 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+// {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Warning: also on SCL
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO
+// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+ {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO
+// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO
+ {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Warning: also on NSS
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)},
+ {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Warning: also on SCLK
+// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Warning: also on SCLK
+ {NC, NC, 0}
+};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PinNames.h Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,196 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
+#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
+#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
+#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
+#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
+#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F)
+#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+#define STM_MODE_INPUT (0)
+#define STM_MODE_OUTPUT_PP (1)
+#define STM_MODE_OUTPUT_OD (2)
+#define STM_MODE_AF_PP (3)
+#define STM_MODE_AF_OD (4)
+#define STM_MODE_ANALOG (5)
+#define STM_MODE_IT_RISING (6)
+#define STM_MODE_IT_FALLING (7)
+#define STM_MODE_IT_RISING_FALLING (8)
+#define STM_MODE_EVT_RISING (9)
+#define STM_MODE_EVT_FALLING (10)
+#define STM_MODE_EVT_RISING_FALLING (11)
+#define STM_MODE_IT_EVT_RESET (12)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X) ((uint32_t)(X) & 0xF)
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = 0x32,
+
+ PH_0 = 0x70,
+ PH_1 = 0x71,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+
+ // Arduino connector namings
+ A0 = PC_0,
+ A1 = PC_1,
+ A2 = PC_2,
+ A3 = PC_3,
+ A4 = NC,
+ A5 = NC,
+ D0 = PA_3,
+ D1 = PA_2,
+ D2 = PA_1,
+ D3 = PA_0,
+ D4 = NC,
+ D5 = NC,
+ D6 = NC,
+ D7 = NC,
+ D8 = NC,
+ D9 = NC,
+ D10 = PB_12,
+ D11 = PB_15,
+ D12 = PB_14,
+ D13 = PB_13,
+ D14 = PC_9,
+ D15 = PA_8,
+
+ // Generic signals namings
+ LED1 = PB_0,
+ LED2 = PB_1,
+ LED3 = PB_0,
+ LED4 = PB_1,
+ USER_BUTTON = PB_7,
+ SERIAL_TX = PA_9,
+ SERIAL_RX = PA_10,
+ USBTX = PA_9,
+ USBRX = PA_10,
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+ SPI_MOSI = D11,
+ SPI_MISO = D12,
+ SPI_SCK = D13,
+ SPI_CS = D10,
+ RF_SPI_MOSI = PA_7,
+ RF_SPI_MISO = PA_6,
+ RF_SPI_SCK = PA_5,
+ RF_SPI_CS = PA_4,
+ RF_RESET = PC_4,
+ RF_DIO0 = PC_10,
+ RF_DIO1 = PC_11,
+ RF_DIO2 = PC_12,
+ RF_DIO3 = PD_2,
+ RF_DIO4 = PB_5,
+ RF_DIO5 = PB_6,
+ RF_RXTX_SW = PC_13
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullUp = 1,
+ PullDown = 2,
+ OpenDrain = 3,
+ PullDefault = PullNone
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PortNames.h Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2,
+ PortD = 3,
+ PortE = 4,
+ PortH = 7
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/device.h Fri Sep 25 12:00:11 2015 +0100 @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 // Not present on this device + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/objects.h Fri Sep 25 12:00:11 2015 +0100
@@ -0,0 +1,108 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct analogin_s {
+ ADCName adc;
+ PinName pin;
+ uint8_t channel;
+};
+
+struct serial_s {
+ UARTName uart;
+ int index; // Used by irq
+ uint32_t baudrate;
+ uint32_t databits;
+ uint32_t stopbits;
+ uint32_t parity;
+ PinName pin_tx;
+ PinName pin_rx;
+};
+
+struct spi_s {
+ SPIName spi;
+ uint32_t bits;
+ uint32_t cpol;
+ uint32_t cpha;
+ uint32_t mode;
+ uint32_t nss;
+ uint32_t br_presc;
+ PinName pin_miso;
+ PinName pin_mosi;
+ PinName pin_sclk;
+ PinName pin_ssel;
+};
+
+struct i2c_s {
+ I2CName i2c;
+ uint32_t slave;
+};
+
+struct pwmout_s {
+ PWMName pwm;
+ PinName pin;
+ uint32_t period;
+ uint32_t pulse;
+ uint8_t channel;
+ uint8_t inverted;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/device.h Fri Sep 25 11:45:09 2015 +0100 +++ b/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/device.h Fri Sep 25 12:00:11 2015 +0100 @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without