lpc17xx_i2s.h

00001 /***********************************************************************//**
00002  * @file        lpc17xx_i2s.h
00003  * @brief        Contains all macro definitions and function prototypes
00004  *                 support for I2S firmware library on LPC17xx
00005  * @version        3.0
00006  * @date        18. June. 2010
00007  * @author        NXP MCU SW Application Team
00008  **************************************************************************
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * products. This software is supplied "AS IS" without any warranties.
00012  * NXP Semiconductors assumes no responsibility or liability for the
00013  * use of the software, conveys no license or title under any patent,
00014  * copyright, or mask work right to the product. NXP Semiconductors
00015  * reserves the right to make changes in the software without
00016  * notification. NXP Semiconductors also make no representation or
00017  * warranty that such application will be suitable for the specified
00018  * use without further testing or modification.
00019  **************************************************************************/
00020 
00021 /* Peripheral group ----------------------------------------------------------- */
00022 /** @defgroup I2S I2S
00023  * @ingroup LPC1700CMSIS_FwLib_Drivers
00024  * @{
00025  */
00026 
00027 #ifndef LPC17XX_I2S_H_
00028 #define LPC17XX_I2S_H_
00029 
00030 /* Includes ------------------------------------------------------------------- */
00031 #include "LPC17xx.h"
00032 #include "lpc_types.h"
00033 
00034 
00035 #ifdef __cplusplus
00036 extern "C"
00037 {
00038 #endif
00039 
00040 /* Public Macros -------------------------------------------------------------- */
00041 /** @defgroup I2S_Public_Macros I2S Public Macros
00042  * @{
00043  */
00044 
00045 /*********************************************************************//**
00046  * I2S configuration parameter defines
00047  **********************************************************************/
00048 /** I2S Wordwidth bit */
00049 #define I2S_WORDWIDTH_8        ((uint32_t)(0))
00050 #define I2S_WORDWIDTH_16    ((uint32_t)(1))
00051 #define I2S_WORDWIDTH_32    ((uint32_t)(3))
00052 /** I2S Channel bit */
00053 #define I2S_STEREO            ((uint32_t)(0))
00054 #define I2S_MONO            ((uint32_t)(1))
00055 /** I2S Master/Slave mode bit */
00056 #define I2S_MASTER_MODE        ((uint8_t)(0))
00057 #define I2S_SLAVE_MODE        ((uint8_t)(1))
00058 /** I2S Stop bit */
00059 #define I2S_STOP_ENABLE        ((uint8_t)(1))
00060 #define I2S_STOP_DISABLE    ((uint8_t)(0))
00061 /** I2S Reset bit */
00062 #define I2S_RESET_ENABLE    ((uint8_t)(1))
00063 #define I2S_RESET_DISABLE    ((uint8_t)(0))
00064 /** I2S Mute bit */
00065 #define I2S_MUTE_ENABLE        ((uint8_t)(1))
00066 #define I2S_MUTE_DISABLE    ((uint8_t)(0))
00067 /** I2S Transmit/Receive bit */
00068 #define I2S_TX_MODE            ((uint8_t)(0))
00069 #define I2S_RX_MODE            ((uint8_t)(1))
00070 /** I2S Clock Select bit */
00071 #define I2S_CLKSEL_FRDCLK    ((uint8_t)(0))
00072 #define I2S_CLKSEL_MCLK        ((uint8_t)(2))
00073 /** I2S 4-pin Mode bit */
00074 #define I2S_4PIN_ENABLE     ((uint8_t)(1))
00075 #define I2S_4PIN_DISABLE     ((uint8_t)(0))
00076 /** I2S MCLK Enable bit */
00077 #define I2S_MCLK_ENABLE        ((uint8_t)(1))
00078 #define I2S_MCLK_DISABLE    ((uint8_t)(0))
00079 /** I2S select DMA bit */
00080 #define I2S_DMA_1            ((uint8_t)(0))
00081 #define I2S_DMA_2            ((uint8_t)(1))
00082 
00083 /**
00084  * @}
00085  */
00086 
00087 /* Private Macros ------------------------------------------------------------- */
00088 /** @defgroup I2S_Private_Macros I2S Private Macros
00089  * @{
00090  */
00091 
00092 /*********************************************************************//**
00093  * Macro defines for DAO-Digital Audio Output register
00094  **********************************************************************/
00095 /** I2S wordwide - the number of bytes in data*/
00096 #define I2S_DAO_WORDWIDTH_8        ((uint32_t)(0))        /** 8 bit    */
00097 #define I2S_DAO_WORDWIDTH_16    ((uint32_t)(1))        /** 16 bit    */
00098 #define I2S_DAO_WORDWIDTH_32    ((uint32_t)(3))        /** 32 bit    */
00099 /** I2S control mono or stereo format */
00100 #define I2S_DAO_MONO            ((uint32_t)(1<<2))
00101 /** I2S control stop mode */
00102 #define I2S_DAO_STOP            ((uint32_t)(1<<3))
00103 /** I2S control reset mode */
00104 #define I2S_DAO_RESET            ((uint32_t)(1<<4))
00105 /** I2S control master/slave mode */
00106 #define I2S_DAO_SLAVE            ((uint32_t)(1<<5))
00107 /** I2S word select half period minus one */
00108 #define I2S_DAO_WS_HALFPERIOD(n)    ((uint32_t)(n<<6))
00109 /** I2S control mute mode */
00110 #define I2S_DAO_MUTE            ((uint32_t)(1<<15))
00111 
00112 /*********************************************************************//**
00113  * Macro defines for DAI-Digital Audio Input register
00114 **********************************************************************/
00115 /** I2S wordwide - the number of bytes in data*/
00116 #define I2S_DAI_WORDWIDTH_8        ((uint32_t)(0))        /** 8 bit    */
00117 #define I2S_DAI_WORDWIDTH_16    ((uint32_t)(1))        /** 16 bit    */
00118 #define I2S_DAI_WORDWIDTH_32    ((uint32_t)(3))        /** 32 bit    */
00119 /** I2S control mono or stereo format */
00120 #define I2S_DAI_MONO            ((uint32_t)(1<<2))
00121 /** I2S control stop mode */
00122 #define I2S_DAI_STOP            ((uint32_t)(1<<3))
00123 /** I2S control reset mode */
00124 #define I2S_DAI_RESET            ((uint32_t)(1<<4))
00125 /** I2S control master/slave mode */
00126 #define I2S_DAI_SLAVE            ((uint32_t)(1<<5))
00127 /** I2S word select half period minus one (9 bits)*/
00128 #define I2S_DAI_WS_HALFPERIOD(n)    ((uint32_t)((n&0x1FF)<<6))
00129 /** I2S control mute mode */
00130 #define I2S_DAI_MUTE            ((uint32_t)(1<<15))
00131 
00132 /*********************************************************************//**
00133  * Macro defines for STAT register (Status Feedback register)
00134 **********************************************************************/
00135 /** I2S Status Receive or Transmit Interrupt */
00136 #define I2S_STATE_IRQ        ((uint32_t)(1))
00137 /** I2S Status Receive or Transmit DMA1 */
00138 #define I2S_STATE_DMA1        ((uint32_t)(1<<1))
00139 /** I2S Status Receive or Transmit DMA2 */
00140 #define I2S_STATE_DMA2        ((uint32_t)(1<<2))
00141 /** I2S Status Current level of the Receive FIFO (5 bits)*/
00142 #define I2S_STATE_RX_LEVEL(n)    ((uint32_t)((n&1F)<<8))
00143 /** I2S Status Current level of the Transmit FIFO (5 bits)*/
00144 #define I2S_STATE_TX_LEVEL(n)    ((uint32_t)((n&1F)<<16))
00145 
00146 /*********************************************************************//**
00147  * Macro defines for DMA1 register (DMA1 Configuration register)
00148 **********************************************************************/
00149 /** I2S control DMA1 for I2S receive */
00150 #define I2S_DMA1_RX_ENABLE        ((uint32_t)(1))
00151 /** I2S control DMA1 for I2S transmit */
00152 #define I2S_DMA1_TX_ENABLE        ((uint32_t)(1<<1))
00153 /** I2S set FIFO level that trigger a receive DMA request on DMA1 */
00154 #define I2S_DMA1_RX_DEPTH(n)    ((uint32_t)((n&0x1F)<<8))
00155 /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
00156 #define I2S_DMA1_TX_DEPTH(n)    ((uint32_t)((n&0x1F)<<16))
00157 
00158 /*********************************************************************//**
00159  * Macro defines for DMA2 register (DMA2 Configuration register)
00160 **********************************************************************/
00161 /** I2S control DMA2 for I2S receive */
00162 #define I2S_DMA2_RX_ENABLE        ((uint32_t)(1))
00163 /** I2S control DMA1 for I2S transmit */
00164 #define I2S_DMA2_TX_ENABLE        ((uint32_t)(1<<1))
00165 /** I2S set FIFO level that trigger a receive DMA request on DMA1 */
00166 #define I2S_DMA2_RX_DEPTH(n)    ((uint32_t)((n&0x1F)<<8))
00167 /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
00168 #define I2S_DMA2_TX_DEPTH(n)    ((uint32_t)((n&0x1F)<<16))
00169 
00170 /*********************************************************************//**
00171 * Macro defines for IRQ register (Interrupt Request Control register)
00172 **********************************************************************/
00173 /** I2S control I2S receive interrupt */
00174 #define I2S_IRQ_RX_ENABLE        ((uint32_t)(1))
00175 /** I2S control I2S transmit interrupt */
00176 #define I2S_IRQ_TX_ENABLE        ((uint32_t)(1<<1))
00177 /** I2S set the FIFO level on which to create an irq request */
00178 #define I2S_IRQ_RX_DEPTH(n)        ((uint32_t)((n&0x1F)<<8))
00179 /** I2S set the FIFO level on which to create an irq request */
00180 #define I2S_IRQ_TX_DEPTH(n)        ((uint32_t)((n&0x1F)<<16))
00181 
00182 /********************************************************************************//**
00183  * Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
00184 *********************************************************************************/
00185 /** I2S Transmit MCLK rate denominator */
00186 #define I2S_TXRATE_Y_DIVIDER(n)    ((uint32_t)(n&0xFF))
00187 /** I2S Transmit MCLK rate denominator */
00188 #define I2S_TXRATE_X_DIVIDER(n)    ((uint32_t)((n&0xFF)<<8))
00189 /** I2S Receive MCLK rate denominator */
00190 #define I2S_RXRATE_Y_DIVIDER(n)    ((uint32_t)(n&0xFF))
00191 /** I2S Receive MCLK rate denominator */
00192 #define I2S_RXRATE_X_DIVIDER(n)    ((uint32_t)((n&0xFF)<<8))
00193 
00194 /*************************************************************************************//**
00195  * Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
00196 **************************************************************************************/
00197 #define I2S_TXBITRATE(n)    ((uint32_t)(n&0x3F))
00198 #define I2S_RXBITRATE(n)    ((uint32_t)(n&0x3F))
00199 
00200 /**********************************************************************************//**
00201  * Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
00202 ************************************************************************************/
00203 /** I2S Transmit select clock source (2 bits)*/
00204 #define I2S_TXMODE_CLKSEL(n)    ((uint32_t)(n&0x03))
00205 /** I2S Transmit control 4-pin mode */
00206 #define I2S_TXMODE_4PIN_ENABLE    ((uint32_t)(1<<2))
00207 /** I2S Transmit control the TX_MCLK output */
00208 #define I2S_TXMODE_MCENA        ((uint32_t)(1<<3))
00209 /** I2S Receive select clock source */
00210 #define I2S_RXMODE_CLKSEL(n)    ((uint32_t)(n&0x03))
00211 /** I2S Receive control 4-pin mode */
00212 #define I2S_RXMODE_4PIN_ENABLE    ((uint32_t)(1<<2))
00213 /** I2S Receive control the TX_MCLK output */
00214 #define I2S_RXMODE_MCENA        ((uint32_t)(1<<3))
00215 
00216 
00217 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
00218 /** Macro to determine if it is valid I2S peripheral */
00219 #define PARAM_I2Sx(n)    (((uint32_t *)n)==((uint32_t *)LPC_I2S))
00220 /** Macro to check Data to send valid */
00221 #define PRAM_I2S_FREQ(freq)        ((freq>=16000)&&(freq <= 96000))
00222 /* Macro check I2S word width type */
00223 #define PARAM_I2S_WORDWIDTH(n)    ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\
00224 ||(n==I2S_WORDWIDTH_32))
00225 /* Macro check I2S channel type */
00226 #define PARAM_I2S_CHANNEL(n)    ((n==I2S_STEREO)||(n==I2S_MONO))
00227 /* Macro check I2S master/slave mode */
00228 #define PARAM_I2S_WS_SEL(n)        ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE))
00229 /* Macro check I2S stop mode */
00230 #define PARAM_I2S_STOP(n)    ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE))
00231 /* Macro check I2S reset mode */
00232 #define PARAM_I2S_RESET(n)    ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE))
00233 /* Macro check I2S reset mode */
00234 #define PARAM_I2S_MUTE(n)    ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE))
00235 /* Macro check I2S transmit/receive mode */
00236 #define PARAM_I2S_TRX(n)         ((n==I2S_TX_MODE)||(n==I2S_RX_MODE))
00237 /* Macro check I2S clock select mode */
00238 #define PARAM_I2S_CLKSEL(n)        ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK))
00239 /* Macro check I2S 4-pin mode */
00240 #define PARAM_I2S_4PIN(n)    ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE))
00241 /* Macro check I2S MCLK mode */
00242 #define PARAM_I2S_MCLK(n)    ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE))
00243 /* Macro check I2S DMA mode */
00244 #define PARAM_I2S_DMA(n)        ((n==I2S_DMA_1)||(n==I2S_DMA_2))
00245 /* Macro check I2S DMA depth value */
00246 #define PARAM_I2S_DMA_DEPTH(n)    ((n>=0)||(n<=31))
00247 /* Macro check I2S irq level value */
00248 #define PARAM_I2S_IRQ_LEVEL(n)    ((n>=0)||(n<=31))
00249 /* Macro check I2S half-period value */
00250 #define PARAM_I2S_HALFPERIOD(n)    ((n>0)&&(n<512))
00251 /* Macro check I2S bit-rate value */
00252 #define PARAM_I2S_BITRATE(n)    ((n>=0)&&(n<=63))
00253 /**
00254  * @}
00255  */
00256 
00257 
00258 
00259 /* Public Types --------------------------------------------------------------- */
00260 /** @defgroup I2S_Public_Types I2S Public Types
00261  * @{
00262  */
00263 
00264 /**
00265  * @brief I2S configuration structure definition
00266  */
00267 typedef struct {
00268     uint8_t wordwidth;        /** the number of bytes in data as follow:
00269                             -I2S_WORDWIDTH_8: 8 bit data
00270                             -I2S_WORDWIDTH_16: 16 bit data
00271                             -I2S_WORDWIDTH_32: 32 bit data */
00272     uint8_t    mono;             /** Set mono/stereo mode, should be:
00273                             - I2S_STEREO: stereo mode
00274                             - I2S_MONO: mono mode */
00275     uint8_t stop;            /** Disables accesses on FIFOs, should be:
00276                             - I2S_STOP_ENABLE: enable stop mode
00277                             - I2S_STOP_DISABLE: disable stop mode */
00278     uint8_t reset;            /** Asynchronously reset tje transmit channel and FIFO, should be:
00279                             - I2S_RESET_ENABLE: enable reset mode
00280                             - I2S_RESET_DISABLE: disable reset mode */
00281     uint8_t ws_sel;            /** Set Master/Slave mode, should be:
00282                             - I2S_MASTER_MODE: I2S master mode
00283                             - I2S_SLAVE_MODE: I2S slave mode */
00284     uint8_t mute;            /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
00285                             - I2S_MUTE_ENABLE: enable mute mode
00286                             - I2S_MUTE_DISABLE: disable mute mode */
00287     uint8_t Reserved0[2];
00288 } I2S_CFG_Type;
00289 
00290 /**
00291  * @brief I2S DMA configuration structure definition
00292  */
00293 typedef struct {
00294     uint8_t DMAIndex;        /** Select DMA1 or DMA2, should be:
00295                             - I2S_DMA_1: DMA1
00296                             - I2S_DMA_2: DMA2 */
00297     uint8_t depth;            /** FIFO level that triggers a DMA request */
00298     uint8_t Reserved0[2];
00299 }I2S_DMAConf_Type;
00300 
00301 /**
00302  * @brief I2S mode configuration structure definition
00303  */
00304 typedef struct{
00305     uint8_t clksel;            /** Clock source selection, should be:
00306                             - I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output
00307                             - I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */
00308     uint8_t fpin;            /** Select four pin mode, should be:
00309                             - I2S_4PIN_ENABLE: 4-pin enable
00310                             - I2S_4PIN_DISABLE: 4-pin disable */
00311     uint8_t mcena;            /** Select MCLK mode, should be:
00312                             - I2S_MCLK_ENABLE: MCLK enable for output
00313                             - I2S_MCLK_DISABLE: MCLK disable for output */
00314     uint8_t Reserved;
00315 }I2S_MODEConf_Type;
00316 
00317 
00318 /**
00319  * @}
00320  */
00321 
00322 
00323 /* Public Functions ----------------------------------------------------------- */
00324 /** @defgroup I2S_Public_Functions I2S Public Functions
00325  * @{
00326  */
00327 /* I2S Init/DeInit functions ---------*/
00328 void I2S_Init(LPC_I2S_TypeDef *I2Sx);
00329 void I2S_DeInit(LPC_I2S_TypeDef *I2Sx);
00330 
00331 /* I2S configuration functions --------*/
00332 void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);
00333 Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode);
00334 void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode);
00335 void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);
00336 uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
00337 
00338 /* I2S operate functions -------------*/
00339 void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData);
00340 uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx);
00341 void I2S_Start(LPC_I2S_TypeDef *I2Sx);
00342 void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
00343 void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
00344 void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
00345 
00346 /* I2S DMA functions ----------------*/
00347 void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);
00348 void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
00349 
00350 /* I2S IRQ functions ----------------*/
00351 void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState);
00352 void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level);
00353 FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
00354 uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
00355 
00356 /**
00357  * @}
00358  */
00359 
00360 
00361 #ifdef __cplusplus
00362 }
00363 #endif
00364 
00365 
00366 #endif /* LPC17XX_SSP_H_ */
00367 
00368 /**
00369  * @}
00370  */
00371 
00372 /* --------------------------------- End Of File ------------------------------ */