Revision 176:2d0c9ad7ef62, committed 2014-04-29

Comitter:

mbed_official

Date:

Tue Apr 29 17:15:06 2014 +0100

Parent:

175:906e2386ace8

Child:

177:d57c40a064c8

Commit message:

Synchronized with git revision 522752bd5859a27060ff825458b84be3c3490190

Full URL: https://github.com/mbedmicro/mbed/commit/522752bd5859a27060ff825458b84be3c3490190/

Changed in this revision

--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/device.h	Tue Apr 29 17:00:07 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/device.h	Tue Apr 29 17:15:06 2014 +0100
@@ -42,10 +42,10 @@
 #define DEVICE_SERIAL           1
 
 #define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         0
+#define DEVICE_I2CSLAVE         1
 
 #define DEVICE_SPI              1
-#define DEVICE_SPISLAVE         0
+#define DEVICE_SPISLAVE         1
 
 #define DEVICE_RTC              1
 

--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/i2c_api.c	Tue Apr 29 17:00:07 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/i2c_api.c	Tue Apr 29 17:15:06 2014 +0100
@@ -69,6 +69,7 @@
     // Enable I2C clock
     if (obj->i2c == I2C_1) {    
         RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
+        RCC_I2CCLKConfig(RCC_I2C1CLK_SYSCLK);
     }
     if (obj->i2c == I2C_2) {
         RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);
@@ -103,7 +104,7 @@
        * Fast Mode (up to 400 kHz)
        * Fast Mode Plus (up to 1 MHz)
        Below values obtained with:
-       - I2C clock source = 8 MHz (HSI clock per default)
+       - I2C clock source = 48 MHz (System Clock)
        - Analog filter delay = ON
        - Digital filter coefficient = 0
        - Rise time = 100 ns
@@ -111,16 +112,16 @@
     */
     switch (hz) {
       case 100000:
-          tim = 0x00201D2B; // Standard mode
+          tim = 0x10805E89; // Standard mode
           break;
       case 200000:
-          tim = 0x0010021E; // Fast Mode
+          tim = 0x00905E82; // Fast Mode
           break;
       case 400000:
-          tim = 0x0010020A; // Fast Mode
+          tim = 0x00901850; // Fast Mode
           break;
       case 1000000:
-          tim = 0x00100001; // Fast Mode Plus
+          tim = 0x00700818; // Fast Mode Plus
           // Enable the Fast Mode Plus capability
           if (obj->i2c == I2C_1) {
               SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C1, ENABLE);
@@ -299,25 +300,19 @@
 
 int i2c_slave_receive(i2c_t *obj) {
     I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-    int event = 0;
-    int timeout;
+    int event = NoData;
   
-    // Wait until address match
-    timeout = FLAG_TIMEOUT;
-    while (I2C_GetFlagStatus(i2c, I2C_ISR_ADDR) == RESET) {
-        timeout--;
-        if (timeout == 0) {
-            return 0;
-        }
-    }
+    if(I2C_GetFlagStatus(i2c, I2C_ISR_BUSY) == SET) {
+        if(I2C_GetFlagStatus(i2c, I2C_ISR_ADDR) == SET) {
         // Check direction
-        if (i2c->ISR & I2C_ISR_DIR) {
+            if (I2C_GetFlagStatus(i2c, I2C_ISR_DIR) == SET) {
             event = ReadAddressed;
         }
         else event = WriteAddressed;
         // Clear adress match flag to generate an acknowledge
         i2c->ICR |= I2C_ICR_ADDRCF;
-
+        }
+    }
     return event;
 }