Jolyon Hill
Changes to support running on smaller memory LPC device LPC1764
Fork of
mbed-dev
by 
mbed official
Revision 113:b3775bf36a83, committed 2016-04-19
- Comitter:
- mbed_official
- Date:
- Tue Apr 19 11:15:15 2016 +0100
- Parent:
- 112:df58eca2f41d
- Child:
- 114:fe4fe5cfc3a3
- Commit message:
- Synchronized with git revision 896981126b34b6d9441e3eea77881c67a1ae3dbd
Full URL: https://github.com/mbedmicro/mbed/commit/896981126b34b6d9441e3eea77881c67a1ae3dbd/
Exporter tool addition for e2 studio
Changed in this revision
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/Release_Notes_stm32l0xx_hal.html Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/Release_Notes_stm32l0xx_hal.html Tue Apr 19 11:15:15 2016 +0100
@@ -1,7 +1,6 @@
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<h1 style="margin-bottom: 0.25in; text-align: center;" align="center"><span style="font-size: 20pt; font-family: "Verdana","sans-serif"; color: rgb(51, 102, 255);">Release
Notes for STM32L0xx HAL Drivers</span><span style="font-size: 20pt; font-family: "Verdana","sans-serif";"><o:p></o:p></span></h1>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;">Copyright
-2015 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+2016 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;"><img style="border: 0px solid ; width: 112px; height: 83px;" alt="" id="_x0000_i1026" src="../../_htmresc/st_logo.png"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
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@@ -677,409 +676,660 @@
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<td style="padding: 0in;" valign="top">
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0
-/ 06-February-2015</span></h3><div style="margin-left: 40px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></div><ul><li><small><span style="font-weight: bold; font-family: Verdana;">HAL has been updated to support the STM32L071xx STM32L072xx STM32L073xx STM32L082xx STM32L083xx series</span></small></li><li><small><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL Flash</span> update <br></span></small></li><ul><li><small><span style="font-family: Verdana;">Flash : 192K Dual Bank </span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL TIM</span> update : </span></small></li><ul><li><small><span style="font-family: Verdana;">Four new instances : </span></small><small><span style="font-family: Verdana;">TIM3, TIM7, TIM21, TIM22</span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL USART</span> update :</span></small></li><ul><li><small><span style="font-family: Verdana;">Two new instances : USART 4, USART 5</span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL I2C</span> update :</span></small></li><ul><li><small><span style="font-family: Verdana;">One new instance I2C3</span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL GPIO</span> update :</span></small></li><ul><li><small><span style="font-family: Verdana;">GPIO Port E</span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL DAC</span> update :</span></small></li><ul><li><small><span style="font-family: Verdana;">A second channel has been introduced</span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL FIREWALL</span> introduction<br></span></small></li><li><small><span style="font-family: Verdana;">All other <span style="font-weight: bold;">HAL IPs</span> have also been updated in the context of the overall HAL alignment effort of all the STM32 family</span></small></li><li><small><span style="font-family: Verdana;">More than 120 corrections have been implemented since the previous V1.1.0 delivery<br></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-weight: bold;">Known limitations</span> :</span></small></li><ul style="font-family: Verdana;"><li><small>Introduced
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
+<br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.0/ 8-January-2016</span></h3>
+<br>
+<div style="margin-left: 40px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></div>
+
+<ul><li><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt;" improvements="" of="" the="" hal=""></span><span><span style="font-weight: bold; font-family: Verdana;"> </span></span></span><span style="font-family: Verdana;"><span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></span></span></span></span><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">U</span></span><span style="font-weight: bold; font-family: Verdana;"><span><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">pdates of the HAL : </span></span></span></span><span style="font-weight: bold; font-family: Verdana;"><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><br></span></span></span><span style="font-weight: bold; font-family: Verdana;"><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><br>
+</span><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">- Compliancy with MISRA coding rules (MISRA C 2004 rule 10.5 except for hal_pcd.c file and MISRA C 2004 rule 5.3)</span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">. <br>- Several functions inside the HAL have been updated in order to prevent unused argument compilation warnings.<br>- The startup timeout value for many clocks (as HSE, HSI, LSI, MSI, PLL) have been updated </span></span></span></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">to
+reach a more accurate value (alignement to the Datasheet).</span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><br>-
+The macro __HAL_CORTEX_SYSTICKCLK_CONFIG(..) has been removed
+since this service is already covered by the function
+HAL_SYSTICK_CLKSourceConfig().<br>- Several updates on dedicated HAL as specified in the list below :</span></span></span></span><span style="font-weight: bold; font-family: Verdana;"><span><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><br></span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><br></span></span></span></span><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;">List of HAL updates or corrections provided by this release:</span></u></b><br><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="text-decoration: underline;"><br></span></span></span></span></span></li><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL</span> </small></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small>update</small></span></span></span></li><ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"></span></span></span><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Update
+the SYSCFG_BOOT_SYSTEMFLASH definition. (SYSCFG_BOOT_SYSTEMFLASH is now
+equal to SYSCFG_CFGR1_BOOT_MODE_0 instead of
+SYSCFG_CFGR1_MEM_MODE_0) </span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">The HSE_STARTUP_TIMEOUT is now equal to 100 instead of 5000.<br></span></span></span></small></li></ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL I2C</span> update</small></span></span></span></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Update the HAL_I2C_Slave_Receive function. Store last data received when requested.</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Improvement of the HAL_I2C_MasterReceive function. Error management update. (HAL_ERROR detection versus HAL_TIMEOUT)<br></span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Improvement
+of the I2C_MasterTransmit_ISR function. Adding of several
+error checks, unlock of the process when requested.</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Improvement
+of the I2C_MasterReceive_DMA function. Adding of several
+error checks and abort DMA when requested.</span></span></span></small></li></ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL UART</span> update</small></span></span></span></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Update the check of parameters inside the function HAL_LIN_SendBreak().</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Correction
+of an error present on the V1.4.0 release. On the V1.4.0 release, the
+clock used inside the function USART_SetConfig(..) was never set.<br></span></span></span></small></li></ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL DMA</span> update</small></span></span></span></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Update the DMA_handler structure in order to be MISRA-C 2004 rule 5.3 compliant.<br></span></span></span></small></li></ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL SPI</span> update</small></span></span></span></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Update the SPI_handler structure in order to be MISRA-C 2004 rule 5.3 compliant.</span></span></span></small></li></ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL RCC</span> update</small></span></span></span></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Update support of RCC_MC03 when requested.</span></span></span></small></li>
+ <li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Update support of dynamic HSE prescaler configuration for LCD/RTC peripherals.</span></span></span></small></li>
+ <li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Some updates inside the HAL_RCC_ClockConfig function.</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Some
+updates inside the HAL_RCC_MCOConfig function. The enabling of the MCO
+clocks (__MC01_CLK_ENABLE() or __MCO2_CLK_ENABLE()) is done separately
+depending on the MCO selected.</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">The function HAL_RCCEx_GetPeriphCLKFreq() has been reworked.</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">The
+function HAL_RCCEx_PeriphCLKConfig() has been updated. A new error is
+now detected when trying to update the HSE divider dynamically.<br></span></span></span></small></li>
+</ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL TSC</span> update</small></span></span></span></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Several updates inside the HAL_TSC_Start function and HAL_TSC_Init function. Check of input parameters</span></span></span></small></li></ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL ADC</span> update</small></span></span></span></li><ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small>The channel 16 (ADC_CHANNEL_16) is not available on all devices.</small></span></span></span></li></ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL CORTEX</span></small></span></span></span></li><ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small>The
+macro __HAL_CORTEX_SYSTICKCLK_CONFIG(..) has been removed since this
+service is already covered by the function
+HAL_SYSTICK_CLKSourceConfig().<span style="font-weight: bold;"><br></span></small></span></span></span></li></ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL FLASH</span> update</small></span></span></span></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"></span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"></span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">The
+restriction which was present on V1.4.0 and linked to the OPTVERR
+bit usage on STM32L031xx and STM32L041xx has been removed. This is due
+to the fact that the </span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">new STM32L031xx/</span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">STM32L041xx</span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"> </span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">devices supports now this feature. On the first revision of the </span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">STM32L031xx/</span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">STM32L031xx </span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">devices (RevID = 0x1000 retrieved via HAL_GetREVID()), the </span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">OPTVERR
+bit was not functional. The OPTVERR (Option valid error bit) is set by
+hardware when, during an Option byte loading, there was a mismatch for
+one or more configurations.</span></span></span></small></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.0/ 16-October-2015</span></h3>
+<br>
+<div style="margin-left: 40px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></div>
+
+<ul><li><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt;" improvements="" of="" the="" hal=""></span><span><span style="font-weight: bold; font-family: Verdana;"> </span></span></span><span style="font-family: Verdana;"><span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></span></span></span></span><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Support
+of </span><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32L011xx and </span></span></span><span style="font-weight: bold; font-family: Verdana;"><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32L021xx
+series<br></span></span></span><span style="font-weight: bold; font-family: Verdana;"><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><br>
+</span><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">
+On STM32L011xx/</span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32L021xx</span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">, compared to </span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32L07xxx</span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">/</span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32L08xxx</span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">, some of the main differences are listed hereafter<span style="font-family: Verdana;"></span> :<br>
+- SRAM size set to 2KB (instead of 20KB)<br>
+- Flash size set to 16KB (instead of 192KB)<br>
+- GPIO available :A,B,C (instead of A,B,C,D,E,H)<br>
+- Timers available : TIM2,TIM21,LPTIM1 (instead of
+TIM2,TIM3,TIM6,TIM7,TIM21,TIM22,LPTIM1)<br><br></span></span></span></span></li><li><span style="font-weight: bold; font-family: Verdana;"><span><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Minor updates of the HAL : <br></span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><br></span></span></span></span><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;">List of HAL updates or corrections provided by this release:</span></u></b><br><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="text-decoration: underline;"><br></span></span></span></span></span></li><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL COMP</span> update</small></span></span></span></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Update of the non inverting inputs available on the whole L0 family. </span></span></span></small></li></ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL RCC</span> </small></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small>update</small></span></span></span></li><ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"></span></span></span><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Usage of a common PLLMulTable[] defined in system_stm32l0xx.c.</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Update in the definition of the different tampers.</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Minor renaming of several macros.</span></span></span></small></li></ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL TIMER</span> update</small></span></span></span></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Handle lock initialization in all TIM init functions.</span></span></span></small></li></ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL LCD</span> update</small></span></span></span></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Add support of new MuxSegment field inside the init structure.</span></span></span></small></li></ul><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL DMA</span> update</small></span></span></span></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Alignment of the different channels within the L0 family.</span></span></span></small></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.0/ 09-September-2015</span></h3><br>
+<div style="margin-left: 40px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></div>
+<ul>
+<li><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt;" improvements="" of="" the="" hal=""></span><span><span style="font-weight: bold; font-family: Verdana;"> <span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Major update of the
+HAL API : <br>
+</span><span style="font-weight: bold; font-family: Verdana;"><br>
+</span></span></span></span><span style="font-family: Verdana;"><span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">
+-
+all <span style="font-weight: bold;">MACROs</span> and <span style="font-weight: bold;">LITERALs</span> values have been reworked to align all STM32 Families as much as possible<br>
+- <span style="font-weight: bold;">Important information</span>
+: A stm32_hal_legacy.h file has been added to the FW package in order to support
+the old MACROs and LITERAL values used in the previous versions of
+customer applications. (this file is automatically included, from HAL/Inc/Legacy)<br>
+- In <span style="font-weight: bold;">HAL MACROs</span> definitions : do { } while(0) have been used in multi statement macros
+</span></span></span></span></span></li>
+</ul>
+<ul>
+<li><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">
+Support
+of </span><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32L031xx and </span></span></span><span style="font-weight: bold; font-family: Verdana;"><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32L041xx
+series<br></span></span></span><span style="font-weight: bold; font-family: Verdana;"><span style="font-weight: bold; font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><br>
+</span><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">
+On STM32L031xx/</span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32L041xx</span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">, compared to </span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32L07xxx</span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">/</span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32L08xxx</span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">, the main differences are as <span style="font-family: Verdana;">follow</span> :<br>
+- SRAM size set to 8KB (instead of 20KB)<br>
+- Flash size set to 32KB (instead of 192KB)<br>
+- GPIO available :A,B,C,H (instead of A,B,C,D,E,H)<br>
+- Timers available : TIM2,TIM21,TIM22,LPTIM1 (instead of
+TIM2,TIM3,TIM6,TIM7,TIM21,TIM22,LPTIM1)<br><br></span></span></span></span><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">List of HAL updates or corrections provided by this release:</span></u></b><br><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="text-decoration: underline;"><br></span><br></span></span></span></span></li><li><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><small><span style="font-weight: bold;">HAL ADC</span> update</small></span></span></span></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">ADC assert param needs to be more specific for discontinuous mode, nb of discont conversions</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"></span></span></span><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">ADC external trigger definition is not complete Flag EOS should not be reset in HAL_ADC_GetValue()</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">ADC poll for event must return timeout instead of error</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">ADC state machine update - States with bitfields are now used for a more accurate status </span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">ADC run in LPrun mode needs SYSCFG buffers enabled</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">ADC_CLOCK_SYNC_PCLK_DIVx was not correct</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Remove WaitLoopIndex at the beginning of the function HAL_ADC_Enable</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">ADC parameter "ADC_SOFTWARE_START" for compatibility with other STM32 devices</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">ADC poll for conversion must return error status in case of ADC-DMA mode</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">ADC identical error code returned generates confusion</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Issue observed with ADC start simultaneous commands</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">The HAl_Delay() is not required when ADVREGEN is set</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">[STM32L07xxx/</span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">STM32L08xxx</span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">] ADC Interface modification : ADC_Init structure update</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">[</span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">STM32L07xxx/</span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">STM32L08xxx</span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"></span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">] ADC Interface modification LowPowerAutoOff is now LowPowerAutoPowerOff</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">ADC_Enable does not support the LowPowerAutoOff function</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL COMP</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">COMP_TRIGGERMODE_NONE missing in stm32l0xx_hal_comp.h</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">COMP wrong implementation of the macro : IS_COMP_WINDOWMODE_INSTANCE</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Misplaced user callback at HAL_COMP_IRQHandler</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">EXTI Usage model update - add MACROs __HAL_COMP_COMPx_EXTI_GENERATE_SWIT()</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">HAL COMP update in HAL_COMP_Lock() to handle state change and prevent C++ compilation error</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Add the LPTIM Comparator connection</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL Cortex</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">[MISRA] bitwise operators ~ and << (MISRA C 2004 rule 10.5)</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Cortex The function HAL_NVIC_GetPriority(IRQn_Type IRQn) was missing</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Cortex HAL_NVIC_DisableIRQ()/HAL_NVIC_EnableIRQ() Add a check on negative parameter values</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL CRC</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">__HAL_CRC_SET_IDR macro improvement</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">CRC wrong definition of __HAL_CRC_SET_IDR macro</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Uncorrect CRC functions naming, portability failing, out of topic comments</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Useless Assignment in stm32l0xx_hal_crc.c detected by CodeSonar</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL DAC</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Missing define for DAC Trigger (010: Timer 3 CH3 event)</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Complete DAC update as per HAL_API_Reference</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">DAC HAL_DAC_Stop_DMA() code clean up</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">HAL_DAC_ConfigChannel: use "hdac->Instance->XXX" instead of "DAC->XXX"</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">No
+reset of previous bits WAVEx / MAMPx before setting values in
+HAL_DACEx_NoiseWaveGenerate & HAL_DACEx_TriangleWaveGenerate</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL DMA</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">The description of __HAL_DMA_GET_IT_SOURCE() was incorrect</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL FLASH</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">FLASH Missing macro __HAL_FLASH_GET_LATENCY</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">FLASH_WaitForLastOperation issue</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">FLASH_Program_IT unlock() issue</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">FLASH Crash during HAL_FLASHEx_HalfPageProgram and HAL_FLASHEx_ProgramParallelHalfPage</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">FLASH Ramfunc error management</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">FLASH IS_OPTIONBYTE(VALUE) is not correct if all options are selected</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">HAL_FLASH Otpion Byte "BootConfig" and "BOOTBit1Config"</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">FLASH SPRMOD option bit is impacted by FLASH_OB_RDPConfig()</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">__HAL_FLASH_GET_FLAG was not functional</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL GPIO</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">GPIO The Clear of the External Interrupt is not properly done</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">GPIO GPIO_SPEED LITERALS renaming</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">GPIO_AF for LPTIM is no more compatible with HAL L0 V1.1</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">GPIO AF2 defines for RTC should be aligned for all L0 devices</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">GPIO AF defines for LPTIM1 should be the same for all devices.</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">GPIO Bug at EXTi register GPIO config in HAL_GPIO_Init() function</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">GPIO GPIO_AF5_I2S3ext Update the defined name to be more generic </span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">GPIO Protect init from impossible AF configuration</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">GPIO interrupt mode is not reset</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">GPIO Check of the Pin availability according to the GPIO in use</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">GPIO rework GPIO_GET_SOURCE</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">[</span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">STM32L07xxx/</span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">STM32L08xxx</span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">] GPIO updates (HAL driver and associated validation test prg)</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">The GET_GPIO_SOURCE() macro is wrongly implemented</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">GPIO alternate functions defined in stm32l0xx_hal_gpio_ex.h not aligned with the spec</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">GPIO private Macro __HAL_GET_GPIO_SOURCE must be renamed GET_GPIO_SOURCE</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL I2C</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">New SYSCFG Define MACROs to manage FM+ on GPIOs</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">NACK is not treated during wait on flag treatment</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL I2S</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">I2S HAL_I2S_Transmit() API update to keep the check on busy flag only for the slave</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">I2S busy flag issue </span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">I2S Management of the bit ASTREN for the I2S various modes</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL LCD</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">LCD HD field initialization of LCD_FCR register is missing in HAL_LCD_init() function</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL LPUART</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">HAL _DIV_LPUART macro possible value saturation </span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">LPUART CR3 register bit 11 must be kept at reset value.</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL PWR</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Cortex SCR SLEEPONEXIT and SEVONPEND bits management</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">PWR PVD feature need falling/rising Event modes</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">PWR REGLPF and VOSF polling request</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL RCC</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RCC Bug in HAL_RCC_GetSysClockFreq</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Missing RCC IRQ handler for LSE CSS interrupt</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Missing external macro __HAL_RCC_MCO_CONFIG</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RCC Enable automatically backup domain</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">In HAL_RCCEx_PeriphCLKConfig, Reset backup domain only if RTC clock source has been changed</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RCC update LSE_CONFIG to remove transaction LSE On to LSE Bypass</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Issue on MSI setting</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Rework __HAL_RCC_LSE_CONFIG macro to manage correctly LSE_Bypass</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Rename HSI48_TIMEOUT_VALUE into RCC_HSI_TIMEOUT_VALUE</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Add defines for RCC_System_Clock_Source_Status</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">New HAL RCC macro to configure the SYSCLK clock source</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Wrong calculation of sysclk in case of PLL clocked by HSI_Div4</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RCC_CRSStatusTypeDef must be typed uint32_t</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RCC Implement workaround to cover RCC limitation regarding Peripheral enable delay</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RCC issue in HAL_RCC_OscConfig when RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RCC Check if need to add interface HAL_RCCEx_GetPeriphCLKFreq</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RCC Add a comment in the How to use section to mention the Peripheral enable delay</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RCC Some values in MSIRangeTable are wrong</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RCC missing macros to easily Enable/Disable HSI48(RC) clock for RNG analog config</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RCC HSERDY must be checked even in HSE_BYPASS mode</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RCC Improve HAL_RCC_OscCOnfig() function</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL RNG</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RNG Type inconsistency of value returned by HAL_RNG_GetRandomNumber() and HAL_RNG_GetRandomNumber_IT() functions.</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RNG Process lock and array of random numbers generation in interrupt mode</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RNG Incorrect DRDY flag resetting</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RNG Incorrect interrupt mode random number generation</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RNG Incorrect TimeOut handling in polling mode random number generation</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL RTC</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RTC macro __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG erroneous definition</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RTC alignment of different HAL_RTC_XXIRQHandler() implementations </span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RTC Bits Mask literals to be used in macro definition </span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RTC macro __HAL_RTC_TAMPER_GET_IT() issue in param: __INTERRUPT__ @arg list</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RTC wrong description of the subsecond item of RTC_TimeTypeDef structure in the header file</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">RTC WUTWF is not reliable</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">HAL_RTC_GetTime function does not return the actual subfraction</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">[</span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">STM32L031xx/</span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">STM32L041xx</span></span></span></small><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">] RTC macros renaming for RTC_OUTPUT_REMAP_XX and RTC_TIMESTAMPPIN_XX</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Enhance @note describing the use of HAL RTC APIs </span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL SPI</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">SPI HAL_SPI_TransmitReceive_DMA() Remove DMA Tx Callback in case of RxOnly mode </span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">SPI HandleTypeDef.ErrorCode must be typed uint32_t</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Warnings with True Studio IDE (tempreg variable not used)</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL TIM</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">TIM problem to use ETR as OCrefClear source</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">TIM Wrong remaping of the TIM2_ETR</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">TIM register BDTR does not exist</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">The assert on trigger polarity for TI1F_ED should be removed</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">TIM Add macros to ENABLE/DISABLE URS bit in TIM CR1 register</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">TIM HAL_TIM_OC_ConfigChannel() / HAL_TIM_PWM_ConfigChannel() Missed/Unused assert param to be added/removed</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">TIM Remove HAL_TIM_SlaveConfigSynchronization_DMA() from HAL_TIM API</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">TIM Trigger DMA request should be activated when working with a slave mode</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">TIM Timer Register Corruption using HAL_TIM_IC_ConfigChannel</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">TIM DMA transfer should be aborted when stopping a DMA burst</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Add "TIM_CHANNEL_ALL" as an argument for all Encoder Start/Stop process in the comment section</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">HAL_TIM_DMADelayPulseCplt callback missing information</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">HAL_TIM_DMACaptureCplt callback missing information</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">TIM Trigger DMA request should be activated when working with a slave mode</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">TIM Trigger interrupt should be activated when working with a slave mode</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">__HAL_TIM_PRESCALER() shall be corrected: use '=' instead of '|='</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL UART/USART</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">UART Incorrect UART speed setting on HSI clock</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Wrong Baud Rate calculation in case of OVER8</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">UART missing closing bracket in header file</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">UART Circular mode when transmitting data not well supported</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">UART/LPUART number of stop bits to correct</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">USART Incorrect number of stop bits definition</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">UART HAL_UART_IRQHandler function not clearing correctly the interrupt flags</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">USART Setting of BRR register bit3:0 not inline with RM when OVER8 sampling mode is used</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">UART UART_WaitOnFlagUntilTimeout should not assign UART handle state to HAL_UART_STATE_TIMEOUT</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">USART Wrong values used as parameter of __HAL_USART_CLEAR_IT() in HAL_USART_IRQHandler()</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">USART BRR setting is wrong compared to Baudrate value</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">USART HAL_USART_Init() update to reach max frequencies (enable oversampling by 8)</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">USART USART_DMAReceiveCplt() Update to set the USART state after performing the test on it</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">UART The code associated to several macros need to be completed</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">USART UART DMA implementation issue: missed clear the TC bit in the SR</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Wrong USART_IT_CM defined value</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Issue with Lin mode data length</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Wrong description for Interrupt mode IO operation within HAL UART driver</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Change UART_DMATransmitCplt- new implementation to remove WaitOnFlag in ISR</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Change UART TX-IT implementation to remove WaitOnFlag in ISR</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">The IS_UART_OVERSAMPLING(SAMPLING) is not called in UART_SetConfig()</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">HAL UART enhancement: remove the check on RXNE flag after reading the DR register</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">UART/USART/IRDA/SMARTCARD transmit process enhancement to use TXE instead of TC</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Add MACRO to UART HAL to control CTS and RTS from the customer application</span></span></span></small></li></ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-weight: bold;">HAL PCD</span> update</span></span></span></small></li><ul><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">HAL_PCD_EP_Transmit() not functional</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">HAL PCD clear flag macros configuration</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">Bad IN/OUT EndPoint parameter array size</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">HAL PCD miss #define for ep0_mps parameter</span></span></span></small></li><li><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;">USB HAL PCD missing #define PCD_SPEED_HIGH<br></span></span></span></small></li></ul></ul><small><span style="font-family: Verdana;"><span style="font-family: Verdana;"><span style="font-family: Verdana;"></span></span></span></small><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0
+/ 06-Feb-2015</span></h3>
+<div style="margin-left: 40px;"><big><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></big></div>
+<ul>
+<li><span style="font-weight: bold; font-family: Verdana; font-size: 10pt;">HAL
+has
+been updated to support the STM32L071xx STM32L072xx
+STM32L073xx STM32L082xx STM32L083xx series</span></li>
+<li><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL Flash</span> update <br>
+</span></li>
+<ul>
+<li><span style="font-family: Verdana; font-size: 10pt;">Flash
+: 192K Dual Bank </span></li>
+</ul>
+<li><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM</span> update
+: </span></li>
+<ul>
+<li><span style="font-family: Verdana; font-size: 10pt;">Four
+new instances : </span><small><span style="font-family: Verdana;">TIM3, TIM7, TIM21, TIM22</span></small></li>
+</ul>
+<li><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL USART</span> update :</span></li>
+<ul>
+<li><span style="font-family: Verdana; font-size: 10pt;">Two
+new instances : USART 4, USART 5</span></li>
+</ul>
+<li><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL I2C</span> update :</span></li>
+<ul>
+<li><span style="font-family: Verdana; font-size: 10pt;">One
+new instance I2C3</span></li>
+</ul>
+<li><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL GPIO</span> update :</span></li>
+<ul>
+<li><span style="font-family: Verdana; font-size: 10pt;">GPIO
+Port E</span></li>
+</ul>
+<li><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL DAC</span> update :</span></li>
+<ul>
+<li><span style="font-family: Verdana; font-size: 10pt;">A
+second channel has been introduced</span></li>
+</ul>
+<li><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">HAL FIREWALL</span>
+introduction<br>
+</span></li>
+<li><span style="font-family: Verdana; font-size: 10pt;">All
+other <span style="font-weight: bold;">HAL IPs</span>
+have also been updated in the context of the overall HAL alignment
+effort of all the STM32 family</span></li>
+<li><span style="font-family: Verdana; font-size: 10pt;">More
+than 120 corrections have been implemented since the previous V1.1.0
+delivery<br>
+</span></li>
+<li><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">Known limitations</span> :</span></li>
+<ul style="font-family: Verdana; font-size: 10pt;">
+<li>Introduced
a FW patch to deactivate the HW SPI-V2.3 correction in case of I2S PCM
Short mode usage (Please refer to the STM32L073xx Errata Sheet for more
details). In this use case, we come back to the HW SPI 2.2 behavior
-which is correct for the I2S PCM short mode</small></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0
-/ 18-June-2014</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+which is correct for the I2S PCM short mode</li>
+</ul>
+</ul>
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0
+/ 18-June-2014</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p>
-<ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
-
-
-
-
-
-
-
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL generic</span> update<br></span></p>
+<ul style="margin-top: 0cm; list-style-type: square;">
+<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL generic</span> update<br>
+</span></small></p>
</li>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix flag clear procedure: use atomic write operation </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">"=" </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">instead of ready-modify-write operation "|=" or "&="</span></li>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix
+flag clear procedure: use atomic write operation </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">"="
+</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">instead
+of ready-modify-write operation "|=" or "&="</span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix
on Timeout management, Timeout value set to 0 passed to API
automatically exits the function after checking the flag without any
wait</span><br>
- <span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Common update for</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> the following communication peripherals: SPI, UART, USART and IRDA</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> </span></li>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add DMA circular mode support<br>
- </span></li>
- </ul>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove lock from recursive process</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><br>
- </span></li>
- </ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
-new macro __HAL_RESET_HANDLE_STATE to reset a given handle state</span></li>
- </ul>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">When USE_RTOS == 1 (in stm32l0xx_hal_conf.h), the __HAL_LOCK() is not defined instead of being defined empty</span></li>
- <li><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;">Use __IO const instead of
-__I, to avoid any compilation issue when __cplusplus switch is defined</span></li>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new functions for the DBGMCU module</span></li>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_EnableDBGSleepMode()</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_DisableDBGSleepMode()</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_EnableDBGStopMode()</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_DisableDBGStopMode()</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_EnableDBGStandbyMode()</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_DisableDBGStandbyMode()</span></li>
- </ul>
- <li><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;">Miscellaneous comments update</span></li>
- </ul>
- <li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
-
-<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL FLASH </span>update <o:p></o:p></span></p>
-
-
-
-
-
-<ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
-new functions: <span style="font-style: italic;">HAL_FLASHEx_OB_SelectPCROP()</span> and <span style="font-style: italic;">HAL_FLASHEx_OB_DeSelectPCROP()</span><o:p></o:p></span></li>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Some functions was renamed and moved to the extension files (stm32l0xx_hal_flash_ex.h/.c)<br>
- </span></li>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename
- <span style="font-style: italic;">FLASH_HalfPageProgram()</span> into <span style="font-style: italic;">HAL_FLASHEx_HalfPageProgram()</span><o:p></o:p></span></li>
- </ul>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename
- <span style="font-style: italic;">FLASH_EnableRunPowerDown()</span> into <span style="font-style: italic;">HAL_FLASHEx_EnableRunPowerDown()</span><o:p></o:p></span></li>
- </ul>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename
- <span style="font-style: italic;">FLASH_DisableRunPowerDown()</span> into <span style="font-style: italic;">HAL_FLASHEx_DisableRunPowerDown()</span><o:p></o:p></span></li>
- </ul>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename
-all<span style="font-style: italic;"> HAL_DATA_EEPROMEx_xxx()</span> functions into <span style="font-style: italic;">HAL_FLASHEx_DATAEEPROM_xxx()</span></span></li>
- </ul>
- <ul>
- <li><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;">Note: aliases has been added to keep compatibility with previous version</span></li>
- </ul>
-</ul><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;"><br>
- </span></li>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">GPIO </span>update<o:p></o:p><br></span></li>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove
- <span style="font-style: italic;">IS_GET_GPIO_PIN</span> macro<o:p></o:p></span></li>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
-a new function <span style="font-style: italic;">HAL_GPIO_LockPin()</span></span></li>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Private Macro <span style="font-style: italic;">__HAL_GET_GPIO_SOURCE</span> renamed into <span style="font-style: italic;">GET_GPIO_SOURCE <br>
- </span></span></li>
- </ul>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL DMA</span> update<br></span></p>
- </li>
- <ul>
-<li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix in <span style="font-style: italic;">HAL_DMA_PollForTransfer()</span> to set error code <span style="font-style: italic;">HAL_DMA_ERROR_TE </span>in case of <span style="font-style: italic;">HAL_ERROR</span> status</span></li>
- </ul>
-</ul><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><br>
- </span>
- <ul style="margin-top: 0cm; list-style-type: square;">
- <li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL PWR</span> update<span style="font-weight: bold;"><br>
- </span></span></li>
- <ul>
- <li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">HAL_PWR_PVDConfig()</span>: add clear of the EXTI trigger before new configuration <br>
- </span></li>
- <li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix in <span style="font-style: italic;">HAL_PWR_EnterSTANDBYMode()</span> to not clear Wakeup flag (WUF), which need to be cleared at application level before to call this function<br>
- </span></li>
- </ul>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RCC</span> update<br></span></p>
- </li>
- <ul>
-<li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Allow to calibrate the HSI when it is used as system clock source<br>
-</span></li>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix implementation of <span style="font-style: italic;">IS_RCC_OSCILLATORTYPE()</span> macro<br>
-</span></li>
- </ul>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL ADC</span> update<br></span></p>
- </li>
- <ul>
-<li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update ADC internal channels mapping: TEMPSENSOR connected to ADC_CHANNEL_18 and VLCD mapped to ADC_CHANNEL_16 <br>
-</span></li>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Skip polling for ADRDY flag when Low Power Auto Off mode is enabled<br>
-</span></li>
- </ul>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL COMP</span> update<br></span></p>
-<ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
- <span style="font-style: italic;">LPTIMConnection</span> field in the <span style="font-style: italic;">COMP_InitTypeDef</span> structure.<o:p></o:p></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
-new defines: <span style="font-style: italic;">COMP_LPTIMCONNECTION_DISABLED</span>, <span style="font-style: italic;">COMP_LPTIMCONNECTION_ENABLED</span><o:p></o:p></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
-new macro IS_COMP_LPTIMCONNECTION<o:p></o:p></span></li></ul></li>
-<li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL LPTIM </span>update<br></span></p>
-
+<span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Common
+update for</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">
+the following communication peripherals: SPI, UART, USART and IRDA</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">
+</span></small></li>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+DMA circular mode support<br>
+</span></small></li>
+</ul>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove
+lock from recursive process</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><br>
+</span></small></li>
+</ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+new macro __HAL_RESET_HANDLE_STATE to reset a given handle state</span></small></li>
+</ul>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">When
+USE_RTOS == 1 (in stm32l0xx_hal_conf.h), the __HAL_LOCK() is not
+defined instead of being defined empty</span></small></li>
+<li><small><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;">Use
+__IO const instead of
+__I, to avoid any compilation issue when __cplusplus switch is defined</span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+new functions for the DBGMCU module</span></small></li>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_EnableDBGSleepMode()</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_DisableDBGSleepMode()</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_EnableDBGStopMode()</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_DisableDBGStopMode()</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_EnableDBGStandbyMode()</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_DisableDBGStandbyMode()</span></small></li>
+</ul>
+<li><small><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;">Miscellaneous
+comments update</span></small></li>
+</ul>
+<li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL FLASH </span>update <o:p></o:p></span></small></p>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+new functions: <span style="font-style: italic;">HAL_FLASHEx_OB_SelectPCROP()</span>
+and <span style="font-style: italic;">HAL_FLASHEx_OB_DeSelectPCROP()</span><o:p></o:p></span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Some
+functions was renamed and moved to the extension files
+(stm32l0xx_hal_flash_ex.h/.c)<br>
+</span></small></li>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename
+<span style="font-style: italic;">FLASH_HalfPageProgram()</span>
+into <span style="font-style: italic;">HAL_FLASHEx_HalfPageProgram()</span><o:p></o:p></span></small></li>
+</ul>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename
+<span style="font-style: italic;">FLASH_EnableRunPowerDown()</span>
+into <span style="font-style: italic;">HAL_FLASHEx_EnableRunPowerDown()</span><o:p></o:p></span></small></li>
+</ul>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename
+<span style="font-style: italic;">FLASH_DisableRunPowerDown()</span>
+into <span style="font-style: italic;">HAL_FLASHEx_DisableRunPowerDown()</span><o:p></o:p></span></small></li>
+</ul>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename
+all<span style="font-style: italic;">
+HAL_DATA_EEPROMEx_xxx()</span> functions into <span style="font-style: italic;">HAL_FLASHEx_DATAEEPROM_xxx()</span></span></small></li>
+</ul>
+<ul>
+<li><small><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;">Note:
+aliases has been added to keep compatibility with previous version</span></small></li>
+</ul>
+</ul>
+<small><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;"><br>
+</span></small></li>
+<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">GPIO </span>update<o:p></o:p><br>
+</span></small></li>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove
+<span style="font-style: italic;">IS_GET_GPIO_PIN</span>
+macro<o:p></o:p></span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+a new function <span style="font-style: italic;">HAL_GPIO_LockPin()</span></span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Private
+Macro <span style="font-style: italic;">__HAL_GET_GPIO_SOURCE</span>
+renamed into <span style="font-style: italic;">GET_GPIO_SOURCE
+<br>
+</span></span></small></li>
+</ul>
+<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL DMA</span> update<br>
+</span></small></p>
</li>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
- <span style="font-style: italic;">CKPOL </span>configuration for encoder mod<span style="font-style: italic;">e</span></span></li>
- </ul>
- <li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">WWDG </span>update<br></span></p>
-
- </li>
- <ul>
-<li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Miscellaneous minor update on the source code <span style="font-style: italic;"></span><span style="font-style: italic;"></span></span></li>
- </ul>
- <li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">IWDG </span>update<br></span></p>
-
- </li>
- <ul>
-<li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Miscellaneous minor update on the source code</span></li>
- </ul>
- <li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">CRC </span>update<br></span></p>
-<ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Some functions was renamed and moved to the extension files (stm32l0xx_hal_crc_ex.h/.c)</span></li>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-style: italic;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">HAL_CRC_Input_Data_Reverse()</span> renamed into <span style="font-style: italic;">HAL_CRCEx_Input_Data_Reverse()</span><o:p></o:p></span></li>
- </ul>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">HAL_CRC_Output_Data_Reverse()</span> renamed into <span style="font-style: italic;">HAL_CRCEx_Output_Data_Reverse()</span></span></li>
- </ul>
- <ul>
- <li><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;">Note: aliases has been added to keep compatibility with previous version</span></li>
- </ul>
-</ul></li>
-<li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
-
-
-
-<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">CRYP </span>update<br></span></p><ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">HAL_CRYP_ComputationCpltCallback()</span> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">renamed into </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-style: italic;">HAL_CRYPEx_ComputationCpltCallback() and </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">moved to the extension files (stm32l0xx_hal_cryp_ex.h/.c)</span></li>
- <li><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;">Note: alias has been added to keep compatibility with previous version</span></li>
-</ul></li>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">I2C</span> update<br></span></p>
- </li>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix
+in <span style="font-style: italic;">HAL_DMA_PollForTransfer()</span>
+to set error code <span style="font-style: italic;">HAL_DMA_ERROR_TE
+</span>in case of <span style="font-style: italic;">HAL_ERROR</span> status</span></small></li>
+</ul>
+</ul>
+<small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><br>
+</span></small>
+<ul style="margin-top: 0cm; list-style-type: square;">
+<li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL PWR</span> update<span style="font-weight: bold;"><br>
+</span></span></small></li>
+<ul>
+<li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">HAL_PWR_PVDConfig()</span>:
+add clear of the EXTI trigger before new configuration <br>
+</span></small></li>
+<li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix
+in <span style="font-style: italic;">HAL_PWR_EnterSTANDBYMode()</span>
+to not clear Wakeup flag (WUF), which need to be cleared at application
+level before to call this function<br>
+</span></small></li>
+</ul>
+<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RCC</span> update<br>
+</span></small></p>
+</li>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Allow
+to calibrate the HSI when it is used as system clock source<br>
+</span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix
+implementation of <span style="font-style: italic;">IS_RCC_OSCILLATORTYPE()</span>
+macro<br>
+</span></small></li>
+</ul>
+<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL ADC</span> update<br>
+</span></small></p>
+</li>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update
+ADC internal channels mapping: TEMPSENSOR connected to ADC_CHANNEL_18
+and VLCD mapped to ADC_CHANNEL_16 <br>
+</span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Skip
+polling for ADRDY flag when Low Power Auto Off mode is enabled<br>
+</span></small></li>
+</ul>
+<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL COMP</span> update<br>
+</span></small></p>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+<span style="font-style: italic;">LPTIMConnection</span>
+field in the <span style="font-style: italic;">COMP_InitTypeDef</span>
+structure.<o:p></o:p></span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+new defines: <span style="font-style: italic;">COMP_LPTIMCONNECTION_DISABLED</span>,
+<span style="font-style: italic;">COMP_LPTIMCONNECTION_ENABLED</span><o:p></o:p></span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+new macro IS_COMP_LPTIMCONNECTION<o:p></o:p></span></small></li>
+</ul>
+</li>
+<li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL LPTIM </span>update<br>
+</span></small></p>
+</li>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+<span style="font-style: italic;">CKPOL </span>configuration
+for encoder mod<span style="font-style: italic;">e</span></span></small></li>
+</ul>
+<li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">WWDG </span>update<br>
+</span></small></p>
+</li>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Miscellaneous
+minor update on the source code <span style="font-style: italic;"></span><span style="font-style: italic;"></span></span></small></li>
+</ul>
+<li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">IWDG </span>update<br>
+</span></small></p>
+</li>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Miscellaneous
+minor update on the source code</span></small></li>
+</ul>
+<li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">CRC </span>update<br>
+</span></small></p>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Some
+functions was renamed and moved to the extension files
+(stm32l0xx_hal_crc_ex.h/.c)</span></small></li>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-style: italic;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">HAL_CRC_Input_Data_Reverse()</span>
+renamed into <span style="font-style: italic;">HAL_CRCEx_Input_Data_Reverse()</span><o:p></o:p></span></small></li>
+</ul>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">HAL_CRC_Output_Data_Reverse()</span>
+renamed into <span style="font-style: italic;">HAL_CRCEx_Output_Data_Reverse()</span></span></small></li>
+</ul>
+<ul>
+<li><small><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;">Note:
+aliases has been added to keep compatibility with previous version</span></small></li>
+</ul>
+</ul>
+</li>
+<li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">CRYP </span>update<br>
+</span></small></p>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">HAL_CRYP_ComputationCpltCallback()</span>
+</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">renamed
+into </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-style: italic;">HAL_CRYPEx_ComputationCpltCallback()
+and </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">moved
+to the extension files (stm32l0xx_hal_cryp_ex.h/.c)</span></small></li>
+<li><small><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;">Note:
+alias has been added to keep compatibility with previous version</span></small></li>
+</ul>
+</li>
+<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">I2C</span> update<br>
+</span></small></p>
+</li>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
management of NACK event in Master transmitter mode and Slave
transmitter/receiver modes (only in polling mode), in that case the
-current transfer is stopped.</span></li>
- </ul>
- <li>
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">SMBUS </span>update<o:p></o:p></span></p>
-
-
-
-
-
-
-
-
-
-
-
- </li>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+current transfer is stopped.</span></small></li>
+</ul>
+<li><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">SMBUS </span>update<o:p></o:p></span></small></p>
+</li>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
a new function: <span style="font-style: italic;">HAL_SMBUS_DisableListen_IT()</span></span><br>
-<span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add aliases for the following functions <br>
- </span></li>
- <ul>
- <li style="font-style: italic;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">#define
+<span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+aliases for the following functions <br>
+</span></small></li>
+<ul>
+<li style="font-style: italic;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">#define
HAL_SMBUS_Slave_Listen_IT
-HAL_SMBUS_EnableListen_IT</span></li>
- <li style="font-style: italic;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback</span></li>
- <li style="font-style: italic;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback</span></li>
- </ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add alias <span style="font-style: italic;">HAL_SMBUS_STATE_SLAVE_LISTEN</span> for the constant <span style="font-style: italic;">HAL_SMBUS_STATE_LISTEN</span></span></li>
- </ul>
- <li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">UART </span>update<o:p></o:p></span></p>
-
-
-
-
+HAL_SMBUS_EnableListen_IT</span></small></li>
+<li style="font-style: italic;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">#define
+HAL_SMBUS_SlaveAddrCallback
+HAL_SMBUS_AddrCallback</span></small></li>
+<li style="font-style: italic;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">#define
+HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback</span></small></li>
+</ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+alias <span style="font-style: italic;">HAL_SMBUS_STATE_SLAVE_LISTEN</span>
+for the constant <span style="font-style: italic;">HAL_SMBUS_STATE_LISTEN</span></span></small></li>
+</ul>
+<li class="MsoNormal WordSection1" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">UART </span>update<o:p></o:p></span></small></p>
<ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_UART_WakeupCallback</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">()</span> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">renamed into </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_UART_WakeupCallback</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-style: italic;">() and </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">moved to the extension files (stm32l0xx_hal_cryp_ex.h/.c)</span></li>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> Add
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_UART_WakeupCallback</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">()</span> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">renamed
+into </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_UART_WakeupCallback</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-style: italic;">()
+and </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">moved
+to the extension files (stm32l0xx_hal_cryp_ex.h/.c)</span></small></li>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">
+Add
new macros to control CTS and RTS</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><br>
- </span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add specific macros to manage the
- flags cleared only by a software sequence<o:p></o:p></span></li>
- <ul style="font-style: italic;">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_UART_CLEAR_PEFLAG()<o:p></o:p></span></li>
- </ul>
- <ul style="font-style: italic;">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_UART_CLEAR_FEFLAG()<o:p></o:p></span></li>
- </ul>
- <ul style="font-style: italic;">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_UART_CLEAR_NEFLAG()<o:p></o:p></span></li>
- </ul>
- <ul style="font-style: italic;">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_UART_CLEAR_OREFLAG()<o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_UART_CLEAR_IDLEFLAG()</span></li>
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add several enhancements without
- affecting the driver functionalities <o:p></o:p></span></li>
- <ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove the check on RXNE set
- after reading the Data in the DR register<o:p></o:p></span></li>
- </ul>
- <ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update the transmit processes to
- use TXE instead of TC</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update <span style="font-style: italic;">HAL_UART_Transmit_IT()</span> to enable <span style="font-style: italic;">UART_IT_TXE</span> instead of <span style="font-style: italic;">UART_IT_TC</span></span></li>
- </ul>
+</span></small></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+specific macros to manage the flags cleared only by a software sequence<o:p></o:p></span></small></li>
+<ul style="font-style: italic;">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_UART_CLEAR_PEFLAG()<o:p></o:p></span></small></li>
+</ul>
+<ul style="font-style: italic;">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_UART_CLEAR_FEFLAG()<o:p></o:p></span></small></li>
+</ul>
+<ul style="font-style: italic;">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_UART_CLEAR_NEFLAG()<o:p></o:p></span></small></li>
+</ul>
+<ul style="font-style: italic;">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_UART_CLEAR_OREFLAG()<o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></small></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_UART_CLEAR_IDLEFLAG()</span></small></li>
+</ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+several enhancements without affecting the driver functionalities <o:p></o:p></span></small></li>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove
+the check on RXNE set after reading the Data in the DR register<o:p></o:p></span></small></li>
+</ul>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update
+the transmit processes to use TXE instead of TC</span></small></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update
+<span style="font-style: italic;">HAL_UART_Transmit_IT()</span>
+to enable <span style="font-style: italic;">UART_IT_TXE</span>
+instead of <span style="font-style: italic;">UART_IT_TC</span></span></small></li>
+</ul>
+</ul>
+</li>
+<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL USART</span> update<br>
+</span></small></p>
+</li>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+specific macros to manage the flags cleared only by a software sequence</span></small></li>
+<ul style="font-style: italic;">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_USART_CLEAR_PEFLAG()<o:p></o:p></span></small></li>
</ul>
- </li>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
-
-
-
-
-
-
-
-<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL USART</span> update<br></span></p></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add specific macros to manage the
- flags cleared only by a software sequence</span></li>
- <ul style="font-style: italic;">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_USART_CLEAR_PEFLAG()<o:p></o:p></span></li>
- </ul>
- <ul style="font-style: italic;">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_USART_CLEAR_FEFLAG()<o:p></o:p></span></li>
- </ul>
- <ul style="font-style: italic;">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_USART_CLEAR_NEFLAG()<o:p></o:p></span></li>
- </ul>
- <ul style="font-style: italic;">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_USART_CLEAR_OREFLAG()<o:p></o:p></span></li>
- </ul>
- <ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">__HAL_USART_CLEAR_IDLEFLAG()</span></span></li>
- </ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update <span style="font-style: italic;">HAL_USART_Transmit_IT()</span> to enable <span style="font-style: italic;">USART_IT_TXE</span> instead of <span style="font-style: italic;">USART_IT_TC</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
- </ul>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL IRDA</span> update<br></span></p>
+<ul style="font-style: italic;">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_USART_CLEAR_FEFLAG()<o:p></o:p></span></small></li>
+</ul>
+<ul style="font-style: italic;">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_USART_CLEAR_NEFLAG()<o:p></o:p></span></small></li>
+</ul>
+<ul style="font-style: italic;">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_USART_CLEAR_OREFLAG()<o:p></o:p></span></small></li>
+</ul>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">__HAL_USART_CLEAR_IDLEFLAG()</span></span></small></li>
+</ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update
+<span style="font-style: italic;">HAL_USART_Transmit_IT()</span>
+to enable <span style="font-style: italic;">USART_IT_TXE</span>
+instead of <span style="font-style: italic;">USART_IT_TC</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></small></li>
+</ul>
+<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL IRDA</span> update<br>
+</span></small></p>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+specific macros to manage the flags cleared only by a software sequence</span></small></li>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_IRDA_CLEAR_PEFLAG()<o:p></o:p></span></small></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_
+IRDA _CLEAR_FEFLAG()<o:p></o:p></span></small></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_
+IRDA _CLEAR_NEFLAG()<o:p></o:p></span></small></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_
+IRDA _CLEAR_OREFLAG()<o:p></o:p></span></small></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">__HAL_ IRDA _CLEAR_IDLEFLAG()</span><o:p></o:p></span></small></li>
+</ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+several enhancements without affecting the driver functionalities</span></small></li>
+<ul style="margin-top: 0cm;" type="circle">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove
+the check on RXNE set after reading the Data in the DR register</span><br>
+<span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></small></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update
+<span style="font-style: italic;">HAL_IRDA_Transmit_IT()</span>
+to enable <span style="font-style: italic;">IRDA_IT_TXE</span>
+instead of <span style="font-style: italic;">IRDA_IT_TC</span></span></small></li>
+</ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+the following APIs used within DMA process <o:p></o:p></span></small></li>
<ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add specific macros to manage the
- flags cleared only by a software sequence</span></li>
- <ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_IRDA_CLEAR_PEFLAG()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_ IRDA _CLEAR_FEFLAG()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_ IRDA _CLEAR_NEFLAG()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_ IRDA _CLEAR_OREFLAG()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">__HAL_ IRDA _CLEAR_IDLEFLAG()</span><o:p></o:p></span></li>
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add several enhancements without
- affecting the driver functionalities</span></li>
- <ul style="margin-top: 0cm;" type="circle">
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove the check on RXNE set
- after reading the Data in the DR register</span><br>
- <span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update <span style="font-style: italic;">HAL_IRDA_Transmit_IT()</span> to enable <span style="font-style: italic;">IRDA_IT_TXE</span> instead of <span style="font-style: italic;">IRDA_IT_TC</span></span></li>
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add the following APIs used within
- DMA process <o:p></o:p></span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_StatusTypeDef
- HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);<o:p></o:p></span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_StatusTypeDef
- HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);<o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_StatusTypeDef
- HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); <o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">void
- HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);<o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">void
- HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);</span></span></li>
- </ul>
-</ul></li>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
-
-
-
-
-
-
-
-<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SMARTCARD</span> update<br></span></p></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add specific macros to manage the
- flags cleared only by a software sequence</span></li>
- <ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_SMARTCARD_CLEAR_PEFLAG()<o:p></o:p></span></li>
- </ul>
- <ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_SMARTCARD_CLEAR_FEFLAG()<o:p></o:p></span></li>
- </ul>
- <ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_SMARTCARD_CLEAR_NEFLAG()<o:p></o:p></span></li>
- </ul>
- <ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_SMARTCARD_CLEAR_OREFLAG()<o:p></o:p></span></li>
- </ul>
- <ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">__HAL_SMARTCARD_CLEAR_IDLEFLAG()</span><o:p></o:p></span></li>
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add several enhancements without
- affecting the driver functionalities</span></li>
- <ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add a new state
- <span style="font-style: italic;">HAL_SMARTCARD_STATE_BUSY_TX_RX</span> and all processes has been updated
- accordingly</span></li>
- </ul>
- <ul>
- <li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update <span style="font-style: italic;">HAL_SMARTCARD_Transmit_IT()</span> to enable <span style="font-style: italic;">SMARTCARD_IT_TXE</span> instead of <span style="font-style: italic;">SMARTCARD_IT_TC</span></span></li>
- </ul>
- </ul>
- </ul>
- <span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;"><br>
- </span></span>
- <ul style="margin-top: 0cm; list-style-type: square;">
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SPI</span> update</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><o:p></o:p></span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Bugs fix</span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">SPI interface is used in synchronous polling mode: at high clock rates like SPI prescaler 2 and 4, calling <br>
-HAL_SPI_TransmitReceive() returns with error HAL_TIMEOUT</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">HAL_SPI_TransmitReceive_DMA()</span> does not clean up the TX DMA, so any subsequent SPI calls return the DMA error</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">HAL_SPI_Transmit_DMA()</span> is failing when data size is equal to 1 byte</span></li>
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add the following APIs used within the DMA process<o:p></o:p></span></li>
- </ul>
- <ul style="margin-top: 0cm;" type="circle">
-<ul style="font-style: italic;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_StatusTypeDef
- HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);<o:p></o:p></span></li></ul><ul style="font-style: italic;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_StatusTypeDef
- HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);<o:p></o:p></span></li></ul><ul style="font-style: italic;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_StatusTypeDef
- HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);<o:p></o:p></span></li></ul><ul style="font-style: italic;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">void
- HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);<o:p></o:p></span></li></ul><ul style="font-style: italic;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">void
- HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);<o:p></o:p></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef
- *hspi);</span><o:p></o:p></span></li></ul>
- </ul>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL TSC</span> update</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></p>
- </li>
- <ul>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix value of the constant <span style="font-style: italic;">TSC_ACQ_MODE_SYNCHRO</span></span></p>
- </li>
- </ul>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL PCD </span>update</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></p>
- </li>
- <ul>
-<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new macro <span style="font-style: italic;">__HAL_USB_EXTI_GENERATE_SWIT()</span></span></p>
- </li>
- </ul>
- </ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_StatusTypeDef
+HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);<o:p></o:p></span></small></li>
+</ul>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_StatusTypeDef
+HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);<o:p></o:p></span></small></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_StatusTypeDef
+HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); <o:p></o:p></span></small></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">void
+HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);<o:p></o:p></span></small></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">void
+HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);</span></span></small></li>
+</ul>
+</ul>
+</li>
+<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SMARTCARD</span> update<br>
+</span></small></p>
+</li>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+specific macros to manage the flags cleared only by a software sequence</span></small></li>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_SMARTCARD_CLEAR_PEFLAG()<o:p></o:p></span></small></li>
+</ul>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_SMARTCARD_CLEAR_FEFLAG()<o:p></o:p></span></small></li>
+</ul>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_SMARTCARD_CLEAR_NEFLAG()<o:p></o:p></span></small></li>
+</ul>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_SMARTCARD_CLEAR_OREFLAG()<o:p></o:p></span></small></li>
+</ul>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">__HAL_SMARTCARD_CLEAR_IDLEFLAG()</span><o:p></o:p></span></small></li>
+</ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+several enhancements without affecting the driver functionalities</span></small></li>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+a new state <span style="font-style: italic;">HAL_SMARTCARD_STATE_BUSY_TX_RX</span>
+and all processes has been updated accordingly</span></small></li>
+</ul>
+<ul>
+<li><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update
+<span style="font-style: italic;">HAL_SMARTCARD_Transmit_IT()</span>
+to enable <span style="font-style: italic;">SMARTCARD_IT_TXE</span>
+instead of <span style="font-style: italic;">SMARTCARD_IT_TC</span></span></small></li>
+</ul>
+</ul>
+</ul>
+<small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;"><br>
+</span></span></small>
+<ul style="margin-top: 0cm; list-style-type: square;">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SPI</span> update</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><o:p></o:p></span></small></li>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Bugs
+fix</span></small></li>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">SPI
+interface is used in synchronous polling mode: at high clock rates like
+SPI prescaler 2 and 4, calling <br>
+HAL_SPI_TransmitReceive() returns with error HAL_TIMEOUT</span></small></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">HAL_SPI_TransmitReceive_DMA()</span>
+does not clean up the TX DMA, so any subsequent SPI calls return the
+DMA error</span></small></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">HAL_SPI_Transmit_DMA()</span>
+is failing when data size is equal to 1 byte</span></small></li>
+</ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+the following APIs used within the DMA process<o:p></o:p></span></small></li>
+</ul>
+<ul style="margin-top: 0cm;" type="circle">
+<ul style="font-style: italic;">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_StatusTypeDef
+HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);<o:p></o:p></span></small></li>
+</ul>
+<ul style="font-style: italic;">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_StatusTypeDef
+HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);<o:p></o:p></span></small></li>
+</ul>
+<ul style="font-style: italic;">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_StatusTypeDef
+HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);<o:p></o:p></span></small></li>
+</ul>
+<ul style="font-style: italic;">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">void
+HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);<o:p></o:p></span></small></li>
+</ul>
+<ul style="font-style: italic;">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">void
+HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);<o:p></o:p></span></small></li>
+</ul>
+<ul>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">void
+HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);</span><o:p></o:p></span></small></li>
+</ul>
+</ul>
+<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL TSC</span> update</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></small></p>
+</li>
+<ul>
+<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix
+value of the constant <span style="font-style: italic;">TSC_ACQ_MODE_SYNCHRO</span></span></small></p>
+</li>
+</ul>
+<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL PCD </span>update</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></small></p>
+</li>
+<ul>
+<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><small>
+</small>
+<p class="MsoListParagraph"><small><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
+new macro <span style="font-style: italic;">__HAL_USB_EXTI_GENERATE_SWIT()</span></span></small></p>
+</li>
+</ul>
+</ul>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0
-/ 22-April-2014</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+/ 22-April-2014</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p>
-<span style="font-size: 10pt; font-family: Verdana;">First official release.</span><br><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span></u></b>
-
-
+<span style="font-size: 10pt; font-family: Verdana;">First
+official release.</span><br>
+<b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span></u></b>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
<div style="text-align: justify;">
<div style="text-align: justify;"><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistribution
@@ -1121,8 +1371,7 @@
<span style="font-family: "Verdana","sans-serif";"></span></div>
<span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span>
<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
-<hr align="center" size="2" width="100%">
-</span></div>
+<hr align="center" size="2" width="100%"></span></div>
<p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">For
complete documentation on </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32<span style="color: black;"> Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
</td>
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.S Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.S Tue Apr 19 11:15:15 2016 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
-;* Version : V1.2.0
-;* Date : 06-February-2015
+;* Version : V1.5.0
+;* Date : 8-January-2016
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@@ -90,7 +90,7 @@
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
@@ -161,11 +161,6 @@
EXPORT SVC_Handler [WEAK]
B .
ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
@@ -240,3 +235,5 @@
ALIGN
END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_STD/startup_stm32l053xx.S Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_STD/startup_stm32l053xx.S Tue Apr 19 11:15:15 2016 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
-;* Version : V1.2.0
-;* Date : 06-February-2015
+;* Version : V1.5.0
+;* Date : 8-January-2016
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@@ -63,7 +63,7 @@
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
@@ -134,11 +134,6 @@
EXPORT SVC_Handler [WEAK]
B .
ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
@@ -213,3 +208,5 @@
ALIGN
END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.S Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.S Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file startup_stm32l053xx.s
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief STM32L053xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
@@ -149,7 +149,7 @@
.word 0
.word 0
.word SVC_Handler
- .word DebugMon_Handler
+ .word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
@@ -203,9 +203,6 @@
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_IAR/startup_stm32l053xx.S Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_IAR/startup_stm32l053xx.S Tue Apr 19 11:15:15 2016 +0100
@@ -1,8 +1,8 @@
-;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
-;* Version : V1.2.0
-;* Date : 06-February-2015
+;* Version : V1.5.0
+;* Date : 8-January-2016
;* Description : STM32L053xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP
@@ -82,7 +82,7 @@
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
@@ -152,12 +152,6 @@
B SVC_Handler
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DebugMon_Handler
- B DebugMon_Handler
-
-
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/stm32l053xx.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/stm32l053xx.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l053xx.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l053xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -174,19 +174,26 @@
__IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
} COMP_TypeDef;
-
-/**
- * @brief CRC calculation unit
- */
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
typedef struct
{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
- uint32_t RESERVED2; /*!< Reserved, 0x0C */
- __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
- __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
} CRC_TypeDef;
/**
@@ -378,7 +385,6 @@
/**
* @brief LCD
*/
-
typedef struct
{
__IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
@@ -392,7 +398,6 @@
/**
* @brief MIFARE Firewall
*/
-
typedef struct
{
__IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
@@ -405,12 +410,11 @@
__IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
__IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
-} FW_TypeDef;
+} FIREWALL_TypeDef;
/**
* @brief Power Control
*/
-
typedef struct
{
__IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
@@ -491,7 +495,6 @@
/**
* @brief Serial Peripheral Interface
*/
-
typedef struct
{
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
@@ -510,27 +513,27 @@
*/
typedef struct
{
- __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
- __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
- __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
- __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
} TIM_TypeDef;
/**
@@ -557,7 +560,6 @@
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
-
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
@@ -586,7 +588,6 @@
/**
* @brief Universal Serial Bus Full Speed Device
*/
-
typedef struct
{
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
@@ -628,13 +629,12 @@
/** @addtogroup Peripheral_memory_map
* @{
*/
-
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_END ((uint32_t)0x0800FFFF) /*!< FLASH end address in the alias region */
-#define DATA_EEPROM_BASE ((uint32_t)0x08080000) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END ((uint32_t)0x080807FF) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
+#define FLASH_END ((uint32_t)0x0800FFFFU) /*!< FLASH end address in the alias region */
+#define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END ((uint32_t)0x080807FFU) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
/*!< Peripheral memory map */
#define APBPERIPH_BASE PERIPH_BASE
@@ -660,10 +660,11 @@
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
#define COMP1_BASE (APBPERIPH_BASE + 0x00010018)
#define COMP2_BASE (APBPERIPH_BASE + 0x0001001C)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
#define TIM21_BASE (APBPERIPH_BASE + 0x00010800)
#define TIM22_BASE (APBPERIPH_BASE + 0x00011400)
-#define FW_BASE (APBPERIPH_BASE + 0x00011C00)
+#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00)
#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
@@ -683,7 +684,7 @@
#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
-#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
+#define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
#define RNG_BASE (AHBPERIPH_BASE + 0x00005000)
@@ -715,6 +716,7 @@
#define CRS ((CRS_TypeDef *) CRS_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define LCD ((LCD_TypeDef *) LCD_BASE)
@@ -724,9 +726,11 @@
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
-#define FW ((FW_TypeDef *) FW_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
@@ -778,139 +782,140 @@
/* */
/******************************************************************************/
/******************** Bits definition for ADC_ISR register ******************/
-#define ADC_ISR_EOCAL ((uint32_t)0x00000800) /*!< End of calibration flag */
-#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
-#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
-#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
-#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
-#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
-#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
+#define ADC_ISR_EOCAL ((uint32_t)0x00000800U) /*!< End of calibration flag */
+#define ADC_ISR_AWD ((uint32_t)0x00000080U) /*!< Analog watchdog flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< Overrun flag */
+#define ADC_ISR_EOSEQ ((uint32_t)0x00000008U) /*!< End of Sequence flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< End of Conversion */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< End of sampling flag */
+#define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC Ready */
/* Old EOSEQ bit definition, maintained for legacy purpose */
#define ADC_ISR_EOS ADC_ISR_EOSEQ
/******************** Bits definition for ADC_IER register ******************/
-#define ADC_IER_EOCALIE ((uint32_t)0x00000800) /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
+#define ADC_IER_EOCALIE ((uint32_t)0x00000800U) /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE ((uint32_t)0x00000080U) /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE ((uint32_t)0x00000008U) /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC Ready interrupt enable */
/* Old EOSEQIE bit definition, maintained for legacy purpose */
#define ADC_IER_EOSIE ADC_IER_EOSEQIE
/******************** Bits definition for ADC_CR register *******************/
-#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
-#define ADC_CR_ADVREGEN ((uint32_t)0x10000000) /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
-#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
-#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */ /*#### TBV */
+#define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */
+#define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC start of conversion */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable command */
+#define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable control */ /*#### TBV */
/******************* Bits definition for ADC_CFGR1 register *****************/
-#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
-#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
-#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
-#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
+#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000U) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
+#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
+#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
+#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
+#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
+#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000U) /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000U) /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000U) /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000U) /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT ((uint32_t)0x00004000U) /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT ((uint32_t)0x00002000U) /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000U) /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00U) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
+#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0U) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
+#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100U) /*!< Bit 2 */
+#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020U) /*!< Data Alignment */
+#define ADC_CFGR1_RES ((uint32_t)0x00000018U) /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
+#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
+#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004U) /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002U) /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001U) /*!< Direct memory access enable */
/* Old WAIT bit definition, maintained for legacy purpose */
#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
/******************* Bits definition for ADC_CFGR2 register *****************/
-#define ADC_CFGR2_TOVS ((uint32_t)0x80000200) /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0) /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
-#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100) /*!< Bit 3 */
-#define ADC_CFGR2_OVSR ((uint32_t)0x0000001C) /*!< OVSR [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010) /*!< Bit 2 */
-#define ADC_CFGR2_OVSE ((uint32_t)0x00000001) /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< Bit 0 */
-#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+#define ADC_CFGR2_TOVS ((uint32_t)0x80000200U) /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
+#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
+#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
+#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
+#define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
+#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
+#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /*!< Bit 2 */
+#define ADC_CFGR2_OVSE ((uint32_t)0x00000001U) /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000U) /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000U) /*!< Bit 0 */
+#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000U) /*!< Bit 1 */
/****************** Bit definition for ADC_SMPR register ********************/
-#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-
-/* Bit names aliases maintained for legacy */
+#define ADC_SMPR_SMP ((uint32_t)0x00000007U) /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
+#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
+
+/* Legacy defines */
#define ADC_SMPR_SMPR ADC_SMPR_SMP
#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
/******************* Bit definition for ADC_TR register ********************/
-#define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
-#define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+#define ADC_TR_HT ((uint32_t)0x0FFF0000U) /*!< Analog watchdog high threshold */
+#define ADC_TR_LT ((uint32_t)0x00000FFFU) /*!< Analog watchdog low threshold */
/****************** Bit definition for ADC_CHSELR register ******************/
-#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
-#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
+#define ADC_CHSELR_CHSEL ((uint32_t)0x0007FFFFU) /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000U) /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000U) /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000U) /*!< Channel 16 selection */
+#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000U) /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000U) /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000U) /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000U) /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800U) /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400U) /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200U) /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100U) /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080U) /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040U) /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020U) /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010U) /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008U) /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004U) /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002U) /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001U) /*!< Channel 0 selection */
/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+#define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< Regular data */
/******************** Bit definition for ADC_CALFACT register ********************/
-#define ADC_CALFACT_CALFACT ((uint32_t)0x0000007F) /*!< Calibration factor */
+#define ADC_CALFACT_CALFACT ((uint32_t)0x0000007FU) /*!< Calibration factor */
/******************* Bit definition for ADC_CCR register ********************/
-#define ADC_CCR_LFMEN ((uint32_t)0x02000000) /*!< Low Frequency Mode enable */
-#define ADC_CCR_VLCDEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
-#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
-#define ADC_CCR_PRESC ((uint32_t)0x003C0000) /*!< PRESC [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+#define ADC_CCR_LFMEN ((uint32_t)0x02000000U) /*!< Low Frequency Mode enable */
+#define ADC_CCR_VLCDEN ((uint32_t)0x01000000U) /*!< Voltage LCD enable */
+#define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< Vrefint enable */
+#define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
+#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
+#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
+#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /*!< Bit 3 */
/******************************************************************************/
/* */
@@ -919,37 +924,40 @@
/******************************************************************************/
/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030) /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
-#define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
-#define COMP_CSR_COMP1WM ((uint32_t)0x00000100) /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000) /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000) /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000) /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
+#define COMP_CSR_COMP1EN ((uint32_t)0x00000001U) /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030U) /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP1 inverting input select bit 0 */
+#define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP1 inverting input select bit 1 */
+#define COMP_CSR_COMP1WM ((uint32_t)0x00000100U) /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000U) /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000U) /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000U) /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000U) /*!< COMP1 lock */
/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED ((uint32_t)0x000C0008) /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL ((uint32_t)0x00100070) /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00100010) /*!< COMP2 inverting input select bit 0 */
-#define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00200020) /*!< COMP2 inverting input select bit 1 */
-#define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00400040) /*!< COMP2 inverting input select bit 2 */
-#define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000) /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000) /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000) /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
+#define COMP_CSR_COMP2EN ((uint32_t)0x00000001U) /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED ((uint32_t)0x00000008U) /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL ((uint32_t)0x00000070U) /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP2 inverting input select bit 0 */
+#define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP2 inverting input select bit 1 */
+#define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00000040U) /*!< COMP2 inverting input select bit 2 */
+#define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700U) /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100U) /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200U) /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400U) /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000U) /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1 ((uint32_t)0x00002000U) /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000U) /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000U) /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000U) /*!< COMP2 lock */
/********************** Bit definition for COMP_CSR register common ****************/
-#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000) /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000) /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
-
+#define COMP_CSR_COMPxEN ((uint32_t)0x00000001U) /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000U) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000U) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000U) /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
/******************************************************************************/
/* */
@@ -957,26 +965,26 @@
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
-#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
+#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
-#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
-#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
-#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+#define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */
+#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
-#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
-#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
+#define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
@@ -985,92 +993,98 @@
/******************************************************************************/
/******************* Bit definition for CRS_CR register *********************/
-#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
-#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
-#define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
-#define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
-#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
-#define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
-#define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
+#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001U) /* SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002U) /* SYNC warning interrupt enable */
+#define CRS_CR_ERRIE ((uint32_t)0x00000004U) /* SYNC error interrupt enable */
+#define CRS_CR_ESYNCIE ((uint32_t)0x00000008U) /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define CRS_CR_CEN ((uint32_t)0x00000020U) /* Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040U) /* Automatic trimming enable */
+#define CRS_CR_SWSYNC ((uint32_t)0x00000080U) /* A Software SYNC event is generated */
+#define CRS_CR_TRIM ((uint32_t)0x00003F00U) /* HSI48 oscillator smooth trimming */
/******************* Bit definition for CRS_CFGR register *********************/
-#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
-#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
-
-#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
-#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
-#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
-#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
-
-#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
-#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
-#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
-
-#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
+#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFFU) /* Counter reload value */
+#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000U) /* Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000U) /* SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000U) /* Bit 0 */
+#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000U) /* Bit 1 */
+#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000U) /* Bit 2 */
+
+#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000U) /* SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000U) /* Bit 0 */
+#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000U) /* Bit 1 */
+
+#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000U) /* SYNC polarity selection */
/******************* Bit definition for CRS_ISR register *********************/
-#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
-#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
-#define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
-#define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
-#define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
-#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
-#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
-#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
+#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001U) /* SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002U) /* SYNC warning */
+#define CRS_ISR_ERRF ((uint32_t)0x00000004U) /* SYNC error flag */
+#define CRS_ISR_ESYNCF ((uint32_t)0x00000008U) /* Expected SYNC flag */
+#define CRS_ISR_SYNCERR ((uint32_t)0x00000100U) /* SYNC error */
+#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200U) /* SYNC missed */
+#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400U) /* Trimming overflow or underflow */
+#define CRS_ISR_FEDIR ((uint32_t)0x00008000U) /* Frequency error direction */
+#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000U) /* Frequency error capture */
/******************* Bit definition for CRS_ICR register *********************/
-#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
-#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
-#define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
-#define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
+#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001U) /* SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002U) /* SYNC warning clear flag */
+#define CRS_ICR_ERRC ((uint32_t)0x00000004U) /* Error clear flag */
+#define CRS_ICR_ESYNCC ((uint32_t)0x00000008U) /* Expected SYNC clear flag */
/******************************************************************************/
/* */
/* Digital to Analog Converter (DAC) */
/* */
/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
/******************** Bit definition for DAC_CR register ********************/
-#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-
-#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-
-#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun interrupt enable */
+#define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002U) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA Underrun interrupt enable */
/***************** Bit definition for DAC_SWTRIGR register ******************/
-#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!< DAC channel1 software trigger */
/***************** Bit definition for DAC_DHR12R1 register ******************/
-#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!< DAC channel1 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L1 register ******************/
-#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel1 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R1 register ******************/
-#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!< DAC channel1 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
-#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFF) /*!< DAC channel1 data output */
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */
/******************** Bit definition for DAC_SR register ********************/
-#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA underrun flag */
/******************************************************************************/
/* */
@@ -1079,44 +1093,44 @@
/******************************************************************************/
/**************** Bit definition for DBGMCU_IDCODE register *****************/
-#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
-#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
-#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
-#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
-#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
-#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /*!< Bit 15 */
/****************** Bit definition for DBGMCU_CR register *******************/
-#define DBGMCU_CR_DBG ((uint32_t)0x00000007) /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+#define DBGMCU_CR_DBG ((uint32_t)0x00000007U) /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U) /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /*!< Debug Standby mode */
/****************** Bit definition for DBGMCU_APB1_FZ register **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP ((uint32_t)0x00400000) /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000) /*!< LPTIM1 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010U) /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000U) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP ((uint32_t)0x00400000U) /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000U) /*!< LPTIM1 counter stopped when core is halted */
/****************** Bit definition for DBGMCU_APB2_FZ register **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020) /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004) /*!< TIM21 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020U) /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004U) /*!< TIM21 counter stopped when core is halted */
/******************************************************************************/
/* */
@@ -1125,107 +1139,107 @@
/******************************************************************************/
/******************* Bit definition for DMA_ISR register ********************/
-#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *******************/
-#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */
/******************* Bit definition for DMA_CCR register ********************/
-#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
-#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
-#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
-#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
-#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-
-#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-
-#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-
-#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+#define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */
/****************** Bit definition for DMA_CNDTR register *******************/
-#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CPAR register ********************/
-#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
/****************** Bit definition for DMA_CMAR register ********************/
-#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
/******************* Bit definition for DMA_CSELR register *******************/
-#define DMA_CSELR_C1S ((uint32_t)0x0000000F) /*!< Channel 1 Selection */
-#define DMA_CSELR_C2S ((uint32_t)0x000000F0) /*!< Channel 2 Selection */
-#define DMA_CSELR_C3S ((uint32_t)0x00000F00) /*!< Channel 3 Selection */
-#define DMA_CSELR_C4S ((uint32_t)0x0000F000) /*!< Channel 4 Selection */
-#define DMA_CSELR_C5S ((uint32_t)0x000F0000) /*!< Channel 5 Selection */
-#define DMA_CSELR_C6S ((uint32_t)0x00F00000) /*!< Channel 6 Selection */
-#define DMA_CSELR_C7S ((uint32_t)0x0F000000) /*!< Channel 7 Selection */
+#define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /*!< Channel 7 Selection */
/******************************************************************************/
@@ -1235,160 +1249,256 @@
/******************************************************************************/
/******************* Bit definition for EXTI_IMR register *******************/
-#define EXTI_IMR_IM0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_IM1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_IM2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_IM3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_IM4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_IM5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_IM6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_IM7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_IM8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_IM9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_IM10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_IM0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26 ((uint32_t)0x04000000U) /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28 ((uint32_t)0x10000000U) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29 ((uint32_t)0x20000000U) /*!< Interrupt Mask on line 29 */
/****************** Bit definition for EXTI_EMR register ********************/
-#define EXTI_EMR_EM0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
-#define EXTI_EMR_EM1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
-#define EXTI_EMR_EM2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
-#define EXTI_EMR_EM3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
-#define EXTI_EMR_EM4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
-#define EXTI_EMR_EM5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
-#define EXTI_EMR_EM6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
-#define EXTI_EMR_EM7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
-#define EXTI_EMR_EM8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
-#define EXTI_EMR_EM9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
-#define EXTI_EMR_EM10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_EM0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26 ((uint32_t)0x04000000U) /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28 ((uint32_t)0x10000000U) /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29 ((uint32_t)0x20000000U) /*!< Event Mask on line 29 */
/******************* Bit definition for EXTI_RTSR register ******************/
-#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_RT0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17 ((uint32_t)0x00020000U) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
/******************* Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_FT0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17 ((uint32_t)0x00020000U) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWI0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17 ((uint32_t)0x00020000U) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
/****************** Bit definition for EXTI_PR register *********************/
-#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
-#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
-#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
-#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
-#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
-#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
-#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
-#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
-#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
-#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
-#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
-#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
-#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
-#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
-#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
-#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
-#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
-#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
-#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
-#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
-#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
-#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
+#define EXTI_PR_PIF0 ((uint32_t)0x00000001U) /*!< Pending bit 0 */
+#define EXTI_PR_PIF1 ((uint32_t)0x00000002U) /*!< Pending bit 1 */
+#define EXTI_PR_PIF2 ((uint32_t)0x00000004U) /*!< Pending bit 2 */
+#define EXTI_PR_PIF3 ((uint32_t)0x00000008U) /*!< Pending bit 3 */
+#define EXTI_PR_PIF4 ((uint32_t)0x00000010U) /*!< Pending bit 4 */
+#define EXTI_PR_PIF5 ((uint32_t)0x00000020U) /*!< Pending bit 5 */
+#define EXTI_PR_PIF6 ((uint32_t)0x00000040U) /*!< Pending bit 6 */
+#define EXTI_PR_PIF7 ((uint32_t)0x00000080U) /*!< Pending bit 7 */
+#define EXTI_PR_PIF8 ((uint32_t)0x00000100U) /*!< Pending bit 8 */
+#define EXTI_PR_PIF9 ((uint32_t)0x00000200U) /*!< Pending bit 9 */
+#define EXTI_PR_PIF10 ((uint32_t)0x00000400U) /*!< Pending bit 10 */
+#define EXTI_PR_PIF11 ((uint32_t)0x00000800U) /*!< Pending bit 11 */
+#define EXTI_PR_PIF12 ((uint32_t)0x00001000U) /*!< Pending bit 12 */
+#define EXTI_PR_PIF13 ((uint32_t)0x00002000U) /*!< Pending bit 13 */
+#define EXTI_PR_PIF14 ((uint32_t)0x00004000U) /*!< Pending bit 14 */
+#define EXTI_PR_PIF15 ((uint32_t)0x00008000U) /*!< Pending bit 15 */
+#define EXTI_PR_PIF16 ((uint32_t)0x00010000U) /*!< Pending bit 16 */
+#define EXTI_PR_PIF17 ((uint32_t)0x00020000U) /*!< Pending bit 17 */
+#define EXTI_PR_PIF19 ((uint32_t)0x00080000U) /*!< Pending bit 19 */
+#define EXTI_PR_PIF20 ((uint32_t)0x00100000U) /*!< Pending bit 20 */
+#define EXTI_PR_PIF21 ((uint32_t)0x00200000U) /*!< Pending bit 21 */
+#define EXTI_PR_PIF22 ((uint32_t)0x00400000U) /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
/******************************************************************************/
/* */
@@ -1397,70 +1507,70 @@
/******************************************************************************/
/******************* Bit definition for FLASH_ACR register ******************/
-#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020) /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ ((uint32_t)0x00000040) /*!< Pre-read data address */
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002U) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008U) /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010U) /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020U) /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ ((uint32_t)0x00000040U) /*!< Pre-read data address */
/******************* Bit definition for FLASH_PECR register ******************/
-#define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
-#define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
-#define FLASH_PECR_FIX ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
-#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
-#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
-#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000) /*!< Half array mode */
+#define FLASH_PECR_PELOCK ((uint32_t)0x00000001U) /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002U) /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004U) /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG ((uint32_t)0x00000008U) /*!< Program matrix selection */
+#define FLASH_PECR_DATA ((uint32_t)0x00000010U) /*!< Data matrix selection */
+#define FLASH_PECR_FIX ((uint32_t)0x00000100U) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE ((uint32_t)0x00000200U) /*!< Page erasing mode */
+#define FLASH_PECR_FPRG ((uint32_t)0x00000400U) /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE ((uint32_t)0x00010000U) /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE ((uint32_t)0x00020000U) /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000U) /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000U) /*!< Half array mode */
/****************** Bit definition for FLASH_PDKEYR register ******************/
-#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
+#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */
/****************** Bit definition for FLASH_PEKEYR register ******************/
-#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
+#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */
/****************** Bit definition for FLASH_PRGKEYR register ******************/
-#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
+#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFFU) /*!< Program matrix Key */
/****************** Bit definition for FLASH_OPTKEYR register ******************/
-#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /*!< Option bytes matrix Key */
/****************** Bit definition for FLASH_SR register *******************/
-#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
-#define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
-#define FLASH_SR_HVOFF ((uint32_t)0x00000004) /*!< End of high voltage */
-#define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protection error */
-#define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
-#define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option Valid error */
-#define FLASH_SR_RDERR ((uint32_t)0x00002000) /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000) /*!< Not Zero error */
-#define FLASH_SR_FWWERR ((uint32_t)0x00020000) /*!< Write/Errase operation aborted */
-
-/* alias maintained for legacy */
+#define FLASH_SR_BSY ((uint32_t)0x00000001U) /*!< Busy */
+#define FLASH_SR_EOP ((uint32_t)0x00000002U) /*!< End Of Programming*/
+#define FLASH_SR_HVOFF ((uint32_t)0x00000004U) /*!< End of high voltage */
+#define FLASH_SR_READY ((uint32_t)0x00000008U) /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR ((uint32_t)0x00000100U) /*!< Write protection error */
+#define FLASH_SR_PGAERR ((uint32_t)0x00000200U) /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR ((uint32_t)0x00000400U) /*!< Size error */
+#define FLASH_SR_OPTVERR ((uint32_t)0x00000800U) /*!< Option Valid error */
+#define FLASH_SR_RDERR ((uint32_t)0x00002000U) /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000U) /*!< Not Zero error */
+#define FLASH_SR_FWWERR ((uint32_t)0x00020000U) /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
#define FLASH_SR_FWWER FLASH_SR_FWWERR
#define FLASH_SR_ENHV FLASH_SR_HVOFF
#define FLASH_SR_ENDHV FLASH_SR_HVOFF
/****************** Bit definition for FLASH_OPTR register *******************/
-#define FLASH_OPTR_RDPROT ((uint32_t)0x000000FF) /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
-#define FLASH_OPTR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000) /*!< BOOT1 */
+#define FLASH_OPTR_RDPROT ((uint32_t)0x000000FFU) /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100U) /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000U) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000U) /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000U) /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000U) /*!< nRST_STDBY */
+#define FLASH_OPTR_USER ((uint32_t)0x00700000U) /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000U) /*!< BOOT1 */
/****************** Bit definition for FLASH_WRPR register ******************/
-#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protection bits */
+#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFFU) /*!< Write Protection bits */
/******************************************************************************/
/* */
@@ -1468,279 +1578,299 @@
/* */
/******************************************************************************/
/******************* Bit definition for GPIO_MODER register *****************/
-#define GPIO_MODER_MODE0 ((uint32_t)0x00000003)
-#define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001)
-#define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002)
-#define GPIO_MODER_MODE1 ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004)
-#define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008)
-#define GPIO_MODER_MODE2 ((uint32_t)0x00000030)
-#define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010)
-#define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020)
-#define GPIO_MODER_MODE3 ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040)
-#define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080)
-#define GPIO_MODER_MODE4 ((uint32_t)0x00000300)
-#define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100)
-#define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200)
-#define GPIO_MODER_MODE5 ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400)
-#define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800)
-#define GPIO_MODER_MODE6 ((uint32_t)0x00003000)
-#define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000)
-#define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000)
-#define GPIO_MODER_MODE7 ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000)
-#define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000)
-#define GPIO_MODER_MODE8 ((uint32_t)0x00030000)
-#define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000)
-#define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000)
-#define GPIO_MODER_MODE9 ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000)
-#define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000)
-#define GPIO_MODER_MODE10 ((uint32_t)0x00300000)
-#define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000)
-#define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000)
-#define GPIO_MODER_MODE11 ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000)
-#define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000)
-#define GPIO_MODER_MODE12 ((uint32_t)0x03000000)
-#define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000)
-#define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000)
-#define GPIO_MODER_MODE13 ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000)
-#define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000)
-#define GPIO_MODER_MODE14 ((uint32_t)0x30000000)
-#define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000)
-#define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000)
-#define GPIO_MODER_MODE15 ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000)
-#define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000)
+#define GPIO_MODER_MODE0 ((uint32_t)0x00000003U)
+#define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U)
+#define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U)
+#define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU)
+#define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U)
+#define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U)
+#define GPIO_MODER_MODE2 ((uint32_t)0x00000030U)
+#define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U)
+#define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U)
+#define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U)
+#define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U)
+#define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U)
+#define GPIO_MODER_MODE4 ((uint32_t)0x00000300U)
+#define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U)
+#define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U)
+#define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U)
+#define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U)
+#define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U)
+#define GPIO_MODER_MODE6 ((uint32_t)0x00003000U)
+#define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U)
+#define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U)
+#define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U)
+#define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U)
+#define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U)
+#define GPIO_MODER_MODE8 ((uint32_t)0x00030000U)
+#define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U)
+#define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U)
+#define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U)
+#define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U)
+#define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U)
+#define GPIO_MODER_MODE10 ((uint32_t)0x00300000U)
+#define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U)
+#define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U)
+#define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U)
+#define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U)
+#define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U)
+#define GPIO_MODER_MODE12 ((uint32_t)0x03000000U)
+#define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U)
+#define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U)
+#define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U)
+#define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U)
+#define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U)
+#define GPIO_MODER_MODE14 ((uint32_t)0x30000000U)
+#define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U)
+#define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U)
+#define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U)
+#define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U)
+#define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U)
/****************** Bit definition for GPIO_OTYPER register *****************/
-#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U)
/**************** Bit definition for GPIO_OSPEEDR register ******************/
-#define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002)
-#define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008)
-#define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020)
-#define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080)
-#define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200)
-#define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800)
-#define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000)
-#define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000)
-#define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000)
-#define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000)
-#define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000)
-#define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000)
-#define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000)
-#define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000)
-#define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000)
-#define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000)
+#define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003U)
+#define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001U)
+#define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002U)
+#define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000CU)
+#define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004U)
+#define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008U)
+#define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030U)
+#define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010U)
+#define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020U)
+#define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0U)
+#define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040U)
+#define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080U)
+#define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300U)
+#define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100U)
+#define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200U)
+#define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00U)
+#define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400U)
+#define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800U)
+#define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000U)
+#define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000U)
+#define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000U)
+#define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000U)
+#define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000U)
+#define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000U)
+#define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000U)
+#define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000U)
+#define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000U)
+#define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000U)
+#define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000U)
+#define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000U)
+#define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000U)
+#define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000U)
+#define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000U)
+#define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000U)
+#define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000U)
+#define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000U)
+#define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000U)
+#define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000U)
+#define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000U)
+#define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000U)
+#define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000U)
+#define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000U)
+#define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000U)
+#define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000U)
+#define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000U)
+#define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000U)
+#define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000U)
+#define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000U)
/******************* Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002)
-#define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008)
-#define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020)
-#define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080)
-#define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200)
-#define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800)
-#define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000)
-#define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000)
-#define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000)
-#define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000)
-#define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000)
-#define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000)
-#define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000)
-#define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000)
-#define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000)
+#define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U)
+#define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U)
+#define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U)
+#define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU)
+#define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U)
+#define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U)
+#define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U)
+#define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U)
+#define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U)
+#define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U)
+#define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U)
+#define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U)
+#define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U)
+#define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U)
+#define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U)
+#define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U)
+#define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U)
+#define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U)
+#define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U)
+#define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U)
+#define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U)
+#define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U)
+#define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U)
+#define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U)
+#define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U)
+#define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U)
+#define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U)
+#define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U)
+#define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U)
+#define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U)
+#define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U)
+#define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U)
+#define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U)
+#define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U)
+#define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U)
+#define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U)
+#define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U)
+#define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U)
+#define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U)
+#define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U)
+#define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U)
+#define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U)
+#define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U)
+#define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U)
+#define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U)
+#define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U)
+#define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U)
+#define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U)
/******************* Bit definition for GPIO_IDR register *******************/
-#define GPIO_IDR_ID0 ((uint32_t)0x00000001)
-#define GPIO_IDR_ID1 ((uint32_t)0x00000002)
-#define GPIO_IDR_ID2 ((uint32_t)0x00000004)
-#define GPIO_IDR_ID3 ((uint32_t)0x00000008)
-#define GPIO_IDR_ID4 ((uint32_t)0x00000010)
-#define GPIO_IDR_ID5 ((uint32_t)0x00000020)
-#define GPIO_IDR_ID6 ((uint32_t)0x00000040)
-#define GPIO_IDR_ID7 ((uint32_t)0x00000080)
-#define GPIO_IDR_ID8 ((uint32_t)0x00000100)
-#define GPIO_IDR_ID9 ((uint32_t)0x00000200)
-#define GPIO_IDR_ID10 ((uint32_t)0x00000400)
-#define GPIO_IDR_ID11 ((uint32_t)0x00000800)
-#define GPIO_IDR_ID12 ((uint32_t)0x00001000)
-#define GPIO_IDR_ID13 ((uint32_t)0x00002000)
-#define GPIO_IDR_ID14 ((uint32_t)0x00004000)
-#define GPIO_IDR_ID15 ((uint32_t)0x00008000)
+#define GPIO_IDR_ID0 ((uint32_t)0x00000001U)
+#define GPIO_IDR_ID1 ((uint32_t)0x00000002U)
+#define GPIO_IDR_ID2 ((uint32_t)0x00000004U)
+#define GPIO_IDR_ID3 ((uint32_t)0x00000008U)
+#define GPIO_IDR_ID4 ((uint32_t)0x00000010U)
+#define GPIO_IDR_ID5 ((uint32_t)0x00000020U)
+#define GPIO_IDR_ID6 ((uint32_t)0x00000040U)
+#define GPIO_IDR_ID7 ((uint32_t)0x00000080U)
+#define GPIO_IDR_ID8 ((uint32_t)0x00000100U)
+#define GPIO_IDR_ID9 ((uint32_t)0x00000200U)
+#define GPIO_IDR_ID10 ((uint32_t)0x00000400U)
+#define GPIO_IDR_ID11 ((uint32_t)0x00000800U)
+#define GPIO_IDR_ID12 ((uint32_t)0x00001000U)
+#define GPIO_IDR_ID13 ((uint32_t)0x00002000U)
+#define GPIO_IDR_ID14 ((uint32_t)0x00004000U)
+#define GPIO_IDR_ID15 ((uint32_t)0x00008000U)
/****************** Bit definition for GPIO_ODR register ********************/
-#define GPIO_ODR_OD0 ((uint32_t)0x00000001)
-#define GPIO_ODR_OD1 ((uint32_t)0x00000002)
-#define GPIO_ODR_OD2 ((uint32_t)0x00000004)
-#define GPIO_ODR_OD3 ((uint32_t)0x00000008)
-#define GPIO_ODR_OD4 ((uint32_t)0x00000010)
-#define GPIO_ODR_OD5 ((uint32_t)0x00000020)
-#define GPIO_ODR_OD6 ((uint32_t)0x00000040)
-#define GPIO_ODR_OD7 ((uint32_t)0x00000080)
-#define GPIO_ODR_OD8 ((uint32_t)0x00000100)
-#define GPIO_ODR_OD9 ((uint32_t)0x00000200)
-#define GPIO_ODR_OD10 ((uint32_t)0x00000400)
-#define GPIO_ODR_OD11 ((uint32_t)0x00000800)
-#define GPIO_ODR_OD12 ((uint32_t)0x00001000)
-#define GPIO_ODR_OD13 ((uint32_t)0x00002000)
-#define GPIO_ODR_OD14 ((uint32_t)0x00004000)
-#define GPIO_ODR_OD15 ((uint32_t)0x00008000)
+#define GPIO_ODR_OD0 ((uint32_t)0x00000001U)
+#define GPIO_ODR_OD1 ((uint32_t)0x00000002U)
+#define GPIO_ODR_OD2 ((uint32_t)0x00000004U)
+#define GPIO_ODR_OD3 ((uint32_t)0x00000008U)
+#define GPIO_ODR_OD4 ((uint32_t)0x00000010U)
+#define GPIO_ODR_OD5 ((uint32_t)0x00000020U)
+#define GPIO_ODR_OD6 ((uint32_t)0x00000040U)
+#define GPIO_ODR_OD7 ((uint32_t)0x00000080U)
+#define GPIO_ODR_OD8 ((uint32_t)0x00000100U)
+#define GPIO_ODR_OD9 ((uint32_t)0x00000200U)
+#define GPIO_ODR_OD10 ((uint32_t)0x00000400U)
+#define GPIO_ODR_OD11 ((uint32_t)0x00000800U)
+#define GPIO_ODR_OD12 ((uint32_t)0x00001000U)
+#define GPIO_ODR_OD13 ((uint32_t)0x00002000U)
+#define GPIO_ODR_OD14 ((uint32_t)0x00004000U)
+#define GPIO_ODR_OD15 ((uint32_t)0x00008000U)
/****************** Bit definition for GPIO_BSRR register ********************/
-#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U)
/****************** Bit definition for GPIO_LCKR register ********************/
-#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000U)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU)
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U)
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U)
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U)
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U)
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U)
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U)
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U)
/****************** Bit definition for GPIO_BRR register *********************/
-#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
-#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
-#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
-#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
-#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
-#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
-#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
-#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
-#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
-#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
-#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
-#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
-#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
-#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
-#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
-#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001U)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002U)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004U)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008U)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010U)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020U)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040U)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080U)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100U)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200U)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400U)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800U)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000U)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000U)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000U)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000U)
/******************************************************************************/
/* */
@@ -1749,102 +1879,110 @@
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register *******************/
-#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
-#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
-#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
-#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
-#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
-#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+#define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */
/****************** Bit definition for I2C_CR2 register ********************/
-#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
-#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
-#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+#define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */
/******************* Bit definition for I2C_OAR1 register ******************/
-#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register ******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
-#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */
/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */
/****************** Bit definition for I2C_ISR register *********************/
-#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
-#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
-#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
-#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
-#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
-#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
-#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
-#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
-#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
-#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+#define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */
/****************** Bit definition for I2C_ICR register *********************/
-#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
-#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */
/****************** Bit definition for I2C_PECR register *********************/
-#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+#define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */
/****************** Bit definition for I2C_RXDR register *********************/
-#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */
/****************** Bit definition for I2C_TXDR register *********************/
-#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */
/******************************************************************************/
/* */
@@ -1852,24 +1990,24 @@
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
+#define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!< Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
-#define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define IWDG_PR_PR ((uint32_t)0x00000007U) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
/******************* Bit definition for IWDG_RLR register *******************/
-#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
+#define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!< Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
-#define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
+#define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint32_t)0x00000004U) /*!< Watchdog counter window value update */
/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
+#define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /*!< Watchdog counter window value */
/******************************************************************************/
/* */
@@ -1878,64 +2016,66 @@
/******************************************************************************/
/******************* Bit definition for LCD_CR register *********************/
-#define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */
-#define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */
-#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */
-#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */
-
-#define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
-#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
+#define LCD_CR_LCDEN ((uint32_t)0x00000001U) /*!< LCD Enable Bit */
+#define LCD_CR_VSEL ((uint32_t)0x00000002U) /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY ((uint32_t)0x0000001CU) /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0 ((uint32_t)0x00000004U) /*!< Duty selector Bit 0 */
+#define LCD_CR_DUTY_1 ((uint32_t)0x00000008U) /*!< Duty selector Bit 1 */
+#define LCD_CR_DUTY_2 ((uint32_t)0x00000010U) /*!< Duty selector Bit 2 */
+
+#define LCD_CR_BIAS ((uint32_t)0x00000060U) /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0 ((uint32_t)0x00000020U) /*!< Bias selector Bit 0 */
+#define LCD_CR_BIAS_1 ((uint32_t)0x00000040U) /*!< Bias selector Bit 1 */
+
+#define LCD_CR_MUX_SEG ((uint32_t)0x00000080U) /*!< Mux Segment Enable Bit */
/******************* Bit definition for LCD_FCR register ********************/
-#define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-
-#define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */
-#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */
-#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */
-
-#define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-
-#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */
-#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */
-#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */
-
-#define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-
-#define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */
+#define LCD_FCR_HD ((uint32_t)0x00000001U) /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE ((uint32_t)0x00000002U) /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE ((uint32_t)0x00000008U) /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON ((uint32_t)0x00000070U) /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
+#define LCD_FCR_PON_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
+#define LCD_FCR_PON_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
+
+#define LCD_FCR_DEAD ((uint32_t)0x00000380U) /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080U) /*!< Bit 0 */
+#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100U) /*!< Bit 1 */
+#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200U) /*!< Bit 2 */
+
+#define LCD_FCR_CC ((uint32_t)0x00001C00U) /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
+#define LCD_FCR_CC_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
+#define LCD_FCR_CC_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
+
+#define LCD_FCR_BLINKF ((uint32_t)0x0000E000U) /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
+#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
+#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
+
+#define LCD_FCR_BLINK ((uint32_t)0x00030000U) /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
+#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
+
+#define LCD_FCR_DIV ((uint32_t)0x003C0000U) /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS ((uint32_t)0x03C00000U) /*!< PS[3:0] bits (Prescaler) */
/******************* Bit definition for LCD_SR register *********************/
-#define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */
-#define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */
-#define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */
+#define LCD_SR_ENS ((uint32_t)0x00000001U) /*!< LCD Enabled Bit */
+#define LCD_SR_SOF ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR ((uint32_t)0x00000004U) /*!< Update Display Request Bit */
+#define LCD_SR_UDD ((uint32_t)0x00000008U) /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY ((uint32_t)0x00000010U) /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR ((uint32_t)0x00000020U) /*!< LCD FCR Register Synchronization Flag Bit */
/******************* Bit definition for LCD_CLR register ********************/
-#define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */
+#define LCD_CLR_SOFC ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC ((uint32_t)0x00000008U) /*!< Update Display Done Flag Clear Bit */
/******************* Bit definition for LCD_RAM register ********************/
-#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */
+#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFFU) /*!< Segment Data Bits */
/******************************************************************************/
/* */
@@ -1943,81 +2083,81 @@
/* */
/******************************************************************************/
/****************** Bit definition for LPTIM_ISR register *******************/
-#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */
-#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
+#define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /*!< Compare match */
+#define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP ((uint32_t)0x00000020U) /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /*!< Counter direction change up to down */
/****************** Bit definition for LPTIM_ICR register *******************/
-#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
+#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /*!< Counter direction change up to down Clear Flag */
/****************** Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
+#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /*!< Counter direction change up to down Interrupt Enable */
/****************** Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */
-#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */
-
-#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-
-#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-
-#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */
-#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */
-#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */
-
-#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */
-#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */
-#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */
-
-#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */
-#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */
-
-#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */
-#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
+#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /*!< Bit 0 */
+#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /*!< Bit 1 */
+
+#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
+#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
+
+#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
+#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
+
+#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
+#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
+#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
+#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
+
+#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /*!< Timout enable */
+#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /*!< Encoder mode enable */
/****************** Bit definition for LPTIM_CR register ********************/
-#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */
+#define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /*!< Timer start in continuous mode */
/****************** Bit definition for LPTIM_CMP register *******************/
-#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */
+#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /*!< Compare register */
/****************** Bit definition for LPTIM_ARR register *******************/
-#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */
+#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!< Auto reload register */
/****************** Bit definition for LPTIM_CNT register *******************/
-#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */
+#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!< Counter register */
/******************************************************************************/
/* */
@@ -2026,17 +2166,17 @@
/******************************************************************************/
/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD ((uint32_t)0x00FFFF00) /*!< Code Segment Start Address */
-#define FW_CSL_LENG ((uint32_t)0x003FFF00) /*!< Code Segment Length */
-#define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00) /*!< Non Volatile Dat Segment Start Address */
-#define FW_NVDSL_LENG ((uint32_t)0x003FFF00) /*!< Non Volatile Data Segment Length */
-#define FW_VDSSA_ADD ((uint32_t)0x0000FFC0) /*!< Volatile Data Segment Start Address */
-#define FW_VDSL_LENG ((uint32_t)0x0000FFC0) /*!< Volatile Data Segment Length */
+#define FW_CSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Code Segment Start Address */
+#define FW_CSL_LENG ((uint32_t)0x003FFF00U) /*!< Code Segment Length */
+#define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG ((uint32_t)0x003FFF00U) /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Length */
/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA ((uint32_t)0x00000001) /*!< Firewall Pre Arm*/
-#define FW_CR_VDS ((uint32_t)0x00000002) /*!< Volatile Data Sharing*/
-#define FW_CR_VDE ((uint32_t)0x00000004) /*!< Volatile Data Execution*/
+#define FW_CR_FPA ((uint32_t)0x00000001U) /*!< Firewall Pre Arm*/
+#define FW_CR_VDS ((uint32_t)0x00000002U) /*!< Volatile Data Sharing*/
+#define FW_CR_VDE ((uint32_t)0x00000004U) /*!< Volatile Data Execution*/
/******************************************************************************/
/* */
@@ -2045,47 +2185,47 @@
/******************************************************************************/
/******************** Bit definition for PWR_CR register ********************/
-#define PWR_CR_LPSDSR ((uint32_t)0x00000001) /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
-#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define PWR_CR_LPSDSR ((uint32_t)0x00000001U) /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS ((uint32_t)0x00000002U) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004U) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008U) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010U) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0U) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
-
-#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP ((uint32_t)0x00000200) /*!< Ultra Low Power mode */
-#define PWR_CR_FWU ((uint32_t)0x00000400) /*!< Fast wakeup */
-
-#define PWR_CR_VOS ((uint32_t)0x00001800) /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0 ((uint32_t)0x00000800) /*!< Bit 0 */
-#define PWR_CR_VOS_1 ((uint32_t)0x00001000) /*!< Bit 1 */
-#define PWR_CR_DSEEKOFF ((uint32_t)0x00002000) /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN ((uint32_t)0x00004000) /*!< Low power run mode */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100U) /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP ((uint32_t)0x00000200U) /*!< Ultra Low Power mode */
+#define PWR_CR_FWU ((uint32_t)0x00000400U) /*!< Fast wakeup */
+
+#define PWR_CR_VOS ((uint32_t)0x00001800U) /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
+#define PWR_CR_VOS_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
+#define PWR_CR_DSEEKOFF ((uint32_t)0x00002000U) /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN ((uint32_t)0x00004000U) /*!< Low power run mode */
/******************* Bit definition for PWR_CSR register ********************/
-#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
-#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
-#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF ((uint32_t)0x00000010) /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF ((uint32_t)0x00000020) /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
+#define PWR_CSR_WUF ((uint32_t)0x00000001U) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002U) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004U) /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF ((uint32_t)0x00000010U) /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF ((uint32_t)0x00000020U) /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /*!< Enable WKUP pin 2 */
/******************************************************************************/
/* */
@@ -2094,325 +2234,395 @@
/******************************************************************************/
/******************** Bit definition for RCC_CR register ********************/
-#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON ((uint32_t)0x00000002) /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY ((uint32_t)0x00000004) /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN ((uint32_t)0x00000008) /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF ((uint32_t)0x00000010) /*!< Internal High Speed clock divider flag */
-#define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON ((uint32_t)0x00080000) /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE ((uint32_t)0x00300000) /*!< RTC/LCD prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000) /*!< RTC/LCD prescaler Bit 0 */
-#define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000) /*!< RTC/LCD prescaler Bit 1 */
-#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
-#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+#define RCC_CR_HSION ((uint32_t)0x00000001U) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON ((uint32_t)0x00000002U) /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000004U) /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN ((uint32_t)0x00000008U) /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF ((uint32_t)0x00000010U) /*!< Internal High Speed clock divider flag */
+#define RCC_CR_MSION ((uint32_t)0x00000100U) /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY ((uint32_t)0x00000200U) /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON ((uint32_t)0x00080000U) /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE ((uint32_t)0x00300000U) /*!< RTC/LCD prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000U) /*!< RTC/LCD prescaler Bit 0 */
+#define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000U) /*!< RTC/LCD prescaler Bit 1 */
+#define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
/******************** Bit definition for RCC_ICSCR register *****************/
-#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */
-#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */
-#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */
-#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */
-#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */
-#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */
-#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */
-#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */
+#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FFU) /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00U) /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000U) /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed clock Range 65.536 KHz */
+#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000U) /*!< Internal Multi Speed clock Range 131.072 KHz */
+#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000U) /*!< Internal Multi Speed clock Range 262.144 KHz */
+#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000U) /*!< Internal Multi Speed clock Range 524.288 KHz */
+#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000U) /*!< Internal Multi Speed clock Range 1.048 MHz */
+#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000U) /*!< Internal Multi Speed clock Range 2.097 MHz */
+#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000U) /*!< Internal Multi Speed clock Range 4.194 MHz */
+#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000U) /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000U) /*!< Internal Multi Speed clock trimming */
/******************** Bit definition for RCC_CRRCR register *****************/
-#define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001) /*!< HSI 48MHz clock enable */
-#define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002) /*!< HSI 48MHz clock ready flag */
-#define RCC_CRRCR_HSI48CAL ((uint32_t)0x0000FF00) /*!< HSI 48MHz clock Calibration */
+#define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001U) /*!< HSI 48MHz clock enable */
+#define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002U) /*!< HSI 48MHz clock ready flag */
+#define RCC_CRRCR_HSI48CAL ((uint32_t)0x0000FF00U) /*!< HSI 48MHz clock Calibration */
/******************* Bit definition for RCC_CFGR register *******************/
/*!< SW configuration */
-#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-
-#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selected as system clock */
/*!< SWS configuration */
-#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-
-#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */
/*!< HPRE configuration */
-#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
-#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
-#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000) /*!< Wake Up from Stop Clock selection */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /*!< Wake Up from Stop Clock selection */
/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000U) /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000U) /*!< HSE as PLL entry clock source */
/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
-
-#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000U) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000U) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000U) /*!< PLL input clock * 48 */
/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */
-#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */
-
-#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */
+#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000U) /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000U) /*!< Bit0 */
+#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000U) /*!< Bit1 */
+
+#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000U) /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000U) /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000U) /*!< PLL clock output = CKVCO / 4 */
/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */
-#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */
-#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */
-#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
+#define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000U) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
+#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
+#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
+#define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000U) /*!< Bit 3 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000U) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000U) /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000U) /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000U) /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000U) /*!< PLL clock divided */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000U) /*!< LSI selected */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000U) /*!< LSE selected */
+#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000U) /*!< HSI48 clock selected as MCO source */
+
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!< MCO is divided by 8 */
+
+#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
/*!<****************** Bit definition for RCC_CIER register ********************/
-#define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001) /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE ((uint32_t)0x00000002) /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004) /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE ((uint32_t)0x00000008) /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010) /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020) /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIER_LSECSSIE ((uint32_t)0x00000080) /*!< LSE CSS Interrupt Enable */
+#define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE ((uint32_t)0x00000080U) /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
/*!<****************** Bit definition for RCC_CIFR register ********************/
-#define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIFR_LSECSSF ((uint32_t)0x00000080) /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSF ((uint32_t)0x00000100) /*!< Clock Security System Interrupt flag */
+#define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
/*!<****************** Bit definition for RCC_CICR register ********************/
-#define RCC_CICR_LSIRDYC ((uint32_t)0x00000001) /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC ((uint32_t)0x00000002) /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC ((uint32_t)0x00000004) /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC ((uint32_t)0x00000008) /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC ((uint32_t)0x00000010) /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC ((uint32_t)0x00000020) /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_HSI48RDYC ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CICR_LSECSSC ((uint32_t)0x00000080) /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSC ((uint32_t)0x00000100) /*!< Clock Security System Interrupt Clear */
-
+#define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_HSI48RDYC ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
/***************** Bit definition for RCC_IOPRSTR register ******************/
-#define RCC_IOPRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOHRST ((uint32_t)0x00000080) /*!< GPIO port H reset */
+#define RCC_IOPRSTR_IOPARST ((uint32_t)0x00000001U) /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST ((uint32_t)0x00000002U) /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST ((uint32_t)0x00000004U) /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST ((uint32_t)0x00000008U) /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPHRST ((uint32_t)0x00000080U) /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
/****************** Bit definition for RCC_AHBRST register ******************/
-#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x00000001) /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100) /*!< Memory interface reset reset */
-#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
-#define RCC_AHBRSTR_TSCRST ((uint32_t)0x00010000) /*!< TSC reset */
-#define RCC_AHBRSTR_RNGRST ((uint32_t)0x00100000) /*!< RNG reset */
+#define RCC_AHBRSTR_DMARST ((uint32_t)0x00000001U) /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100U) /*!< Memory interface reset reset */
+#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000U) /*!< CRC reset */
+#define RCC_AHBRSTR_TSCRST ((uint32_t)0x00010000U) /*!< TSC reset */
+#define RCC_AHBRSTR_RNGRST ((uint32_t)0x00100000U) /*!< RNG reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
/***************** Bit definition for RCC_APB2RSTR register *****************/
-#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
-#define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004) /*!< TIM21 clock reset */
-#define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020) /*!< TIM22 clock reset */
-#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 clock reset */
-#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
-#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
-#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U) /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004U) /*!< TIM21 clock reset */
+#define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020U) /*!< TIM22 clock reset */
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200U) /*!< ADC1 clock reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U) /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000U) /*!< USART1 clock reset */
+#define RCC_APB2RSTR_DBGRST ((uint32_t)0x00400000U) /*!< DBGMCU clock reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 clock reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU clock reset */
/***************** Bit definition for RCC_APB1RSTR register *****************/
-#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
-#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
-#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD clock reset */
-#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
-#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
-#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
-#define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000) /*!< LPUART1 clock reset */
-#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
-#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
-#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
-#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
-#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
-#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
-#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000) /*!< LPTIM1 clock reset */
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001U) /*!< Timer 2 clock reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010U) /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200U) /*!< LCD clock reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800U) /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000U) /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000U) /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000U) /*!< LPUART1 clock reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000U) /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000U) /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000U) /*!< USB clock reset */
+#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000U) /*!< CRS clock reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000U) /*!< PWR clock reset */
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000U) /*!< DAC clock reset */
+#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000U) /*!< LPTIM1 clock reset */
/***************** Bit definition for RCC_IOPENR register ******************/
-#define RCC_IOPENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOHEN ((uint32_t)0x00000080) /*!< GPIO port H clock enable */
+#define RCC_IOPENR_IOPAEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPDEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enable */
+#define RCC_IOPENR_IOPHEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
/***************** Bit definition for RCC_AHBENR register ******************/
-#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN ((uint32_t)0x00000100) /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
-#define RCC_AHBENR_TSCEN ((uint32_t)0x00010000) /*!< TSC clock enable */
-#define RCC_AHBENR_RNGEN ((uint32_t)0x00100000) /*!< RNG clock enable */
+#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001U) /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000U) /*!< CRC clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x00010000U) /*!< TSC clock enable */
+#define RCC_AHBENR_RNGEN ((uint32_t)0x00100000U) /*!< RNG clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
/***************** Bit definition for RCC_APB2ENR register ******************/
-#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004) /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020) /*!< TIM22 clock enable */
-#define RCC_APB2ENR_MIFIEN ((uint32_t)0x00000080) /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004U) /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020U) /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U) /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200U) /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000U) /*!< USART1 clock enable */
+#define RCC_APB2ENR_DBGEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
/***************** Bit definition for RCC_APB1ENR register ******************/
-#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000) /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
-#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
-#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000) /*!< LPTIM1 clock enable */
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001U) /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010U) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200U) /*!< LCD clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000U) /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000U) /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000U) /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000U) /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000U) /*!< I2C2 clock enable */
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000U) /*!< USB clock enable */
+#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000U) /*!< CRS clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000U) /*!< PWR clock enable */
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000U) /*!< DAC clock enable */
+#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enable */
/****************** Bit definition for RCC_IOPSMENR register ****************/
-#define RCC_IOPSMENR_GPIOASMEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN ((uint32_t)0x00000080) /*!< GPIO port H clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPASMEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
/***************** Bit definition for RCC_AHBSMENR register ******************/
-#define RCC_AHBSMENR_DMA1SMEN ((uint32_t)0x00000001) /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100) /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200) /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_TSCSMEN ((uint32_t)0x00010000) /*!< TSC clock enabled in sleep mode */
-#define RCC_AHBSMENR_RNGSMEN ((uint32_t)0x00100000) /*!< RNG clock enabled in sleep mode */
+#define RCC_AHBSMENR_DMASMEN ((uint32_t)0x00000001U) /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200U) /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000U) /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBSMENR_TSCSMEN ((uint32_t)0x00010000U) /*!< TSC clock enabled in sleep mode */
+#define RCC_AHBSMENR_RNGSMEN ((uint32_t)0x00100000U) /*!< RNG clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
/***************** Bit definition for RCC_APB2SMENR register ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001) /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004) /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020) /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADC1SMEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN ((uint32_t)0x00400000) /*!< DBGMCU clock enabled in sleep mode */
+#define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004U) /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020U) /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN ((uint32_t)0x00000200U) /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U) /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000U) /*!< USART1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
/***************** Bit definition for RCC_APB1SMENR register ******************/
-#define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LCDSMEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN ((uint32_t)0x00004000) /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000) /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000) /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000) /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN ((uint32_t)0x00400000) /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USBSMEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */
-#define RCC_APB1SMENR_CRSSMEN ((uint32_t)0x08000000) /*!< CRS clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000) /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_DACSMEN ((uint32_t)0x20000000) /*!< DAC clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000) /*!< LPTIM1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001U) /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM6SMEN ((uint32_t)0x00000010U) /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LCDSMEN ((uint32_t)0x00000200U) /*!< LCD clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_SPI2SMEN ((uint32_t)0x00004000U) /*!< SPI2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000U) /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000U) /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000U) /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C2SMEN ((uint32_t)0x00400000U) /*!< I2C2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USBSMEN ((uint32_t)0x00800000U) /*!< USB clock enabled in sleep mode */
+#define RCC_APB1SMENR_CRSSMEN ((uint32_t)0x08000000U) /*!< CRS clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000U) /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_DACSMEN ((uint32_t)0x20000000U) /*!< DAC clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enabled in sleep mode */
/******************* Bit definition for RCC_CCIPR register *******************/
/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003) /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003U) /*!< USART1SEL[1:0] bits */
+#define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000C) /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU) /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
+#define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
/*!< LPUART1 Clock source selection */
#define RCC_CCIPR_LPUART1SEL ((uint32_t)0x0000C00) /*!< LPUART1SEL[1:0] bits */
@@ -2420,59 +2630,63 @@
#define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */
/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000) /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U) /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
+#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
/*!< LPTIM1 Clock source selection */
-#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000) /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U) /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
+#define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
/*!< HSI48 Clock source selection */
-#define RCC_CCIPR_HSI48SEL ((uint32_t)0x04000000) /*!< HSI48 RC clock source selection bit for USB and RNG*/
-
-/* Bit name alias maintained for legacy */
+#define RCC_CCIPR_HSI48SEL ((uint32_t)0x04000000U) /*!< HSI48 RC clock source selection bit for USB and RNG*/
+
+/* Legacy defines */
#define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
/******************* Bit definition for RCC_CSR register *******************/
-#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */
+#define RCC_CSR_LSION ((uint32_t)0x00000001U) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002U) /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON ((uint32_t)0x00000100U) /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY ((uint32_t)0x00000200U) /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP ((uint32_t)0x00000400U) /*!< External Low Speed oscillator Bypass */
-#define RCC_CSR_LSEDRV ((uint32_t)0x00001800) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800) /*!< Bit 0 */
-#define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CSR_LSEDRV ((uint32_t)0x00001800U) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
+#define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
-#define RCC_CSR_LSECSSON ((uint32_t)0x00002000) /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD ((uint32_t)0x00004000) /*!< External Low Speed oscillator CSS Detected */
+#define RCC_CSR_LSECSSON ((uint32_t)0x00002000U) /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD ((uint32_t)0x00004000U) /*!< External Low Speed oscillator CSS Detected */
/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define RCC_CSR_RTCSEL ((uint32_t)0x00030000U) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
+#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
-#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000U) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000U) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000U) /*!< HSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCEN ((uint32_t)0x00040000) /*!< RTC clock enable */
-#define RCC_CSR_RTCRST ((uint32_t)0x00080000) /*!< RTC software reset */
-
-#define RCC_CSR_RMVF ((uint32_t)0x00800000) /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF ((uint32_t)0x01000000) /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBL ((uint32_t)0x02000000) /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+#define RCC_CSR_RTCEN ((uint32_t)0x00040000U) /*!< RTC clock enable */
+#define RCC_CSR_RTCRST ((uint32_t)0x00080000U) /*!< RTC software reset */
+
+#define RCC_CSR_RMVF ((uint32_t)0x00800000U) /*!< Remove reset flag */
+#define RCC_CSR_FWRSTF ((uint32_t)0x01000000U) /*!< Mifare Firewall reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000U) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000U) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U) /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
/******************************************************************************/
/* */
@@ -2480,15 +2694,15 @@
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
-#define RNG_CR_RNGEN ((uint32_t)0x00000004)
-#define RNG_CR_IE ((uint32_t)0x00000008)
+#define RNG_CR_RNGEN ((uint32_t)0x00000004U)
+#define RNG_CR_IE ((uint32_t)0x00000008U)
/******************** Bits definition for RNG_SR register *******************/
-#define RNG_SR_DRDY ((uint32_t)0x00000001)
-#define RNG_SR_CECS ((uint32_t)0x00000002)
-#define RNG_SR_SECS ((uint32_t)0x00000004)
-#define RNG_SR_CEIS ((uint32_t)0x00000020)
-#define RNG_SR_SEIS ((uint32_t)0x00000040)
+#define RNG_SR_DRDY ((uint32_t)0x00000001U)
+#define RNG_SR_CECS ((uint32_t)0x00000002U)
+#define RNG_SR_SECS ((uint32_t)0x00000004U)
+#define RNG_SR_CEIS ((uint32_t)0x00000020U)
+#define RNG_SR_SEIS ((uint32_t)0x00000040U)
/******************************************************************************/
/* */
@@ -2496,339 +2710,357 @@
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
-#define RTC_TR_PM ((uint32_t)0x00400000) /*!< */
-#define RTC_TR_HT ((uint32_t)0x00300000) /*!< */
-#define RTC_TR_HT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_TR_HT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_TR_HU ((uint32_t)0x000F0000) /*!< */
-#define RTC_TR_HU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_TR_HU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_TR_HU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_TR_HU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_TR_MNT ((uint32_t)0x00007000) /*!< */
-#define RTC_TR_MNT_0 ((uint32_t)0x00001000) /*!< */
-#define RTC_TR_MNT_1 ((uint32_t)0x00002000) /*!< */
-#define RTC_TR_MNT_2 ((uint32_t)0x00004000) /*!< */
-#define RTC_TR_MNU ((uint32_t)0x00000F00) /*!< */
-#define RTC_TR_MNU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TR_MNU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TR_MNU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TR_MNU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_TR_ST ((uint32_t)0x00000070) /*!< */
-#define RTC_TR_ST_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_TR_ST_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_TR_ST_2 ((uint32_t)0x00000040) /*!< */
-#define RTC_TR_SU ((uint32_t)0x0000000F) /*!< */
-#define RTC_TR_SU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_TR_SU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_TR_SU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_TR_SU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_TR_PM ((uint32_t)0x00400000U) /*!< */
+#define RTC_TR_HT ((uint32_t)0x00300000U) /*!< */
+#define RTC_TR_HT_0 ((uint32_t)0x00100000U) /*!< */
+#define RTC_TR_HT_1 ((uint32_t)0x00200000U) /*!< */
+#define RTC_TR_HU ((uint32_t)0x000F0000U) /*!< */
+#define RTC_TR_HU_0 ((uint32_t)0x00010000U) /*!< */
+#define RTC_TR_HU_1 ((uint32_t)0x00020000U) /*!< */
+#define RTC_TR_HU_2 ((uint32_t)0x00040000U) /*!< */
+#define RTC_TR_HU_3 ((uint32_t)0x00080000U) /*!< */
+#define RTC_TR_MNT ((uint32_t)0x00007000U) /*!< */
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000U) /*!< */
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000U) /*!< */
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000U) /*!< */
+#define RTC_TR_MNU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_TR_ST ((uint32_t)0x00000070U) /*!< */
+#define RTC_TR_ST_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_TR_ST_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_TR_ST_2 ((uint32_t)0x00000040U) /*!< */
+#define RTC_TR_SU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_TR_SU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_TR_SU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_TR_SU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_TR_SU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_DR register *******************/
-#define RTC_DR_YT ((uint32_t)0x00F00000) /*!< */
-#define RTC_DR_YT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_DR_YT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_DR_YT_2 ((uint32_t)0x00400000) /*!< */
-#define RTC_DR_YT_3 ((uint32_t)0x00800000) /*!< */
-#define RTC_DR_YU ((uint32_t)0x000F0000) /*!< */
-#define RTC_DR_YU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_DR_YU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_DR_YU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_DR_YU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_DR_WDU ((uint32_t)0x0000E000) /*!< */
-#define RTC_DR_WDU_0 ((uint32_t)0x00002000) /*!< */
-#define RTC_DR_WDU_1 ((uint32_t)0x00004000) /*!< */
-#define RTC_DR_WDU_2 ((uint32_t)0x00008000) /*!< */
-#define RTC_DR_MT ((uint32_t)0x00001000) /*!< */
-#define RTC_DR_MU ((uint32_t)0x00000F00) /*!< */
-#define RTC_DR_MU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_DR_MU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_DR_MU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_DR_MU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_DR_DT ((uint32_t)0x00000030) /*!< */
-#define RTC_DR_DT_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_DR_DT_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_DR_DU ((uint32_t)0x0000000F) /*!< */
-#define RTC_DR_DU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_DR_DU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_DR_DU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_DR_DU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_DR_YT ((uint32_t)0x00F00000U) /*!< */
+#define RTC_DR_YT_0 ((uint32_t)0x00100000U) /*!< */
+#define RTC_DR_YT_1 ((uint32_t)0x00200000U) /*!< */
+#define RTC_DR_YT_2 ((uint32_t)0x00400000U) /*!< */
+#define RTC_DR_YT_3 ((uint32_t)0x00800000U) /*!< */
+#define RTC_DR_YU ((uint32_t)0x000F0000U) /*!< */
+#define RTC_DR_YU_0 ((uint32_t)0x00010000U) /*!< */
+#define RTC_DR_YU_1 ((uint32_t)0x00020000U) /*!< */
+#define RTC_DR_YU_2 ((uint32_t)0x00040000U) /*!< */
+#define RTC_DR_YU_3 ((uint32_t)0x00080000U) /*!< */
+#define RTC_DR_WDU ((uint32_t)0x0000E000U) /*!< */
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000U) /*!< */
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000U) /*!< */
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000U) /*!< */
+#define RTC_DR_MT ((uint32_t)0x00001000U) /*!< */
+#define RTC_DR_MU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_DR_MU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_DR_MU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_DR_MU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_DR_MU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_DR_DT ((uint32_t)0x00000030U) /*!< */
+#define RTC_DR_DT_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_DR_DT_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_DR_DU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_DR_DU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_DR_DU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_DR_DU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_DR_DU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_CR register *******************/
-#define RTC_CR_COE ((uint32_t)0x00800000) /*!< */
-#define RTC_CR_OSEL ((uint32_t)0x00600000) /*!< */
-#define RTC_CR_OSEL_0 ((uint32_t)0x00200000) /*!< */
-#define RTC_CR_OSEL_1 ((uint32_t)0x00400000) /*!< */
-#define RTC_CR_POL ((uint32_t)0x00100000) /*!< */
-#define RTC_CR_COSEL ((uint32_t)0x00080000) /*!< */
-#define RTC_CR_BCK ((uint32_t)0x00040000) /*!< */
-#define RTC_CR_SUB1H ((uint32_t)0x00020000) /*!< */
-#define RTC_CR_ADD1H ((uint32_t)0x00010000) /*!< */
-#define RTC_CR_TSIE ((uint32_t)0x00008000) /*!< */
-#define RTC_CR_WUTIE ((uint32_t)0x00004000) /*!< */
-#define RTC_CR_ALRBIE ((uint32_t)0x00002000) /*!< */
-#define RTC_CR_ALRAIE ((uint32_t)0x00001000) /*!< */
-#define RTC_CR_TSE ((uint32_t)0x00000800) /*!< */
-#define RTC_CR_WUTE ((uint32_t)0x00000400) /*!< */
-#define RTC_CR_ALRBE ((uint32_t)0x00000200) /*!< */
-#define RTC_CR_ALRAE ((uint32_t)0x00000100) /*!< */
-#define RTC_CR_FMT ((uint32_t)0x00000040) /*!< */
-#define RTC_CR_BYPSHAD ((uint32_t)0x00000020) /*!< */
-#define RTC_CR_REFCKON ((uint32_t)0x00000010) /*!< */
-#define RTC_CR_TSEDGE ((uint32_t)0x00000008) /*!< */
-#define RTC_CR_WUCKSEL ((uint32_t)0x00000007) /*!< */
-#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) /*!< */
+#define RTC_CR_COE ((uint32_t)0x00800000U) /*!< */
+#define RTC_CR_OSEL ((uint32_t)0x00600000U) /*!< */
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000U) /*!< */
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000U) /*!< */
+#define RTC_CR_POL ((uint32_t)0x00100000U) /*!< */
+#define RTC_CR_COSEL ((uint32_t)0x00080000U) /*!< */
+#define RTC_CR_BCK ((uint32_t)0x00040000U) /*!< */
+#define RTC_CR_SUB1H ((uint32_t)0x00020000U) /*!< */
+#define RTC_CR_ADD1H ((uint32_t)0x00010000U) /*!< */
+#define RTC_CR_TSIE ((uint32_t)0x00008000U) /*!< */
+#define RTC_CR_WUTIE ((uint32_t)0x00004000U) /*!< */
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000U) /*!< */
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000U) /*!< */
+#define RTC_CR_TSE ((uint32_t)0x00000800U) /*!< */
+#define RTC_CR_WUTE ((uint32_t)0x00000400U) /*!< */
+#define RTC_CR_ALRBE ((uint32_t)0x00000200U) /*!< */
+#define RTC_CR_ALRAE ((uint32_t)0x00000100U) /*!< */
+#define RTC_CR_FMT ((uint32_t)0x00000040U) /*!< */
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020U) /*!< */
+#define RTC_CR_REFCKON ((uint32_t)0x00000010U) /*!< */
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008U) /*!< */
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007U) /*!< */
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U) /*!< */
/******************** Bits definition for RTC_ISR register ******************/
-#define RTC_ISR_RECALPF ((uint32_t)0x00010000) /*!< */
-#define RTC_ISR_TAMP2F ((uint32_t)0x00004000) /*!< */
-#define RTC_ISR_TAMP1F ((uint32_t)0x00002000) /*!< */
-#define RTC_ISR_TSOVF ((uint32_t)0x00001000) /*!< */
-#define RTC_ISR_TSF ((uint32_t)0x00000800) /*!< */
-#define RTC_ISR_WUTF ((uint32_t)0x00000400) /*!< */
-#define RTC_ISR_ALRBF ((uint32_t)0x00000200) /*!< */
-#define RTC_ISR_ALRAF ((uint32_t)0x00000100) /*!< */
-#define RTC_ISR_INIT ((uint32_t)0x00000080) /*!< */
-#define RTC_ISR_INITF ((uint32_t)0x00000040) /*!< */
-#define RTC_ISR_RSF ((uint32_t)0x00000020) /*!< */
-#define RTC_ISR_INITS ((uint32_t)0x00000010) /*!< */
-#define RTC_ISR_SHPF ((uint32_t)0x00000008) /*!< */
-#define RTC_ISR_WUTWF ((uint32_t)0x00000004) /*!< */
-#define RTC_ISR_ALRBWF ((uint32_t)0x00000002) /*!< */
-#define RTC_ISR_ALRAWF ((uint32_t)0x00000001) /*!< */
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000U) /*!< */
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000U) /*!< */
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000U) /*!< */
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000U) /*!< */
+#define RTC_ISR_TSF ((uint32_t)0x00000800U) /*!< */
+#define RTC_ISR_WUTF ((uint32_t)0x00000400U) /*!< */
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200U) /*!< */
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100U) /*!< */
+#define RTC_ISR_INIT ((uint32_t)0x00000080U) /*!< */
+#define RTC_ISR_INITF ((uint32_t)0x00000040U) /*!< */
+#define RTC_ISR_RSF ((uint32_t)0x00000020U) /*!< */
+#define RTC_ISR_INITS ((uint32_t)0x00000010U) /*!< */
+#define RTC_ISR_SHPF ((uint32_t)0x00000008U) /*!< */
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004U) /*!< */
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002U) /*!< */
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001U) /*!< */
/******************** Bits definition for RTC_PRER register *****************/
-#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) /*!< */
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) /*!< */
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U) /*!< */
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU) /*!< */
/******************** Bits definition for RTC_WUTR register *****************/
-#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU)
/******************** Bits definition for RTC_ALRMAR register ***************/
-#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) /*!< */
-#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) /*!< */
-#define RTC_ALRMAR_DT ((uint32_t)0x30000000) /*!< */
-#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) /*!< */
-#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) /*!< */
-#define RTC_ALRMAR_DU ((uint32_t)0x0F000000) /*!< */
-#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) /*!< */
-#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) /*!< */
-#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) /*!< */
-#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) /*!< */
-#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) /*!< */
-#define RTC_ALRMAR_PM ((uint32_t)0x00400000) /*!< */
-#define RTC_ALRMAR_HT ((uint32_t)0x00300000) /*!< */
-#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_ALRMAR_HU ((uint32_t)0x000F0000) /*!< */
-#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) /*!< */
-#define RTC_ALRMAR_MNT ((uint32_t)0x00007000) /*!< */
-#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) /*!< */
-#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) /*!< */
-#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) /*!< */
-#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) /*!< */
-#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) /*!< */
-#define RTC_ALRMAR_ST ((uint32_t)0x00000070) /*!< */
-#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) /*!< */
-#define RTC_ALRMAR_SU ((uint32_t)0x0000000F) /*!< */
-#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U) /*!< */
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U) /*!< */
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000U) /*!< */
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U) /*!< */
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U) /*!< */
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000U) /*!< */
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U) /*!< */
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U) /*!< */
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U) /*!< */
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U) /*!< */
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U) /*!< */
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000U) /*!< */
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000U) /*!< */
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U) /*!< */
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U) /*!< */
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000U) /*!< */
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U) /*!< */
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U) /*!< */
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U) /*!< */
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U) /*!< */
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U) /*!< */
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000U) /*!< */
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U) /*!< */
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U) /*!< */
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U) /*!< */
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U) /*!< */
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070U) /*!< */
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U) /*!< */
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_ALRMBR register ***************/
-#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) /*!< */
-#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) /*!< */
-#define RTC_ALRMBR_DT ((uint32_t)0x30000000) /*!< */
-#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) /*!< */
-#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) /*!< */
-#define RTC_ALRMBR_DU ((uint32_t)0x0F000000) /*!< */
-#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) /*!< */
-#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) /*!< */
-#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) /*!< */
-#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) /*!< */
-#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) /*!< */
-#define RTC_ALRMBR_PM ((uint32_t)0x00400000) /*!< */
-#define RTC_ALRMBR_HT ((uint32_t)0x00300000) /*!< */
-#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_ALRMBR_HU ((uint32_t)0x000F0000) /*!< */
-#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) /*!< */
-#define RTC_ALRMBR_MNT ((uint32_t)0x00007000) /*!< */
-#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) /*!< */
-#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) /*!< */
-#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) /*!< */
-#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) /*!< */
-#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) /*!< */
-#define RTC_ALRMBR_ST ((uint32_t)0x00000070) /*!< */
-#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) /*!< */
-#define RTC_ALRMBR_SU ((uint32_t)0x0000000F) /*!< */
-#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U) /*!< */
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U) /*!< */
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000U) /*!< */
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U) /*!< */
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U) /*!< */
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000U) /*!< */
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U) /*!< */
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U) /*!< */
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U) /*!< */
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U) /*!< */
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U) /*!< */
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000U) /*!< */
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000U) /*!< */
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U) /*!< */
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U) /*!< */
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000U) /*!< */
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U) /*!< */
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U) /*!< */
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U) /*!< */
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U) /*!< */
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U) /*!< */
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000U) /*!< */
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U) /*!< */
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U) /*!< */
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U) /*!< */
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U) /*!< */
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070U) /*!< */
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U) /*!< */
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_WPR register ******************/
-#define RTC_WPR_KEY ((uint32_t)0x000000FF) /*!< */
+#define RTC_WPR_KEY ((uint32_t)0x000000FFU) /*!< */
/******************** Bits definition for RTC_SSR register ******************/
-#define RTC_SSR_SS ((uint32_t)0x0000FFFF) /*!< */
+#define RTC_SSR_SS ((uint32_t)0x0000FFFFU) /*!< */
/******************** Bits definition for RTC_SHIFTR register ***************/
-#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) /*!< */
-#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) /*!< */
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU) /*!< */
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U) /*!< */
/******************** Bits definition for RTC_TSTR register *****************/
-#define RTC_TSTR_PM ((uint32_t)0x00400000) /*!< */
-#define RTC_TSTR_HT ((uint32_t)0x00300000) /*!< */
-#define RTC_TSTR_HT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_TSTR_HT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_TSTR_HU ((uint32_t)0x000F0000) /*!< */
-#define RTC_TSTR_HU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_TSTR_HU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_TSTR_HU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_TSTR_HU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_TSTR_MNT ((uint32_t)0x00007000) /*!< */
-#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) /*!< */
-#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) /*!< */
-#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) /*!< */
-#define RTC_TSTR_MNU ((uint32_t)0x00000F00) /*!< */
-#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_TSTR_ST ((uint32_t)0x00000070) /*!< */
-#define RTC_TSTR_ST_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_TSTR_ST_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_TSTR_ST_2 ((uint32_t)0x00000040) /*!< */
-#define RTC_TSTR_SU ((uint32_t)0x0000000F) /*!< */
-#define RTC_TSTR_SU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_TSTR_SU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_TSTR_SU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_TSTR_SU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_TSTR_PM ((uint32_t)0x00400000U) /*!< */
+#define RTC_TSTR_HT ((uint32_t)0x00300000U) /*!< */
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000U) /*!< */
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000U) /*!< */
+#define RTC_TSTR_HU ((uint32_t)0x000F0000U) /*!< */
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000U) /*!< */
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000U) /*!< */
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000U) /*!< */
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000U) /*!< */
+#define RTC_TSTR_MNT ((uint32_t)0x00007000U) /*!< */
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U) /*!< */
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U) /*!< */
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U) /*!< */
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_TSTR_ST ((uint32_t)0x00000070U) /*!< */
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040U) /*!< */
+#define RTC_TSTR_SU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_TSDR register *****************/
-#define RTC_TSDR_WDU ((uint32_t)0x0000E000) /*!< */
-#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) /*!< */
-#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) /*!< */
-#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) /*!< */
-#define RTC_TSDR_MT ((uint32_t)0x00001000) /*!< */
-#define RTC_TSDR_MU ((uint32_t)0x00000F00) /*!< */
-#define RTC_TSDR_MU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TSDR_MU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TSDR_MU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TSDR_MU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_TSDR_DT ((uint32_t)0x00000030) /*!< */
-#define RTC_TSDR_DT_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_TSDR_DT_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_TSDR_DU ((uint32_t)0x0000000F) /*!< */
-#define RTC_TSDR_DU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_TSDR_DU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_TSDR_DU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_TSDR_DU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000U) /*!< */
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U) /*!< */
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U) /*!< */
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U) /*!< */
+#define RTC_TSDR_MT ((uint32_t)0x00001000U) /*!< */
+#define RTC_TSDR_MU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_TSDR_DT ((uint32_t)0x00000030U) /*!< */
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_TSDR_DU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_TSSSR register ****************/
-#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
-
-/******************** Bits definition for RTC_CAL register *****************/
-#define RTC_CAL_CALP ((uint32_t)0x00008000) /*!< */
-#define RTC_CAL_CALW8 ((uint32_t)0x00004000) /*!< */
-#define RTC_CAL_CALW16 ((uint32_t)0x00002000) /*!< */
-#define RTC_CAL_CALM ((uint32_t)0x000001FF) /*!< */
-#define RTC_CAL_CALM_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_CAL_CALM_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_CAL_CALM_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_CAL_CALM_3 ((uint32_t)0x00000008) /*!< */
-#define RTC_CAL_CALM_4 ((uint32_t)0x00000010) /*!< */
-#define RTC_CAL_CALM_5 ((uint32_t)0x00000020) /*!< */
-#define RTC_CAL_CALM_6 ((uint32_t)0x00000040) /*!< */
-#define RTC_CAL_CALM_7 ((uint32_t)0x00000080) /*!< */
-#define RTC_CAL_CALM_8 ((uint32_t)0x00000100) /*!< */
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU)
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000U) /*!< */
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000U) /*!< */
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000U) /*!< */
+#define RTC_CALR_CALM ((uint32_t)0x000001FFU) /*!< */
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008U) /*!< */
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010U) /*!< */
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020U) /*!< */
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040U) /*!< */
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080U) /*!< */
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100U) /*!< */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
/******************** Bits definition for RTC_TAMPCR register ****************/
-#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000) /*!< */
-#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000) /*!< */
-#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000) /*!< */
-#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000) /*!< */
-#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000) /*!< */
-#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000) /*!< */
-#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000) /*!< */
-#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000) /*!< */
-#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000) /*!< */
-#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000) /*!< */
-#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800) /*!< */
-#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800) /*!< */
-#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000) /*!< */
-#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700) /*!< */
-#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080) /*!< */
-#define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010) /*!< */
-#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008) /*!< */
-#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004) /*!< */
-#define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002) /*!< */
-#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001) /*!< */
+#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U) /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U) /*!< */
+#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U) /*!< */
+#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000U) /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000U) /*!< */
+#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000U) /*!< */
+#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U) /*!< */
+#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U) /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U) /*!< */
+#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U) /*!< */
+#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U) /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U) /*!< */
+#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U) /*!< */
+#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U) /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U) /*!< */
+#define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U) /*!< */
+#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U) /*!< */
+#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U) /*!< */
+#define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002U) /*!< */
+#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001U) /*!< */
/******************** Bits definition for RTC_ALRMASSR register *************/
-#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU)
/******************** Bits definition for RTC_ALRMBSSR register *************/
-#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU)
/******************** Bits definition for RTC_OR register ****************/
-#define RTC_OR_OUT_RMP ((uint32_t)0x00000002) /*!< */
-#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001) /*!< */
-
-/* Bit names aliases maintained for legacy */
+#define RTC_OR_OUT_RMP ((uint32_t)0x00000002U) /*!< */
+#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U) /*!< */
+
+/* Legacy defines */
#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
/******************** Bits definition for RTC_BKP0R register ****************/
-#define RTC_BKP0R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFFU) /*!< */
/******************** Bits definition for RTC_BKP1R register ****************/
-#define RTC_BKP1R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFFU) /*!< */
/******************** Bits definition for RTC_BKP2R register ****************/
-#define RTC_BKP2R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFFU) /*!< */
/******************** Bits definition for RTC_BKP3R register ****************/
-#define RTC_BKP3R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFFU) /*!< */
/******************** Bits definition for RTC_BKP4R register ****************/
-#define RTC_BKP4R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFFU) /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER ((uint32_t)0x00000005U) /*!< */
/******************************************************************************/
/* */
@@ -2836,75 +3068,75 @@
/* */
/******************************************************************************/
/******************* Bit definition for SPI_CR1 register ********************/
-#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
-#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
-#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
-#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
-#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
-#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
-#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
-#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+#define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!< Master Selection */
+#define SPI_CR1_BR ((uint32_t)0x00000038U) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
+#define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!< Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800U) /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!< Bidirectional data mode enable */
/******************* Bit definition for SPI_CR2 register ********************/
-#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
-#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */
/******************** Bit definition for SPI_SR register ********************/
-#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
-#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
-#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
-#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
-#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
-#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
-#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
+#define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100U) /*!< TI frame format error */
/******************** Bit definition for SPI_DR register ********************/
-#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
+#define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!< Data Register */
/******************* Bit definition for SPI_CRCPR register ******************/
-#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!< CRC polynomial register */
/****************** Bit definition for SPI_RXCRCR register ******************/
-#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!< Rx CRC Register */
/****************** Bit definition for SPI_TXCRCR register ******************/
-#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!< Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register *****************/
-#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
-#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
-#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001U) /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006U) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002U) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004U) /*!<Bit 1 */
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008U) /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030U) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080U) /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300U) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400U) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800U) /*!<I2S mode selection */
/****************** Bit definition for SPI_I2SPR register *******************/
-#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FFU) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100U) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200U) /*!<Master Clock Output Enable */
/******************************************************************************/
/* */
@@ -2912,183 +3144,183 @@
/* */
/******************************************************************************/
/***************** Bit definition for SYSCFG_CFGR1 register ****************/
-#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
-#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
-#define SYSCFG_CFGR1_BOOT_MODE ((uint32_t)0x00000300) /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MOD_0 ((uint32_t)0x00000100) /*!< SYSCFG_Boot mode Config Bit 0 */
-#define SYSCFG_CFGR1_BOOT_MODE_1 ((uint32_t)0x00000200) /*!< SYSCFG_Boot mode Config Bit 1 */
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003U) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001U) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002U) /*!< SYSCFG_Memory Remap Config Bit 1 */
+#define SYSCFG_CFGR1_BOOT_MODE ((uint32_t)0x00000300U) /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 ((uint32_t)0x00000100U) /*!< SYSCFG_Boot mode Config Bit 0 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 ((uint32_t)0x00000200U) /*!< SYSCFG_Boot mode Config Bit 1 */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
-#define SYSCFG_CFGR2_FWDISEN ((uint32_t)0x00000001) /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_CAPA ((uint32_t)0x0000000E) /*!< Connection of internal Vlcd rail to external capacitors */
-#define SYSCFG_CFGR2_CAPA_0 ((uint32_t)0x00000002)
-#define SYSCFG_CFGR2_CAPA_1 ((uint32_t)0x00000004)
-#define SYSCFG_CFGR2_CAPA_2 ((uint32_t)0x00000008)
-#define SYSCFG_CFGR2_I2C_PB6_FMP ((uint32_t)0x00000100) /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP ((uint32_t)0x00000200) /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP ((uint32_t)0x00000400) /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP ((uint32_t)0x00000800) /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP ((uint32_t)0x00001000) /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP ((uint32_t)0x00002000) /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR2_FWDISEN ((uint32_t)0x00000001U) /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_CAPA ((uint32_t)0x0000000EU) /*!< Connection of internal Vlcd rail to external capacitors */
+#define SYSCFG_CFGR2_CAPA_0 ((uint32_t)0x00000002U)
+#define SYSCFG_CFGR2_CAPA_1 ((uint32_t)0x00000004U)
+#define SYSCFG_CFGR2_CAPA_2 ((uint32_t)0x00000008U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP ((uint32_t)0x00000100U) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP ((uint32_t)0x00000200U) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP ((uint32_t)0x00000400U) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP ((uint32_t)0x00000800U) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP ((uint32_t)0x00001000U) /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR2_I2C2_FMP ((uint32_t)0x00002000U) /*!< I2C2 Fast mode plus */
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
-#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000FU) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0U) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00U) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000U) /*!< EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
-#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005) /*!< PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005U) /*!< PH[0] pin */
/**
* @brief EXTI1 configuration
*/
-#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050) /*!< PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050U) /*!< PH[1] pin */
/**
* @brief EXTI2 configuration
*/
-#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300U) /*!< PD[2] pin */
/**
* @brief EXTI3 configuration
*/
-#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000U) /*!< PC[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
-#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000FU) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0U) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00U) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000U) /*!< EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
-#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002U) /*!< PC[4] pin */
/**
* @brief EXTI5 configuration
*/
-#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020U) /*!< PC[5] pin */
/**
* @brief EXTI6 configuration
*/
-#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200U) /*!< PC[6] pin */
/**
* @brief EXTI7 configuration
*/
-#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000U) /*!< PC[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
-#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000FU) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0U) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00U) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000U) /*!< EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
-#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002U) /*!< PC[8] pin */
/**
* @brief EXTI9 configuration
*/
-#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020U) /*!< PC[9] pin */
/**
* @brief EXTI10 configuration
*/
-#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200U) /*!< PC[10] pin */
/**
* @brief EXTI11 configuration
*/
-#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000U) /*!< PC[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
-#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000FU) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0U) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00U) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000U) /*!< EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
-#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002U) /*!< PC[12] pin */
/**
* @brief EXTI13 configuration
*/
-#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020U) /*!< PC[13] pin */
/**
* @brief EXTI14 configuration
*/
-#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200U) /*!< PC[14] pin */
/**
* @brief EXTI15 configuration
*/
-#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000U) /*!< PC[15] pin */
/***************** Bit definition for SYSCFG_CFGR3 register ****************/
-#define SYSCFG_CFGR3_EN_VREFINT ((uint32_t)0x00000001) /*!< Vref Enable bit*/
-#define SYSCFG_CFGR3_VREF_OUT ((uint32_t)0x00000030) /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define SYSCFG_CFGR3_VREF_OUT_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC ((uint32_t)0x00000100) /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC ((uint32_t)0x00000200) /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ((uint32_t)0x00001000) /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_ENREF_HSI48 ((uint32_t)0x00002000) /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
-#define SYSCFG_CFGR3_REF_HSI48_RDYF ((uint32_t)0x04000000) /*!< VREFINT for 48 MHz RC oscillator ready flag */
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF ((uint32_t)0x08000000) /*!< Sensor for ADC ready flag */
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF ((uint32_t)0x10000000) /*!< VREFINT for ADC ready flag */
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF ((uint32_t)0x20000000) /*!< VREFINT for comparator ready flag */
-#define SYSCFG_CFGR3_VREFINT_RDYF ((uint32_t)0x40000000) /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK ((uint32_t)0x80000000) /*!< CFGR3 lock bit */
-
-/* Bit names aliases maintained for legacy */
+#define SYSCFG_CFGR3_EN_VREFINT ((uint32_t)0x00000001U) /*!< Vref Enable bit*/
+#define SYSCFG_CFGR3_VREF_OUT ((uint32_t)0x00000030U) /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
+#define SYSCFG_CFGR3_VREF_OUT_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC ((uint32_t)0x00000100U) /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC ((uint32_t)0x00000200U) /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ((uint32_t)0x00001000U) /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_ENREF_HSI48 ((uint32_t)0x00002000U) /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
+#define SYSCFG_CFGR3_REF_HSI48_RDYF ((uint32_t)0x04000000U) /*!< VREFINT for 48 MHz RC oscillator ready flag */
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF ((uint32_t)0x08000000U) /*!< Sensor for ADC ready flag */
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF ((uint32_t)0x10000000U) /*!< VREFINT for ADC ready flag */
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF ((uint32_t)0x20000000U) /*!< VREFINT for comparator ready flag */
+#define SYSCFG_CFGR3_VREFINT_RDYF ((uint32_t)0x40000000U) /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK ((uint32_t)0x80000000U) /*!< CFGR3 lock bit */
+
+/* Legacy defines */
#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
@@ -3102,315 +3334,285 @@
/* Timers (TIM) */
/* */
/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
/******************* Bit definition for TIM_CR1 register ********************/
-#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
-#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
-#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
-#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
-#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
-
-#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-
-#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_CR1_CEN ((uint32_t)0x00000001U) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002U) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004U) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008U) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010U) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060U) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080U) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300U) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
/******************* Bit definition for TIM_CR2 register ********************/
-#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-
-#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
-#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008U) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070U) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080U) /*!<TI1 Selection */
/******************* Bit definition for TIM_SMCR register *******************/
-#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-
-#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-
-#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-
-#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-
-#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
-#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+#define TIM_SMCR_SMS ((uint32_t)0x00000007U) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008U) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070U) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080U) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00U) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000U) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000U) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000U) /*!<External trigger polarity */
/******************* Bit definition for TIM_DIER register *******************/
-#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+#define TIM_DIER_UIE ((uint32_t)0x00000001U) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040U) /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100U) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200U) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400U) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800U) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000U) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000U) /*!<Trigger DMA request enable */
/******************** Bit definition for TIM_SR register ********************/
-#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
-#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
-#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_UIF ((uint32_t)0x00000001U) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040U) /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200U) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400U) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000U) /*!<Capture/Compare 4 Overcapture Flag */
/******************* Bit definition for TIM_EGR register ********************/
-#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
-#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
-#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+#define TIM_EGR_UG ((uint32_t)0x00000001U) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002U) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004U) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008U) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010U) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040U) /*!<Trigger Generation */
/****************** Bit definition for TIM_CCMR1 register *******************/
-#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003U) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004U) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008U) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00000070U) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080U) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300U) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400U) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800U) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x00007000U) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000U) /*!<Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
-#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-
-#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000CU) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0U) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00U) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000U) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
/****************** Bit definition for TIM_CCMR2 register *******************/
-#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003U) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004U) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008U) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00000070U) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080U) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300U) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400U) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800U) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x00007000U) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000U) /*!<Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
-#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-
-#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000CU) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0U) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00U) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000U) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
/******************* Bit definition for TIM_CCER register *******************/
-#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC1E ((uint32_t)0x00000001U) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002U) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008U) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010U) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020U) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080U) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100U) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200U) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000U) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000U) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000U) /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
-#define TIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!<Counter Value */
+#define TIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!<Counter Value */
/******************* Bit definition for TIM_PSC register ********************/
-#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFFU) /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
-#define TIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!<actual auto-reload Value */
-
-/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+#define TIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_CCR1 register *******************/
-#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
-#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
-#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
-#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
-
-/******************* Bit definition for TIM_BDTR register *******************/
-#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
-
-#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-
-#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
-#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
-#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
-#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_DCR register ********************/
-#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-
-#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define TIM_DCR_DBA ((uint32_t)0x0000001FU) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00U) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
/******************* Bit definition for TIM_DMAR register *******************/
-#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFFU) /*!<DMA register for burst accesses */
/******************* Bit definition for TIM_OR register *********************/
-#define TIM2_OR_ETR_RMP ((uint32_t)0x00000007) /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM2_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM2_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM2_OR_ETR_RMP ((uint32_t)0x00000007U) /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM2_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM2_OR_ETR_RMP_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
#define TIM2_OR_TI4_RMP ((uint32_t)0x0000018) /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0 ((uint32_t)0x00000008) /*!<Bit 0 */
-#define TIM2_OR_TI4_RMP_1 ((uint32_t)0x00000010) /*!<Bit 1 */
-
-#define TIM21_OR_ETR_RMP ((uint32_t)0x00000003) /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM21_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM21_OR_TI1_RMP ((uint32_t)0x0000001C) /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define TIM21_OR_TI1_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
-#define TIM21_OR_TI1_RMP_2 ((uint32_t)0x00000010) /*!<Bit 2 */
-#define TIM21_OR_TI2_RMP ((uint32_t)0x00000020) /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP ((uint32_t)0x00000003) /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM22_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM22_OR_TI1_RMP ((uint32_t)0x0000000C) /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+#define TIM2_OR_TI4_RMP_0 ((uint32_t)0x00000008U) /*!<Bit 0 */
+#define TIM2_OR_TI4_RMP_1 ((uint32_t)0x00000010U) /*!<Bit 1 */
+
+#define TIM21_OR_ETR_RMP ((uint32_t)0x00000003U) /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM21_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM21_OR_TI1_RMP ((uint32_t)0x0000001CU) /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
+#define TIM21_OR_TI1_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
+#define TIM21_OR_TI1_RMP_2 ((uint32_t)0x00000010U) /*!<Bit 2 */
+#define TIM21_OR_TI2_RMP ((uint32_t)0x00000020U) /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP ((uint32_t)0x00000003U) /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM22_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM22_OR_TI1_RMP ((uint32_t)0x0000000CU) /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
+#define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
/******************************************************************************/
@@ -3419,375 +3621,381 @@
/* */
/******************************************************************************/
/******************* Bit definition for TSC_CR register *********************/
-#define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
-#define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
-#define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
-
-#define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
-
-#define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-
-#define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
-#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
-#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
-#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
-#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
-#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
-#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
-
-#define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-
-#define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
-#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
-#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
+#define TSC_CR_TSCE ((uint32_t)0x00000001U) /*!<Touch sensing controller enable */
+#define TSC_CR_START ((uint32_t)0x00000002U) /*!<Start acquisition */
+#define TSC_CR_AM ((uint32_t)0x00000004U) /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL ((uint32_t)0x00000008U) /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF ((uint32_t)0x00000010U) /*!<IO default mode */
+
+#define TSC_CR_MCV ((uint32_t)0x000000E0U) /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
+#define TSC_CR_MCV_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
+#define TSC_CR_MCV_2 ((uint32_t)0x00000080U) /*!<Bit 2 */
+
+#define TSC_CR_PGPSC ((uint32_t)0x00007000U) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
+
+#define TSC_CR_SSPSC ((uint32_t)0x00008000U) /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE ((uint32_t)0x00010000U) /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD ((uint32_t)0x00FE0000U) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
+#define TSC_CR_SSD_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
+#define TSC_CR_SSD_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
+#define TSC_CR_SSD_3 ((uint32_t)0x00100000U) /*!<Bit 3 */
+#define TSC_CR_SSD_4 ((uint32_t)0x00200000U) /*!<Bit 4 */
+#define TSC_CR_SSD_5 ((uint32_t)0x00400000U) /*!<Bit 5 */
+#define TSC_CR_SSD_6 ((uint32_t)0x00800000U) /*!<Bit 6 */
+
+#define TSC_CR_CTPL ((uint32_t)0x0F000000U) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
+#define TSC_CR_CTPL_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
+#define TSC_CR_CTPL_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
+#define TSC_CR_CTPL_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
+
+#define TSC_CR_CTPH ((uint32_t)0xF0000000U) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
+#define TSC_CR_CTPH_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
+#define TSC_CR_CTPH_2 ((uint32_t)0x40000000U) /*!<Bit 2 */
+#define TSC_CR_CTPH_3 ((uint32_t)0x80000000U) /*!<Bit 3 */
/******************* Bit definition for TSC_IER register ********************/
-#define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
+#define TSC_IER_EOAIE ((uint32_t)0x00000001U) /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE ((uint32_t)0x00000002U) /*!<Max count error interrupt enable */
/******************* Bit definition for TSC_ICR register ********************/
-#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
+#define TSC_ICR_EOAIC ((uint32_t)0x00000001U) /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC ((uint32_t)0x00000002U) /*!<Max count error interrupt clear */
/******************* Bit definition for TSC_ISR register ********************/
-#define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
-#define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
+#define TSC_ISR_EOAF ((uint32_t)0x00000001U) /*!<End of acquisition flag */
+#define TSC_ISR_MCEF ((uint32_t)0x00000002U) /*!<Max count error flag */
/******************* Bit definition for TSC_IOHCR register ******************/
-#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
/******************* Bit definition for TSC_IOASCR register *****************/
-#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
+#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 analog switch enable */
/******************* Bit definition for TSC_IOSCR register ******************/
-#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
+#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 sampling mode */
/******************* Bit definition for TSC_IOCCR register ******************/
-#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
+#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 channel mode */
/******************* Bit definition for TSC_IOGCSR register *****************/
-#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
+#define TSC_IOGCSR_G1E ((uint32_t)0x00000001U) /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E ((uint32_t)0x00000002U) /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E ((uint32_t)0x00000004U) /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E ((uint32_t)0x00000008U) /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E ((uint32_t)0x00000010U) /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E ((uint32_t)0x00000020U) /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E ((uint32_t)0x00000040U) /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E ((uint32_t)0x00000080U) /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S ((uint32_t)0x00010000U) /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S ((uint32_t)0x00020000U) /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S ((uint32_t)0x00040000U) /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S ((uint32_t)0x00080000U) /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S ((uint32_t)0x00100000U) /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S ((uint32_t)0x00200000U) /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S ((uint32_t)0x00400000U) /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S ((uint32_t)0x00800000U) /*!<Analog IO GROUP8 status */
/******************* Bit definition for TSC_IOGXCR register *****************/
-#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
+#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFFU) /*!<CNT[13:0] bits (Counter value) */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
/****************** Bit definition for USART_CR1 register *******************/
-#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
-#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
-#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
-#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
-#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
-#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
-#define USART_CR1_M ((uint32_t)0x10001000) /*!< Word length */
-#define USART_CR1_M_0 ((uint32_t)0x00001000) /*!< Word length - Bit 0 */
-#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
-#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
-#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
-#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
-#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
-#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
-#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
-#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
-#define USART_CR1_M_1 ((uint32_t)0x10000000) /*!< Word length - Bit 1 */
+#define USART_CR1_UE ((uint32_t)0x00000001U) /*!< USART Enable */
+#define USART_CR1_UESM ((uint32_t)0x00000002U) /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE ((uint32_t)0x00000004U) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008U) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010U) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020U) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080U) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100U) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200U) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400U) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800U) /*!< Receiver Wakeup method */
+#define USART_CR1_M ((uint32_t)0x10001000U) /*!< Word length */
+#define USART_CR1_M0 ((uint32_t)0x00001000U) /*!< Word length - Bit 0 */
+#define USART_CR1_MME ((uint32_t)0x00002000U) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000U) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000U) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000U) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000U) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000U) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000U) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000U) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000U) /*!< End of Block interrupt enable */
+#define USART_CR1_M1 ((uint32_t)0x10000000U) /*!< Word length - Bit 1 */
/****************** Bit definition for USART_CR2 register *******************/
-#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
-#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
-#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
-#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
-#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
-#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
-#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
-#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
-#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010U) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL ((uint32_t)0x00000020U) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040U) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100U) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200U) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400U) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800U) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000U) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000U) /*!< LIN mode enable */
+#define USART_CR2_SWAP ((uint32_t)0x00008000U) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000U) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000U) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000U) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000U) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000U) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000U) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000U) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000U) /*!< Address of the USART node */
/****************** Bit definition for USART_CR3 register *******************/
-#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
-#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
-#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
-#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
-#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
-#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
-#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
-#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
-#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
-#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
-#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
-#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM ((uint32_t)0x00800000) /*!< Clock Enable in Stop mode */
+#define USART_CR3_EIE ((uint32_t)0x00000001U) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002U) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004U) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008U) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010U) /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020U) /*!< SmartCard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040U) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080U) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100U) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200U) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400U) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800U) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000U) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000U) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000U) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000U) /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000U) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000U) /*!< Bit 2 */
+#define USART_CR3_WUS ((uint32_t)0x00300000U) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
+#define USART_CR3_WUFIE ((uint32_t)0x00400000U) /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM ((uint32_t)0x00800000U) /*!< Clock Enable in Stop mode */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000FU) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0U) /*!< Mantissa of USARTDIV */
/****************** Bit definition for USART_GTPR register ******************/
-#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
+#define USART_GTPR_PSC ((uint32_t)0x000000FFU) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint32_t)0x0000FF00U) /*!< GT[7:0] bits (Guard time value) */
/******************* Bit definition for USART_RTOR register *****************/
-#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFFU) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000U) /*!< Block Length */
/******************* Bit definition for USART_RQR register ******************/
-#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
-#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
+#define USART_RQR_ABRRQ ((uint32_t)0x00000001U) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint32_t)0x00000002U) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint32_t)0x00000004U) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint32_t)0x00000008U) /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ ((uint32_t)0x00000010U) /*!< Transmit data flush Request */
/******************* Bit definition for USART_ISR register ******************/
-#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
-#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
-#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
-#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
-#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
-#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
-#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
-#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
-#define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
-#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
-#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
-#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
-#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
-#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
-#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
-#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_PE ((uint32_t)0x00000001U) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002U) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004U) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008U) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010U) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020U) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040U) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080U) /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF ((uint32_t)0x00000100U) /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200U) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400U) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800U) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000U) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000U) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000U) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000U) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000U) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000U) /*!< Send Break Flag */
+#define USART_ISR_RWU ((uint32_t)0x00080000U) /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000U) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000U) /*!< Receive Enable Acknowledge Flag */
/******************* Bit definition for USART_ICR register ******************/
-#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
+#define USART_ICR_PECF ((uint32_t)0x00000001U) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002U) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004U) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008U) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010U) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040U) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF ((uint32_t)0x00000100U) /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200U) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800U) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF ((uint32_t)0x00001000U) /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000U) /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Clear Flag */
/******************* Bit definition for USART_RDR register ******************/
-#define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
+#define USART_RDR_RDR ((uint32_t)0x000001FFU) /*!< RDR[8:0] bits (Receive Data value) */
/******************* Bit definition for USART_TDR register ******************/
-#define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
+#define USART_TDR_TDR ((uint32_t)0x000001FFU) /*!< TDR[8:0] bits (Transmit Data value) */
/******************************************************************************/
/* */
/* USB Device General registers */
/* */
/******************************************************************************/
-#define USB_BASE ((uint32_t)0x40005C00) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR ((uint32_t)0x40006000) /*!< USB_IP Packet Memory Area base address */
+#define USB_BASE ((uint32_t)0x40005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR ((uint32_t)0x40006000U) /*!< USB_IP Packet Memory Area base address */
#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
@@ -3798,17 +4006,17 @@
#define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
/**************************** ISTR interrupt events *************************/
-#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
-#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
-#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
-#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
-#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
-#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
-#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
-#define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
-#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
-#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
+#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
+#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
+#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
@@ -3820,45 +4028,45 @@
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
/************************* CNTR control register bits definitions ***********/
-#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
-#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
-#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
-#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
-#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
-#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
-#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
-#define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
-#define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
-#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
-#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
-#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
-#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
-#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
+#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
+#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
+#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
/************************* BCDR control register bits definitions ***********/
-#define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
-#define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
-#define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
-#define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
-#define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
-#define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
-#define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
-#define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
-#define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
+#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
+#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
+#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
+#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
+#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
+#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
+#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
+#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
+#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
/*************************** LPM register bits definitions ******************/
-#define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
-#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
-#define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
-#define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
+#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
+#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
/******************** FNR Frame Number Register bit definitions ************/
-#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
-#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
-#define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
-#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
-#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
+#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
+#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
+#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
+#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
+#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
/******************** DADDR Device ADDRess bit definitions ****************/
-#define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
-#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
+#define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
+#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
/****************************** Endpoint register *************************/
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
@@ -3869,43 +4077,43 @@
#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
/* bit positions */
-#define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
-#define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
-#define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
-#define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
-#define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
+#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
/* EndPoint REGister MASK (no toggle fields) */
#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
/*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
-#define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
/*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************************************************************************/
@@ -3915,35 +4123,57 @@
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
-#define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */
-
-#define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */
+#define WWDG_CR_T ((uint32_t)0x0000007FU) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define WWDG_CR_T_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
+#define WWDG_CR_T_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
+#define WWDG_CR_T_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
+#define WWDG_CR_T_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
+#define WWDG_CR_T_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
+#define WWDG_CR_T_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA ((uint32_t)0x00000080U) /*!< Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
-#define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */
-
-#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */
-#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */
-
-#define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */
+#define WWDG_CFR_W ((uint32_t)0x0000007FU) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define WWDG_CFR_W_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
+#define WWDG_CFR_W_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
+#define WWDG_CFR_W_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
+#define WWDG_CFR_W_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
+#define WWDG_CFR_W_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
+#define WWDG_CFR_W_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x00000180U) /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080U) /*!< Bit 0 */
+#define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100U) /*!< Bit 1 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI ((uint32_t)0x00000200U) /*!< Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
-#define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */
+#define WWDG_SR_EWIF ((uint32_t)0x00000001U) /*!< Early Wakeup Interrupt Flag */
/**
* @}
@@ -3964,6 +4194,8 @@
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2))
+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
+
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
@@ -3987,6 +4219,12 @@
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOH))
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOH))
+
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
@@ -4016,6 +4254,34 @@
((INSTANCE) == TIM21) || \
((INSTANCE) == TIM22))
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
((INSTANCE) == TIM21) || \
@@ -4073,6 +4339,14 @@
((INSTANCE) == TIM21) || \
((INSTANCE) == TIM22))
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM2) && \
@@ -4113,11 +4387,9 @@
((INSTANCE) == USART2))
/******************** UART Instances : Wake-up from Stop mode **********************/
-
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == LPUART1))
-
/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/stm32l0xx.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/stm32l0xx.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.4.0
+ * @date 01-October-2015
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@@ -77,8 +77,16 @@
application
*/
-#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) \
- && !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && \
+ !defined (STM32L031xx) && !defined (STM32L041xx) && \
+ !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && \
+ !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) && \
+ !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && \
+ !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) \
+ /* #define STM32L011xx */
+ /* #define STM32L021xx */
+ /* #define STM32L031xx */ /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */
+ /* #define STM32L041xx */ /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */
/* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */
/* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */
#define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
@@ -106,12 +114,12 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V1.2.0
+ * @brief CMSIS Device version number V1.2.0RC1
*/
#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x01) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
@@ -124,8 +132,11 @@
/** @addtogroup Device_Included
* @{
*/
-
-#if defined(STM32L031xx)
+#if defined(STM32L011xx)
+ #include "stm32l011xx.h"
+#elif defined(STM32L021xx)
+ #include "stm32l021xx.h"
+#elif defined(STM32L031xx)
#include "stm32l031xx.h"
#elif defined(STM32L041xx)
#include "stm32l041xx.h"
@@ -205,6 +216,7 @@
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/stm32l0xx_hal_conf.h Sun Apr 17 17:45:10 2016 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/stm32l0xx_hal_conf.h Tue Apr 19 11:15:15 2016 +0100 @@ -1,16 +1,16 @@ /** ****************************************************************************** - * @file stm32l0xx_hal_conf_template.h + * @file stm32l0xx_hal_conf.h * @author MCD Application Team - * @version V1.2.0 - * @date 06-February-2015 + * @version V1.5.0 + * @date 8-January-2016 * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32l0xx_hal_conf.h. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -114,6 +114,23 @@ #endif /* HSI_VALUE */ /** + * @brief Internal High Speed oscillator for USB (HSI48) value. + */ +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)37000) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,20 +2,20 @@
******************************************************************************
* @file system_stm32l0xx.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
*
- * This file provides two functions and one global variable to be called from
+ * This file provides two functions and one global variable to be called from
* user application:
- * - SystemInit(): This function is called at startup just after reset and
+ * - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32l0xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
+ * by the user application to setup the SysTick
* timer or configure other parameters.
- *
+ *
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
@@ -36,11 +36,11 @@
* APB2CLK (MHz) | 32 | 32
*-----------------------------------------------------------------------------
* USB capable (48 MHz precise clock) | YES | YES
- *-----------------------------------------------------------------------------
+ *-----------------------------------------------------------------------------
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -73,8 +73,8 @@
/** @addtogroup stm32l0xx_system
* @{
- */
-
+ */
+
/** @addtogroup STM32L0xx_System_Private_Includes
* @{
*/
@@ -82,14 +82,14 @@
#include "stm32l0xx.h"
#include "hal_tick.h"
-#if !defined (HSE_VALUE)
+#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
-
+
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
@@ -115,7 +115,7 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
@@ -140,14 +140,14 @@
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 32000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t PLLMulTable_2[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
/**
* @}
@@ -177,19 +177,19 @@
* @retval None
*/
void SystemInit (void)
-{
+{
/*!< Set MSION bit */
RCC->CR |= (uint32_t)0x00000100;
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
RCC->CFGR &= (uint32_t) 0x88FF400C;
-
+
/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFF6;
-
+
/*!< Reset HSI48ON bit */
RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
-
+
/*!< Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
@@ -198,7 +198,7 @@
/*!< Disable all interrupts */
RCC->CIER = 0x00000000;
-
+
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
@@ -224,34 +224,34 @@
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
- *
+ *
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
- *
- * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
* value as defined by the MSI range.
- *
+ *
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
+ *
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
+ *
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
+ *
* (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
* 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
+ * in voltage and temperature.
+ *
* (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
- *
+ *
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
@@ -263,7 +263,7 @@
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
-
+
switch (tmp)
{
case 0x00: /* MSI used as system clock */
@@ -280,9 +280,9 @@
/* Get PLL clock source and multiplication factor ----------------------*/
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
- pllmul = PLLMulTable_2[(pllmul >> 18)];
+ pllmul = PLLMulTable[(pllmul >> 18)];
plldiv = (plldiv >> 22) + 1;
-
+
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
if (pllsource == 0x00)
@@ -311,8 +311,8 @@
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
- * @note This function should be called only once the RCC clock configuration
- * is reset to the default reset state (done in SystemInit() function).
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
@@ -338,7 +338,7 @@
}
}
}
-
+
/* Output clock on MCO1 pin(PA8) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
@@ -358,13 +358,13 @@
{
return 0;
}
-
- /* The voltage scaling allows optimizing the power consumption when the device is
- clocked below the maximum system frequency, to update the voltage scaling value
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
+
/* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
if (bypass == 0)
@@ -376,7 +376,10 @@
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
}
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
+ !defined (STM32L011xx) && !defined (STM32L021xx)
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
+#endif
// PLLCLK = (8 MHz * 8)/2 = 32 MHz
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
@@ -386,7 +389,7 @@
{
return 0; // FAIL
}
-
+
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
@@ -403,7 +406,7 @@
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
//else
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-
+
return 1; // OK
}
#endif
@@ -416,17 +419,20 @@
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
- /* The voltage scaling allows optimizing the power consumption when the device is
- clocked below the maximum system frequency, to update the voltage scaling value
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
+
/* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
+ !defined (STM32L011xx) && !defined (STM32L021xx)
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
+#endif
// PLLCLK = (16 MHz * 4)/2 = 32 MHz
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
@@ -436,7 +442,7 @@
{
return 0; // FAIL
}
-
+
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
@@ -450,7 +456,7 @@
/* Output clock on MCO1 pin(PA8) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-
+
return 1; // OK
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.h Sun Apr 17 17:45:10 2016 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.h Tue Apr 19 11:15:15 2016 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32l0xx.h * @author MCD Application Team - * @version V1.2.0 - * @date 06-February-2015 + * @version V1.5.0 + * @date 8-January-2016 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.S Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.S Tue Apr 19 11:15:15 2016 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
-;* Version : V1.2.0
-;* Date : 06-February-2015
+;* Version : V1.5.0
+;* Date : 8-January-2016
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@@ -90,7 +90,7 @@
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
@@ -161,11 +161,6 @@
EXPORT SVC_Handler [WEAK]
B .
ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
@@ -240,3 +235,5 @@
ALIGN
END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/startup_stm32l053xx.S Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/startup_stm32l053xx.S Tue Apr 19 11:15:15 2016 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
-;* Version : V1.2.0
-;* Date : 06-February-2015
+;* Version : V1.5.0
+;* Date : 8-January-2016
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@@ -63,7 +63,7 @@
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
@@ -134,11 +134,6 @@
EXPORT SVC_Handler [WEAK]
B .
ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
@@ -213,3 +208,5 @@
ALIGN
END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.S Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.S Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file startup_stm32l053xx.s
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief STM32L053xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
@@ -149,7 +149,7 @@
.word 0
.word 0
.word SVC_Handler
- .word DebugMon_Handler
+ .word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
@@ -203,9 +203,6 @@
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_IAR/startup_stm32l053xx.S Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_IAR/startup_stm32l053xx.S Tue Apr 19 11:15:15 2016 +0100
@@ -1,8 +1,8 @@
-;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
-;* Version : V1.2.0
-;* Date : 06-February-2015
+;* Version : V1.5.0
+;* Date : 8-January-2016
;* Description : STM32L053xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP
@@ -82,7 +82,7 @@
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
@@ -152,12 +152,6 @@
B SVC_Handler
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DebugMon_Handler
- B DebugMon_Handler
-
-
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/stm32l053xx.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/stm32l053xx.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l053xx.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l053xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -174,19 +174,26 @@
__IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
} COMP_TypeDef;
-
-/**
- * @brief CRC calculation unit
- */
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
typedef struct
{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
- uint32_t RESERVED2; /*!< Reserved, 0x0C */
- __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
- __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
} CRC_TypeDef;
/**
@@ -378,7 +385,6 @@
/**
* @brief LCD
*/
-
typedef struct
{
__IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
@@ -392,7 +398,6 @@
/**
* @brief MIFARE Firewall
*/
-
typedef struct
{
__IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
@@ -405,12 +410,11 @@
__IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
__IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
-} FW_TypeDef;
+} FIREWALL_TypeDef;
/**
* @brief Power Control
*/
-
typedef struct
{
__IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
@@ -491,7 +495,6 @@
/**
* @brief Serial Peripheral Interface
*/
-
typedef struct
{
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
@@ -510,27 +513,27 @@
*/
typedef struct
{
- __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
- __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
- __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
- __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
} TIM_TypeDef;
/**
@@ -557,7 +560,6 @@
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
-
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
@@ -586,7 +588,6 @@
/**
* @brief Universal Serial Bus Full Speed Device
*/
-
typedef struct
{
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
@@ -628,13 +629,12 @@
/** @addtogroup Peripheral_memory_map
* @{
*/
-
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_END ((uint32_t)0x0800FFFF) /*!< FLASH end address in the alias region */
-#define DATA_EEPROM_BASE ((uint32_t)0x08080000) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END ((uint32_t)0x080807FF) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
+#define FLASH_END ((uint32_t)0x0800FFFFU) /*!< FLASH end address in the alias region */
+#define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END ((uint32_t)0x080807FFU) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
/*!< Peripheral memory map */
#define APBPERIPH_BASE PERIPH_BASE
@@ -660,10 +660,11 @@
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
#define COMP1_BASE (APBPERIPH_BASE + 0x00010018)
#define COMP2_BASE (APBPERIPH_BASE + 0x0001001C)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
#define TIM21_BASE (APBPERIPH_BASE + 0x00010800)
#define TIM22_BASE (APBPERIPH_BASE + 0x00011400)
-#define FW_BASE (APBPERIPH_BASE + 0x00011C00)
+#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00)
#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
@@ -683,7 +684,7 @@
#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
-#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
+#define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
#define RNG_BASE (AHBPERIPH_BASE + 0x00005000)
@@ -715,6 +716,7 @@
#define CRS ((CRS_TypeDef *) CRS_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define LCD ((LCD_TypeDef *) LCD_BASE)
@@ -724,9 +726,11 @@
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
-#define FW ((FW_TypeDef *) FW_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
@@ -778,139 +782,140 @@
/* */
/******************************************************************************/
/******************** Bits definition for ADC_ISR register ******************/
-#define ADC_ISR_EOCAL ((uint32_t)0x00000800) /*!< End of calibration flag */
-#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
-#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
-#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
-#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
-#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
-#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
+#define ADC_ISR_EOCAL ((uint32_t)0x00000800U) /*!< End of calibration flag */
+#define ADC_ISR_AWD ((uint32_t)0x00000080U) /*!< Analog watchdog flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< Overrun flag */
+#define ADC_ISR_EOSEQ ((uint32_t)0x00000008U) /*!< End of Sequence flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< End of Conversion */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< End of sampling flag */
+#define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC Ready */
/* Old EOSEQ bit definition, maintained for legacy purpose */
#define ADC_ISR_EOS ADC_ISR_EOSEQ
/******************** Bits definition for ADC_IER register ******************/
-#define ADC_IER_EOCALIE ((uint32_t)0x00000800) /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
+#define ADC_IER_EOCALIE ((uint32_t)0x00000800U) /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE ((uint32_t)0x00000080U) /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE ((uint32_t)0x00000008U) /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC Ready interrupt enable */
/* Old EOSEQIE bit definition, maintained for legacy purpose */
#define ADC_IER_EOSIE ADC_IER_EOSEQIE
/******************** Bits definition for ADC_CR register *******************/
-#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
-#define ADC_CR_ADVREGEN ((uint32_t)0x10000000) /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
-#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
-#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */ /*#### TBV */
+#define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */
+#define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC start of conversion */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable command */
+#define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable control */ /*#### TBV */
/******************* Bits definition for ADC_CFGR1 register *****************/
-#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
-#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
-#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
-#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
+#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000U) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
+#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
+#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
+#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
+#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
+#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000U) /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000U) /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000U) /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000U) /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT ((uint32_t)0x00004000U) /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT ((uint32_t)0x00002000U) /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000U) /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00U) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
+#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0U) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
+#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100U) /*!< Bit 2 */
+#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020U) /*!< Data Alignment */
+#define ADC_CFGR1_RES ((uint32_t)0x00000018U) /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
+#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
+#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004U) /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002U) /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001U) /*!< Direct memory access enable */
/* Old WAIT bit definition, maintained for legacy purpose */
#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
/******************* Bits definition for ADC_CFGR2 register *****************/
-#define ADC_CFGR2_TOVS ((uint32_t)0x80000200) /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0) /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
-#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100) /*!< Bit 3 */
-#define ADC_CFGR2_OVSR ((uint32_t)0x0000001C) /*!< OVSR [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010) /*!< Bit 2 */
-#define ADC_CFGR2_OVSE ((uint32_t)0x00000001) /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< Bit 0 */
-#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+#define ADC_CFGR2_TOVS ((uint32_t)0x80000200U) /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
+#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
+#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
+#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
+#define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
+#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
+#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /*!< Bit 2 */
+#define ADC_CFGR2_OVSE ((uint32_t)0x00000001U) /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000U) /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000U) /*!< Bit 0 */
+#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000U) /*!< Bit 1 */
/****************** Bit definition for ADC_SMPR register ********************/
-#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-
-/* Bit names aliases maintained for legacy */
+#define ADC_SMPR_SMP ((uint32_t)0x00000007U) /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
+#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
+
+/* Legacy defines */
#define ADC_SMPR_SMPR ADC_SMPR_SMP
#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
/******************* Bit definition for ADC_TR register ********************/
-#define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
-#define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+#define ADC_TR_HT ((uint32_t)0x0FFF0000U) /*!< Analog watchdog high threshold */
+#define ADC_TR_LT ((uint32_t)0x00000FFFU) /*!< Analog watchdog low threshold */
/****************** Bit definition for ADC_CHSELR register ******************/
-#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
-#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
+#define ADC_CHSELR_CHSEL ((uint32_t)0x0007FFFFU) /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000U) /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000U) /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000U) /*!< Channel 16 selection */
+#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000U) /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000U) /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000U) /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000U) /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800U) /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400U) /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200U) /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100U) /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080U) /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040U) /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020U) /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010U) /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008U) /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004U) /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002U) /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001U) /*!< Channel 0 selection */
/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+#define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< Regular data */
/******************** Bit definition for ADC_CALFACT register ********************/
-#define ADC_CALFACT_CALFACT ((uint32_t)0x0000007F) /*!< Calibration factor */
+#define ADC_CALFACT_CALFACT ((uint32_t)0x0000007FU) /*!< Calibration factor */
/******************* Bit definition for ADC_CCR register ********************/
-#define ADC_CCR_LFMEN ((uint32_t)0x02000000) /*!< Low Frequency Mode enable */
-#define ADC_CCR_VLCDEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
-#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
-#define ADC_CCR_PRESC ((uint32_t)0x003C0000) /*!< PRESC [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+#define ADC_CCR_LFMEN ((uint32_t)0x02000000U) /*!< Low Frequency Mode enable */
+#define ADC_CCR_VLCDEN ((uint32_t)0x01000000U) /*!< Voltage LCD enable */
+#define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< Vrefint enable */
+#define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
+#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
+#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
+#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /*!< Bit 3 */
/******************************************************************************/
/* */
@@ -919,37 +924,40 @@
/******************************************************************************/
/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030) /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
-#define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
-#define COMP_CSR_COMP1WM ((uint32_t)0x00000100) /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000) /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000) /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000) /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
+#define COMP_CSR_COMP1EN ((uint32_t)0x00000001U) /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030U) /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP1 inverting input select bit 0 */
+#define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP1 inverting input select bit 1 */
+#define COMP_CSR_COMP1WM ((uint32_t)0x00000100U) /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000U) /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000U) /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000U) /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000U) /*!< COMP1 lock */
/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED ((uint32_t)0x000C0008) /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL ((uint32_t)0x00100070) /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00100010) /*!< COMP2 inverting input select bit 0 */
-#define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00200020) /*!< COMP2 inverting input select bit 1 */
-#define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00400040) /*!< COMP2 inverting input select bit 2 */
-#define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000) /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000) /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000) /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
+#define COMP_CSR_COMP2EN ((uint32_t)0x00000001U) /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED ((uint32_t)0x00000008U) /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL ((uint32_t)0x00000070U) /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP2 inverting input select bit 0 */
+#define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP2 inverting input select bit 1 */
+#define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00000040U) /*!< COMP2 inverting input select bit 2 */
+#define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700U) /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100U) /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200U) /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400U) /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000U) /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1 ((uint32_t)0x00002000U) /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000U) /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000U) /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000U) /*!< COMP2 lock */
/********************** Bit definition for COMP_CSR register common ****************/
-#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000) /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000) /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
-
+#define COMP_CSR_COMPxEN ((uint32_t)0x00000001U) /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000U) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000U) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000U) /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
/******************************************************************************/
/* */
@@ -957,26 +965,26 @@
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
-#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
+#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
-#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
-#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
-#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+#define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */
+#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
-#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
-#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
+#define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
@@ -985,92 +993,98 @@
/******************************************************************************/
/******************* Bit definition for CRS_CR register *********************/
-#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
-#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
-#define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
-#define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
-#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
-#define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
-#define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
+#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001U) /* SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002U) /* SYNC warning interrupt enable */
+#define CRS_CR_ERRIE ((uint32_t)0x00000004U) /* SYNC error interrupt enable */
+#define CRS_CR_ESYNCIE ((uint32_t)0x00000008U) /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define CRS_CR_CEN ((uint32_t)0x00000020U) /* Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040U) /* Automatic trimming enable */
+#define CRS_CR_SWSYNC ((uint32_t)0x00000080U) /* A Software SYNC event is generated */
+#define CRS_CR_TRIM ((uint32_t)0x00003F00U) /* HSI48 oscillator smooth trimming */
/******************* Bit definition for CRS_CFGR register *********************/
-#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
-#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
-
-#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
-#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
-#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
-#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
-
-#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
-#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
-#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
-
-#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
+#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFFU) /* Counter reload value */
+#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000U) /* Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000U) /* SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000U) /* Bit 0 */
+#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000U) /* Bit 1 */
+#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000U) /* Bit 2 */
+
+#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000U) /* SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000U) /* Bit 0 */
+#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000U) /* Bit 1 */
+
+#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000U) /* SYNC polarity selection */
/******************* Bit definition for CRS_ISR register *********************/
-#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
-#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
-#define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
-#define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
-#define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
-#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
-#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
-#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
+#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001U) /* SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002U) /* SYNC warning */
+#define CRS_ISR_ERRF ((uint32_t)0x00000004U) /* SYNC error flag */
+#define CRS_ISR_ESYNCF ((uint32_t)0x00000008U) /* Expected SYNC flag */
+#define CRS_ISR_SYNCERR ((uint32_t)0x00000100U) /* SYNC error */
+#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200U) /* SYNC missed */
+#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400U) /* Trimming overflow or underflow */
+#define CRS_ISR_FEDIR ((uint32_t)0x00008000U) /* Frequency error direction */
+#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000U) /* Frequency error capture */
/******************* Bit definition for CRS_ICR register *********************/
-#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
-#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
-#define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
-#define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
+#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001U) /* SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002U) /* SYNC warning clear flag */
+#define CRS_ICR_ERRC ((uint32_t)0x00000004U) /* Error clear flag */
+#define CRS_ICR_ESYNCC ((uint32_t)0x00000008U) /* Expected SYNC clear flag */
/******************************************************************************/
/* */
/* Digital to Analog Converter (DAC) */
/* */
/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
/******************** Bit definition for DAC_CR register ********************/
-#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-
-#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-
-#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun interrupt enable */
+#define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002U) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA Underrun interrupt enable */
/***************** Bit definition for DAC_SWTRIGR register ******************/
-#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!< DAC channel1 software trigger */
/***************** Bit definition for DAC_DHR12R1 register ******************/
-#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!< DAC channel1 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L1 register ******************/
-#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel1 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R1 register ******************/
-#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!< DAC channel1 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
-#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFF) /*!< DAC channel1 data output */
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */
/******************** Bit definition for DAC_SR register ********************/
-#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA underrun flag */
/******************************************************************************/
/* */
@@ -1079,44 +1093,44 @@
/******************************************************************************/
/**************** Bit definition for DBGMCU_IDCODE register *****************/
-#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
-#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
-#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
-#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
-#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
-#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /*!< Bit 15 */
/****************** Bit definition for DBGMCU_CR register *******************/
-#define DBGMCU_CR_DBG ((uint32_t)0x00000007) /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+#define DBGMCU_CR_DBG ((uint32_t)0x00000007U) /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U) /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /*!< Debug Standby mode */
/****************** Bit definition for DBGMCU_APB1_FZ register **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP ((uint32_t)0x00400000) /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000) /*!< LPTIM1 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010U) /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000U) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP ((uint32_t)0x00400000U) /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000U) /*!< LPTIM1 counter stopped when core is halted */
/****************** Bit definition for DBGMCU_APB2_FZ register **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020) /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004) /*!< TIM21 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020U) /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004U) /*!< TIM21 counter stopped when core is halted */
/******************************************************************************/
/* */
@@ -1125,107 +1139,107 @@
/******************************************************************************/
/******************* Bit definition for DMA_ISR register ********************/
-#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *******************/
-#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */
/******************* Bit definition for DMA_CCR register ********************/
-#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
-#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
-#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
-#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
-#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-
-#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-
-#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-
-#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+#define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */
/****************** Bit definition for DMA_CNDTR register *******************/
-#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CPAR register ********************/
-#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
/****************** Bit definition for DMA_CMAR register ********************/
-#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
/******************* Bit definition for DMA_CSELR register *******************/
-#define DMA_CSELR_C1S ((uint32_t)0x0000000F) /*!< Channel 1 Selection */
-#define DMA_CSELR_C2S ((uint32_t)0x000000F0) /*!< Channel 2 Selection */
-#define DMA_CSELR_C3S ((uint32_t)0x00000F00) /*!< Channel 3 Selection */
-#define DMA_CSELR_C4S ((uint32_t)0x0000F000) /*!< Channel 4 Selection */
-#define DMA_CSELR_C5S ((uint32_t)0x000F0000) /*!< Channel 5 Selection */
-#define DMA_CSELR_C6S ((uint32_t)0x00F00000) /*!< Channel 6 Selection */
-#define DMA_CSELR_C7S ((uint32_t)0x0F000000) /*!< Channel 7 Selection */
+#define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /*!< Channel 7 Selection */
/******************************************************************************/
@@ -1235,160 +1249,256 @@
/******************************************************************************/
/******************* Bit definition for EXTI_IMR register *******************/
-#define EXTI_IMR_IM0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_IM1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_IM2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_IM3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_IM4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_IM5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_IM6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_IM7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_IM8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_IM9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_IM10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_IM0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26 ((uint32_t)0x04000000U) /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28 ((uint32_t)0x10000000U) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29 ((uint32_t)0x20000000U) /*!< Interrupt Mask on line 29 */
/****************** Bit definition for EXTI_EMR register ********************/
-#define EXTI_EMR_EM0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
-#define EXTI_EMR_EM1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
-#define EXTI_EMR_EM2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
-#define EXTI_EMR_EM3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
-#define EXTI_EMR_EM4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
-#define EXTI_EMR_EM5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
-#define EXTI_EMR_EM6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
-#define EXTI_EMR_EM7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
-#define EXTI_EMR_EM8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
-#define EXTI_EMR_EM9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
-#define EXTI_EMR_EM10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_EM0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26 ((uint32_t)0x04000000U) /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28 ((uint32_t)0x10000000U) /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29 ((uint32_t)0x20000000U) /*!< Event Mask on line 29 */
/******************* Bit definition for EXTI_RTSR register ******************/
-#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_RT0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17 ((uint32_t)0x00020000U) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
/******************* Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_FT0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17 ((uint32_t)0x00020000U) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWI0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17 ((uint32_t)0x00020000U) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
/****************** Bit definition for EXTI_PR register *********************/
-#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
-#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
-#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
-#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
-#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
-#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
-#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
-#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
-#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
-#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
-#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
-#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
-#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
-#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
-#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
-#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
-#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
-#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
-#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
-#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
-#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
-#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
+#define EXTI_PR_PIF0 ((uint32_t)0x00000001U) /*!< Pending bit 0 */
+#define EXTI_PR_PIF1 ((uint32_t)0x00000002U) /*!< Pending bit 1 */
+#define EXTI_PR_PIF2 ((uint32_t)0x00000004U) /*!< Pending bit 2 */
+#define EXTI_PR_PIF3 ((uint32_t)0x00000008U) /*!< Pending bit 3 */
+#define EXTI_PR_PIF4 ((uint32_t)0x00000010U) /*!< Pending bit 4 */
+#define EXTI_PR_PIF5 ((uint32_t)0x00000020U) /*!< Pending bit 5 */
+#define EXTI_PR_PIF6 ((uint32_t)0x00000040U) /*!< Pending bit 6 */
+#define EXTI_PR_PIF7 ((uint32_t)0x00000080U) /*!< Pending bit 7 */
+#define EXTI_PR_PIF8 ((uint32_t)0x00000100U) /*!< Pending bit 8 */
+#define EXTI_PR_PIF9 ((uint32_t)0x00000200U) /*!< Pending bit 9 */
+#define EXTI_PR_PIF10 ((uint32_t)0x00000400U) /*!< Pending bit 10 */
+#define EXTI_PR_PIF11 ((uint32_t)0x00000800U) /*!< Pending bit 11 */
+#define EXTI_PR_PIF12 ((uint32_t)0x00001000U) /*!< Pending bit 12 */
+#define EXTI_PR_PIF13 ((uint32_t)0x00002000U) /*!< Pending bit 13 */
+#define EXTI_PR_PIF14 ((uint32_t)0x00004000U) /*!< Pending bit 14 */
+#define EXTI_PR_PIF15 ((uint32_t)0x00008000U) /*!< Pending bit 15 */
+#define EXTI_PR_PIF16 ((uint32_t)0x00010000U) /*!< Pending bit 16 */
+#define EXTI_PR_PIF17 ((uint32_t)0x00020000U) /*!< Pending bit 17 */
+#define EXTI_PR_PIF19 ((uint32_t)0x00080000U) /*!< Pending bit 19 */
+#define EXTI_PR_PIF20 ((uint32_t)0x00100000U) /*!< Pending bit 20 */
+#define EXTI_PR_PIF21 ((uint32_t)0x00200000U) /*!< Pending bit 21 */
+#define EXTI_PR_PIF22 ((uint32_t)0x00400000U) /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
/******************************************************************************/
/* */
@@ -1397,70 +1507,70 @@
/******************************************************************************/
/******************* Bit definition for FLASH_ACR register ******************/
-#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020) /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ ((uint32_t)0x00000040) /*!< Pre-read data address */
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002U) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008U) /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010U) /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020U) /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ ((uint32_t)0x00000040U) /*!< Pre-read data address */
/******************* Bit definition for FLASH_PECR register ******************/
-#define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
-#define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
-#define FLASH_PECR_FIX ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
-#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
-#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
-#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000) /*!< Half array mode */
+#define FLASH_PECR_PELOCK ((uint32_t)0x00000001U) /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002U) /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004U) /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG ((uint32_t)0x00000008U) /*!< Program matrix selection */
+#define FLASH_PECR_DATA ((uint32_t)0x00000010U) /*!< Data matrix selection */
+#define FLASH_PECR_FIX ((uint32_t)0x00000100U) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE ((uint32_t)0x00000200U) /*!< Page erasing mode */
+#define FLASH_PECR_FPRG ((uint32_t)0x00000400U) /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE ((uint32_t)0x00010000U) /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE ((uint32_t)0x00020000U) /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000U) /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000U) /*!< Half array mode */
/****************** Bit definition for FLASH_PDKEYR register ******************/
-#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
+#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */
/****************** Bit definition for FLASH_PEKEYR register ******************/
-#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
+#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */
/****************** Bit definition for FLASH_PRGKEYR register ******************/
-#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
+#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFFU) /*!< Program matrix Key */
/****************** Bit definition for FLASH_OPTKEYR register ******************/
-#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /*!< Option bytes matrix Key */
/****************** Bit definition for FLASH_SR register *******************/
-#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
-#define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
-#define FLASH_SR_HVOFF ((uint32_t)0x00000004) /*!< End of high voltage */
-#define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protection error */
-#define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
-#define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option Valid error */
-#define FLASH_SR_RDERR ((uint32_t)0x00002000) /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000) /*!< Not Zero error */
-#define FLASH_SR_FWWERR ((uint32_t)0x00020000) /*!< Write/Errase operation aborted */
-
-/* alias maintained for legacy */
+#define FLASH_SR_BSY ((uint32_t)0x00000001U) /*!< Busy */
+#define FLASH_SR_EOP ((uint32_t)0x00000002U) /*!< End Of Programming*/
+#define FLASH_SR_HVOFF ((uint32_t)0x00000004U) /*!< End of high voltage */
+#define FLASH_SR_READY ((uint32_t)0x00000008U) /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR ((uint32_t)0x00000100U) /*!< Write protection error */
+#define FLASH_SR_PGAERR ((uint32_t)0x00000200U) /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR ((uint32_t)0x00000400U) /*!< Size error */
+#define FLASH_SR_OPTVERR ((uint32_t)0x00000800U) /*!< Option Valid error */
+#define FLASH_SR_RDERR ((uint32_t)0x00002000U) /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000U) /*!< Not Zero error */
+#define FLASH_SR_FWWERR ((uint32_t)0x00020000U) /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
#define FLASH_SR_FWWER FLASH_SR_FWWERR
#define FLASH_SR_ENHV FLASH_SR_HVOFF
#define FLASH_SR_ENDHV FLASH_SR_HVOFF
/****************** Bit definition for FLASH_OPTR register *******************/
-#define FLASH_OPTR_RDPROT ((uint32_t)0x000000FF) /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
-#define FLASH_OPTR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000) /*!< BOOT1 */
+#define FLASH_OPTR_RDPROT ((uint32_t)0x000000FFU) /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100U) /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000U) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000U) /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000U) /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000U) /*!< nRST_STDBY */
+#define FLASH_OPTR_USER ((uint32_t)0x00700000U) /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000U) /*!< BOOT1 */
/****************** Bit definition for FLASH_WRPR register ******************/
-#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protection bits */
+#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFFU) /*!< Write Protection bits */
/******************************************************************************/
/* */
@@ -1468,279 +1578,299 @@
/* */
/******************************************************************************/
/******************* Bit definition for GPIO_MODER register *****************/
-#define GPIO_MODER_MODE0 ((uint32_t)0x00000003)
-#define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001)
-#define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002)
-#define GPIO_MODER_MODE1 ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004)
-#define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008)
-#define GPIO_MODER_MODE2 ((uint32_t)0x00000030)
-#define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010)
-#define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020)
-#define GPIO_MODER_MODE3 ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040)
-#define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080)
-#define GPIO_MODER_MODE4 ((uint32_t)0x00000300)
-#define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100)
-#define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200)
-#define GPIO_MODER_MODE5 ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400)
-#define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800)
-#define GPIO_MODER_MODE6 ((uint32_t)0x00003000)
-#define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000)
-#define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000)
-#define GPIO_MODER_MODE7 ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000)
-#define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000)
-#define GPIO_MODER_MODE8 ((uint32_t)0x00030000)
-#define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000)
-#define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000)
-#define GPIO_MODER_MODE9 ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000)
-#define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000)
-#define GPIO_MODER_MODE10 ((uint32_t)0x00300000)
-#define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000)
-#define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000)
-#define GPIO_MODER_MODE11 ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000)
-#define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000)
-#define GPIO_MODER_MODE12 ((uint32_t)0x03000000)
-#define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000)
-#define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000)
-#define GPIO_MODER_MODE13 ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000)
-#define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000)
-#define GPIO_MODER_MODE14 ((uint32_t)0x30000000)
-#define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000)
-#define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000)
-#define GPIO_MODER_MODE15 ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000)
-#define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000)
+#define GPIO_MODER_MODE0 ((uint32_t)0x00000003U)
+#define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U)
+#define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U)
+#define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU)
+#define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U)
+#define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U)
+#define GPIO_MODER_MODE2 ((uint32_t)0x00000030U)
+#define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U)
+#define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U)
+#define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U)
+#define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U)
+#define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U)
+#define GPIO_MODER_MODE4 ((uint32_t)0x00000300U)
+#define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U)
+#define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U)
+#define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U)
+#define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U)
+#define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U)
+#define GPIO_MODER_MODE6 ((uint32_t)0x00003000U)
+#define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U)
+#define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U)
+#define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U)
+#define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U)
+#define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U)
+#define GPIO_MODER_MODE8 ((uint32_t)0x00030000U)
+#define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U)
+#define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U)
+#define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U)
+#define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U)
+#define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U)
+#define GPIO_MODER_MODE10 ((uint32_t)0x00300000U)
+#define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U)
+#define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U)
+#define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U)
+#define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U)
+#define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U)
+#define GPIO_MODER_MODE12 ((uint32_t)0x03000000U)
+#define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U)
+#define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U)
+#define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U)
+#define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U)
+#define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U)
+#define GPIO_MODER_MODE14 ((uint32_t)0x30000000U)
+#define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U)
+#define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U)
+#define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U)
+#define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U)
+#define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U)
/****************** Bit definition for GPIO_OTYPER register *****************/
-#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U)
/**************** Bit definition for GPIO_OSPEEDR register ******************/
-#define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002)
-#define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008)
-#define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020)
-#define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080)
-#define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200)
-#define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800)
-#define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000)
-#define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000)
-#define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000)
-#define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000)
-#define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000)
-#define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000)
-#define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000)
-#define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000)
-#define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000)
-#define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000)
+#define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003U)
+#define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001U)
+#define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002U)
+#define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000CU)
+#define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004U)
+#define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008U)
+#define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030U)
+#define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010U)
+#define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020U)
+#define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0U)
+#define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040U)
+#define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080U)
+#define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300U)
+#define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100U)
+#define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200U)
+#define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00U)
+#define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400U)
+#define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800U)
+#define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000U)
+#define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000U)
+#define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000U)
+#define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000U)
+#define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000U)
+#define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000U)
+#define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000U)
+#define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000U)
+#define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000U)
+#define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000U)
+#define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000U)
+#define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000U)
+#define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000U)
+#define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000U)
+#define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000U)
+#define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000U)
+#define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000U)
+#define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000U)
+#define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000U)
+#define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000U)
+#define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000U)
+#define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000U)
+#define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000U)
+#define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000U)
+#define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000U)
+#define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000U)
+#define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000U)
+#define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000U)
+#define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000U)
+#define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000U)
/******************* Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002)
-#define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008)
-#define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020)
-#define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080)
-#define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200)
-#define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800)
-#define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000)
-#define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000)
-#define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000)
-#define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000)
-#define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000)
-#define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000)
-#define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000)
-#define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000)
-#define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000)
+#define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U)
+#define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U)
+#define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U)
+#define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU)
+#define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U)
+#define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U)
+#define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U)
+#define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U)
+#define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U)
+#define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U)
+#define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U)
+#define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U)
+#define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U)
+#define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U)
+#define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U)
+#define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U)
+#define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U)
+#define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U)
+#define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U)
+#define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U)
+#define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U)
+#define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U)
+#define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U)
+#define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U)
+#define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U)
+#define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U)
+#define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U)
+#define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U)
+#define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U)
+#define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U)
+#define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U)
+#define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U)
+#define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U)
+#define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U)
+#define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U)
+#define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U)
+#define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U)
+#define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U)
+#define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U)
+#define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U)
+#define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U)
+#define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U)
+#define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U)
+#define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U)
+#define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U)
+#define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U)
+#define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U)
+#define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U)
/******************* Bit definition for GPIO_IDR register *******************/
-#define GPIO_IDR_ID0 ((uint32_t)0x00000001)
-#define GPIO_IDR_ID1 ((uint32_t)0x00000002)
-#define GPIO_IDR_ID2 ((uint32_t)0x00000004)
-#define GPIO_IDR_ID3 ((uint32_t)0x00000008)
-#define GPIO_IDR_ID4 ((uint32_t)0x00000010)
-#define GPIO_IDR_ID5 ((uint32_t)0x00000020)
-#define GPIO_IDR_ID6 ((uint32_t)0x00000040)
-#define GPIO_IDR_ID7 ((uint32_t)0x00000080)
-#define GPIO_IDR_ID8 ((uint32_t)0x00000100)
-#define GPIO_IDR_ID9 ((uint32_t)0x00000200)
-#define GPIO_IDR_ID10 ((uint32_t)0x00000400)
-#define GPIO_IDR_ID11 ((uint32_t)0x00000800)
-#define GPIO_IDR_ID12 ((uint32_t)0x00001000)
-#define GPIO_IDR_ID13 ((uint32_t)0x00002000)
-#define GPIO_IDR_ID14 ((uint32_t)0x00004000)
-#define GPIO_IDR_ID15 ((uint32_t)0x00008000)
+#define GPIO_IDR_ID0 ((uint32_t)0x00000001U)
+#define GPIO_IDR_ID1 ((uint32_t)0x00000002U)
+#define GPIO_IDR_ID2 ((uint32_t)0x00000004U)
+#define GPIO_IDR_ID3 ((uint32_t)0x00000008U)
+#define GPIO_IDR_ID4 ((uint32_t)0x00000010U)
+#define GPIO_IDR_ID5 ((uint32_t)0x00000020U)
+#define GPIO_IDR_ID6 ((uint32_t)0x00000040U)
+#define GPIO_IDR_ID7 ((uint32_t)0x00000080U)
+#define GPIO_IDR_ID8 ((uint32_t)0x00000100U)
+#define GPIO_IDR_ID9 ((uint32_t)0x00000200U)
+#define GPIO_IDR_ID10 ((uint32_t)0x00000400U)
+#define GPIO_IDR_ID11 ((uint32_t)0x00000800U)
+#define GPIO_IDR_ID12 ((uint32_t)0x00001000U)
+#define GPIO_IDR_ID13 ((uint32_t)0x00002000U)
+#define GPIO_IDR_ID14 ((uint32_t)0x00004000U)
+#define GPIO_IDR_ID15 ((uint32_t)0x00008000U)
/****************** Bit definition for GPIO_ODR register ********************/
-#define GPIO_ODR_OD0 ((uint32_t)0x00000001)
-#define GPIO_ODR_OD1 ((uint32_t)0x00000002)
-#define GPIO_ODR_OD2 ((uint32_t)0x00000004)
-#define GPIO_ODR_OD3 ((uint32_t)0x00000008)
-#define GPIO_ODR_OD4 ((uint32_t)0x00000010)
-#define GPIO_ODR_OD5 ((uint32_t)0x00000020)
-#define GPIO_ODR_OD6 ((uint32_t)0x00000040)
-#define GPIO_ODR_OD7 ((uint32_t)0x00000080)
-#define GPIO_ODR_OD8 ((uint32_t)0x00000100)
-#define GPIO_ODR_OD9 ((uint32_t)0x00000200)
-#define GPIO_ODR_OD10 ((uint32_t)0x00000400)
-#define GPIO_ODR_OD11 ((uint32_t)0x00000800)
-#define GPIO_ODR_OD12 ((uint32_t)0x00001000)
-#define GPIO_ODR_OD13 ((uint32_t)0x00002000)
-#define GPIO_ODR_OD14 ((uint32_t)0x00004000)
-#define GPIO_ODR_OD15 ((uint32_t)0x00008000)
+#define GPIO_ODR_OD0 ((uint32_t)0x00000001U)
+#define GPIO_ODR_OD1 ((uint32_t)0x00000002U)
+#define GPIO_ODR_OD2 ((uint32_t)0x00000004U)
+#define GPIO_ODR_OD3 ((uint32_t)0x00000008U)
+#define GPIO_ODR_OD4 ((uint32_t)0x00000010U)
+#define GPIO_ODR_OD5 ((uint32_t)0x00000020U)
+#define GPIO_ODR_OD6 ((uint32_t)0x00000040U)
+#define GPIO_ODR_OD7 ((uint32_t)0x00000080U)
+#define GPIO_ODR_OD8 ((uint32_t)0x00000100U)
+#define GPIO_ODR_OD9 ((uint32_t)0x00000200U)
+#define GPIO_ODR_OD10 ((uint32_t)0x00000400U)
+#define GPIO_ODR_OD11 ((uint32_t)0x00000800U)
+#define GPIO_ODR_OD12 ((uint32_t)0x00001000U)
+#define GPIO_ODR_OD13 ((uint32_t)0x00002000U)
+#define GPIO_ODR_OD14 ((uint32_t)0x00004000U)
+#define GPIO_ODR_OD15 ((uint32_t)0x00008000U)
/****************** Bit definition for GPIO_BSRR register ********************/
-#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U)
/****************** Bit definition for GPIO_LCKR register ********************/
-#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000U)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU)
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U)
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U)
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U)
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U)
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U)
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U)
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U)
/****************** Bit definition for GPIO_BRR register *********************/
-#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
-#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
-#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
-#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
-#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
-#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
-#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
-#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
-#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
-#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
-#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
-#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
-#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
-#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
-#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
-#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001U)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002U)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004U)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008U)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010U)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020U)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040U)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080U)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100U)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200U)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400U)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800U)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000U)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000U)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000U)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000U)
/******************************************************************************/
/* */
@@ -1749,102 +1879,110 @@
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register *******************/
-#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
-#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
-#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
-#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
-#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
-#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+#define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */
/****************** Bit definition for I2C_CR2 register ********************/
-#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
-#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
-#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+#define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */
/******************* Bit definition for I2C_OAR1 register ******************/
-#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register ******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
-#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */
/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */
/****************** Bit definition for I2C_ISR register *********************/
-#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
-#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
-#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
-#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
-#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
-#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
-#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
-#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
-#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
-#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+#define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */
/****************** Bit definition for I2C_ICR register *********************/
-#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
-#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */
/****************** Bit definition for I2C_PECR register *********************/
-#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+#define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */
/****************** Bit definition for I2C_RXDR register *********************/
-#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */
/****************** Bit definition for I2C_TXDR register *********************/
-#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */
/******************************************************************************/
/* */
@@ -1852,24 +1990,24 @@
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
+#define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!< Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
-#define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define IWDG_PR_PR ((uint32_t)0x00000007U) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
/******************* Bit definition for IWDG_RLR register *******************/
-#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
+#define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!< Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
-#define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
+#define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint32_t)0x00000004U) /*!< Watchdog counter window value update */
/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
+#define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /*!< Watchdog counter window value */
/******************************************************************************/
/* */
@@ -1878,64 +2016,66 @@
/******************************************************************************/
/******************* Bit definition for LCD_CR register *********************/
-#define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */
-#define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */
-#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */
-#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */
-
-#define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
-#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
+#define LCD_CR_LCDEN ((uint32_t)0x00000001U) /*!< LCD Enable Bit */
+#define LCD_CR_VSEL ((uint32_t)0x00000002U) /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY ((uint32_t)0x0000001CU) /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0 ((uint32_t)0x00000004U) /*!< Duty selector Bit 0 */
+#define LCD_CR_DUTY_1 ((uint32_t)0x00000008U) /*!< Duty selector Bit 1 */
+#define LCD_CR_DUTY_2 ((uint32_t)0x00000010U) /*!< Duty selector Bit 2 */
+
+#define LCD_CR_BIAS ((uint32_t)0x00000060U) /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0 ((uint32_t)0x00000020U) /*!< Bias selector Bit 0 */
+#define LCD_CR_BIAS_1 ((uint32_t)0x00000040U) /*!< Bias selector Bit 1 */
+
+#define LCD_CR_MUX_SEG ((uint32_t)0x00000080U) /*!< Mux Segment Enable Bit */
/******************* Bit definition for LCD_FCR register ********************/
-#define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-
-#define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */
-#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */
-#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */
-
-#define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-
-#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */
-#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */
-#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */
-
-#define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-
-#define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */
+#define LCD_FCR_HD ((uint32_t)0x00000001U) /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE ((uint32_t)0x00000002U) /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE ((uint32_t)0x00000008U) /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON ((uint32_t)0x00000070U) /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
+#define LCD_FCR_PON_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
+#define LCD_FCR_PON_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
+
+#define LCD_FCR_DEAD ((uint32_t)0x00000380U) /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080U) /*!< Bit 0 */
+#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100U) /*!< Bit 1 */
+#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200U) /*!< Bit 2 */
+
+#define LCD_FCR_CC ((uint32_t)0x00001C00U) /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
+#define LCD_FCR_CC_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
+#define LCD_FCR_CC_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
+
+#define LCD_FCR_BLINKF ((uint32_t)0x0000E000U) /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
+#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
+#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
+
+#define LCD_FCR_BLINK ((uint32_t)0x00030000U) /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
+#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
+
+#define LCD_FCR_DIV ((uint32_t)0x003C0000U) /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS ((uint32_t)0x03C00000U) /*!< PS[3:0] bits (Prescaler) */
/******************* Bit definition for LCD_SR register *********************/
-#define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */
-#define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */
-#define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */
+#define LCD_SR_ENS ((uint32_t)0x00000001U) /*!< LCD Enabled Bit */
+#define LCD_SR_SOF ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR ((uint32_t)0x00000004U) /*!< Update Display Request Bit */
+#define LCD_SR_UDD ((uint32_t)0x00000008U) /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY ((uint32_t)0x00000010U) /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR ((uint32_t)0x00000020U) /*!< LCD FCR Register Synchronization Flag Bit */
/******************* Bit definition for LCD_CLR register ********************/
-#define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */
+#define LCD_CLR_SOFC ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC ((uint32_t)0x00000008U) /*!< Update Display Done Flag Clear Bit */
/******************* Bit definition for LCD_RAM register ********************/
-#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */
+#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFFU) /*!< Segment Data Bits */
/******************************************************************************/
/* */
@@ -1943,81 +2083,81 @@
/* */
/******************************************************************************/
/****************** Bit definition for LPTIM_ISR register *******************/
-#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */
-#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
+#define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /*!< Compare match */
+#define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP ((uint32_t)0x00000020U) /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /*!< Counter direction change up to down */
/****************** Bit definition for LPTIM_ICR register *******************/
-#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
+#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /*!< Counter direction change up to down Clear Flag */
/****************** Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
+#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /*!< Counter direction change up to down Interrupt Enable */
/****************** Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */
-#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */
-
-#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-
-#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-
-#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */
-#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */
-#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */
-
-#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */
-#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */
-#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */
-
-#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */
-#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */
-
-#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */
-#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
+#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /*!< Bit 0 */
+#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /*!< Bit 1 */
+
+#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
+#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
+
+#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
+#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
+
+#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
+#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
+#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
+#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
+
+#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /*!< Timout enable */
+#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /*!< Encoder mode enable */
/****************** Bit definition for LPTIM_CR register ********************/
-#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */
+#define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /*!< Timer start in continuous mode */
/****************** Bit definition for LPTIM_CMP register *******************/
-#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */
+#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /*!< Compare register */
/****************** Bit definition for LPTIM_ARR register *******************/
-#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */
+#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!< Auto reload register */
/****************** Bit definition for LPTIM_CNT register *******************/
-#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */
+#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!< Counter register */
/******************************************************************************/
/* */
@@ -2026,17 +2166,17 @@
/******************************************************************************/
/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD ((uint32_t)0x00FFFF00) /*!< Code Segment Start Address */
-#define FW_CSL_LENG ((uint32_t)0x003FFF00) /*!< Code Segment Length */
-#define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00) /*!< Non Volatile Dat Segment Start Address */
-#define FW_NVDSL_LENG ((uint32_t)0x003FFF00) /*!< Non Volatile Data Segment Length */
-#define FW_VDSSA_ADD ((uint32_t)0x0000FFC0) /*!< Volatile Data Segment Start Address */
-#define FW_VDSL_LENG ((uint32_t)0x0000FFC0) /*!< Volatile Data Segment Length */
+#define FW_CSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Code Segment Start Address */
+#define FW_CSL_LENG ((uint32_t)0x003FFF00U) /*!< Code Segment Length */
+#define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG ((uint32_t)0x003FFF00U) /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Length */
/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA ((uint32_t)0x00000001) /*!< Firewall Pre Arm*/
-#define FW_CR_VDS ((uint32_t)0x00000002) /*!< Volatile Data Sharing*/
-#define FW_CR_VDE ((uint32_t)0x00000004) /*!< Volatile Data Execution*/
+#define FW_CR_FPA ((uint32_t)0x00000001U) /*!< Firewall Pre Arm*/
+#define FW_CR_VDS ((uint32_t)0x00000002U) /*!< Volatile Data Sharing*/
+#define FW_CR_VDE ((uint32_t)0x00000004U) /*!< Volatile Data Execution*/
/******************************************************************************/
/* */
@@ -2045,47 +2185,47 @@
/******************************************************************************/
/******************** Bit definition for PWR_CR register ********************/
-#define PWR_CR_LPSDSR ((uint32_t)0x00000001) /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
-#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define PWR_CR_LPSDSR ((uint32_t)0x00000001U) /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS ((uint32_t)0x00000002U) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004U) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008U) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010U) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0U) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
-
-#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP ((uint32_t)0x00000200) /*!< Ultra Low Power mode */
-#define PWR_CR_FWU ((uint32_t)0x00000400) /*!< Fast wakeup */
-
-#define PWR_CR_VOS ((uint32_t)0x00001800) /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0 ((uint32_t)0x00000800) /*!< Bit 0 */
-#define PWR_CR_VOS_1 ((uint32_t)0x00001000) /*!< Bit 1 */
-#define PWR_CR_DSEEKOFF ((uint32_t)0x00002000) /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN ((uint32_t)0x00004000) /*!< Low power run mode */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100U) /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP ((uint32_t)0x00000200U) /*!< Ultra Low Power mode */
+#define PWR_CR_FWU ((uint32_t)0x00000400U) /*!< Fast wakeup */
+
+#define PWR_CR_VOS ((uint32_t)0x00001800U) /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
+#define PWR_CR_VOS_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
+#define PWR_CR_DSEEKOFF ((uint32_t)0x00002000U) /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN ((uint32_t)0x00004000U) /*!< Low power run mode */
/******************* Bit definition for PWR_CSR register ********************/
-#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
-#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
-#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF ((uint32_t)0x00000010) /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF ((uint32_t)0x00000020) /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
+#define PWR_CSR_WUF ((uint32_t)0x00000001U) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002U) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004U) /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF ((uint32_t)0x00000010U) /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF ((uint32_t)0x00000020U) /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /*!< Enable WKUP pin 2 */
/******************************************************************************/
/* */
@@ -2094,325 +2234,395 @@
/******************************************************************************/
/******************** Bit definition for RCC_CR register ********************/
-#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON ((uint32_t)0x00000002) /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY ((uint32_t)0x00000004) /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN ((uint32_t)0x00000008) /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF ((uint32_t)0x00000010) /*!< Internal High Speed clock divider flag */
-#define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON ((uint32_t)0x00080000) /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE ((uint32_t)0x00300000) /*!< RTC/LCD prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000) /*!< RTC/LCD prescaler Bit 0 */
-#define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000) /*!< RTC/LCD prescaler Bit 1 */
-#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
-#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+#define RCC_CR_HSION ((uint32_t)0x00000001U) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON ((uint32_t)0x00000002U) /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000004U) /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN ((uint32_t)0x00000008U) /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF ((uint32_t)0x00000010U) /*!< Internal High Speed clock divider flag */
+#define RCC_CR_MSION ((uint32_t)0x00000100U) /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY ((uint32_t)0x00000200U) /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON ((uint32_t)0x00080000U) /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE ((uint32_t)0x00300000U) /*!< RTC/LCD prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000U) /*!< RTC/LCD prescaler Bit 0 */
+#define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000U) /*!< RTC/LCD prescaler Bit 1 */
+#define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
/******************** Bit definition for RCC_ICSCR register *****************/
-#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */
-#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */
-#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */
-#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */
-#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */
-#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */
-#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */
-#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */
+#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FFU) /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00U) /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000U) /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed clock Range 65.536 KHz */
+#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000U) /*!< Internal Multi Speed clock Range 131.072 KHz */
+#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000U) /*!< Internal Multi Speed clock Range 262.144 KHz */
+#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000U) /*!< Internal Multi Speed clock Range 524.288 KHz */
+#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000U) /*!< Internal Multi Speed clock Range 1.048 MHz */
+#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000U) /*!< Internal Multi Speed clock Range 2.097 MHz */
+#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000U) /*!< Internal Multi Speed clock Range 4.194 MHz */
+#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000U) /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000U) /*!< Internal Multi Speed clock trimming */
/******************** Bit definition for RCC_CRRCR register *****************/
-#define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001) /*!< HSI 48MHz clock enable */
-#define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002) /*!< HSI 48MHz clock ready flag */
-#define RCC_CRRCR_HSI48CAL ((uint32_t)0x0000FF00) /*!< HSI 48MHz clock Calibration */
+#define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001U) /*!< HSI 48MHz clock enable */
+#define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002U) /*!< HSI 48MHz clock ready flag */
+#define RCC_CRRCR_HSI48CAL ((uint32_t)0x0000FF00U) /*!< HSI 48MHz clock Calibration */
/******************* Bit definition for RCC_CFGR register *******************/
/*!< SW configuration */
-#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-
-#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selected as system clock */
/*!< SWS configuration */
-#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-
-#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */
/*!< HPRE configuration */
-#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
-#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
-#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000) /*!< Wake Up from Stop Clock selection */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /*!< Wake Up from Stop Clock selection */
/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000U) /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000U) /*!< HSE as PLL entry clock source */
/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
-
-#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000U) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000U) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000U) /*!< PLL input clock * 48 */
/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */
-#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */
-
-#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */
+#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000U) /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000U) /*!< Bit0 */
+#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000U) /*!< Bit1 */
+
+#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000U) /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000U) /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000U) /*!< PLL clock output = CKVCO / 4 */
/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */
-#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */
-#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */
-#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
+#define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000U) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
+#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
+#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
+#define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000U) /*!< Bit 3 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000U) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000U) /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000U) /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000U) /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000U) /*!< PLL clock divided */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000U) /*!< LSI selected */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000U) /*!< LSE selected */
+#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000U) /*!< HSI48 clock selected as MCO source */
+
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!< MCO is divided by 8 */
+
+#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
/*!<****************** Bit definition for RCC_CIER register ********************/
-#define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001) /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE ((uint32_t)0x00000002) /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004) /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE ((uint32_t)0x00000008) /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010) /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020) /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIER_LSECSSIE ((uint32_t)0x00000080) /*!< LSE CSS Interrupt Enable */
+#define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE ((uint32_t)0x00000080U) /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
/*!<****************** Bit definition for RCC_CIFR register ********************/
-#define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIFR_LSECSSF ((uint32_t)0x00000080) /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSF ((uint32_t)0x00000100) /*!< Clock Security System Interrupt flag */
+#define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
/*!<****************** Bit definition for RCC_CICR register ********************/
-#define RCC_CICR_LSIRDYC ((uint32_t)0x00000001) /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC ((uint32_t)0x00000002) /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC ((uint32_t)0x00000004) /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC ((uint32_t)0x00000008) /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC ((uint32_t)0x00000010) /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC ((uint32_t)0x00000020) /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_HSI48RDYC ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CICR_LSECSSC ((uint32_t)0x00000080) /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSC ((uint32_t)0x00000100) /*!< Clock Security System Interrupt Clear */
-
+#define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_HSI48RDYC ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
/***************** Bit definition for RCC_IOPRSTR register ******************/
-#define RCC_IOPRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOHRST ((uint32_t)0x00000080) /*!< GPIO port H reset */
+#define RCC_IOPRSTR_IOPARST ((uint32_t)0x00000001U) /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST ((uint32_t)0x00000002U) /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST ((uint32_t)0x00000004U) /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST ((uint32_t)0x00000008U) /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPHRST ((uint32_t)0x00000080U) /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
/****************** Bit definition for RCC_AHBRST register ******************/
-#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x00000001) /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100) /*!< Memory interface reset reset */
-#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
-#define RCC_AHBRSTR_TSCRST ((uint32_t)0x00010000) /*!< TSC reset */
-#define RCC_AHBRSTR_RNGRST ((uint32_t)0x00100000) /*!< RNG reset */
+#define RCC_AHBRSTR_DMARST ((uint32_t)0x00000001U) /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100U) /*!< Memory interface reset reset */
+#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000U) /*!< CRC reset */
+#define RCC_AHBRSTR_TSCRST ((uint32_t)0x00010000U) /*!< TSC reset */
+#define RCC_AHBRSTR_RNGRST ((uint32_t)0x00100000U) /*!< RNG reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
/***************** Bit definition for RCC_APB2RSTR register *****************/
-#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
-#define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004) /*!< TIM21 clock reset */
-#define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020) /*!< TIM22 clock reset */
-#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 clock reset */
-#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
-#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
-#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U) /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004U) /*!< TIM21 clock reset */
+#define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020U) /*!< TIM22 clock reset */
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200U) /*!< ADC1 clock reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U) /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000U) /*!< USART1 clock reset */
+#define RCC_APB2RSTR_DBGRST ((uint32_t)0x00400000U) /*!< DBGMCU clock reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 clock reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU clock reset */
/***************** Bit definition for RCC_APB1RSTR register *****************/
-#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
-#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
-#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD clock reset */
-#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
-#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
-#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
-#define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000) /*!< LPUART1 clock reset */
-#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
-#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
-#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
-#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
-#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
-#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
-#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000) /*!< LPTIM1 clock reset */
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001U) /*!< Timer 2 clock reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010U) /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200U) /*!< LCD clock reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800U) /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000U) /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000U) /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000U) /*!< LPUART1 clock reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000U) /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000U) /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000U) /*!< USB clock reset */
+#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000U) /*!< CRS clock reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000U) /*!< PWR clock reset */
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000U) /*!< DAC clock reset */
+#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000U) /*!< LPTIM1 clock reset */
/***************** Bit definition for RCC_IOPENR register ******************/
-#define RCC_IOPENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOHEN ((uint32_t)0x00000080) /*!< GPIO port H clock enable */
+#define RCC_IOPENR_IOPAEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPDEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enable */
+#define RCC_IOPENR_IOPHEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
/***************** Bit definition for RCC_AHBENR register ******************/
-#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN ((uint32_t)0x00000100) /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
-#define RCC_AHBENR_TSCEN ((uint32_t)0x00010000) /*!< TSC clock enable */
-#define RCC_AHBENR_RNGEN ((uint32_t)0x00100000) /*!< RNG clock enable */
+#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001U) /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000U) /*!< CRC clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x00010000U) /*!< TSC clock enable */
+#define RCC_AHBENR_RNGEN ((uint32_t)0x00100000U) /*!< RNG clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
/***************** Bit definition for RCC_APB2ENR register ******************/
-#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004) /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020) /*!< TIM22 clock enable */
-#define RCC_APB2ENR_MIFIEN ((uint32_t)0x00000080) /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004U) /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020U) /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U) /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200U) /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000U) /*!< USART1 clock enable */
+#define RCC_APB2ENR_DBGEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
/***************** Bit definition for RCC_APB1ENR register ******************/
-#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000) /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
-#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
-#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000) /*!< LPTIM1 clock enable */
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001U) /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010U) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200U) /*!< LCD clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000U) /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000U) /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000U) /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000U) /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000U) /*!< I2C2 clock enable */
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000U) /*!< USB clock enable */
+#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000U) /*!< CRS clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000U) /*!< PWR clock enable */
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000U) /*!< DAC clock enable */
+#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enable */
/****************** Bit definition for RCC_IOPSMENR register ****************/
-#define RCC_IOPSMENR_GPIOASMEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN ((uint32_t)0x00000080) /*!< GPIO port H clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPASMEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
/***************** Bit definition for RCC_AHBSMENR register ******************/
-#define RCC_AHBSMENR_DMA1SMEN ((uint32_t)0x00000001) /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100) /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200) /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_TSCSMEN ((uint32_t)0x00010000) /*!< TSC clock enabled in sleep mode */
-#define RCC_AHBSMENR_RNGSMEN ((uint32_t)0x00100000) /*!< RNG clock enabled in sleep mode */
+#define RCC_AHBSMENR_DMASMEN ((uint32_t)0x00000001U) /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200U) /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000U) /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBSMENR_TSCSMEN ((uint32_t)0x00010000U) /*!< TSC clock enabled in sleep mode */
+#define RCC_AHBSMENR_RNGSMEN ((uint32_t)0x00100000U) /*!< RNG clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
/***************** Bit definition for RCC_APB2SMENR register ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001) /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004) /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020) /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADC1SMEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN ((uint32_t)0x00400000) /*!< DBGMCU clock enabled in sleep mode */
+#define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004U) /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020U) /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN ((uint32_t)0x00000200U) /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U) /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000U) /*!< USART1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
/***************** Bit definition for RCC_APB1SMENR register ******************/
-#define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LCDSMEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN ((uint32_t)0x00004000) /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000) /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000) /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000) /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN ((uint32_t)0x00400000) /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USBSMEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */
-#define RCC_APB1SMENR_CRSSMEN ((uint32_t)0x08000000) /*!< CRS clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000) /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_DACSMEN ((uint32_t)0x20000000) /*!< DAC clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000) /*!< LPTIM1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001U) /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM6SMEN ((uint32_t)0x00000010U) /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LCDSMEN ((uint32_t)0x00000200U) /*!< LCD clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_SPI2SMEN ((uint32_t)0x00004000U) /*!< SPI2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000U) /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000U) /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000U) /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C2SMEN ((uint32_t)0x00400000U) /*!< I2C2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USBSMEN ((uint32_t)0x00800000U) /*!< USB clock enabled in sleep mode */
+#define RCC_APB1SMENR_CRSSMEN ((uint32_t)0x08000000U) /*!< CRS clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000U) /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_DACSMEN ((uint32_t)0x20000000U) /*!< DAC clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enabled in sleep mode */
/******************* Bit definition for RCC_CCIPR register *******************/
/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003) /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003U) /*!< USART1SEL[1:0] bits */
+#define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000C) /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU) /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
+#define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
/*!< LPUART1 Clock source selection */
#define RCC_CCIPR_LPUART1SEL ((uint32_t)0x0000C00) /*!< LPUART1SEL[1:0] bits */
@@ -2420,59 +2630,63 @@
#define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */
/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000) /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U) /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
+#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
/*!< LPTIM1 Clock source selection */
-#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000) /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U) /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
+#define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
/*!< HSI48 Clock source selection */
-#define RCC_CCIPR_HSI48SEL ((uint32_t)0x04000000) /*!< HSI48 RC clock source selection bit for USB and RNG*/
-
-/* Bit name alias maintained for legacy */
+#define RCC_CCIPR_HSI48SEL ((uint32_t)0x04000000U) /*!< HSI48 RC clock source selection bit for USB and RNG*/
+
+/* Legacy defines */
#define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
/******************* Bit definition for RCC_CSR register *******************/
-#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */
+#define RCC_CSR_LSION ((uint32_t)0x00000001U) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002U) /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON ((uint32_t)0x00000100U) /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY ((uint32_t)0x00000200U) /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP ((uint32_t)0x00000400U) /*!< External Low Speed oscillator Bypass */
-#define RCC_CSR_LSEDRV ((uint32_t)0x00001800) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800) /*!< Bit 0 */
-#define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CSR_LSEDRV ((uint32_t)0x00001800U) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
+#define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
-#define RCC_CSR_LSECSSON ((uint32_t)0x00002000) /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD ((uint32_t)0x00004000) /*!< External Low Speed oscillator CSS Detected */
+#define RCC_CSR_LSECSSON ((uint32_t)0x00002000U) /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD ((uint32_t)0x00004000U) /*!< External Low Speed oscillator CSS Detected */
/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define RCC_CSR_RTCSEL ((uint32_t)0x00030000U) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
+#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
-#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000U) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000U) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000U) /*!< HSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCEN ((uint32_t)0x00040000) /*!< RTC clock enable */
-#define RCC_CSR_RTCRST ((uint32_t)0x00080000) /*!< RTC software reset */
-
-#define RCC_CSR_RMVF ((uint32_t)0x00800000) /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF ((uint32_t)0x01000000) /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBL ((uint32_t)0x02000000) /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+#define RCC_CSR_RTCEN ((uint32_t)0x00040000U) /*!< RTC clock enable */
+#define RCC_CSR_RTCRST ((uint32_t)0x00080000U) /*!< RTC software reset */
+
+#define RCC_CSR_RMVF ((uint32_t)0x00800000U) /*!< Remove reset flag */
+#define RCC_CSR_FWRSTF ((uint32_t)0x01000000U) /*!< Mifare Firewall reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000U) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000U) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U) /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
/******************************************************************************/
/* */
@@ -2480,15 +2694,15 @@
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
-#define RNG_CR_RNGEN ((uint32_t)0x00000004)
-#define RNG_CR_IE ((uint32_t)0x00000008)
+#define RNG_CR_RNGEN ((uint32_t)0x00000004U)
+#define RNG_CR_IE ((uint32_t)0x00000008U)
/******************** Bits definition for RNG_SR register *******************/
-#define RNG_SR_DRDY ((uint32_t)0x00000001)
-#define RNG_SR_CECS ((uint32_t)0x00000002)
-#define RNG_SR_SECS ((uint32_t)0x00000004)
-#define RNG_SR_CEIS ((uint32_t)0x00000020)
-#define RNG_SR_SEIS ((uint32_t)0x00000040)
+#define RNG_SR_DRDY ((uint32_t)0x00000001U)
+#define RNG_SR_CECS ((uint32_t)0x00000002U)
+#define RNG_SR_SECS ((uint32_t)0x00000004U)
+#define RNG_SR_CEIS ((uint32_t)0x00000020U)
+#define RNG_SR_SEIS ((uint32_t)0x00000040U)
/******************************************************************************/
/* */
@@ -2496,339 +2710,357 @@
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
-#define RTC_TR_PM ((uint32_t)0x00400000) /*!< */
-#define RTC_TR_HT ((uint32_t)0x00300000) /*!< */
-#define RTC_TR_HT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_TR_HT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_TR_HU ((uint32_t)0x000F0000) /*!< */
-#define RTC_TR_HU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_TR_HU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_TR_HU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_TR_HU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_TR_MNT ((uint32_t)0x00007000) /*!< */
-#define RTC_TR_MNT_0 ((uint32_t)0x00001000) /*!< */
-#define RTC_TR_MNT_1 ((uint32_t)0x00002000) /*!< */
-#define RTC_TR_MNT_2 ((uint32_t)0x00004000) /*!< */
-#define RTC_TR_MNU ((uint32_t)0x00000F00) /*!< */
-#define RTC_TR_MNU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TR_MNU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TR_MNU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TR_MNU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_TR_ST ((uint32_t)0x00000070) /*!< */
-#define RTC_TR_ST_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_TR_ST_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_TR_ST_2 ((uint32_t)0x00000040) /*!< */
-#define RTC_TR_SU ((uint32_t)0x0000000F) /*!< */
-#define RTC_TR_SU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_TR_SU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_TR_SU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_TR_SU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_TR_PM ((uint32_t)0x00400000U) /*!< */
+#define RTC_TR_HT ((uint32_t)0x00300000U) /*!< */
+#define RTC_TR_HT_0 ((uint32_t)0x00100000U) /*!< */
+#define RTC_TR_HT_1 ((uint32_t)0x00200000U) /*!< */
+#define RTC_TR_HU ((uint32_t)0x000F0000U) /*!< */
+#define RTC_TR_HU_0 ((uint32_t)0x00010000U) /*!< */
+#define RTC_TR_HU_1 ((uint32_t)0x00020000U) /*!< */
+#define RTC_TR_HU_2 ((uint32_t)0x00040000U) /*!< */
+#define RTC_TR_HU_3 ((uint32_t)0x00080000U) /*!< */
+#define RTC_TR_MNT ((uint32_t)0x00007000U) /*!< */
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000U) /*!< */
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000U) /*!< */
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000U) /*!< */
+#define RTC_TR_MNU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_TR_ST ((uint32_t)0x00000070U) /*!< */
+#define RTC_TR_ST_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_TR_ST_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_TR_ST_2 ((uint32_t)0x00000040U) /*!< */
+#define RTC_TR_SU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_TR_SU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_TR_SU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_TR_SU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_TR_SU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_DR register *******************/
-#define RTC_DR_YT ((uint32_t)0x00F00000) /*!< */
-#define RTC_DR_YT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_DR_YT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_DR_YT_2 ((uint32_t)0x00400000) /*!< */
-#define RTC_DR_YT_3 ((uint32_t)0x00800000) /*!< */
-#define RTC_DR_YU ((uint32_t)0x000F0000) /*!< */
-#define RTC_DR_YU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_DR_YU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_DR_YU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_DR_YU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_DR_WDU ((uint32_t)0x0000E000) /*!< */
-#define RTC_DR_WDU_0 ((uint32_t)0x00002000) /*!< */
-#define RTC_DR_WDU_1 ((uint32_t)0x00004000) /*!< */
-#define RTC_DR_WDU_2 ((uint32_t)0x00008000) /*!< */
-#define RTC_DR_MT ((uint32_t)0x00001000) /*!< */
-#define RTC_DR_MU ((uint32_t)0x00000F00) /*!< */
-#define RTC_DR_MU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_DR_MU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_DR_MU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_DR_MU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_DR_DT ((uint32_t)0x00000030) /*!< */
-#define RTC_DR_DT_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_DR_DT_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_DR_DU ((uint32_t)0x0000000F) /*!< */
-#define RTC_DR_DU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_DR_DU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_DR_DU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_DR_DU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_DR_YT ((uint32_t)0x00F00000U) /*!< */
+#define RTC_DR_YT_0 ((uint32_t)0x00100000U) /*!< */
+#define RTC_DR_YT_1 ((uint32_t)0x00200000U) /*!< */
+#define RTC_DR_YT_2 ((uint32_t)0x00400000U) /*!< */
+#define RTC_DR_YT_3 ((uint32_t)0x00800000U) /*!< */
+#define RTC_DR_YU ((uint32_t)0x000F0000U) /*!< */
+#define RTC_DR_YU_0 ((uint32_t)0x00010000U) /*!< */
+#define RTC_DR_YU_1 ((uint32_t)0x00020000U) /*!< */
+#define RTC_DR_YU_2 ((uint32_t)0x00040000U) /*!< */
+#define RTC_DR_YU_3 ((uint32_t)0x00080000U) /*!< */
+#define RTC_DR_WDU ((uint32_t)0x0000E000U) /*!< */
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000U) /*!< */
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000U) /*!< */
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000U) /*!< */
+#define RTC_DR_MT ((uint32_t)0x00001000U) /*!< */
+#define RTC_DR_MU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_DR_MU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_DR_MU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_DR_MU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_DR_MU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_DR_DT ((uint32_t)0x00000030U) /*!< */
+#define RTC_DR_DT_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_DR_DT_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_DR_DU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_DR_DU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_DR_DU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_DR_DU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_DR_DU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_CR register *******************/
-#define RTC_CR_COE ((uint32_t)0x00800000) /*!< */
-#define RTC_CR_OSEL ((uint32_t)0x00600000) /*!< */
-#define RTC_CR_OSEL_0 ((uint32_t)0x00200000) /*!< */
-#define RTC_CR_OSEL_1 ((uint32_t)0x00400000) /*!< */
-#define RTC_CR_POL ((uint32_t)0x00100000) /*!< */
-#define RTC_CR_COSEL ((uint32_t)0x00080000) /*!< */
-#define RTC_CR_BCK ((uint32_t)0x00040000) /*!< */
-#define RTC_CR_SUB1H ((uint32_t)0x00020000) /*!< */
-#define RTC_CR_ADD1H ((uint32_t)0x00010000) /*!< */
-#define RTC_CR_TSIE ((uint32_t)0x00008000) /*!< */
-#define RTC_CR_WUTIE ((uint32_t)0x00004000) /*!< */
-#define RTC_CR_ALRBIE ((uint32_t)0x00002000) /*!< */
-#define RTC_CR_ALRAIE ((uint32_t)0x00001000) /*!< */
-#define RTC_CR_TSE ((uint32_t)0x00000800) /*!< */
-#define RTC_CR_WUTE ((uint32_t)0x00000400) /*!< */
-#define RTC_CR_ALRBE ((uint32_t)0x00000200) /*!< */
-#define RTC_CR_ALRAE ((uint32_t)0x00000100) /*!< */
-#define RTC_CR_FMT ((uint32_t)0x00000040) /*!< */
-#define RTC_CR_BYPSHAD ((uint32_t)0x00000020) /*!< */
-#define RTC_CR_REFCKON ((uint32_t)0x00000010) /*!< */
-#define RTC_CR_TSEDGE ((uint32_t)0x00000008) /*!< */
-#define RTC_CR_WUCKSEL ((uint32_t)0x00000007) /*!< */
-#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) /*!< */
+#define RTC_CR_COE ((uint32_t)0x00800000U) /*!< */
+#define RTC_CR_OSEL ((uint32_t)0x00600000U) /*!< */
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000U) /*!< */
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000U) /*!< */
+#define RTC_CR_POL ((uint32_t)0x00100000U) /*!< */
+#define RTC_CR_COSEL ((uint32_t)0x00080000U) /*!< */
+#define RTC_CR_BCK ((uint32_t)0x00040000U) /*!< */
+#define RTC_CR_SUB1H ((uint32_t)0x00020000U) /*!< */
+#define RTC_CR_ADD1H ((uint32_t)0x00010000U) /*!< */
+#define RTC_CR_TSIE ((uint32_t)0x00008000U) /*!< */
+#define RTC_CR_WUTIE ((uint32_t)0x00004000U) /*!< */
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000U) /*!< */
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000U) /*!< */
+#define RTC_CR_TSE ((uint32_t)0x00000800U) /*!< */
+#define RTC_CR_WUTE ((uint32_t)0x00000400U) /*!< */
+#define RTC_CR_ALRBE ((uint32_t)0x00000200U) /*!< */
+#define RTC_CR_ALRAE ((uint32_t)0x00000100U) /*!< */
+#define RTC_CR_FMT ((uint32_t)0x00000040U) /*!< */
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020U) /*!< */
+#define RTC_CR_REFCKON ((uint32_t)0x00000010U) /*!< */
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008U) /*!< */
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007U) /*!< */
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U) /*!< */
/******************** Bits definition for RTC_ISR register ******************/
-#define RTC_ISR_RECALPF ((uint32_t)0x00010000) /*!< */
-#define RTC_ISR_TAMP2F ((uint32_t)0x00004000) /*!< */
-#define RTC_ISR_TAMP1F ((uint32_t)0x00002000) /*!< */
-#define RTC_ISR_TSOVF ((uint32_t)0x00001000) /*!< */
-#define RTC_ISR_TSF ((uint32_t)0x00000800) /*!< */
-#define RTC_ISR_WUTF ((uint32_t)0x00000400) /*!< */
-#define RTC_ISR_ALRBF ((uint32_t)0x00000200) /*!< */
-#define RTC_ISR_ALRAF ((uint32_t)0x00000100) /*!< */
-#define RTC_ISR_INIT ((uint32_t)0x00000080) /*!< */
-#define RTC_ISR_INITF ((uint32_t)0x00000040) /*!< */
-#define RTC_ISR_RSF ((uint32_t)0x00000020) /*!< */
-#define RTC_ISR_INITS ((uint32_t)0x00000010) /*!< */
-#define RTC_ISR_SHPF ((uint32_t)0x00000008) /*!< */
-#define RTC_ISR_WUTWF ((uint32_t)0x00000004) /*!< */
-#define RTC_ISR_ALRBWF ((uint32_t)0x00000002) /*!< */
-#define RTC_ISR_ALRAWF ((uint32_t)0x00000001) /*!< */
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000U) /*!< */
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000U) /*!< */
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000U) /*!< */
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000U) /*!< */
+#define RTC_ISR_TSF ((uint32_t)0x00000800U) /*!< */
+#define RTC_ISR_WUTF ((uint32_t)0x00000400U) /*!< */
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200U) /*!< */
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100U) /*!< */
+#define RTC_ISR_INIT ((uint32_t)0x00000080U) /*!< */
+#define RTC_ISR_INITF ((uint32_t)0x00000040U) /*!< */
+#define RTC_ISR_RSF ((uint32_t)0x00000020U) /*!< */
+#define RTC_ISR_INITS ((uint32_t)0x00000010U) /*!< */
+#define RTC_ISR_SHPF ((uint32_t)0x00000008U) /*!< */
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004U) /*!< */
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002U) /*!< */
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001U) /*!< */
/******************** Bits definition for RTC_PRER register *****************/
-#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) /*!< */
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) /*!< */
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U) /*!< */
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU) /*!< */
/******************** Bits definition for RTC_WUTR register *****************/
-#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU)
/******************** Bits definition for RTC_ALRMAR register ***************/
-#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) /*!< */
-#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) /*!< */
-#define RTC_ALRMAR_DT ((uint32_t)0x30000000) /*!< */
-#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) /*!< */
-#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) /*!< */
-#define RTC_ALRMAR_DU ((uint32_t)0x0F000000) /*!< */
-#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) /*!< */
-#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) /*!< */
-#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) /*!< */
-#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) /*!< */
-#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) /*!< */
-#define RTC_ALRMAR_PM ((uint32_t)0x00400000) /*!< */
-#define RTC_ALRMAR_HT ((uint32_t)0x00300000) /*!< */
-#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_ALRMAR_HU ((uint32_t)0x000F0000) /*!< */
-#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) /*!< */
-#define RTC_ALRMAR_MNT ((uint32_t)0x00007000) /*!< */
-#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) /*!< */
-#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) /*!< */
-#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) /*!< */
-#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) /*!< */
-#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) /*!< */
-#define RTC_ALRMAR_ST ((uint32_t)0x00000070) /*!< */
-#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) /*!< */
-#define RTC_ALRMAR_SU ((uint32_t)0x0000000F) /*!< */
-#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U) /*!< */
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U) /*!< */
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000U) /*!< */
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U) /*!< */
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U) /*!< */
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000U) /*!< */
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U) /*!< */
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U) /*!< */
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U) /*!< */
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U) /*!< */
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U) /*!< */
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000U) /*!< */
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000U) /*!< */
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U) /*!< */
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U) /*!< */
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000U) /*!< */
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U) /*!< */
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U) /*!< */
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U) /*!< */
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U) /*!< */
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U) /*!< */
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000U) /*!< */
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U) /*!< */
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U) /*!< */
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U) /*!< */
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U) /*!< */
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070U) /*!< */
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U) /*!< */
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_ALRMBR register ***************/
-#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) /*!< */
-#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) /*!< */
-#define RTC_ALRMBR_DT ((uint32_t)0x30000000) /*!< */
-#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) /*!< */
-#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) /*!< */
-#define RTC_ALRMBR_DU ((uint32_t)0x0F000000) /*!< */
-#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) /*!< */
-#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) /*!< */
-#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) /*!< */
-#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) /*!< */
-#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) /*!< */
-#define RTC_ALRMBR_PM ((uint32_t)0x00400000) /*!< */
-#define RTC_ALRMBR_HT ((uint32_t)0x00300000) /*!< */
-#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_ALRMBR_HU ((uint32_t)0x000F0000) /*!< */
-#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) /*!< */
-#define RTC_ALRMBR_MNT ((uint32_t)0x00007000) /*!< */
-#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) /*!< */
-#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) /*!< */
-#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) /*!< */
-#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) /*!< */
-#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) /*!< */
-#define RTC_ALRMBR_ST ((uint32_t)0x00000070) /*!< */
-#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) /*!< */
-#define RTC_ALRMBR_SU ((uint32_t)0x0000000F) /*!< */
-#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U) /*!< */
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U) /*!< */
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000U) /*!< */
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U) /*!< */
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U) /*!< */
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000U) /*!< */
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U) /*!< */
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U) /*!< */
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U) /*!< */
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U) /*!< */
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U) /*!< */
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000U) /*!< */
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000U) /*!< */
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U) /*!< */
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U) /*!< */
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000U) /*!< */
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U) /*!< */
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U) /*!< */
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U) /*!< */
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U) /*!< */
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U) /*!< */
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000U) /*!< */
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U) /*!< */
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U) /*!< */
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U) /*!< */
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U) /*!< */
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070U) /*!< */
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U) /*!< */
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_WPR register ******************/
-#define RTC_WPR_KEY ((uint32_t)0x000000FF) /*!< */
+#define RTC_WPR_KEY ((uint32_t)0x000000FFU) /*!< */
/******************** Bits definition for RTC_SSR register ******************/
-#define RTC_SSR_SS ((uint32_t)0x0000FFFF) /*!< */
+#define RTC_SSR_SS ((uint32_t)0x0000FFFFU) /*!< */
/******************** Bits definition for RTC_SHIFTR register ***************/
-#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) /*!< */
-#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) /*!< */
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU) /*!< */
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U) /*!< */
/******************** Bits definition for RTC_TSTR register *****************/
-#define RTC_TSTR_PM ((uint32_t)0x00400000) /*!< */
-#define RTC_TSTR_HT ((uint32_t)0x00300000) /*!< */
-#define RTC_TSTR_HT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_TSTR_HT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_TSTR_HU ((uint32_t)0x000F0000) /*!< */
-#define RTC_TSTR_HU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_TSTR_HU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_TSTR_HU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_TSTR_HU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_TSTR_MNT ((uint32_t)0x00007000) /*!< */
-#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) /*!< */
-#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) /*!< */
-#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) /*!< */
-#define RTC_TSTR_MNU ((uint32_t)0x00000F00) /*!< */
-#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_TSTR_ST ((uint32_t)0x00000070) /*!< */
-#define RTC_TSTR_ST_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_TSTR_ST_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_TSTR_ST_2 ((uint32_t)0x00000040) /*!< */
-#define RTC_TSTR_SU ((uint32_t)0x0000000F) /*!< */
-#define RTC_TSTR_SU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_TSTR_SU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_TSTR_SU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_TSTR_SU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_TSTR_PM ((uint32_t)0x00400000U) /*!< */
+#define RTC_TSTR_HT ((uint32_t)0x00300000U) /*!< */
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000U) /*!< */
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000U) /*!< */
+#define RTC_TSTR_HU ((uint32_t)0x000F0000U) /*!< */
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000U) /*!< */
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000U) /*!< */
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000U) /*!< */
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000U) /*!< */
+#define RTC_TSTR_MNT ((uint32_t)0x00007000U) /*!< */
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U) /*!< */
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U) /*!< */
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U) /*!< */
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_TSTR_ST ((uint32_t)0x00000070U) /*!< */
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040U) /*!< */
+#define RTC_TSTR_SU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_TSDR register *****************/
-#define RTC_TSDR_WDU ((uint32_t)0x0000E000) /*!< */
-#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) /*!< */
-#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) /*!< */
-#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) /*!< */
-#define RTC_TSDR_MT ((uint32_t)0x00001000) /*!< */
-#define RTC_TSDR_MU ((uint32_t)0x00000F00) /*!< */
-#define RTC_TSDR_MU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TSDR_MU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TSDR_MU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TSDR_MU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_TSDR_DT ((uint32_t)0x00000030) /*!< */
-#define RTC_TSDR_DT_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_TSDR_DT_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_TSDR_DU ((uint32_t)0x0000000F) /*!< */
-#define RTC_TSDR_DU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_TSDR_DU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_TSDR_DU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_TSDR_DU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000U) /*!< */
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U) /*!< */
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U) /*!< */
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U) /*!< */
+#define RTC_TSDR_MT ((uint32_t)0x00001000U) /*!< */
+#define RTC_TSDR_MU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_TSDR_DT ((uint32_t)0x00000030U) /*!< */
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_TSDR_DU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_TSSSR register ****************/
-#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
-
-/******************** Bits definition for RTC_CAL register *****************/
-#define RTC_CAL_CALP ((uint32_t)0x00008000) /*!< */
-#define RTC_CAL_CALW8 ((uint32_t)0x00004000) /*!< */
-#define RTC_CAL_CALW16 ((uint32_t)0x00002000) /*!< */
-#define RTC_CAL_CALM ((uint32_t)0x000001FF) /*!< */
-#define RTC_CAL_CALM_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_CAL_CALM_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_CAL_CALM_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_CAL_CALM_3 ((uint32_t)0x00000008) /*!< */
-#define RTC_CAL_CALM_4 ((uint32_t)0x00000010) /*!< */
-#define RTC_CAL_CALM_5 ((uint32_t)0x00000020) /*!< */
-#define RTC_CAL_CALM_6 ((uint32_t)0x00000040) /*!< */
-#define RTC_CAL_CALM_7 ((uint32_t)0x00000080) /*!< */
-#define RTC_CAL_CALM_8 ((uint32_t)0x00000100) /*!< */
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU)
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000U) /*!< */
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000U) /*!< */
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000U) /*!< */
+#define RTC_CALR_CALM ((uint32_t)0x000001FFU) /*!< */
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008U) /*!< */
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010U) /*!< */
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020U) /*!< */
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040U) /*!< */
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080U) /*!< */
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100U) /*!< */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
/******************** Bits definition for RTC_TAMPCR register ****************/
-#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000) /*!< */
-#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000) /*!< */
-#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000) /*!< */
-#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000) /*!< */
-#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000) /*!< */
-#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000) /*!< */
-#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000) /*!< */
-#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000) /*!< */
-#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000) /*!< */
-#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000) /*!< */
-#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800) /*!< */
-#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800) /*!< */
-#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000) /*!< */
-#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700) /*!< */
-#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080) /*!< */
-#define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010) /*!< */
-#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008) /*!< */
-#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004) /*!< */
-#define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002) /*!< */
-#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001) /*!< */
+#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U) /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U) /*!< */
+#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U) /*!< */
+#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000U) /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000U) /*!< */
+#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000U) /*!< */
+#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U) /*!< */
+#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U) /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U) /*!< */
+#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U) /*!< */
+#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U) /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U) /*!< */
+#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U) /*!< */
+#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U) /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U) /*!< */
+#define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U) /*!< */
+#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U) /*!< */
+#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U) /*!< */
+#define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002U) /*!< */
+#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001U) /*!< */
/******************** Bits definition for RTC_ALRMASSR register *************/
-#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU)
/******************** Bits definition for RTC_ALRMBSSR register *************/
-#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU)
/******************** Bits definition for RTC_OR register ****************/
-#define RTC_OR_OUT_RMP ((uint32_t)0x00000002) /*!< */
-#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001) /*!< */
-
-/* Bit names aliases maintained for legacy */
+#define RTC_OR_OUT_RMP ((uint32_t)0x00000002U) /*!< */
+#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U) /*!< */
+
+/* Legacy defines */
#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
/******************** Bits definition for RTC_BKP0R register ****************/
-#define RTC_BKP0R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFFU) /*!< */
/******************** Bits definition for RTC_BKP1R register ****************/
-#define RTC_BKP1R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFFU) /*!< */
/******************** Bits definition for RTC_BKP2R register ****************/
-#define RTC_BKP2R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFFU) /*!< */
/******************** Bits definition for RTC_BKP3R register ****************/
-#define RTC_BKP3R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFFU) /*!< */
/******************** Bits definition for RTC_BKP4R register ****************/
-#define RTC_BKP4R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFFU) /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER ((uint32_t)0x00000005U) /*!< */
/******************************************************************************/
/* */
@@ -2836,75 +3068,75 @@
/* */
/******************************************************************************/
/******************* Bit definition for SPI_CR1 register ********************/
-#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
-#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
-#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
-#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
-#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
-#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
-#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
-#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+#define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!< Master Selection */
+#define SPI_CR1_BR ((uint32_t)0x00000038U) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
+#define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!< Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800U) /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!< Bidirectional data mode enable */
/******************* Bit definition for SPI_CR2 register ********************/
-#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
-#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */
/******************** Bit definition for SPI_SR register ********************/
-#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
-#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
-#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
-#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
-#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
-#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
-#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
+#define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100U) /*!< TI frame format error */
/******************** Bit definition for SPI_DR register ********************/
-#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
+#define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!< Data Register */
/******************* Bit definition for SPI_CRCPR register ******************/
-#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!< CRC polynomial register */
/****************** Bit definition for SPI_RXCRCR register ******************/
-#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!< Rx CRC Register */
/****************** Bit definition for SPI_TXCRCR register ******************/
-#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!< Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register *****************/
-#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
-#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
-#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001U) /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006U) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002U) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004U) /*!<Bit 1 */
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008U) /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030U) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080U) /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300U) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400U) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800U) /*!<I2S mode selection */
/****************** Bit definition for SPI_I2SPR register *******************/
-#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FFU) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100U) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200U) /*!<Master Clock Output Enable */
/******************************************************************************/
/* */
@@ -2912,183 +3144,183 @@
/* */
/******************************************************************************/
/***************** Bit definition for SYSCFG_CFGR1 register ****************/
-#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
-#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
-#define SYSCFG_CFGR1_BOOT_MODE ((uint32_t)0x00000300) /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MOD_0 ((uint32_t)0x00000100) /*!< SYSCFG_Boot mode Config Bit 0 */
-#define SYSCFG_CFGR1_BOOT_MODE_1 ((uint32_t)0x00000200) /*!< SYSCFG_Boot mode Config Bit 1 */
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003U) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001U) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002U) /*!< SYSCFG_Memory Remap Config Bit 1 */
+#define SYSCFG_CFGR1_BOOT_MODE ((uint32_t)0x00000300U) /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 ((uint32_t)0x00000100U) /*!< SYSCFG_Boot mode Config Bit 0 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 ((uint32_t)0x00000200U) /*!< SYSCFG_Boot mode Config Bit 1 */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
-#define SYSCFG_CFGR2_FWDISEN ((uint32_t)0x00000001) /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_CAPA ((uint32_t)0x0000000E) /*!< Connection of internal Vlcd rail to external capacitors */
-#define SYSCFG_CFGR2_CAPA_0 ((uint32_t)0x00000002)
-#define SYSCFG_CFGR2_CAPA_1 ((uint32_t)0x00000004)
-#define SYSCFG_CFGR2_CAPA_2 ((uint32_t)0x00000008)
-#define SYSCFG_CFGR2_I2C_PB6_FMP ((uint32_t)0x00000100) /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP ((uint32_t)0x00000200) /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP ((uint32_t)0x00000400) /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP ((uint32_t)0x00000800) /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP ((uint32_t)0x00001000) /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP ((uint32_t)0x00002000) /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR2_FWDISEN ((uint32_t)0x00000001U) /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_CAPA ((uint32_t)0x0000000EU) /*!< Connection of internal Vlcd rail to external capacitors */
+#define SYSCFG_CFGR2_CAPA_0 ((uint32_t)0x00000002U)
+#define SYSCFG_CFGR2_CAPA_1 ((uint32_t)0x00000004U)
+#define SYSCFG_CFGR2_CAPA_2 ((uint32_t)0x00000008U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP ((uint32_t)0x00000100U) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP ((uint32_t)0x00000200U) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP ((uint32_t)0x00000400U) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP ((uint32_t)0x00000800U) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP ((uint32_t)0x00001000U) /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR2_I2C2_FMP ((uint32_t)0x00002000U) /*!< I2C2 Fast mode plus */
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
-#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000FU) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0U) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00U) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000U) /*!< EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
-#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005) /*!< PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005U) /*!< PH[0] pin */
/**
* @brief EXTI1 configuration
*/
-#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050) /*!< PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050U) /*!< PH[1] pin */
/**
* @brief EXTI2 configuration
*/
-#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300U) /*!< PD[2] pin */
/**
* @brief EXTI3 configuration
*/
-#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000U) /*!< PC[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
-#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000FU) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0U) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00U) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000U) /*!< EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
-#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002U) /*!< PC[4] pin */
/**
* @brief EXTI5 configuration
*/
-#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020U) /*!< PC[5] pin */
/**
* @brief EXTI6 configuration
*/
-#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200U) /*!< PC[6] pin */
/**
* @brief EXTI7 configuration
*/
-#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000U) /*!< PC[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
-#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000FU) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0U) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00U) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000U) /*!< EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
-#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002U) /*!< PC[8] pin */
/**
* @brief EXTI9 configuration
*/
-#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020U) /*!< PC[9] pin */
/**
* @brief EXTI10 configuration
*/
-#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200U) /*!< PC[10] pin */
/**
* @brief EXTI11 configuration
*/
-#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000U) /*!< PC[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
-#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000FU) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0U) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00U) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000U) /*!< EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
-#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002U) /*!< PC[12] pin */
/**
* @brief EXTI13 configuration
*/
-#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020U) /*!< PC[13] pin */
/**
* @brief EXTI14 configuration
*/
-#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200U) /*!< PC[14] pin */
/**
* @brief EXTI15 configuration
*/
-#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000U) /*!< PC[15] pin */
/***************** Bit definition for SYSCFG_CFGR3 register ****************/
-#define SYSCFG_CFGR3_EN_VREFINT ((uint32_t)0x00000001) /*!< Vref Enable bit*/
-#define SYSCFG_CFGR3_VREF_OUT ((uint32_t)0x00000030) /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define SYSCFG_CFGR3_VREF_OUT_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC ((uint32_t)0x00000100) /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC ((uint32_t)0x00000200) /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ((uint32_t)0x00001000) /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_ENREF_HSI48 ((uint32_t)0x00002000) /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
-#define SYSCFG_CFGR3_REF_HSI48_RDYF ((uint32_t)0x04000000) /*!< VREFINT for 48 MHz RC oscillator ready flag */
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF ((uint32_t)0x08000000) /*!< Sensor for ADC ready flag */
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF ((uint32_t)0x10000000) /*!< VREFINT for ADC ready flag */
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF ((uint32_t)0x20000000) /*!< VREFINT for comparator ready flag */
-#define SYSCFG_CFGR3_VREFINT_RDYF ((uint32_t)0x40000000) /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK ((uint32_t)0x80000000) /*!< CFGR3 lock bit */
-
-/* Bit names aliases maintained for legacy */
+#define SYSCFG_CFGR3_EN_VREFINT ((uint32_t)0x00000001U) /*!< Vref Enable bit*/
+#define SYSCFG_CFGR3_VREF_OUT ((uint32_t)0x00000030U) /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
+#define SYSCFG_CFGR3_VREF_OUT_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC ((uint32_t)0x00000100U) /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC ((uint32_t)0x00000200U) /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ((uint32_t)0x00001000U) /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_ENREF_HSI48 ((uint32_t)0x00002000U) /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
+#define SYSCFG_CFGR3_REF_HSI48_RDYF ((uint32_t)0x04000000U) /*!< VREFINT for 48 MHz RC oscillator ready flag */
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF ((uint32_t)0x08000000U) /*!< Sensor for ADC ready flag */
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF ((uint32_t)0x10000000U) /*!< VREFINT for ADC ready flag */
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF ((uint32_t)0x20000000U) /*!< VREFINT for comparator ready flag */
+#define SYSCFG_CFGR3_VREFINT_RDYF ((uint32_t)0x40000000U) /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK ((uint32_t)0x80000000U) /*!< CFGR3 lock bit */
+
+/* Legacy defines */
#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
@@ -3102,315 +3334,285 @@
/* Timers (TIM) */
/* */
/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
/******************* Bit definition for TIM_CR1 register ********************/
-#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
-#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
-#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
-#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
-#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
-
-#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-
-#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_CR1_CEN ((uint32_t)0x00000001U) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002U) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004U) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008U) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010U) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060U) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080U) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300U) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
/******************* Bit definition for TIM_CR2 register ********************/
-#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-
-#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
-#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008U) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070U) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080U) /*!<TI1 Selection */
/******************* Bit definition for TIM_SMCR register *******************/
-#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-
-#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-
-#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-
-#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-
-#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
-#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+#define TIM_SMCR_SMS ((uint32_t)0x00000007U) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008U) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070U) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080U) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00U) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000U) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000U) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000U) /*!<External trigger polarity */
/******************* Bit definition for TIM_DIER register *******************/
-#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+#define TIM_DIER_UIE ((uint32_t)0x00000001U) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040U) /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100U) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200U) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400U) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800U) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000U) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000U) /*!<Trigger DMA request enable */
/******************** Bit definition for TIM_SR register ********************/
-#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
-#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
-#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_UIF ((uint32_t)0x00000001U) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040U) /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200U) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400U) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000U) /*!<Capture/Compare 4 Overcapture Flag */
/******************* Bit definition for TIM_EGR register ********************/
-#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
-#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
-#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+#define TIM_EGR_UG ((uint32_t)0x00000001U) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002U) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004U) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008U) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010U) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040U) /*!<Trigger Generation */
/****************** Bit definition for TIM_CCMR1 register *******************/
-#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003U) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004U) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008U) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00000070U) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080U) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300U) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400U) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800U) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x00007000U) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000U) /*!<Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
-#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-
-#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000CU) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0U) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00U) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000U) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
/****************** Bit definition for TIM_CCMR2 register *******************/
-#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003U) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004U) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008U) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00000070U) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080U) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300U) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400U) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800U) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x00007000U) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000U) /*!<Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
-#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-
-#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000CU) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0U) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00U) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000U) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
/******************* Bit definition for TIM_CCER register *******************/
-#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC1E ((uint32_t)0x00000001U) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002U) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008U) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010U) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020U) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080U) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100U) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200U) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000U) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000U) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000U) /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
-#define TIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!<Counter Value */
+#define TIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!<Counter Value */
/******************* Bit definition for TIM_PSC register ********************/
-#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFFU) /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
-#define TIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!<actual auto-reload Value */
-
-/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+#define TIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_CCR1 register *******************/
-#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
-#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
-#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
-#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
-
-/******************* Bit definition for TIM_BDTR register *******************/
-#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
-
-#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-
-#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
-#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
-#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
-#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_DCR register ********************/
-#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-
-#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define TIM_DCR_DBA ((uint32_t)0x0000001FU) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00U) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
/******************* Bit definition for TIM_DMAR register *******************/
-#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFFU) /*!<DMA register for burst accesses */
/******************* Bit definition for TIM_OR register *********************/
-#define TIM2_OR_ETR_RMP ((uint32_t)0x00000007) /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM2_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM2_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM2_OR_ETR_RMP ((uint32_t)0x00000007U) /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM2_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM2_OR_ETR_RMP_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
#define TIM2_OR_TI4_RMP ((uint32_t)0x0000018) /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0 ((uint32_t)0x00000008) /*!<Bit 0 */
-#define TIM2_OR_TI4_RMP_1 ((uint32_t)0x00000010) /*!<Bit 1 */
-
-#define TIM21_OR_ETR_RMP ((uint32_t)0x00000003) /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM21_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM21_OR_TI1_RMP ((uint32_t)0x0000001C) /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define TIM21_OR_TI1_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
-#define TIM21_OR_TI1_RMP_2 ((uint32_t)0x00000010) /*!<Bit 2 */
-#define TIM21_OR_TI2_RMP ((uint32_t)0x00000020) /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP ((uint32_t)0x00000003) /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM22_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM22_OR_TI1_RMP ((uint32_t)0x0000000C) /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+#define TIM2_OR_TI4_RMP_0 ((uint32_t)0x00000008U) /*!<Bit 0 */
+#define TIM2_OR_TI4_RMP_1 ((uint32_t)0x00000010U) /*!<Bit 1 */
+
+#define TIM21_OR_ETR_RMP ((uint32_t)0x00000003U) /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM21_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM21_OR_TI1_RMP ((uint32_t)0x0000001CU) /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
+#define TIM21_OR_TI1_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
+#define TIM21_OR_TI1_RMP_2 ((uint32_t)0x00000010U) /*!<Bit 2 */
+#define TIM21_OR_TI2_RMP ((uint32_t)0x00000020U) /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP ((uint32_t)0x00000003U) /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM22_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM22_OR_TI1_RMP ((uint32_t)0x0000000CU) /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
+#define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
/******************************************************************************/
@@ -3419,375 +3621,381 @@
/* */
/******************************************************************************/
/******************* Bit definition for TSC_CR register *********************/
-#define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
-#define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
-#define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
-
-#define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
-
-#define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-
-#define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
-#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
-#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
-#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
-#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
-#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
-#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
-
-#define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-
-#define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
-#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
-#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
+#define TSC_CR_TSCE ((uint32_t)0x00000001U) /*!<Touch sensing controller enable */
+#define TSC_CR_START ((uint32_t)0x00000002U) /*!<Start acquisition */
+#define TSC_CR_AM ((uint32_t)0x00000004U) /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL ((uint32_t)0x00000008U) /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF ((uint32_t)0x00000010U) /*!<IO default mode */
+
+#define TSC_CR_MCV ((uint32_t)0x000000E0U) /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
+#define TSC_CR_MCV_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
+#define TSC_CR_MCV_2 ((uint32_t)0x00000080U) /*!<Bit 2 */
+
+#define TSC_CR_PGPSC ((uint32_t)0x00007000U) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
+
+#define TSC_CR_SSPSC ((uint32_t)0x00008000U) /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE ((uint32_t)0x00010000U) /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD ((uint32_t)0x00FE0000U) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
+#define TSC_CR_SSD_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
+#define TSC_CR_SSD_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
+#define TSC_CR_SSD_3 ((uint32_t)0x00100000U) /*!<Bit 3 */
+#define TSC_CR_SSD_4 ((uint32_t)0x00200000U) /*!<Bit 4 */
+#define TSC_CR_SSD_5 ((uint32_t)0x00400000U) /*!<Bit 5 */
+#define TSC_CR_SSD_6 ((uint32_t)0x00800000U) /*!<Bit 6 */
+
+#define TSC_CR_CTPL ((uint32_t)0x0F000000U) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
+#define TSC_CR_CTPL_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
+#define TSC_CR_CTPL_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
+#define TSC_CR_CTPL_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
+
+#define TSC_CR_CTPH ((uint32_t)0xF0000000U) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
+#define TSC_CR_CTPH_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
+#define TSC_CR_CTPH_2 ((uint32_t)0x40000000U) /*!<Bit 2 */
+#define TSC_CR_CTPH_3 ((uint32_t)0x80000000U) /*!<Bit 3 */
/******************* Bit definition for TSC_IER register ********************/
-#define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
+#define TSC_IER_EOAIE ((uint32_t)0x00000001U) /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE ((uint32_t)0x00000002U) /*!<Max count error interrupt enable */
/******************* Bit definition for TSC_ICR register ********************/
-#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
+#define TSC_ICR_EOAIC ((uint32_t)0x00000001U) /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC ((uint32_t)0x00000002U) /*!<Max count error interrupt clear */
/******************* Bit definition for TSC_ISR register ********************/
-#define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
-#define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
+#define TSC_ISR_EOAF ((uint32_t)0x00000001U) /*!<End of acquisition flag */
+#define TSC_ISR_MCEF ((uint32_t)0x00000002U) /*!<Max count error flag */
/******************* Bit definition for TSC_IOHCR register ******************/
-#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
/******************* Bit definition for TSC_IOASCR register *****************/
-#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
+#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 analog switch enable */
/******************* Bit definition for TSC_IOSCR register ******************/
-#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
+#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 sampling mode */
/******************* Bit definition for TSC_IOCCR register ******************/
-#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
+#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 channel mode */
/******************* Bit definition for TSC_IOGCSR register *****************/
-#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
+#define TSC_IOGCSR_G1E ((uint32_t)0x00000001U) /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E ((uint32_t)0x00000002U) /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E ((uint32_t)0x00000004U) /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E ((uint32_t)0x00000008U) /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E ((uint32_t)0x00000010U) /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E ((uint32_t)0x00000020U) /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E ((uint32_t)0x00000040U) /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E ((uint32_t)0x00000080U) /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S ((uint32_t)0x00010000U) /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S ((uint32_t)0x00020000U) /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S ((uint32_t)0x00040000U) /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S ((uint32_t)0x00080000U) /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S ((uint32_t)0x00100000U) /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S ((uint32_t)0x00200000U) /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S ((uint32_t)0x00400000U) /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S ((uint32_t)0x00800000U) /*!<Analog IO GROUP8 status */
/******************* Bit definition for TSC_IOGXCR register *****************/
-#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
+#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFFU) /*!<CNT[13:0] bits (Counter value) */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
/****************** Bit definition for USART_CR1 register *******************/
-#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
-#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
-#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
-#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
-#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
-#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
-#define USART_CR1_M ((uint32_t)0x10001000) /*!< Word length */
-#define USART_CR1_M_0 ((uint32_t)0x00001000) /*!< Word length - Bit 0 */
-#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
-#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
-#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
-#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
-#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
-#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
-#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
-#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
-#define USART_CR1_M_1 ((uint32_t)0x10000000) /*!< Word length - Bit 1 */
+#define USART_CR1_UE ((uint32_t)0x00000001U) /*!< USART Enable */
+#define USART_CR1_UESM ((uint32_t)0x00000002U) /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE ((uint32_t)0x00000004U) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008U) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010U) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020U) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080U) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100U) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200U) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400U) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800U) /*!< Receiver Wakeup method */
+#define USART_CR1_M ((uint32_t)0x10001000U) /*!< Word length */
+#define USART_CR1_M0 ((uint32_t)0x00001000U) /*!< Word length - Bit 0 */
+#define USART_CR1_MME ((uint32_t)0x00002000U) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000U) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000U) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000U) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000U) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000U) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000U) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000U) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000U) /*!< End of Block interrupt enable */
+#define USART_CR1_M1 ((uint32_t)0x10000000U) /*!< Word length - Bit 1 */
/****************** Bit definition for USART_CR2 register *******************/
-#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
-#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
-#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
-#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
-#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
-#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
-#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
-#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
-#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010U) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL ((uint32_t)0x00000020U) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040U) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100U) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200U) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400U) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800U) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000U) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000U) /*!< LIN mode enable */
+#define USART_CR2_SWAP ((uint32_t)0x00008000U) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000U) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000U) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000U) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000U) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000U) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000U) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000U) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000U) /*!< Address of the USART node */
/****************** Bit definition for USART_CR3 register *******************/
-#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
-#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
-#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
-#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
-#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
-#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
-#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
-#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
-#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
-#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
-#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
-#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM ((uint32_t)0x00800000) /*!< Clock Enable in Stop mode */
+#define USART_CR3_EIE ((uint32_t)0x00000001U) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002U) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004U) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008U) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010U) /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020U) /*!< SmartCard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040U) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080U) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100U) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200U) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400U) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800U) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000U) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000U) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000U) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000U) /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000U) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000U) /*!< Bit 2 */
+#define USART_CR3_WUS ((uint32_t)0x00300000U) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
+#define USART_CR3_WUFIE ((uint32_t)0x00400000U) /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM ((uint32_t)0x00800000U) /*!< Clock Enable in Stop mode */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000FU) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0U) /*!< Mantissa of USARTDIV */
/****************** Bit definition for USART_GTPR register ******************/
-#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
+#define USART_GTPR_PSC ((uint32_t)0x000000FFU) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint32_t)0x0000FF00U) /*!< GT[7:0] bits (Guard time value) */
/******************* Bit definition for USART_RTOR register *****************/
-#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFFU) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000U) /*!< Block Length */
/******************* Bit definition for USART_RQR register ******************/
-#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
-#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
+#define USART_RQR_ABRRQ ((uint32_t)0x00000001U) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint32_t)0x00000002U) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint32_t)0x00000004U) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint32_t)0x00000008U) /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ ((uint32_t)0x00000010U) /*!< Transmit data flush Request */
/******************* Bit definition for USART_ISR register ******************/
-#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
-#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
-#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
-#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
-#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
-#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
-#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
-#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
-#define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
-#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
-#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
-#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
-#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
-#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
-#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
-#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_PE ((uint32_t)0x00000001U) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002U) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004U) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008U) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010U) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020U) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040U) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080U) /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF ((uint32_t)0x00000100U) /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200U) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400U) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800U) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000U) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000U) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000U) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000U) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000U) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000U) /*!< Send Break Flag */
+#define USART_ISR_RWU ((uint32_t)0x00080000U) /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000U) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000U) /*!< Receive Enable Acknowledge Flag */
/******************* Bit definition for USART_ICR register ******************/
-#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
+#define USART_ICR_PECF ((uint32_t)0x00000001U) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002U) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004U) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008U) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010U) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040U) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF ((uint32_t)0x00000100U) /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200U) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800U) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF ((uint32_t)0x00001000U) /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000U) /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Clear Flag */
/******************* Bit definition for USART_RDR register ******************/
-#define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
+#define USART_RDR_RDR ((uint32_t)0x000001FFU) /*!< RDR[8:0] bits (Receive Data value) */
/******************* Bit definition for USART_TDR register ******************/
-#define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
+#define USART_TDR_TDR ((uint32_t)0x000001FFU) /*!< TDR[8:0] bits (Transmit Data value) */
/******************************************************************************/
/* */
/* USB Device General registers */
/* */
/******************************************************************************/
-#define USB_BASE ((uint32_t)0x40005C00) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR ((uint32_t)0x40006000) /*!< USB_IP Packet Memory Area base address */
+#define USB_BASE ((uint32_t)0x40005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR ((uint32_t)0x40006000U) /*!< USB_IP Packet Memory Area base address */
#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
@@ -3798,17 +4006,17 @@
#define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
/**************************** ISTR interrupt events *************************/
-#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
-#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
-#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
-#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
-#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
-#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
-#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
-#define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
-#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
-#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
+#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
+#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
+#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
@@ -3820,45 +4028,45 @@
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
/************************* CNTR control register bits definitions ***********/
-#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
-#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
-#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
-#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
-#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
-#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
-#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
-#define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
-#define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
-#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
-#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
-#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
-#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
-#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
+#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
+#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
+#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
/************************* BCDR control register bits definitions ***********/
-#define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
-#define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
-#define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
-#define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
-#define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
-#define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
-#define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
-#define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
-#define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
+#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
+#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
+#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
+#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
+#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
+#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
+#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
+#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
+#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
/*************************** LPM register bits definitions ******************/
-#define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
-#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
-#define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
-#define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
+#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
+#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
/******************** FNR Frame Number Register bit definitions ************/
-#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
-#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
-#define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
-#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
-#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
+#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
+#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
+#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
+#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
+#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
/******************** DADDR Device ADDRess bit definitions ****************/
-#define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
-#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
+#define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
+#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
/****************************** Endpoint register *************************/
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
@@ -3869,43 +4077,43 @@
#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
/* bit positions */
-#define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
-#define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
-#define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
-#define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
-#define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
+#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
/* EndPoint REGister MASK (no toggle fields) */
#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
/*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
-#define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
/*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************************************************************************/
@@ -3915,35 +4123,57 @@
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
-#define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */
-
-#define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */
+#define WWDG_CR_T ((uint32_t)0x0000007FU) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define WWDG_CR_T_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
+#define WWDG_CR_T_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
+#define WWDG_CR_T_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
+#define WWDG_CR_T_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
+#define WWDG_CR_T_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
+#define WWDG_CR_T_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA ((uint32_t)0x00000080U) /*!< Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
-#define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */
-
-#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */
-#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */
-
-#define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */
+#define WWDG_CFR_W ((uint32_t)0x0000007FU) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define WWDG_CFR_W_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
+#define WWDG_CFR_W_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
+#define WWDG_CFR_W_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
+#define WWDG_CFR_W_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
+#define WWDG_CFR_W_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
+#define WWDG_CFR_W_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x00000180U) /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080U) /*!< Bit 0 */
+#define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100U) /*!< Bit 1 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI ((uint32_t)0x00000200U) /*!< Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
-#define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */
+#define WWDG_SR_EWIF ((uint32_t)0x00000001U) /*!< Early Wakeup Interrupt Flag */
/**
* @}
@@ -3964,6 +4194,8 @@
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2))
+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
+
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
@@ -3987,6 +4219,12 @@
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOH))
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOH))
+
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
@@ -4016,6 +4254,34 @@
((INSTANCE) == TIM21) || \
((INSTANCE) == TIM22))
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
((INSTANCE) == TIM21) || \
@@ -4073,6 +4339,14 @@
((INSTANCE) == TIM21) || \
((INSTANCE) == TIM22))
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM2) && \
@@ -4113,11 +4387,9 @@
((INSTANCE) == USART2))
/******************** UART Instances : Wake-up from Stop mode **********************/
-
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == LPUART1))
-
/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/stm32l0xx.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/stm32l0xx.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.4.0
+ * @date 01-October-2015
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@@ -77,8 +77,16 @@
application
*/
-#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) \
- && !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && \
+ !defined (STM32L031xx) && !defined (STM32L041xx) && \
+ !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && \
+ !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) && \
+ !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && \
+ !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) \
+ /* #define STM32L011xx */
+ /* #define STM32L021xx */
+ /* #define STM32L031xx */ /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */
+ /* #define STM32L041xx */ /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */
/* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */
/* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */
#define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
@@ -106,12 +114,12 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V1.2.0
+ * @brief CMSIS Device version number V1.2.0RC1
*/
#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x01) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
@@ -124,8 +132,11 @@
/** @addtogroup Device_Included
* @{
*/
-
-#if defined(STM32L031xx)
+#if defined(STM32L011xx)
+ #include "stm32l011xx.h"
+#elif defined(STM32L021xx)
+ #include "stm32l021xx.h"
+#elif defined(STM32L031xx)
#include "stm32l031xx.h"
#elif defined(STM32L041xx)
#include "stm32l041xx.h"
@@ -205,6 +216,7 @@
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/stm32l0xx_hal_conf.h Sun Apr 17 17:45:10 2016 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/stm32l0xx_hal_conf.h Tue Apr 19 11:15:15 2016 +0100 @@ -1,16 +1,16 @@ /** ****************************************************************************** - * @file stm32l0xx_hal_conf_template.h + * @file stm32l0xx_hal_conf.h * @author MCD Application Team - * @version V1.2.0 - * @date 06-February-2015 + * @version V1.5.0 + * @date 8-January-2016 * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32l0xx_hal_conf.h. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -114,6 +114,23 @@ #endif /* HSI_VALUE */ /** + * @brief Internal High Speed oscillator for USB (HSI48) value. + */ +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)37000) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,20 +2,20 @@
******************************************************************************
* @file system_stm32l0xx.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
*
- * This file provides two functions and one global variable to be called from
+ * This file provides two functions and one global variable to be called from
* user application:
- * - SystemInit(): This function is called at startup just after reset and
+ * - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32l0xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
+ * by the user application to setup the SysTick
* timer or configure other parameters.
- *
+ *
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
@@ -36,11 +36,11 @@
* APB2CLK (MHz) | 32 | 32
*-----------------------------------------------------------------------------
* USB capable (48 MHz precise clock) | YES | YES
- *-----------------------------------------------------------------------------
+ *-----------------------------------------------------------------------------
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -73,8 +73,8 @@
/** @addtogroup stm32l0xx_system
* @{
- */
-
+ */
+
/** @addtogroup STM32L0xx_System_Private_Includes
* @{
*/
@@ -82,14 +82,14 @@
#include "stm32l0xx.h"
#include "hal_tick.h"
-#if !defined (HSE_VALUE)
+#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
-
+
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
@@ -115,7 +115,7 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
@@ -140,14 +140,14 @@
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 32000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t PLLMulTable_2[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
/**
* @}
@@ -177,19 +177,19 @@
* @retval None
*/
void SystemInit (void)
-{
+{
/*!< Set MSION bit */
RCC->CR |= (uint32_t)0x00000100;
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
RCC->CFGR &= (uint32_t) 0x88FF400C;
-
+
/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFF6;
-
+
/*!< Reset HSI48ON bit */
RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
-
+
/*!< Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
@@ -198,7 +198,7 @@
/*!< Disable all interrupts */
RCC->CIER = 0x00000000;
-
+
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
@@ -224,34 +224,34 @@
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
- *
+ *
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
- *
- * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
* value as defined by the MSI range.
- *
+ *
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
+ *
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
+ *
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
+ *
* (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
* 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
+ * in voltage and temperature.
+ *
* (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
- *
+ *
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
@@ -263,7 +263,7 @@
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
-
+
switch (tmp)
{
case 0x00: /* MSI used as system clock */
@@ -280,9 +280,9 @@
/* Get PLL clock source and multiplication factor ----------------------*/
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
- pllmul = PLLMulTable_2[(pllmul >> 18)];
+ pllmul = PLLMulTable[(pllmul >> 18)];
plldiv = (plldiv >> 22) + 1;
-
+
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
if (pllsource == 0x00)
@@ -311,8 +311,8 @@
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
- * @note This function should be called only once the RCC clock configuration
- * is reset to the default reset state (done in SystemInit() function).
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
@@ -338,7 +338,7 @@
}
}
}
-
+
/* Output clock on MCO1 pin(PA8) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
@@ -358,13 +358,13 @@
{
return 0;
}
-
- /* The voltage scaling allows optimizing the power consumption when the device is
- clocked below the maximum system frequency, to update the voltage scaling value
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
+
/* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
if (bypass == 0)
@@ -376,7 +376,10 @@
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
}
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
+ !defined (STM32L011xx) && !defined (STM32L021xx)
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
+#endif
// PLLCLK = (8 MHz * 8)/2 = 32 MHz
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
@@ -386,7 +389,7 @@
{
return 0; // FAIL
}
-
+
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
@@ -403,7 +406,7 @@
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
//else
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-
+
return 1; // OK
}
#endif
@@ -416,17 +419,20 @@
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
- /* The voltage scaling allows optimizing the power consumption when the device is
- clocked below the maximum system frequency, to update the voltage scaling value
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
+
/* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
+ !defined (STM32L011xx) && !defined (STM32L021xx)
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
+#endif
// PLLCLK = (16 MHz * 4)/2 = 32 MHz
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
@@ -436,7 +442,7 @@
{
return 0; // FAIL
}
-
+
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
@@ -450,7 +456,7 @@
/* Output clock on MCO1 pin(PA8) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-
+
return 1; // OK
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.h Sun Apr 17 17:45:10 2016 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.h Tue Apr 19 11:15:15 2016 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32l0xx.h * @author MCD Application Team - * @version V1.2.0 - * @date 06-February-2015 + * @version V1.5.0 + * @date 8-January-2016 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_MICRO/startup_stm32l073xx.S Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_MICRO/startup_stm32l073xx.S Tue Apr 19 11:15:15 2016 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l073xx.s
;* Author : MCD Application Team
-;* Version : V1.2.0
-;* Date : 06-February-2015
+;* Version : V1.5.0
+;* Date : 8-January-2016
;* Description : STM32l073xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@@ -90,7 +90,7 @@
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
@@ -161,11 +161,6 @@
EXPORT SVC_Handler [WEAK]
B .
ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_STD/startup_stm32l073xx.S Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_STD/startup_stm32l073xx.S Tue Apr 19 11:15:15 2016 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l073xx.s
;* Author : MCD Application Team
-;* Version : V1.2.0
-;* Date : 06-February-2015
+;* Version : V1.5.0
+;* Date : 8-January-2016
;* Description : STM32l073xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@@ -63,7 +63,7 @@
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
@@ -134,11 +134,6 @@
EXPORT SVC_Handler [WEAK]
B .
ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_GCC_ARM/startup_stm32l073xx.S Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_GCC_ARM/startup_stm32l073xx.S Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file startup_stm32l073xx.s
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief STM32L073xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
@@ -149,7 +149,7 @@
.word 0
.word 0
.word SVC_Handler
- .word DebugMon_Handler
+ .word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
@@ -203,9 +203,6 @@
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_IAR/startup_stm32l073xx.S Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_IAR/startup_stm32l073xx.S Tue Apr 19 11:15:15 2016 +0100
@@ -1,8 +1,8 @@
-;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l073xx.s
;* Author : MCD Application Team
-;* Version : V1.2.0
-;* Date : 06-February-2015
+;* Version : V1.5.0
+;* Date : 8-January-2016
;* Description : STM32L073xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP
@@ -82,7 +82,7 @@
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
@@ -152,12 +152,6 @@
B SVC_Handler
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DebugMon_Handler
- B DebugMon_Handler
-
-
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/stm32l073xx.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/stm32l073xx.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l073xx.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l073xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -178,19 +178,26 @@
__IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
} COMP_TypeDef;
-
-/**
- * @brief CRC calculation unit
- */
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
typedef struct
{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
- uint32_t RESERVED2; /*!< Reserved, 0x0C */
- __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
- __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
} CRC_TypeDef;
/**
@@ -391,7 +398,6 @@
/**
* @brief LCD
*/
-
typedef struct
{
__IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
@@ -405,7 +411,6 @@
/**
* @brief MIFARE Firewall
*/
-
typedef struct
{
__IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
@@ -418,12 +423,11 @@
__IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
__IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
-} FW_TypeDef;
+} FIREWALL_TypeDef;
/**
* @brief Power Control
*/
-
typedef struct
{
__IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
@@ -504,7 +508,6 @@
/**
* @brief Serial Peripheral Interface
*/
-
typedef struct
{
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
@@ -523,27 +526,27 @@
*/
typedef struct
{
- __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
- __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
- __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
- __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
} TIM_TypeDef;
/**
@@ -570,7 +573,6 @@
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
-
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
@@ -599,7 +601,6 @@
/**
* @brief Universal Serial Bus Full Speed Device
*/
-
typedef struct
{
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
@@ -641,17 +642,16 @@
/** @addtogroup Peripheral_memory_map
* @{
*/
-
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK2_BASE ((uint32_t)0x08018000) /*!< FLASH BANK2 base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x08017FFF) /*!< Program end FLASH BANK1 address */
-#define FLASH_BANK2_END ((uint32_t)0x0802FFFF) /*!< Program end FLASH BANK2 address */
-#define DATA_EEPROM_BASE ((uint32_t)0x08080000) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_BANK2_BASE ((uint32_t)0x08080C00) /*!< DATA EEPROM BANK2 base address in the alias region */
-#define DATA_EEPROM_BANK1_END ((uint32_t)0x08080BFF) /*!< Program end DATA EEPROM BANK1 address */
-#define DATA_EEPROM_BANK2_END ((uint32_t)0x080817FF) /*!< Program end DATA EEPROM BANK2 address */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
+#define FLASH_BANK2_BASE ((uint32_t)0x08018000U) /*!< FLASH BANK2 base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x08017FFFU) /*!< Program end FLASH BANK1 address */
+#define FLASH_BANK2_END ((uint32_t)0x0802FFFFU) /*!< Program end FLASH BANK2 address */
+#define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_BANK2_BASE ((uint32_t)0x08080C00U) /*!< DATA EEPROM BANK2 base address in the alias region */
+#define DATA_EEPROM_BANK1_END ((uint32_t)0x08080BFFU) /*!< Program end DATA EEPROM BANK1 address */
+#define DATA_EEPROM_BANK2_END ((uint32_t)0x080817FFU) /*!< Program end DATA EEPROM BANK2 address */
+#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
/*!< Peripheral memory map */
#define APBPERIPH_BASE PERIPH_BASE
@@ -682,10 +682,11 @@
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
#define COMP1_BASE (APBPERIPH_BASE + 0x00010018)
#define COMP2_BASE (APBPERIPH_BASE + 0x0001001C)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
#define TIM21_BASE (APBPERIPH_BASE + 0x00010800)
#define TIM22_BASE (APBPERIPH_BASE + 0x00011400)
-#define FW_BASE (APBPERIPH_BASE + 0x00011C00)
+#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00)
#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
@@ -705,7 +706,7 @@
#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
-#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
+#define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
#define RNG_BASE (AHBPERIPH_BASE + 0x00005000)
@@ -741,6 +742,7 @@
#define CRS ((CRS_TypeDef *) CRS_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define LCD ((LCD_TypeDef *) LCD_BASE)
#define USART4 ((USART_TypeDef *) USART4_BASE)
@@ -752,9 +754,11 @@
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
-#define FW ((FW_TypeDef *) FW_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
@@ -807,139 +811,140 @@
/* */
/******************************************************************************/
/******************** Bits definition for ADC_ISR register ******************/
-#define ADC_ISR_EOCAL ((uint32_t)0x00000800) /*!< End of calibration flag */
-#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
-#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
-#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
-#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
-#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
-#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
+#define ADC_ISR_EOCAL ((uint32_t)0x00000800U) /*!< End of calibration flag */
+#define ADC_ISR_AWD ((uint32_t)0x00000080U) /*!< Analog watchdog flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< Overrun flag */
+#define ADC_ISR_EOSEQ ((uint32_t)0x00000008U) /*!< End of Sequence flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< End of Conversion */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< End of sampling flag */
+#define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC Ready */
/* Old EOSEQ bit definition, maintained for legacy purpose */
#define ADC_ISR_EOS ADC_ISR_EOSEQ
/******************** Bits definition for ADC_IER register ******************/
-#define ADC_IER_EOCALIE ((uint32_t)0x00000800) /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
+#define ADC_IER_EOCALIE ((uint32_t)0x00000800U) /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE ((uint32_t)0x00000080U) /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE ((uint32_t)0x00000008U) /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC Ready interrupt enable */
/* Old EOSEQIE bit definition, maintained for legacy purpose */
#define ADC_IER_EOSIE ADC_IER_EOSEQIE
/******************** Bits definition for ADC_CR register *******************/
-#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
-#define ADC_CR_ADVREGEN ((uint32_t)0x10000000) /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
-#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
-#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */ /*#### TBV */
+#define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */
+#define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC start of conversion */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable command */
+#define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable control */ /*#### TBV */
/******************* Bits definition for ADC_CFGR1 register *****************/
-#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
-#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
-#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
-#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
+#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000U) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
+#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
+#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
+#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
+#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
+#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000U) /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000U) /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000U) /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000U) /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT ((uint32_t)0x00004000U) /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT ((uint32_t)0x00002000U) /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000U) /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00U) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
+#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0U) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
+#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100U) /*!< Bit 2 */
+#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020U) /*!< Data Alignment */
+#define ADC_CFGR1_RES ((uint32_t)0x00000018U) /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
+#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
+#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004U) /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002U) /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001U) /*!< Direct memory access enable */
/* Old WAIT bit definition, maintained for legacy purpose */
#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
/******************* Bits definition for ADC_CFGR2 register *****************/
-#define ADC_CFGR2_TOVS ((uint32_t)0x80000200) /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0) /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
-#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100) /*!< Bit 3 */
-#define ADC_CFGR2_OVSR ((uint32_t)0x0000001C) /*!< OVSR [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010) /*!< Bit 2 */
-#define ADC_CFGR2_OVSE ((uint32_t)0x00000001) /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< Bit 0 */
-#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+#define ADC_CFGR2_TOVS ((uint32_t)0x80000200U) /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
+#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
+#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
+#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
+#define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
+#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
+#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /*!< Bit 2 */
+#define ADC_CFGR2_OVSE ((uint32_t)0x00000001U) /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000U) /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000U) /*!< Bit 0 */
+#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000U) /*!< Bit 1 */
/****************** Bit definition for ADC_SMPR register ********************/
-#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-
-/* Bit names aliases maintained for legacy */
+#define ADC_SMPR_SMP ((uint32_t)0x00000007U) /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
+#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
+
+/* Legacy defines */
#define ADC_SMPR_SMPR ADC_SMPR_SMP
#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
/******************* Bit definition for ADC_TR register ********************/
-#define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
-#define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+#define ADC_TR_HT ((uint32_t)0x0FFF0000U) /*!< Analog watchdog high threshold */
+#define ADC_TR_LT ((uint32_t)0x00000FFFU) /*!< Analog watchdog low threshold */
/****************** Bit definition for ADC_CHSELR register ******************/
-#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
-#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
+#define ADC_CHSELR_CHSEL ((uint32_t)0x0007FFFFU) /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000U) /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000U) /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000U) /*!< Channel 16 selection */
+#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000U) /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000U) /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000U) /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000U) /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800U) /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400U) /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200U) /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100U) /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080U) /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040U) /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020U) /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010U) /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008U) /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004U) /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002U) /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001U) /*!< Channel 0 selection */
/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+#define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< Regular data */
/******************** Bit definition for ADC_CALFACT register ********************/
-#define ADC_CALFACT_CALFACT ((uint32_t)0x0000007F) /*!< Calibration factor */
+#define ADC_CALFACT_CALFACT ((uint32_t)0x0000007FU) /*!< Calibration factor */
/******************* Bit definition for ADC_CCR register ********************/
-#define ADC_CCR_LFMEN ((uint32_t)0x02000000) /*!< Low Frequency Mode enable */
-#define ADC_CCR_VLCDEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
-#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
-#define ADC_CCR_PRESC ((uint32_t)0x003C0000) /*!< PRESC [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+#define ADC_CCR_LFMEN ((uint32_t)0x02000000U) /*!< Low Frequency Mode enable */
+#define ADC_CCR_VLCDEN ((uint32_t)0x01000000U) /*!< Voltage LCD enable */
+#define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< Vrefint enable */
+#define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
+#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
+#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
+#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /*!< Bit 3 */
/******************************************************************************/
/* */
@@ -948,37 +953,40 @@
/******************************************************************************/
/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030) /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
-#define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
-#define COMP_CSR_COMP1WM ((uint32_t)0x00000100) /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000) /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000) /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000) /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
+#define COMP_CSR_COMP1EN ((uint32_t)0x00000001U) /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030U) /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP1 inverting input select bit 0 */
+#define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP1 inverting input select bit 1 */
+#define COMP_CSR_COMP1WM ((uint32_t)0x00000100U) /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000U) /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000U) /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000U) /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000U) /*!< COMP1 lock */
/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED ((uint32_t)0x000C0008) /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL ((uint32_t)0x00100070) /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00100010) /*!< COMP2 inverting input select bit 0 */
-#define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00200020) /*!< COMP2 inverting input select bit 1 */
-#define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00400040) /*!< COMP2 inverting input select bit 2 */
-#define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000) /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000) /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000) /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
+#define COMP_CSR_COMP2EN ((uint32_t)0x00000001U) /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED ((uint32_t)0x00000008U) /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL ((uint32_t)0x00000070U) /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP2 inverting input select bit 0 */
+#define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP2 inverting input select bit 1 */
+#define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00000040U) /*!< COMP2 inverting input select bit 2 */
+#define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700U) /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100U) /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200U) /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400U) /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000U) /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1 ((uint32_t)0x00002000U) /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000U) /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000U) /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000U) /*!< COMP2 lock */
/********************** Bit definition for COMP_CSR register common ****************/
-#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000) /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000) /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
-
+#define COMP_CSR_COMPxEN ((uint32_t)0x00000001U) /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000U) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000U) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000U) /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
/******************************************************************************/
/* */
@@ -986,26 +994,26 @@
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
-#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
+#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
-#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
-#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
-#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+#define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */
+#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
-#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
-#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
+#define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
@@ -1014,140 +1022,146 @@
/******************************************************************************/
/******************* Bit definition for CRS_CR register *********************/
-#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
-#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
-#define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
-#define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
-#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
-#define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
-#define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
+#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001U) /* SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002U) /* SYNC warning interrupt enable */
+#define CRS_CR_ERRIE ((uint32_t)0x00000004U) /* SYNC error interrupt enable */
+#define CRS_CR_ESYNCIE ((uint32_t)0x00000008U) /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define CRS_CR_CEN ((uint32_t)0x00000020U) /* Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040U) /* Automatic trimming enable */
+#define CRS_CR_SWSYNC ((uint32_t)0x00000080U) /* A Software SYNC event is generated */
+#define CRS_CR_TRIM ((uint32_t)0x00003F00U) /* HSI48 oscillator smooth trimming */
/******************* Bit definition for CRS_CFGR register *********************/
-#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
-#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
-
-#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
-#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
-#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
-#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
-
-#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
-#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
-#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
-
-#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
+#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFFU) /* Counter reload value */
+#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000U) /* Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000U) /* SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000U) /* Bit 0 */
+#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000U) /* Bit 1 */
+#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000U) /* Bit 2 */
+
+#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000U) /* SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000U) /* Bit 0 */
+#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000U) /* Bit 1 */
+
+#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000U) /* SYNC polarity selection */
/******************* Bit definition for CRS_ISR register *********************/
-#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
-#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
-#define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
-#define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
-#define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
-#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
-#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
-#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
+#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001U) /* SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002U) /* SYNC warning */
+#define CRS_ISR_ERRF ((uint32_t)0x00000004U) /* SYNC error flag */
+#define CRS_ISR_ESYNCF ((uint32_t)0x00000008U) /* Expected SYNC flag */
+#define CRS_ISR_SYNCERR ((uint32_t)0x00000100U) /* SYNC error */
+#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200U) /* SYNC missed */
+#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400U) /* Trimming overflow or underflow */
+#define CRS_ISR_FEDIR ((uint32_t)0x00008000U) /* Frequency error direction */
+#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000U) /* Frequency error capture */
/******************* Bit definition for CRS_ICR register *********************/
-#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
-#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
-#define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
-#define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
+#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001U) /* SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002U) /* SYNC warning clear flag */
+#define CRS_ICR_ERRC ((uint32_t)0x00000004U) /* Error clear flag */
+#define CRS_ICR_ESYNCC ((uint32_t)0x00000008U) /* Expected SYNC clear flag */
/******************************************************************************/
/* */
/* Digital to Analog Converter (DAC) */
/* */
/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
+
/******************** Bit definition for DAC_CR register ********************/
-#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-
-#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-
-#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun interrupt enable */
-
-#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
-#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
-#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
-#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
-#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
-
-#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
-#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
-
-#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel12DMA Underrun interrupt enable */
+#define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002U) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA Underrun interrupt enable */
+
+#define DAC_CR_EN2 ((uint32_t)0x00010000U) /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000U) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000U) /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000U) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000U) /*!< Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000U) /*!< Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000U) /*!< Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000U) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000U) /*!< Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000U) /*!< Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000U) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000U) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000U) /*!< DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000U) /*!< DAC channel12DMA Underrun interrupt enable */
/***************** Bit definition for DAC_SWTRIGR register ******************/
-#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002U) /*!< DAC channel2 software trigger */
/***************** Bit definition for DAC_DHR12R1 register ******************/
-#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!< DAC channel1 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L1 register ******************/
-#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel1 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R1 register ******************/
-#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!< DAC channel1 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12R2 register ******************/
-#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFFU) /*!< DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L2 register ******************/
-#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R2 register ******************/
-#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FFU) /*!< DAC channel2 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12RD register ******************/
-#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFFU) /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000U) /*!< DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
-#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000U) /*!< DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
-#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FFU) /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00U) /*!< DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
-#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFF) /*!< DAC channel1 data output */
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */
/******************* Bit definition for DAC_DOR2 register *******************/
-#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFFU) /*!< DAC channel2 data output */
/******************** Bit definition for DAC_SR register ********************/
-#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000U) /*!< DAC channel2 DMA underrun flag */
/******************************************************************************/
/* */
@@ -1156,49 +1170,49 @@
/******************************************************************************/
/**************** Bit definition for DBGMCU_IDCODE register *****************/
-#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_DIV_ID ((uint32_t)0x0000F000) /*!< Division Identifier */
-#define DBGMCU_IDCODE_MCD_DIV_ID ((uint32_t)0x00006000) /*!< MCD divsion ID is 6 */
-#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
-#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
-#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
-#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
-#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
-#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_DIV_ID ((uint32_t)0x0000F000U) /*!< Division Identifier */
+#define DBGMCU_IDCODE_MCD_DIV_ID ((uint32_t)0x00006000U) /*!< MCD divsion ID is 6 */
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /*!< Bit 15 */
/****************** Bit definition for DBGMCU_CR register *******************/
-#define DBGMCU_CR_DBG ((uint32_t)0x00000007) /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+#define DBGMCU_CR_DBG ((uint32_t)0x00000007U) /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U) /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /*!< Debug Standby mode */
/****************** Bit definition for DBGMCU_APB1_FZ register **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP ((uint32_t)0x00400000) /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP ((uint32_t)0x00800000) /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000) /*!< LPTIM1 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010U) /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000U) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP ((uint32_t)0x00400000U) /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP ((uint32_t)0x00800000U) /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000U) /*!< LPTIM1 counter stopped when core is halted */
/****************** Bit definition for DBGMCU_APB2_FZ register **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020) /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004) /*!< TIM21 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020U) /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004U) /*!< TIM21 counter stopped when core is halted */
/******************************************************************************/
/* */
@@ -1207,107 +1221,107 @@
/******************************************************************************/
/******************* Bit definition for DMA_ISR register ********************/
-#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *******************/
-#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */
/******************* Bit definition for DMA_CCR register ********************/
-#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
-#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
-#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
-#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
-#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-
-#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-
-#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-
-#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+#define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */
/****************** Bit definition for DMA_CNDTR register *******************/
-#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CPAR register ********************/
-#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
/****************** Bit definition for DMA_CMAR register ********************/
-#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
/******************* Bit definition for DMA_CSELR register *******************/
-#define DMA_CSELR_C1S ((uint32_t)0x0000000F) /*!< Channel 1 Selection */
-#define DMA_CSELR_C2S ((uint32_t)0x000000F0) /*!< Channel 2 Selection */
-#define DMA_CSELR_C3S ((uint32_t)0x00000F00) /*!< Channel 3 Selection */
-#define DMA_CSELR_C4S ((uint32_t)0x0000F000) /*!< Channel 4 Selection */
-#define DMA_CSELR_C5S ((uint32_t)0x000F0000) /*!< Channel 5 Selection */
-#define DMA_CSELR_C6S ((uint32_t)0x00F00000) /*!< Channel 6 Selection */
-#define DMA_CSELR_C7S ((uint32_t)0x0F000000) /*!< Channel 7 Selection */
+#define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /*!< Channel 7 Selection */
/******************************************************************************/
@@ -1317,162 +1331,258 @@
/******************************************************************************/
/******************* Bit definition for EXTI_IMR register *******************/
-#define EXTI_IMR_IM0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_IM1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_IM2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_IM3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_IM4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_IM5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_IM6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_IM7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_IM8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_IM9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_IM10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
-#define EXTI_IMR_IM25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_IM0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM24 ((uint32_t)0x01000000U) /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR_IM25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26 ((uint32_t)0x04000000U) /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28 ((uint32_t)0x10000000U) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29 ((uint32_t)0x20000000U) /*!< Interrupt Mask on line 29 */
/****************** Bit definition for EXTI_EMR register ********************/
-#define EXTI_EMR_EM0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
-#define EXTI_EMR_EM1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
-#define EXTI_EMR_EM2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
-#define EXTI_EMR_EM3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
-#define EXTI_EMR_EM4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
-#define EXTI_EMR_EM5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
-#define EXTI_EMR_EM6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
-#define EXTI_EMR_EM7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
-#define EXTI_EMR_EM8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
-#define EXTI_EMR_EM9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
-#define EXTI_EMR_EM10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
-#define EXTI_EMR_EM25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_EM0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM24 ((uint32_t)0x01000000U) /*!< Event Mask on line 24 */
+#define EXTI_EMR_EM25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26 ((uint32_t)0x04000000U) /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28 ((uint32_t)0x10000000U) /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29 ((uint32_t)0x20000000U) /*!< Event Mask on line 29 */
/******************* Bit definition for EXTI_RTSR register ******************/
-#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_RT0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17 ((uint32_t)0x00020000U) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
/******************* Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_FT0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17 ((uint32_t)0x00020000U) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWI0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17 ((uint32_t)0x00020000U) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
/****************** Bit definition for EXTI_PR register *********************/
-#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
-#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
-#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
-#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
-#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
-#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
-#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
-#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
-#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
-#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
-#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
-#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
-#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
-#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
-#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
-#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
-#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
-#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
-#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
-#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
-#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
-#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
+#define EXTI_PR_PIF0 ((uint32_t)0x00000001U) /*!< Pending bit 0 */
+#define EXTI_PR_PIF1 ((uint32_t)0x00000002U) /*!< Pending bit 1 */
+#define EXTI_PR_PIF2 ((uint32_t)0x00000004U) /*!< Pending bit 2 */
+#define EXTI_PR_PIF3 ((uint32_t)0x00000008U) /*!< Pending bit 3 */
+#define EXTI_PR_PIF4 ((uint32_t)0x00000010U) /*!< Pending bit 4 */
+#define EXTI_PR_PIF5 ((uint32_t)0x00000020U) /*!< Pending bit 5 */
+#define EXTI_PR_PIF6 ((uint32_t)0x00000040U) /*!< Pending bit 6 */
+#define EXTI_PR_PIF7 ((uint32_t)0x00000080U) /*!< Pending bit 7 */
+#define EXTI_PR_PIF8 ((uint32_t)0x00000100U) /*!< Pending bit 8 */
+#define EXTI_PR_PIF9 ((uint32_t)0x00000200U) /*!< Pending bit 9 */
+#define EXTI_PR_PIF10 ((uint32_t)0x00000400U) /*!< Pending bit 10 */
+#define EXTI_PR_PIF11 ((uint32_t)0x00000800U) /*!< Pending bit 11 */
+#define EXTI_PR_PIF12 ((uint32_t)0x00001000U) /*!< Pending bit 12 */
+#define EXTI_PR_PIF13 ((uint32_t)0x00002000U) /*!< Pending bit 13 */
+#define EXTI_PR_PIF14 ((uint32_t)0x00004000U) /*!< Pending bit 14 */
+#define EXTI_PR_PIF15 ((uint32_t)0x00008000U) /*!< Pending bit 15 */
+#define EXTI_PR_PIF16 ((uint32_t)0x00010000U) /*!< Pending bit 16 */
+#define EXTI_PR_PIF17 ((uint32_t)0x00020000U) /*!< Pending bit 17 */
+#define EXTI_PR_PIF19 ((uint32_t)0x00080000U) /*!< Pending bit 19 */
+#define EXTI_PR_PIF20 ((uint32_t)0x00100000U) /*!< Pending bit 20 */
+#define EXTI_PR_PIF21 ((uint32_t)0x00200000U) /*!< Pending bit 21 */
+#define EXTI_PR_PIF22 ((uint32_t)0x00400000U) /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
/******************************************************************************/
/* */
@@ -1481,73 +1591,73 @@
/******************************************************************************/
/******************* Bit definition for FLASH_ACR register ******************/
-#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020) /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ ((uint32_t)0x00000040) /*!< Pre-read data address */
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002U) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008U) /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010U) /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020U) /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ ((uint32_t)0x00000040U) /*!< Pre-read data address */
/******************* Bit definition for FLASH_PECR register ******************/
-#define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
-#define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
-#define FLASH_PECR_FIX ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
-#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000) /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
-#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
-#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000) /*!< Half array mode */
-#define FLASH_PECR_NZDISABLE ((uint32_t)0x00400000) /*!< Non-Zero check disable */
+#define FLASH_PECR_PELOCK ((uint32_t)0x00000001U) /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002U) /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004U) /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG ((uint32_t)0x00000008U) /*!< Program matrix selection */
+#define FLASH_PECR_DATA ((uint32_t)0x00000010U) /*!< Data matrix selection */
+#define FLASH_PECR_FIX ((uint32_t)0x00000100U) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE ((uint32_t)0x00000200U) /*!< Page erasing mode */
+#define FLASH_PECR_FPRG ((uint32_t)0x00000400U) /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000U) /*!< Parallel Bank mode */
+#define FLASH_PECR_EOPIE ((uint32_t)0x00010000U) /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE ((uint32_t)0x00020000U) /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000U) /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000U) /*!< Half array mode */
+#define FLASH_PECR_NZDISABLE ((uint32_t)0x00400000U) /*!< Non-Zero check disable */
/****************** Bit definition for FLASH_PDKEYR register ******************/
-#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
+#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */
/****************** Bit definition for FLASH_PEKEYR register ******************/
-#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
+#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */
/****************** Bit definition for FLASH_PRGKEYR register ******************/
-#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
+#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFFU) /*!< Program matrix Key */
/****************** Bit definition for FLASH_OPTKEYR register ******************/
-#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /*!< Option bytes matrix Key */
/****************** Bit definition for FLASH_SR register *******************/
-#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
-#define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
-#define FLASH_SR_HVOFF ((uint32_t)0x00000004) /*!< End of high voltage */
-#define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protection error */
-#define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
-#define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option Valid error */
-#define FLASH_SR_RDERR ((uint32_t)0x00002000) /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000) /*!< Not Zero error */
-#define FLASH_SR_FWWERR ((uint32_t)0x00020000) /*!< Write/Errase operation aborted */
-
-/* alias maintained for legacy */
+#define FLASH_SR_BSY ((uint32_t)0x00000001U) /*!< Busy */
+#define FLASH_SR_EOP ((uint32_t)0x00000002U) /*!< End Of Programming*/
+#define FLASH_SR_HVOFF ((uint32_t)0x00000004U) /*!< End of high voltage */
+#define FLASH_SR_READY ((uint32_t)0x00000008U) /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR ((uint32_t)0x00000100U) /*!< Write protection error */
+#define FLASH_SR_PGAERR ((uint32_t)0x00000200U) /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR ((uint32_t)0x00000400U) /*!< Size error */
+#define FLASH_SR_OPTVERR ((uint32_t)0x00000800U) /*!< Option Valid error */
+#define FLASH_SR_RDERR ((uint32_t)0x00002000U) /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000U) /*!< Not Zero error */
+#define FLASH_SR_FWWERR ((uint32_t)0x00020000U) /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
#define FLASH_SR_FWWER FLASH_SR_FWWERR
#define FLASH_SR_ENHV FLASH_SR_HVOFF
#define FLASH_SR_ENDHV FLASH_SR_HVOFF
/****************** Bit definition for FLASH_OPTR register *******************/
-#define FLASH_OPTR_RDPROT ((uint32_t)0x000000FF) /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
-#define FLASH_OPTR_BFB2 ((uint32_t)0x00800000) /*!< BFB2 */
-#define FLASH_OPTR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000) /*!< BOOT1 */
+#define FLASH_OPTR_RDPROT ((uint32_t)0x000000FFU) /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100U) /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000U) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000U) /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000U) /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000U) /*!< nRST_STDBY */
+#define FLASH_OPTR_BFB2 ((uint32_t)0x00800000U) /*!< BFB2 */
+#define FLASH_OPTR_USER ((uint32_t)0x00700000U) /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000U) /*!< BOOT1 */
/****************** Bit definition for FLASH_WRPR register ******************/
-#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protection bits */
+#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFFU) /*!< Write Protection bits */
/******************************************************************************/
/* */
@@ -1555,279 +1665,299 @@
/* */
/******************************************************************************/
/******************* Bit definition for GPIO_MODER register *****************/
-#define GPIO_MODER_MODE0 ((uint32_t)0x00000003)
-#define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001)
-#define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002)
-#define GPIO_MODER_MODE1 ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004)
-#define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008)
-#define GPIO_MODER_MODE2 ((uint32_t)0x00000030)
-#define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010)
-#define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020)
-#define GPIO_MODER_MODE3 ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040)
-#define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080)
-#define GPIO_MODER_MODE4 ((uint32_t)0x00000300)
-#define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100)
-#define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200)
-#define GPIO_MODER_MODE5 ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400)
-#define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800)
-#define GPIO_MODER_MODE6 ((uint32_t)0x00003000)
-#define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000)
-#define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000)
-#define GPIO_MODER_MODE7 ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000)
-#define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000)
-#define GPIO_MODER_MODE8 ((uint32_t)0x00030000)
-#define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000)
-#define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000)
-#define GPIO_MODER_MODE9 ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000)
-#define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000)
-#define GPIO_MODER_MODE10 ((uint32_t)0x00300000)
-#define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000)
-#define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000)
-#define GPIO_MODER_MODE11 ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000)
-#define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000)
-#define GPIO_MODER_MODE12 ((uint32_t)0x03000000)
-#define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000)
-#define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000)
-#define GPIO_MODER_MODE13 ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000)
-#define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000)
-#define GPIO_MODER_MODE14 ((uint32_t)0x30000000)
-#define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000)
-#define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000)
-#define GPIO_MODER_MODE15 ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000)
-#define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000)
+#define GPIO_MODER_MODE0 ((uint32_t)0x00000003U)
+#define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U)
+#define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U)
+#define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU)
+#define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U)
+#define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U)
+#define GPIO_MODER_MODE2 ((uint32_t)0x00000030U)
+#define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U)
+#define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U)
+#define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U)
+#define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U)
+#define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U)
+#define GPIO_MODER_MODE4 ((uint32_t)0x00000300U)
+#define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U)
+#define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U)
+#define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U)
+#define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U)
+#define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U)
+#define GPIO_MODER_MODE6 ((uint32_t)0x00003000U)
+#define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U)
+#define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U)
+#define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U)
+#define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U)
+#define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U)
+#define GPIO_MODER_MODE8 ((uint32_t)0x00030000U)
+#define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U)
+#define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U)
+#define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U)
+#define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U)
+#define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U)
+#define GPIO_MODER_MODE10 ((uint32_t)0x00300000U)
+#define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U)
+#define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U)
+#define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U)
+#define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U)
+#define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U)
+#define GPIO_MODER_MODE12 ((uint32_t)0x03000000U)
+#define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U)
+#define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U)
+#define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U)
+#define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U)
+#define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U)
+#define GPIO_MODER_MODE14 ((uint32_t)0x30000000U)
+#define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U)
+#define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U)
+#define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U)
+#define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U)
+#define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U)
/****************** Bit definition for GPIO_OTYPER register *****************/
-#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U)
/**************** Bit definition for GPIO_OSPEEDR register ******************/
-#define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002)
-#define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008)
-#define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020)
-#define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080)
-#define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200)
-#define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800)
-#define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000)
-#define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000)
-#define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000)
-#define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000)
-#define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000)
-#define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000)
-#define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000)
-#define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000)
-#define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000)
-#define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000)
+#define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003U)
+#define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001U)
+#define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002U)
+#define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000CU)
+#define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004U)
+#define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008U)
+#define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030U)
+#define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010U)
+#define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020U)
+#define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0U)
+#define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040U)
+#define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080U)
+#define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300U)
+#define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100U)
+#define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200U)
+#define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00U)
+#define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400U)
+#define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800U)
+#define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000U)
+#define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000U)
+#define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000U)
+#define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000U)
+#define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000U)
+#define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000U)
+#define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000U)
+#define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000U)
+#define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000U)
+#define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000U)
+#define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000U)
+#define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000U)
+#define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000U)
+#define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000U)
+#define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000U)
+#define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000U)
+#define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000U)
+#define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000U)
+#define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000U)
+#define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000U)
+#define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000U)
+#define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000U)
+#define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000U)
+#define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000U)
+#define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000U)
+#define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000U)
+#define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000U)
+#define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000U)
+#define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000U)
+#define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000U)
/******************* Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002)
-#define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008)
-#define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020)
-#define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080)
-#define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200)
-#define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800)
-#define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000)
-#define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000)
-#define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000)
-#define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000)
-#define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000)
-#define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000)
-#define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000)
-#define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000)
-#define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000)
+#define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U)
+#define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U)
+#define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U)
+#define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU)
+#define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U)
+#define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U)
+#define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U)
+#define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U)
+#define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U)
+#define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U)
+#define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U)
+#define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U)
+#define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U)
+#define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U)
+#define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U)
+#define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U)
+#define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U)
+#define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U)
+#define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U)
+#define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U)
+#define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U)
+#define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U)
+#define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U)
+#define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U)
+#define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U)
+#define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U)
+#define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U)
+#define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U)
+#define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U)
+#define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U)
+#define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U)
+#define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U)
+#define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U)
+#define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U)
+#define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U)
+#define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U)
+#define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U)
+#define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U)
+#define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U)
+#define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U)
+#define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U)
+#define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U)
+#define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U)
+#define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U)
+#define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U)
+#define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U)
+#define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U)
+#define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U)
/******************* Bit definition for GPIO_IDR register *******************/
-#define GPIO_IDR_ID0 ((uint32_t)0x00000001)
-#define GPIO_IDR_ID1 ((uint32_t)0x00000002)
-#define GPIO_IDR_ID2 ((uint32_t)0x00000004)
-#define GPIO_IDR_ID3 ((uint32_t)0x00000008)
-#define GPIO_IDR_ID4 ((uint32_t)0x00000010)
-#define GPIO_IDR_ID5 ((uint32_t)0x00000020)
-#define GPIO_IDR_ID6 ((uint32_t)0x00000040)
-#define GPIO_IDR_ID7 ((uint32_t)0x00000080)
-#define GPIO_IDR_ID8 ((uint32_t)0x00000100)
-#define GPIO_IDR_ID9 ((uint32_t)0x00000200)
-#define GPIO_IDR_ID10 ((uint32_t)0x00000400)
-#define GPIO_IDR_ID11 ((uint32_t)0x00000800)
-#define GPIO_IDR_ID12 ((uint32_t)0x00001000)
-#define GPIO_IDR_ID13 ((uint32_t)0x00002000)
-#define GPIO_IDR_ID14 ((uint32_t)0x00004000)
-#define GPIO_IDR_ID15 ((uint32_t)0x00008000)
+#define GPIO_IDR_ID0 ((uint32_t)0x00000001U)
+#define GPIO_IDR_ID1 ((uint32_t)0x00000002U)
+#define GPIO_IDR_ID2 ((uint32_t)0x00000004U)
+#define GPIO_IDR_ID3 ((uint32_t)0x00000008U)
+#define GPIO_IDR_ID4 ((uint32_t)0x00000010U)
+#define GPIO_IDR_ID5 ((uint32_t)0x00000020U)
+#define GPIO_IDR_ID6 ((uint32_t)0x00000040U)
+#define GPIO_IDR_ID7 ((uint32_t)0x00000080U)
+#define GPIO_IDR_ID8 ((uint32_t)0x00000100U)
+#define GPIO_IDR_ID9 ((uint32_t)0x00000200U)
+#define GPIO_IDR_ID10 ((uint32_t)0x00000400U)
+#define GPIO_IDR_ID11 ((uint32_t)0x00000800U)
+#define GPIO_IDR_ID12 ((uint32_t)0x00001000U)
+#define GPIO_IDR_ID13 ((uint32_t)0x00002000U)
+#define GPIO_IDR_ID14 ((uint32_t)0x00004000U)
+#define GPIO_IDR_ID15 ((uint32_t)0x00008000U)
/****************** Bit definition for GPIO_ODR register ********************/
-#define GPIO_ODR_OD0 ((uint32_t)0x00000001)
-#define GPIO_ODR_OD1 ((uint32_t)0x00000002)
-#define GPIO_ODR_OD2 ((uint32_t)0x00000004)
-#define GPIO_ODR_OD3 ((uint32_t)0x00000008)
-#define GPIO_ODR_OD4 ((uint32_t)0x00000010)
-#define GPIO_ODR_OD5 ((uint32_t)0x00000020)
-#define GPIO_ODR_OD6 ((uint32_t)0x00000040)
-#define GPIO_ODR_OD7 ((uint32_t)0x00000080)
-#define GPIO_ODR_OD8 ((uint32_t)0x00000100)
-#define GPIO_ODR_OD9 ((uint32_t)0x00000200)
-#define GPIO_ODR_OD10 ((uint32_t)0x00000400)
-#define GPIO_ODR_OD11 ((uint32_t)0x00000800)
-#define GPIO_ODR_OD12 ((uint32_t)0x00001000)
-#define GPIO_ODR_OD13 ((uint32_t)0x00002000)
-#define GPIO_ODR_OD14 ((uint32_t)0x00004000)
-#define GPIO_ODR_OD15 ((uint32_t)0x00008000)
+#define GPIO_ODR_OD0 ((uint32_t)0x00000001U)
+#define GPIO_ODR_OD1 ((uint32_t)0x00000002U)
+#define GPIO_ODR_OD2 ((uint32_t)0x00000004U)
+#define GPIO_ODR_OD3 ((uint32_t)0x00000008U)
+#define GPIO_ODR_OD4 ((uint32_t)0x00000010U)
+#define GPIO_ODR_OD5 ((uint32_t)0x00000020U)
+#define GPIO_ODR_OD6 ((uint32_t)0x00000040U)
+#define GPIO_ODR_OD7 ((uint32_t)0x00000080U)
+#define GPIO_ODR_OD8 ((uint32_t)0x00000100U)
+#define GPIO_ODR_OD9 ((uint32_t)0x00000200U)
+#define GPIO_ODR_OD10 ((uint32_t)0x00000400U)
+#define GPIO_ODR_OD11 ((uint32_t)0x00000800U)
+#define GPIO_ODR_OD12 ((uint32_t)0x00001000U)
+#define GPIO_ODR_OD13 ((uint32_t)0x00002000U)
+#define GPIO_ODR_OD14 ((uint32_t)0x00004000U)
+#define GPIO_ODR_OD15 ((uint32_t)0x00008000U)
/****************** Bit definition for GPIO_BSRR register ********************/
-#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U)
/****************** Bit definition for GPIO_LCKR register ********************/
-#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000U)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU)
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U)
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U)
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U)
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U)
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U)
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U)
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U)
/****************** Bit definition for GPIO_BRR register *********************/
-#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
-#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
-#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
-#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
-#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
-#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
-#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
-#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
-#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
-#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
-#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
-#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
-#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
-#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
-#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
-#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001U)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002U)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004U)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008U)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010U)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020U)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040U)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080U)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100U)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200U)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400U)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800U)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000U)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000U)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000U)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000U)
/******************************************************************************/
/* */
@@ -1836,102 +1966,110 @@
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register *******************/
-#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
-#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
-#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
-#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
-#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
-#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+#define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */
/****************** Bit definition for I2C_CR2 register ********************/
-#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
-#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
-#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+#define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */
/******************* Bit definition for I2C_OAR1 register ******************/
-#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register ******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
-#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */
/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */
/****************** Bit definition for I2C_ISR register *********************/
-#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
-#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
-#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
-#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
-#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
-#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
-#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
-#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
-#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
-#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+#define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */
/****************** Bit definition for I2C_ICR register *********************/
-#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
-#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */
/****************** Bit definition for I2C_PECR register *********************/
-#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+#define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */
/****************** Bit definition for I2C_RXDR register *********************/
-#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */
/****************** Bit definition for I2C_TXDR register *********************/
-#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */
/******************************************************************************/
/* */
@@ -1939,24 +2077,24 @@
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
+#define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!< Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
-#define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define IWDG_PR_PR ((uint32_t)0x00000007U) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
/******************* Bit definition for IWDG_RLR register *******************/
-#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
+#define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!< Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
-#define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
+#define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint32_t)0x00000004U) /*!< Watchdog counter window value update */
/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
+#define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /*!< Watchdog counter window value */
/******************************************************************************/
/* */
@@ -1965,64 +2103,66 @@
/******************************************************************************/
/******************* Bit definition for LCD_CR register *********************/
-#define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */
-#define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */
-#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */
-#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */
-
-#define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
-#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
+#define LCD_CR_LCDEN ((uint32_t)0x00000001U) /*!< LCD Enable Bit */
+#define LCD_CR_VSEL ((uint32_t)0x00000002U) /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY ((uint32_t)0x0000001CU) /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0 ((uint32_t)0x00000004U) /*!< Duty selector Bit 0 */
+#define LCD_CR_DUTY_1 ((uint32_t)0x00000008U) /*!< Duty selector Bit 1 */
+#define LCD_CR_DUTY_2 ((uint32_t)0x00000010U) /*!< Duty selector Bit 2 */
+
+#define LCD_CR_BIAS ((uint32_t)0x00000060U) /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0 ((uint32_t)0x00000020U) /*!< Bias selector Bit 0 */
+#define LCD_CR_BIAS_1 ((uint32_t)0x00000040U) /*!< Bias selector Bit 1 */
+
+#define LCD_CR_MUX_SEG ((uint32_t)0x00000080U) /*!< Mux Segment Enable Bit */
/******************* Bit definition for LCD_FCR register ********************/
-#define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-
-#define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */
-#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */
-#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */
-
-#define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-
-#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */
-#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */
-#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */
-
-#define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-
-#define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */
+#define LCD_FCR_HD ((uint32_t)0x00000001U) /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE ((uint32_t)0x00000002U) /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE ((uint32_t)0x00000008U) /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON ((uint32_t)0x00000070U) /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
+#define LCD_FCR_PON_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
+#define LCD_FCR_PON_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
+
+#define LCD_FCR_DEAD ((uint32_t)0x00000380U) /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080U) /*!< Bit 0 */
+#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100U) /*!< Bit 1 */
+#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200U) /*!< Bit 2 */
+
+#define LCD_FCR_CC ((uint32_t)0x00001C00U) /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
+#define LCD_FCR_CC_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
+#define LCD_FCR_CC_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
+
+#define LCD_FCR_BLINKF ((uint32_t)0x0000E000U) /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
+#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
+#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
+
+#define LCD_FCR_BLINK ((uint32_t)0x00030000U) /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
+#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
+
+#define LCD_FCR_DIV ((uint32_t)0x003C0000U) /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS ((uint32_t)0x03C00000U) /*!< PS[3:0] bits (Prescaler) */
/******************* Bit definition for LCD_SR register *********************/
-#define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */
-#define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */
-#define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */
+#define LCD_SR_ENS ((uint32_t)0x00000001U) /*!< LCD Enabled Bit */
+#define LCD_SR_SOF ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR ((uint32_t)0x00000004U) /*!< Update Display Request Bit */
+#define LCD_SR_UDD ((uint32_t)0x00000008U) /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY ((uint32_t)0x00000010U) /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR ((uint32_t)0x00000020U) /*!< LCD FCR Register Synchronization Flag Bit */
/******************* Bit definition for LCD_CLR register ********************/
-#define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */
+#define LCD_CLR_SOFC ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC ((uint32_t)0x00000008U) /*!< Update Display Done Flag Clear Bit */
/******************* Bit definition for LCD_RAM register ********************/
-#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */
+#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFFU) /*!< Segment Data Bits */
/******************************************************************************/
/* */
@@ -2030,81 +2170,81 @@
/* */
/******************************************************************************/
/****************** Bit definition for LPTIM_ISR register *******************/
-#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */
-#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
+#define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /*!< Compare match */
+#define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP ((uint32_t)0x00000020U) /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /*!< Counter direction change up to down */
/****************** Bit definition for LPTIM_ICR register *******************/
-#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
+#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /*!< Counter direction change up to down Clear Flag */
/****************** Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
+#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /*!< Counter direction change up to down Interrupt Enable */
/****************** Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */
-#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */
-
-#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-
-#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-
-#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */
-#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */
-#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */
-
-#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */
-#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */
-#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */
-
-#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */
-#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */
-
-#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */
-#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
+#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /*!< Bit 0 */
+#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /*!< Bit 1 */
+
+#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
+#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
+
+#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
+#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
+
+#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
+#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
+#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
+#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
+
+#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /*!< Timout enable */
+#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /*!< Encoder mode enable */
/****************** Bit definition for LPTIM_CR register ********************/
-#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */
+#define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /*!< Timer start in continuous mode */
/****************** Bit definition for LPTIM_CMP register *******************/
-#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */
+#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /*!< Compare register */
/****************** Bit definition for LPTIM_ARR register *******************/
-#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */
+#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!< Auto reload register */
/****************** Bit definition for LPTIM_CNT register *******************/
-#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */
+#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!< Counter register */
/******************************************************************************/
/* */
@@ -2113,17 +2253,17 @@
/******************************************************************************/
/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD ((uint32_t)0x00FFFF00) /*!< Code Segment Start Address */
-#define FW_CSL_LENG ((uint32_t)0x003FFF00) /*!< Code Segment Length */
-#define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00) /*!< Non Volatile Dat Segment Start Address */
-#define FW_NVDSL_LENG ((uint32_t)0x003FFF00) /*!< Non Volatile Data Segment Length */
-#define FW_VDSSA_ADD ((uint32_t)0x0000FFC0) /*!< Volatile Data Segment Start Address */
-#define FW_VDSL_LENG ((uint32_t)0x0000FFC0) /*!< Volatile Data Segment Length */
+#define FW_CSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Code Segment Start Address */
+#define FW_CSL_LENG ((uint32_t)0x003FFF00U) /*!< Code Segment Length */
+#define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG ((uint32_t)0x003FFF00U) /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Length */
/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA ((uint32_t)0x00000001) /*!< Firewall Pre Arm*/
-#define FW_CR_VDS ((uint32_t)0x00000002) /*!< Volatile Data Sharing*/
-#define FW_CR_VDE ((uint32_t)0x00000004) /*!< Volatile Data Execution*/
+#define FW_CR_FPA ((uint32_t)0x00000001U) /*!< Firewall Pre Arm*/
+#define FW_CR_VDS ((uint32_t)0x00000002U) /*!< Volatile Data Sharing*/
+#define FW_CR_VDE ((uint32_t)0x00000004U) /*!< Volatile Data Execution*/
/******************************************************************************/
/* */
@@ -2132,48 +2272,48 @@
/******************************************************************************/
/******************** Bit definition for PWR_CR register ********************/
-#define PWR_CR_LPSDSR ((uint32_t)0x00000001) /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
-#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
-#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
-#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define PWR_CR_LPSDSR ((uint32_t)0x00000001U) /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS ((uint32_t)0x00000002U) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004U) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008U) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010U) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0U) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
-
-#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP ((uint32_t)0x00000200) /*!< Ultra Low Power mode */
-#define PWR_CR_FWU ((uint32_t)0x00000400) /*!< Fast wakeup */
-
-#define PWR_CR_VOS ((uint32_t)0x00001800) /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0 ((uint32_t)0x00000800) /*!< Bit 0 */
-#define PWR_CR_VOS_1 ((uint32_t)0x00001000) /*!< Bit 1 */
-#define PWR_CR_DSEEKOFF ((uint32_t)0x00002000) /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN ((uint32_t)0x00004000) /*!< Low power run mode */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100U) /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP ((uint32_t)0x00000200U) /*!< Ultra Low Power mode */
+#define PWR_CR_FWU ((uint32_t)0x00000400U) /*!< Fast wakeup */
+
+#define PWR_CR_VOS ((uint32_t)0x00001800U) /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
+#define PWR_CR_VOS_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
+#define PWR_CR_DSEEKOFF ((uint32_t)0x00002000U) /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN ((uint32_t)0x00004000U) /*!< Low power run mode */
/******************* Bit definition for PWR_CSR register ********************/
-#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
-#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
-#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF ((uint32_t)0x00000010) /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF ((uint32_t)0x00000020) /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
+#define PWR_CSR_WUF ((uint32_t)0x00000001U) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002U) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004U) /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF ((uint32_t)0x00000010U) /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF ((uint32_t)0x00000020U) /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3 ((uint32_t)0x00000400U) /*!< Enable WKUP pin 3 */
/******************************************************************************/
/* */
@@ -2182,345 +2322,418 @@
/******************************************************************************/
/******************** Bit definition for RCC_CR register ********************/
-#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON ((uint32_t)0x00000002) /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY ((uint32_t)0x00000004) /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN ((uint32_t)0x00000008) /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF ((uint32_t)0x00000010) /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN ((uint32_t)0x00000020) /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON ((uint32_t)0x00080000) /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE ((uint32_t)0x00300000) /*!< RTC/LCD prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000) /*!< RTC/LCD prescaler Bit 0 */
-#define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000) /*!< RTC/LCD prescaler Bit 1 */
-#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
-#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+#define RCC_CR_HSION ((uint32_t)0x00000001U) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON ((uint32_t)0x00000002U) /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000004U) /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN ((uint32_t)0x00000008U) /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF ((uint32_t)0x00000010U) /*!< Internal High Speed clock divider flag */
+#define RCC_CR_HSIOUTEN ((uint32_t)0x00000020U) /*!< Internal High Speed clock out enable */
+#define RCC_CR_MSION ((uint32_t)0x00000100U) /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY ((uint32_t)0x00000200U) /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON ((uint32_t)0x00080000U) /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE ((uint32_t)0x00300000U) /*!< RTC/LCD prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000U) /*!< RTC/LCD prescaler Bit 0 */
+#define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000U) /*!< RTC/LCD prescaler Bit 1 */
+#define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
/******************** Bit definition for RCC_ICSCR register *****************/
-#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */
-#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */
-#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */
-#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */
-#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */
-#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */
-#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */
-#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */
+#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FFU) /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00U) /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000U) /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed clock Range 65.536 KHz */
+#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000U) /*!< Internal Multi Speed clock Range 131.072 KHz */
+#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000U) /*!< Internal Multi Speed clock Range 262.144 KHz */
+#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000U) /*!< Internal Multi Speed clock Range 524.288 KHz */
+#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000U) /*!< Internal Multi Speed clock Range 1.048 MHz */
+#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000U) /*!< Internal Multi Speed clock Range 2.097 MHz */
+#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000U) /*!< Internal Multi Speed clock Range 4.194 MHz */
+#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000U) /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000U) /*!< Internal Multi Speed clock trimming */
/******************** Bit definition for RCC_CRRCR register *****************/
-#define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001) /*!< HSI 48MHz clock enable */
-#define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002) /*!< HSI 48MHz clock ready flag */
-#define RCC_CRRCR_HSI48DIV6OUTEN ((uint32_t)0x00000004) /*!< HSI 48MHz DIV6 out enable */
-#define RCC_CRRCR_HSI48CAL ((uint32_t)0x0000FF00) /*!< HSI 48MHz clock Calibration */
+#define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001U) /*!< HSI 48MHz clock enable */
+#define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002U) /*!< HSI 48MHz clock ready flag */
+#define RCC_CRRCR_HSI48DIV6OUTEN ((uint32_t)0x00000004U) /*!< HSI 48MHz DIV6 out enable */
+#define RCC_CRRCR_HSI48CAL ((uint32_t)0x0000FF00U) /*!< HSI 48MHz clock Calibration */
/******************* Bit definition for RCC_CFGR register *******************/
/*!< SW configuration */
-#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-
-#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selected as system clock */
/*!< SWS configuration */
-#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-
-#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */
/*!< HPRE configuration */
-#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
-#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
-#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000) /*!< Wake Up from Stop Clock selection */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /*!< Wake Up from Stop Clock selection */
/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000U) /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000U) /*!< HSE as PLL entry clock source */
/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
-
-#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000U) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000U) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000U) /*!< PLL input clock * 48 */
/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */
-#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */
-
-#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */
+#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000U) /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000U) /*!< Bit0 */
+#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000U) /*!< Bit1 */
+
+#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000U) /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000U) /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000U) /*!< PLL clock output = CKVCO / 4 */
/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */
-#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */
-#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */
-#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
+#define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000U) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
+#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
+#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
+#define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000U) /*!< Bit 3 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000U) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000U) /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000U) /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000U) /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000U) /*!< PLL clock divided */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000U) /*!< LSI selected */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000U) /*!< LSE selected */
+#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000U) /*!< HSI48 clock selected as MCO source */
+
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!< MCO is divided by 8 */
+
+#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
/*!<****************** Bit definition for RCC_CIER register ********************/
-#define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001) /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE ((uint32_t)0x00000002) /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004) /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE ((uint32_t)0x00000008) /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010) /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020) /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIER_LSECSSIE ((uint32_t)0x00000080) /*!< LSE CSS Interrupt Enable */
+#define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE ((uint32_t)0x00000080U) /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
/*!<****************** Bit definition for RCC_CIFR register ********************/
-#define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIFR_LSECSSF ((uint32_t)0x00000080) /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSF ((uint32_t)0x00000100) /*!< Clock Security System Interrupt flag */
+#define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
/*!<****************** Bit definition for RCC_CICR register ********************/
-#define RCC_CICR_LSIRDYC ((uint32_t)0x00000001) /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC ((uint32_t)0x00000002) /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC ((uint32_t)0x00000004) /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC ((uint32_t)0x00000008) /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC ((uint32_t)0x00000010) /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC ((uint32_t)0x00000020) /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_HSI48RDYC ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CICR_LSECSSC ((uint32_t)0x00000080) /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSC ((uint32_t)0x00000100) /*!< Clock Security System Interrupt Clear */
-
+#define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_HSI48RDYC ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
/***************** Bit definition for RCC_IOPRSTR register ******************/
-#define RCC_IOPRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIO port E reset */
-#define RCC_IOPRSTR_GPIOHRST ((uint32_t)0x00000080) /*!< GPIO port H reset */
+#define RCC_IOPRSTR_IOPARST ((uint32_t)0x00000001U) /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST ((uint32_t)0x00000002U) /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST ((uint32_t)0x00000004U) /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST ((uint32_t)0x00000008U) /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPERST ((uint32_t)0x00000010U) /*!< GPIO port E reset */
+#define RCC_IOPRSTR_IOPHRST ((uint32_t)0x00000080U) /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
+#define RCC_IOPRSTR_GPIOERST RCC_IOPRSTR_IOPERST /*!< GPIO port E reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
/****************** Bit definition for RCC_AHBRST register ******************/
-#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x00000001) /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100) /*!< Memory interface reset reset */
-#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
-#define RCC_AHBRSTR_TSCRST ((uint32_t)0x00010000) /*!< TSC reset */
-#define RCC_AHBRSTR_RNGRST ((uint32_t)0x00100000) /*!< RNG reset */
+#define RCC_AHBRSTR_DMARST ((uint32_t)0x00000001U) /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100U) /*!< Memory interface reset reset */
+#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000U) /*!< CRC reset */
+#define RCC_AHBRSTR_TSCRST ((uint32_t)0x00010000U) /*!< TSC reset */
+#define RCC_AHBRSTR_RNGRST ((uint32_t)0x00100000U) /*!< RNG reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
/***************** Bit definition for RCC_APB2RSTR register *****************/
-#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
-#define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004) /*!< TIM21 clock reset */
-#define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020) /*!< TIM22 clock reset */
-#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 clock reset */
-#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
-#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
-#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U) /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004U) /*!< TIM21 clock reset */
+#define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020U) /*!< TIM22 clock reset */
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200U) /*!< ADC1 clock reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U) /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000U) /*!< USART1 clock reset */
+#define RCC_APB2RSTR_DBGRST ((uint32_t)0x00400000U) /*!< DBGMCU clock reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 clock reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU clock reset */
/***************** Bit definition for RCC_APB1RSTR register *****************/
-#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
-#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
-#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
-#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
-#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD clock reset */
-#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
-#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
-#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
-#define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000) /*!< LPUART1 clock reset */
-#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART4 clock reset */
-#define RCC_APB1RSTR_USART5RST ((uint32_t)0x00100000) /*!< USART5 clock reset */
-#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
-#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
-#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
-#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
-#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
-#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
-#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /*!< I2C 3 clock reset */
-#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000) /*!< LPTIM1 clock reset */
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001U) /*!< Timer 2 clock reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002U) /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010U) /*!< Timer 6 clock reset */
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020U) /*!< Timer 7 clock reset */
+#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200U) /*!< LCD clock reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800U) /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000U) /*!< SPI2 clock reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000U) /*!< USART 2 clock reset */
+#define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000U) /*!< LPUART1 clock reset */
+#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000U) /*!< USART4 clock reset */
+#define RCC_APB1RSTR_USART5RST ((uint32_t)0x00100000U) /*!< USART5 clock reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000U) /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000U) /*!< I2C 2 clock reset */
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000U) /*!< USB clock reset */
+#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000U) /*!< CRS clock reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000U) /*!< PWR clock reset */
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000U) /*!< DAC clock reset */
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000U) /*!< I2C 3 clock reset */
+#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000U) /*!< LPTIM1 clock reset */
/***************** Bit definition for RCC_IOPENR register ******************/
-#define RCC_IOPENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIO port E clock enable */
-#define RCC_IOPENR_GPIOHEN ((uint32_t)0x00000080) /*!< GPIO port H clock enable */
+#define RCC_IOPENR_IOPAEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPDEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enable */
+#define RCC_IOPENR_IOPEEN ((uint32_t)0x00000010U) /*!< GPIO port E clock enable */
+#define RCC_IOPENR_IOPHEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
+#define RCC_IOPENR_GPIOEEN RCC_IOPENR_IOPEEN /*!< GPIO port E clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
/***************** Bit definition for RCC_AHBENR register ******************/
-#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN ((uint32_t)0x00000100) /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
-#define RCC_AHBENR_TSCEN ((uint32_t)0x00010000) /*!< TSC clock enable */
-#define RCC_AHBENR_RNGEN ((uint32_t)0x00100000) /*!< RNG clock enable */
+#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001U) /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000U) /*!< CRC clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x00010000U) /*!< TSC clock enable */
+#define RCC_AHBENR_RNGEN ((uint32_t)0x00100000U) /*!< RNG clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
/***************** Bit definition for RCC_APB2ENR register ******************/
-#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004) /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020) /*!< TIM22 clock enable */
-#define RCC_APB2ENR_MIFIEN ((uint32_t)0x00000080) /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004U) /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020U) /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U) /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200U) /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000U) /*!< USART1 clock enable */
+#define RCC_APB2ENR_DBGEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
/***************** Bit definition for RCC_APB1ENR register ******************/
-#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000) /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
-#define RCC_APB1ENR_USART5EN ((uint32_t)0x00100000) /*!< USART5 clock enable */
-#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
-#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
-#define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /*!< I2C3 clock enable */
-#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000) /*!< LPTIM1 clock enable */
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001U) /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002U) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010U) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020U) /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200U) /*!< LCD clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000U) /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000U) /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000U) /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000U) /*!< USART4 clock enable */
+#define RCC_APB1ENR_USART5EN ((uint32_t)0x00100000U) /*!< USART5 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000U) /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000U) /*!< I2C2 clock enable */
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000U) /*!< USB clock enable */
+#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000U) /*!< CRS clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000U) /*!< PWR clock enable */
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000U) /*!< DAC clock enable */
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000U) /*!< I2C3 clock enable */
+#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enable */
/****************** Bit definition for RCC_IOPSMENR register ****************/
-#define RCC_IOPSMENR_GPIOASMEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOESMEN ((uint32_t)0x00000010) /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN ((uint32_t)0x00000080) /*!< GPIO port H clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPASMEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPESMEN ((uint32_t)0x00000010U) /*!< GPIO port E clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOESMEN RCC_IOPSMENR_IOPESMEN /*!< GPIO port E clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
/***************** Bit definition for RCC_AHBSMENR register ******************/
-#define RCC_AHBSMENR_DMA1SMEN ((uint32_t)0x00000001) /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100) /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200) /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_TSCSMEN ((uint32_t)0x00010000) /*!< TSC clock enabled in sleep mode */
-#define RCC_AHBSMENR_RNGSMEN ((uint32_t)0x00100000) /*!< RNG clock enabled in sleep mode */
+#define RCC_AHBSMENR_DMASMEN ((uint32_t)0x00000001U) /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200U) /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000U) /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBSMENR_TSCSMEN ((uint32_t)0x00010000U) /*!< TSC clock enabled in sleep mode */
+#define RCC_AHBSMENR_RNGSMEN ((uint32_t)0x00100000U) /*!< RNG clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
/***************** Bit definition for RCC_APB2SMENR register ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001) /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004) /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020) /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADC1SMEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN ((uint32_t)0x00400000) /*!< DBGMCU clock enabled in sleep mode */
+#define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004U) /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020U) /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN ((uint32_t)0x00000200U) /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U) /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000U) /*!< USART1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
/***************** Bit definition for RCC_APB1SMENR register ******************/
-#define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM3SMEN ((uint32_t)0x00000002) /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM7SMEN ((uint32_t)0x00000020) /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LCDSMEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN ((uint32_t)0x00004000) /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000) /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000) /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART4SMEN ((uint32_t)0x00080000) /*!< USART4 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART5SMEN ((uint32_t)0x00100000) /*!< USART5 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000) /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN ((uint32_t)0x00400000) /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USBSMEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */
-#define RCC_APB1SMENR_CRSSMEN ((uint32_t)0x08000000) /*!< CRS clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000) /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_DACSMEN ((uint32_t)0x20000000) /*!< DAC clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C3SMEN ((uint32_t)0x40000000) /*!< I2C3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000) /*!< LPTIM1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001U) /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM3SMEN ((uint32_t)0x00000002U) /*!< Timer 3 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM6SMEN ((uint32_t)0x00000010U) /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM7SMEN ((uint32_t)0x00000020U) /*!< Timer 7 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LCDSMEN ((uint32_t)0x00000200U) /*!< LCD clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_SPI2SMEN ((uint32_t)0x00004000U) /*!< SPI2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000U) /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000U) /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART4SMEN ((uint32_t)0x00080000U) /*!< USART4 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART5SMEN ((uint32_t)0x00100000U) /*!< USART5 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000U) /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C2SMEN ((uint32_t)0x00400000U) /*!< I2C2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USBSMEN ((uint32_t)0x00800000U) /*!< USB clock enabled in sleep mode */
+#define RCC_APB1SMENR_CRSSMEN ((uint32_t)0x08000000U) /*!< CRS clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000U) /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_DACSMEN ((uint32_t)0x20000000U) /*!< DAC clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C3SMEN ((uint32_t)0x40000000U) /*!< I2C3 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enabled in sleep mode */
/******************* Bit definition for RCC_CCIPR register *******************/
/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003) /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003U) /*!< USART1SEL[1:0] bits */
+#define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000C) /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU) /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
+#define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
/*!< LPUART1 Clock source selection */
#define RCC_CCIPR_LPUART1SEL ((uint32_t)0x0000C00) /*!< LPUART1SEL[1:0] bits */
@@ -2528,63 +2741,67 @@
#define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */
/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000) /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U) /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
+#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
/*!< I2C3 Clock source selection */
-#define RCC_CCIPR_I2C3SEL ((uint32_t)0x00030000) /*!< I2C3SEL [1:0] bits */
-#define RCC_CCIPR_I2C3SEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define RCC_CCIPR_I2C3SEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define RCC_CCIPR_I2C3SEL ((uint32_t)0x00030000U) /*!< I2C3SEL [1:0] bits */
+#define RCC_CCIPR_I2C3SEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
+#define RCC_CCIPR_I2C3SEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
/*!< LPTIM1 Clock source selection */
-#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000) /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U) /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
+#define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
/*!< HSI48 Clock source selection */
-#define RCC_CCIPR_HSI48SEL ((uint32_t)0x04000000) /*!< HSI48 RC clock source selection bit for USB and RNG*/
-
-/* Bit name alias maintained for legacy */
+#define RCC_CCIPR_HSI48SEL ((uint32_t)0x04000000U) /*!< HSI48 RC clock source selection bit for USB and RNG*/
+
+/* Legacy defines */
#define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
/******************* Bit definition for RCC_CSR register *******************/
-#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */
+#define RCC_CSR_LSION ((uint32_t)0x00000001U) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002U) /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON ((uint32_t)0x00000100U) /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY ((uint32_t)0x00000200U) /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP ((uint32_t)0x00000400U) /*!< External Low Speed oscillator Bypass */
-#define RCC_CSR_LSEDRV ((uint32_t)0x00001800) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800) /*!< Bit 0 */
-#define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CSR_LSEDRV ((uint32_t)0x00001800U) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
+#define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
-#define RCC_CSR_LSECSSON ((uint32_t)0x00002000) /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD ((uint32_t)0x00004000) /*!< External Low Speed oscillator CSS Detected */
+#define RCC_CSR_LSECSSON ((uint32_t)0x00002000U) /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD ((uint32_t)0x00004000U) /*!< External Low Speed oscillator CSS Detected */
/*!< RTC congiguration */
-#define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define RCC_CSR_RTCSEL ((uint32_t)0x00030000U) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
+#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
-#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000U) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000U) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000U) /*!< HSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCEN ((uint32_t)0x00040000) /*!< RTC clock enable */
-#define RCC_CSR_RTCRST ((uint32_t)0x00080000) /*!< RTC software reset */
-
-#define RCC_CSR_RMVF ((uint32_t)0x00800000) /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF ((uint32_t)0x01000000) /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBL ((uint32_t)0x02000000) /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+#define RCC_CSR_RTCEN ((uint32_t)0x00040000U) /*!< RTC clock enable */
+#define RCC_CSR_RTCRST ((uint32_t)0x00080000U) /*!< RTC software reset */
+
+#define RCC_CSR_RMVF ((uint32_t)0x00800000U) /*!< Remove reset flag */
+#define RCC_CSR_FWRSTF ((uint32_t)0x01000000U) /*!< Mifare Firewall reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000U) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000U) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U) /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
/******************************************************************************/
/* */
@@ -2592,15 +2809,15 @@
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
-#define RNG_CR_RNGEN ((uint32_t)0x00000004)
-#define RNG_CR_IE ((uint32_t)0x00000008)
+#define RNG_CR_RNGEN ((uint32_t)0x00000004U)
+#define RNG_CR_IE ((uint32_t)0x00000008U)
/******************** Bits definition for RNG_SR register *******************/
-#define RNG_SR_DRDY ((uint32_t)0x00000001)
-#define RNG_SR_CECS ((uint32_t)0x00000002)
-#define RNG_SR_SECS ((uint32_t)0x00000004)
-#define RNG_SR_CEIS ((uint32_t)0x00000020)
-#define RNG_SR_SEIS ((uint32_t)0x00000040)
+#define RNG_SR_DRDY ((uint32_t)0x00000001U)
+#define RNG_SR_CECS ((uint32_t)0x00000002U)
+#define RNG_SR_SECS ((uint32_t)0x00000004U)
+#define RNG_SR_CEIS ((uint32_t)0x00000020U)
+#define RNG_SR_SEIS ((uint32_t)0x00000040U)
/******************************************************************************/
/* */
@@ -2608,345 +2825,363 @@
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
-#define RTC_TR_PM ((uint32_t)0x00400000) /*!< */
-#define RTC_TR_HT ((uint32_t)0x00300000) /*!< */
-#define RTC_TR_HT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_TR_HT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_TR_HU ((uint32_t)0x000F0000) /*!< */
-#define RTC_TR_HU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_TR_HU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_TR_HU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_TR_HU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_TR_MNT ((uint32_t)0x00007000) /*!< */
-#define RTC_TR_MNT_0 ((uint32_t)0x00001000) /*!< */
-#define RTC_TR_MNT_1 ((uint32_t)0x00002000) /*!< */
-#define RTC_TR_MNT_2 ((uint32_t)0x00004000) /*!< */
-#define RTC_TR_MNU ((uint32_t)0x00000F00) /*!< */
-#define RTC_TR_MNU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TR_MNU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TR_MNU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TR_MNU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_TR_ST ((uint32_t)0x00000070) /*!< */
-#define RTC_TR_ST_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_TR_ST_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_TR_ST_2 ((uint32_t)0x00000040) /*!< */
-#define RTC_TR_SU ((uint32_t)0x0000000F) /*!< */
-#define RTC_TR_SU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_TR_SU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_TR_SU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_TR_SU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_TR_PM ((uint32_t)0x00400000U) /*!< */
+#define RTC_TR_HT ((uint32_t)0x00300000U) /*!< */
+#define RTC_TR_HT_0 ((uint32_t)0x00100000U) /*!< */
+#define RTC_TR_HT_1 ((uint32_t)0x00200000U) /*!< */
+#define RTC_TR_HU ((uint32_t)0x000F0000U) /*!< */
+#define RTC_TR_HU_0 ((uint32_t)0x00010000U) /*!< */
+#define RTC_TR_HU_1 ((uint32_t)0x00020000U) /*!< */
+#define RTC_TR_HU_2 ((uint32_t)0x00040000U) /*!< */
+#define RTC_TR_HU_3 ((uint32_t)0x00080000U) /*!< */
+#define RTC_TR_MNT ((uint32_t)0x00007000U) /*!< */
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000U) /*!< */
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000U) /*!< */
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000U) /*!< */
+#define RTC_TR_MNU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_TR_ST ((uint32_t)0x00000070U) /*!< */
+#define RTC_TR_ST_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_TR_ST_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_TR_ST_2 ((uint32_t)0x00000040U) /*!< */
+#define RTC_TR_SU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_TR_SU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_TR_SU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_TR_SU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_TR_SU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_DR register *******************/
-#define RTC_DR_YT ((uint32_t)0x00F00000) /*!< */
-#define RTC_DR_YT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_DR_YT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_DR_YT_2 ((uint32_t)0x00400000) /*!< */
-#define RTC_DR_YT_3 ((uint32_t)0x00800000) /*!< */
-#define RTC_DR_YU ((uint32_t)0x000F0000) /*!< */
-#define RTC_DR_YU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_DR_YU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_DR_YU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_DR_YU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_DR_WDU ((uint32_t)0x0000E000) /*!< */
-#define RTC_DR_WDU_0 ((uint32_t)0x00002000) /*!< */
-#define RTC_DR_WDU_1 ((uint32_t)0x00004000) /*!< */
-#define RTC_DR_WDU_2 ((uint32_t)0x00008000) /*!< */
-#define RTC_DR_MT ((uint32_t)0x00001000) /*!< */
-#define RTC_DR_MU ((uint32_t)0x00000F00) /*!< */
-#define RTC_DR_MU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_DR_MU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_DR_MU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_DR_MU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_DR_DT ((uint32_t)0x00000030) /*!< */
-#define RTC_DR_DT_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_DR_DT_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_DR_DU ((uint32_t)0x0000000F) /*!< */
-#define RTC_DR_DU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_DR_DU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_DR_DU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_DR_DU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_DR_YT ((uint32_t)0x00F00000U) /*!< */
+#define RTC_DR_YT_0 ((uint32_t)0x00100000U) /*!< */
+#define RTC_DR_YT_1 ((uint32_t)0x00200000U) /*!< */
+#define RTC_DR_YT_2 ((uint32_t)0x00400000U) /*!< */
+#define RTC_DR_YT_3 ((uint32_t)0x00800000U) /*!< */
+#define RTC_DR_YU ((uint32_t)0x000F0000U) /*!< */
+#define RTC_DR_YU_0 ((uint32_t)0x00010000U) /*!< */
+#define RTC_DR_YU_1 ((uint32_t)0x00020000U) /*!< */
+#define RTC_DR_YU_2 ((uint32_t)0x00040000U) /*!< */
+#define RTC_DR_YU_3 ((uint32_t)0x00080000U) /*!< */
+#define RTC_DR_WDU ((uint32_t)0x0000E000U) /*!< */
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000U) /*!< */
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000U) /*!< */
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000U) /*!< */
+#define RTC_DR_MT ((uint32_t)0x00001000U) /*!< */
+#define RTC_DR_MU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_DR_MU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_DR_MU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_DR_MU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_DR_MU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_DR_DT ((uint32_t)0x00000030U) /*!< */
+#define RTC_DR_DT_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_DR_DT_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_DR_DU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_DR_DU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_DR_DU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_DR_DU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_DR_DU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_CR register *******************/
-#define RTC_CR_COE ((uint32_t)0x00800000) /*!< */
-#define RTC_CR_OSEL ((uint32_t)0x00600000) /*!< */
-#define RTC_CR_OSEL_0 ((uint32_t)0x00200000) /*!< */
-#define RTC_CR_OSEL_1 ((uint32_t)0x00400000) /*!< */
-#define RTC_CR_POL ((uint32_t)0x00100000) /*!< */
-#define RTC_CR_COSEL ((uint32_t)0x00080000) /*!< */
-#define RTC_CR_BCK ((uint32_t)0x00040000) /*!< */
-#define RTC_CR_SUB1H ((uint32_t)0x00020000) /*!< */
-#define RTC_CR_ADD1H ((uint32_t)0x00010000) /*!< */
-#define RTC_CR_TSIE ((uint32_t)0x00008000) /*!< */
-#define RTC_CR_WUTIE ((uint32_t)0x00004000) /*!< */
-#define RTC_CR_ALRBIE ((uint32_t)0x00002000) /*!< */
-#define RTC_CR_ALRAIE ((uint32_t)0x00001000) /*!< */
-#define RTC_CR_TSE ((uint32_t)0x00000800) /*!< */
-#define RTC_CR_WUTE ((uint32_t)0x00000400) /*!< */
-#define RTC_CR_ALRBE ((uint32_t)0x00000200) /*!< */
-#define RTC_CR_ALRAE ((uint32_t)0x00000100) /*!< */
-#define RTC_CR_FMT ((uint32_t)0x00000040) /*!< */
-#define RTC_CR_BYPSHAD ((uint32_t)0x00000020) /*!< */
-#define RTC_CR_REFCKON ((uint32_t)0x00000010) /*!< */
-#define RTC_CR_TSEDGE ((uint32_t)0x00000008) /*!< */
-#define RTC_CR_WUCKSEL ((uint32_t)0x00000007) /*!< */
-#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) /*!< */
+#define RTC_CR_COE ((uint32_t)0x00800000U) /*!< */
+#define RTC_CR_OSEL ((uint32_t)0x00600000U) /*!< */
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000U) /*!< */
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000U) /*!< */
+#define RTC_CR_POL ((uint32_t)0x00100000U) /*!< */
+#define RTC_CR_COSEL ((uint32_t)0x00080000U) /*!< */
+#define RTC_CR_BCK ((uint32_t)0x00040000U) /*!< */
+#define RTC_CR_SUB1H ((uint32_t)0x00020000U) /*!< */
+#define RTC_CR_ADD1H ((uint32_t)0x00010000U) /*!< */
+#define RTC_CR_TSIE ((uint32_t)0x00008000U) /*!< */
+#define RTC_CR_WUTIE ((uint32_t)0x00004000U) /*!< */
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000U) /*!< */
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000U) /*!< */
+#define RTC_CR_TSE ((uint32_t)0x00000800U) /*!< */
+#define RTC_CR_WUTE ((uint32_t)0x00000400U) /*!< */
+#define RTC_CR_ALRBE ((uint32_t)0x00000200U) /*!< */
+#define RTC_CR_ALRAE ((uint32_t)0x00000100U) /*!< */
+#define RTC_CR_FMT ((uint32_t)0x00000040U) /*!< */
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020U) /*!< */
+#define RTC_CR_REFCKON ((uint32_t)0x00000010U) /*!< */
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008U) /*!< */
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007U) /*!< */
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U) /*!< */
/******************** Bits definition for RTC_ISR register ******************/
-#define RTC_ISR_RECALPF ((uint32_t)0x00010000) /*!< */
-#define RTC_ISR_TAMP3F ((uint32_t)0x00008000) /*!< */
-#define RTC_ISR_TAMP2F ((uint32_t)0x00004000) /*!< */
-#define RTC_ISR_TAMP1F ((uint32_t)0x00002000) /*!< */
-#define RTC_ISR_TSOVF ((uint32_t)0x00001000) /*!< */
-#define RTC_ISR_TSF ((uint32_t)0x00000800) /*!< */
-#define RTC_ISR_WUTF ((uint32_t)0x00000400) /*!< */
-#define RTC_ISR_ALRBF ((uint32_t)0x00000200) /*!< */
-#define RTC_ISR_ALRAF ((uint32_t)0x00000100) /*!< */
-#define RTC_ISR_INIT ((uint32_t)0x00000080) /*!< */
-#define RTC_ISR_INITF ((uint32_t)0x00000040) /*!< */
-#define RTC_ISR_RSF ((uint32_t)0x00000020) /*!< */
-#define RTC_ISR_INITS ((uint32_t)0x00000010) /*!< */
-#define RTC_ISR_SHPF ((uint32_t)0x00000008) /*!< */
-#define RTC_ISR_WUTWF ((uint32_t)0x00000004) /*!< */
-#define RTC_ISR_ALRBWF ((uint32_t)0x00000002) /*!< */
-#define RTC_ISR_ALRAWF ((uint32_t)0x00000001) /*!< */
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000U) /*!< */
+#define RTC_ISR_TAMP3F ((uint32_t)0x00008000U) /*!< */
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000U) /*!< */
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000U) /*!< */
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000U) /*!< */
+#define RTC_ISR_TSF ((uint32_t)0x00000800U) /*!< */
+#define RTC_ISR_WUTF ((uint32_t)0x00000400U) /*!< */
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200U) /*!< */
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100U) /*!< */
+#define RTC_ISR_INIT ((uint32_t)0x00000080U) /*!< */
+#define RTC_ISR_INITF ((uint32_t)0x00000040U) /*!< */
+#define RTC_ISR_RSF ((uint32_t)0x00000020U) /*!< */
+#define RTC_ISR_INITS ((uint32_t)0x00000010U) /*!< */
+#define RTC_ISR_SHPF ((uint32_t)0x00000008U) /*!< */
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004U) /*!< */
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002U) /*!< */
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001U) /*!< */
/******************** Bits definition for RTC_PRER register *****************/
-#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) /*!< */
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) /*!< */
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U) /*!< */
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU) /*!< */
/******************** Bits definition for RTC_WUTR register *****************/
-#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU)
/******************** Bits definition for RTC_ALRMAR register ***************/
-#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) /*!< */
-#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) /*!< */
-#define RTC_ALRMAR_DT ((uint32_t)0x30000000) /*!< */
-#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) /*!< */
-#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) /*!< */
-#define RTC_ALRMAR_DU ((uint32_t)0x0F000000) /*!< */
-#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) /*!< */
-#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) /*!< */
-#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) /*!< */
-#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) /*!< */
-#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) /*!< */
-#define RTC_ALRMAR_PM ((uint32_t)0x00400000) /*!< */
-#define RTC_ALRMAR_HT ((uint32_t)0x00300000) /*!< */
-#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_ALRMAR_HU ((uint32_t)0x000F0000) /*!< */
-#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) /*!< */
-#define RTC_ALRMAR_MNT ((uint32_t)0x00007000) /*!< */
-#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) /*!< */
-#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) /*!< */
-#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) /*!< */
-#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) /*!< */
-#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) /*!< */
-#define RTC_ALRMAR_ST ((uint32_t)0x00000070) /*!< */
-#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) /*!< */
-#define RTC_ALRMAR_SU ((uint32_t)0x0000000F) /*!< */
-#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U) /*!< */
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U) /*!< */
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000U) /*!< */
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U) /*!< */
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U) /*!< */
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000U) /*!< */
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U) /*!< */
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U) /*!< */
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U) /*!< */
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U) /*!< */
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U) /*!< */
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000U) /*!< */
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000U) /*!< */
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U) /*!< */
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U) /*!< */
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000U) /*!< */
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U) /*!< */
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U) /*!< */
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U) /*!< */
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U) /*!< */
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U) /*!< */
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000U) /*!< */
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U) /*!< */
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U) /*!< */
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U) /*!< */
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U) /*!< */
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070U) /*!< */
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U) /*!< */
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_ALRMBR register ***************/
-#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) /*!< */
-#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) /*!< */
-#define RTC_ALRMBR_DT ((uint32_t)0x30000000) /*!< */
-#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) /*!< */
-#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) /*!< */
-#define RTC_ALRMBR_DU ((uint32_t)0x0F000000) /*!< */
-#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) /*!< */
-#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) /*!< */
-#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) /*!< */
-#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) /*!< */
-#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) /*!< */
-#define RTC_ALRMBR_PM ((uint32_t)0x00400000) /*!< */
-#define RTC_ALRMBR_HT ((uint32_t)0x00300000) /*!< */
-#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_ALRMBR_HU ((uint32_t)0x000F0000) /*!< */
-#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) /*!< */
-#define RTC_ALRMBR_MNT ((uint32_t)0x00007000) /*!< */
-#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) /*!< */
-#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) /*!< */
-#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) /*!< */
-#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) /*!< */
-#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) /*!< */
-#define RTC_ALRMBR_ST ((uint32_t)0x00000070) /*!< */
-#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) /*!< */
-#define RTC_ALRMBR_SU ((uint32_t)0x0000000F) /*!< */
-#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U) /*!< */
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U) /*!< */
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000U) /*!< */
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U) /*!< */
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U) /*!< */
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000U) /*!< */
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U) /*!< */
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U) /*!< */
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U) /*!< */
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U) /*!< */
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U) /*!< */
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000U) /*!< */
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000U) /*!< */
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U) /*!< */
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U) /*!< */
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000U) /*!< */
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U) /*!< */
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U) /*!< */
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U) /*!< */
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U) /*!< */
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U) /*!< */
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000U) /*!< */
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U) /*!< */
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U) /*!< */
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U) /*!< */
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U) /*!< */
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070U) /*!< */
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U) /*!< */
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_WPR register ******************/
-#define RTC_WPR_KEY ((uint32_t)0x000000FF) /*!< */
+#define RTC_WPR_KEY ((uint32_t)0x000000FFU) /*!< */
/******************** Bits definition for RTC_SSR register ******************/
-#define RTC_SSR_SS ((uint32_t)0x0000FFFF) /*!< */
+#define RTC_SSR_SS ((uint32_t)0x0000FFFFU) /*!< */
/******************** Bits definition for RTC_SHIFTR register ***************/
-#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) /*!< */
-#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) /*!< */
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU) /*!< */
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U) /*!< */
/******************** Bits definition for RTC_TSTR register *****************/
-#define RTC_TSTR_PM ((uint32_t)0x00400000) /*!< */
-#define RTC_TSTR_HT ((uint32_t)0x00300000) /*!< */
-#define RTC_TSTR_HT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_TSTR_HT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_TSTR_HU ((uint32_t)0x000F0000) /*!< */
-#define RTC_TSTR_HU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_TSTR_HU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_TSTR_HU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_TSTR_HU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_TSTR_MNT ((uint32_t)0x00007000) /*!< */
-#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) /*!< */
-#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) /*!< */
-#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) /*!< */
-#define RTC_TSTR_MNU ((uint32_t)0x00000F00) /*!< */
-#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_TSTR_ST ((uint32_t)0x00000070) /*!< */
-#define RTC_TSTR_ST_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_TSTR_ST_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_TSTR_ST_2 ((uint32_t)0x00000040) /*!< */
-#define RTC_TSTR_SU ((uint32_t)0x0000000F) /*!< */
-#define RTC_TSTR_SU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_TSTR_SU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_TSTR_SU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_TSTR_SU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_TSTR_PM ((uint32_t)0x00400000U) /*!< */
+#define RTC_TSTR_HT ((uint32_t)0x00300000U) /*!< */
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000U) /*!< */
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000U) /*!< */
+#define RTC_TSTR_HU ((uint32_t)0x000F0000U) /*!< */
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000U) /*!< */
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000U) /*!< */
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000U) /*!< */
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000U) /*!< */
+#define RTC_TSTR_MNT ((uint32_t)0x00007000U) /*!< */
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U) /*!< */
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U) /*!< */
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U) /*!< */
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_TSTR_ST ((uint32_t)0x00000070U) /*!< */
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040U) /*!< */
+#define RTC_TSTR_SU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_TSDR register *****************/
-#define RTC_TSDR_WDU ((uint32_t)0x0000E000) /*!< */
-#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) /*!< */
-#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) /*!< */
-#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) /*!< */
-#define RTC_TSDR_MT ((uint32_t)0x00001000) /*!< */
-#define RTC_TSDR_MU ((uint32_t)0x00000F00) /*!< */
-#define RTC_TSDR_MU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TSDR_MU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TSDR_MU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TSDR_MU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_TSDR_DT ((uint32_t)0x00000030) /*!< */
-#define RTC_TSDR_DT_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_TSDR_DT_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_TSDR_DU ((uint32_t)0x0000000F) /*!< */
-#define RTC_TSDR_DU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_TSDR_DU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_TSDR_DU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_TSDR_DU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000U) /*!< */
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U) /*!< */
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U) /*!< */
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U) /*!< */
+#define RTC_TSDR_MT ((uint32_t)0x00001000U) /*!< */
+#define RTC_TSDR_MU ((uint32_t)0x00000F00U) /*!< */
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800U) /*!< */
+#define RTC_TSDR_DT ((uint32_t)0x00000030U) /*!< */
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010U) /*!< */
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020U) /*!< */
+#define RTC_TSDR_DU ((uint32_t)0x0000000FU) /*!< */
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008U) /*!< */
/******************** Bits definition for RTC_TSSSR register ****************/
-#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
-
-/******************** Bits definition for RTC_CAL register *****************/
-#define RTC_CAL_CALP ((uint32_t)0x00008000) /*!< */
-#define RTC_CAL_CALW8 ((uint32_t)0x00004000) /*!< */
-#define RTC_CAL_CALW16 ((uint32_t)0x00002000) /*!< */
-#define RTC_CAL_CALM ((uint32_t)0x000001FF) /*!< */
-#define RTC_CAL_CALM_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_CAL_CALM_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_CAL_CALM_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_CAL_CALM_3 ((uint32_t)0x00000008) /*!< */
-#define RTC_CAL_CALM_4 ((uint32_t)0x00000010) /*!< */
-#define RTC_CAL_CALM_5 ((uint32_t)0x00000020) /*!< */
-#define RTC_CAL_CALM_6 ((uint32_t)0x00000040) /*!< */
-#define RTC_CAL_CALM_7 ((uint32_t)0x00000080) /*!< */
-#define RTC_CAL_CALM_8 ((uint32_t)0x00000100) /*!< */
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU)
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000U) /*!< */
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000U) /*!< */
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000U) /*!< */
+#define RTC_CALR_CALM ((uint32_t)0x000001FFU) /*!< */
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001U) /*!< */
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002U) /*!< */
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004U) /*!< */
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008U) /*!< */
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010U) /*!< */
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020U) /*!< */
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040U) /*!< */
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080U) /*!< */
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100U) /*!< */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
/******************** Bits definition for RTC_TAMPCR register ****************/
-#define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000) /*!< */
-#define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000) /*!< */
-#define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000) /*!< */
-#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000) /*!< */
-#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000) /*!< */
-#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000) /*!< */
-#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000) /*!< */
-#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000) /*!< */
-#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000) /*!< */
-#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000) /*!< */
-#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000) /*!< */
-#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000) /*!< */
-#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000) /*!< */
-#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800) /*!< */
-#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800) /*!< */
-#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000) /*!< */
-#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700) /*!< */
-#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080) /*!< */
-#define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040) /*!< */
-#define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020) /*!< */
-#define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010) /*!< */
-#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008) /*!< */
-#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004) /*!< */
-#define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002) /*!< */
-#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001) /*!< */
+#define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000U) /*!< */
+#define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000U) /*!< */
+#define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000U) /*!< */
+#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U) /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U) /*!< */
+#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U) /*!< */
+#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000U) /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000U) /*!< */
+#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000U) /*!< */
+#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U) /*!< */
+#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U) /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U) /*!< */
+#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U) /*!< */
+#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U) /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U) /*!< */
+#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U) /*!< */
+#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U) /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U) /*!< */
+#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U) /*!< */
+#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U) /*!< */
+#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U) /*!< */
+#define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040U) /*!< */
+#define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020U) /*!< */
+#define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U) /*!< */
+#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U) /*!< */
+#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U) /*!< */
+#define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002U) /*!< */
+#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001U) /*!< */
/******************** Bits definition for RTC_ALRMASSR register *************/
-#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU)
/******************** Bits definition for RTC_ALRMBSSR register *************/
-#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU)
/******************** Bits definition for RTC_OR register ****************/
-#define RTC_OR_OUT_RMP ((uint32_t)0x00000002) /*!< */
-#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001) /*!< */
-
-/* Bit names aliases maintained for legacy */
+#define RTC_OR_OUT_RMP ((uint32_t)0x00000002U) /*!< */
+#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U) /*!< */
+
+/* Legacy defines */
#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
/******************** Bits definition for RTC_BKP0R register ****************/
-#define RTC_BKP0R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFFU) /*!< */
/******************** Bits definition for RTC_BKP1R register ****************/
-#define RTC_BKP1R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFFU) /*!< */
/******************** Bits definition for RTC_BKP2R register ****************/
-#define RTC_BKP2R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFFU) /*!< */
/******************** Bits definition for RTC_BKP3R register ****************/
-#define RTC_BKP3R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFFU) /*!< */
/******************** Bits definition for RTC_BKP4R register ****************/
-#define RTC_BKP4R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFFU) /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER ((uint32_t)0x00000005U) /*!< */
/******************************************************************************/
/* */
@@ -2954,76 +3189,76 @@
/* */
/******************************************************************************/
/******************* Bit definition for SPI_CR1 register ********************/
-#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
-#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
-#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
-#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
-#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
-#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
-#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
-#define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+#define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!< Master Selection */
+#define SPI_CR1_BR ((uint32_t)0x00000038U) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
+#define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!< Receive only */
+#define SPI_CR1_DFF ((uint32_t)0x00000800U) /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!< Bidirectional data mode enable */
/******************* Bit definition for SPI_CR2 register ********************/
-#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
-#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */
/******************** Bit definition for SPI_SR register ********************/
-#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
-#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
-#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
-#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
-#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
-#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
-#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
+#define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100U) /*!< TI frame format error */
/******************** Bit definition for SPI_DR register ********************/
-#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
+#define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!< Data Register */
/******************* Bit definition for SPI_CRCPR register ******************/
-#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!< CRC polynomial register */
/****************** Bit definition for SPI_RXCRCR register ******************/
-#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!< Rx CRC Register */
/****************** Bit definition for SPI_TXCRCR register ******************/
-#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!< Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register *****************/
-#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
-#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
-#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
-#define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x000001000) /*!<Asynchronous start enable */
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001U) /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006U) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002U) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004U) /*!<Bit 1 */
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008U) /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030U) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080U) /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300U) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400U) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800U) /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000U) /*!<Asynchronous start enable */
/****************** Bit definition for SPI_I2SPR register *******************/
-#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FFU) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100U) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200U) /*!<Master Clock Output Enable */
/******************************************************************************/
/* */
@@ -3031,219 +3266,220 @@
/* */
/******************************************************************************/
/***************** Bit definition for SYSCFG_CFGR1 register ****************/
-#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
-#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
-#define SYSCFG_CFGR1_BOOT_MODE ((uint32_t)0x00000300) /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MOD_0 ((uint32_t)0x00000100) /*!< SYSCFG_Boot mode Config Bit 0 */
-#define SYSCFG_CFGR1_BOOT_MODE_1 ((uint32_t)0x00000200) /*!< SYSCFG_Boot mode Config Bit 1 */
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003U) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001U) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002U) /*!< SYSCFG_Memory Remap Config Bit 1 */
+#define SYSCFG_CFGR1_UFB ((uint32_t)0x00000008U) /*!< User bank swapping */
+#define SYSCFG_CFGR1_BOOT_MODE ((uint32_t)0x00000300U) /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 ((uint32_t)0x00000100U) /*!< SYSCFG_Boot mode Config Bit 0 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 ((uint32_t)0x00000200U) /*!< SYSCFG_Boot mode Config Bit 1 */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
-#define SYSCFG_CFGR2_FWDISEN ((uint32_t)0x00000001) /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_CAPA ((uint32_t)0x0000003E) /*!< Connection of internal Vlcd rail to external capacitors */
-#define SYSCFG_CFGR2_CAPA_0 ((uint32_t)0x00000002)
-#define SYSCFG_CFGR2_CAPA_1 ((uint32_t)0x00000004)
-#define SYSCFG_CFGR2_CAPA_2 ((uint32_t)0x00000008)
-#define SYSCFG_CFGR2_CAPA_3 ((uint32_t)0x00000010)
-#define SYSCFG_CFGR2_CAPA_4 ((uint32_t)0x00000020)
-#define SYSCFG_CFGR2_I2C_PB6_FMP ((uint32_t)0x00000100) /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP ((uint32_t)0x00000200) /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP ((uint32_t)0x00000400) /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP ((uint32_t)0x00000800) /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP ((uint32_t)0x00001000) /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP ((uint32_t)0x00002000) /*!< I2C2 Fast mode plus */
-#define SYSCFG_CFGR2_I2C3_FMP ((uint32_t)0x00004000) /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR2_FWDISEN ((uint32_t)0x00000001U) /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_CAPA ((uint32_t)0x0000003EU) /*!< Connection of internal Vlcd rail to external capacitors */
+#define SYSCFG_CFGR2_CAPA_0 ((uint32_t)0x00000002U)
+#define SYSCFG_CFGR2_CAPA_1 ((uint32_t)0x00000004U)
+#define SYSCFG_CFGR2_CAPA_2 ((uint32_t)0x00000008U)
+#define SYSCFG_CFGR2_CAPA_3 ((uint32_t)0x00000010U)
+#define SYSCFG_CFGR2_CAPA_4 ((uint32_t)0x00000020U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP ((uint32_t)0x00000100U) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP ((uint32_t)0x00000200U) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP ((uint32_t)0x00000400U) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP ((uint32_t)0x00000800U) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP ((uint32_t)0x00001000U) /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR2_I2C2_FMP ((uint32_t)0x00002000U) /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR2_I2C3_FMP ((uint32_t)0x00004000U) /*!< I2C3 Fast mode plus */
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
-#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000FU) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0U) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00U) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000U) /*!< EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
-#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005) /*!< PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003U) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004U) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005U) /*!< PH[0] pin */
/**
* @brief EXTI1 configuration
*/
-#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050) /*!< PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030U) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040U) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050U) /*!< PH[1] pin */
/**
* @brief EXTI2 configuration
*/
-#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300U) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400U) /*!< PE[2] pin */
/**
* @brief EXTI3 configuration
*/
-#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000U) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000U) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000U) /*!< PE[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
-#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000FU) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0U) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00U) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000U) /*!< EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
-#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002U) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003U) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004U) /*!< PE[4] pin */
/**
* @brief EXTI5 configuration
*/
-#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020U) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030U) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040U) /*!< PE[5] pin */
/**
* @brief EXTI6 configuration
*/
-#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200U) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300U) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400U) /*!< PE[6] pin */
/**
* @brief EXTI7 configuration
*/
-#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000U) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000U) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000U) /*!< PE[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
-#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000FU) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0U) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00U) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000U) /*!< EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
-#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002U) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003U) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004U) /*!< PE[8] pin */
/**
* @brief EXTI9 configuration
*/
-#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000050) /*!< PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020U) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030U) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040U) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000050U) /*!< PH[9] pin */
/**
* @brief EXTI10 configuration
*/
-#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000500) /*!< PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200U) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300U) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400U) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000500U) /*!< PH[10] pin */
/**
* @brief EXTI11 configuration
*/
-#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000U) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000U) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000U) /*!< PE[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
-#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000FU) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0U) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00U) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000U) /*!< EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
-#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002U) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003U) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004U) /*!< PE[12] pin */
/**
* @brief EXTI13 configuration
*/
-#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020U) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030U) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040U) /*!< PE[13] pin */
/**
* @brief EXTI14 configuration
*/
-#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200U) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300U) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400U) /*!< PE[14] pin */
/**
* @brief EXTI15 configuration
*/
-#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000U) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000U) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000U) /*!< PE[15] pin */
/***************** Bit definition for SYSCFG_CFGR3 register ****************/
-#define SYSCFG_CFGR3_EN_VREFINT ((uint32_t)0x00000001) /*!< Vref Enable bit*/
-#define SYSCFG_CFGR3_VREF_OUT ((uint32_t)0x00000030) /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define SYSCFG_CFGR3_VREF_OUT_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC ((uint32_t)0x00000100) /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC ((uint32_t)0x00000200) /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ((uint32_t)0x00001000) /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_ENREF_HSI48 ((uint32_t)0x00002000) /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
-#define SYSCFG_CFGR3_REF_HSI48_RDYF ((uint32_t)0x04000000) /*!< VREFINT for 48 MHz RC oscillator ready flag */
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF ((uint32_t)0x08000000) /*!< Sensor for ADC ready flag */
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF ((uint32_t)0x10000000) /*!< VREFINT for ADC ready flag */
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF ((uint32_t)0x20000000) /*!< VREFINT for comparator ready flag */
-#define SYSCFG_CFGR3_VREFINT_RDYF ((uint32_t)0x40000000) /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK ((uint32_t)0x80000000) /*!< CFGR3 lock bit */
-
-/* Bit names aliases maintained for legacy */
+#define SYSCFG_CFGR3_EN_VREFINT ((uint32_t)0x00000001U) /*!< Vref Enable bit*/
+#define SYSCFG_CFGR3_VREF_OUT ((uint32_t)0x00000030U) /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
+#define SYSCFG_CFGR3_VREF_OUT_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC ((uint32_t)0x00000100U) /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC ((uint32_t)0x00000200U) /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ((uint32_t)0x00001000U) /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_ENREF_HSI48 ((uint32_t)0x00002000U) /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
+#define SYSCFG_CFGR3_REF_HSI48_RDYF ((uint32_t)0x04000000U) /*!< VREFINT for 48 MHz RC oscillator ready flag */
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF ((uint32_t)0x08000000U) /*!< Sensor for ADC ready flag */
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF ((uint32_t)0x10000000U) /*!< VREFINT for ADC ready flag */
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF ((uint32_t)0x20000000U) /*!< VREFINT for comparator ready flag */
+#define SYSCFG_CFGR3_VREFINT_RDYF ((uint32_t)0x40000000U) /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK ((uint32_t)0x80000000U) /*!< CFGR3 lock bit */
+
+/* Legacy defines */
#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
@@ -3257,322 +3493,292 @@
/* Timers (TIM) */
/* */
/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
/******************* Bit definition for TIM_CR1 register ********************/
-#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
-#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
-#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
-#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
-#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
-
-#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-
-#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_CR1_CEN ((uint32_t)0x00000001U) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002U) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004U) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008U) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010U) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060U) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080U) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300U) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
/******************* Bit definition for TIM_CR2 register ********************/
-#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-
-#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
-#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008U) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070U) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080U) /*!<TI1 Selection */
/******************* Bit definition for TIM_SMCR register *******************/
-#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-
-#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-
-#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-
-#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-
-#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
-#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+#define TIM_SMCR_SMS ((uint32_t)0x00000007U) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008U) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070U) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080U) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00U) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000U) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000U) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000U) /*!<External trigger polarity */
/******************* Bit definition for TIM_DIER register *******************/
-#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+#define TIM_DIER_UIE ((uint32_t)0x00000001U) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040U) /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100U) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200U) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400U) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800U) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000U) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000U) /*!<Trigger DMA request enable */
/******************** Bit definition for TIM_SR register ********************/
-#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
-#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
-#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_UIF ((uint32_t)0x00000001U) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040U) /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200U) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400U) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000U) /*!<Capture/Compare 4 Overcapture Flag */
/******************* Bit definition for TIM_EGR register ********************/
-#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
-#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
-#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+#define TIM_EGR_UG ((uint32_t)0x00000001U) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002U) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004U) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008U) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010U) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040U) /*!<Trigger Generation */
/****************** Bit definition for TIM_CCMR1 register *******************/
-#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003U) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004U) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008U) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00000070U) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080U) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300U) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400U) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800U) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x00007000U) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000U) /*!<Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
-#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-
-#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000CU) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0U) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00U) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000U) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
/****************** Bit definition for TIM_CCMR2 register *******************/
-#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003U) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004U) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008U) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00000070U) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080U) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300U) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400U) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800U) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x00007000U) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000U) /*!<Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
-#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
-
-#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
-#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000CU) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0U) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00U) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000U) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
/******************* Bit definition for TIM_CCER register *******************/
-#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC1E ((uint32_t)0x00000001U) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002U) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008U) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010U) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020U) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080U) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100U) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200U) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000U) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000U) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000U) /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
-#define TIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!<Counter Value */
+#define TIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!<Counter Value */
/******************* Bit definition for TIM_PSC register ********************/
-#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFFU) /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
-#define TIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!<actual auto-reload Value */
-
-/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+#define TIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_CCR1 register *******************/
-#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
-#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
-#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
-#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
-
-/******************* Bit definition for TIM_BDTR register *******************/
-#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
-#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
-#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
-
-#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-
-#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
-#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
-#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
-#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_DCR register ********************/
-#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
-
-#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
-#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
-#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
-#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define TIM_DCR_DBA ((uint32_t)0x0000001FU) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00U) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
/******************* Bit definition for TIM_DMAR register *******************/
-#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFFU) /*!<DMA register for burst accesses */
/******************* Bit definition for TIM_OR register *********************/
-#define TIM2_OR_ETR_RMP ((uint32_t)0x00000007) /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM2_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM2_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM2_OR_ETR_RMP ((uint32_t)0x00000007U) /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM2_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM2_OR_ETR_RMP_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
#define TIM2_OR_TI4_RMP ((uint32_t)0x0000018) /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0 ((uint32_t)0x00000008) /*!<Bit 0 */
-#define TIM2_OR_TI4_RMP_1 ((uint32_t)0x00000010) /*!<Bit 1 */
-
-#define TIM21_OR_ETR_RMP ((uint32_t)0x00000003) /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM21_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM21_OR_TI1_RMP ((uint32_t)0x0000001C) /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define TIM21_OR_TI1_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
-#define TIM21_OR_TI1_RMP_2 ((uint32_t)0x00000010) /*!<Bit 2 */
-#define TIM21_OR_TI2_RMP ((uint32_t)0x00000020) /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP ((uint32_t)0x00000003) /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM22_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM22_OR_TI1_RMP ((uint32_t)0x0000000C) /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
-#define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
-
-#define TIM3_OR_ETR_RMP ((uint32_t)0x00000003) /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
-#define TIM3_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM3_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM3_OR_TI1_RMP ((uint32_t)0x00000004) /*!<TI1_RMP[2] bit */
-#define TIM3_OR_TI2_RMP ((uint32_t)0x00000008) /*!<TI2_RMP[3] bit */
-#define TIM3_OR_TI4_RMP ((uint32_t)0x00000010) /*!<TI4_RMP[4] bit */
+#define TIM2_OR_TI4_RMP_0 ((uint32_t)0x00000008U) /*!<Bit 0 */
+#define TIM2_OR_TI4_RMP_1 ((uint32_t)0x00000010U) /*!<Bit 1 */
+
+#define TIM21_OR_ETR_RMP ((uint32_t)0x00000003U) /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM21_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM21_OR_TI1_RMP ((uint32_t)0x0000001CU) /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
+#define TIM21_OR_TI1_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
+#define TIM21_OR_TI1_RMP_2 ((uint32_t)0x00000010U) /*!<Bit 2 */
+#define TIM21_OR_TI2_RMP ((uint32_t)0x00000020U) /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP ((uint32_t)0x00000003U) /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM22_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM22_OR_TI1_RMP ((uint32_t)0x0000000CU) /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
+#define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
+
+#define TIM3_OR_ETR_RMP ((uint32_t)0x00000003U) /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
+#define TIM3_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
+#define TIM3_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
+#define TIM3_OR_TI1_RMP ((uint32_t)0x00000004U) /*!<TI1_RMP[2] bit */
+#define TIM3_OR_TI2_RMP ((uint32_t)0x00000008U) /*!<TI2_RMP[3] bit */
+#define TIM3_OR_TI4_RMP ((uint32_t)0x00000010U) /*!<TI4_RMP[4] bit */
/******************************************************************************/
@@ -3581,375 +3787,381 @@
/* */
/******************************************************************************/
/******************* Bit definition for TSC_CR register *********************/
-#define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
-#define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
-#define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
-
-#define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
-#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
-#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
-
-#define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
-#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
-#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
-
-#define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
-#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
-#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
-#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
-#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
-#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
-#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
-
-#define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
-#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
-#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
-#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
-
-#define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
-#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
-#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
-#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
+#define TSC_CR_TSCE ((uint32_t)0x00000001U) /*!<Touch sensing controller enable */
+#define TSC_CR_START ((uint32_t)0x00000002U) /*!<Start acquisition */
+#define TSC_CR_AM ((uint32_t)0x00000004U) /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL ((uint32_t)0x00000008U) /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF ((uint32_t)0x00000010U) /*!<IO default mode */
+
+#define TSC_CR_MCV ((uint32_t)0x000000E0U) /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
+#define TSC_CR_MCV_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
+#define TSC_CR_MCV_2 ((uint32_t)0x00000080U) /*!<Bit 2 */
+
+#define TSC_CR_PGPSC ((uint32_t)0x00007000U) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
+#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
+#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
+
+#define TSC_CR_SSPSC ((uint32_t)0x00008000U) /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE ((uint32_t)0x00010000U) /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD ((uint32_t)0x00FE0000U) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
+#define TSC_CR_SSD_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
+#define TSC_CR_SSD_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
+#define TSC_CR_SSD_3 ((uint32_t)0x00100000U) /*!<Bit 3 */
+#define TSC_CR_SSD_4 ((uint32_t)0x00200000U) /*!<Bit 4 */
+#define TSC_CR_SSD_5 ((uint32_t)0x00400000U) /*!<Bit 5 */
+#define TSC_CR_SSD_6 ((uint32_t)0x00800000U) /*!<Bit 6 */
+
+#define TSC_CR_CTPL ((uint32_t)0x0F000000U) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
+#define TSC_CR_CTPL_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
+#define TSC_CR_CTPL_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
+#define TSC_CR_CTPL_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
+
+#define TSC_CR_CTPH ((uint32_t)0xF0000000U) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
+#define TSC_CR_CTPH_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
+#define TSC_CR_CTPH_2 ((uint32_t)0x40000000U) /*!<Bit 2 */
+#define TSC_CR_CTPH_3 ((uint32_t)0x80000000U) /*!<Bit 3 */
/******************* Bit definition for TSC_IER register ********************/
-#define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
+#define TSC_IER_EOAIE ((uint32_t)0x00000001U) /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE ((uint32_t)0x00000002U) /*!<Max count error interrupt enable */
/******************* Bit definition for TSC_ICR register ********************/
-#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
+#define TSC_ICR_EOAIC ((uint32_t)0x00000001U) /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC ((uint32_t)0x00000002U) /*!<Max count error interrupt clear */
/******************* Bit definition for TSC_ISR register ********************/
-#define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
-#define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
+#define TSC_ISR_EOAF ((uint32_t)0x00000001U) /*!<End of acquisition flag */
+#define TSC_ISR_MCEF ((uint32_t)0x00000002U) /*!<Max count error flag */
/******************* Bit definition for TSC_IOHCR register ******************/
-#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
/******************* Bit definition for TSC_IOASCR register *****************/
-#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
+#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 analog switch enable */
/******************* Bit definition for TSC_IOSCR register ******************/
-#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
+#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 sampling mode */
/******************* Bit definition for TSC_IOCCR register ******************/
-#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
+#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 channel mode */
/******************* Bit definition for TSC_IOGCSR register *****************/
-#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
+#define TSC_IOGCSR_G1E ((uint32_t)0x00000001U) /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E ((uint32_t)0x00000002U) /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E ((uint32_t)0x00000004U) /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E ((uint32_t)0x00000008U) /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E ((uint32_t)0x00000010U) /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E ((uint32_t)0x00000020U) /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E ((uint32_t)0x00000040U) /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E ((uint32_t)0x00000080U) /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S ((uint32_t)0x00010000U) /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S ((uint32_t)0x00020000U) /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S ((uint32_t)0x00040000U) /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S ((uint32_t)0x00080000U) /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S ((uint32_t)0x00100000U) /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S ((uint32_t)0x00200000U) /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S ((uint32_t)0x00400000U) /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S ((uint32_t)0x00800000U) /*!<Analog IO GROUP8 status */
/******************* Bit definition for TSC_IOGXCR register *****************/
-#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
+#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFFU) /*!<CNT[13:0] bits (Counter value) */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
/****************** Bit definition for USART_CR1 register *******************/
-#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
-#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
-#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
-#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
-#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
-#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
-#define USART_CR1_M ((uint32_t)0x10001000) /*!< Word length */
-#define USART_CR1_M_0 ((uint32_t)0x00001000) /*!< Word length - Bit 0 */
-#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
-#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
-#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
-#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
-#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
-#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
-#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
-#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
-#define USART_CR1_M_1 ((uint32_t)0x10000000) /*!< Word length - Bit 1 */
+#define USART_CR1_UE ((uint32_t)0x00000001U) /*!< USART Enable */
+#define USART_CR1_UESM ((uint32_t)0x00000002U) /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE ((uint32_t)0x00000004U) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008U) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010U) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020U) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080U) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100U) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200U) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400U) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800U) /*!< Receiver Wakeup method */
+#define USART_CR1_M ((uint32_t)0x10001000U) /*!< Word length */
+#define USART_CR1_M0 ((uint32_t)0x00001000U) /*!< Word length - Bit 0 */
+#define USART_CR1_MME ((uint32_t)0x00002000U) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000U) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000U) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000U) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000U) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000U) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000U) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000U) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000U) /*!< End of Block interrupt enable */
+#define USART_CR1_M1 ((uint32_t)0x10000000U) /*!< Word length - Bit 1 */
/****************** Bit definition for USART_CR2 register *******************/
-#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
-#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
-#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
-#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
-#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
-#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
-#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
-#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
-#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010U) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL ((uint32_t)0x00000020U) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040U) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100U) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200U) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400U) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800U) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000U) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000U) /*!< LIN mode enable */
+#define USART_CR2_SWAP ((uint32_t)0x00008000U) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000U) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000U) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000U) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000U) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000U) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000U) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000U) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000U) /*!< Address of the USART node */
/****************** Bit definition for USART_CR3 register *******************/
-#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
-#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
-#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
-#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
-#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
-#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
-#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
-#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
-#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
-#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
-#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
-#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM ((uint32_t)0x00800000) /*!< Clock Enable in Stop mode */
+#define USART_CR3_EIE ((uint32_t)0x00000001U) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002U) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004U) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008U) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010U) /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020U) /*!< SmartCard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040U) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080U) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100U) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200U) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400U) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800U) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000U) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000U) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000U) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000U) /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000U) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000U) /*!< Bit 2 */
+#define USART_CR3_WUS ((uint32_t)0x00300000U) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
+#define USART_CR3_WUFIE ((uint32_t)0x00400000U) /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM ((uint32_t)0x00800000U) /*!< Clock Enable in Stop mode */
/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000FU) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0U) /*!< Mantissa of USARTDIV */
/****************** Bit definition for USART_GTPR register ******************/
-#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
+#define USART_GTPR_PSC ((uint32_t)0x000000FFU) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint32_t)0x0000FF00U) /*!< GT[7:0] bits (Guard time value) */
/******************* Bit definition for USART_RTOR register *****************/
-#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFFU) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000U) /*!< Block Length */
/******************* Bit definition for USART_RQR register ******************/
-#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
-#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
+#define USART_RQR_ABRRQ ((uint32_t)0x00000001U) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint32_t)0x00000002U) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint32_t)0x00000004U) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint32_t)0x00000008U) /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ ((uint32_t)0x00000010U) /*!< Transmit data flush Request */
/******************* Bit definition for USART_ISR register ******************/
-#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
-#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
-#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
-#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
-#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
-#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
-#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
-#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
-#define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
-#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
-#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
-#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
-#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
-#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
-#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
-#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_PE ((uint32_t)0x00000001U) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002U) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004U) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008U) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010U) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020U) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040U) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080U) /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF ((uint32_t)0x00000100U) /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200U) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400U) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800U) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000U) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000U) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000U) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000U) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000U) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000U) /*!< Send Break Flag */
+#define USART_ISR_RWU ((uint32_t)0x00080000U) /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000U) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000U) /*!< Receive Enable Acknowledge Flag */
/******************* Bit definition for USART_ICR register ******************/
-#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
+#define USART_ICR_PECF ((uint32_t)0x00000001U) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002U) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004U) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008U) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010U) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040U) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF ((uint32_t)0x00000100U) /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200U) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800U) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF ((uint32_t)0x00001000U) /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000U) /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Clear Flag */
/******************* Bit definition for USART_RDR register ******************/
-#define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
+#define USART_RDR_RDR ((uint32_t)0x000001FFU) /*!< RDR[8:0] bits (Receive Data value) */
/******************* Bit definition for USART_TDR register ******************/
-#define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
+#define USART_TDR_TDR ((uint32_t)0x000001FFU) /*!< TDR[8:0] bits (Transmit Data value) */
/******************************************************************************/
/* */
/* USB Device General registers */
/* */
/******************************************************************************/
-#define USB_BASE ((uint32_t)0x40005C00) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR ((uint32_t)0x40006000) /*!< USB_IP Packet Memory Area base address */
+#define USB_BASE ((uint32_t)0x40005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR ((uint32_t)0x40006000U) /*!< USB_IP Packet Memory Area base address */
#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
@@ -3960,17 +4172,17 @@
#define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
/**************************** ISTR interrupt events *************************/
-#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
-#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
-#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
-#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
-#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
-#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
-#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
-#define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
-#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
-#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
+#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
+#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
+#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
@@ -3982,45 +4194,45 @@
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
/************************* CNTR control register bits definitions ***********/
-#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
-#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
-#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
-#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
-#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
-#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
-#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
-#define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
-#define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
-#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
-#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
-#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
-#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
-#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
+#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
+#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
+#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
/************************* BCDR control register bits definitions ***********/
-#define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
-#define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
-#define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
-#define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
-#define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
-#define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
-#define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
-#define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
-#define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
+#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
+#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
+#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
+#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
+#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
+#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
+#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
+#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
+#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
/*************************** LPM register bits definitions ******************/
-#define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
-#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
-#define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
-#define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
+#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
+#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
/******************** FNR Frame Number Register bit definitions ************/
-#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
-#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
-#define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
-#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
-#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
+#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
+#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
+#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
+#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
+#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
/******************** DADDR Device ADDRess bit definitions ****************/
-#define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
-#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
+#define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
+#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
/****************************** Endpoint register *************************/
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
@@ -4031,43 +4243,43 @@
#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
/* bit positions */
-#define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
-#define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
-#define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
-#define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
-#define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
+#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
/* EndPoint REGister MASK (no toggle fields) */
#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
/*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
-#define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
/*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************************************************************************/
@@ -4077,35 +4289,57 @@
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
-#define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */
-
-#define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */
+#define WWDG_CR_T ((uint32_t)0x0000007FU) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define WWDG_CR_T_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
+#define WWDG_CR_T_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
+#define WWDG_CR_T_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
+#define WWDG_CR_T_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
+#define WWDG_CR_T_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
+#define WWDG_CR_T_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA ((uint32_t)0x00000080U) /*!< Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
-#define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */
-
-#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */
-#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */
-
-#define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */
+#define WWDG_CFR_W ((uint32_t)0x0000007FU) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
+#define WWDG_CFR_W_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
+#define WWDG_CFR_W_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
+#define WWDG_CFR_W_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
+#define WWDG_CFR_W_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
+#define WWDG_CFR_W_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
+#define WWDG_CFR_W_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x00000180U) /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080U) /*!< Bit 0 */
+#define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100U) /*!< Bit 1 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI ((uint32_t)0x00000200U) /*!< Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
-#define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */
+#define WWDG_SR_EWIF ((uint32_t)0x00000001U) /*!< Early Wakeup Interrupt Flag */
/**
* @}
@@ -4126,6 +4360,8 @@
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2))
+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
+
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
@@ -4150,6 +4386,13 @@
((INSTANCE) == GPIOE) || \
((INSTANCE) == GPIOH))
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
@@ -4183,6 +4426,40 @@
((INSTANCE) == TIM21) || \
((INSTANCE) == TIM22))
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
@@ -4255,6 +4532,16 @@
((INSTANCE) == TIM21) || \
((INSTANCE) == TIM22))
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
(((((INSTANCE) == TIM2) || \
@@ -4303,11 +4590,9 @@
((INSTANCE) == USART2))
/******************** UART Instances : Wake-up from Stop mode **********************/
-
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == LPUART1))
-
/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/stm32l0xx.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/stm32l0xx.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.4.0
+ * @date 01-October-2015
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@@ -77,8 +77,16 @@
application
*/
-#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) \
- && !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && \
+ !defined (STM32L031xx) && !defined (STM32L041xx) && \
+ !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && \
+ !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) && \
+ !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && \
+ !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) \
+ /* #define STM32L011xx */
+ /* #define STM32L021xx */
+ /* #define STM32L031xx */ /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */
+ /* #define STM32L041xx */ /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */
/* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */
/* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */
/* #define STM32L053xx */ /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
@@ -106,12 +114,12 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V1.2.0
+ * @brief CMSIS Device version number V1.2.0RC1
*/
#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x01) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
@@ -124,8 +132,11 @@
/** @addtogroup Device_Included
* @{
*/
-
-#if defined(STM32L031xx)
+#if defined(STM32L011xx)
+ #include "stm32l011xx.h"
+#elif defined(STM32L021xx)
+ #include "stm32l021xx.h"
+#elif defined(STM32L031xx)
#include "stm32l031xx.h"
#elif defined(STM32L041xx)
#include "stm32l041xx.h"
@@ -205,6 +216,7 @@
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/stm32l0xx_hal_conf.h Sun Apr 17 17:45:10 2016 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/stm32l0xx_hal_conf.h Tue Apr 19 11:15:15 2016 +0100 @@ -1,16 +1,16 @@ /** ****************************************************************************** - * @file stm32l0xx_hal_conf_template.h + * @file stm32l0xx_hal_conf.h * @author MCD Application Team - * @version V1.2.0 - * @date 06-February-2015 + * @version V1.5.0 + * @date 8-January-2016 * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32l0xx_hal_conf.h. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -114,6 +114,23 @@ #endif /* HSI_VALUE */ /** + * @brief Internal High Speed oscillator for USB (HSI48) value. + */ +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)37000) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,20 +2,20 @@
******************************************************************************
* @file system_stm32l0xx.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
*
- * This file provides two functions and one global variable to be called from
+ * This file provides two functions and one global variable to be called from
* user application:
- * - SystemInit(): This function is called at startup just after reset and
+ * - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32l0xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
+ * by the user application to setup the SysTick
* timer or configure other parameters.
- *
+ *
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
@@ -36,11 +36,11 @@
* APB2CLK (MHz) | 32 | 32
*-----------------------------------------------------------------------------
* USB capable (48 MHz precise clock) | YES | YES
- *-----------------------------------------------------------------------------
+ *-----------------------------------------------------------------------------
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -73,8 +73,8 @@
/** @addtogroup stm32l0xx_system
* @{
- */
-
+ */
+
/** @addtogroup STM32L0xx_System_Private_Includes
* @{
*/
@@ -82,14 +82,14 @@
#include "stm32l0xx.h"
#include "hal_tick.h"
-#if !defined (HSE_VALUE)
+#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
-
+
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
@@ -115,7 +115,7 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
@@ -140,14 +140,14 @@
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 32000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t PLLMulTable_2[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
/**
* @}
@@ -177,19 +177,19 @@
* @retval None
*/
void SystemInit (void)
-{
+{
/*!< Set MSION bit */
RCC->CR |= (uint32_t)0x00000100;
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
RCC->CFGR &= (uint32_t) 0x88FF400C;
-
+
/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFF6;
-
+
/*!< Reset HSI48ON bit */
RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
-
+
/*!< Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
@@ -198,7 +198,7 @@
/*!< Disable all interrupts */
RCC->CIER = 0x00000000;
-
+
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
@@ -224,34 +224,34 @@
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
- *
+ *
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
- *
- * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
* value as defined by the MSI range.
- *
+ *
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
+ *
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
+ *
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
+ *
* (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
* 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
+ * in voltage and temperature.
+ *
* (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
- *
+ *
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
@@ -263,7 +263,7 @@
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
-
+
switch (tmp)
{
case 0x00: /* MSI used as system clock */
@@ -280,9 +280,9 @@
/* Get PLL clock source and multiplication factor ----------------------*/
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
- pllmul = PLLMulTable_2[(pllmul >> 18)];
+ pllmul = PLLMulTable[(pllmul >> 18)];
plldiv = (plldiv >> 22) + 1;
-
+
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
if (pllsource == 0x00)
@@ -311,8 +311,8 @@
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
- * @note This function should be called only once the RCC clock configuration
- * is reset to the default reset state (done in SystemInit() function).
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
@@ -338,7 +338,7 @@
}
}
}
-
+
/* Output clock on MCO1 pin(PA8) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
@@ -358,13 +358,13 @@
{
return 0;
}
-
- /* The voltage scaling allows optimizing the power consumption when the device is
- clocked below the maximum system frequency, to update the voltage scaling value
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
+
/* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
if (bypass == 0)
@@ -376,7 +376,10 @@
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
}
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
+ !defined (STM32L011xx) && !defined (STM32L021xx)
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
+#endif
// PLLCLK = (8 MHz * 8)/2 = 32 MHz
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
@@ -386,7 +389,7 @@
{
return 0; // FAIL
}
-
+
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
@@ -403,7 +406,7 @@
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
//else
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-
+
return 1; // OK
}
#endif
@@ -416,17 +419,20 @@
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
- /* The voltage scaling allows optimizing the power consumption when the device is
- clocked below the maximum system frequency, to update the voltage scaling value
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
+
/* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
+ !defined (STM32L011xx) && !defined (STM32L021xx)
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
+#endif
// PLLCLK = (16 MHz * 4)/2 = 32 MHz
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
@@ -436,7 +442,7 @@
{
return 0; // FAIL
}
-
+
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
@@ -450,7 +456,7 @@
/* Output clock on MCO1 pin(PA8) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-
+
return 1; // OK
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -41,8 +41,8 @@
/** @addtogroup stm32l0xx_system
* @{
- */
-
+ */
+
/**
* @brief Define to prevent recursive inclusion
*/
@@ -51,7 +51,7 @@
#ifdef __cplusplus
extern "C" {
-#endif
+#endif
/** @addtogroup STM32L0xx_System_Includes
* @{
@@ -68,7 +68,7 @@
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
@@ -98,7 +98,7 @@
/** @addtogroup STM32L0xx_System_Exported_Functions
* @{
*/
-
+
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void);
@@ -116,8 +116,8 @@
/**
* @}
*/
-
+
/**
* @}
- */
+ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32_hal_legacy.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32_hal_legacy.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
- * @version V1.2.0RC4
- * @date 23-January-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -30,7 +30,7 @@
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- UART * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
@@ -51,8 +51,8 @@
/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
* @{
*/
-#define AES_FLAG_RDERR CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR CRYP_FLAG_WRERR
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
@@ -90,6 +90,8 @@
#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
@@ -100,7 +102,16 @@
#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
/**
* @}
*/
@@ -119,11 +130,28 @@
* @{
*/
-#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
/**
* @}
*/
@@ -146,7 +174,7 @@
#define DAC1_CHANNEL_1 DAC_CHANNEL_1
#define DAC1_CHANNEL_2 DAC_CHANNEL_2
#define DAC2_CHANNEL_1 DAC_CHANNEL_1
-#define DAC_WAVE_NONE ((uint32_t)0x00000000)
+#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
@@ -157,6 +185,34 @@
* @}
*/
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+
+
+/**
+ * @}
+ */
/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
* @{
@@ -204,7 +260,6 @@
#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
-#define IS_NBSECTORS IS_FLASH_NBSECTORS
#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
@@ -224,7 +279,16 @@
#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
-
+#define OB_WDG_SW OB_IWDG_SW
+#define OB_WDG_HW OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
/**
* @}
*/
@@ -233,19 +297,38 @@
* @{
*/
-#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
-#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
-#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
-#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
-#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
-#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
-#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
-
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
/**
* @}
*/
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+ * @{
+ */
+#if defined(STM32L4) || defined(STM32F7)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
+#else
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+ * @}
+ */
+
/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
* @{
*/
@@ -261,10 +344,74 @@
*/
#define GET_GPIO_SOURCE GPIO_GET_INDEX
#define GET_GPIO_INDEX GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
+
+#if defined(STM32L1)
+ #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
/**
* @}
*/
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
+/**
+ * @}
+ */
/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
* @{
@@ -277,6 +424,14 @@
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0)
+#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#endif
/**
* @}
*/
@@ -314,6 +469,18 @@
#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
/**
* @}
*/
@@ -323,6 +490,11 @@
*/
#define NAND_AddressTypedef NAND_AddressTypeDef
+#define __ARRAY_ADDRESS ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
/**
* @}
*/
@@ -336,6 +508,8 @@
#define NOR_ERROR HAL_NOR_STATUS_ERROR
#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
+#define __NOR_WRITE NOR_WRITE
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
/**
* @}
*/
@@ -424,14 +598,27 @@
#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
/**
* @}
@@ -470,6 +657,8 @@
#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
/**
* @}
@@ -523,6 +712,7 @@
#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
#define TIM_DMABase_OR2 TIM_DMABASE_OR2
#define TIM_DMABase_OR3 TIM_DMABASE_OR3
+#define TIM_DMABase_OR TIM_DMABASE_OR
#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
@@ -557,6 +747,15 @@
* @}
*/
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
+/**
+ * @}
+ */
+
/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
* @{
*/
@@ -618,9 +817,9 @@
#define CAN_IT_RQCP2 CAN_IT_TME
#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
-#define CAN_TXSTATUS_OK ((uint8_t)0x01)
-#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
/**
* @}
@@ -639,17 +838,17 @@
#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
-#define ETH_MMCCR ((uint32_t)0x00000100)
-#define ETH_MMCRIR ((uint32_t)0x00000104)
-#define ETH_MMCTIR ((uint32_t)0x00000108)
-#define ETH_MMCRIMR ((uint32_t)0x0000010C)
-#define ETH_MMCTIMR ((uint32_t)0x00000110)
-#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
-#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
-#define ETH_MMCTGFCR ((uint32_t)0x00000168)
-#define ETH_MMCRFCECR ((uint32_t)0x00000194)
-#define ETH_MMCRFAECR ((uint32_t)0x00000198)
-#define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
+#define ETH_MMCCR ((uint32_t)0x00000100U)
+#define ETH_MMCRIR ((uint32_t)0x00000104U)
+#define ETH_MMCTIR ((uint32_t)0x00000108U)
+#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
+#define ETH_MMCTIMR ((uint32_t)0x00000110U)
+#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
+#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
+#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
+#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
+#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
+#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
/**
* @}
@@ -676,7 +875,8 @@
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
* @{
*/
-
+#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
@@ -827,6 +1027,14 @@
/**
* @}
*/
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+/**
+ * @}
+ */
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
@@ -1042,23 +1250,166 @@
/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
* @{
*/
-
+#if defined(STM32F3)
+#define COMP_START __HAL_COMP_ENABLE
+#define COMP_STOP __HAL_COMP_DISABLE
+#define COMP_LOCK __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
__HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
__HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
__HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
/**
@@ -1085,6 +1436,8 @@
#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
#define IS_TYPEERASE IS_FLASH_TYPEERASE
+#define IS_NBSECTORS IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
/**
* @}
@@ -1208,7 +1561,7 @@
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@@ -1217,8 +1570,8 @@
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
-#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
@@ -1314,6 +1667,10 @@
#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
@@ -1344,6 +1701,10 @@
#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
@@ -1694,6 +2055,26 @@
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
@@ -1837,64 +2218,329 @@
#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
-#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET __HAL_RCC_OTGHS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET __HAL_RCC_OTGHS_RELEASE_RESET
-#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
-#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
-#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
-#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
-#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
-#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
/* alias define maintained for legacy */
#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
-#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14 RCC_IT_HSI14RDY
+
+#if defined(STM32L0)
+#define RCC_IT_LSECSS RCC_IT_CSSLSE
+#define RCC_IT_CSS RCC_IT_CSSHSE
+#endif
-#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV IS_RCC_PCLK
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV RCC_MCODIV_1
+#define RCC_MCO_DIV1 RCC_MCODIV_1
+#define RCC_MCO_DIV2 RCC_MCODIV_2
+#define RCC_MCO_DIV4 RCC_MCODIV_4
+#define RCC_MCO_DIV8 RCC_MCODIV_8
+#define RCC_MCO_DIV16 RCC_MCODIV_16
+#define RCC_MCO_DIV32 RCC_MCODIV_32
+#define RCC_MCO_DIV64 RCC_MCODIV_64
+#define RCC_MCO_DIV128 RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#define RCC_MCO_NODIV RCC_MCODIV_1
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+
+#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
#define HSION_BitNumber RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
#define LSION_BitNumber RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
-
+#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
@@ -1915,9 +2561,18 @@
#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB RCC_CR_HSEON_BB
+#define CSR_RMVF_BB RCC_CSR_RMVF_BB
#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
/**
* @}
*/
@@ -1938,24 +2593,8 @@
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
-#if defined (RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
-((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
- ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
- ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
- ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
- ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#else
+#if defined (STM32F1)
#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
@@ -1965,8 +2604,23 @@
#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-
-#endif
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif /* STM32F1 */
#define IS_ALARM IS_RTC_ALARM
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
@@ -1996,7 +2650,58 @@
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-
+
+#if defined(STM32F4)
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define SDMMC1_IRQn SDIO_IRQn
+#define SDMMC1_IRQHandler SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define SDIO_IRQn SDMMC1_IRQn
+#define SDIO_IRQHandler SDMMC1_IRQHandler
+#endif
/**
* @}
*/
@@ -2142,6 +2847,8 @@
#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+
#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
@@ -2154,32 +2861,6 @@
#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
-
-#define TIM_TS_ITR0 ((uint32_t)0x0000)
-#define TIM_TS_ITR1 ((uint32_t)0x0010)
-#define TIM_TS_ITR2 ((uint32_t)0x0020)
-#define TIM_TS_ITR3 ((uint32_t)0x0030)
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3))
-
-#define TIM_CHANNEL_1 ((uint32_t)0x0000)
-#define TIM_CHANNEL_2 ((uint32_t)0x0004)
-#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
-
-#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
-#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
-
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
- ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
-
-#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
-#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
-
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
- ((STATE) == TIM_OUTPUTSTATE_ENABLE))
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@@ -23,7 +23,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -57,33 +57,26 @@
* @{
*/
-/** @addgroup HAL
+#ifdef HAL_MODULE_ENABLED
+
+/** @addtogroup HAL
* @brief HAL module driver.
* @{
*/
-#ifdef HAL_MODULE_ENABLED
-
/** @addtogroup HAL_Exported_Constants
- *
* @{
*/
/** @defgroup HAL_Version HAL Version
* @{
*/
-#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000)
-#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_CFGR1_MEM_MODE_0)
-#define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_CFGR1_BOOT_MODE)
-
-
-#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
/**
- * @brief STM32L0xx HAL Driver version number V1.2.0
- */
+ * @brief STM32L0xx HAL Driver version number V1.5.0
+ */
#define __STM32L0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32L0xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32L0xx_HAL_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
#define __STM32L0xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_HAL_VERSION ((__STM32L0xx_HAL_VERSION_MAIN << 24)\
@@ -100,7 +93,7 @@
/**
* @}
*/
-/** @defgroup HAL_Private_Data
+/** @defgroup HAL_Private HAL Private
* @{
*/
static __IO uint32_t uwTick;
@@ -113,7 +106,7 @@
* @{
*/
-/** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+/** @addtogroup HAL_Exported_Functions_Group1
* @brief Initialization and de-initialization functions
*
@verbatim
@@ -156,7 +149,6 @@
* Once done, time base tick start incrementing.
* In the default implementation,Systick is used as source of time base.
* the tick variable is incremented each 1ms in its ISR.
- * @param None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
@@ -189,7 +181,6 @@
* @brief This function de-Initializes common part of the HAL and stops the source
* of time base.
* @note This function is optional.
- * @param None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DeInit(void)
@@ -216,7 +207,6 @@
/**
* @brief Initializes the MSP.
- * @param None
* @retval None
*/
__weak void HAL_MspInit(void)
@@ -228,7 +218,6 @@
/**
* @brief DeInitializes the MSP.
- * @param None
* @retval None
*/
__weak void HAL_MspDeInit(void)
@@ -286,8 +275,8 @@
(+) Get the HAL API driver version
(+) Get the device identifier
(+) Get the device revision identifier
- (+) Configures low power mode behavior when the MCU is in Debug mode
- (+) Manages the VEREFINT feature (activation, lock, output selection)
+ (+) Configure low power mode behavior when the MCU is in Debug mode
+ (+) Manage the VEREFINT feature (activation, lock, output selection)
@endverbatim
* @{
@@ -300,7 +289,6 @@
* in Systick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
- * @param None
* @retval None
*/
__weak void HAL_IncTick(void)
@@ -312,7 +300,6 @@
* @brief Provides a tick value in millisecond.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
- * @param None
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
@@ -340,14 +327,13 @@
}
/**
- * @brief Suspend Tick increment.
+ * @brief Suspends the Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
* is called, the the SysTick interrupt will be disabled and so Tick increment
* is suspended.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
- * @param None
* @retval None
*/
__weak void HAL_SuspendTick(void)
@@ -357,14 +343,13 @@
}
/**
- * @brief Resume Tick increment.
+ * @brief Resumes the Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
* is called, the the SysTick interrupt will be enabled and so Tick increment
* is resumed.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
- * @param None
* @retval None
*/
__weak void HAL_ResumeTick(void)
@@ -375,7 +360,6 @@
/**
* @brief Returns the HAL revision
- * @param None
* @retval version: 0xXYZR (8bits for each decimal, R for RC)
*/
uint32_t HAL_GetHalVersion(void)
@@ -385,7 +369,6 @@
/**
* @brief Returns the device revision identifier.
- * @param None
* @retval Device revision identifier
*/
uint32_t HAL_GetREVID(void)
@@ -395,7 +378,6 @@
/**
* @brief Returns the device identifier.
- * @param None
* @retval Device identifier
*/
uint32_t HAL_GetDEVID(void)
@@ -404,8 +386,7 @@
}
/**
- * @brief Enable the Debug Module during SLEEP mode
- * @param None
+ * @brief Enables the Debug Module during SLEEP mode
* @retval None
*/
void HAL_DBGMCU_EnableDBGSleepMode(void)
@@ -414,8 +395,7 @@
}
/**
- * @brief Disable the Debug Module during SLEEP mode
- * @param None
+ * @brief Disables the Debug Module during SLEEP mode
* @retval None
*/
void HAL_DBGMCU_DisableDBGSleepMode(void)
@@ -424,8 +404,7 @@
}
/**
- * @brief Enable the Debug Module during STOP mode
- * @param None
+ * @brief Enables the Debug Module during STOP mode
* @retval None
*/
void HAL_DBGMCU_EnableDBGStopMode(void)
@@ -434,8 +413,7 @@
}
/**
- * @brief Disable the Debug Module during STOP mode
- * @param None
+ * @brief Disables the Debug Module during STOP mode
* @retval None
*/
void HAL_DBGMCU_DisableDBGStopMode(void)
@@ -444,8 +422,7 @@
}
/**
- * @brief Enable the Debug Module during STANDBY mode
- * @param None
+ * @brief Enables the Debug Module during STANDBY mode
* @retval None
*/
void HAL_DBGMCU_EnableDBGStandbyMode(void)
@@ -454,8 +431,7 @@
}
/**
- * @brief Disable the Debug Module during STANDBY mode
- * @param None
+ * @brief Disables the Debug Module during STANDBY mode
* @retval None
*/
void HAL_DBGMCU_DisableDBGStandbyMode(void)
@@ -500,12 +476,11 @@
/**
* @brief Returns the boot mode as configured by user.
- * @param None.
* @retval The boot mode as configured by user. The returned value can be one
* of the following values:
- * - 0x00000000: Boot is configured in Main Flash memory
- * - 0x00000100: Boot is configured in System Flash memory
- * - 0x00000300: Boot is configured in Embedded SRAM memory
+ * - 0x00000000 : Boot is configured in Main Flash memory
+ * - 0x00000100 : Boot is configured in System Flash memory
+ * - 0x00000300 : Boot is configured in Embedded SRAM memory
*/
uint32_t HAL_SYSCFG_GetBootMode(void)
{
@@ -514,7 +489,6 @@
/**
* @brief Enables the VREFINT.
- * @param None
* @retval None
*/
void HAL_SYSCFG_EnableVREFINT(void)
@@ -525,7 +499,6 @@
/**
* @brief Disables the VREFINT.
- * @param None.
* @retval None
*/
void HAL_SYSCFG_DisableVREFINT(void)
@@ -537,10 +510,6 @@
* @brief Selects the output of internal reference voltage (VREFINT).
* The VREFINT output can be routed to(PB0) or
* (PB1) or both.
- * @note Kept for backward compatibility
- * We recommend to use the MACRO
- * __HAL_SYSCFG_VREFINT_OUTPUT_SELECT(__VREFINT_OUTPUT__)
- * rather than this function
* @param SYSCFG_Vrefint_OUTPUT: new state of the Vrefint output.
* This parameter can be one of the following values:
* @arg SYSCFG_VREFINT_OUT_NONE
@@ -587,11 +556,10 @@
* @}
*/
-#endif /* HAL_MODULE_ENABLED */
/**
* @}
*/
-
+#endif /* HAL_MODULE_ENABLED */
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32l0xx_hal.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,7 +54,7 @@
/** @defgroup HAL HAL
* @{
*/
-/** @defgroup HAL_Exported_Constants HAL Exported constants
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
@@ -62,14 +62,14 @@
* @{
*/
#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000)
-#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_CFGR1_MEM_MODE_0)
+#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_CFGR1_BOOT_MODE_0)
#define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_CFGR1_BOOT_MODE)
/**
* @}
*/
-/** @defgroup DBGMCU_Low_Power_Config
+/** @defgroup DBGMCU_Low_Power_Config DBGMCU Low Power Configuration
* @{
*/
#define DBGMCU_SLEEP DBGMCU_CR_DBG_SLEEP
@@ -82,7 +82,8 @@
* @}
*/
-/** @defgroup HAL_SYSCFG_LCD_EXT_CAPA
+#if defined (LCD_BASE) /* STM32L0x3xx only */
+/** @defgroup SYSCFG_LCD_EXT_CAPA SYSCFG LCD External Capacitors
* @{
*/
#define SYSCFG_LCD_EXT_CAPA SYSCFG_CFGR2_CAPA /*!< Connection of internal Vlcd rail to external capacitors */
@@ -99,8 +100,9 @@
/**
* @}
*/
+#endif
-/** @defgroup HAL_SYSCFG_VREFINT_OUT_SELECT
+/** @defgroup SYSCFG_VREFINT_OUT_SELECT SYSCFG VREFINT Out Selection
* @{
*/
#define SYSCFG_VREFINT_OUT_NONE ((uint32_t)0x00000000) /* no pad connected */
@@ -116,7 +118,7 @@
* @}
*/
-/** @defgroup HAL_SYSCFG_flags_definition
+/** @defgroup SYSCFG_flags_definition SYSCFG Flags Definition
* @{
*/
#define SYSCFG_FLAG_VREFINT_READY SYSCFG_CFGR3_VREFINT_RDYF
@@ -126,6 +128,32 @@
/**
* @}
*/
+
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast Mode Plus on GPIO
+ * @{
+ */
+/** @brief Fast mode Plus driving capability on a specific GPIO
+ */
+#if defined (SYSCFG_CFGR2_I2C_PB6_FMP)
+#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /* Enable Fast Mode Plus on PB6 */
+#endif
+#if defined (SYSCFG_CFGR2_I2C_PB7_FMP)
+#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP /* Enable Fast Mode Plus on PB7 */
+#endif
+#if defined (SYSCFG_CFGR2_I2C_PB8_FMP)
+#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /* Enable Fast Mode Plus on PB8 */
+#endif
+#if defined (SYSCFG_CFGR2_I2C_PB9_FMP)
+#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /* Enable Fast Mode Plus on PB9 */
+#endif
+
+#define IS_SYSCFG_FASTMODEPLUS(PIN) ((((PIN) & (SYSCFG_FASTMODEPLUS_PB6)) == SYSCFG_FASTMODEPLUS_PB6) || \
+ (((PIN) & (SYSCFG_FASTMODEPLUS_PB7)) == SYSCFG_FASTMODEPLUS_PB7) || \
+ (((PIN) & (SYSCFG_FASTMODEPLUS_PB8)) == SYSCFG_FASTMODEPLUS_PB8) || \
+ (((PIN) & (SYSCFG_FASTMODEPLUS_PB9)) == SYSCFG_FASTMODEPLUS_PB9) )
+/**
+ * @}
+ */
/**
* @}
*/
@@ -255,25 +283,53 @@
/** @brief Configuration of the DBG Low Power mode.
* @param __DBGLPMODE__: bit field to indicate in wich Low Power mode DBG is still active.
- * This parameter can be a value of @ref HAL_DBGMCU_Low_Power_Config
+ * This parameter can be a value of
+ * - DBGMCU_SLEEP
+ * - DBGMCU_STOP
+ * - DBGMCU_STANDBY
*/
#define __HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__) do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); \
MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); \
} while (0)
/**
* @brief Returns the boot mode as configured by user.
- * @retval The boot mode as configured by user. The returned can be a value of @ref HAL_SYSCFG_BootMode
+ * @retval The boot mode as configured by user. The returned can be a value of :
+ * - SYSCFG_BOOT_MAINFLASH
+ * - SYSCFG_BOOT_SYSTEMFLASH
+ * - SYSCFG_BOOT_SRAM
*/
#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE)
/** @brief Check whether the specified SYSCFG flag is set or not.
* @param __FLAG__: specifies the flag to check.
- * This parameter can a value of @ref HAL_SYSCFG_flags_definition
+ * The only parameter supported is SYSCFG_FLAG_VREFINT_READY
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SYSCFG_GET_FLAG(__FLAG__) (((SYSCFG->CFGR3) & (__FLAG__)) == (__FLAG__))
+/** @brief Fast mode Plus driving capability enable macro
+ * @param __FASTMODEPLUS__: This parameter can be a value of :
+ * @arg SYSCFG_FASTMODEPLUS_PB6
+ * @arg SYSCFG_FASTMODEPLUS_PB7
+ * @arg SYSCFG_FASTMODEPLUS_PB8
+ * @arg SYSCFG_FASTMODEPLUS_PB9
+ */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
+ SET_BIT(SYSCFG->CFGR2, __FASTMODEPLUS__); \
+ }while(0)
+/** @brief Fast mode Plus driving capability disable macro
+ * @param __FASTMODEPLUS__: This parameter can be a value of :
+ * @arg SYSCFG_FASTMODEPLUS_PB6
+ * @arg SYSCFG_FASTMODEPLUS_PB7
+ * @arg SYSCFG_FASTMODEPLUS_PB8
+ * @arg SYSCFG_FASTMODEPLUS_PB9
+ */
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
+ CLEAR_BIT(SYSCFG->CFGR2, __FASTMODEPLUS__); \
+ }while(0)
+
+
/**
* @}
*/
@@ -329,6 +385,17 @@
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup HAL_Private HAL Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_adc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
@@ -11,101 +11,228 @@
* ++ Initialization and Configuration of ADC
* + Operation functions
* ++ Start, stop, get result of conversions of regular
- * groups, using 3 possible modes : polling, interruption or DMA.
- * ++ Calibration feature
+ * group, using 3 possible modes : polling, interruption or DMA.
* + Control functions
+ * ++ Channels configuration on regular group
* ++ Analog Watchdog configuration
- * ++ Regular Channels Configuration
* + State functions
* ++ ADC state machine management
* ++ Interrupts and flags management
+ * Other functions (extended functions) are available in file
+ * "stm32l0xx_hal_adc_ex.c".
*
@verbatim
==============================================================================
- ##### ADC specific features #####
+ ##### ADC peripheral features #####
==============================================================================
[..]
- (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
-
- (#) A built-in hardware oversampler allows to improve analog performances
- while off-loading the related computational burden from the CPU.
+ (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
- (#) Interrupt generation at the end of conversion and in case of analog
- watchdog or overrun events.
-
- (#) Single and continuous conversion modes.
-
- (#) Scan or discontinuous mode conversion of channel 0 to channel 18.
+ (+) A built-in hardware oversampler can handle multiple conversions and average
+ them into a single data with increased data width, up to 16-bit.
+
+ (+) Interrupt generation at the end of regular conversion and in case of
+ analog watchdog or overrun events.
- (#) Configurable scan direction (Upward from channel 0 to 18 or Backward from
- channel 18 to channel 0)
+ (+) Single and continuous conversion modes.
+
+ (+) Scan mode for conversion of several channels sequentially.
- (#) Data alignment with in-built data coherency.
+ (+) Data alignment with in-built data coherency.
+
+ (+) Programmable sampling time (common for all channels)
- (#) Channel-wise programmable sampling time.
-
- (#) External trigger option with configurable polarity.
+ (+) ADC conversion of regular group.
+
+ (+) External trigger (timer or EXTI) with configurable polarity
- (#) DMA request generation during regular channel conversion.
-
- (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
+ (+) DMA request generation for transfer of conversions data of regular group.
+
+ (+) ADC calibration
+
+ (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
slower speed.
- (#) ADC input range: VREF- =VIN =VREF+.
-
- (#) ADC self-calibration.
-
- (#) ADC is automatically powered off (AutoOff mode) except during the active
- conversion phase. This dramatically reduces the power consumption of the
- ADC.
-
- (#) Wait mode to prevent ADC overrun in applications with low frequency.
+ (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
+ Vdda or to an external voltage reference).
##### How to use this driver #####
==============================================================================
[..]
+ *** Configuration of top level parameters related to ADC ***
+ ============================================================
+ [..]
+
(#) Enable the ADC interface
- As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured
- at RCC top level.
+ (++) As prerequisite, ADC clock must be configured at RCC top level.
+ Caution: On STM32L0, ADC clock frequency max is 16MHz (refer
+ to device datasheet).
+ Therefore, ADC clock prescaler must be configured in
+ function of ADC clock source frequency to remain below
+ this maximum frequency.
+
+ (++) Two clock settings are mandatory:
+ (+++) ADC clock (core clock, also possibly conversion clock).
- Depending on both possible clock sources: PCLK clock or ADC asynchronous
- clock.
- __HAL_RCC_ADC1_CLK_ENABLE();
+ (+++) ADC clock (conversions clock).
+ Two possible clock sources: synchronous clock derived from APB clock
+ or asynchronous clock derived from ADC dedicated HSI RC oscillator
+ 16MHz.
+ If asynchronous clock is selected, parameter "HSIState" must be set either:
+ - to "...HSIState = RCC_HSI_ON" to maintain the HSI16 oscillator
+ always enabled: can be used to supply the main system clock.
+ (+++) Example:
+ Into HAL_ADC_MspInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) __HAL_RCC_ADC1_CLK_ENABLE(); (mandatory)
+
+ HSI16 enable : (optional: if asynchronous clock selected)
+ (+++) RCC_OscInitTypeDef RCC_OscInitStructure;
+ (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ (+++) RCC_OscInitStructure.HSI16CalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ (+++) RCC_OscInitStructure.HSIState = RCC_HSI_ON;
+ (+++) RCC_OscInitStructure.PLL... (optional if used for system clock)
+ (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+ (++) ADC clock source and clock prescaler are configured at ADC level with
+ parameter "ClockPrescaler" using function HAL_ADC_Init().
(#) ADC pins configuration
- (++) Enable the clock for the ADC GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE();
- (++) Configure these ADC pins in analog mode using HAL_GPIO_Init();
-
- (#) Configure the ADC parameters (conversion resolution, oversampler,
- data alignment, continuous mode,...) using the HAL_ADC_Init() function.
+ (++) Enable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+ (++) Configure these ADC pins in analog mode
+ using function HAL_GPIO_Init()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Configure the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding ADC interruption vector
+ ADCx_IRQHandler().
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+ using function HAL_DMA_Init().
+ (++) Configure the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding DMA interruption vector
+ DMAx_Channelx_IRQHandler().
+
+ *** Configuration of ADC, group regular, channels parameters ***
+ ================================================================
+ [..]
+
+ (#) Configure the ADC parameters (resolution, data alignment, oversampler, continuous mode, ...)
+ and regular group parameters (conversion trigger, sequencer, ...)
+ using function HAL_ADC_Init().
+
+ (#) Configure the channels for regular group parameters (channel number,
+ channel rank into sequencer, ..., into regular group)
+ using function HAL_ADC_ConfigChannel().
+
+ (#) Optionally, configure the analog watchdog parameters (channels
+ monitored, thresholds, ...)
+ using function HAL_ADC_AnalogWDGConfig().
+
+
+ (#) When device is in mode low-power (low-power run, low-power sleep or stop mode),
+ function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init().
+ In case of internal temperature sensor to be measured:
+ function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly
- (#) Activate the ADC peripheral using one of the start functions:
- HAL_ADC_Start(), HAL_ADC_Start_IT() or HAL_ADC_Start_DMA()
+ *** Execution of ADC conversions ***
+ ====================================
+ [..]
+
+ (#) Optionally, perform an automatic ADC calibration to improve the
+ conversion accuracy
+ using function HAL_ADCEx_Calibration_Start().
+
+ (#) ADC driver can be used among three modes: polling, interruption,
+ transfer by DMA.
+
+ (++) ADC conversion by polling:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start()
+ (+++) Wait for ADC conversion completion
+ using function HAL_ADC_PollForConversion()
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop()
+
+ (++) ADC conversion by interruption:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_IT()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback()
+ (this function must be implemented in user program)
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_IT()
+
+ (++) ADC conversion with transfer by DMA:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_DMA()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+ (these functions must be implemented in user program)
+ (+++) Conversion results are automatically transferred by DMA into
+ destination variable address.
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_DMA()
- *** Channels configuration ***
- ===============================
[..]
- (+) To configure the ADC channels group, use HAL_ADC_ConfigChannel() function.
- (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
- *** DMA feature configuration ***
- =================================
+ (@) Callback functions must be implemented in user program:
+ (+@) HAL_ADC_ErrorCallback()
+ (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+ (+@) HAL_ADC_ConvCpltCallback()
+ (+@) HAL_ADC_ConvHalfCpltCallback
+
+ *** Deinitialization of ADC ***
+ ============================================================
[..]
- (+) To enable the DMA mode, use the HAL_ADC_Start_DMA() function.
- (+) To enable the generation of DMA requests continuously at the end of
- the last DMA transfer, set .Init.DMAContinuousRequests to ENABLE and
- call HAL_ADC_Init() function.
+
+ (#) Disable the ADC interface
+ (++) ADC clock can be hard reset and disabled at RCC top level.
+ (++) Hard reset of ADC peripherals
+ using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
+ (++) ADC clock disable
+ using the equivalent macro/functions as configuration step.
+ (+++) Example:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
+ (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+ (#) ADC pins configuration
+ (++) Disable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Disable the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Deinitialize the DMA
+ using function HAL_DMA_Init().
+ (++) Disable the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+ [..]
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -139,12 +266,16 @@
* @{
*/
+#ifdef HAL_ADC_MODULE_ENABLED
+
/** @addtogroup ADC
* @brief ADC driver modules
* @{
*/
-#ifdef HAL_ADC_MODULE_ENABLED
+/** @addtogroup ADC_Private
+ * @{
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -158,25 +289,32 @@
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
/* Unit: us */
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup ADC_Private
+ * @{
+ */
static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
+static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
+static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc);
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
static void ADC_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
-static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
static void ADC_DelayMicroSecond(uint32_t microSecond);
+/**
+ * @}
+ */
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Functions
+/** @addtogroup ADC_Exported_Functions
* @{
*/
-/** @defgroup ADC_Group1 Initialization/de-initialization functions
+/** @addtogroup ADC_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
@@ -193,32 +331,40 @@
/**
- * @brief Initializes the ADCx peripheral according to the specified parameters
- * in the ADC_InitStruct.
- * @note This function is used to configure the global features of the ADC
- * (ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
- * the rest of the configuration parameters are specific to the regular
- * channels group (scan mode activation, continuous mode activation,
- * External trigger source and edge, DMA continuous request after the
- * last transfer and End of conversion selection).
- *
- * As prerequisite, into HAL_ADC_MspInit(), ADC clock must be
- * configured at RCC top level.
- * See commented example code below that can be copied
- * and uncommented into HAL_ADC_MspInit().
- *
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
+ * @brief Initializes the ADC peripheral and regular group according to
+ * parameters specified in structure "ADC_InitTypeDef".
+ * @note As prerequisite, ADC clock must be configured at RCC top level
+ * depending on both possible clock sources: APB clock of HSI clock.
+ * See commented example code below that can be copied and uncommented
+ * into HAL_ADC_MspInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+ * coming from ADC state reset. Following calls to this function can
+ * be used to reconfigure some parameters of ADC_InitTypeDef
+ * structure on the fly, without modifying MSP configuration. If ADC
+ * MSP has to be modified again, HAL_ADC_DeInit() must be called
+ * before HAL_ADC_Init().
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InitTypeDef".
+ * @note This function configures the ADC within 2 scopes: scope of entire
+ * ADC and scope of regular group. For parameters details, see comments
+ * of structure "ADC_InitTypeDef".
+ * @note When device is in mode low-power (low-power run, low-power sleep or stop mode),
+ * function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init()
+ * (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first).
+ * In case of internal temperature sensor to be measured:
+ * function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly.
+ * @param hadc: ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
- uint32_t tickstart = 0x00;
-
+
/* Check ADC handle */
if(hadc == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Check the parameters */
@@ -231,42 +377,79 @@
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
- assert_param(IS_ADC_EXTERNAL_TRIG_CONV(hadc->Init.ExternalTrigConv));
+ assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
- assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerFrequencyMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
+ /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
+ /* at RCC top level depending on both possible clock sources: */
+ /* APB clock or HSI clock. */
+ /* Refer to header of this file for more details on clock enabling procedure*/
+
+ /* Actions performed only if ADC is coming from state reset: */
+ /* - Initialization of ADC MSP */
+ /* - ADC voltage regulator enable */
if(hadc->State == HAL_ADC_STATE_RESET)
{
+ /* Initialize ADC error code */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Allocate lock resource and initialize it */
+ hadc->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
}
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
- /* and if there is no conversion on going (ADC can be enabled anyway, */
- /* in case of call of this function to update a parameter */
+ /* and if there is no conversion on going on regular group (ADC can be */
+ /* enabled anyway, in case of call of this function to update a parameter */
/* on the fly). */
- if ((hadc->State == HAL_ADC_STATE_ERROR) ||
- (ADC_IS_CONVERSION_ONGOING(hadc) != RESET) )
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) ||
+ (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET) )
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
/* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_ERROR;
}
- /* Initialize the ADC state */
- hadc->State = HAL_ADC_STATE_BUSY;
-
- /* Configuration of ADC clock: clock source PCLK or asynchronous with
- selectable prescaler */
- __HAL_ADC_CLOCK_PRESCALER(hadc);
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - ADC clock mode */
+ /* - ADC clock prescaler */
+ /* - ADC Resolution */
+ if (ADC_IS_ENABLE(hadc) == RESET)
+ {
+ /* Some parameters of this register are not reset, since they are set */
+ /* by other functions and must be kept in case of usage of this */
+ /* function on the fly (update of a parameter of ADC_InitTypeDef */
+ /* without needing to reconfigure all other ADC groups/channels */
+ /* parameters): */
+ /* - internal measurement paths: Vbat, temperature sensor, Vref */
+ /* (set into HAL_ADC_ConfigChannel() ) */
+
+ /* Configuration of ADC clock: clock source PCLK or asynchronous with
+ selectable prescaler */
+ __HAL_ADC_CLOCK_PRESCALER(hadc);
+
+ /* Configuration of ADC: */
+ /* - Resolution */
+ hadc->Instance->CFGR1 &= ~( ADC_CFGR1_RES);
+ hadc->Instance->CFGR1 |= hadc->Init.Resolution;
+ }
/* Set the Low Frequency mode */
ADC->CCR &= (uint32_t)~ADC_CCR_LFMEN;
@@ -275,47 +458,6 @@
/* Enable voltage regulator (if disabled at this step) */
if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
{
- /* Disable the ADC (if not already disabled) */
- if (ADC_IS_ENABLE(hadc) != RESET )
- {
- /* Check if conditions to disable the ADC are fulfilled */
- if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
- {
- __HAL_ADC_DISABLE(hadc);
- }
- else
- {
- hadc->State= HAL_ADC_STATE_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait for disabling completion */
- while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
- {
- /* Check for the Timeout */
- if(ADC_ENABLE_TIMEOUT != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT)
- {
- hadc->State= HAL_ADC_STATE_TIMEOUT;
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- }
-
/* Set ADVREGEN bit */
hadc->Instance->CR |= ADC_CR_ADVREGEN;
}
@@ -323,7 +465,7 @@
/* Configuration of ADC: */
/* - Resolution */
/* - Data alignment */
- /* - Scan direction */
+ /* - Scan direction */
/* - External trigger to start conversion */
/* - External trigger polarity */
/* - Continuous conversion mode */
@@ -331,8 +473,7 @@
/* - Overrun */
/* - AutoDelay feature */
/* - Discontinuous mode */
- hadc->Instance->CFGR1 &= ~( ADC_CFGR1_RES |
- ADC_CFGR1_ALIGN |
+ hadc->Instance->CFGR1 &= ~(ADC_CFGR1_ALIGN |
ADC_CFGR1_SCANDIR |
ADC_CFGR1_EXTSEL |
ADC_CFGR1_EXTEN |
@@ -343,27 +484,45 @@
ADC_CFGR1_AUTOFF |
ADC_CFGR1_DISCEN);
- hadc->Instance->CFGR1 |= ( hadc->Init.Resolution |
- hadc->Init.DataAlign |
+ hadc->Instance->CFGR1 |= (hadc->Init.DataAlign |
ADC_SCANDIR(hadc->Init.ScanConvMode) |
- hadc->Init.ExternalTrigConvEdge |
ADC_CONTINUOUS(hadc->Init.ContinuousConvMode) |
ADC_DMACONTREQ(hadc->Init.DMAContinuousRequests) |
- hadc->Init.Overrun |
- __HAL_ADC_CFGR1_AutoDelay(hadc->Init.LowPowerAutoWait) |
+ hadc->Init.Overrun |
+ __HAL_ADC_CFGR1_AutoDelay(hadc->Init.LowPowerAutoWait) |
__HAL_ADC_CFGR1_AUTOFF(hadc->Init.LowPowerAutoPowerOff));
- /* Configure the external trigger only if Conversion edge is not "NONE" */
- if (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIGCONVEDGE_NONE)
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
- hadc->Instance->CFGR1 |= hadc->Init.ExternalTrigConv;
+ hadc->Instance->CFGR1 |= hadc->Init.ExternalTrigConv |
+ hadc->Init.ExternalTrigConvEdge;
}
/* Enable discontinuous mode only if continuous mode is disabled */
- if ((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == DISABLE))
- {
- /* Enable the selected ADC discontinuous mode */
- hadc->Instance->CFGR1 |= ( ADC_CFGR1_DISCEN);
+ if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ {
+ if (hadc->Init.ContinuousConvMode == DISABLE)
+ {
+ /* Enable the selected ADC group regular discontinuous mode */
+ hadc->Instance->CFGR1 |= (ADC_CFGR1_DISCEN);
+ }
+ else
+ {
+ /* ADC regular group discontinuous was intended to be enabled, */
+ /* but ADC regular group modes continuous and sequencer discontinuous */
+ /* cannot be enabled simultaneously. */
+
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
}
if (hadc->Init.OversamplingMode == ENABLE)
@@ -390,8 +549,11 @@
}
else
{
- /* Disable OverSampling mode */
- hadc->Instance->CFGR2 &= ~ADC_CFGR2_OVSE;
+ if(HAL_IS_BIT_SET(hadc->Instance->CFGR2, ADC_CFGR2_OVSE))
+ {
+ /* Disable OverSampling mode if needed */
+ hadc->Instance->CFGR2 &= ~ADC_CFGR2_OVSE;
+ }
}
/* Clear the old sampling time */
@@ -400,30 +562,34 @@
/* Set the new sample time */
hadc->Instance->SMPR |= hadc->Init.SamplingTime;
-
- /* Set ADC error code to none */
- hadc->ErrorCode = HAL_ADC_ERROR_NONE;
-
- /* Initialize the ADC state */
- hadc->State = HAL_ADC_STATE_READY;
-
+ /* Clear ADC error code */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Deinitialize the ADC peripheral registers to its default reset values.
- * @note To not impact other ADCs, reset of common ADC registers have been
- * left commented below.
- * If needed, the example code can be copied and uncommented into
- * function HAL_ADC_MspDeInit().
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
+ * @brief Deinitialize the ADC peripheral registers to their default reset
+ * values, with deinitialization of the ADC MSP.
+ * @note For devices with several ADCs: reset of ADC common registers is done
+ * only if all ADCs sharing the same common group are disabled.
+ * If this is not the case, reset of these common parameters reset is
+ * bypassed without error reporting: it can be the intended behaviour in
+ * case of reset of a single ADC while the other ADCs sharing the same
+ * common group is still running.
+ * @param hadc: ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
{
- uint32_t tickstart = 0;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check ADC handle */
if(hadc == NULL)
@@ -434,112 +600,120 @@
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY;
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
- /* Stop potential conversion ongoing */
- if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS))
- {
- /* Stop regular conversion */
- hadc->Instance->CR |= ADC_CR_ADSTP;
- }
-
- /* Disable ADC: Solution to recover from an unknown ADC state (for example, */
- /* in case of forbidden action on register bits) */
- /* Procedure to disable the ADC peripheral: wait for conversions */
- /* effectively stopped, then disable ADC */
- /* 1. Wait until ADSTART = 0 */
-
- /* Get timeout */
- tickstart = HAL_GetTick();
+ /* Stop potential conversion on going, on regular group */
+ tmp_hal_status = ADC_ConversionStop(hadc);
- while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART))
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status != HAL_ERROR)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ }
+
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if (tmp_hal_status != HAL_ERROR)
{
- /* Check for the Timeout */
- if(ADC_STOP_CONVERSION_TIMEOUT != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > ADC_STOP_CONVERSION_TIMEOUT)
- {
- hadc->State= HAL_ADC_STATE_TIMEOUT;
+
+ /* ========== Reset ADC registers ========== */
+ /* Reset register IER */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD | ADC_IT_OVR | ADC_IT_EOCAL | ADC_IT_EOS | \
+ ADC_IT_EOC | ADC_IT_RDY | ADC_IT_EOSMP ));
+
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* 2. Disable the ADC peripheral */
- __HAL_ADC_DISABLE(hadc);
+ /* Reset register ISR */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_EOCAL | ADC_FLAG_OVR | ADC_FLAG_EOS | \
+ ADC_FLAG_EOC | ADC_FLAG_EOSMP | ADC_FLAG_RDY));
- /* Reset ADC registers****************/
- /* Reset register IER */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD | ADC_IT_OVR | ADC_IT_EOCAL | ADC_IT_EOS | \
- ADC_IT_EOC | ADC_IT_RDY | ADC_IT_EOSMP ));
-
- /* Reset register ISR */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_EOCAL | ADC_FLAG_OVR | ADC_FLAG_EOS | \
- ADC_FLAG_EOC | ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+ /* Reset register CR */
+ /* Disable voltage regulator */
+ /* Note: Regulator disable useful for power saving */
+ /* Reset ADVREGEN bit */
+ hadc->Instance->CR &= ~ADC_CR_ADVREGEN;
+
+ /* Bits ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode "read-set": no direct reset applicable */
+ /* No action */
+
+ /* Reset register CFGR1 */
+ hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | \
+ ADC_CFGR1_DISCEN | ADC_CFGR1_AUTOFF | ADC_CFGR1_AUTDLY | \
+ ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | ADC_CFGR1_EXTEN | \
+ ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | \
+ ADC_CFGR1_SCANDIR| ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN);
- /* Reset register CR */
- /* Disable voltage regulator */
- /* Note: Regulator disable useful for power saving */
- /* Reset ADVREGEN bit */
- hadc->Instance->CR &= ~ADC_CR_ADVREGEN;
+ /* Reset register CFGR2 */
+ hadc->Instance->CFGR2 &= ~(ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR | \
+ ADC_CFGR2_OVSE | ADC_CFGR2_CKMODE );
- /* Bits ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode "read-set": no direct reset applicable */
- /* No action */
+
+ /* Reset register SMPR */
+ hadc->Instance->SMPR &= ~(ADC_SMPR_SMPR);
+
+ /* Reset register TR */
+ hadc->Instance->TR &= ~(ADC_TR_LT | ADC_TR_HT);
+
+ /* Reset register CALFACT */
+ hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT);
+
+
+
- /* Reset register CFGR1 */
- hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | \
- ADC_CFGR1_DISCEN | ADC_CFGR1_AUTOFF | ADC_CFGR1_AUTDLY | \
- ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | ADC_CFGR1_EXTEN | \
- ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | \
- ADC_CFGR1_SCANDIR| ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN);
-
- /* Reset register CFGR2 */
- hadc->Instance->CFGR2 &= ~(ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR | \
- ADC_CFGR2_OVSE | ADC_CFGR2_CKMODE );
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register CALFACT */
+ hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT);
+
+ /* ========== Hard reset ADC peripheral ========== */
+ /* Performs a global reset of the entire ADC peripheral: ADC state is */
+ /* forced to a similar state after device power-on. */
+ /* If needed, copy-paste and uncomment the following reset code into */
+ /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
+ /* */
+ /* __HAL_RCC_ADC1_FORCE_RESET() */
+ /* __HAL_RCC_ADC1_RELEASE_RESET() */
- /* Reset register SMPR */
- hadc->Instance->SMPR &= ~(ADC_SMPR_SMPR);
-
- /* Reset register TR */
- hadc->Instance->TR &= ~(ADC_TR_LT | ADC_TR_HT);
+ /* DeInit the low level hardware */
+ HAL_ADC_MspDeInit(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set ADC state */
+ hadc->State = HAL_ADC_STATE_RESET;
+ }
- /* Reset register CALFACT */
- hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT);
-
- /* Reset register DR */
- /* bits in access mode read only, no direct reset applicable*/
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
- /* Reset register CALFACT */
- hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT);
+ /* Return function status */
+ return tmp_hal_status;
+}
- /* DeInit the low level hardware */
- HAL_ADC_MspDeInit(hadc);
-
- /* Set ADC error code to none */
- hadc->ErrorCode = HAL_ADC_ERROR_NONE;
-
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_RESET;
-
- /* Return function status */
- return HAL_OK;
-}
-
/**
* @brief Initializes the ADC MSP.
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
+ * @param hadc: ADC handle
* @retval None
*/
__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_MspInit could be implemented in the user file
*/
@@ -547,14 +721,16 @@
/**
* @brief DeInitializes the ADC MSP.
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
+ * @param hadc: ADC handle
* @retval None
*/
__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ADC_MspDeInit could be implemented in the user file
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspDeInit must be implemented in the user file.
*/
}
@@ -562,7 +738,7 @@
* @}
*/
-/** @defgroup ADC_Group2 I/O operation functions
+/** @addtogroup ADC_Exported_Functions_Group2
* @brief I/O operation functions
*
@verbatim
@@ -570,118 +746,126 @@
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) Start conversion.
- (+) Stop conversion.
- (+) poll for conversion complete.
+ (+) Start conversion of regular group.
+ (+) Stop conversion of regular group.
+ (+) Poll for conversion complete on regular group.
(+) poll for conversion event.
- (+) Start conversion and enable interrupt.
- (+) Stop conversion and disable interrupt.
- (+) handle ADC interrupt request.
- (+) Start conversion of regular channel and enable DMA transfer.
- (+) Stop conversion of regular channel and disable DMA transfer.
(+) Get result of regular channel conversion.
- (+) Handle ADC interrupt request.
-
+ (+) Start conversion of regular group and enable interruptions.
+ (+) Stop conversion of regular group and disable interruptions.
+ (+) Handle ADC interrupt request
+ (+) Start conversion of regular group and enable DMA transfer.
+ (+) Stop conversion of regular group and disable ADC DMA transfer.
@endverbatim
* @{
*/
/**
- * @brief Enables ADC and starts conversion of the regular channels.
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
+ * @brief Enables ADC, starts conversion of regular group.
+ * Interruptions enabled in this function: None.
+ * @param hadc: ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
- if (ADC_IS_CONVERSION_ONGOING(hadc) == RESET)
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
{
/* Process locked */
__HAL_LOCK(hadc);
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_REG;
-
- /* Set ADC error code to none */
- hadc->ErrorCode = HAL_ADC_ERROR_NONE;
-
/* Enable the ADC peripheral */
/* If low power mode AutoPowerOff is enabled, power-on/off phases are */
/* performed automatically by hardware. */
if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
{
- tmpHALStatus = ADC_Enable(hadc);
+ tmp_hal_status = ADC_Enable(hadc);
}
/* Start conversion if ADC is effectively enabled */
- if (tmpHALStatus != HAL_ERROR)
+ if (tmp_hal_status == HAL_OK)
{
- /* ADC start conversion command */
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
hadc->Instance->CR |= ADC_CR_ADSTART;
}
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
}
else
{
- tmpHALStatus = HAL_BUSY;
+ tmp_hal_status = HAL_BUSY;
}
/* Return function status */
- return tmpHALStatus;
+ return tmp_hal_status;
}
/**
- * @brief Stop ADC conversion of regular channels, disable ADC peripheral.
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
- * @retval None
+ * @brief Stop ADC conversion of regular group, disable ADC peripheral.
+ * @param hadc: ADC handle
+ * @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
- /* 1. Stop potential conversion ongoing (regular conversion) */
- tmpHALStatus = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+ /* 1. Stop potential conversion on going, on regular group */
+ tmp_hal_status = ADC_ConversionStop(hadc);
- /* 2. Disable ADC peripheral if conversions are effectively stopped */
- if (tmpHALStatus != HAL_ERROR)
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
{
- /* Disable the ADC peripheral */
- tmpHALStatus = ADC_Disable(hadc);
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
/* Check if ADC is effectively disabled */
- if ((hadc->State != HAL_ADC_STATE_ERROR) && (tmpHALStatus != HAL_ERROR))
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
- }
- else
+ if (tmp_hal_status == HAL_OK)
{
- return HAL_ERROR;
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
}
- }
- else
- {
- return HAL_ERROR;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
@@ -696,18 +880,20 @@
* parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
* In this case, DMA resets the flag EOC and polling cannot be
* performed on each conversion. Nevertheless, polling can still
- * be performed on the complete sequence.
+ * be performed on the complete sequence (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
* @param hadc: ADC handle
* @param Timeout: Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart;
uint32_t tmp_Flag_EOC;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
/* If end of conversion selected to end of sequence */
if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
@@ -726,7 +912,7 @@
if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN))
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
/* Process unlocked */
__HAL_UNLOCK(hadc);
@@ -739,7 +925,7 @@
}
}
- /* Get tick */
+ /* Get tick count */
tickstart = HAL_GetTick();
/* Wait until End of Conversion flag is raised */
@@ -751,7 +937,7 @@
if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Update ADC state machine to timeout */
- hadc->State = HAL_ADC_STATE_TIMEOUT;
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
/* Process unlocked */
__HAL_UNLOCK(hadc);
@@ -761,6 +947,43 @@
}
}
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+
/* Clear end of conversion flag of regular group if low power feature */
/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
/* until data register is read using function HAL_ADC_GetValue(). */
@@ -770,24 +993,17 @@
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
}
- /* Update state machine on conversion status if not in error state */
- if(hadc->State != HAL_ADC_STATE_ERROR)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC;
- }
-
/* Return ADC state */
return HAL_OK;
}
/**
* @brief Poll for conversion event.
- * @param hadc: ADC handle.
+ * @param hadc: ADC handle
* @param EventType: the ADC event type.
* This parameter can be one of the following values:
- * @arg ADC_AWD_EVENT: ADC Analog watchdog event.
- * @arg ADC_OVR_EVENT: ADC Overrun event.
+ * @arg ADC_AWD_EVENT: ADC Analog watchdog event
+ * @arg ADC_OVR_EVENT: ADC Overrun event
* @param Timeout: Timeout value in millisecond.
* @retval HAL status
*/
@@ -799,11 +1015,11 @@
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_EVENT_TYPE(EventType));
- /* Get timeout */
+ /* Get tick count */
tickstart = HAL_GetTick();
/* Check selected event flag */
- while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
+ while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
{
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
@@ -811,7 +1027,7 @@
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Update ADC state machine to timeout */
- hadc->State = HAL_ADC_STATE_TIMEOUT;
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
/* Process unlocked */
__HAL_UNLOCK(hadc);
@@ -823,19 +1039,29 @@
switch(EventType)
{
- /* Check analog watchdog flag */
+ /* Analog watchdog (level out of window) event */
case ADC_AWD_EVENT:
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_AWD;
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
break;
- /* Case ADC_OVR_EVENT */
- default:
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_ERROR;
+ /* Overrun event */
+ default: /* Case ADC_OVR_EVENT */
+ /* If overrun is set to overwrite previous data, overrun event is not */
+ /* considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without */
+ /* overrun ") */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+ }
/* Clear ADC Overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
@@ -847,280 +1073,188 @@
}
/**
- * @brief Enables the interrupt and starts ADC conversion of regular channels.
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
- * @retval HAL status.
+ * @brief Enables ADC, starts conversion of regular group with interruption.
+ * Interruptions enabled in this function:
+ * - EOC (end of conversion of regular group) or EOS (end of
+ * sequence of regular group) depending on ADC initialization
+ * parameter "EOCSelection"
+ * - overrun (if available)
+ * Each of these interruptions has its dedicated callback function.
+ * @param hadc: ADC handle
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
- if (ADC_IS_CONVERSION_ONGOING(hadc) == RESET)
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
{
/* Process locked */
__HAL_LOCK(hadc);
- /* State machine update: Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_REG;
-
- /* Set ADC error code to none */
- hadc->ErrorCode = HAL_ADC_ERROR_NONE;
-
/* Enable the ADC peripheral */
/* If low power mode AutoPowerOff is enabled, power-on/off phases are */
/* performed automatically by hardware. */
if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
{
- tmpHALStatus = ADC_Enable(hadc);
+ tmp_hal_status = ADC_Enable(hadc);
}
/* Start conversion if ADC is effectively enabled */
- if (tmpHALStatus != HAL_ERROR)
+ if (tmp_hal_status == HAL_OK)
{
- /* Enable ADC overrun interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
/* Enable ADC end of conversion interrupt */
+ /* Enable ADC overrun interrupt */
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
switch(hadc->Init.EOCSelection)
{
case ADC_EOC_SEQ_CONV:
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
+ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR));
break;
/* case ADC_EOC_SINGLE_CONV */
default:
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOS);
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
break;
}
- /* ADC start conversion command */
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
hadc->Instance->CR |= ADC_CR_ADSTART;
}
-
- else
- {
- tmpHALStatus = HAL_ERROR;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
}
else
{
- tmpHALStatus = HAL_BUSY;
+ tmp_hal_status = HAL_BUSY;
}
/* Return function status */
- return tmpHALStatus;
+ return tmp_hal_status;
}
/**
- * @brief Stop ADC conversion of regular channels, disable interruptions
- * EOC/EOS/OVR, disable ADC peripheral.
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
- * @retval None
+ * @brief Stop ADC conversion of regular group, disable interruption of
+ * end-of-conversion, disable ADC peripheral.
+ * @param hadc: ADC handle
+ * @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
- /* 1. Stop potential conversion ongoing (regular conversion) */
- tmpHALStatus = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+ /* 1. Stop potential conversion on going, on regular group */
+ tmp_hal_status = ADC_ConversionStop(hadc);
- /* 2. Disable ADC peripheral if conversions are effectively stopped */
- if (tmpHALStatus != HAL_ERROR)
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
{
- /* Disable ADC interrupts */
+ /* Disable ADC end of conversion interrupt for regular group */
+ /* Disable ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
- /* Disable the ADC peripheral */
- tmpHALStatus = ADC_Disable(hadc);
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
/* Check if ADC is effectively disabled */
- if ((hadc->State != HAL_ADC_STATE_ERROR) && (tmpHALStatus != HAL_ERROR))
+ if (tmp_hal_status == HAL_OK)
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
- }
- else
- {
- return HAL_ERROR;
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
}
}
- else
- {
- return HAL_ERROR;
- }
-
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
- * @brief Handles ADC interrupt request
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
- * @retval None
- */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
-
-
- /* Check End of Conversion flag for regular channels */
- if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || \
- (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) )
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC;
-
-
- /* Disable interruption if no further conversion upcoming by continuous mode or external trigger */
- if((hadc->Init.ContinuousConvMode == DISABLE) && \
- (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
- )
- {
- /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit ADSTART==0 (no conversion on going) */
- if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADSTART))
- {
- /* Cases of interruption after each conversion or after each sequence */
- /* If interruption after each sequence */
- if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
- {
- /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS/ADC_IT_OVR only if bit*/
- /* ADSTART==0 (no conversion on going) */
- if (ADC_IS_CONVERSION_ONGOING(hadc) == RESET)
- {
- /* If End of Sequence is reached, disable interrupts */
- if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
- {
- /* DISABLE ADC end of sequence conversion interrupt */
- /* DISABLE ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR);
- }
- }
- else
- {
- /* Change ADC state to error state */
- hadc->State = HAL_ADC_STATE_ERROR;
- /* Set ADC error code to ADC IP internal error */
- hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
- }
- }
- /* If interruption after each conversion */
- else
- {
- /* DISABLE ADC end of single conversion interrupt */
- /* DISABLE ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_OVR);
- }
- }
- else
- {
- /* Change ADC state to error state */
- hadc->State = HAL_ADC_STATE_ERROR;
- }
- }
-
- /* Conversion complete callback */
- /* Note: into callback, to determine if callback has been triggered from EOC or EOS, */
- /* it is possible to use: if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) */
- HAL_ADC_ConvCpltCallback(hadc);
-
- /* Clear regular channels conversion flag */
- if (hadc->Init.LowPowerAutoWait != ENABLE)
- {
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
- }
- }
-
-
- /* Check Analog watchdog flags */
- if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)))
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_AWD;
-
- /* Level out of window callback */
- HAL_ADC_LevelOutOfWindowCallback(hadc);
-
- /* Clear ADC Analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
- }
-
- /* Check Overrun flag */
- if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
- {
- /* Change ADC state to overrun state */
- hadc->State = HAL_ADC_STATE_ERROR;
-
- /* Set ADC error code to overrun */
- hadc->ErrorCode |= HAL_ADC_ERROR_OVR;
-
- /* Clear the Overrun flag */
- __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_OVR);
-
- /* Error callback */
- HAL_ADC_ErrorCallback(hadc);
- }
-}
-
-/**
- * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
+ * @brief Enables ADC, starts conversion of regular group and transfers result
+ * through DMA.
+ * Interruptions enabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun
+ * Each of these interruptions has its dedicated callback function.
+ * @param hadc: ADC handle
* @param pData: The destination Buffer address.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
* @retval None
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
- if (ADC_IS_CONVERSION_ONGOING(hadc) == RESET)
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
{
/* Process locked */
__HAL_LOCK(hadc);
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_REG;
-
- /* Set ADC error code to none */
- hadc->ErrorCode = HAL_ADC_ERROR_NONE;
-
- /* Enable the ADC peripheral */
+ /* Enable the ADC peripheral */
/* If low power mode AutoPowerOff is enabled, power-on/off phases are */
/* performed automatically by hardware. */
if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
{
- tmpHALStatus = ADC_Enable(hadc);
+ tmp_hal_status = ADC_Enable(hadc);
}
/* Start conversion if ADC is effectively enabled */
- if (tmpHALStatus != HAL_ERROR)
+ if (tmp_hal_status == HAL_OK)
{
- /* Enable ADC DMA mode */
- hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN;
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
@@ -1131,155 +1265,311 @@
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
- /* Manage ADC and DMA start: ADC overrun interruption, DMA start,
- ADC start (in case of SW start) */
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
- /* Enable the DMA Stream */
+ /* Enable ADC DMA mode */
+ hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN;
+
+ /* Start the DMA channel */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
- /* ADC start conversion command */
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
hadc->Instance->CR |= ADC_CR_ADSTART;
}
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
}
else
{
- tmpHALStatus = HAL_BUSY;
+ tmp_hal_status = HAL_BUSY;
}
/* Return function status */
- return tmpHALStatus;
+ return tmp_hal_status;
}
/**
- * @brief Disable ADC DMA (Single-ADC mode), disable ADC peripheral
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
- * @retval None
+ * @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable
+ * ADC peripheral.
+ * Each of these interruptions has its dedicated callback function.
+ * @param hadc: ADC handle
+ * @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
- /* 1. Stop potential conversion ongoing (regular conversion) */
- tmpHALStatus = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+ /* 1. Stop potential conversion on going, on regular group */
+ tmp_hal_status = ADC_ConversionStop(hadc);
- /* 2. Disable ADC peripheral if conversions are effectively stopped */
- if (tmpHALStatus != HAL_ERROR)
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
{
/* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
hadc->Instance->CFGR1 &= ~ADC_CFGR1_DMAEN;
- /* Disable the DMA Stream */
- if (HAL_DMA_Abort(hadc->DMA_Handle) != HAL_OK)
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
}
/* Disable ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
- /* Disable the ADC peripheral */
- tmpHALStatus = ADC_Disable(hadc);
-
- /* Check if ADC is effectively disabled */
- if ((hadc->State != HAL_ADC_STATE_ERROR) && (tmpHALStatus != HAL_ERROR))
+ /* 2. Disable the ADC peripheral */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */
+ /* in memory a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ tmp_hal_status = ADC_Disable(hadc);
}
else
{
- return HAL_ERROR;
+ ADC_Disable(hadc);
}
- }
- else
- {
- return HAL_ERROR;
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
- * @brief Gets the converted value from data register of regular channel.
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
+ * @brief Get ADC regular group conversion result.
+ * @note Reading DR register automatically clears EOC (end of conversion of
+ * regular group) flag.
+ * @note This function does not clear ADC flag EOS
+ * (ADC group regular end of sequence conversion).
+ * Occurrence of flag EOS rising:
+ * - If sequencer is composed of 1 rank, flag EOS is equivalent
+ * to flag EOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag EOC only is raised, at the end of the scan sequence
+ * both flags EOC and EOS are raised.
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADC_PollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+ * @param hadc: ADC handle
* @retval Converted value
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
{
- /* Return the selected ADC converted value */
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Note: EOC flag is not cleared here by software because automatically */
+ /* cleared by hardware when reading register DR. */
+
+ /* Return ADC converted value */
return hadc->Instance->DR;
}
/**
- * @brief Regular conversion complete callback in non blocking mode
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
+ * @brief Handles ADC interrupt request.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+
+ /* ========== Check End of Conversion flag for regular group ========== */
+ if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) ||
+ (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) )
+ {
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ }
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+ /* Note: into callback, to determine if conversion has been triggered */
+ /* from EOC or EOS, possibility to use: */
+ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
+ HAL_ADC_ConvCpltCallback(hadc);
+
+
+ /* Clear regular group conversion flag */
+ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
+ /* conversion flags clear induces the release of the preserved data.*/
+ /* Therefore, if the preserved data value is needed, it must be */
+ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
+ }
+
+ /* ========== Check Analog watchdog flags ========== */
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Level out of window callback */
+ HAL_ADC_LevelOutOfWindowCallback(hadc);
+
+ /* Clear ADC Analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+
+ }
+
+
+ /* ========== Check Overrun flag ========== */
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
+ {
+ /* If overrun is set to overwrite previous data (default setting), */
+ /* overrun event is not considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without */
+ /* overrun ") */
+ /* Exception for usage with DMA overrun event always considered as an */
+ /* error. */
+ if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) ||
+ HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) )
+ {
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+
+ /* Clear ADC overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+
+ /* Error callback */
+ HAL_ADC_ErrorCallback(hadc);
+ }
+
+ /* Clear the Overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ }
+}
+
+/**
+ * @brief Conversion complete callback in non blocking mode
+ * @param hadc: ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ADC_ConvCpltCallback could be implemented in the user file
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvCpltCallback must be implemented in the user file.
*/
}
/**
- * @brief Regular conversion half DMA transfer callback in non blocking mode
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
+ * @brief Conversion DMA half-transfer callback in non blocking mode
+ * @param hadc: ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
*/
}
/**
- * @brief Analog watchdog callback in non blocking mode
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
+ * @brief Analog watchdog callback in non blocking mode.
+ * @param hadc: ADC handle
* @retval None
*/
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
*/
}
/**
- * @brief Error ADC callback.
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
+ * @brief ADC error callback in non blocking mode
+ * (ADC conversion with interruption or transfer by DMA)
+ * @param hadc: ADC handle
* @retval None
*/
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ADC_ErrorCallback could be implemented in the user file
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ErrorCallback must be implemented in the user file.
*/
}
@@ -1287,7 +1577,7 @@
* @}
*/
-/** @defgroup ADC_Group3 Peripheral Control functions
+/** @addtogroup ADC_Exported_Functions_Group3
* @brief Peripheral Control functions
*
@verbatim
@@ -1295,8 +1585,8 @@
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) Configure channels.
- (+) Configure the analog watch dog.
+ (+) Configure channels on regular group
+ (+) Configure the analog watchdog
@endverbatim
* @{
@@ -1304,11 +1594,27 @@
/**
- * @brief Configures the selected ADC regular channel: sampling time,
- * offset,.
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
- * @param sConfig: ADC regular channel configuration structure.
+ * @brief Configures the the selected channel to be linked to the regular
+ * group.
+ * @note In case of usage of internal measurement channels:
+ * VrefInt/Vlcd(STM32L0x3xx only)/TempSensor.
+ * Sampling time constraints must be respected (sampling time can be
+ * adjusted in function of ADC clock frequency and sampling time
+ * setting).
+ * Refer to device datasheet for timings values, parameters TS_vrefint,
+ * TS_vlcd (STM32L0x3xx only), TS_temp (values rough order: 5us to 17us).
+ * These internal paths can be be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes channel into regular group, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_ChannelConfTypeDef".
+ * @param hadc: ADC handle
+ * @param sConfig: Structure of ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
@@ -1316,51 +1622,85 @@
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+ assert_param(IS_ADC_RANK(sConfig->Rank));
/* Process locked */
__HAL_LOCK(hadc);
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going : */
+ /* conversion on going on regular group: */
/* - Channel number */
/* - Management of internal measurement channels: Vbat/VrefInt/TempSensor */
- if (ADC_IS_CONVERSION_ONGOING(hadc) != RESET)
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET)
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
/* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_ERROR;
}
- /* Enable selected channels */
- hadc->Instance->CHSELR |= (uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK);
-
- /* Management of internal measurement channels: Vlcd/VrefInt/TempSensor */
- /* internal measurement paths enable: If internal channel selected, enable */
- /* dedicated internal buffers and path. */
-
- /* If Temperature sensor channel is selected, then enable the internal */
- /* buffers and path */
- if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_MASK))
+ if (sConfig->Rank != ADC_RANK_NONE)
{
- ADC->CCR |= ADC_CCR_TSEN;
+ /* Enable selected channels */
+ hadc->Instance->CHSELR |= (uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK);
+
+ /* Management of internal measurement channels: Vlcd (STM32L0x3xx only)/VrefInt/TempSensor */
+ /* internal measurement paths enable: If internal channel selected, enable */
+ /* dedicated internal buffers and path. */
+
+ /* If Temperature sensor channel is selected, then enable the internal */
+ /* buffers and path */
+ if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_MASK))
+ {
+ ADC->CCR |= ADC_CCR_TSEN;
+
+ /* Delay for temperature sensor stabilization time */
+ ADC_DelayMicroSecond(ADC_TEMPSENSOR_DELAY_US);
+ }
+
+ /* If VRefInt channel is selected, then enable the internal buffers and path */
+ if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK))
+ {
+ ADC->CCR |= ADC_CCR_VREFEN;
+ }
- /* Delay for temperature sensor stabilization time */
- ADC_DelayMicroSecond(ADC_TEMPSENSOR_DELAY_US);
+#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
+ /* If Vlcd channel is selected, then enable the internal buffers and path */
+ if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VLCD) == (ADC_CHANNEL_VLCD & ADC_CHANNEL_MASK))
+ {
+ ADC->CCR |= ADC_CCR_VLCDEN;
+ }
+#endif
}
-
- /* If VRefInt channel is selected, then enable the internal buffers and path */
- if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK))
+ else
{
- ADC->CCR |= ADC_CCR_VREFEN;
- }
-
- /* If Vlcd channel is selected, then enable the internal buffers and path */
- if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VLCD) == (ADC_CHANNEL_VLCD & ADC_CHANNEL_MASK))
- {
- ADC->CCR |= ADC_CCR_VLCDEN;
+ /* Regular sequence configuration */
+ /* Reset the channel selection register from the selected channel */
+ hadc->Instance->CHSELR &= ~((uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK));
+
+ /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
+ /* internal measurement paths disable: If internal channel selected, */
+ /* disable dedicated internal buffers and path. */
+ if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_MASK))
+ {
+ ADC->CCR &= ~ADC_CCR_TSEN;
+ }
+
+ /* If VRefInt channel is selected, then enable the internal buffers and path */
+ if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK))
+ {
+ ADC->CCR &= ~ADC_CCR_VREFEN;
+ }
+
+#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
+ /* If Vlcd channel is selected, then enable the internal buffers and path */
+ if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VLCD) == (ADC_CHANNEL_VLCD & ADC_CHANNEL_MASK))
+ {
+ ADC->CCR &= ~ADC_CCR_VLCDEN;
+ }
+#endif
}
/* Process unlocked */
@@ -1372,14 +1712,22 @@
/**
* @brief Configures the analog watchdog.
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
- * @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure
- * that contains the configuration information of ADC analog watchdog.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the selected analog watchdog, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_AnalogWDGConfTypeDef".
+ * @param hadc: ADC handle
+ * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
uint32_t tmpAWDHighThresholdShifted;
uint32_t tmpAWDLowThresholdShifted;
@@ -1389,75 +1737,83 @@
assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+ /* Verify if threshold is within the selected ADC resolution */
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+ if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
+ {
+ assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+ }
+
/* Process locked */
__HAL_LOCK(hadc);
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going : */
+ /* conversion on going on regular group: */
/* - Analog watchdog channels */
/* - Analog watchdog thresholds */
- if (ADC_IS_CONVERSION_ONGOING(hadc) != RESET)
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
{
- /* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
- return HAL_ERROR;
- }
-
- /* Configure ADC Analog watchdog interrupt */
- if(AnalogWDGConfig->ITMode == ENABLE)
- {
- /* Enable the ADC Analog watchdog interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
+ /* Configure ADC Analog watchdog interrupt */
+ if(AnalogWDGConfig->ITMode == ENABLE)
+ {
+ /* Enable the ADC Analog watchdog interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
+ }
+ else
+ {
+ /* Disable the ADC Analog watchdog interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
+ }
+
+ /* Configuration of analog watchdog: */
+ /* - Set the analog watchdog mode */
+ /* - Set the Analog watchdog channel (is not used if watchdog */
+ /* mode "all channels": ADC_CFGR1_AWD1SGL=0) */
+ hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL |
+ ADC_CFGR1_AWDEN |
+ ADC_CFGR1_AWDCH);
+
+ hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode |
+ (AnalogWDGConfig->Channel & ADC_CHANNEL_AWD_MASK));
+
+
+ /* Shift the offset in function of the selected ADC resolution: Thresholds */
+ /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+ tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+ tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+
+ /* Clear High & Low high thresholds */
+ hadc->Instance->TR &= (uint32_t) ~ (ADC_TR_HT | ADC_TR_LT);
+
+ /* Set the high threshold */
+ hadc->Instance->TR = ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted);
+ /* Set the low threshold */
+ hadc->Instance->TR |= tmpAWDLowThresholdShifted;
}
else
{
- /* Disable the ADC Analog watchdog interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
- }
-
- /* Configuration of analog watchdog: */
- /* - Set the analog watchdog mode */
- /* - Set the Analog watchdog channel (is not used if watchdog */
- /* mode "all channels": ADC_CFGR1_AWD1SGL=0) */
- hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL |
- ADC_CFGR1_AWDEN |
- ADC_CFGR1_AWDCH);
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode |
- (AnalogWDGConfig->Channel & ADC_CHANNEL_AWD_MASK));
-
+ tmp_hal_status = HAL_ERROR;
+ }
- /* Shift the offset in function of the selected ADC resolution: Thresholds */
- /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
- tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
- tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
-
- /* Clear High & Low high thresholds */
- hadc->Instance->TR &= (uint32_t) ~ (ADC_TR_HT | ADC_TR_LT);
-
- /* Set the high threshold */
- hadc->Instance->TR = ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted);
- /* Set the low threshold */
- hadc->Instance->TR |= tmpAWDLowThresholdShifted;
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
* @}
*/
-/** @defgroup ADC_Group4 ADC Peripheral State functions
+/** @addtogroup ADC_Exported_Functions_Group4
* @brief ADC Peripheral State functions
*
@verbatim
@@ -1475,20 +1831,21 @@
/**
* @brief return the ADC state
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
+ * @param hadc: ADC handle
* @retval HAL state
*/
-HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
/* Return ADC state */
return hadc->State;
}
/**
* @brief Return the ADC error code
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
+ * @param hadc: ADC handle
* @retval ADC Error Code
*/
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
@@ -1502,6 +1859,15 @@
*/
/**
+ * @}
+ */
+
+
+/** @addtogroup ADC_Private
+ * @{
+ */
+
+/**
* @brief Enable the selected ADC.
* @note Prerequisite condition to use this function: ADC must be disabled
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
@@ -1528,10 +1894,10 @@
if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
- hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
@@ -1542,31 +1908,24 @@
/* Delay for ADC stabilization time. */
ADC_DelayMicroSecond(ADC_STAB_DELAY_US);
- /* Wait for ADC effectively enabled */
- /* Get timeout */
+ /* Get tick count */
tickstart = HAL_GetTick();
- /* Skip polling for RDY ADRDY when AutoOFF is enabled */
- if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
- {
+ /* Wait for ADC effectively enabled */
while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
{
- /* Check for the Timeout */
- if(ADC_ENABLE_TIMEOUT != HAL_MAX_DELAY)
- {
if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT)
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
- hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
}
- }
- }
+
}
/* Return HAL status */
@@ -1576,7 +1935,7 @@
/**
* @brief Disable the selected ADC.
* @note Prerequisite condition to use this function: ADC conversions must be
- * stopped to disable the ADC.
+ * stopped.
* @param hadc: ADC handle
* @retval HAL status.
*/
@@ -1585,7 +1944,7 @@
uint32_t tickstart = 0;
/* Verification if ADC is not already disabled: */
- /* forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
+ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
/* disabled. */
if (ADC_IS_ENABLE(hadc) != RESET )
{
@@ -1598,36 +1957,32 @@
else
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Set ADC error code to ADC internal error */
- hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
/* Wait for ADC effectively disabled */
- /* Get timeout */
+ /* Get tick count */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
{
- /* Check for the Timeout */
- if(ADC_ENABLE_TIMEOUT != HAL_MAX_DELAY)
- {
if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT)
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Set ADC error code to ADC internal error */
- hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
}
}
- }
/* Return HAL status */
return HAL_OK;
@@ -1638,66 +1993,47 @@
* @note Prerequisite condition to use this function: ADC conversions must be
* stopped to disable the ADC.
* @param hadc: ADC handle
- * @param ConversionGroup: Only ADC group regular.
- * This parameter can be one of the following values:
- * @arg ADC_REGULAR_GROUP: ADC regular conversion type.
* @retval HAL status.
*/
-static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
+static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
{
- uint32_t tickstart = 0 ;
+ uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
-
- /* Parameters update conditioned to ADC state: */
- /* Parameters that can be updated when ADC is disabled or enabled without */
- /* conversion on going : */
- if (ADC_IS_CONVERSION_ONGOING(hadc) != RESET)
+
+ /* Verification if ADC is not already stopped on regular group to bypass */
+ /* this function if not needed. */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
{
- /* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
- /* Process unlocked */
- return HAL_ERROR;
- }
-
- /* Verification: if ADC is not already stopped, bypass this function */
- if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART))
- {
- /* Stop potential conversion on regular group */
- if (ConversionGroup == ADC_REGULAR_GROUP)
+
+ /* Stop potential conversion on going on regular group */
+ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
{
- /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
- if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && \
- HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
- {
- /* Stop conversions on regular group */
- hadc->Instance->CR |= ADC_CR_ADSTP;
- }
+ /* Stop conversions on regular group */
+ hadc->Instance->CR |= ADC_CR_ADSTP;
}
/* Wait for conversion effectively stopped */
- /* Get timeout */
+ /* Get tick count */
tickstart = HAL_GetTick();
while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
{
- /* Check for the Timeout */
- if(ADC_STOP_CONVERSION_TIMEOUT != HAL_MAX_DELAY)
+ if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
- if((HAL_GetTick() - tickstart ) > ADC_STOP_CONVERSION_TIMEOUT)
- {
- /* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
-
- /* Set ADC error code to ADC IP internal error */
- hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
-
- return HAL_ERROR;
- }
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
}
- }
+ }
+
}
/* Return HAL status */
@@ -1711,13 +2047,59 @@
*/
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
+ /* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC;
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+
+ /* Conversion complete callback */
HAL_ADC_ConvCpltCallback(hadc);
}
+ else
+ {
+ /* Call DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
+ }
+
+}
/**
* @brief DMA half transfer complete callback.
@@ -1726,9 +2108,10 @@
*/
static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
{
+ /* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Conversion complete callback */
+ /* Half conversion callback */
HAL_ADC_ConvHalfCpltCallback(hadc);
}
@@ -1739,11 +2122,17 @@
*/
static void ADC_DMAError(DMA_HandleTypeDef *hdma)
{
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hadc->State= HAL_ADC_STATE_ERROR;
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
/* Set ADC error code to DMA error */
- hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
- HAL_ADC_ErrorCallback(hadc);
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+
+ /* Error callback */
+ HAL_ADC_ErrorCallback(hadc);
}
/**
@@ -1766,11 +2155,11 @@
* @}
*/
-#endif /* HAL_ADC_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_ADC_MODULE_ENABLED */
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32l0xx_hal_adc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -51,25 +51,49 @@
* @{
*/
-/** @addtogroup ADC
+/** @defgroup ADC ADC
* @{
*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
+
/* Exported types ------------------------------------------------------------*/
/**
- * @brief HAL State structures definition
+ * @brief HAL ADC state machine: ADC states definition (bitfields)
*/
-typedef enum
-{
- HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
- HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
- HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
- HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
- HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
- HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
- HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog */
-}HAL_ADC_StateTypeDef;
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+ external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32F0 device: End Of Sampling flag raised */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+ external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Not available on STM32F0 device: Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */
/**
@@ -101,7 +125,10 @@
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t ClockPrescaler; /*!< Selects the ADC clock frequency.
This parameter can be a value of @ref ADC_ClockPrescaler
- Note: This parameter can be modified only if ADC is disabled. */
+ Note: This parameter can be modified only if ADC is disabled.
+ Note: In case of Synchronous clock mode divided by 1, this configuration must be enabled only
+ if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC
+ must be bypassed and the system clock must by 50% duty cycle). Refer to reference manual for details */
uint32_t Resolution; /*!< Configures the ADC resolution mode.
This parameter can be a value of @ref ADC_Resolution
Note: This parameter can be modified only if ADC is disabled. */
@@ -109,6 +136,9 @@
This parameter can be a value of @ref ADC_sampling_times
Note: This parameter can be modified only if there is no conversion ongoing. */
uint32_t ScanConvMode; /*!< The scan sequence direction.
+ If several channels are set: Conversions are performed in sequence mode
+ (ranks defined by each channel number: channel 0 fixed on rank 0,
+ channel 1 fixed on rank1, ...).
This parameter can be a value of @ref ADC_Scan_mode
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
@@ -122,11 +152,13 @@
Discontinuous mode can be enabled only if continuous mode is disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
- uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger.
- This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge
+ uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion.
+ If set to ADC_SOFTWARE_START, external triggers are disabled.
+ This parameter can be a value of @ref ADC_External_trigger_Source
Note: This parameter can be modified only if there is no conversion is ongoing. */
- uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion.
- This parameter can be a value of @ref ADC_External_trigger_Source
+ uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger.
+ If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
+ This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
@@ -158,7 +190,7 @@
/**
* @brief ADC handle Structure definition
*/
-typedef struct __ADC_HandleTypeDef
+typedef struct
{
ADC_TypeDef *Instance; /*!< Register base address */
@@ -168,7 +200,7 @@
HAL_LockTypeDef Lock; /*!< ADC locking object */
- __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
+ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */
}ADC_HandleTypeDef;
@@ -180,6 +212,12 @@
{
uint32_t Channel; /*!< the ADC channel to configure
This parameter can be a value of @ref ADC_channels */
+
+ uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
+ On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number
+ (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
+ This parameter can be a value of @ref ADC_rank */
}ADC_ChannelConfTypeDef;
@@ -203,26 +241,30 @@
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
}ADC_AnalogWDGConfTypeDef;
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADC_Exported_Constants
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
* @{
*/
-/** @defgroup ADC_Error_Code
+/** @defgroup ADC_Error_Code ADC Error Code
* @{
*/
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< OVR error */
-#define HAL_ADC_ERROR_DMA ((uint32_t)0x03) /*!< DMA transfer error */
+#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
/**
* @}
*/
-/** @defgroup ADC_TimeOut_Values
+/** @defgroup ADC_TimeOut_Values ADC TimeOut Values
* @{
*/
@@ -242,7 +284,7 @@
* @}
*/
-/** @defgroup ADC_ClockPrescaler
+/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
* @{
*/
#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode divided by 1 */
@@ -258,60 +300,34 @@
#define ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */
#define ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
-#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< Synchronous clock mode divided by 1
+#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 1
This configuration must be enabled only if PCLK has a 50%
duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
must by 50% duty cycle)*/
-#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< Synchronous clock mode divided by 2 */
-#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 4 */
+#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< Synchronous clock mode divided by 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< Synchronous clock mode divided by 4 */
-#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
/**
* @}
*/
-/** @defgroup ADC_Resolution
+/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */
-
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
- ((RESOLUTION) == ADC_RESOLUTION_10B) || \
- ((RESOLUTION) == ADC_RESOLUTION_8B) || \
- ((RESOLUTION) == ADC_RESOLUTION_6B))
-
-#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
- ((RESOLUTION) == ADC_RESOLUTION_6B))
/**
* @}
*/
-/** @defgroup ADC_data_align
+/** @defgroup ADC_data_align ADC Data Align
* @{
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
- ((ALIGN) == ADC_DATAALIGN_LEFT))
/**
* @}
*/
@@ -323,63 +339,41 @@
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN)
+/**
+ * @}
+ */
-#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
+/** @defgroup ADC_EOCSelection ADC EOC Selection
+ * @{
+ */
+#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
+#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
+#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */
/**
* @}
*/
-/** @defgroup ADC_External_trigger_Source
+/** @defgroup ADC_Overrun ADC Overrun
* @{
- */
-#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)0x00000000)
-#define ADC_EXTERNALTRIGCONV_T21_CC2 ADC_CFGR1_EXTSEL_0
-#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_CFGR1_EXTSEL_1
-#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)0x000000C0)
-#define ADC_EXTERNALTRIGCONV_T22_TRGO ADC_CFGR1_EXTSEL_2
-#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_CFGR1_EXTSEL
-
-#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_EXTERNALTRIGCONV_T6_TRGO ) || \
- ((CONV) == ADC_EXTERNALTRIGCONV_T21_CC2 ) || \
- ((CONV) == ADC_EXTERNALTRIGCONV_T2_TRGO ) || \
- ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC4 ) || \
- ((CONV) == ADC_EXTERNALTRIGCONV_T22_TRGO ) || \
- ((CONV) == ADC_EXTERNALTRIGCONV_EXT_IT11 ))
-
+ */
+#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000)
+#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD)
/**
* @}
*/
-/** @defgroup ADC_EOCSelection
+
+/** @defgroup ADC_rank ADC rank
* @{
*/
-#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
-#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
-#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */
-
-#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
- ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \
- ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV))
+#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
+#define ADC_RANK_NONE ((uint32_t)0x00001001) /*!< Disable the selected rank (selected channel) from sequencer */
/**
* @}
- */
-
-/** @defgroup ADC_Overrun
- * @{
- */
-#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000)
-#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD)
+ */
-#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
- ((OVR) == ADC_OVR_DATA_OVERWRITTEN))
-/**
- * @}
- */
-/** @defgroup ADC_channels
+/** @defgroup ADC_channels ADC_Channels
* @{
*/
#define ADC_CHANNEL_0 ((uint32_t)(ADC_CHSELR_CHSEL0))
@@ -398,41 +392,23 @@
#define ADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)
#define ADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)
#define ADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)
+#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
#define ADC_CHANNEL_16 ((uint32_t)(ADC_CHSELR_CHSEL16)| ADC_CFGR1_AWDCH_4)
+#endif
#define ADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_0)
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_1)
/* Internal channels */
+#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
#define ADC_CHANNEL_VLCD ADC_CHANNEL_16
+#endif
#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18
-
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
- ((CHANNEL) == ADC_CHANNEL_1) || \
- ((CHANNEL) == ADC_CHANNEL_2) || \
- ((CHANNEL) == ADC_CHANNEL_3) || \
- ((CHANNEL) == ADC_CHANNEL_4) || \
- ((CHANNEL) == ADC_CHANNEL_5) || \
- ((CHANNEL) == ADC_CHANNEL_6) || \
- ((CHANNEL) == ADC_CHANNEL_7) || \
- ((CHANNEL) == ADC_CHANNEL_8) || \
- ((CHANNEL) == ADC_CHANNEL_9) || \
- ((CHANNEL) == ADC_CHANNEL_10) || \
- ((CHANNEL) == ADC_CHANNEL_11) || \
- ((CHANNEL) == ADC_CHANNEL_12) || \
- ((CHANNEL) == ADC_CHANNEL_13) || \
- ((CHANNEL) == ADC_CHANNEL_14) || \
- ((CHANNEL) == ADC_CHANNEL_15) || \
- ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
- ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
- ((CHANNEL) == ADC_CHANNEL_VLCD))
-
/**
* @}
*/
-/** @defgroup ADC_Channel_AWD_Masks
+/** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks
* @{
*/
#define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFF)
@@ -442,7 +418,7 @@
*/
-/** @defgroup ADC_sampling_times
+/** @defgroup ADC_sampling_times ADC Sampling Cycles
* @{
*/
@@ -454,15 +430,6 @@
#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 55.5 CYCLES */
#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1)) /*!< ADC sampling time 71.5 CYCLES */
#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /*!< ADC sampling time 239.5 CYCLES */
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) || \
- ((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) || \
- ((TIME) == ADC_SAMPLETIME_13CYCLES_5 ) || \
- ((TIME) == ADC_SAMPLETIME_28CYCLES_5 ) || \
- ((TIME) == ADC_SAMPLETIME_41CYCLES_5 ) || \
- ((TIME) == ADC_SAMPLETIME_55CYCLES_5 ) || \
- ((TIME) == ADC_SAMPLETIME_71CYCLES_5 ) || \
- ((TIME) == ADC_SAMPLETIME_239CYCLES_5))
/**
* @}
*/
@@ -486,15 +453,11 @@
#define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002) /*!< Scan direction backward: from channel 18 to channel 0 */
#define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */
-
-#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
- ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
-
/**
* @}
*/
-/** @defgroup ADC_Oversampling_Ratio
+/** @defgroup ADC_Oversampling_Ratio ADC Oversampling Ratio
* @{
*/
@@ -506,19 +469,11 @@
#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014) /*!< ADC Oversampling ratio 64x */
#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018) /*!< ADC Oversampling ratio 128x */
#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001C) /*!< ADC Oversampling ratio 256x */
-#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) || \
- ((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) || \
- ((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) || \
- ((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) || \
- ((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) || \
- ((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) || \
- ((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) || \
- ((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))
/**
* @}
*/
-/** @defgroup ADC_Right_Bit_Shift
+/** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift
* @{
*/
#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */
@@ -530,67 +485,47 @@
#define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0) /*!< ADC 6 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0) /*!< ADC 7 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100) /*!< ADC 8 bits shift for oversampling */
-#define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_1 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_2 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_3 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_4 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_5 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_6 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_7 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_8 ))
/**
* @}
*/
-/** @defgroup ADC_Triggered_Oversampling_Mode
+/** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode
* @{
*/
#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */
#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200) /*!< ADC No bit shift for oversampling */
-#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
- ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
/**
* @}
*/
-/** @defgroup ADC_analog_watchdog_mode
+/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
* @{
*/
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN)
-
-
-#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG ))
/**
* @}
*/
-/** @defgroup ADC_conversion_type
+/** @defgroup ADC_conversion_type ADC Conversion Group
* @{
*/
#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))
-#define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP)
/**
* @}
*/
-/** @defgroup ADC_Event_type
+/** @defgroup ADC_Event_type ADC Event
* @{
*/
#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
-
-#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
- ((EVENT) == ADC_OVR_EVENT))
/**
* @}
*/
-/** @defgroup ADC_interrupts_definition
+/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
* @{
*/
#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready (ADRDY) interrupt source */
@@ -600,18 +535,13 @@
#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
#define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog 1 interrupt source */
#define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */
-
-/* Check of single flag */
-#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_RDY) || \
- ((IT) == ADC_IT_EOSMP) || ((IT) == ADC_IT_EOC) || \
- ((IT) == ADC_IT_EOS) || ((IT) == ADC_IT_OVR))
/**
* @}
*/
-/** @defgroup ADC_flags_definition
+/** @defgroup ADC_flags_definition ADC Flags Definition
* @{
*/
#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready (ADRDY) flag */
@@ -625,34 +555,6 @@
#define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
ADC_FLAG_OVR | ADC_FLAG_AWD | ADC_FLAG_EOCAL)
-
-/* Check of single flag */
-#define IS_ADC_FLAG(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
- ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOS) || \
- ((FLAG) == ADC_FLAG_OVR) || ((FLAG) == ADC_FLAG_AWD) || \
- ((FLAG) == ADC_FLAG_EOCAL))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_range_verification
- * in function of ADC resolution selected (12, 10, 8 or 6 bits)
- * @{
- */
-#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
- ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
- (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
- (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
- (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_nb_conv_verification
- * @{
- */
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
/**
* @}
*/
@@ -662,7 +564,7 @@
*/
/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Macro
+/** @defgroup ADC_Exported_Macro ADC Exported Macro
* @{
*/
/** @brief Reset ADC handle state
@@ -727,14 +629,25 @@
* @retval None
*/
#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
+/**
+ * @brief Test if conversion trigger of regular group is software start
+ * or external trigger.
+ * @param __HANDLE__: ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
+ (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
+
+
/**
- * @brief Check if no conversion is ongoing on regular groups
+ * @brief Check if no conversion on going on regular group
* @param __HANDLE__: ADC handle
* @retval SET (conversion is on going) or RESET (no conversion is on going)
*/
-#define ADC_IS_CONVERSION_ONGOING(__HANDLE__) \
- (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART)) == RESET ) ? RESET : SET)
+#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
+ (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
+ ) ? RESET : SET)
/**
* @brief Enable ADC continuous conversion mode.
@@ -788,7 +701,7 @@
*/
#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16)
- /**
+/**
* @brief Enable the ADC Low Frequency mode.
* @param _LOW_FREQUENCY_MODE_: Low Frequency mode.
* @retval None
@@ -840,7 +753,8 @@
* @param __INTERRUPT__: ADC Interrupt.
* @retval None
*/
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
/**
* @brief Disable the ADC end of conversion interrupt.
@@ -848,14 +762,18 @@
* @param __INTERRUPT__: ADC interrupt.
* @retval None
*/
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the ADC Handle.
- * @param __INTERRUPT__: specifies the ADC interrupt source to check.
- * @retval The new state of __IT__ (TRUE or FALSE).
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC interrupt source to check
+ * @arg ...
+ * @arg ...
+ * @retval State of interruption (TRUE or FALSE)
*/
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clear the ADC's pending flags
@@ -864,7 +782,8 @@
* @retval None
*/
/* Note: bit cleared bit by writing 1 */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (((__HANDLE__)->Instance->ISR) = (__FLAG__))
/**
* @brief Get the selected ADC's flag status.
@@ -872,7 +791,27 @@
* @param __FLAG__: ADC flag.
* @retval None
*/
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+
+/**
+ * @brief Simultaneously clears and sets specific bits of the handle State
+ * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+ * the first parameter is the ADC handle State, the second parameter is the
+ * bit field to clear, the third and last parameter is the bit field to set.
+ * @retval None
+ */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+ * @brief Clear ADC error code (set it to error code: "no error")
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
+ ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
@@ -900,6 +839,156 @@
} \
} while(0)
+
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_10B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_8B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_6B))
+
+#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_6B))
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT))
+
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
+
+#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
+ ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \
+ ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV))
+
+#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
+ ((OVR) == ADC_OVR_DATA_OVERWRITTEN))
+
+#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \
+ ((WATCHDOG) == ADC_RANK_NONE))
+
+#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
+ ((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) || \
+ ((CHANNEL) == ADC_CHANNEL_15) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
+ ((CHANNEL) == ADC_CHANNEL_VLCD))
+#else
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
+ ((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) || \
+ ((CHANNEL) == ADC_CHANNEL_15) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((CHANNEL) == ADC_CHANNEL_VREFINT))
+#endif
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) || \
+ ((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) || \
+ ((TIME) == ADC_SAMPLETIME_13CYCLES_5 ) || \
+ ((TIME) == ADC_SAMPLETIME_28CYCLES_5 ) || \
+ ((TIME) == ADC_SAMPLETIME_41CYCLES_5 ) || \
+ ((TIME) == ADC_SAMPLETIME_55CYCLES_5 ) || \
+ ((TIME) == ADC_SAMPLETIME_71CYCLES_5 ) || \
+ ((TIME) == ADC_SAMPLETIME_239CYCLES_5))
+
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
+ ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
+
+#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) || \
+ ((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) || \
+ ((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) || \
+ ((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) || \
+ ((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) || \
+ ((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) || \
+ ((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) || \
+ ((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))
+
+#define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_1 ) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_2 ) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_3 ) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_4 ) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_5 ) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_6 ) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_7 ) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_8 ))
+
+#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
+ ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
+
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG ))
+
+#define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP)
+
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
+ ((EVENT) == ADC_OVR_EVENT))
+
+
+/** @defgroup ADC_range_verification ADC Range Verification
+ * in function of ADC resolution selected (12, 10, 8 or 6 bits)
+ * @{
+ */
+#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
+ ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification
+ * @{
+ */
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -908,13 +997,26 @@
#include "stm32l0xx_hal_adc_ex.h"
/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+ * @{
+ */
/* Initialization and de-initialization functions **********************************/
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+/**
+ * @}
+ */
/* IO operation functions *****************************************************/
+/** @defgroup ADC_Exported_Functions_Group2 I/O operation functions
+ * @{
+ */
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
@@ -933,25 +1035,54 @@
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
/* Peripheral Control functions ***********************************************/
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+/**
+ * @}
+ */
/* Peripheral State functions *************************************************/
-HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
/**
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup ADC_Private ADC Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
+/**
+ * @}
+ */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc_ex.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc_ex.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_adc_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
@@ -33,7 +33,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -67,22 +67,41 @@
* @{
*/
+#ifdef HAL_ADC_MODULE_ENABLED
+
/** @addtogroup ADCEx
* @brief ADC driver modules
* @{
*/
-#ifdef HAL_ADC_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
+
/* Private define ------------------------------------------------------------*/
+
+/* Fixed timeout values for ADC calibration, enable settling time, disable */
+ /* settling time. */
+ /* Values defined to be higher than worst cases: low clock frequency, */
+ /* maximum prescaler. */
+ /* Unit: ms */
+ #define ADC_CALIBRATION_TIMEOUT 10
+
+/* Delay for VREFINT stabilization time. */
+/* Internal reference startup time max value is 3ms (refer to device datasheet, parameter TVREFINT). */
+/* Unit: ms */
+#define SYSCFG_BUF_VREFINT_ENABLE_TIMEOUT ((uint32_t) 3)
+
+/* Delay for TEMPSENSOR stabilization time. */
+/* Temperature sensor startup time max value is 10µs (refer to device datasheet, parameter tSTART). */
+/* Unit: ms */
+#define SYSCFG_BUF_TEMPSENSOR_ENABLE_TIMEOUT ((uint32_t) 1)
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @addtgroup ADCEx_Group ADC Extended features functions
+/** @addtogroup ADCEx_Exported_Functions
* @brief ADC Extended features functions
*
@verbatim
@@ -94,11 +113,18 @@
(+) Start calibration.
(+) Get calibration factor.
(+) Set calibration factor.
+ (+) Enable VREFInt.
+ (+) Disable VREFInt.
+ (+) Enable VREFInt TempSensor.
+ (+) Disable VREFInt TempSensor.
@endverbatim
* @{
*/
+/** @addtogroup ADCEx_Exported_Functions_Group3
+ * @{
+ */
/**
* @brief Start an automatic calibration
@@ -111,88 +137,66 @@
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
{
- uint32_t tickstart = 0;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tickstart=0;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
/* Process locked */
__HAL_LOCK(hadc);
-
- /* Disable the ADC (if not already disabled) */
- if (ADC_IS_ENABLE(hadc) != RESET )
+
+ /* Calibration prerequisite: ADC must be disabled. */
+ if (ADC_IS_ENABLE(hadc) == RESET)
{
- /* Check if conditions to disable the ADC are fulfilled */
- if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
- {
- __HAL_ADC_DISABLE(hadc);
- }
- else
- {
- hadc->State= HAL_ADC_STATE_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
- /* Wait for ADC effectively disabled */
- /* Get timeout */
+ /* Start ADC calibration */
+ hadc->Instance->CR |= ADC_CR_ADCAL;
+
tickstart = HAL_GetTick();
- /* Wait for disabling completion */
- while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
+ /* Wait for calibration completion */
+ while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
{
- /* Check for the Timeout */
- if(ADC_DISABLE_TIMEOUT != HAL_MAX_DELAY)
+ if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
{
- if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT)
- {
- hadc->State= HAL_ADC_STATE_TIMEOUT;
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
- /* Start ADC calibration */
- hadc->Instance->CR |= ADC_CR_ADCAL;
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait for calibration completion */
- while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
- {
- /* Check for the Timeout */
- if(ADC_CALIBRATION_TIMEOUT != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > ADC_CALIBRATION_TIMEOUT)
- {
- hadc->State= HAL_ADC_STATE_TIMEOUT;
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
/* Process unlocked */
__HAL_UNLOCK(hadc);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
- }
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
-
+ return tmp_hal_status;
}
+
/**
* @brief Get the calibration factor.
* @param hadc: ADC handle.
@@ -221,7 +225,7 @@
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -234,7 +238,7 @@
/* Verification of hardware constraints before modifying the calibration */
/* factors register: ADC must be enabled, no conversion on going. */
if ( (ADC_IS_ENABLE(hadc) != RESET) &&
- (ADC_IS_CONVERSION_ONGOING(hadc) == RESET) )
+ (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
{
/* Set the selected ADC calibration value */
hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT;
@@ -243,28 +247,49 @@
else
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
/* Update ADC state machine to error */
- tmpHALStatus = HAL_ERROR;
+ tmp_hal_status = HAL_ERROR;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
- return tmpHALStatus;
+ return tmp_hal_status;
}
/**
- * @brief Enables the Buffer Vrefint for the ADC.
- * @note This is functional only if the LOCK is not set.
+ * @brief Enables the buffer of Vrefint for the ADC, required when device is in mode low-power (low-power run, low-power sleep or stop mode)
+ * This function must be called before function HAL_ADC_Init()
+ * (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first)
+ * For more details on procedure and buffer current consumption, refer to device reference manual.
+ * @note This is functional only if the LOCK is not set.
* @retval None
- */
-void HAL_ADCEx_EnableVREFINT(void)
+*/
+HAL_StatusTypeDef HAL_ADCEx_EnableVREFINT(void)
{
- /* Enable the Buffer for the ADC by setting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */
- SET_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_VREFINT_ADC | SYSCFG_CFGR3_EN_VREFINT));
+ uint32_t tickstart = 0;
+
+ /* Enable the Buffer for the ADC by setting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */
+ SET_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_VREFINT_ADC | SYSCFG_CFGR3_EN_VREFINT));
+
+ /* Wait for Vrefint buffer effectively enabled */
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_ADC_RDYF))
+ {
+ if((HAL_GetTick() - tickstart) > SYSCFG_BUF_VREFINT_ENABLE_TIMEOUT)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ return HAL_OK;
}
/**
@@ -279,14 +304,33 @@
}
/**
- * @brief Enables VEREFINT and the Sensor for the ADC.
- * @note This is functional only if the LOCK is not set.
- * @retval None
- */
-void HAL_ADCEx_EnableVREFINTTempSensor(void)
+* @brief Enables the buffer of temperature sensor for the ADC, required when device is in mode low-power (low-power run, low-power sleep or stop mode)
+* This function must be called before function HAL_ADC_Init()
+* (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first)
+* For more details on procedure and buffer current consumption, refer to device reference manual.
+* @note This is functional only if the LOCK is not set.
+* @retval None
+*/
+HAL_StatusTypeDef HAL_ADCEx_EnableVREFINTTempSensor(void)
{
- /* Enable the Buffer for the ADC by setting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */
- SET_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_SENSOR_ADC | SYSCFG_CFGR3_EN_VREFINT));
+ uint32_t tickstart = 0;
+
+ /* Enable the Buffer for the ADC by setting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */
+ SET_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_SENSOR_ADC | SYSCFG_CFGR3_EN_VREFINT));
+
+ /* Wait for Vrefint buffer effectively enabled */
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_ADC_RDYF))
+ {
+ if((HAL_GetTick() - tickstart) > SYSCFG_BUF_TEMPSENSOR_ENABLE_TIMEOUT)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ return HAL_OK;
}
/**
@@ -304,14 +348,17 @@
* @}
*/
-
-#endif /* HAL_ADC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32l0xx_hal_adc_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -51,35 +51,82 @@
* @{
*/
-/** @addtogroup ADCEx
+/** @defgroup ADCEx ADCEx
+ * @brief ADC driver modules
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Constants
+/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
* @{
*/
- /** @defgroup ADCEx_TimeOut_Values
+/** @defgroup ADCEx_Channel_Mode ADC Single Ended
+ * @{
+ */
+#define ADC_SINGLE_ENDED (uint32_t)0x00000000 /* dummy value */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_External_trigger_Source ADC External Trigger Source
* @{
- */
-#define ADC_CALIBRATION_TIMEOUT 10
+ */
+#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONV_T21_CC2 (ADC_CFGR1_EXTSEL_0)
+#define ADC_EXTERNALTRIGCONV_T2_TRGO (ADC_CFGR1_EXTSEL_1)
+#define ADC_EXTERNALTRIGCONV_T2_CC4 (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)
+#define ADC_EXTERNALTRIGCONV_T22_TRGO (ADC_CFGR1_EXTSEL_2)
+#define ADC_EXTERNALTRIGCONV_T3_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1)
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)
+#define ADC_SOFTWARE_START (ADC_CFGR1_EXTSEL + (uint32_t)1)
+
+/* ADC group regular external trigger TIM21_TRGO available only on */
+/* STM32L0 devices categories: Cat.2, Cat.3, Cat.5 */
+#if defined (STM32L031xx) || defined (STM32L041xx) || \
+ defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || \
+ defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || \
+ defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \
+ defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define ADC_EXTERNALTRIGCONV_T21_TRGO (ADC_EXTERNALTRIGCONV_T22_TRGO)
+#endif
+
+/* ADC group regular external trigger TIM2_CC3 available only on */
+/* STM32L0 devices categories: Cat.1, Cat.2, Cat.5 */
+#if defined (STM32L011xx) || defined (STM32L021xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || \
+ defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \
+ defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define ADC_EXTERNALTRIGCONV_T2_CC3 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0)
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_SYSCFG_internal_paths_flags_definition ADC SYSCFG internal paths Flags Definition
+ * @{
+ */
+#define ADC_FLAG_SENSOR SYSCFG_CFGR3_SENSOR_ADC_RDYF
+#define ADC_FLAG_VREFINT SYSCFG_VREFINT_ADC_RDYF
/**
* @}
*/
-
-/** @defgroup ADCEx_Channel_Mode
- * @{
- */
-#define ADC_SINGLE_ENDED (uint32_t)0x00000000 /* dummy value */
-#define IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF) ((SING_DIFF) == ADC_SINGLE_ENDED)
/**
* @}
*/
-
-/** @defgroup ADCEx_calibration_factor_length_verification
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macros ADCEx Private Macros
+ * @{
+ */
+
+#define IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF) ((SING_DIFF) == ADC_SINGLE_ENDED)
+
+/** @defgroup ADCEx_calibration_factor_length_verification ADC Calibration Factor Length Verification
* @{
*/
/**
@@ -92,23 +139,75 @@
* @}
*/
-#define ADC_FLAG_SENSOR SYSCFG_CFGR3_SENSOR_ADC_RDYF
-#define ADC_FLAG_VREFINT SYSCFG_VREFINT_ADC_RDYF
+/** @defgroup ADC_External_trigger_Source ADC External Trigger Source
+ * @{
+ */
+#if defined (STM32L031xx) || defined (STM32L041xx) || \
+ defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \
+ defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define IS_ADC_EXTTRIG(CONV) (((CONV) == ADC_EXTERNALTRIGCONV_T6_TRGO ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T21_CC2 ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T2_TRGO ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC4 ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T22_TRGO ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T21_TRGO ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC3 ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T3_TRGO ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_EXT_IT11 ) || \
+ ((CONV) == ADC_SOFTWARE_START))
+#elif defined (STM32L011xx) || defined (STM32L021xx)
+#define IS_ADC_EXTTRIG(CONV) (((CONV) == ADC_EXTERNALTRIGCONV_T6_TRGO ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T21_CC2 ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T2_TRGO ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC4 ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T22_TRGO ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC3 ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T3_TRGO ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_EXT_IT11 ) || \
+ ((CONV) == ADC_SOFTWARE_START))
+#elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || \
+ defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx)
+#define IS_ADC_EXTTRIG(CONV) (((CONV) == ADC_EXTERNALTRIGCONV_T6_TRGO ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T21_CC2 ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T2_TRGO ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC4 ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T22_TRGO ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T21_TRGO ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_T3_TRGO ) || \
+ ((CONV) == ADC_EXTERNALTRIGCONV_EXT_IT11 ) || \
+ ((CONV) == ADC_SOFTWARE_START))
+#endif
+/**
+ * @}
+ */
/**
* @}
*/
-
+
+/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
/* Exported functions --------------------------------------------------------*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
-void HAL_ADCEx_EnableVREFINT(void);
-void HAL_ADCEx_DisableVREFINT(void);
-void HAL_ADCEx_EnableVREFINTTempSensor(void);
-void HAL_ADCEx_DisableVREFINTTempSensor(void);
+HAL_StatusTypeDef HAL_ADCEx_EnableVREFINT(void);
+void HAL_ADCEx_DisableVREFINT(void);
+HAL_StatusTypeDef HAL_ADCEx_EnableVREFINTTempSensor(void);
+void HAL_ADCEx_DisableVREFINTTempSensor(void);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_comp.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief COMP HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -101,7 +101,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -135,18 +135,31 @@
* @{
*/
+#ifdef HAL_COMP_MODULE_ENABLED
+
/** @addtogroup COMP
* @brief COMP HAL module driver
* @{
*/
-#ifdef HAL_COMP_MODULE_ENABLED
-
+/** @addtogroup COMP_Private
+ * @{
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* CSR register reset value */
#define COMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
+#define C_REV_ID_A 0x1000 //Cut1.0
+#define C_REV_ID_Z 0x1008 //Cut1.1
+#define C_REV_ID_Y 0x1003 //Cut1.2
+
+#define C_DEV_ID_L073 0x447
+#define C_DEV_ID_L053 0x417
+/**
+ * @}
+ */
+
/** @addtogroup COMP_Exported_Functions
* @{
@@ -157,7 +170,7 @@
*
@verbatim
===============================================================================
- ##### Initialization/de-initialization functions #####
+ ##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions to initialize and de-initialize comparators
@@ -190,7 +203,6 @@
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput));
assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput));
- assert_param(IS_COMP_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
assert_param(IS_COMP_MODE(hcomp->Init.Mode));
@@ -202,6 +214,8 @@
if(hcomp->State == HAL_COMP_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hcomp->Lock = HAL_UNLOCKED;
/* Init SYSCFG and the low level hardware to access comparators */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Init the low level hardware : SYSCFG to access comparators */
@@ -211,21 +225,103 @@
/* Change COMP peripheral state */
hcomp->State = HAL_COMP_STATE_BUSY;
- /* Set COMP parameters */
- /* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */
- /* Set COMPxNONINSEL bits according to hcomp->Init.NonInvertingInput value */
- /* Set COMPxPOL bit according to hcomp->Init.OutputPol value */
- /* Set COMPxMODE bits according to hcomp->Init.Mode value */
- /* Set COMP1WM bit according to hcomp->Init.WindowMode value */
- MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \
- hcomp->Init.InvertingInput | \
- hcomp->Init.NonInvertingInput | \
- hcomp->Init.LPTIMConnection | \
- hcomp->Init.OutputPol | \
- hcomp->Init.Mode | \
- hcomp->Init.WindowMode);
+ /* Set COMP parameters */
+ /* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */
+ /* Set COMPxNONINSEL bits according to hcomp->Init.NonInvertingInput value */
+ /* Set COMPxLPTIMCONNECTION bits according to hcomp->Init.LPTIMConnection value */
+ /* Set COMPxPOL bit according to hcomp->Init.OutputPol value */
+ /* Set COMPxMODE bits according to hcomp->Init.Mode value */
+ /* Set COMP1WM bit according to hcomp->Init.WindowMode value */
-
+ /* No LPTIM connexion requested */
+ if (hcomp->Init.LPTIMConnection == COMP_LPTIMCONNECTION_DISABLED)
+ {
+ MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \
+ hcomp->Init.InvertingInput | \
+ hcomp->Init.NonInvertingInput | \
+ hcomp->Init.OutputPol | \
+ hcomp->Init.Mode | \
+ hcomp->Init.WindowMode);
+ }
+ else
+ {
+ /* LPTIM connexion requested on COMP2*/
+ if ((hcomp->Instance) == COMP2)
+ {
+ /* Check the MCU_ID in order to allow or not the COMP2 connection to LPTIM-input2 */
+ if (((HAL_GetDEVID() == C_DEV_ID_L073) && (HAL_GetREVID() == C_REV_ID_A))
+ ||
+ ((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_A))
+ ||
+ ((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_Z)))
+ {
+ /* Note : COMP2 can be connected only to input 1 of LPTIM if requested */
+ assert_param(IS_COMP2_LPTIMCONNECTION_RESTRICTED(hcomp->Init.LPTIMConnection));
+ MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \
+ hcomp->Init.InvertingInput | \
+ hcomp->Init.NonInvertingInput | \
+ COMP_CSR_COMP2LPTIM1IN1 | \
+ hcomp->Init.OutputPol | \
+ hcomp->Init.Mode | \
+ hcomp->Init.WindowMode);
+ }
+ else
+ {
+ /* Note : COMP2 can be connected to input 1 or input2 of LPTIM if requested */
+ assert_param(IS_COMP2_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
+ switch (hcomp->Init.LPTIMConnection)
+ {
+ case COMP_LPTIMCONNECTION_IN1_ENABLED :
+ MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \
+ hcomp->Init.InvertingInput | \
+ hcomp->Init.NonInvertingInput | \
+ COMP_CSR_COMP2LPTIM1IN1 | \
+ hcomp->Init.OutputPol | \
+ hcomp->Init.Mode | \
+ hcomp->Init.WindowMode);
+ break;
+ case COMP_LPTIMCONNECTION_IN2_ENABLED :
+ MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \
+ hcomp->Init.InvertingInput | \
+ hcomp->Init.NonInvertingInput | \
+ COMP_CSR_COMP2LPTIM1IN2 | \
+ hcomp->Init.OutputPol | \
+ hcomp->Init.Mode | \
+ hcomp->Init.WindowMode);
+ break;
+ default :
+ MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \
+ hcomp->Init.InvertingInput | \
+ hcomp->Init.NonInvertingInput | \
+ hcomp->Init.OutputPol | \
+ hcomp->Init.Mode | \
+ hcomp->Init.WindowMode);
+ break;
+ }
+ }
+ }
+ else
+ /* LPTIM connexion requested on COMP1 */
+ {
+ /* Note : COMP1 can be connected to the input 1 of LPTIM if requested */
+ assert_param(IS_COMP1_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
+ if (hcomp->Init.LPTIMConnection == COMP_LPTIMCONNECTION_IN1_ENABLED)
+ MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \
+ hcomp->Init.InvertingInput | \
+ hcomp->Init.NonInvertingInput | \
+ COMP_CSR_COMP1LPTIM1IN1 | \
+ hcomp->Init.OutputPol | \
+ hcomp->Init.Mode | \
+ hcomp->Init.WindowMode);
+ else
+ MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \
+ hcomp->Init.InvertingInput | \
+ hcomp->Init.NonInvertingInput | \
+ hcomp->Init.OutputPol | \
+ hcomp->Init.Mode | \
+ hcomp->Init.WindowMode);
+ }
+ }
/* Initialize the COMP state*/
hcomp->State = HAL_COMP_STATE_READY;
@@ -277,6 +373,9 @@
*/
__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcomp);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_COMP_MspInit could be implenetd in the user file
*/
@@ -289,6 +388,9 @@
*/
__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcomp);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_COMP_MspDeInit could be implenetd in the user file
*/
@@ -321,6 +423,7 @@
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
{
HAL_StatusTypeDef status = HAL_OK;
+ uint32_t extiline = 0;
/* Check the COMP handle allocation and lock status */
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00))
@@ -334,6 +437,69 @@
if(hcomp->State == HAL_COMP_STATE_READY)
{
+ /* Check the Exti Line output configuration */
+ extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
+
+ /* Configure the rising edge */
+ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_RISING) != 0x0)
+ {
+ if (extiline == COMP_EXTI_LINE_COMP1)
+ {
+ __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE();
+ }
+ else
+ {
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE();
+ }
+ }
+ else
+ {
+ if (extiline == COMP_EXTI_LINE_COMP1)
+ {
+ __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE();
+ }
+ else
+ {
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE();
+ }
+ }
+
+ /* Configure the falling edge */
+ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_FALLING) != 0x0)
+ {
+ if (extiline == COMP_EXTI_LINE_COMP1)
+ {
+ __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE();
+ }
+ else
+ {
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE();
+ }
+ }
+ else
+ {
+ if (extiline == COMP_EXTI_LINE_COMP1)
+ {
+ __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE();
+ }
+ else
+ {
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE();
+ }
+ }
+
+ /* Configure the COMP module */
+ if (extiline == COMP_EXTI_LINE_COMP1)
+ {
+ /* Clear COMP Exti pending bit */
+ __HAL_COMP_COMP1_EXTI_CLEAR_FLAG();
+ }
+ else
+ {
+ /* Clear COMP Exti pending bit */
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG();
+ }
+
/* Enable the selected comparator */
__HAL_COMP_ENABLE(hcomp);
@@ -393,72 +559,93 @@
HAL_StatusTypeDef status = HAL_OK;
uint32_t extiline = 0;
- status = HAL_COMP_Start(hcomp);
- if(status == HAL_OK)
+ /* Check the COMP handle allocation and lock status */
+ if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00))
{
- /* Check the Exti Line output configuration */
- extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
-
- /* Configure the rising edge */
- if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != 0x00)
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ if(hcomp->State == HAL_COMP_STATE_READY)
{
- if (extiline == COMP_EXTI_LINE_COMP1)
- {
- __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE();
- }
- else
- {
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE();
- }
+ /* Check the Exti Line output configuration */
+ extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
+
+ /* Configure the rising edge */
+ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != 0x0)
+ {
+ if (extiline == COMP_EXTI_LINE_COMP1)
+ {
+ __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE();
+ }
+ else
+ {
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE();
+ }
+ }
+ else
+ {
+ if (extiline == COMP_EXTI_LINE_COMP1)
+ {
+ __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE();
+ }
+ else
+ {
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE();
+ }
+ }
+
+ /* Configure the falling edge */
+ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != 0x0)
+ {
+ if (extiline == COMP_EXTI_LINE_COMP1)
+ {
+ __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE();
+ }
+ else
+ {
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE();
+ }
+ }
+ else
+ {
+ if (extiline == COMP_EXTI_LINE_COMP1)
+ {
+ __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE();
+ }
+ else
+ {
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE();
+ }
+ }
+
+ /* Configure the COMP module */
+ if (extiline == COMP_EXTI_LINE_COMP1)
+ {
+ /* Clear COMP Exti pending bit */
+ __HAL_COMP_COMP1_EXTI_CLEAR_FLAG();
+ /* Enable Exti interrupt mode */
+ __HAL_COMP_COMP1_EXTI_ENABLE_IT();
+ }
+ else
+ {
+ /* Clear COMP Exti pending bit */
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG();
+ /* Enable Exti interrupt mode */
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT();
+ }
+
+ /* Enable the selected comparator */
+ __HAL_COMP_ENABLE(hcomp);
+
+ hcomp->State = HAL_COMP_STATE_BUSY;
}
else
{
- if (extiline == COMP_EXTI_LINE_COMP1)
- {
- __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE();
- }
- else
- {
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE();
- }
- }
-
- /* Configure the falling edge */
- if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != 0x00)
- {
- if (extiline == COMP_EXTI_LINE_COMP1)
- {
- __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE();
- }
- else
- {
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE();
- }
- }
- else
- {
- if (extiline == COMP_EXTI_LINE_COMP1)
- {
- __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE();
- }
- else
- {
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE();
- }
- }
-
- if (extiline == COMP_EXTI_LINE_COMP1)
- {
- /* Clear COMP Exti pending bit */
- __HAL_COMP_COMP1_EXTI_CLEAR_FLAG();
- /* Enable Exti interrupt mode */
- __HAL_COMP_COMP1_EXTI_ENABLE_IT();
- } else
- {
- /* Clear COMP Exti pending bit */
- __HAL_COMP_COMP2_EXTI_CLEAR_FLAG();
- /* Enable Exti interrupt mode */
- __HAL_COMP_COMP2_EXTI_ENABLE_IT();
+ status = HAL_ERROR;
}
}
@@ -495,22 +682,32 @@
*/
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
{
-
- /* Check COMP Exti flag */
+ /* Check which exti line is involved */
+ uint32_t extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
- if(__HAL_COMP_COMP1_EXTI_GET_FLAG() != RESET)
- {
- /* Clear COMP Exti pending bit */
- __HAL_COMP_COMP1_EXTI_CLEAR_FLAG();
- }
- if(__HAL_COMP_COMP2_EXTI_GET_FLAG() != RESET)
- {
- /* Clear COMP Exti pending bit */
- __HAL_COMP_COMP2_EXTI_CLEAR_FLAG();
- }
-
- /* COMP trigger user callback */
- HAL_COMP_TriggerCallback(hcomp);
+ /* Manage COMP1 Exti line */
+ if (extiline == COMP_EXTI_LINE_COMP1)
+ {
+ if(__HAL_COMP_COMP1_EXTI_GET_FLAG() != RESET)
+ {
+ /* Clear COMP Exti pending bit */
+ __HAL_COMP_COMP1_EXTI_CLEAR_FLAG();
+ /* COMP trigger user callback */
+ HAL_COMP_TriggerCallback(hcomp);
+ }
+ }
+
+ /* Manage COMP2 Exti line */
+ if (extiline == COMP_EXTI_LINE_COMP2)
+ {
+ if(__HAL_COMP_COMP2_EXTI_GET_FLAG() != RESET)
+ {
+ /* Clear COMP Exti pending bit */
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG();
+ /* COMP trigger user callback */
+ HAL_COMP_TriggerCallback(hcomp);
+ }
+ }
}
/**
@@ -608,6 +805,9 @@
*/
__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcomp);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_COMP_TriggerCallback should be implemented in the user file
*/
@@ -661,11 +861,12 @@
* @}
*/
-#endif /* HAL_COMP_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_COMP_MODULE_ENABLED */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_comp.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -86,7 +86,7 @@
to adjust the speed/consumption.
This parameter can be a value of @ref COMP_Mode */
- uint32_t WindowMode; /*!< Selects the window mode of the comparator 2.
+ uint32_t WindowMode; /*!< Selects the window mode of the comparator.
This parameter can be a value of @ref COMP_WindowMode */
uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator (interrupt mode).
@@ -194,18 +194,16 @@
#define COMP_NONINVERTINGINPUT_IO3 ((uint32_t)0x00000200) /*!< I/O3 (PB5) connected to comparator non inverting input */
#define COMP_NONINVERTINGINPUT_IO4 ((uint32_t)0x00000300) /*!< I/O1 (PB6) connected to comparator non inverting input */
#define COMP_NONINVERTINGINPUT_IO5 ((uint32_t)0x00000400) /*!< I/O3 (PB7) connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_IO6 ((uint32_t)0x00000500) /*!< I/O3 (PB7) connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_IO7 ((uint32_t)0x00000600) /*!< I/O3 (PB7) connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_IO8 ((uint32_t)0x00000700) /*!< I/O3 (PB7) connected to comparator non inverting input */
+#define COMP_NONINVERTINGINPUT_IO6 ((uint32_t)0x00000500) /*!< I/O3 (PA7) connected to comparator non inverting input */
+#define COMP_NONINVERTINGINPUT_IO7 ((uint32_t)0x00000600) /*!< Reserved */
+#define COMP_NONINVERTINGINPUT_IO8 ((uint32_t)0x00000700) /*!< Reserved */
#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
((INPUT) == COMP_NONINVERTINGINPUT_IO2) || \
((INPUT) == COMP_NONINVERTINGINPUT_IO3) || \
((INPUT) == COMP_NONINVERTINGINPUT_IO4) || \
((INPUT) == COMP_NONINVERTINGINPUT_IO5) || \
- ((INPUT) == COMP_NONINVERTINGINPUT_IO6) || \
- ((INPUT) == COMP_NONINVERTINGINPUT_IO7) || \
- ((INPUT) == COMP_NONINVERTINGINPUT_IO8))
+ ((INPUT) == COMP_NONINVERTINGINPUT_IO6))
/**
* @}
*/
@@ -233,12 +231,8 @@
#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))
-#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
-#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) ||\
- ((INSTANCE) == COMP2))
-#else
#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
-#endif
+
/**
* @}
*/
@@ -246,11 +240,20 @@
/** @defgroup COMP_LPTIMConnection COMP Low power timer connection definition
* @{
*/
-#define COMP_LPTIMCONNECTION_DISABLED ((uint32_t)0x00000000) /*!< COMPx signal is gated */
-#define COMP_LPTIMCONNECTION_ENABLED COMP_CSR_COMP1LPTIM1IN1 /*!< COMPx signal is connected to LPTIM */
-#define IS_COMP_LPTIMCONNECTION(LPTIMCONNECTION) (((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_DISABLED) || \
- ((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_ENABLED))
+
+#define COMP_LPTIMCONNECTION_DISABLED ((uint32_t)0x00000000) /*!< COMPx signal is gated */
+#define COMP_LPTIMCONNECTION_IN1_ENABLED ((uint32_t)0x00000001) /*!< COMPx signal is connected to LPTIM input 1 */
+#define COMP_LPTIMCONNECTION_IN2_ENABLED ((uint32_t)0x00000002) /*!< COMPx signal is connected to LPTIM input 2 */
+#define IS_COMP1_LPTIMCONNECTION(LPTIMCONNECTION) (((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_DISABLED) || \
+ ((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN1_ENABLED))
+
+#define IS_COMP2_LPTIMCONNECTION(LPTIMCONNECTION) (((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_DISABLED) || \
+ ((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN1_ENABLED) || \
+ ((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN2_ENABLED))
+
+#define IS_COMP2_LPTIMCONNECTION_RESTRICTED(LPTIMCONNECTION) (((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_DISABLED) || \
+ ((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN2_ENABLED))
/**
* @}
*/
@@ -279,12 +282,15 @@
/** @defgroup COMP_TriggerMode COMP trigger mode definition
* @{
*/
+#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000) /*!< No External Interrupt trigger detection */
#define COMP_TRIGGERMODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
#define COMP_TRIGGERMODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
#define COMP_TRIGGERMODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define IS_COMP_TRIGGERMODE(MODE) (((MODE) == COMP_TRIGGERMODE_IT_RISING) || \
- ((MODE) == COMP_TRIGGERMODE_IT_FALLING) || \
- ((MODE) == COMP_TRIGGERMODE_IT_RISING_FALLING))
+
+#define COMP_TRIGGERMODE_EVENT_RISING ((uint32_t)0x00000010) /*!< Event Mode with Rising edge trigger detection */
+#define COMP_TRIGGERMODE_EVENT_FALLING ((uint32_t)0x00000020) /*!< Event Mode with Falling edge trigger detection */
+#define COMP_TRIGGERMODE_EVENT_RISING_FALLING ((uint32_t)0x00000030) /*!< Event Mode with Rising/Falling edge trigger detection */
+
/**
* @}
*/
@@ -293,8 +299,8 @@
* @{
*/
-#define COMP_EXTI_LINE_COMP2 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to COMP2 */
-#define COMP_EXTI_LINE_COMP1 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to COMP1 */
+#define COMP_EXTI_LINE_COMP2 (EXTI_IMR_IM22) /*!< External interrupt line 22 Connected to COMP2 */
+#define COMP_EXTI_LINE_COMP1 (EXTI_IMR_IM21) /*!< External interrupt line 21 Connected to COMP1 */
/**
@@ -310,7 +316,7 @@
* @retval None
*/
-/** @defgroup COMP_Exported_Macro COMP Exported Macro
+/** @defgroup COMP_Exported_Macro COMP Exported Macros
* @{
*/
/**
@@ -539,6 +545,16 @@
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup COMP_Private COMP Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp_ex.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp_ex.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_comp_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Extended COMP HAL module driver.
* @brief This file provides firmware functions to manage the VREFINT
* which can act as input to the comparator.
@@ -23,7 +23,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -57,14 +57,13 @@
* @{
*/
+#ifdef HAL_COMP_MODULE_ENABLED
+
/** @addtogroup COMPEx
* @brief Extended COMP HAL module driver
* @{
*/
-#ifdef HAL_COMP_MODULE_ENABLED
-
-
/** @addtogroup COMPEx_Exported_Functions
* @{
*/
@@ -108,12 +107,12 @@
* @}
*/
-
-#endif /* HAL_COMP_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_COMP_MODULE_ENABLED */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_comp_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of COMP HAL Extended module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,7 +55,7 @@
*/
/* Exported functions --------------------------------------------------------*/
-/** @defgroup COMPEx_Exported_Functions COMP Extended Exported Functions
+/** @defgroup COMPEx_Exported_Functions COMPEx Exported Functions
* @{
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cortex.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cortex.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_cortex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@@ -48,10 +48,10 @@
(++) Enables the SysTick Interrupt.
(++) Starts the SysTick Counter.
- (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
- __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
- HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
- inside the stm32l0xx_hal_cortex.h file.
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function
+ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+ HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() function is defined
+ inside the stm32l0xx_hal_cortex.c file.
(+) You can change the SysTick IRQ priority by calling the
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
@@ -67,7 +67,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -101,13 +101,13 @@
* @{
*/
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
/** @addtogroup CORTEX
* @brief CORTEX HAL module driver
* @{
*/
-#ifdef HAL_CORTEX_MODULE_ENABLED
-
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
@@ -191,7 +191,6 @@
/**
* @brief Initiates a system reset request to reset the MCU.
- * @param None
* @retval None
*/
void HAL_NVIC_SystemReset(void)
@@ -232,11 +231,23 @@
*/
+/**
+ * @brief Gets the priority of an interrupt.
+ * @param IRQn: External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l0xxxx.h))
+ * @retval None
+ */
+uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
+{
+ /* Get priority for Cortex-M system or device specific interrupts */
+ return NVIC_GetPriority(IRQn);
+}
/**
* @brief Sets Pending bit of an external interrupt.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
+ * @param IRQn: External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
* @retval None
*/
@@ -249,7 +260,7 @@
/**
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
* and returns the pending bit for the specified interrupt).
- * @param IRQn External interrupt number .
+ * @param IRQn: External interrupt number .
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
* @retval status: - 0 Interrupt status is not pending.
@@ -263,8 +274,8 @@
/**
* @brief Clears the pending bit of an external interrupt.
- * @param IRQn External interrupt number .
- * This parameter can be an enumerator of IRQn_Type enumeration
+ * @param IRQn: External interrupt number .
+ * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
* @retval None
*/
@@ -299,7 +310,6 @@
/**
* @brief This function handles SYSTICK interrupt request.
- * @param None
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
@@ -309,7 +319,6 @@
/**
* @brief SYSTICK callback.
- * @param None
* @retval None
*/
__weak void HAL_SYSTICK_Callback(void)
@@ -319,6 +328,59 @@
*/
}
+#if (__MPU_PRESENT == 1)
+/**
+ * @brief Initialize and configure the Region and the memory to be protected.
+ * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+ assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+ /* Set the Region number */
+ MPU->RNR = MPU_Init->Number;
+
+ if ((MPU_Init->Enable) == MPU_REGION_ENABLE)
+ {
+ /* Check the parameters */
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+ /* Set the base adsress and set the 4 LSB to 0 */
+ MPU->RBAR = (MPU_Init->BaseAddress) & 0xfffffff0;
+
+ /* Fill the field RASR */
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
+ }
+ else
+ {
+ MPU->RBAR = 0x00;
+ MPU->RASR = 0x00;
+ }
+}
+#endif /* __MPU_PRESENT */
+
+
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -332,9 +394,5 @@
* @}
*/
-/**
- * @}
- */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cortex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cortex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_cortex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,9 +54,54 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
+
+ uint8_t Enable; /*!< Specifies the status of the region.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
+ uint8_t Number; /*!< Specifies the number of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */
+
+ uint8_t Size; /*!< Specifies the size of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Size */
+ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint8_t TypeExtField; /*!< This parameter is NOT used but is kept to keep API unified through all families*/
+
+ uint8_t AccessPermission; /*!< Specifies the region access permission type.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
+ uint8_t DisableExec; /*!< Specifies the instruction access status.
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
+}MPU_Region_InitTypeDef;
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported constants
+/** @defgroup CORTEX_Exported_Constants CORTEx Exported Constants
* @{
*/
@@ -65,7 +110,7 @@
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
-/** @defgroup CORTEX_SysTick_clock_source
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick Clock Source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
@@ -75,36 +120,133 @@
/**
* @}
*/
-
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
+ * @{
+ */
+#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
+#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
+#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
+#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+ * @{
+ */
+#define MPU_REGION_ENABLE ((uint8_t)0x01)
+#define MPU_REGION_DISABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+ * @{
+ */
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+ * @{
+ */
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+ * @{
+ */
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+ * @{
+ */
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+ * @{
+ */
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+ * @{
+ */
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+ * @{
+ */
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+
/**
* @}
*/
-/* Exported Macros -----------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
- * @{
- */
-/** @brief Configures the SysTick clock source.
- * @param __CLKSRC__ : specifies the SysTick clock source.
- * This parameter can be one of the following values:
- * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
- * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
- * @retval None
- */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \
- do { \
- if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \
- { \
- SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \
- } \
- else \
- SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \
- } while(0)
-
-/**
- * @}
- */
-
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
@@ -119,6 +261,43 @@
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+#if (__MPU_PRESENT == 1)
+/**
+ * @brief Disable the MPU.
+ * @retval None
+ */
+__STATIC_INLINE void HAL_MPU_Disable(void)
+{
+
+ /*Data Memory Barrier setup */
+ __DMB();
+ /* Disable the MPU */
+ MPU->CTRL = 0;
+}
+
+/**
+ * @brief Enable the MPU.
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged access to the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+
+__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+ /* Data Synchronization Barrier setup */
+ __DSB();
+ /* Instruction Synchronization Barrier setup */
+ __ISB();
+
+}
+#endif /* __MPU_PRESENT */
/**
* @}
*/
@@ -127,13 +306,17 @@
* @brief Cortex control functions
* @{
*/
+
+uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
-
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
/**
* @}
*/
@@ -141,7 +324,81 @@
/**
* @}
*/
-
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+ ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RW) || \
+ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+ ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RO) || \
+ ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
+ ((NUMBER) == MPU_REGION_NUMBER1) || \
+ ((NUMBER) == MPU_REGION_NUMBER2) || \
+ ((NUMBER) == MPU_REGION_NUMBER3) || \
+ ((NUMBER) == MPU_REGION_NUMBER4) || \
+ ((NUMBER) == MPU_REGION_NUMBER5) || \
+ ((NUMBER) == MPU_REGION_NUMBER6) || \
+ ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \
+ ((SIZE) == MPU_REGION_SIZE_512B) || \
+ ((SIZE) == MPU_REGION_SIZE_1KB) || \
+ ((SIZE) == MPU_REGION_SIZE_2KB) || \
+ ((SIZE) == MPU_REGION_SIZE_4KB) || \
+ ((SIZE) == MPU_REGION_SIZE_8KB) || \
+ ((SIZE) == MPU_REGION_SIZE_16KB) || \
+ ((SIZE) == MPU_REGION_SIZE_32KB) || \
+ ((SIZE) == MPU_REGION_SIZE_64KB) || \
+ ((SIZE) == MPU_REGION_SIZE_128KB) || \
+ ((SIZE) == MPU_REGION_SIZE_256KB) || \
+ ((SIZE) == MPU_REGION_SIZE_512KB) || \
+ ((SIZE) == MPU_REGION_SIZE_1MB) || \
+ ((SIZE) == MPU_REGION_SIZE_2MB) || \
+ ((SIZE) == MPU_REGION_SIZE_4MB) || \
+ ((SIZE) == MPU_REGION_SIZE_8MB) || \
+ ((SIZE) == MPU_REGION_SIZE_16MB) || \
+ ((SIZE) == MPU_REGION_SIZE_32MB) || \
+ ((SIZE) == MPU_REGION_SIZE_64MB) || \
+ ((SIZE) == MPU_REGION_SIZE_128MB) || \
+ ((SIZE) == MPU_REGION_SIZE_256MB) || \
+ ((SIZE) == MPU_REGION_SIZE_512MB) || \
+ ((SIZE) == MPU_REGION_SIZE_1GB) || \
+ ((SIZE) == MPU_REGION_SIZE_2GB) || \
+ ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+
+/**
+ * @}
+ */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_crc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief CRC HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -38,7 +38,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -72,13 +72,16 @@
* @{
*/
+#ifdef HAL_CRC_MODULE_ENABLED
+
/** @addtogroup CRC
* @brief CRC HAL module driver
* @{
*/
-#ifdef HAL_CRC_MODULE_ENABLED
-
+/** @addtogroup CRC_Private
+ * @{
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -86,6 +89,9 @@
/* Private function prototypes -----------------------------------------------*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CRC_Exported_Functions
@@ -156,6 +162,7 @@
else
{
/* initialize CRC IP with generating polynomial defined by user */
+ assert_param(IS_CRC_POL_LENGTH(hcrc->Init.CRCLength));
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
{
return HAL_ERROR;
@@ -242,6 +249,9 @@
*/
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcrc);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspInit can be implemented in the user file
*/
@@ -254,6 +264,9 @@
*/
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcrc);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspDeInit can be implemented in the user file
*/
@@ -291,7 +304,13 @@
* @param hcrc: CRC handle
* @param pBuffer: pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
- * @param BufferLength: input data buffer length
+ * @param BufferLength: input data buffer length (number of bytes if pBuffer
+ * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+ * number of words if pBuffer type is * uint32_t).
+ * @note By default, the API expects a uint32_t pointer as input buffer parameter.
+ * Input buffer pointers with other types simply need to be cast in uint32_t
+ * and the API will internally adjust its input data processing based on the
+ * handle field hcrc->InputDataFormat.
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
@@ -344,7 +363,13 @@
* @param hcrc: CRC handle
* @param pBuffer: pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
- * @param BufferLength: input data buffer length
+ * @param BufferLength: input data buffer length (number of bytes if pBuffer
+ * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+ * number of words if pBuffer type is * uint32_t).
+ * @note By default, the API expects a uint32_t pointer as input buffer parameter.
+ * Input buffer pointers with other types simply need to be cast in uint32_t
+ * and the API will internally adjust its input data processing based on the
+ * handle field hcrc->InputDataFormat.
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
@@ -397,85 +422,18 @@
}
-/**
- * @brief Enter 8-bit input data to the CRC calculator.
- * Specific data handling to optimize processing time.
- * @param hcrc: CRC handle
- * @param pBuffer: pointer to the input data buffer
- * @param BufferLength: input data buffer length
- * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
- */
-static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t i = 0; /* input data buffer index */
-
- /* Processing time optimization: 4 bytes are entered in a row with a single word write,
- * last bytes must be carefully fed to the CRC calculator to ensure a correct type
- * handling by the IP */
- for(i = 0; i < (BufferLength/4); i++)
- {
- hcrc->Instance->DR = (pBuffer[4*i]<<24) | (pBuffer[4*i+1]<<16) | (pBuffer[4*i+2]<<8) | pBuffer[4*i+3];
- }
- /* last bytes specific handling */
- if ((BufferLength%4) != 0)
- {
- if (BufferLength%4 == 1)
- {
- *(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];
- }
- if (BufferLength%4 == 2)
- {
- *(uint16_t*) (&hcrc->Instance->DR) = (pBuffer[4*i]<<8) | pBuffer[4*i+1];
- }
- if (BufferLength%4 == 3)
- {
- *(uint16_t*) (&hcrc->Instance->DR) = (pBuffer[4*i]<<8) | pBuffer[4*i+1];
- *(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
- }
- }
-
- /* Return the CRC computed value */
- return hcrc->Instance->DR;
-}
-/**
- * @brief Enter 16-bit input data to the CRC calculator.
- * Specific data handling to optimize processing time.
- * @param hcrc: CRC handle
- * @param pBuffer: pointer to the input data buffer
- * @param BufferLength: input data buffer length
- * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
- */
-static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t i = 0; /* input data buffer index */
-
- /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
- * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
- * a correct type handling by the IP */
- for(i = 0; i < (BufferLength/2); i++)
- {
- hcrc->Instance->DR = (pBuffer[2*i]<<16) | pBuffer[2*i+1];
- }
- if ((BufferLength%2) != 0)
- {
- *(uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i];
- }
-
- /* Return the CRC computed value */
- return hcrc->Instance->DR;
-}
/**
* @}
*/
/** @addtogroup CRC_Exported_Functions_Group3
- * @brief Peripheral State functions.
+ * @brief Peripheral State functions.
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@@ -501,7 +459,77 @@
* @}
*/
-#endif /* HAL_CRC_MODULE_ENABLED */
+/** @addtogroup CRC_Private
+ * @{
+ */
+/**
+ * @brief Enter 8-bit input data to the CRC calculator.
+ * Specific data handling to optimize processing time.
+ * @param hcrc: CRC handle
+ * @param pBuffer: pointer to the input data buffer
+ * @param BufferLength: input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t i = 0; /* input data buffer index */
+
+ /* Processing time optimization: 4 bytes are entered in a row with a single word write,
+ * last bytes must be carefully fed to the CRC calculator to ensure a correct type
+ * handling by the IP */
+ for(i = 0; i < (BufferLength/4); i++)
+ {
+ hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3];
+ }
+ /* last bytes specific handling */
+ if ((BufferLength%4) != 0)
+ {
+ if (BufferLength%4 == 1)
+ {
+ *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i];
+ }
+ if (BufferLength%4 == 2)
+ {
+ *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
+ }
+ if (BufferLength%4 == 3)
+ {
+ *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
+ *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
+ }
+ }
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+/**
+ * @brief Enter 16-bit input data to the CRC calculator.
+ * Specific data handling to optimize processing time.
+ * @param hcrc: CRC handle
+ * @param pBuffer: pointer to the input data buffer
+ * @param BufferLength: input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t i = 0; /* input data buffer index */
+
+ /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
+ * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
+ * a correct type handling by the IP */
+ for(i = 0; i < (BufferLength/2); i++)
+ {
+ hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1];
+ }
+ if ((BufferLength%2) != 0)
+ {
+ *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i];
+ }
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
/**
* @}
@@ -511,5 +539,11 @@
* @}
*/
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_crc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,6 +54,9 @@
* @{
*/
+ /** @defgroup CRC_Exported_Types CRC Exported Types
+ * @{
+ */
/* Exported types ------------------------------------------------------------*/
/**
@@ -136,8 +139,12 @@
must occur if InputBufferFormat is not one of the three values listed above */
}CRC_HandleTypeDef;
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRC_Exported_Constants CRC exported constants
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
* @{
*/
@@ -165,9 +172,6 @@
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)
-#define IS_DEFAULT_POLYNOMIAL(__DEFAULT__) (((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || \
- ((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE))
-
/**
* @}
*/
@@ -178,8 +182,6 @@
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00)
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01)
-#define IS_DEFAULT_INIT_VALUE(__VALUE__) (((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || \
- ((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE))
/**
* @}
@@ -192,10 +194,6 @@
#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
-#define IS_CRC_POL_LENGTH(__LENGTH__) (((__LENGTH__) == CRC_POLYLENGTH_32B) || \
- ((__LENGTH__) == CRC_POLYLENGTH_16B) || \
- ((__LENGTH__) == CRC_POLYLENGTH_8B) || \
- ((__LENGTH__) == CRC_POLYLENGTH_7B))
/**
* @}
*/
@@ -224,9 +222,6 @@
#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002)
#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003)
-#define IS_CRC_INPUTDATA_FORMAT(__FORMAT__) (((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || \
- ((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
- ((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS))
/**
* @}
*/
@@ -236,7 +231,7 @@
*/
/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CRC_Exported_Macros CRC exported macros
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
* @{
*/
@@ -267,7 +262,7 @@
* @param __VALUE__: 8-bit value to be stored in the ID register
* @retval None
*/
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/**
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.
@@ -279,10 +274,47 @@
* @}
*/
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRC_Private_Macros CRC Private Macros
+ * @{
+ */
+#define IS_DEFAULT_POLYNOMIAL(__DEFAULT__) (((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || \
+ ((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE))
+
+
+#define IS_DEFAULT_INIT_VALUE(__VALUE__) (((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || \
+ ((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE))
+
+#define IS_CRC_POL_LENGTH(__LENGTH__) (((__LENGTH__) == CRC_POLYLENGTH_32B) || \
+ ((__LENGTH__) == CRC_POLYLENGTH_16B) || \
+ ((__LENGTH__) == CRC_POLYLENGTH_8B) || \
+ ((__LENGTH__) == CRC_POLYLENGTH_7B))
+
+
+#define IS_CRC_INPUTDATA_FORMAT(__FORMAT__) (((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || \
+ ((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
+ ((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS))
+
+/**
+ * @}
+ */
+
/* Include CRC HAL Extension module */
#include "stm32l0xx_hal_crc_ex.h"
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
+ * @{
+ */
+
+/* Aliases for inter STM32 series compatibility */
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
+
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
@@ -300,10 +332,6 @@
* @}
*/
-/* Aliases for inter STM32 series compatibility */
-#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
-#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
-
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
@@ -327,6 +355,16 @@
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup CRC_Private CRC Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc_ex.c Sun Apr 17 17:45:10 2016 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc_ex.c Tue Apr 19 11:15:15 2016 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.2.0 - * @date 06-February-2015 + * @version V1.5.0 + * @date 8-January-2016 * @brief Extended CRC HAL module driver. * * This file provides firmware functions to manage the following @@ -23,7 +23,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_crc_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of CRC HAL extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -57,7 +57,7 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRCEx_Exported_Constants CRC Extended exported constants
+/** @defgroup CRCEx_Exported_Constants CRCEx Exported constants
* @{
*/
@@ -69,10 +69,6 @@
#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
-#define IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || \
- ((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || \
- ((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
- ((__MODE__) == CRC_INPUTDATA_INVERSION_WORD))
/**
* @}
*/
@@ -82,9 +78,6 @@
*/
#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000)
#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)
-
-#define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
- ((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE))
/**
* @}
*/
@@ -95,7 +88,7 @@
*/
/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CRCEx_Exported_Macros CRC Extended exported macros
+/** @defgroup CRCEx_Exported_Macros CRCEx Exported Macros
* @{
*/
@@ -125,8 +118,23 @@
* @}
*/
+/** @defgroup CRCEx_Private_Macros CRCEx Private Macros
+ * @{
+ */
+
+#define IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || \
+ ((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || \
+ ((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
+ ((__MODE__) == CRC_INPUTDATA_INVERSION_WORD))
+
-/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
+ ((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE))
+
+/**
+ * @}
+ */
+/** @defgroup CRCEx_Exported_Functions CRCEx Exported Functions
* @{
*/
@@ -150,7 +158,6 @@
* @}
*/
-
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_cryp.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief CRYP HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -97,7 +97,7 @@
******************************************************************************
*/
-#if defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal.h"
@@ -106,7 +106,7 @@
* @{
*/
-/** @defgroup CRYP CRYP
+/** @addtogroup CRYP
* @brief CRYP HAL module driver.
* @{
*/
@@ -115,7 +115,7 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup CRYP_Private_Defines CRYP Private Defines
+/** @addtogroup CRYP_Private CRYP Private
* @{
*/
@@ -129,7 +129,7 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @defgroup CRYP_Private_Functions CRYP Private Functions
+/** @addtogroup CRYP_Private
* @{
*/
@@ -148,11 +148,11 @@
/* Private functions ---------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
+/** @addtogroup CRYP_Exported_Functions
* @{
*/
-/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
@@ -279,6 +279,9 @@
*/
__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_CRYP_MspInit can be implemented in the user file */
}
@@ -291,6 +294,9 @@
*/
__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_CRYP_MspDeInit can be implemented in the user file */
}
@@ -299,7 +305,7 @@
* @}
*/
-/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions
+/** @addtogroup CRYP_Exported_Functions_Group2
* @brief processing functions.
*
@verbatim
@@ -1718,7 +1724,7 @@
* @}
*/
-/** @defgroup CRYP_Exported_Functions_Group3 DMA callback functions
+/** @addtogroup CRYP_Exported_Functions_Group3
* @brief DMA callback functions.
*
@verbatim
@@ -1742,6 +1748,9 @@
*/
__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_CRYP_ErrorCallback can be implemented in the user file
*/
@@ -1755,6 +1764,9 @@
*/
__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_CRYP_InCpltCallback can be implemented in the user file
*/
@@ -1768,6 +1780,9 @@
*/
__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_CRYP_OutCpltCallback can be implemented in the user file
*/
@@ -1777,7 +1792,7 @@
* @}
*/
-/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
+/** @addtogroup CRYP_Exported_Functions_Group4
* @brief CRYP IRQ handler.
*
@verbatim
@@ -1843,7 +1858,7 @@
* @}
*/
-/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions
+/** @addtogroup CRYP_Exported_Functions_Group5
* @brief Peripheral State functions.
*
@verbatim
@@ -1876,7 +1891,7 @@
* @}
*/
-/** @addtogroup CRYP_Private_Functions
+/** @addtogroup CRYP_Private
* @{
*/
@@ -2159,6 +2174,6 @@
*/
#endif /* HAL_CRYP_MODULE_ENABLED */
-#endif /* STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
+#endif /* STM32L021xx || STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_cryp.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#if defined (STM32L021xx) || (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal_def.h"
@@ -52,7 +52,7 @@
* @{
*/
-/** @addtogroup CRYP
+/** @defgroup CRYP CRYP
* @{
*/
@@ -177,9 +177,6 @@
#define CRYP_IT_CC AES_CR_CCIE /*!< Computation Complete interrupt */
#define CRYP_IT_ERR AES_CR_ERRIE /*!< Error interrupt */
-#define IS_CRYP_AES_IT(IT) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00000000) && ((IT) != 0x00000000))
-#define IS_CRYP_AES_GET_IT(IT) (((IT) == CRYP_IT_CC) || ((IT) == CRYP_IT_ERR))
-
/**
* @}
*/
@@ -192,9 +189,6 @@
#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read Error Flag */
#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error Flag */
-#define IS_CRYP_STATUS_FLAG(FLAG) (((FLAG) == CRYP_FLAG_CCF) || \
- ((FLAG) == CRYP_FLAG_RDERR) || \
- ((FLAG) == CRYP_FLAG_WRERR))
/**
* @}
*/
@@ -314,11 +308,11 @@
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRYP_Exported_Functions
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
* @{
*/
-/** @addtogroup CRYP_Exported_Functions_Group1
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
@@ -334,7 +328,7 @@
* @}
*/
-/** @addtogroup CRYP_Exported_Functions_Group2
+/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions
* @{
*/
@@ -366,7 +360,7 @@
* @}
*/
-/** @addtogroup CRYP_Exported_Functions_Group3
+/** @addtogroup CRYP_Exported_Functions_Group3 DMA callback functions
* @{
*/
@@ -379,7 +373,7 @@
* @}
*/
-/** @addtogroup CRYP_Exported_Functions_Group4
+/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
* @{
*/
@@ -390,7 +384,7 @@
* @}
*/
-/** @addtogroup CRYP_Exported_Functions_Group5
+/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions
* @{
*/
@@ -405,6 +399,17 @@
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup CRYP_Private CRYP Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
+
/**
* @}
*/
@@ -413,7 +418,7 @@
* @}
*/
-#endif /* STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
+#endif /* STM32L021xx || STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp_ex.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp_ex.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_cryp_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief CRYPEx HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -40,16 +40,17 @@
******************************************************************************
*/
-#if defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#if defined (STM32L021xx) ||defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal.h"
-#ifdef HAL_CRYP_MODULE_ENABLED
/** @addtogroup STM32L0xx_HAL_Driver
* @{
*/
+#ifdef HAL_CRYP_MODULE_ENABLED
-/** @defgroup CRYPEx CRYPEx
+
+/** @addtogroup CRYPEx
* @brief CRYP HAL Extended module driver.
* @{
*/
@@ -62,12 +63,12 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
+/** @addtogroup CRYPEx_Exported_Functions
* @{
*/
-/** @defgroup CRYPEx_Exported_Functions_Group1 Extended features functions
+/** @addtogroup CRYPEx_Exported_Functions_Group1
* @brief Extended features functions.
*
@verbatim
@@ -89,6 +90,9 @@
*/
__weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_ComputationCpltCallback could be implemented in the user file
*/
@@ -106,11 +110,11 @@
* @}
*/
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
/**
* @}
*/
-
-#endif /* HAL_CRYP_MODULE_ENABLED */
-#endif /* STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
+#endif /* STM32L021xx || STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_cryp_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of CRYPEx HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal_def.h"
@@ -52,7 +52,7 @@
* @{
*/
-/** @addtogroup CRYPEx
+/** @defgroup CRYPEx CRYPEx
* @{
*/
@@ -60,11 +60,11 @@
/* Exported constants --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRYPEx_Exported_Functions
+/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
* @{
*/
-/** @addtogroup CRYPEx_Exported_Functions_Group1
+/** @defgroup CRYPEx_Exported_Functions_Group1 Extended features functions
* @{
*/
@@ -77,8 +77,7 @@
/**
* @}
- */
-
+ */
/**
* @}
@@ -88,7 +87,7 @@
* @}
*/
-#endif /* STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
+#endif /* STM32L021xx || STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
#ifdef __cplusplus
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_dac.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@@ -157,7 +157,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -185,7 +185,7 @@
*/
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal.h"
@@ -194,7 +194,7 @@
* @{
*/
-/** @defgroup DAC DAC HAL module driver
+/** @addtogroup DAC
* @brief DAC driver modules
* @{
*/
@@ -208,11 +208,11 @@
/* Private functions ---------------------------------------------------------*/
-/** @defgroup DAC_Exported_Functions DAC Exported Functions
+/** @addtogroup DAC_Exported_Functions
* @{
*/
-/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup DAC_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
@@ -245,7 +245,10 @@
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
if(hdac->State == HAL_DAC_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ hdac->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
}
@@ -307,6 +310,9 @@
*/
__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_MspInit could be implemented in the user file
*/
@@ -320,6 +326,9 @@
*/
__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_MspDeInit could be implemented in the user file
*/
@@ -329,7 +338,7 @@
* @}
*/
-/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
+/** @addtogroup DAC_Exported_Functions_Group2
* @brief IO operation functions
*
@verbatim
@@ -360,6 +369,10 @@
*/
__weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ UNUSED(Channel);
+
/* Note : This function is defined into this file for library reference. */
/* Function content is located into file stm32l0xx_hal_dac_ex.c */
@@ -411,6 +424,13 @@
*/
__weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ UNUSED(Channel);
+ UNUSED(pData);
+ UNUSED(Length);
+ UNUSED(Alignment);
+
/* Note : This function is defined into this file for library reference. */
/* Function content is located into file stm32l0xx_hal_dac_ex.c */
@@ -430,6 +450,10 @@
*/
__weak HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ UNUSED(Channel);
+
/* Note : This function is defined into this file for library reference. */
/* Function content is located into file stm32l0xx_hal_dac_ex.c */
@@ -449,6 +473,10 @@
*/
__weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ UNUSED(Channel);
+
/* Note : This function is defined into this file for library reference. */
/* Function content is located into file stm32l0xx_hal_dac_ex.c */
@@ -464,6 +492,9 @@
*/
__weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* Note : This function is defined into this file for library reference. */
/* Function content is located into file stm32l0xx_hal_dac_ex.c */
@@ -477,6 +508,9 @@
*/
__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
*/
@@ -490,6 +524,9 @@
*/
__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
*/
@@ -503,6 +540,9 @@
*/
__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
*/
@@ -516,6 +556,9 @@
*/
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
*/
@@ -525,7 +568,7 @@
* @}
*/
-/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
+/** @addtogroup DAC_Exported_Functions_Group3
* @brief Peripheral Control functions
*
@verbatim
@@ -591,35 +634,10 @@
}
/**
- * @brief Set the specified data holding register value for DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
- * @param Alignment: Specifies the data alignment.
- * This parameter can be one of the following values:
- * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
- * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
- * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @param Data: Data to be loaded in the selected data holding register.
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32l0xx_hal_dac_ex.c */
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
* @}
*/
-/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
+/** @addtogroup DAC_Exported_Functions_Group4
* @brief Peripheral State and Errors functions
*
@verbatim
@@ -660,18 +678,38 @@
}
/**
- * @}
+ * @brief Set the specified data holding register value for DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
+ * @param Alignment: Specifies the data alignment.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @param Data: Data to be loaded in the selected data holding register.
+ * @retval HAL status
*/
+__weak HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+ UNUSED(Channel);
+ UNUSED(Alignment);
+ UNUSED(Data);
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32l0xx_hal_dac_ex.c */
+ /* Return function status */
+ return HAL_OK;
+}
/**
* @}
*/
-/** @addtogroup DAC_Private_Functions
- * @{
- */
-
-
/**
* @}
*/
@@ -684,7 +722,7 @@
* @}
*/
#endif /* HAL_DAC_MODULE_ENABLED */
-#endif /* !STM32L031xx && !STM32L041xx && !STM32L051xx && !STM32L061xx&& !STM32L071xx&& !STM32L081xx*/
+#endif /* !STM32L011xx && STM32L021xx && !STM32L031xx && !STM32L041xx && !STM32L051xx && !STM32L061xx&& !STM32L071xx&& !STM32L081xx*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_dac.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal_def.h"
@@ -52,7 +52,7 @@
* @{
*/
-/** @addtogroup DAC
+/** @defgroup DAC DAC
* @{
*/
@@ -135,33 +135,35 @@
/** @defgroup DAC_trigger_selection DAC trigger selection
* @{
*/
-#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T21_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM21 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T21_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM21 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
-#define DAC_TRIGGER_T3_TRGO ((uint32_t)( DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t)( DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_CH3 ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM3 CH3 selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#endif
#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T21_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_CH3) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T21_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#else /* STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T21_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T21_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
/**
@@ -228,12 +230,6 @@
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#endif
-#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR1) || \
- ((FLAG) == DAC_FLAG_DMAUDR2))
-#else
-#define IS_DAC_FLAG(FLAG) ((FLAG) == DAC_FLAG_DMAUDR1)
-#endif
/**
* @}
*/
@@ -246,13 +242,6 @@
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#endif
-#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR1) || \
- ((IT) == DAC_IT_DMAUDR2))
-#else
-#define IS_DAC_IT(IT) ((IT) == DAC_IT_DMAUDR1)
-#endif
-
/**
* @}
*/
@@ -289,29 +278,7 @@
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \
CLEAR_BIT((__HANDLE__)->Instance->CR, (DAC_CR_EN1 << (__DAC_CHANNEL__)))
-/** @brief Set DHR12R1 alignment
- * @param __ALIGNEMENT__: specifies the DAC alignement
- * @retval None
- */
-#define __DAC_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
-
-/** @brief Set DHR12R2 alignment
- * @param __ALIGNEMENT__: specifies the DAC alignement
- * @retval None
- */
-#define __DAC_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__))
-
-/** @brief Set DHR12RD alignment
- * @param __ALIGNEMENT__: specifies the DAC alignement
- * @retval None
- */
-#define __DAC_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__))
-
-/** @brief Enable the DAC interrupt
- * @param __HANDLE__: specifies the DAC handle
- * @param __INTERRUPT__: specifies the DAC interrupt.
- * @retval None
- */
+
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
SET_BIT((__HANDLE__)->Instance->CR, __INTERRUPT__)
@@ -324,21 +291,67 @@
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
CLEAR_BIT((__HANDLE__)->Instance->CR, __INTERRUPT__)
+/** @brief Check whether the specified DAC interrupt source is enabled or not.
+ * @param __HANDLE__: DAC handle
+ * @param __INTERRUPT__: DAC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt (STM32L072xx STM32L073xx STM32L082xx STM32L083xx only)
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+(((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status.
* @param __HANDLE__: specifies the DAC handle.
* @param __FLAG__: specifies the FLAG.
* @retval None
*/
-#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) \
+((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the DAC's flag.
* @param __HANDLE__: specifies the DAC handle.
* @param __FLAG__: specifies the FLAG.
* @retval None
*/
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((__HANDLE__)->Instance->SR) = (__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Private macro ------------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Macros DAC Private Macros
+ * @{
+ */
+
+/** @brief Set DHR12R1 alignment
+ * @param __ALIGNEMENT__: specifies the DAC alignement
+ * @retval None
+ */
+#define DAC_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
+/** @brief Set DHR12R2 alignment
+ * @param __ALIGNEMENT__: specifies the DAC alignement
+ * @retval None
+ */
+#define DAC_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__))
+
+/** @brief Set DHR12RD alignment
+ * @param __ALIGNEMENT__: specifies the DAC alignement
+ * @retval None
+ */
+#define DAC_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__))
+
+/** @brief Enable the DAC interrupt
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __INTERRUPT__: specifies the DAC interrupt.
+ * @retval None
+ */
+
/**
* @}
*/
@@ -349,11 +362,11 @@
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DAC_Exported_Functions
+/** @defgroup DAC_Exported_Functions DAC Exported Functions
* @{
*/
-/** @addtogroup DAC_Exported_Functions_Group1
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
@@ -366,7 +379,7 @@
* @}
*/
-/** @addtogroup DAC_Exported_Functions_Group2
+/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
@@ -376,12 +389,17 @@
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
/**
* @}
*/
-/** @addtogroup DAC_Exported_Functions_Group2
+/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
@@ -391,19 +409,13 @@
* @}
*/
-/** @addtogroup DAC_Exported_Functions_Group2
+/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
* @{
*/
/* Peripheral State functions ***************************************************/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-
/**
* @}
*/
@@ -412,7 +424,6 @@
* @}
*/
-
/**
* @}
*/
@@ -421,7 +432,7 @@
* @}
*/
-#endif /* STM32L031xx && STM32L041xx && STM32L061xx && STM32L071xx && STM32L081xx*/
+#endif /* STM32L011xx && STM32L021xx && STM32L031xx && STM32L041xx && STM32L061xx && STM32L071xx && STM32L081xx*/
#ifdef __cplusplus
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac_ex.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac_ex.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_dac_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:
@@ -25,7 +25,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -53,7 +53,7 @@
*/
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal.h"
@@ -62,11 +62,14 @@
* @{
*/
-/** @defgroup DACEx DACEx
+/** @addtogroup DACEx DACEx
* @brief DAC driver modules
* @{
*/
+/** @addtogroup DACEx_Private
+ * @{
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -74,9 +77,7 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @addtogroup DACEx_Private_Functions
- * @{
- */
+
#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
@@ -85,16 +86,15 @@
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
-
/**
* @}
*/
-/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
+/** @addtogroup DACEx_Exported_Functions
* @{
*/
-/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
+/** @addtogroup DACEx_Exported_Functions_Group1
* @brief Extended features functions
*
@@ -256,7 +256,7 @@
}
tmp = (uint32_t)hdac->Instance;
- tmp += __DAC_DHR12RD_ALIGNEMENT(Alignment);
+ tmp += DAC_DHR12RD_ALIGNEMENT(Alignment);
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
@@ -274,6 +274,9 @@
*/
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
*/
@@ -287,6 +290,9 @@
*/
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
*/
@@ -300,6 +306,9 @@
*/
__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
*/
@@ -313,6 +322,9 @@
*/
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
*/
@@ -656,11 +668,11 @@
tmp = (uint32_t)hdac->Instance;
if(Channel == DAC_CHANNEL_1)
{
- tmp += __DAC_DHR12R1_ALIGNEMENT(Alignment);
+ tmp += DAC_DHR12R1_ALIGNEMENT(Alignment);
}
else
{
- tmp += __DAC_DHR12R2_ALIGNEMENT(Alignment);
+ tmp += DAC_DHR12R2_ALIGNEMENT(Alignment);
}
/* Set the DAC channel selected data holding register */
@@ -906,7 +918,7 @@
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)hdac->Instance;
- tmp += __DAC_DHR12R1_ALIGNEMENT(Alignment);
+ tmp += DAC_DHR12R1_ALIGNEMENT(Alignment);
/* Set the DAC channel selected data holding register */
*(__IO uint32_t *) tmp = Data;
@@ -925,7 +937,7 @@
* @}
*/
-/** @defgroup DACEx_Private_Functions DACEx Private Functions
+/** @addtogroup DACEx_Private
* @{
*/
#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
@@ -1026,8 +1038,6 @@
* @}
*/
-
-
/**
* @}
*/
@@ -1036,6 +1046,6 @@
* @}
*/
#endif /* HAL_DAC_MODULE_ENABLED */
-#endif /* #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
+#endif /* #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_dac_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal_def.h"
@@ -52,7 +52,7 @@
* @{
*/
-/** @addtogroup DACEx
+/** @defgroup DACEx DACEx
* @{
*/
@@ -129,11 +129,11 @@
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DACEx_Exported_Functions
+/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
* @{
*/
-/** @addtogroup DACEx_Exported_Functions_Group1
+/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
* @{
*/
/* Extension features functions ***********************************************/
@@ -156,6 +156,15 @@
/**
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup DACEx_Private DACEx Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
/**
* @}
@@ -164,7 +173,7 @@
/**
* @}
*/
-#endif /* STM32L031xx && STM32L041xx && !STM32L051xx && !STM32L061xx && !STM32L071xx && !STM32L081xx*/
+#endif /* !STM32L011xx && !STM32L021xx && !STM32L031xx && !STM32L041xx && !STM32L051xx && !STM32L061xx && !STM32L071xx && !STM32L081xx*/
#ifdef __cplusplus
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_def.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_def.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32l0xx_hal_def.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
- * @brief This file contains HAL common defines, enumeration, macros and
- * structures definitions.
+ * @version V1.5.0
+ * @date 8-January-2016
+ * @brief This file contains HAL common defines, enumeration, macros and
+ * structures definitions.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -51,10 +51,10 @@
/* Exported types ------------------------------------------------------------*/
-/**
- * @brief HAL Status structures definition
- */
-typedef enum
+/**
+ * @brief HAL Status structures definition
+ */
+typedef enum
{
HAL_OK = 0x00,
HAL_ERROR = 0x01,
@@ -62,13 +62,13 @@
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;
-/**
- * @brief HAL Lock structures definition
+/**
+ * @brief HAL Lock structures definition
*/
-typedef enum
+typedef enum
{
HAL_UNLOCKED = 0x00,
- HAL_LOCKED = 0x01
+ HAL_LOCKED = 0x01
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
@@ -88,11 +88,11 @@
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
- * @note This macro can be used for the following purpose:
+ * @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
- * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
- * Otherwise, "State" field may have any random value and the first time the function
+ * Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
@@ -104,10 +104,10 @@
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
#if (USE_RTOS == 1)
-
+
/* Reserved for future use */
- #error USE_RTOS should be 0 in the current HAL release
-
+ #error "USE_RTOS should be 0 in the current HAL release"
+
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
@@ -134,8 +134,8 @@
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
-
- #define __NOINLINE __attribute__ ( (noinline) )
+
+ #define __NOINLINE __attribute__ ( (noinline) )
#endif /* __GNUC__ */
@@ -145,44 +145,44 @@
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
- #ifndef __ALIGN_BEGIN
+ #ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
- #ifndef __ALIGN_BEGIN
+ #ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
- #define __ALIGN_BEGIN __align(4)
+ #define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
- #define __ALIGN_BEGIN
+ #define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
-/**
+/**
* @brief __RAM_FUNC definition
- */
+ */
#if defined ( __CC_ARM )
/* ARM Compiler
------------
- RAM functions are defined using the toolchain options.
+ RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
- Using the 'Options for File' dialog you can simply change the 'Code / Const'
+ Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
- dialog.
+ dialog.
*/
-#define __RAM_FUNC HAL_StatusTypeDef
+#define __RAM_FUNC HAL_StatusTypeDef
-#define __NOINLINE __attribute__ ( (noinline) )
+#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
- RAM functions are defined using a specific toolchain keyword "__ramfunc".
+ RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
@@ -191,13 +191,13 @@
#elif defined ( __GNUC__ )
/* GNU Compiler
------------
- RAM functions are defined using a specific toolchain attribute
+ RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
#endif
-
+
#ifdef __cplusplus
}
#endif
@@ -205,4 +205,3 @@
#endif /* ___STM32L0xx_HAL_DEF */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_dma.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -59,7 +59,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -92,29 +92,21 @@
/** @addtogroup STM32L0xx_HAL_Driver
* @{
*/
+#ifdef HAL_DMA_MODULE_ENABLED
/** @addtogroup DMA DMA
* @brief DMA HAL module driver
* @{
*/
-#ifdef HAL_DMA_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
-/** @defgroup DMA_Private_Types DMA Private Types
+/** @addtogroup DMA_Private
*
* @{
*/
#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
-/**
- * @}
- */
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
- * @{
- */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
/**
* @}
@@ -157,7 +149,7 @@
}
/* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(hdma->Instance));
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
@@ -167,6 +159,12 @@
assert_param(IS_DMA_MODE(hdma->Init.Mode));
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+ if(hdma->State == HAL_DMA_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hdma->Lock = HAL_UNLOCKED;
+ }
+
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
@@ -228,6 +226,7 @@
/* Configure request selection for DMA1 Channel5 */
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16);
}
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
else if (hdma->Instance == DMA1_Channel6)
{
/*Reset request selection for DMA1 Channel6*/
@@ -244,7 +243,7 @@
/* Configure request selection for DMA1 Channel7 */
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24);
}
-
+#endif
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
@@ -318,6 +317,7 @@
/*Reset DMA request*/
DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S;
}
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
else if (hdma->Instance == DMA1_Channel6)
{
/*Reset DMA request*/
@@ -328,7 +328,7 @@
/*Reset DMA request*/
DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S;
}
-
+#endif
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@@ -441,7 +441,6 @@
* @brief Aborts the DMA Transfer.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
- * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
@@ -719,7 +718,7 @@
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup DMA_Private_Functions DMA Private Functions
+/** @addtogroup DMA_Private
* @{
*/
@@ -760,11 +759,11 @@
* @}
*/
-#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_dma.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,6 +54,9 @@
* @{
*/
+ /** @defgroup DMA_Exported_Types DMA Exported Types
+ * @{
+ */
/* Exported types ------------------------------------------------------------*/
/**
@@ -152,6 +155,10 @@
} DMA_HandleTypeDef;
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants DMA Exported Constants
@@ -165,14 +172,22 @@
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
-#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
- ((PERIPH) == DMA1_Channel2) || \
- ((PERIPH) == DMA1_Channel3) || \
- ((PERIPH) == DMA1_Channel4) || \
- ((PERIPH) == DMA1_Channel5) || \
- ((PERIPH) == DMA1_Channel6) || \
- ((PERIPH) == DMA1_Channel7))
+#if defined (STM32L011xx) || defined (STM32L021xx)
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5))
+#else
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+#endif
#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1))
/**
@@ -264,7 +279,7 @@
* @}
*/
-/** @defgroup DMA_Data_buffer_size
+/** @defgroup DMA_Data_buffer_size DMA Data Buffer Size Check
* @{
*/
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
@@ -272,7 +287,7 @@
* @}
*/
-/** @defgroup DMA_Peripheral_incremented_mode
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral Incremented Mode
* @{
*/
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
@@ -284,7 +299,7 @@
* @}
*/
-/** @defgroup DMA_Memory_incremented_mode
+/** @defgroup DMA_Memory_incremented_mode DMA Memory Incremented Mode
* @{
*/
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
@@ -296,7 +311,7 @@
* @}
*/
-/** @defgroup DMA_Peripheral_data_size
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral Data Size Alignment
* @{
*/
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
@@ -311,7 +326,7 @@
*/
-/** @defgroup DMA_Memory_data_size
+/** @defgroup DMA_Memory_data_size DMA Memory Data Size Alignment
* @{
*/
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
@@ -325,7 +340,7 @@
* @}
*/
-/** @defgroup DMA_mode
+/** @defgroup DMA_mode DMA Mode
* @{
*/
#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
@@ -337,7 +352,7 @@
* @}
*/
-/** @defgroup DMA_Priority_level
+/** @defgroup DMA_Priority_level DMA Priority Level
* @{
*/
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
@@ -354,7 +369,7 @@
*/
-/** @defgroup DMA_interrupt_enable_definitions
+/** @defgroup DMA_interrupt_enable_definitions DMA Interrupt Definitions
* @{
*/
@@ -366,7 +381,7 @@
* @}
*/
-/** @defgroup DMA_flag_definitions
+/** @defgroup DMA_flag_definitions DMA Flag Definitions
* @{
*/
@@ -443,6 +458,14 @@
* @retval The specified transfer complete flag index.
*/
+#if defined (STM32L011xx) || defined (STM32L021xx)
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ DMA_FLAG_TC5)
+#else
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
@@ -450,13 +473,21 @@
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
- DMA_FLAG_TC7)
-
+ DMA_FLAG_TC7)
+#endif
/**
* @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index.
- */
+ */
+#if defined (STM32L011xx) || defined (STM32L021xx)
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ DMA_FLAG_HT5)
+#else
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
@@ -465,12 +496,20 @@
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
DMA_FLAG_HT7)
-
+#endif
/**
* @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
+#if defined (STM32L011xx) || defined (STM32L021xx)
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ DMA_FLAG_TE5)
+#else
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
@@ -479,12 +518,20 @@
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7)
-
+#endif
/**
* @brief Returns the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
+#if defined (STM32L011xx) || defined (STM32L021xx)
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
+ DMA_ISR_GIF5)
+#else
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
@@ -493,6 +540,7 @@
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
DMA_ISR_GIF7)
+#endif
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
@@ -546,7 +594,7 @@
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
/**
- * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
+ * @brief Checks whether the specified DMA Channel interrupt is enabled or not.
* @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
@@ -608,6 +656,15 @@
/**
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup DMA_Private DMA Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_firewall.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_firewall.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,10 +2,9 @@
******************************************************************************
* @file stm32l0xx_hal_firewall.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief FIREWALL HAL module driver.
- *
* This file provides firmware functions to manage the Firewall
* Peripheral initialization and enabling.
*
@@ -35,7 +34,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -61,6 +60,7 @@
*
******************************************************************************
*/
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal.h"
@@ -69,25 +69,20 @@
* @{
*/
-/** @defgroup FIREWALL FIREWALL
+#ifdef HAL_FIREWALL_MODULE_ENABLED
+
+/** @addtogroup FIREWALL
* @brief HAL FIREWALL module driver
* @{
*/
-#ifdef HAL_FIREWALL_MODULE_ENABLED
+
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FIREWALL_Exported_Functions FIREWALL Exported Functions
+/** @addtogroup FIREWALL_Exported_Functions
* @{
*/
-/** @defgroup FIREWALL_Exported_Functions_Group1 Initialization Functions
+/** @addtogroup FIREWALL_Exported_Functions_Group1
* @brief Initialization and Configuration Functions
*
@verbatim
@@ -164,23 +159,23 @@
/* Configuration */
/* Protected code segment start address configuration */
- WRITE_REG(FW->CSSA, (FW_CSSA_ADD & fw_init->CodeSegmentStartAddress));
+ WRITE_REG(FIREWALL->CSSA, (FW_CSSA_ADD & fw_init->CodeSegmentStartAddress));
/* Protected code segment length configuration */
- WRITE_REG(FW->CSL, (FW_CSL_LENG & fw_init->CodeSegmentLength));
+ WRITE_REG(FIREWALL->CSL, (FW_CSL_LENG & fw_init->CodeSegmentLength));
/* Protected non volatile data segment start address configuration */
- WRITE_REG(FW->NVDSSA, (FW_NVDSSA_ADD & fw_init->NonVDataSegmentStartAddress));
+ WRITE_REG(FIREWALL->NVDSSA, (FW_NVDSSA_ADD & fw_init->NonVDataSegmentStartAddress));
/* Protected non volatile data segment length configuration */
- WRITE_REG(FW->NVDSL, (FW_NVDSL_LENG & fw_init->NonVDataSegmentLength));
+ WRITE_REG(FIREWALL->NVDSL, (FW_NVDSL_LENG & fw_init->NonVDataSegmentLength));
/* Protected volatile data segment start address configuration */
- WRITE_REG(FW->VDSSA, (FW_VDSSA_ADD & fw_init->VDataSegmentStartAddress));
+ WRITE_REG(FIREWALL->VDSSA, (FW_VDSSA_ADD & fw_init->VDataSegmentStartAddress));
/* Protected volatile data segment length configuration */
- WRITE_REG(FW->VDSL, (FW_VDSL_LENG & fw_init->VDataSegmentLength));
+ WRITE_REG(FIREWALL->VDSL, (FW_VDSL_LENG & fw_init->VDataSegmentLength));
/* Set Firewall Configuration Register VDE and VDS bits
(volatile data execution and shared configuration) */
- MODIFY_REG(FW->CR, FW_CR_VDS|FW_CR_VDE, fw_init->VolatileDataExecution|fw_init->VolatileDataShared);
+ MODIFY_REG(FIREWALL->CR, FW_CR_VDS|FW_CR_VDE, fw_init->VolatileDataExecution|fw_init->VolatileDataShared);
return HAL_OK;
}
@@ -203,22 +198,22 @@
__HAL_RCC_FIREWALL_CLK_ENABLE();
/* Retrieve code segment protection setting */
- fw_config->CodeSegmentStartAddress = (READ_REG(FW->CSSA) & FW_CSSA_ADD);
- fw_config->CodeSegmentLength = (READ_REG(FW->CSL) & FW_CSL_LENG);
+ fw_config->CodeSegmentStartAddress = (READ_REG(FIREWALL->CSSA) & FW_CSSA_ADD);
+ fw_config->CodeSegmentLength = (READ_REG(FIREWALL->CSL) & FW_CSL_LENG);
/* Retrieve non volatile data segment protection setting */
- fw_config->NonVDataSegmentStartAddress = (READ_REG(FW->NVDSSA) & FW_NVDSSA_ADD);
- fw_config->NonVDataSegmentLength = (READ_REG(FW->NVDSL) & FW_NVDSL_LENG);
+ fw_config->NonVDataSegmentStartAddress = (READ_REG(FIREWALL->NVDSSA) & FW_NVDSSA_ADD);
+ fw_config->NonVDataSegmentLength = (READ_REG(FIREWALL->NVDSL) & FW_NVDSL_LENG);
/* Retrieve volatile data segment protection setting */
- fw_config->VDataSegmentStartAddress = (READ_REG(FW->VDSSA) & FW_VDSSA_ADD);
- fw_config->VDataSegmentLength = (READ_REG(FW->VDSL) & FW_VDSL_LENG);
+ fw_config->VDataSegmentStartAddress = (READ_REG(FIREWALL->VDSSA) & FW_VDSSA_ADD);
+ fw_config->VDataSegmentLength = (READ_REG(FIREWALL->VDSL) & FW_VDSL_LENG);
/* Retrieve volatile data execution setting */
- fw_config->VolatileDataExecution = (READ_REG(FW->CR) & FW_CR_VDE);
+ fw_config->VolatileDataExecution = (READ_REG(FIREWALL->CR) & FW_CR_VDE);
/* Retrieve volatile data shared setting */
- fw_config->VolatileDataShared = (READ_REG(FW->CR) & FW_CR_VDS);
+ fw_config->VolatileDataShared = (READ_REG(FIREWALL->CR) & FW_CR_VDS);
return;
}
@@ -245,14 +240,13 @@
* will close the Firewall.
* @note This API provides the same service as __HAL_FIREWALL_PREARM_ENABLE() macro
* but can't be executed inside a code area protected by the Firewall.
- * @note -- When the Firewall is disabled, user can resort to
- * HAL_FIREWALL_EnablePreArmFlag() API any time.
- * -- When the Firewall is enabled and NVDSL register is equal to 0 (that is,
+ * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.
+ * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is,
* when the non volatile data segment is not defined),
* ** this API can be executed when the Firewall is closed
* ** when the Firewall is opened, user should resort to
* __HAL_FIREWALL_PREARM_ENABLE() macro instead
- * -- When the Firewall is enabled and NVDSL register is different from 0
+ * @note When the Firewall is enabled and NVDSL register is different from 0
* (that is, when the non volatile data segment is defined)
* ** FW_CR register can be accessed only when the Firewall is opened:
* user should resort to __HAL_FIREWALL_PREARM_ENABLE() macro instead.
@@ -261,7 +255,7 @@
void HAL_FIREWALL_EnablePreArmFlag(void)
{
/* Set FPA bit */
- SET_BIT(FW->CR, FW_CR_FPA);
+ SET_BIT(FIREWALL->CR, FW_CR_FPA);
}
@@ -271,14 +265,13 @@
* when the Firewall is opened will generate a system reset.
* @note This API provides the same service as __HAL_FIREWALL_PREARM_DISABLE() macro
* but can't be executed inside a code area protected by the Firewall.
- * @note -- When the Firewall is disabled, user can resort to
- * HAL_FIREWALL_EnablePreArmFlag() API any time.
- * -- When the Firewall is enabled and NVDSL register is equal to 0 (that is,
+ * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.
+ * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is,
* when the non volatile data segment is not defined),
* ** this API can be executed when the Firewall is closed
* ** when the Firewall is opened, user should resort to
* __HAL_FIREWALL_PREARM_DISABLE() macro instead
- * -- When the Firewall is enabled and NVDSL register is different from 0
+ * @note When the Firewall is enabled and NVDSL register is different from 0
* (that is, when the non volatile data segment is defined)
* ** FW_CR register can be accessed only when the Firewall is opened:
* user should resort to __HAL_FIREWALL_PREARM_DISABLE() macro instead.
@@ -288,7 +281,7 @@
void HAL_FIREWALL_DisablePreArmFlag(void)
{
/* Clear FPA bit */
- CLEAR_BIT(FW->CR, FW_CR_FPA);
+ CLEAR_BIT(FIREWALL->CR, FW_CR_FPA);
}
/**
@@ -299,13 +292,16 @@
* @}
*/
-#endif /* HAL_FIREWALL_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_FIREWALL_MODULE_ENABLED */
+
/**
* @}
*/
+#endif /* #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_firewall.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_firewall.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_firewall.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of FIREWALL HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,6 +43,8 @@
extern "C" {
#endif
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal_def.h"
@@ -50,7 +52,7 @@
* @{
*/
-/** @addtogroup FIREWALL FIREWALL
+/** @defgroup FIREWALL FIREWALL
* @{
*/
@@ -136,17 +138,17 @@
*/
/* Private macros --------------------------------------------------------*/
-/** @defgroup FIREWALL_Private_Macros FIREWALL Private Macros
+/** @addtogroup FIREWALL_Private
* @{
*/
-#define IS_FIREWALL_CODE_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF))
-#define IS_FIREWALL_CODE_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= 0x080FFFFF)
+#define IS_FIREWALL_CODE_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))
+#define IS_FIREWALL_CODE_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))
-#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF))
-#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= 0x080FFFFF)
+#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))
+#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))
-#define IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= 0x20000000) && ((ADDRESS) <= 0x20017FFF))
-#define IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= 0x20017FFF)
+#define IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= SRAM_BASE) && ((ADDRESS) < (SRAM_BASE + SRAM1_SIZE_MAX)))
+#define IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (SRAM_BASE + SRAM_SIZE_MAX))
#define IS_FIREWALL_VOLATILEDATA_SHARE(SHARE) (((SHARE) == FIREWALL_VOLATILEDATA_NOT_SHARED) || \
@@ -164,7 +166,7 @@
* @{
*/
-/** @brief Check whether or not the FIREWALL is enabled
+/** @brief Check whether the FIREWALL is enabled or not.
* @retval FIREWALL enabling status (TRUE or FALSE).
*/
#define __HAL_FIREWALL_IS_ENABLED() HAL_IS_BIT_CLR(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN)
@@ -183,10 +185,10 @@
#define __HAL_FIREWALL_PREARM_ENABLE() \
do { \
__IO uint32_t tmpreg; \
- SET_BIT(FW->CR, FW_CR_FPA) ; \
+ SET_BIT(FIREWALL->CR, FW_CR_FPA) ; \
/* Read bit back to ensure it is taken into account by IP */ \
/* (introduce proper delay inside macro execution) */ \
- tmpreg = READ_BIT(FW->CR, FW_CR_FPA) ; \
+ tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ; \
UNUSED(tmpreg); \
} while(0)
@@ -205,10 +207,10 @@
#define __HAL_FIREWALL_PREARM_DISABLE() \
do { \
__IO uint32_t tmpreg; \
- CLEAR_BIT(FW->CR, FW_CR_FPA) ; \
+ CLEAR_BIT(FIREWALL->CR, FW_CR_FPA) ; \
/* Read bit back to ensure it is taken into account by IP */ \
/* (introduce proper delay inside macro execution) */ \
- tmpreg = READ_BIT(FW->CR, FW_CR_FPA) ; \
+ tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ; \
UNUSED(tmpreg); \
} while(0)
@@ -224,10 +226,10 @@
#define __HAL_FIREWALL_VOLATILEDATA_SHARED_ENABLE() \
do { \
__IO uint32_t tmpreg; \
- SET_BIT(FW->CR, FW_CR_VDS) ; \
+ SET_BIT(FIREWALL->CR, FW_CR_VDS) ; \
/* Read bit back to ensure it is taken into account by IP */ \
/* (introduce proper delay inside macro execution) */ \
- tmpreg = READ_BIT(FW->CR, FW_CR_VDS) ; \
+ tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ; \
UNUSED(tmpreg); \
} while(0)
@@ -244,10 +246,10 @@
#define __HAL_FIREWALL_VOLATILEDATA_SHARED_DISABLE() \
do { \
__IO uint32_t tmpreg; \
- CLEAR_BIT(FW->CR, FW_CR_VDS) ; \
+ CLEAR_BIT(FIREWALL->CR, FW_CR_VDS) ; \
/* Read bit back to ensure it is taken into account by IP */ \
/* (introduce proper delay inside macro execution) */ \
- tmpreg = READ_BIT(FW->CR, FW_CR_VDS) ; \
+ tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ; \
UNUSED(tmpreg); \
} while(0)
@@ -266,10 +268,10 @@
#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_ENABLE() \
do { \
__IO uint32_t tmpreg; \
- SET_BIT(FW->CR, FW_CR_VDE) ; \
+ SET_BIT(FIREWALL->CR, FW_CR_VDE) ; \
/* Read bit back to ensure it is taken into account by IP */ \
/* (introduce proper delay inside macro execution) */ \
- tmpreg = READ_BIT(FW->CR, FW_CR_VDE) ; \
+ tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ; \
UNUSED(tmpreg); \
} while(0)
@@ -286,10 +288,10 @@
#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_DISABLE() \
do { \
__IO uint32_t tmpreg; \
- CLEAR_BIT(FW->CR, FW_CR_VDE) ; \
+ CLEAR_BIT(FIREWALL->CR, FW_CR_VDE) ; \
/* Read bit back to ensure it is taken into account by IP */ \
/* (introduce proper delay inside macro execution) */ \
- tmpreg = READ_BIT(FW->CR, FW_CR_VDE) ; \
+ tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ; \
UNUSED(tmpreg); \
} while(0)
@@ -302,7 +304,7 @@
* executed only when the Firewall is opened.
* @retval VDS bit setting status (TRUE or FALSE).
*/
-#define __HAL_FIREWALL_GET_VOLATILEDATA_SHARED() ((FW->CR & FW_CR_VDS) == FW_CR_VDS)
+#define __HAL_FIREWALL_GET_VOLATILEDATA_SHARED() ((FIREWALL->CR & FW_CR_VDS) == FW_CR_VDS)
/** @brief Check whether or not the volatile data segment is declared executable.
* @note This macro can be executed inside a code area protected by the Firewall.
@@ -312,7 +314,7 @@
* executed only when the Firewall is opened.
* @retval VDE bit setting status (TRUE or FALSE).
*/
-#define __HAL_FIREWALL_GET_VOLATILEDATA_EXECUTION() ((FW->CR & FW_CR_VDE) == FW_CR_VDE)
+#define __HAL_FIREWALL_GET_VOLATILEDATA_EXECUTION() ((FIREWALL->CR & FW_CR_VDE) == FW_CR_VDE)
/** @brief Check whether or not the Firewall pre arm bit is set.
* @note This macro can be executed inside a code area protected by the Firewall.
@@ -322,7 +324,7 @@
* executed only when the Firewall is opened.
* @retval FPA bit setting status (TRUE or FALSE).
*/
-#define __HAL_FIREWALL_GET_PREARM() ((FW->CR & FW_CR_FPA) == FW_CR_FPA)
+#define __HAL_FIREWALL_GET_PREARM() ((FIREWALL->CR & FW_CR_FPA) == FW_CR_FPA)
/**
@@ -331,11 +333,11 @@
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FIREWALL_Exported_Functions FIREWALL Exported Functions
+/** @defgroup FIREWALL_Exported_Functions FIREWALL Exported Functions
* @{
*/
-/** @addtogroup FIREWALL_Exported_Functions_Group1 Initialization Functions
+/** @defgroup FIREWALL_Exported_Functions_Group1 Initialization Functions
* @brief Initialization and Configuration Functions
* @{
*/
@@ -354,6 +356,15 @@
/**
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup FIREWALL_Private FIREWALL Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
/**
* @}
@@ -363,6 +374,9 @@
* @}
*/
+
+#endif /* #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) */
+
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_flash.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -144,7 +144,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -185,11 +185,12 @@
* @{
*/
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/** @addtogroup FLASH_Private_Variables FLASH Internal Variables
+/** @addtogroup FLASH_Private
* @{
*/
@@ -198,16 +199,18 @@
*/
FLASH_ProcessTypeDef ProcFlash;
+
+/* Private function prototypes -----------------------------------------------*/
+static void FLASH_SetErrorCode(void);
+static void FLASH_Program_Word(uint32_t Address, uint32_t Data);
+
/**
* @}
- */
-/* Private function prototypes -----------------------------------------------*/
-static void FLASH_SetErrorCode(void);
-static void FLASH_Program_Word(uint32_t Address, uint32_t Data);
-
+ */
+
/* functions -----------------------------------------------------------------*/
-/** @addtogroup FLASH_Exported_Functions FLASH Exported functions
+/** @addtogroup FLASH_Exported_Functions
* @{
*/
@@ -278,27 +281,31 @@
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
- /* Enable End of FLASH Operation interrupt */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
-
- /* Enable Error source interrupt */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
- ProcFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
- ProcFlash.Address = Address;
-
- if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+ if(status == HAL_OK)
{
- /* Program word (32-bit) at a specified address */
- FLASH_Program_Word(Address, (uint32_t) Data);
- }
-
+ /* Enable End of FLASH Operation interrupt */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+
+ /* Enable Error source interrupt */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+
+ ProcFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
+ ProcFlash.Address = Address;
+
+ if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+ {
+ /* Program word (32-bit) at a specified address */
+ FLASH_Program_Word(Address, (uint32_t) Data);
+ }
+ }
return status;
}
/**
* @brief This function handles FLASH interrupt request.
- * @param None
* @retval None
*/
void HAL_FLASH_IRQHandler(void)
@@ -306,6 +313,18 @@
uint32_t temp;
/* Check FLASH operation error flags */
+
+ /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
+ * (RevID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
+ * as expected. If the user run an application using the first
+ * cut of the STM32L031xx device or the first cut of the STM32L041xx
+ * device, the check on the FLASH_FLAG_OPTVERR bit should be ignored.
+ *
+ * Note :The RevID of the device can be retrieved via the HAL_GetREVID()
+ * function.
+ *
+ */
+
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_OPTVERR | \
FLASH_FLAG_RDERR | FLASH_FLAG_FWWERR | FLASH_FLAG_NOTZEROERR) != RESET)
{
@@ -413,6 +432,9 @@
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
*/
@@ -427,6 +449,9 @@
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
*/
@@ -588,7 +613,7 @@
* @}
*/
-/** @addtogroup FLASH_Private_Functions
+/** @addtogroup FLASH_Private
* @{
*/
@@ -615,12 +640,30 @@
}
}
}
+
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ }
+
+
if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) || \
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) || \
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) != RESET) || \
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) != RESET))
{
/* Save the error code */
+
+ /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
+ * (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
+ * as expected. If the user run an application using the first
+ * cut of the STM32L031xx device or the first cut of the STM32L041xx
+ * device, this error should be ignored. The revId of the device
+ * can be retrieved via the HAL_GetREVID() function.
+ *
+ */
FLASH_SetErrorCode();
return HAL_ERROR;
}
@@ -631,7 +674,6 @@
/**
* @brief Set the specific FLASH error flag.
- * @param None
* @retval None
*/
static void FLASH_SetErrorCode(void)
@@ -650,6 +692,14 @@
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
{
+ /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
+ * (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
+ * as expected. If the user run an application using the first
+ * cut of the STM32L031xx device or the first cut of the STM32L041xx
+ * device, this error should be ignored. The revId of the device
+ * can be retrieved via the HAL_GetREVID() function.
+ *
+ */
ProcFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
@@ -666,6 +716,7 @@
}
/* Errors are now stored, clear errors flags */
+
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR |
FLASH_FLAG_OPTVERR | FLASH_FLAG_RDERR | FLASH_FLAG_FWWERR |
FLASH_FLAG_NOTZEROERR);
@@ -718,10 +769,6 @@
* @}
*/
-/**
- * @}
- */
-
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_flash.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of Flash HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -83,14 +83,6 @@
This parameter must be a value between 1 and (max number of pages - value of Initial page)*/
} FLASH_EraseInitTypeDef;
-/**
- * @}
- */
-
-
-/** @defgroup FLASH_Private_Types FLASH Private Types
- * @{
- */
/**
* @brief FLASH handle Structure definition
@@ -114,7 +106,7 @@
* @}
*/
-/** @defgroup FLASH_Private_Variables FLASH Private Variables
+/** @addtogroup FLASH_Private
* @{
*/
@@ -123,13 +115,8 @@
* Put as extern as used also in flash_ex.c.
*/
extern FLASH_ProcessTypeDef ProcFlash;
-/**
- * @}
- */
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
- * @{
- */
+
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000) /* 50 s */
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FF8007C)
/**
@@ -147,7 +134,7 @@
#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER) * 1024)
#define FLASH_PAGE_SIZE ((uint32_t)128)
-/** @defgroup FLASH_Type_Program
+/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/
@@ -183,7 +170,7 @@
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
-#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */
+#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag (not valid with STM32L031xx/STM32L041xx) */
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protected error flag */
#define FLASH_FLAG_FWWERR FLASH_SR_FWWERR /*!< FLASH Write or Errase operation aborted */
#define FLASH_FLAG_NOTZEROERR FLASH_SR_NOTZEROERR /*!< FLASH Read protected error flag */
@@ -243,11 +230,13 @@
* @{
*/
-/** @defgroup FLASH_Interrupt macros to handle FLASH interrupts
+/** @defgroup FLASH_Macro_Interrupt Macros to handle FLASH interrupts
+ * @brief Enable and disable the specified FLASH interrupt.
* @{
*/
+
/**
- * @brief Enable/Disable the specified FLASH interrupt.
+ * @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ : FLASH interrupt
* This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
@@ -255,6 +244,15 @@
* @retval none
*/
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) ((FLASH->PECR) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified FLASH interrupt.
+ * @param __INTERRUPT__ : FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_ERR: Error Interrupt
+ * @retval none
+ */
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) ((FLASH->PECR) &= ~(uint32_t)(__INTERRUPT__))
/**
@@ -266,9 +264,9 @@
* @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode
* @arg FLASH_FLAG_ENDHV: FLASH End of high voltage flag
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag (not valid with STM32L031xx/STM32L041xx)
* @arg FLASH_FLAG_SIZERR: FLASH Size error flag
- * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
+ * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag (not valid with STM32L031xx/STM32L041xx)
* @arg FLASH_FLAG_RDERR: FLASH Read protected error flag
* @arg FLASH_FLAG_FWWERR: FLASH Fetch While Write Error flag
* @arg FLASH_FLAG_NOTZEROERR: Not Zero area error flag
@@ -282,9 +280,9 @@
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag (not valid with STM32L031xx/STM32L041xx)
* @arg FLASH_FLAG_SIZERR: FLASH size error flag
- * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
+ * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag (not valid with STM32L031xx/STM32L041xx)
* @arg FLASH_FLAG_RDERR: FLASH Read protected error flag
* @arg FLASH_FLAG_FWWERR: FLASH Fetch While Write Error flag
* @arg FLASH_FLAG_NOTZEROERR: Not Zero area error flag
@@ -363,7 +361,7 @@
* @}
*/
-/** @defgroup FLASH_Private_Macros FLASH Private Macros
+/** @addtogroup FLASH_Private
* @{
*/
@@ -371,14 +369,6 @@
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
((__LATENCY__) == FLASH_LATENCY_1))
-/**
- * @}
- */
-
-
-/** @defgroup FLASH_Private_Functions FLASH Private functions
- * @{
- */
/**
* @brief Function used internally by HAL FLASH driver.
@@ -389,6 +379,17 @@
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup FLASH_Private FLASH Private
+ * @{
+ */
+
+/**
+ * @}
+ */
+/**************************************************************/
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ex.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ex.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_flash_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -37,7 +37,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -71,18 +71,21 @@
* @{
*/
+#ifdef HAL_FLASH_MODULE_ENABLED
+
/** @addtogroup FLASHEx
* @brief FLASH HAL Extension module driver
* @{
*/
-#ifdef HAL_FLASH_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FLASHEx_Private
+ * @{
+ */
static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP);
static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR);
static uint8_t FLASH_OB_GetUser(void);
@@ -104,6 +107,9 @@
#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
static HAL_StatusTypeDef FLASH_OB_BFB2Config(uint8_t OB_BFB2);
#endif
+/**
+ * @}
+ */
/* Exported functions ---------------------------------------------------------*/
@@ -222,26 +228,32 @@
/* Process Locked */
__HAL_LOCK(&ProcFlash);
- /* Enable End of FLASH Operation interrupt */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
-
- /* Enable Error source interrupt */
- __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
- /* Check the parameters */
- assert_param(IS_NBPAGES(pEraseInit->NbPages));
- assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
- assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
- assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1));
-
- /* Clean the error context */
- ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
- ProcFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
- ProcFlash.NbPagesToErase = pEraseInit->NbPages;
- ProcFlash.Page = pEraseInit->PageAddress;
-
- /* Erase 1st page and wait for IT */
- FLASH_ErasePage(pEraseInit->PageAddress);
+ if (status == HAL_OK)
+ {
+ /* Enable End of FLASH Operation interrupt */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+
+ /* Enable Error source interrupt */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+
+ /* Check the parameters */
+ assert_param(IS_NBPAGES(pEraseInit->NbPages));
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1));
+
+ /* Clean the error context */
+ ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+ ProcFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
+ ProcFlash.NbPagesToErase = pEraseInit->NbPages;
+ ProcFlash.Page = pEraseInit->PageAddress;
+
+ /* Erase 1st page and wait for IT */
+ FLASH_ErasePage(pEraseInit->PageAddress);
+ }
return status;
}
@@ -463,7 +475,6 @@
* @brief Select the Protection Mode (WPRMOD).
* @note Once WPRMOD bit is active, unprotection of a protected sector is not possible
* @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
- * @param None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
@@ -475,7 +486,6 @@
* @brief Deselect the Protection Mode (WPRMOD).
* @note Once WPRMOD bit is active, unprotection of a protected sector is not possible
* @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
- * @param None
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
@@ -514,7 +524,6 @@
*/
/**
* @brief Unlocks the data memory and FLASH_PECR register access.
- * @param None
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void)
@@ -534,7 +543,6 @@
/**
* @brief Locks the Data memory and FLASH_PECR register access.
- * @param None
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void)
@@ -571,7 +579,10 @@
/* Write "00000000h" to valid address in the data memory" */
*(__IO uint32_t *) Address = 0x00000000;
- }
+
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+ }
+
return status;
}
@@ -655,8 +666,15 @@
*/
/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Private
+ * @{
+ */
+
+/**
* @brief Returns the FLASH User Option Bytes values.
- * @param None
* @retval The FLASH User Option Bytes.
*/
static uint8_t FLASH_OB_GetUser(void)
@@ -667,7 +685,6 @@
/**
* @brief Returns the FLASH Read out Protection Level.
- * @param None
* @retval FLASH RDP level.
*/
static uint8_t FLASH_OB_GetRDP(void)
@@ -677,7 +694,6 @@
/**
* @brief Returns the FLASH BOR level.
- * @param None
* @retval The BOR level Option Bytes.
*/
static uint8_t FLASH_OB_GetBOR(void)
@@ -688,7 +704,6 @@
/**
* @brief Returns the FLASH BOOT bit1 value.
- * @param None
* @retval The BOOT bit 1 value Option Bytes.
*/
static uint8_t FLASH_OB_GetBOOTBit1(void)
@@ -700,7 +715,6 @@
/**
* @brief Returns the FLASH Write Protection Option Bytes value.
- * @param None
* @retval The FLASH Write Protection Option Bytes value.
*/
static uint32_t FLASH_OB_GetWRP(void)
@@ -712,7 +726,6 @@
#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
/**
* @brief Returns the FLASH Write Protection Option Bytes value.
- * @param None
* @retval The FLASH Write Protection Option Bytes value.
*/
static uint32_t FLASH_OB_GetWRP2(void)
@@ -779,11 +792,11 @@
* must be called before.
* @param OB_RDP: specifies the read protection level.
* This parameter can be:
- * @arg OB_RDP_LEVEL0: No protection
- * @arg OB_RDP_LEVEL1: Read protection of the memory
- * @arg OB_RDP_LEVEL2: Chip protection
+ * @arg OB_RDP_LEVEL_0: No protection
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory
+ * @arg OB_RDP_LEVEL_2: Chip protection
*
- * !!!Warning!!! When enabling OB_RDP_LEVEL2 it's no more possible to go back to level 1 or 0
+ * !!!Warning!!! When enabling OB_RDP_LEVEL_2 it's no more possible to go back to level 1 or 0
*
* @retval HAL status
*/
@@ -901,7 +914,7 @@
* @brief Select the Protection Mode (WPRMOD).
* @note Once WPRMOD bit is active, unprotection of a protected sector is not possible
* @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
- * @param OB_PcROP: Select the Protection Mode of WPR bits.
+ * @param WPRMOD: Select the Protection Mode of WPR bits.
* This parameter can be:
* @arg OB_PCROP_SELECTED: nWRP control the read&write protection (PcROP) of respective user sectors.
* @arg OB_PCROP_DESELECTED: nWRP control the write protection of respective user sectors.
@@ -938,7 +951,7 @@
#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
/**
* @brief Sets or resets the BFB2 option bit.
- * @param BFB2: Set or Reset the BFB2 option bit.
+ * @param OB_BFB2: Set or Reset the BFB2 option bit.
* This parameter can be one of the following values:
* @arg OB_BOOT_BANK1: BFB2 option bit reset
* @arg OB_BOOT_BANK2: BFB2 option bit set
@@ -977,17 +990,25 @@
}
#endif
+
+#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
/**
* @brief Write Option Byte of the desired pages of the Flash.
* @param Sector: specifies the sectors to be write protected.
- * @param Sector2: specifies the sectors to be write protected only stm32l07xxx and stm32l08xxx devices
+ * @param Sector2: specifies the sectors to be write protected (only stm32l07xxx and stm32l08xxx devices)
* @param NewState: new state of the specified FLASH Pages Wite protection.
* This parameter can be: ENABLE or DISABLE.
* @retval HAL_StatusTypeDef
*/
-#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32_t Sector2, uint32_t NewState)
#else
+/**
+ * @brief Write Option Byte of the desired pages of the Flash.
+ * @param Sector: specifies the sectors to be write protected.
+ * @param NewState: new state of the specified FLASH Pages Wite protection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval HAL_StatusTypeDef
+ */
static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32_t NewState)
#endif
{
@@ -1060,6 +1081,13 @@
/**
* @}
*/
-#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+#endif /* HAL_FLASH_MODULE_ENABLED */
+/**
+ * @}
+ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_flash_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of FLash HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,7 +54,7 @@
* @{
*/
-/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
+/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
* @{
*/
@@ -123,7 +123,7 @@
* @{
*/
-/** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
* @{
*/
#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!< Page erase only */
@@ -131,7 +131,7 @@
* @}
*/
-/** @defgroup FLASHEx_Option_Type FLASHEx Option Type
+/** @defgroup FLASHEx_Option_Type FLASH Option Type
* @{
*/
#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */
@@ -143,7 +143,7 @@
* @}
*/
-/** @defgroup FLASHEx_WRP_State FLASHEx WRP State
+/** @defgroup FLASHEx_WRP_State FLASH WRP State
* @{
*/
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired sectors */
@@ -152,7 +152,7 @@
* @}
*/
-/** @defgroup FLASHEx_Option_Bytes_ReadWrite_Mask FLASHEx Option Bytes Write Mask
+/** @defgroup FLASHEx_Option_Bytes_ReadWrite_Mask FLASH Option Bytes Write Mask
* @{
*/
#define WRP_MASK_LOW ((uint32_t)0x0000FFFF)
@@ -161,8 +161,8 @@
* @}
*/
-#if defined (STM32L031xx) || defined (STM32L041xx)
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASHEx Option Bytes Write Protection
+#if defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx)
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
* @{
*/
#define OB_WRP_Pages0to31 ((uint32_t)0x00000001) /* Write protection of Sector0 */
@@ -178,7 +178,7 @@
* @}
*/
#elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx)
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASHEx Option Bytes Write Protection
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
* @{
*/
#define OB_WRP_Pages0to31 ((uint32_t)0x00000001) /* Write protection of Sector0 */
@@ -203,7 +203,7 @@
*/
#elif defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASHEx Option Bytes Write ProtectionP
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write ProtectionP
* @{
*/
#define OB_WRP_Pages0to31 ((uint32_t)0x00000001) /* Write protection of Sector0 */
@@ -243,7 +243,7 @@
* @}
*/
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASHEx Option Bytes Write Protection
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASH Option Bytes Write Protection
* @{
*/
#define OB_WRP2_Pages1024to1055 ((uint32_t)0x00000001) /* Write protection of Sector32 */
@@ -268,18 +268,18 @@
*/
#endif /* STM32L071xx || STM32L072xx || (STM32L073xx) || (STM32L081xx) || (STM32L082xx) || (STM32L083xx) */
-/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
* @{
*/
-#define OB_RDP_LEVEL0 ((uint8_t)0xAA)
-#define OB_RDP_LEVEL1 ((uint8_t)0xBB)
-#define OB_RDP_LEVEL2 ((uint8_t)0xCC) /* Warning: When enabling read protection level 2
+#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
+#define OB_RDP_LEVEL_1 ((uint8_t)0xBB)
+#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /* Warning: When enabling read protection level 2
it is no more possible to go back to level 1 or 0 */
/**
* @}
*/
-/** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level
+/** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASH Option Bytes BOR Level
* @{
*/
#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD
@@ -293,7 +293,7 @@
* @}
*/
-/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */
@@ -311,7 +311,7 @@
* @}
*/
-/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
* @{
*/
#define OB_STDBY_NORST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */
@@ -321,7 +321,7 @@
*/
-/** @defgroup FLASHEx_PCROP_State
+/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
* @{
*/
#define OB_PCROP_STATE_DISABLE ((uint8_t)0x00) /*!< Disable PCROP */
@@ -331,7 +331,7 @@
*/
-/** @defgroup FLASHEx_OptionAdv_Type
+/** @defgroup FLASHEx_OptionAdv_Type FLASH Option Byte
* @{
*/
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
@@ -344,7 +344,7 @@
* @}
*/
-#if defined (STM32L031xx) || defined (STM32L041xx)
+#if defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx)
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASHEx Option Bytes PC Read/Write Protection
* @{
*/
@@ -387,7 +387,7 @@
#endif
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASHEx Option Bytes PC Read/Write Protection
+/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC Read/Write Protection
* @{
*/
#define OB_PCROP_Pages0to31 ((uint32_t)0x00000001) /* PC Read/Write protection of Sector0 */
@@ -427,7 +427,7 @@
* @}
*/
-/** @defgroup FLASHEx_Option_Bytes_ReadWrite_Protection2 FLASHEx Option Bytes Read Write Protection
+/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 FLASH Option Bytes PC Read/Write Protection (Sector 2)
* @{
*/
#define OB_PCROP2_Pages1024to1055 ((uint32_t)0x00000001) /* PC Read/Write protection of Sector32 */
@@ -452,7 +452,7 @@
*/
#endif /* if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
-/** @defgroup FLASHEx_Option_Bytes_BOOTBit1
+/** @defgroup FLASHEx_Option_Bytes_BOOTBit1 FLASH Option Bytes BOOT Bit1 Setup
* @{
*/
#define OB_BOOT_BIT1_RESET (uint8_t)(0x00) /*!< BOOT Bit 1 Reset */
@@ -462,20 +462,19 @@
*/
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-/** @defgroup FLASHEx_Option_Bytes_BOOT_BANK FLASHEx Option Bytes BOOT BANK
+/** @defgroup FLASHEx_Option_Bytes_BOOT_BANK FLASH Option Bytes BOOT BANK
* @{
*/
#define OB_BOOT_BANK1 ((uint8_t)0x00) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position
- and this parameter is selected the device will boot from Bank 2
- or Bank 1, depending on the activation of the bank */
+ and this parameter is selected the device will boot from Bank 1 (Default)*/
#define OB_BOOT_BANK2 (uint8_t)(0x01) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position
- and this parameter is selected the device will boot from Bank1(Default) */
+ and this parameter is selected the device will boot from Bank 2 */
/**
* @}
*/
#endif /* if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
-/** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data
+/** @defgroup FLASHEx_Type_Program_Data FLASH Type Program Data
* @{
*/
#define FLASH_TYPEPROGRAMDATA_BYTE ((uint32_t)0x00) /*!< Program byte (8-bit) at a specified address.*/
@@ -501,7 +500,7 @@
* @}
*/
-/** @defgroup FLASHEx_Exported_Macros macros to control FLASH features
+/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
* @brief
* @{
*/
@@ -518,6 +517,15 @@
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
/**
+ * @brief Get the FLASH Latency.
+ * @retval FLASH Latency
+ * This parameter can be one of the following values:
+ * @arg FLASH_LATENCY_0: FLASH Zero Latency cycle
+ * @arg FLASH_LATENCY_1: FLASH One Latency cycle
+*/
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
* @brief Enable/Disable the FLASH prefetch buffer.
* @retval none
*/
@@ -569,7 +577,7 @@
* @}
*/
-/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported functions
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
* @{
*/
@@ -613,7 +621,7 @@
* @}
*/
-/** @addtogroup FLASH_Private_Macros FLASH Private Macros
+/** @addtogroup FLASHEx_Private
* @{
*/
#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES))
@@ -626,9 +634,9 @@
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
-#define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL0)||\
- ((__LEVEL__) == OB_RDP_LEVEL1)||\
- ((__LEVEL__) == OB_RDP_LEVEL2))
+#define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0)||\
+ ((__LEVEL__) == OB_RDP_LEVEL_1)||\
+ ((__LEVEL__) == OB_RDP_LEVEL_2))
#define IS_OB_BOR_LEVEL(__LEVEL__) ( ((__LEVEL__) == OB_BOR_OFF) || \
((__LEVEL__) == OB_BOR_LEVEL1) || \
@@ -674,6 +682,16 @@
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup FLASHEx_Private FLASHEx Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ramfunc.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ramfunc.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_flash_ramfunc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief FLASH RAMFUNC driver.
* This file provides a Flash firmware functions which should be
* executed from internal SRAM
@@ -32,7 +32,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -62,15 +62,20 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal.h"
-#ifdef HAL_FLASH_MODULE_ENABLED
/** @addtogroup STM32L0xx_HAL_Driver
* @{
*/
-/** @addtogroup FLASHRamfunc
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+
+/** @addtogroup FLASH_RAMFUNC
* @brief FLASH functions executed from RAM
* @{
*/
+/** @addtogroup FLASH_RAMFUNC_Private
+ * @{
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -79,9 +84,12 @@
/* Private function prototypes -----------------------------------------------*/
static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout);
static __RAM_FUNC FLASHRAM_SetErrorCode(void);
+/**
+ * @}
+ */
-/** @addtogroup FLASHRamfunc_Exported_Functions
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions
*
@verbatim
===============================================================================
@@ -95,15 +103,14 @@
* @{
*/
-/** @addtogroup FLASHRamfunc_Exported_Functions_Group1
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
* @{
*/
/**
* @brief Enable the power down mode during RUN mode.
* @note This function can be used only when the user code is running from Internal SRAM.
- * @param None
- * @retval None
+ * @retval HAL Status
*/
__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)
{
@@ -115,8 +122,7 @@
/**
* @brief Disable the power down mode during RUN mode.
* @note This function can be used only when the user code is running from Internal SRAM.
- * @param None
- * @retval None
+ * @retval HAL Status
*/
__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
{
@@ -129,14 +135,15 @@
* @}
*/
-/** @addtogroup FLASHRamfunc_Exported_Functions_Group2
+#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
+
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group2
*
@verbatim
@endverbatim
* @{
*/
-#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
/**
* @brief Erases a specified 2 pages in program memory in parallel.
* @note This function can be used only for STM32L07xxx/STM32L08xxx devices.
@@ -274,8 +281,15 @@
/* Return the Write Status */
return status;
}
+/**
+ * @}
+ */
#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */
-
+
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
+ *
+ * @{
+ */
/**
* @brief Program a half page in program memory.
* @param Address: specifies the address to be written.
@@ -352,6 +366,7 @@
* @arg HAL_FLASH_ERROR_OPTV: FLASH Option valid error flag
* @arg HAL_FLASH_ERROR_FWWERR: FLASH Write or Errase operation aborted
* @arg HAL_FLASH_ERROR_NOTZERO: FLASH Write operation is done in a not-erased region
+ * @retval HAL Status
*/
__RAM_FUNC HAL_FLASHRAM_GetError(uint32_t * error)
{
@@ -359,8 +374,6 @@
return HAL_OK;
}
-
-
/**
* @}
*/
@@ -369,14 +382,13 @@
* @}
*/
-/** @defgroup FLASHRamfunc_Private_Functions FLASH RAM Private Functions
+/** @addtogroup FLASH_RAMFUNC_Private
* @{
*/
/**
* @brief Set the specific FLASH error flag.
- * @param None
- * @retval None
+ * @retval HAL Status
*/
static __RAM_FUNC FLASHRAM_SetErrorCode(void)
{
@@ -394,6 +406,14 @@
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
{
+ /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
+ * (RevID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
+ * as expected. If the user run an application using the first
+ * cut of the STM32L031xx device or the first cut of the STM32L041xx
+ * device, this error should be ignored. The RevID of the device
+ * can be retrieved via the HAL_GetREVID() function.
+ *
+ */
ProcFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
@@ -410,6 +430,7 @@
}
/* Errors are now stored, clear errors flags */
+
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR |
FLASH_FLAG_OPTVERR | FLASH_FLAG_RDERR | FLASH_FLAG_FWWERR |
FLASH_FLAG_NOTZEROERR);
@@ -447,6 +468,16 @@
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) != RESET) )
{
/*Save the error code*/
+
+ /* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
+ * (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving
+ * as expected. If the user run an application using the first
+ * cut of the STM32L031xx device or the first cut of the STM32L041xx
+ * device, this error should be ignored. The revId of the device
+ * can be retrieved via the HAL_GetREVID() function.
+ *
+ */
+
FLASHRAM_SetErrorCode();
return HAL_ERROR;
}
@@ -463,10 +494,12 @@
* @}
*/
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
/**
* @}
*/
-#endif /* HAL_FLASH_MODULE_ENABLED */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ramfunc.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ramfunc.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_flash_ramfunc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,16 +50,13 @@
* @{
*/
-/** @defgroup FLASHRamfunc FLASHRamfunc
+/** @defgroup FLASH_RAMFUNC FLASH Ram Function
* @{
*/
-/* Exported types ------------------------------------------------------------*/
-
-
/* Exported functions --------------------------------------------------------*/
-/** @defgroup FLASHRamfunc_Exported_Functions FLASH RAM Exported Functions
+/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH Ram Exported Functions
* @{
*/
@@ -69,7 +66,7 @@
* file.
*/
-/** @defgroup FLASHRamfunc_Exported_Functions_Group1 FLASH RAM Peripheral features functions
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 FLASH RAM peripheral features functions
* @{
*/
__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer);
@@ -81,7 +78,7 @@
*/
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
-/** @defgroup FLASHRamfunc_Exported_Functions_Group2 FLASH RAM Programming and erasing operation functions
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 FLASH RAM programming and erasing operation functions
* @{
*/
__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);
@@ -93,7 +90,17 @@
/**
* @}
- */
+ */
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup FLASH_RAMFUNC_Private FLASH Ram Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_gpio.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -98,7 +98,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -132,16 +132,17 @@
* @{
*/
+#ifdef HAL_GPIO_MODULE_ENABLED
+
/** @addtogroup GPIO
* @brief GPIO HAL module driver
* @{
*/
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
+/** @addtogroup GPIO_Private
+ * @{
+ */
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
#define GPIO_MODE ((uint32_t)0x00000003)
@@ -153,10 +154,10 @@
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
#define GPIO_NUMBER ((uint32_t)16)
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
/** @addtogroup GPIO_Exported_Functions
* @{
*/
@@ -184,7 +185,6 @@
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
uint32_t position = 0x00;
- uint32_t ioposition = 0x00;
uint32_t iocurrent = 0x00;
uint32_t temp = 0x00;
@@ -194,21 +194,17 @@
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,(GPIO_Init->Pin)));
/* Configure the port pins */
- for(position = 0; position < GPIO_NUMBER; position++)
+ while ((GPIO_Init->Pin) >> position)
{
/* Get the IO position */
- ioposition = ((uint32_t)0x01) << position;
- /* Get the current IO position */
- iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+ iocurrent = (GPIO_Init->Pin) & (1 << position);
- if(iocurrent == ioposition)
+ if(iocurrent)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
- /* Check the Alternate function parameter */
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Check if the Alternate function is compliant with the GPIO in use */
assert_param(IS_GPIO_AF_AVAILABLE(GPIOx,(GPIO_Init->Alternate)));
/* Configure Alternate function mapped with the current IO */
@@ -296,6 +292,7 @@
EXTI->FTSR = temp;
}
}
+ position++;
}
}
@@ -311,22 +308,19 @@
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
uint32_t position = 0x00;
- uint32_t ioposition = 0x00;
uint32_t iocurrent = 0x00;
uint32_t tmp = 0x00;
/* Check the parameters */
- assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin));
+ assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin));
/* Configure the port pins */
- for(position = 0; position < GPIO_NUMBER; position++)
+ while (GPIO_Pin >> position)
{
/* Get the IO position */
- ioposition = ((uint32_t)0x01) << position;
- /* Get the current IO position */
- iocurrent = (GPIO_Pin) & ioposition;
-
- if(iocurrent == ioposition)
+ iocurrent = (GPIO_Pin) & (1 << position);
+
+ if(iocurrent)
{
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO Direction in Input Floting Mode */
@@ -344,20 +338,26 @@
/* Deactivate the Pull-up oand Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2));
-
/*------------------------- EXTI Mode Configuration --------------------*/
- /* Configure the External Interrupt or event for the current IO */
- tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
- SYSCFG->EXTICR[position >> 2] &= ~tmp;
+ /* Clear the External Interrupt or Event for the current IO */
- /* Clear EXTI line configuration */
- EXTI->IMR &= ~((uint32_t)iocurrent);
- EXTI->EMR &= ~((uint32_t)iocurrent);
-
- /* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~((uint32_t)iocurrent);
- EXTI->FTSR &= ~((uint32_t)iocurrent);
+ tmp = SYSCFG->EXTICR[position >> 2];
+ tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+ if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
+ {
+ tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+ SYSCFG->EXTICR[position >> 2] &= ~tmp;
+
+ /* Clear EXTI line configuration */
+ EXTI->IMR &= ~((uint32_t)iocurrent);
+ EXTI->EMR &= ~((uint32_t)iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR &= ~((uint32_t)iocurrent);
+ EXTI->FTSR &= ~((uint32_t)iocurrent);
+ }
}
+ position++;
}
}
@@ -516,6 +516,9 @@
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(GPIO_Pin);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
@@ -530,11 +533,12 @@
* @}
*/
-#endif /* HAL_GPIO_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_gpio.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -102,12 +102,13 @@
/**
* @}
*/
+
+
+#define IS_GPIO_PIN_ACTION(__ACTION__) (((__ACTION__) == GPIO_PIN_RESET) || ((__ACTION__) == GPIO_PIN_SET))
+
/**
* @}
*/
-
-#define IS_GPIO_PIN_ACTION(__ACTION__) (((__ACTION__) == GPIO_PIN_RESET) || ((__ACTION__) == GPIO_PIN_SET))
-
/******************************************************************************/
/* Exported constants --------------------------------------------------------*/
/******************************************************************************/
@@ -191,17 +192,17 @@
* @brief GPIO Output Maximum frequency
* @{
*/
-#define GPIO_SPEED_LOW ((uint32_t)0x00000000) /*!< Low speed */
-#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */
-#define GPIO_SPEED_FAST ((uint32_t)0x00000002) /*!< Fast speed */
-#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */
+#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< range up to 0.4 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< range 0.4 MHz to 2 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002) /*!< range 2 MHz to 10 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< range 10 MHz to 35 MHz, please refer to the product datasheet */
/**
* @}
*/
-#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_LOW) || ((__SPEED__) == GPIO_SPEED_MEDIUM) || \
- ((__SPEED__) == GPIO_SPEED_FAST) || ((__SPEED__) == GPIO_SPEED_HIGH))
+#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW ) || ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM ) || \
+ ((__SPEED__) == GPIO_SPEED_FREQ_HIGH ) || ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
/** @defgroup GPIO_pull_define Pull definition
@@ -227,7 +228,7 @@
/* Exported macro ------------------------------------------------------------*/
/******************************************************************************/
/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Macro GPIO Exported Macro
+/** @defgroup GPIO_Exported_Macro GPIO Exported Macros
* @{
*/
/**
@@ -312,6 +313,18 @@
/**
* @}
*/
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup GPIO_Private GPIO Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_gpio_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,7 +50,7 @@
* @{
*/
-/** @defgroup GPIOEx GPIOx
+/** @defgroup GPIOEx GPIOEx
* @{
*/
@@ -174,8 +174,8 @@
* @{
*/
-/** @defgroup GPIOEx_Alternate_function_AF0 Alternate function AF0
- * @{
+/*
+ * Alternate function AF0
*/
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */
#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */
@@ -192,22 +192,22 @@
#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */
#define GPIO_AF0_USB ((uint8_t)0x00) /* USB Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF1 Alternate function AF1
- * @{
+/*
+ * Alternate function AF1
*/
#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */
#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */
#define GPIO_AF1_TIM21 ((uint8_t)0x01) /* TIM21 Alternate Function mapping */
#define GPIO_AF1_LCD ((uint8_t)0x01) /* LCD Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF2 Alternate function AF2
- * @{
+/*
+ * Alternate function AF2
*/
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
@@ -215,27 +215,27 @@
#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */
#define GPIO_AF2_MCO ((uint8_t)0x02) /* MCO Alternate Function mapping */
-#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */
+#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */
#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */
#define GPIO_AF2_USART5 ((uint8_t)0x02) /* USART5 Alternate Function mapping */
#define GPIO_AF2_SPI1 ((uint8_t)0x02) /* SPI1 Alternate Function mapping */
#define GPIO_AF2_USB ((uint8_t)0x00) /* USB Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF3 Alternate function AF3
- * @{
+/*
+ * Alternate function AF3
*/
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */
#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF4 Alternate function AF4
- * @{
+/*
+ * Alternate function AF4
*/
#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */
#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */
@@ -245,11 +245,11 @@
#define GPIO_AF4_TIM3 ((uint8_t)0x04) /* TIM3 Alternate Function mapping */
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF5 Alternate function AF5
- * @{
+/*
+ * Alternate function AF5
*/
#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */
#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */
@@ -258,11 +258,11 @@
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF6 Alternate function AF6
- * @{
+/*
+ * Alternate function AF6
*/
#define GPIO_AF6_USART4 ((uint8_t)0x06) /* USART4 Alternate Function mapping */
@@ -273,17 +273,21 @@
#define GPIO_AF6_USART5 ((uint8_t)0x06) /* USART5 Alternate Function mapping */
#define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF7 Alternate function AF7
- * @{
+/*
+ * Alternate function AF7
*/
#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */
#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */
#define GPIO_AF7_I2C3 ((uint8_t)0x07) /* I2C3 Alternate Function mapping */
#define GPIO_AF7_LPUART1 ((uint8_t)0x07) /* LPUART1 Alternate Function mapping */
/**
+ *
+ */
+
+/**
* @}
*/
@@ -291,8 +295,11 @@
* @}
*/
+/** @defgroup GPIOEx_Private GPIOEx Private
+ * @{
+ */
/**
- * @brief IS_GPIO_AF macro definition
+ * IS_GPIO_AF macro definition
*/
#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_EVENTOUT) || ((__AF__) == GPIO_AF1_LCD) || \
((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF1_I2C1) || \
@@ -357,6 +364,9 @@
((__AF__) == GPIO_AF6_USART4))) || \
(((__INSTANCE__) == GPIOH) && (((__AF__) == GPIO_AF0_USB))))
+ /**
+ * @}
+ */
#endif /* (STM32L083xx) || (STM32L073xx) */
/*----------------------------------------------------------------------------*/
@@ -469,8 +479,8 @@
* @{
*/
-/** @defgroup GPIOEx_Alternate_function_AF1 Alternate function AF1
- * @{
+/*
+ * Alternate function AF0
*/
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */
#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */
@@ -487,21 +497,21 @@
#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */
#define GPIO_AF0_USB ((uint8_t)0x00) /* USB Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF0 Alternate function AF0
- * @{
+/*
+ * Alternate function AF1
*/
#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */
#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */
#define GPIO_AF1_TIM21 ((uint8_t)0x01) /* TIM21 Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF2 Alternate function AF2
- * @{
+/*
+ * Alternate function AF2
*/
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
@@ -509,27 +519,27 @@
#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */
#define GPIO_AF2_MCO ((uint8_t)0x02) /* MCO Alternate Function mapping */
-#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */
+#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */
#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */
#define GPIO_AF2_USART5 ((uint8_t)0x02) /* USART5 Alternate Function mapping */
#define GPIO_AF2_SPI1 ((uint8_t)0x02) /* SPI1 Alternate Function mapping */
#define GPIO_AF2_USB ((uint8_t)0x00) /* USB Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF3 Alternate function AF3
- * @{
+/*
+ * Alternate function AF3
*/
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */
#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF4 Alternate function AF4
- * @{
+/*
+ * Alternate function AF4
*/
#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */
#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */
@@ -539,11 +549,11 @@
#define GPIO_AF4_TIM3 ((uint8_t)0x04) /* TIM3 Alternate Function mapping */
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF5 Alternate function AF5
- * @{
+/*
+ * Alternate function AF5
*/
#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */
#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */
@@ -552,11 +562,11 @@
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF6 Alternate function AF6
- * @{
+/*
+ * Alternate function AF6
*/
#define GPIO_AF6_USART4 ((uint8_t)0x06) /* USART4 Alternate Function mapping */
#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /* LPUART1 Alternate Function mapping */
@@ -566,17 +576,21 @@
#define GPIO_AF6_USART5 ((uint8_t)0x06) /* USART5 Alternate Function mapping */
#define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF7 Alternate function AF7
- * @{
+ /*
+ * Alternate function AF7
*/
#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */
#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */
#define GPIO_AF7_I2C3 ((uint8_t)0x07) /* I2C3 Alternate Function mapping */
#define GPIO_AF7_LPUART1 ((uint8_t)0x07) /* LPUART1 Alternate Function mapping */
/**
+ *
+ */
+
+ /**
* @}
*/
@@ -584,8 +598,11 @@
* @}
*/
+/** @defgroup GPIOEx_Private GPIOEx Private
+ * @{
+ */
/**
- * IS_GPIO_AF macro definition
+ * @brief IS_GPIO_AF macro definition
*/
#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_EVENTOUT) || ((__AF__) == GPIO_AF6_TIM21) || \
((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF1_I2C1) || \
@@ -646,7 +663,9 @@
((__AF__) == GPIO_AF6_USART4))) || \
(((__INSTANCE__) == GPIOH) && (((__AF__) == GPIO_AF0_USB))))
-
+ /**
+ * @}
+ */
#endif /* (STM32L082xx) || (STM32L072xx) */
@@ -761,8 +780,9 @@
* @{
*/
-/** @defgroup GPIOEx_Alternate_function_AF0 Alternate function AF0
- * @{
+/*
+ * Alternate function AF0
+ *
*/
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */
#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */
@@ -778,47 +798,51 @@
#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */
#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF1 Alternate function AF1
- * @{
+/*
+ * Alternate function AF1
+ *
*/
#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */
#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */
#define GPIO_AF1_TIM21 ((uint8_t)0x01) /* TIM21 Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF2 Alternate function AF2
- * @{
+/*
+ * Alternate function AF2
+ *
*/
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */
#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */
-#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */
+#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */
#define GPIO_AF2_MCO ((uint8_t)0x02) /* MCO Alternate Function mapping */
-#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */
-#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */
+#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */
+#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */
#define GPIO_AF2_USART5 ((uint8_t)0x02) /* USART5 Alternate Function mapping */
-#define GPIO_AF2_SPI1 ((uint8_t)0x02) /* SPI1 Alternate Function mapping */
+#define GPIO_AF2_SPI1 ((uint8_t)0x02) /* SPI1 Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF3 Alternate function AF3
+/*
+ * Alternate function AF3
* @{
*/
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */
+#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF4 Alternate function AF4
- * @{
+/*
+ * Alternate function AF4
+ *
*/
#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */
#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */
@@ -828,11 +852,12 @@
#define GPIO_AF4_TIM3 ((uint8_t)0x04) /* TIM3 Alternate Function mapping */
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF5 Alternate function AF5
- * @{
+/*
+ * Alternate function AF5
+ *
*/
#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */
#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */
@@ -841,11 +866,12 @@
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF6 Alternate function AF6
- * @{
+/*
+ * Alternate function AF6
+ *
*/
#define GPIO_AF6_USART4 ((uint8_t)0x06) /* USART4 Alternate Function mapping */
#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /* LPUART1 Alternate Function mapping */
@@ -855,17 +881,22 @@
#define GPIO_AF6_USART5 ((uint8_t)0x06) /* USART5 Alternate Function mapping */
#define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF7 Alternate function AF7
- * @{
+/*
+ * Alternate function AF7
+ *
*/
#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */
#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */
#define GPIO_AF7_I2C3 ((uint8_t)0x07) /* I2C3 Alternate Function mapping */
#define GPIO_AF7_LPUART1 ((uint8_t)0x07) /* LPUART1 Alternate Function mapping */
/**
+ *
+ */
+
+/**
* @}
*/
@@ -873,7 +904,11 @@
* @}
*/
- /**
+/** @defgroup GPIOEx_Private GPIOEx Private
+ * @{
+ */
+
+ /**
* IS_GPIO_AF macro definition
*/
#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_EVENTOUT) || ((__AF__) == GPIO_AF7_LPUART1) || \
@@ -932,7 +967,9 @@
((__AF__) == GPIO_AF2_TIM3) || \
((__AF__) == GPIO_AF6_USART4))))
-
+ /**
+ * @}
+ */
#endif /* (STM32L081xx) || (STM32L071xx) */
/*----------------------------------------------------------------------------*/
@@ -1008,8 +1045,8 @@
* @{
*/
-/** @defgroup GPIOEx_Alternate_function_AF0 Alternate function AF0
- * @{
+/*
+ * Alternate function AF0
*/
#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */
#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */
@@ -1027,22 +1064,22 @@
#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */
#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF1 Alternate function AF1
- * @{
+ /*
+ * Alternate function AF1
*/
#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */
#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */
#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */
#define GPIO_AF1_LCD ((uint8_t)0x01) /* LCD Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF2 Alternate function AF2
- * @{
+/*
+ * Alternate function AF2
*/
#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */
#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */
@@ -1050,23 +1087,23 @@
#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */
+#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF3 Alternate function AF3
- * @{
+/*
+ * Alternate function AF3
*/
#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF4 Alternate function AF4
- * @{
+/*
+ * Alternate function AF4
*/
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
@@ -1075,11 +1112,11 @@
#define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */
#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF5 Alternate function AF5
- * @{
+ /*
+ * Alternate function AF5
*/
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */
@@ -1087,25 +1124,29 @@
#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */
#define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF6 Alternate function AF6
- * @{
+/*
+ * Alternate function AF6
*/
#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */
#define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF7 Alternate function AF7
- * @{
+/*
+ * Alternate function AF7
*/
#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */
#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */
/**
+ *
+ */
+
+/**
* @}
*/
@@ -1113,7 +1154,12 @@
* @}
*/
-
+/** @defgroup GPIOEx_Private GPIOEx Private
+ * @{
+ */
+/**
+ * @brief IS_GPIO_AF macro definition
+ */
#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF2_SPI2) || \
((__AF__) == GPIO_AF0_SPI2) || ((__AF__) == GPIO_AF2_LPUART1) || \
@@ -1164,6 +1210,9 @@
((__AF__) == GPIO_AF1_LCD))) || \
(((__INSTANCE__) == GPIOH) && (((__AF__) == GPIO_AF0_USB))))
+/**
+ * @}
+ */
#endif /* STM32L053xx || STM32L063xx */
/*------------------------------------------------------------------------------------------*/
@@ -1241,8 +1290,8 @@
* @{
*/
-/** @defgroup GPIOEx_Alternate_function_AF0 Alternate function AF0
- * @{
+/*
+ * Alternate function AF0
*/
#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */
#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */
@@ -1260,45 +1309,45 @@
#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */
#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF1 Alternate function AF1
- * @{
+/*
+ * Alternate function AF1
*/
#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */
#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */
#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF2 Alternate function AF2
- * @{
+/**
+ * Alternate function AF2
*/
#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */
#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */
#define GPIO_AF2_USB ((uint8_t)0x02) /* USB Alternate Function mapping */
-#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */
+#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF3 Alternate function AF3
- * @{
+/*
+ * Alternate function AF3
*/
#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */
#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF4 Alternate function AF4
- * @{
+/*
+ * Alternate function AF4
*/
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
@@ -1307,11 +1356,11 @@
#define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */
#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF5 Alternate function AF5
- * @{
+/*
+ * Alternate function AF5
*/
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */
@@ -1319,25 +1368,29 @@
#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */
#define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF6 Alternate function AF6
- * @{
+/*
+ * Alternate function AF6
*/
#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */
#define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF7 Alternate function AF7
- * @{
+/*
+ * Alternate function AF7
*/
#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */
#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */
/**
+ *
+ */
+
+/**
* @}
*/
@@ -1345,6 +1398,12 @@
* @}
*/
+/** @defgroup GPIOEx_Private GPIOEx Private
+ * @{
+ */
+/**
+ * @brief IS_GPIO_AF macro definition
+ */
#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF2_SPI2) || \
((__AF__) == GPIO_AF0_SPI2) || ((__AF__) == GPIO_AF2_LPUART1) || \
@@ -1391,7 +1450,9 @@
(((__INSTANCE__) == GPIOD) && (((__AF__) == GPIO_AF0_LPUART1))) || \
(((__INSTANCE__) == GPIOH) && (((__AF__) == GPIO_AF0_USB))))
-
+ /**
+ * @}
+ */
#endif /* STM32L052xx || STM32L062xx */
/*------------------------------------------------------------------------------------------*/
@@ -1467,8 +1528,8 @@
* @{
*/
-/** @defgroup GPIOEx_Alternate_function_AF0 Alternate function AF0
- * @{
+/*
+ * Alternate function AF0
*/
#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */
#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */
@@ -1484,44 +1545,44 @@
#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */
#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF1 Alternate function AF1
- * @{
+/*
+ * Alternate function AF1
*/
#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */
#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */
#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF2 Alternate function AF2
- * @{
+ /*
+ * Alternate function AF2
*/
#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */
#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */
#define GPIO_AF2_USB ((uint8_t)0x02) /* USB Alternate Function mapping */
-#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */
+#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF3 Alternate function AF3
- * @{
+/*
+ * Alternate function AF3
*/
#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF4 Alternate function AF4
- * @{
+/*
+ * Alternate function AF4
*/
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
@@ -1530,11 +1591,11 @@
#define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */
#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF5 Alternate function AF5
- * @{
+/*
+ * Alternate function AF5
*/
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */
@@ -1542,25 +1603,29 @@
#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */
#define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF6 Alternate function AF6
- * @{
+/*
+ * Alternate function AF6
*/
#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */
#define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF7 Alternate function AF7
- * @{
+/*
+ * Alternate function AF7
*/
#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */
#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */
/**
+ *
+ */
+
+/**
* @}
*/
@@ -1568,7 +1633,13 @@
* @}
*/
+/** @defgroup GPIOEx_Private GPIOEx Private
+ * @{
+ */
+/**
+ * @brief IS_GPIO_AF macro definition
+ */
#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF2_SPI2) || \
((__AF__) == GPIO_AF0_SPI2) || ((__AF__) == GPIO_AF2_LPUART1) || \
((__AF__) == GPIO_AF0_USART1) || ((__AF__) == GPIO_AF7_COMP1) || \
@@ -1611,7 +1682,9 @@
((__AF__) == GPIO_AF2_LPUART1))) || \
(((__INSTANCE__) == GPIOD) && (((__AF__) == GPIO_AF0_LPUART1))))
-
+ /**
+ * @}
+ */
#endif /* STM32L051xx/STM32L061xx*/
/*------------------------------------------------------------------------------------------*/
@@ -1633,10 +1706,10 @@
* PA5 |SPI1 |LPTIM1 |TIM2_TR | | |TIM2_C1 | | |
* PA6 |SPI1 |LPTIM1 | | |LPUART |TIM22_C1|EVENTOUT|COMP1 |
* PA7 |SPI1 |LPTIM1 | | |USART2 |TIM22_C2|EVENTOUT|COMP2 |
- * PA8 |MCO | |LPTIM1 |EVENTOUT|USART2 | | | |
+ * PA8 |MCO | |LPTIM1 |EVENTOUT|USART2 |TIM2_C1 | | |
* PA9 |MCO |I2C1 | | |USART2 |TIM22_C1| | |
* PA10| |I2C1 | | |USART2 |TIM22_C2| | |
- * PA11|SPI1 | |EVENTOUT| |USART2 | | |COMP1 |
+ * PA11|SPI1 | |EVENTOUT| |USART2 |TIM21_C2| |COMP1 |
* PA12|SPI1 | |EVENTOUT| |USART2 | | |COMP2 |
* PA13|SWDIO |LPTIM1 | | | | |LPUART1 | |
* PA14|SWCLK |LPTIM1 | |I2C1 |USART2 | |LPUART1 | |
@@ -1648,7 +1721,7 @@
* PB3 |SPI1 | |TIM2_C2 | |EVENTOUT| | | |
* PB4 |SPI1 | |EVENTOUT| |TIM22_C1| | | |
* PB5 |SPI1 | |LPTIM1_I|I2C1 |TIM22_C2| | | |
- * PB6 |USART2 |I2C1 |LPTIM1_T| | | | | |
+ * PB6 |USART2 |I2C1 |LPTIM1_T| | |TIM21_C1| | |
* PB7 |USART2 |I2C1 |LPTIM1_I| | | | | |
* PB8 | | | | |I2C1 | | | |
* PB9 | | |EVENTOUT| |I2C1 | | | |
@@ -1660,7 +1733,6 @@
* PB15|SPI2 | |RTC | | | | | |
*_____________________________________________________________________________|
* PC0 |LPTIM1_I| |EVENTOUT| | | |LPUART1 | |
- * PC1 | | | | | | | | |
* PC13| | | | | | | | |
* PC14| | | | | | | | |
* PC15| | | | | | | | |
@@ -1674,8 +1746,8 @@
* @{
*/
-/** @defgroup GPIOEx_Alternate_function_AF0 Alternate function AF0
- * @{
+/*
+ * Alternate function AF0
*/
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */
#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */
@@ -1686,41 +1758,42 @@
#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */
#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF1 Alternate function AF1
- * @{
+/*
+ * Alternate function AF1
*/
#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */
#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
/**
- * @}
+ *
*/
- /** @defgroup GPIOEx_Alternate_function_AF2 Alternate function AF2
- * @{
+/*
+ * Alternate function AF2
*/
#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_MCO ((uint8_t)0x02) /* MCO Alternate Function mapping */
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */
-#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */
+#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF3 Alternate function AF3
- * @{
+/*
+ * Alternate function AF3
*/
#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF4 Alternate function AF4
- * @{
+/*
+ * Alternate function AF4
*/
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */
@@ -1728,34 +1801,38 @@
#define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */
#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF5 Alternate function AF5
- * @{
+/*
+ * Alternate function AF5
*/
#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */
#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */
#define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF6 Alternate function AF6
- * @{
+/*
+ * Alternate function AF6
*/
#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /* LPUART1 Alternate Function mapping */
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */
/**
- * @}
+ *
*/
-/** @defgroup GPIOEx_Alternate_function_AF7 Alternate function AF7
- * @{
+/*
+ * Alternate function AF7
*/
#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */
#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */
/**
+ *
+ */
+
+/**
* @}
*/
@@ -1763,6 +1840,13 @@
* @}
*/
+/** @defgroup GPIOEx_Private GPIOEx Private
+ * @{
+ */
+/**
+ * @brief IS_GPIO_AF macro definition
+ */
+
#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_EVENTOUT ) || \
((__AF__) == GPIO_AF0_TIM21 ) || \
((__AF__) == GPIO_AF0_SPI1 ) || \
@@ -1776,6 +1860,7 @@
((__AF__) == GPIO_AF1_LPTIM1 ) || \
((__AF__) == GPIO_AF2_LPTIM1 ) || \
((__AF__) == GPIO_AF2_TIM2 ) || \
+ ((__AF__) == GPIO_AF2_MCO ) || \
((__AF__) == GPIO_AF2_EVENTOUT ) || \
((__AF__) == GPIO_AF2_RTC ) || \
((__AF__) == GPIO_AF3_I2C1 ) || \
@@ -1793,28 +1878,241 @@
((__AF__) == GPIO_AF7_COMP1 ) || \
((__AF__) == GPIO_AF7_COMP2 ))
-
-#define IS_GPIO_AF_AVAILABLE(__INSTANCE__,__AF__) \
- (1)
+ #define IS_GPIO_AF_AVAILABLE(__INSTANCE__,__AF__) \
+ ((((__INSTANCE__) == GPIOA) && (((__AF__) == GPIO_AF0_EVENTOUT) || \
+ ((__AF__) == GPIO_AF1_LPTIM1) || \
+ ((__AF__) == GPIO_AF2_TIM2) || \
+ ((__AF__) == GPIO_AF3_I2C1) || \
+ ((__AF__) == GPIO_AF4_USART2) || \
+ ((__AF__) == GPIO_AF5_TIM22) || \
+ ((__AF__) == GPIO_AF6_LPUART1) || \
+ ((__AF__) == GPIO_AF7_COMP2))) || \
+ (((__INSTANCE__) == GPIOB) && (((__AF__) == GPIO_AF0_EVENTOUT) || \
+ ((__AF__) == GPIO_AF1_SPI1) || \
+ ((__AF__) == GPIO_AF2_LPTIM1) || \
+ ((__AF__) == GPIO_AF3_I2C1) || \
+ ((__AF__) == GPIO_AF4_LPUART1) || \
+ ((__AF__) == GPIO_AF5_TIM2) || \
+ ((__AF__) == GPIO_AF6_EVENTOUT))) || \
+ (((__INSTANCE__) == GPIOC) && (((__AF__) == GPIO_AF0_LPTIM1) || \
+ ((__AF__) == GPIO_AF2_EVENTOUT) || \
+ ((__AF__) == GPIO_AF6_LPUART1))))
+/**
+ * @}
+ */
#endif /* STM32L031xx/STM32L041xx*/
/*------------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------*/
+/*------------------------- STM32L011xx/STM32L021xx---------------------------*/
+/*----------------------------------------------------------------------------*/
+#if defined (STM32L011xx)|| defined (STM32L021xx)
+/* The table below gives an overview of the different alternate functions per port.
+ * For more details refer yourself to the product data sheet.
+ *
+ */
+/* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 |
+ *______________________________________________________________________________________
+ * PA0 |USART2_RX|LPTIM1_IN1|TIM2_C1 | |USART2_CTS|TIM2_ETR|LPUART1_RX |COMP1_OUT|
+ * PA1 |EVENTOUT |LPTIM1_IN2|TIM2_C2 |I2C1 |USART2_RTS|TIM21_TR|LPUART1_TX | |
+ * PA2 |TIM21_C1 | |TIM2_C3 | |USART2_TX | |LPUART1_TX |COMP2_OUT|
+ * PA3 |TIM21_C2 | |TIM2_C4 | |USART2_RX | |LPUART1_RX | |
+ * PA4 |SPI1 |LPTIM1_IN1|LPTIM1_TR|I2C1_SCL|USART2_CK |TIM2_TR |LPUART1_TX |COMP2_OUT|
+ * PA5 |SPI1 |LPTIM1_IN2|TIM2_TR | | |TIM2_C1 | | |
+ * PA6 |SPI1 |LPTIM1_ETR| | |LPUART1_CT| |EVENTOUT |COMP1_OUT|
+ * PA7 |SPI1 |LPTIM1_OUT| | |USART2_CTS|TIM21_T |EVENTOUT |COMP2_OUT|
+ * PA8 |MCO | |LPTIM1_I1|EVENTOUT|USART2_CK |TIM2_C1 | | |
+ * PA9 |MCO |I2C1_SCL |LPTIM1_O | |USART2_TX |TIM21_C2| |COMP1_OUT|
+ * PA10|TIM21_C1 |I2C1_SDA |RTC_REFIN| |USART2_RX |TIM2_C3 | |COMP1_OUT|
+ * PA11|SPI1 |LPTIM1_OUT|EVENTOUT | |USART2_CTS|TIM21_C2| |COMP1_OUT|
+ * PA12|SPI1 | |EVENTOUT | |USART2_RTS| | |COMP2_OUT|
+ * PA13|SWDIO |LPTIM1_T | |I2C1_SDA| |SPI1 |LPUART1_RX |COMP1_OUT|
+ * PA14|SWCLK |LPTIM1_O | |I2C1_SMB|USART2_TX |SPI1 |LPUART1_TX |COMP2_OUT|
+ * PA15|SPI1 | |TIM2_TR |EVENTOUT|USART2_RX |TIM2_C1 | | |
+ *______________________________________________________________________________________ |
+ * PB0 |EVENTOUT |SPI1 |TIM2_C2 | |USART2_RTS|TIM2_C3 | | |
+ * PB1 |USART2_CK|SPI1 |LPTIM1_I1| |LPUART1_RT|TIM2_C4 | | |
+ * PB2 | | |LPTIM1_O | | | | | |
+ * PB3 |SPI1 | |TIM2_C2 | |EVENTOUT | | | |
+ * PB4 |SPI1 | |EVENTOUT | | | | | |
+ * PB5 |SPI1 | |LPTIM1_I1|I2C1 | |TIM21_C1| | |
+ * PB6 |USART2_TX|I2C1_SCL |LPTIM1_T | | |TIM2_C3 |LPUART1_TX | |
+ * PB7 |USART2_RX|I2C1 |LPTIM1_I2| | |TIM2_C4 |LPUART1_RX | |
+ * PB8 |USART2_TX| |EVENTOUT | |I2C1 |SPI1 | | |
+ * PB9 | | | | | | | | |
+ *______________________________________________________________________________________ |
+ * PC14| | | | | | | | |
+ * PC15| | | | | | | | |
+ *______________________________________________________________________________________ |
+ */
+
+/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection
+ * @{
+ */
+
+/*
+ * Alternate function AF0
+ */
+#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */
+#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */
+#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */
+#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */
+#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF1
+ */
+#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */
+#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
+/**
+ *
+ */
+
+/* Alternate function AF2
+ *
+ */
+#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC Alternate Function mapping */
+#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF3
+ */
+#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */
+#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF4
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */
+#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */
+#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF5
+ */
+#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */
+#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF6
+ */
+#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /* LPUART1 Alternate Function mapping */
+#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */
+/**
+ *
+ */
+
+/*
+ * Alternate function AF7
+ */
+#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */
+#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */
+/**
+ *
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIOEx_Private GPIOEx Private
+ * @{
+ */
+/**
+ * IS_GPIO_AF macro definition
+ */
+
+#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_EVENTOUT ) || \
+ ((__AF__) == GPIO_AF0_TIM21 ) || \
+ ((__AF__) == GPIO_AF0_SPI1 ) || \
+ ((__AF__) == GPIO_AF0_USART2 ) || \
+ ((__AF__) == GPIO_AF0_MCO ) || \
+ ((__AF__) == GPIO_AF0_SWDIO ) || \
+ ((__AF__) == GPIO_AF0_SWCLK ) || \
+ ((__AF__) == GPIO_AF1_SPI1 ) || \
+ ((__AF__) == GPIO_AF1_I2C1 ) || \
+ ((__AF__) == GPIO_AF1_LPTIM1 ) || \
+ ((__AF__) == GPIO_AF2_LPTIM1 ) || \
+ ((__AF__) == GPIO_AF2_TIM2 ) || \
+ ((__AF__) == GPIO_AF2_EVENTOUT ) || \
+ ((__AF__) == GPIO_AF2_RTC ) || \
+ ((__AF__) == GPIO_AF3_I2C1 ) || \
+ ((__AF__) == GPIO_AF3_EVENTOUT ) || \
+ ((__AF__) == GPIO_AF4_I2C1 ) || \
+ ((__AF__) == GPIO_AF4_USART2 ) || \
+ ((__AF__) == GPIO_AF4_LPUART1 ) || \
+ ((__AF__) == GPIO_AF4_EVENTOUT ) || \
+ ((__AF__) == GPIO_AF5_TIM2 ) || \
+ ((__AF__) == GPIO_AF5_TIM21 ) || \
+ ((__AF__) == GPIO_AF5_SPI1 ) || \
+ ((__AF__) == GPIO_AF6_LPUART1 ) || \
+ ((__AF__) == GPIO_AF6_EVENTOUT ) || \
+ ((__AF__) == GPIO_AF7_COMP1 ) || \
+ ((__AF__) == GPIO_AF7_COMP2 ))
+
+
+ #define IS_GPIO_AF_AVAILABLE(__INSTANCE__,__AF__) \
+ ((((__INSTANCE__) == GPIOA) && (((__AF__) == GPIO_AF0_EVENTOUT) || \
+ ((__AF__) == GPIO_AF1_LPTIM1) || \
+ ((__AF__) == GPIO_AF2_TIM2) || \
+ ((__AF__) == GPIO_AF3_I2C1) || \
+ ((__AF__) == GPIO_AF4_USART2) || \
+ ((__AF__) == GPIO_AF5_TIM2) || \
+ ((__AF__) == GPIO_AF6_LPUART1) || \
+ ((__AF__) == GPIO_AF7_COMP2))) || \
+ (((__INSTANCE__) == GPIOB) && (((__AF__) == GPIO_AF0_EVENTOUT) || \
+ ((__AF__) == GPIO_AF1_SPI1) || \
+ ((__AF__) == GPIO_AF2_LPTIM1) || \
+ ((__AF__) == GPIO_AF3_I2C1) || \
+ ((__AF__) == GPIO_AF4_LPUART1) || \
+ ((__AF__) == GPIO_AF5_TIM2) || \
+ ((__AF__) == GPIO_AF6_EVENTOUT))))
+
+ /**
+ * @}
+ */
+
+#endif /* STM32L011xx/STM32L021xx*/
+/*------------------------------------------------------------------------------------------*/
+
#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
- ((__GPIOx__) == (GPIOB))? 1U :\
- ((__GPIOx__) == (GPIOC))? 2U :\
- ((__GPIOx__) == (GPIOD))? 3U :\
- ((__GPIOx__) == (GPIOE))? 4U :\
- ((__GPIOx__) == (GPIOH))? 5U : 6U)
-
-/** @defgroup GPIOEx_Pin_Available Pin available
+ /** @addtogroup GPIOEx_Exported_Constants
+ * @{
+ */
+ /** @defgroup GPIOEx_Pin_Available Pin available
* @{
*/
#define GPIOA_PIN_AVAILABLE GPIO_PIN_All
@@ -1826,6 +2124,19 @@
/**
* @}
*/
+/**
+ * @}
+ */
+
+ /** @addtogroup GPIOEx_Private
+ * @{
+ */
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOH))? 5U : 6U)
#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \
((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
@@ -1834,24 +2145,37 @@
(((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \
(((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \
(((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))
-
+/**
+ * @}
+ */
#elif defined (STM32L031xx) || defined (STM32L041xx)
+/** @addtogroup GPIOEx_Exported_Constants
+ * @{
+ */
+/** @defgroup GPIOEx_Pin_Available Pin available
+ * @{
+ */
+
+#define GPIOA_PIN_AVAILABLE GPIO_PIN_All
+#define GPIOB_PIN_AVAILABLE GPIO_PIN_All
+#define GPIOC_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)
+#define GPIOH_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1)
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup GPIOEx_Private
+ * @{
+ */
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\
((__GPIOx__) == (GPIOH))? 5U : 6U)
-/** @defgroup GPIOEx_Pin_Available Pin available
- * @{
- */
-#define GPIOA_PIN_AVAILABLE GPIO_PIN_All
-#define GPIOB_PIN_AVAILABLE GPIO_PIN_All
-#define GPIOC_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)
-#define GPIOH_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1)
-/**
- * @}
- */
#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \
((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
@@ -1859,15 +2183,53 @@
(((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
(((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))
+/**
+ * @}
+ */
+
+#elif defined (STM32L011xx) || defined (STM32L021xx)
+
+/** @addtogroup GPIOEx_Exported_Constants
+ * @{
+ */
+/** @defgroup GPIOEx_Pin_Available Pin available
+ * @{
+ */
+
+#define GPIOA_PIN_AVAILABLE GPIO_PIN_All
+#define GPIOB_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
+ GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 )
+#define GPIOC_PIN_AVAILABLE (GPIO_PIN_14 | GPIO_PIN_15)
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup GPIOEx_Private
+ * @{
+ */
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U : 6U)
+
+
+#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \
+ ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
+ (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
+ (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))))
+/**
+ * @}
+ */
+
#elif defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
- ((__GPIOx__) == (GPIOB))? 1U :\
- ((__GPIOx__) == (GPIOC))? 2U :\
- ((__GPIOx__) == (GPIOD))? 3U :\
- ((__GPIOx__) == (GPIOH))? 5U : 6U)
-
+/** @addtogroup GPIOEx_Exported_Constants
+ * @{
+ */
/** @defgroup GPIOEx_Pin_Available Pin available
* @{
*/
@@ -1879,6 +2241,18 @@
/**
* @}
*/
+/**
+ * @}
+ */
+
+/** @addtogroup GPIOEx_Private
+ * @{
+ */
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOH))? 5U : 6U)
#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \
((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
@@ -1886,16 +2260,14 @@
(((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
(((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \
(((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))
-
+/**
+ * @}
+ */
#endif /* STM32L083xx || STM32L082xx || STM32L081xx || STM32L073xx || STM32L072xx || STM32L071xx*/
/**
- * @}
- */
-
-/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -151,7 +151,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -185,16 +185,16 @@
* @{
*/
-/** @defgroup I2C I2C
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/** @addtogroup I2C I2C
* @brief I2C HAL module driver
* @{
*/
-#ifdef HAL_I2C_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @addtogroup I2C_Private_Constants I2C Private Constants
+/** @addtogroup I2C_Private
* @{
*/
#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! I2C TIMING clear register Mask */
@@ -214,7 +214,7 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup I2C_Private_Functions I2C Private Functions
+/** @addtogroup I2C_Private
* @{
*/
static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
@@ -246,11 +246,11 @@
/* Exported functions --------------------------------------------------------*/
-/** @defgroup I2C_Exported_Functions I2C Exported Functions
+/** @addtogroup I2C_Exported_Functions
* @{
*/
-/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup I2C_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
@@ -308,6 +308,9 @@
if(hi2c->State == HAL_I2C_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hi2c->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
}
@@ -405,6 +408,9 @@
*/
__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2C_MspInit could be implemented in the user file
*/
@@ -418,6 +424,9 @@
*/
__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2C_MspDeInit could be implemented in the user file
*/
@@ -427,7 +436,7 @@
* @}
*/
-/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+/** @addtogroup I2C_Exported_Functions_Group2
* @brief Data transfers functions
*
@verbatim
@@ -553,7 +562,7 @@
if((sizetmp == 0)&&(Size!=0))
{
- /* Wait until TXE flag is set */
+ /* Wait until TCR flag is set */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
@@ -655,9 +664,16 @@
do
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK)
{
- return HAL_TIMEOUT;
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
}
/* Write data to RXDR */
@@ -902,6 +918,14 @@
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from RXDR */
+ (*pData++) = hi2c->Instance->RXDR;
+ }
+
if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
{
return HAL_TIMEOUT;
@@ -1270,6 +1294,9 @@
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ /* Abort DMA */
+ HAL_DMA_Abort(hi2c->hdmatx);
+
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
@@ -1356,11 +1383,20 @@
}
/* Wait until RXNE flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK)
{
- return HAL_TIMEOUT;
+ /* Abort DMA */
+ HAL_DMA_Abort(hi2c->hdmarx);
+
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
}
-
/* Enable DMA Request */
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
@@ -2328,7 +2364,7 @@
* @}
*/
-/** @defgroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+/** @addtogroup IRQ_Handler_and_Callbacks
* @{
*/
@@ -2430,6 +2466,9 @@
*/
__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2C_TxCpltCallback could be implemented in the user file
*/
@@ -2443,6 +2482,9 @@
*/
__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2C_TxCpltCallback could be implemented in the user file
*/
@@ -2455,6 +2497,9 @@
*/
__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2C_TxCpltCallback could be implemented in the user file
*/
@@ -2468,6 +2513,9 @@
*/
__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2C_TxCpltCallback could be implemented in the user file
*/
@@ -2481,6 +2529,9 @@
*/
__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2C_TxCpltCallback could be implemented in the user file
*/
@@ -2494,6 +2545,9 @@
*/
__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2C_TxCpltCallback could be implemented in the user file
*/
@@ -2507,6 +2561,9 @@
*/
__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2C_ErrorCallback could be implemented in the user file
*/
@@ -2517,7 +2574,7 @@
*/
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
+/** @addtogroup I2C_Exported_Functions_Group3
* @brief Peripheral State and Errors functions
*
@verbatim
@@ -2562,7 +2619,7 @@
* @}
*/
-/** @addtogroup I2C_Private_Functions
+/** @addtogroup I2C_Private
* @{
*/
@@ -2632,7 +2689,14 @@
}
else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
{
- /* Disable ERR, TC, STOP, NACK, TXI interrupt */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ /* Disable ERR, TC, STOP, NACK, TXI interrupts */
__HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );
/* Clear STOP Flag */
@@ -2641,18 +2705,42 @@
/* Clear Configuration Register 2 */
__I2C_RESET_CR2(hi2c);
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
+ /* Flush TX register if not empty */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
{
- HAL_I2C_MemTxCpltCallback(hi2c);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+ }
+
+ /* Call the correct callback to inform upper layer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_ErrorCallback(hi2c);
}
else
{
- HAL_I2C_MasterTxCpltCallback(hi2c);
+ if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_MemTxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
}
}
else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
@@ -2739,7 +2827,14 @@
}
else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
{
- /* Disable ERR, TC, STOP, NACK, TXI interrupt */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ /* Disable ERR, TC, STOP, NACK, RXI interrupts */
__HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI );
/* Clear STOP Flag */
@@ -2748,18 +2843,36 @@
/* Clear Configuration Register 2 */
__I2C_RESET_CR2(hi2c);
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Call the correct callback to inform upper layer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
- {
- HAL_I2C_MemRxCpltCallback(hi2c);
+ HAL_I2C_ErrorCallback(hi2c);
}
else
{
- HAL_I2C_MasterRxCpltCallback(hi2c);
+ if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_MemRxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+ }
}
}
else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
@@ -2833,7 +2946,7 @@
/* communication with Master */
else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
{
- /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
+ /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupts */
__HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI );
/* Disable Address Acknowledge */
@@ -2903,8 +3016,8 @@
}
else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
{
- /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
- __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_RXI );
+ /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupts */
+ __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI );
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -3024,7 +3137,7 @@
/* Send Memory Address */
hi2c->Instance->TXDR = __I2C_MEM_ADD_LSB(MemAddress);
}
- /* If Mememory address size is 16Bit */
+ /* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
@@ -3954,6 +4067,11 @@
while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
{
+ /* Check if a NACK is detected */
+ if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Check if a STOPF is detected */
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
{
@@ -4037,6 +4155,11 @@
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ /* Flush TX register if not empty */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+ {
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+ }
/* Clear Configuration Register 2 */
__I2C_RESET_CR2(hi2c);
@@ -4064,7 +4187,7 @@
* @arg I2C_SOFTEND_MODE: Enable Software end mode.
* @param Request: new state of the I2C START condition generation.
* This parameter can be one of the following values:
- * @arg I2C_NO_STARTSTOP: Don't Generate stop and start condition.
+ * @arg I2C_NO_STARTSTOP: Do not Generate stop and start condition.
* @arg I2C_GENERATE_STOP: Generate stop condition (Size should be set to 0).
* @arg I2C_GENERATE_START_READ: Generate Restart for read request.
* @arg I2C_GENERATE_START_WRITE: Generate Restart for write request.
@@ -4097,11 +4220,12 @@
* @}
*/
-#endif /* HAL_I2C_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_I2C_MODULE_ENABLED */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,7 +50,7 @@
* @{
*/
-/** @addtogroup I2C
+/** @defgroup I2C I2C
* @{
*/
@@ -420,15 +420,75 @@
* @}
*/
+/**
+ * @}
+ */
+
/* Include I2C HAL Extension module */
#include "stm32l0xx_hal_i2c_ex.h"
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_Exported_Functions
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_Private
* @{
*/
-/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
+ ((MASK) == I2C_OA2_MASK01) || \
+ ((MASK) == I2C_OA2_MASK02) || \
+ ((MASK) == I2C_OA2_MASK03) || \
+ ((MASK) == I2C_OA2_MASK04) || \
+ ((MASK) == I2C_OA2_MASK05) || \
+ ((MASK) == I2C_OA2_MASK06) || \
+ ((MASK) == I2C_OA2_MASK07))
+
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
+ ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+
+#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
+ ((MODE) == I2C_AUTOEND_MODE) || \
+ ((MODE) == I2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
+ ((REQUEST) == I2C_GENERATE_START_READ) || \
+ ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+ ((REQUEST) == I2C_NO_STARTSTOP))
+
+
+#define __I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+
+#define __I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
+#define __I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+#define __I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+/**
+ * @}
+ */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+ * @{
+ */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions******************************/
@@ -440,7 +500,7 @@
* @}
*/
-/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions ****************************************************/
@@ -472,7 +532,7 @@
* @}
*/
-/** @addtogroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+/** @defgroup IRQ_Handler_and_Callbacks RQ Handler and Callbacks
* @{
*/
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
@@ -489,7 +549,7 @@
* @}
*/
-/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
* @{
*/
/* Peripheral State and Errors functions *************************************/
@@ -504,77 +564,16 @@
* @}
*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
- * @{
- */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macro I2C Private Macros
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup I2C_Private I2C Private
* @{
*/
-
-#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
- ((MODE) == I2C_ADDRESSINGMODE_10BIT))
-
-#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
- ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
-
-#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
- ((MASK) == I2C_OA2_MASK01) || \
- ((MASK) == I2C_OA2_MASK02) || \
- ((MASK) == I2C_OA2_MASK03) || \
- ((MASK) == I2C_OA2_MASK04) || \
- ((MASK) == I2C_OA2_MASK05) || \
- ((MASK) == I2C_OA2_MASK06) || \
- ((MASK) == I2C_OA2_MASK07))
-
-#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
- ((CALL) == I2C_GENERALCALL_ENABLE))
-
-#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
- ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-
-#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
- ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-
-
-#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
- ((MODE) == I2C_AUTOEND_MODE) || \
- ((MODE) == I2C_SOFTEND_MODE))
-
-#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
- ((REQUEST) == I2C_GENERATE_START_READ) || \
- ((REQUEST) == I2C_GENERATE_START_WRITE) || \
- ((REQUEST) == I2C_NO_STARTSTOP))
-
-
-#define __I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
-
-#define __I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
-#define __I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-
-#define __I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
/**
* @}
- */
-
-/* Private Fonctions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
- * @{
*/
-/* Private functions are defined in stm32l0xx_hal_i2c.c file */
-/**
- * @}
- */
+/**************************************************************/
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c_ex.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c_ex.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_i2c_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
@@ -36,7 +36,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -69,14 +69,13 @@
/** @addtogroup STM32L0xx_HAL_Driver
* @{
*/
+#ifdef HAL_I2C_MODULE_ENABLED
-/** @defgroup I2CEx I2C Extended HAL module driver
+/** @addtogroup I2CEx
* @brief I2C Extended HAL module driver
* @{
*/
-#ifdef HAL_I2C_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -84,11 +83,11 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+/** @addtogroup I2CEx_Exported_Functions
* @{
*/
-/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
+/** @addtogroup I2CEx_Exported_Functions_Group1
* @brief Extended features functions
*
@verbatim
@@ -178,7 +177,7 @@
tmpreg = hi2c->Instance->CR1;
/* Reset I2Cx DNF bits [11:8] */
- tmpreg &= ~(I2C_CR1_DFN);
+ tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8;
@@ -335,11 +334,12 @@
* @}
*/
-#endif /* HAL_I2C_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_I2C_MODULE_ENABLED */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_i2c_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of I2C HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,18 +50,18 @@
* @{
*/
-/** @addtogroup I2CEx
+/** @defgroup I2CEx I2CEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2CEx_Exported_Constants
+/** @defgroup I2CEx_Exported_Constants I2CEx Exported Constants
* @{
*/
-/** @defgroup I2CEx_Analog_Filter
+/** @defgroup I2CEx_Analog_Filter I2C Analog Filter Enabling
* @{
*/
#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
@@ -70,7 +70,7 @@
* @}
*/
-/** @defgroup I2CEx_FastModePlus
+/** @defgroup I2CEx_FastModePlus I2C Fast Mode Plus
* @{
*/
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
@@ -78,7 +78,7 @@
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR2_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
-#if !defined(STM32L031xx) && !defined(STM32L041xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR2_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#endif
#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
@@ -94,26 +94,31 @@
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Functions I2CEx Exported Functions
+ * @{
+ */
/* Peripheral Control methods ************************************************/
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended Features Functions
+ * @{
+ */
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
- * @{
- */
+/**
+ * @}
+ */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macro I2C Private Macros
+/** @defgroup I2CEx_Private I2CEx Private
* @{
*/
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
@@ -121,7 +126,7 @@
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
-#if defined(STM32L031xx) || defined(STM32L041xx)
+#if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L011xx) || defined(STM32L021xx)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
@@ -147,14 +152,15 @@
* @}
*/
-/* Private Fonctions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup I2CEx_Private I2CEx Private
* @{
*/
-/* Private functions are defined in stm32l0xx_hal_i2c_ex.c file */
/**
* @}
*/
+/**************************************************************/
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_i2s.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -108,7 +108,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -135,16 +135,17 @@
******************************************************************************
*/
-#if !defined(STM32L031xx) && !defined(STM32L041xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal.h"
-#ifdef HAL_I2S_MODULE_ENABLED
/** @addtogroup STM32L0xx_HAL_Driver
* @{
*/
-/** @defgroup I2S I2S
+#ifdef HAL_I2S_MODULE_ENABLED
+
+/** @addtogroup I2S I2S
* @brief I2S HAL module driver
* @{
*/
@@ -156,7 +157,7 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup I2S_Private_Functions I2S Private Functions
+/** @addtogroup I2S_Private
* @{
*/
static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
@@ -172,11 +173,11 @@
*/
/* Exported functions ---------------------------------------------------------*/
-/** @defgroup I2S_Exported_Functions I2S Exported Functions
+/** @addtogroup I2S_Exported_Functions I2S Exported Functions
* @{
*/
-/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup I2S_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
@@ -233,6 +234,9 @@
if(hi2s->State == HAL_I2S_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hi2s->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2S_MspInit(hi2s);
}
@@ -375,6 +379,9 @@
*/
__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspInit could be implemented in the user file
*/
@@ -388,6 +395,9 @@
*/
__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspDeInit could be implemented in the user file
*/
@@ -397,7 +407,7 @@
* @}
*/
-/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
+/** @addtogroup I2S_Exported_Functions_Group2
* @brief Data transfers functions
*
@verbatim
@@ -507,12 +517,16 @@
{
return HAL_TIMEOUT;
}
- /* Wait until Busy flag is reset */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
+
+ /* Check if Slave mode is selected */
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
+ {
+ /* Wait until Busy flag is reset */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
}
-
hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
@@ -1090,6 +1104,9 @@
*/
__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
*/
@@ -1103,6 +1120,9 @@
*/
__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxCpltCallback could be implemented in the user file
*/
@@ -1116,6 +1136,9 @@
*/
__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
*/
@@ -1129,6 +1152,9 @@
*/
__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_RxCpltCallback could be implemented in the user file
*/
@@ -1142,6 +1168,9 @@
*/
__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_ErrorCallback could be implemented in the user file
*/
@@ -1151,7 +1180,7 @@
* @}
*/
-/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+/** @addtogroup I2S_Exported_Functions_Group3
* @brief Peripheral State functions
*
@verbatim
@@ -1196,7 +1225,7 @@
*/
/* Private functions ---------------------------------------------------------*/
-/** @addtogroup I2S_Private_Functions I2S Private Functions
+/** @addtogroup I2S_Private
* @{
*/
/**
@@ -1397,13 +1426,13 @@
/**
* @}
*/
+#endif /* HAL_I2S_MODULE_ENABLED */
/**
* @}
*/
-#endif /* HAL_I2S_MODULE_ENABLED */
-#endif /* #if !defined(STM32L031xx) && !defined(STM32L041xx) */
+#endif /* #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_i2s.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,7 +43,7 @@
extern "C" {
#endif
-#if !defined (STM32L031xx) && !defined (STM32L041xx)
+#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L011xx) && !defined (STM32L021xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal_def.h"
@@ -51,7 +51,7 @@
* @{
*/
-/** @addtogroup I2S
+/** @defgroup I2S I2S
* @{
*/
@@ -270,7 +270,7 @@
*/
/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_macros I2S Exported Macros
+/** @defgroup I2S_Exported_Macros I2S Exported Macros
* @{
*/
@@ -358,11 +358,11 @@
*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_Exported_Functions
+/** @defgroup I2S_Exported_Functions I2S Exported Functions
* @{
*/
-/** @addtogroup I2S_Exported_Functions_Group1
+/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
@@ -374,7 +374,7 @@
* @}
*/
-/** @addtogroup I2S_Exported_Functions_Group2
+/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
* @{
*/
/* I/O operation functions ***************************************************/
@@ -405,7 +405,7 @@
* @}
*/
-/** @addtogroup I2S_Exported_Functions_Group3
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral Control and State functions
* @{
*/
/* Peripheral Control and State functions ************************************/
@@ -420,7 +420,7 @@
*/
/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_Private_Macros I2S Private Macros
+/** @defgroup I2S_Private I2S Private
* @{
*/
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
@@ -452,11 +452,16 @@
* @}
*/
-/* Private Fonctions ---------------------------------------------------------*/
-/** @defgroup I2S_Private_Functions I2S Private Functions
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup I2S_Private I2S Private
* @{
*/
-/* Private functions are defined in stm32f1xx_hal_i2s.c file */
+/**
+ * @}
+ */
+/**************************************************************/
+
/**
* @}
*/
@@ -465,15 +470,12 @@
* @}
*/
-/**
- * @}
- */
+#endif /* !STM32L031xx && !STM32L041xx && !STM32L011xx && !STM32L021xx */
+
#ifdef __cplusplus
}
#endif
-#endif /* !STM32L031xx && !STM32L041xx */
-
#endif /* __STM32L0xx_HAL_I2S_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_irda.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief IRDA HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -101,7 +101,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -135,12 +135,16 @@
* @{
*/
+#ifdef HAL_IRDA_MODULE_ENABLED
+
/** @addtogroup IRDA
* @brief IRDA HAL module driver
* @{
*/
-#ifdef HAL_IRDA_MODULE_ENABLED
-
+
+/** @addtogroup IRDA_Private
+ * @{
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define TEACK_REACK_TIMEOUT 1000
@@ -161,8 +165,9 @@
static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
-/* Private functions ---------------------------------------------------------*/
-
+/**
+ * @}
+ */
/** @addtogroup IRDA_Exported_Functions
* @{
*/
@@ -232,6 +237,9 @@
if(hirda->State == HAL_IRDA_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hirda->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, CORTEX */
HAL_IRDA_MspInit(hirda);
}
@@ -299,6 +307,9 @@
*/
__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_IRDA_MspInit could be implented in the user file
*/
@@ -311,6 +322,9 @@
*/
__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_IRDA_MspDeInit could be implented in the user file
*/
@@ -957,6 +971,9 @@
*/
__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file
*/
@@ -969,6 +986,9 @@
*/
__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_TxCpltCallback can be implemented in the user file
*/
@@ -981,6 +1001,9 @@
*/
__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file
*/
@@ -993,6 +1016,9 @@
*/
__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_RxCpltCallback can be implemented in the user file
*/
@@ -1005,6 +1031,9 @@
*/
__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_ErrorCallback can be implemented in the user file
*/
@@ -1055,6 +1084,13 @@
*/
/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Private
+ * @{
+ */
+/**
* @brief Configure the IRDA peripheral
* @param hirda: irda handle
* @retval None
@@ -1452,11 +1488,11 @@
* @}
*/
-#endif /* HAL_IRDA_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_IRDA_MODULE_ENABLED */
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_irda.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,6 +54,9 @@
* @{
*/
+ /** @defgroup IRDA_Exported_Types IRDA Exported Types
+ * @{
+ */
/* Exported types ------------------------------------------------------------*/
/**
@@ -76,7 +79,7 @@
word length is set to 8 data bits). */
uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref IRDA_Mode */
+ This parameter can be a value of @ref IRDA_Transfer_Mode */
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
to achieve low-power frequency.
@@ -101,28 +104,8 @@
HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */
}HAL_IRDA_StateTypeDef;
-/**
- * @brief HAL IRDA Error Code definition
- */
-
-#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_IRDA_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
-#define HAL_IRDA_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
-#define HAL_IRDA_ERROR_FE ((uint32_t)0x04) /*!< frame error */
-#define HAL_IRDA_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
-#define HAL_IRDA_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
-/**
- * @brief IRDA clock sources definition
- */
-typedef enum
-{
- IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
- IRDA_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
- IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
- IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
- IRDA_CLOCKSOURCE_LSE = 0x08 /*!< LSE clock source */
-}IRDA_ClockSourceTypeDef;
+
/**
* @brief IRDA handle Structure definition
@@ -159,6 +142,10 @@
}IRDA_HandleTypeDef;
+/**
+ * @}
+ */
+
/**
* @brief IRDA Configuration enumeration values definition
*/
@@ -168,6 +155,29 @@
* @{
*/
+/**
+ * @brief HAL IRDA Error Code definition
+ */
+
+#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_IRDA_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
+#define HAL_IRDA_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
+#define HAL_IRDA_ERROR_FE ((uint32_t)0x04) /*!< frame error */
+#define HAL_IRDA_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
+
+/**
+ * @brief IRDA clock sources definition
+ */
+typedef enum
+{
+ IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
+ IRDA_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
+ IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
+ IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
+ IRDA_CLOCKSOURCE_LSE = 0x08 /*!< LSE clock source */
+}IRDA_ClockSourceTypeDef;
+
/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
@@ -264,18 +274,18 @@
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
-#define IRDA_FLAG_REACK ((uint32_t)0x00400000)
-#define IRDA_FLAG_TEACK ((uint32_t)0x00200000)
-#define IRDA_FLAG_BUSY ((uint32_t)0x00010000)
-#define IRDA_FLAG_ABRF ((uint32_t)0x00008000)
-#define IRDA_FLAG_ABRE ((uint32_t)0x00004000)
-#define IRDA_FLAG_TXE ((uint32_t)0x00000080)
-#define IRDA_FLAG_TC ((uint32_t)0x00000040)
-#define IRDA_FLAG_RXNE ((uint32_t)0x00000020)
-#define IRDA_FLAG_ORE ((uint32_t)0x00000008)
-#define IRDA_FLAG_NE ((uint32_t)0x00000004)
-#define IRDA_FLAG_FE ((uint32_t)0x00000002)
-#define IRDA_FLAG_PE ((uint32_t)0x00000001)
+#define IRDA_FLAG_REACK USART_ISR_REACK /*!< Receive Enable Acknowledge Flag */
+#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< Transmit Enable Acknowledge Flag */
+#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< Busy Flag */
+#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< Auto-Baud Rate Flag */
+#define IRDA_FLAG_ABRE USART_ISR_ABRE /*!< Auto-Baud Rate Error */
+#define IRDA_FLAG_TXE USART_ISR_TXE /*!< Transmit Data Register Empty */
+#define IRDA_FLAG_TC USART_ISR_TC /*!< Transmission Complete */
+#define IRDA_FLAG_RXNE USART_ISR_RXNE /*!< Read Data Register Not Empty */
+#define IRDA_FLAG_ORE USART_ISR_ORE /*!< OverRun Error */
+#define IRDA_FLAG_NE USART_ISR_NE /*!< Noise detected Flag */
+#define IRDA_FLAG_FE USART_ISR_FE /*!< Framing Error */
+#define IRDA_FLAG_PE USART_ISR_PE /*!< Parity Error */
/**
* @}
*/
@@ -396,7 +406,8 @@
* @arg IRDA_CLEAR_IDLEF
* @retval None
*/
-#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ~(__FLAG__))
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
/** @brief Clear the IRDA PE pending flag.
* @param __HANDLE__: specifies the IRDA Handle.
@@ -650,7 +661,17 @@
/**
* @}
- */
+ */
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup IRDA_Private IRDA Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_irda_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of IRDA HAL Extension module.
******************************************************************************
* @attention
@@ -50,22 +50,22 @@
* @{
*/
-/** @addtogroup IRDAEx
+/** @defgroup IRDAEx IRDAEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDAEx_Extended_Exported_Constants IRDA Extended Exported Constants
+/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Exported Constants
* @{
*/
/** @defgroup IRDAEx_Word_Length IRDAEx Word length
* @{
*/
-#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
+#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
-#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
+#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \
((LENGTH) == IRDA_WORDLENGTH_8B) || \
((LENGTH) == IRDA_WORDLENGTH_9B))
@@ -80,7 +80,7 @@
/* Exported macro ------------------------------------------------------------*/
-/** @defgroup IRDAEx_Extended_Exported_Macros IRDA Extended Exported Macros
+/** @defgroup IRDAEx_Extended_Exported_Macros IRDAEx Exported Macros
* @{
*/
/** @brief Reports the IRDA clock source.
@@ -88,7 +88,7 @@
* @param __CLOCKSOURCE__ : output variable
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
*/
-#if defined (STM32L031xx) || defined (STM32L041xx)
+#if defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART2) \
@@ -133,7 +133,7 @@
} \
} while(0)
-#else /* (STM32L031xx) || defined (STM32L041xx) */
+#else /* (STM32L031xx) || defined (STM32L041xx) || (STM32L011xx) || defined (STM32L021xx) */
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
@@ -198,7 +198,7 @@
} \
} \
} while(0)
-#endif /* (STM32L031xx) || (STM32L041xx) */
+#endif /* (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || (STM32L021xx) */
/** @brief Reports the mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
@@ -251,7 +251,6 @@
/* Peripheral Control methods ************************************************/
/* Peripheral State methods **************************************************/
-
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_iwdg.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_iwdg.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_iwdg.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
@@ -84,7 +84,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -118,18 +118,24 @@
* @{
*/
+#ifdef HAL_IWDG_MODULE_ENABLED
+
/** @addtogroup IWDG
* @brief IWDG HAL module driver.
* @{
*/
-#ifdef HAL_IWDG_MODULE_ENABLED
-
+/** @addtogroup IWDG_Private
+ * @{
+ */
/* TimeOut value */
#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000
/* Local define used to check the SR status register */
#define IWDG_SR_FLAGS (IWDG_FLAG_PVU | IWDG_FLAG_RVU | IWDG_FLAG_WVU)
+/**
+ * @}
+ */
/** @addtogroup IWDG_Exported_Functions
* @{
@@ -187,6 +193,9 @@
if(hiwdg->State == HAL_IWDG_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hiwdg->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware */
HAL_IWDG_MspInit(hiwdg);
}
@@ -237,6 +246,9 @@
*/
__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hiwdg);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_IWDG_MspInit could be implemented in the user file
*/
@@ -396,11 +408,12 @@
* @}
*/
-#endif /* HAL_IWDG_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_iwdg.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_iwdg.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_iwdg.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,7 +50,7 @@
* @{
*/
-/** @defgroup IWDG
+/** @defgroup IWDG IWDG
* @{
*/
@@ -161,10 +161,6 @@
/**
* @}
*/
-#define IS_IWDG_FLAG(__FLAG__) (((__FLAG__) == IWDG_FLAG_PVU) || \
- ((__FLAG__) == IWDG_FLAG_RVU) || \
- ((__FLAG__) == IWDG_FLAG_WVU))
-
/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
@@ -206,7 +202,7 @@
* @}
*/
/* Exported macro ------------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Macro IWDG Exported Macro
+/** @defgroup IWDG_Exported_Macro IWDG Exported Macros
* @{
*/
@@ -262,7 +258,7 @@
*/
/* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Functions
+/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
* @{
*/
@@ -296,6 +292,16 @@
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup IWDG_Private IWDG Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lcd.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lcd.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_lcd.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief LCD Controller HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LCD Controller (LCD) peripheral:
@@ -15,56 +15,52 @@
==============================================================================
##### How to use this driver #####
==============================================================================
- [..] The LCD HAL driver can be used as follows:
+ [..] The LCD HAL driver can be used as follow:
(#) Declare a LCD_HandleTypeDef handle structure.
- (#) Initialize the LCD low level resources by implement the HAL_LCD_MspInit() API:
- (##) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, proceed as follows:
- (+) Use RCC function HAL_RCCEx_PeriphCLKConfig in indicating RCC_PERIPHCLK_LCD and
- selected clock source (HSE, LSI or LSE)
-
- -@- The frequency generator allows you to achieve various LCD frame rates
- starting from an LCD input clock frequency (LCDCLK) which can vary
- from 32 kHz up to 1 MHz.
+ (#) Prepare the initialization of the LCD low level resources by implementing your HAL_LCD_MspInit() API:
+ (##) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, use the RCC function
+ HAL_RCCEx_PeriphCLKConfig, indicating here RCC_PERIPHCLK_LCD and the selected clock
+ source (HSE, LSI or LSE)
+ (##) The frequency generator allows you to achieve various LCD frame rates starting from an
+ LCD input clock frequency (LCDCLK) which can vary from 32 kHz up to 1 MHz.
(##) LCD pins configuration:
- (+) Enable the clock for the LCD GPIOs.
- (+) Configure these LCD pins as alternate function no-pull.
+ - Enable the clock for the LCD GPIOs
+ - Configure these LCD pins as alternate function no-pull.
(##) Enable the LCD interface clock.
- (#) Program the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias,
- Voltage Source, Dead Time, Pulse On Duration and Contrast in the hlcd Init structure.
+ (#) Set the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias, Voltage Source,
+ Dead Time, Pulse On Duration and Contrast in the hlcd Init structure.
(#) Initialize the LCD registers by calling the HAL_LCD_Init() API.
-
- -@- The HAL_LCD_Init() API configures also the low level Hardware GPIO, CLOCK, ...etc)
- by calling the custumed HAL_LCD_MspInit() API.
- -@- After calling the HAL_LCD_Init() the LCD RAM memory is cleared
+ (##) The HAL_LCD_Init() API configures the low level Hardware (GPIO, CLOCK, ...etc)
+ by calling the user customized HAL_LCD_MspInit() API.
+ (#) After calling the HAL_LCD_Init() the LCD RAM memory is cleared
(#) Optionally you can update the LCD configuration using these macros:
- (+) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros
- (+) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro
- (+) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro
- (+) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro
- (+) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro
+ (##) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros
+ (##) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro
+ (##) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro
+ (##) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro
+ (##) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro
(#) Write to the LCD RAM memory using the HAL_LCD_Write() API, this API can be called
- more time to update the different LCD RAM registers before calling
+ several times to update the different LCD RAM registers before calling
HAL_LCD_UpdateDisplayRequest() API.
(#) The HAL_LCD_Clear() API can be used to clear the LCD RAM memory.
- (#) When LCD RAM memory is updated enable the update display request using
+ (#) When the LCD RAM memory is updated, enable the update display request calling
the HAL_LCD_UpdateDisplayRequest() API.
- [..] LCD and low power modes:
- (#) The LCD remain active during STOP mode.
+ [..] LCD and low power modes: The LCD remain active during STOP mode.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -102,14 +98,14 @@
#ifdef HAL_LCD_MODULE_ENABLED
-/** @defgroup LCD LCD
+/** @addtogroup LCD
* @brief LCD HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup LCD_Private_Defines LCD Private Defines
+/** @addtogroup LCD_Private
* @{
*/
#define LCD_TIMEOUT_VALUE 1000
@@ -121,11 +117,11 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup LCD_Exported_Functions LCD Exported Functions
+/** @addtogroup LCD_Exported_Functions
* @{
*/
-/** @defgroup LCD_Exported_Functions_Group1 Initialization/de-initialization methods
+/** @addtogroup LCD_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
@@ -212,9 +208,13 @@
assert_param(IS_LCD_CONTRAST(hlcd->Init.Contrast));
assert_param(IS_LCD_BLINK_FREQUENCY(hlcd->Init.BlinkFrequency));
assert_param(IS_LCD_BLINK_MODE(hlcd->Init.BlinkMode));
+ assert_param(IS_LCD_MUXSEGMENT(hlcd->Init.MuxSegment));
if(hlcd->State == HAL_LCD_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ __HAL_UNLOCK(hlcd);
+
/* Initialize the low level hardware (MSP) */
HAL_LCD_MspInit(hlcd);
}
@@ -257,10 +257,11 @@
/* Configure the LCD Duty, Bias, Voltage Source, Dead Time:
Set DUTY[2:0] bits according to hlcd->Init.Duty value
Set BIAS[1:0] bits according to hlcd->Init.Bias value
- Set VSEL bits according to hlcd->Init.VoltageSource value */
+ Set VSEL bit according to hlcd->Init.VoltageSource value
+ Set MUX_SEG bit according to hlcd->Init.MuxSegment value */
MODIFY_REG(hlcd->Instance->CR, \
- (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL), \
- (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource));
+ (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL | LCD_CR_MUX_SEG), \
+ (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource | hlcd->Init.MuxSegment));
/* Enable the peripheral */
__HAL_LCD_ENABLE(hlcd);
@@ -305,6 +306,9 @@
*/
__weak void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlcd);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_LCD_MspDeInit could be implemented in the user file
*/
@@ -317,6 +321,9 @@
*/
__weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlcd);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_LCD_MspInit could be implemented in the user file
*/
@@ -326,7 +333,7 @@
* @}
*/
-/** @defgroup LCD_Exported_Functions_Group2 IO operation methods
+/** @addtogroup LCD_Exported_Functions_Group2
* @brief LCD RAM functions
*
@verbatim
@@ -529,7 +536,7 @@
* @}
*/
-/** @defgroup LCD_Exported_Functions_Group3 Peripheral State methods
+/** @addtogroup LCD_Exported_Functions_Group3
* @brief LCD State functions
*
@verbatim
@@ -572,7 +579,7 @@
* @}
*/
-/** @defgroup LCD_Private_Functions LCD Private Functions
+/** @addtogroup LCD_Private
* @{
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lcd.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lcd.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_lcd.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of LCD Controller HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -53,7 +53,7 @@
* @{
*/
-/** @addtogroup LCD LCD
+/** @defgroup LCD LCD
* @{
*/
@@ -90,6 +90,8 @@
This parameter can be one value of @ref LCD_BlinkMode */
uint32_t BlinkFrequency; /*!< Configures the LCD Blink frequency.
This parameter can be one value of @ref LCD_BlinkFrequency */
+ uint32_t MuxSegment; /*!< Enable or disable mux segment.
+ This parameter can be one value of @ref LCD_MuxSegment */
}LCD_InitTypeDef;
/**
@@ -420,6 +422,19 @@
* @}
*/
+/** @defgroup LCD_MuxSegment LCD Mux Segment
+ * @{
+ */
+
+#define LCD_MUXSEGMENT_DISABLE ((uint32_t)0x00000000) /*!< SEG pin multiplexing disabled */
+#define LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG) /*!< SEG[31:28] are multiplexed with SEG[43:40] */
+
+#define IS_LCD_MUXSEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
+ ((__VALUE__) == LCD_MUXSEGMENT_DISABLE))
+/**
+ * @}
+ */
+
/** @defgroup LCD_Flag LCD Flag
* @{
*/
@@ -683,11 +698,11 @@
/* Exported functions ------------------------------------------------------- */
-/** @addtogroup LCD_Exported_Functions
+/** @defgroup LCD_Exported_Functions LCD Exported Functions
* @{
*/
-/** @addtogroup LCD_Exported_Functions_Group1
+/** @defgroup LCD_Exported_Functions_Group1 Initialization and de-initialization methods
* @{
*/
@@ -701,7 +716,7 @@
* @}
*/
-/** @addtogroup LCD_Exported_Functions_Group2
+/** @defgroup LCD_Exported_Functions_Group2 IO operation methods
* @{
*/
@@ -714,7 +729,7 @@
* @}
*/
-/** @addtogroup LCD_Exported_Functions_Group3
+/** @defgroup LCD_Exported_Functions_Group3 Peripheral State methods
* @{
*/
@@ -730,7 +745,7 @@
* @}
*/
-/** @addtogroup LCD_Private_Functions
+/** @addtogroup LCD_Private
* @{
*/
@@ -741,6 +756,16 @@
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup LCD_Private LCD Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
/**
* @}
*/
@@ -758,5 +783,5 @@
#endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
-/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/
+/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_lptim.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief LPTIM HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -94,7 +94,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -128,13 +128,13 @@
* @{
*/
+#ifdef HAL_LPTIM_MODULE_ENABLED
+
/** @addtogroup LPTIM
* @brief LPTIM HAL module driver.
* @{
*/
-#ifdef HAL_LPTIM_MODULE_ENABLED
-
/** @addtogroup LPTIM_Exported_Functions
* @{
*/
@@ -195,6 +195,9 @@
if(hlptim->State == HAL_LPTIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hlptim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware */
HAL_LPTIM_MspInit(hlptim);
}
@@ -288,6 +291,9 @@
*/
__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_MspInit could be implemented in the user file
*/
@@ -300,6 +306,9 @@
*/
__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_MspDeInit could be implemented in the user file
*/
@@ -1470,6 +1479,9 @@
*/
__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
*/
@@ -1482,6 +1494,9 @@
*/
__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
*/
@@ -1494,6 +1509,9 @@
*/
__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_TriggerCallback could be implemented in the user file
*/
@@ -1506,6 +1524,9 @@
*/
__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
*/
@@ -1518,6 +1539,9 @@
*/
__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
*/
@@ -1530,6 +1554,9 @@
*/
__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
*/
@@ -1542,6 +1569,9 @@
*/
__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hlptim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
*/
@@ -1587,13 +1617,11 @@
* @}
*/
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-
/**
* @}
*/
+#endif /* HAL_LPTIM_MODULE_ENABLED */
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_lptim.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,7 +55,7 @@
*/
/* Exported types ------------------------------------------------------------*/
- /** @defgroup TIM_Exported_Types TIM Exported Types
+ /** @defgroup LPTIM_Exported_Types LPTIM Exported Types
* @{
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_lptim_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of LPTIM Extended HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -56,7 +56,7 @@
/* Exported constants --------------------------------------------------------*/
-/** @defgroup LPTIMEx_Exported_Constants LPTIM Extended Exported constants
+/** @defgroup LPTIMEx_Exported_Constants LPTIMEx Exported Constants
* @{
*/
@@ -72,7 +72,8 @@
#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#endif
@@ -82,8 +83,16 @@
* @}
*/
+ /**
+ * @}
+ */
+
+ /** @addtogroup LPTIMEx_Private
+ * @{
+ */
#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
@@ -104,10 +113,9 @@
((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
((__TRIG__) == LPTIM_TRIGSOURCE_7))
#endif
-
/**
* @}
- */
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -28,7 +28,7 @@
(#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
(##) Enable the PCD/USB Low Level interface clock using
- (+++) __HAL_RCC_USB_CLK_ENABLE;
+ (+++) __HAL_RCC_USB_CLK_ENABLE();
(##) Initialize the related GPIO clocks
(##) Configure PCD pin-out
@@ -44,7 +44,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -74,18 +74,20 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal.h"
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
#ifdef HAL_PCD_MODULE_ENABLED
/** @addtogroup STM32L0xx_HAL_Driver
* @{
*/
-/** @defgroup PCD
+/** @addtogroup PCD
* @brief PCD HAL module driver
* @{
*/
-
+/** @addtogroup PCD_Private
+ * @{
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -96,14 +98,18 @@
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+
+/**
+ * @}
+ */
/* Private functions ---------------------------------------------------------*/
-/** @defgroup PCD_Private_Functions
+/** @addtogroup PCD_Exported_Functions
* @{
*/
-/** @defgroup PCD_Group1 Initialization and de-initialization functions
+/** @addtogroup PCD_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
@@ -137,11 +143,17 @@
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
- hpcd->State = PCD_BUSY;
+ if(hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hpcd->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_PCD_MspInit(hpcd);
+ }
+
+ hpcd->State = HAL_PCD_STATE_BUSY;
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_PCD_MspInit(hpcd);
-
/* Init endpoints structures */
for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
{
@@ -187,7 +199,7 @@
hpcd->Instance->CNTR = wInterrupt_Mask;
hpcd->USB_Address = 0;
- hpcd->State= PCD_READY;
+ hpcd->State= HAL_PCD_STATE_READY;
return HAL_OK;
}
@@ -205,7 +217,7 @@
return HAL_ERROR;
}
- hpcd->State = PCD_BUSY;
+ hpcd->State = HAL_PCD_STATE_BUSY;
/* Stop Device */
HAL_PCD_Stop(hpcd);
@@ -213,7 +225,7 @@
/* DeInit the low level hardware */
HAL_PCD_MspDeInit(hpcd);
- hpcd->State = PCD_READY;
+ hpcd->State = HAL_PCD_STATE_RESET;
return HAL_OK;
}
@@ -225,8 +237,11 @@
*/
__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_MspInit could be implenetd in the user file
+ the HAL_PCD_MspInit could be implemented in the user file
*/
}
@@ -237,8 +252,11 @@
*/
__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_MspDeInit could be implenetd in the user file
+ the HAL_PCD_MspDeInit could be implemented in the user file
*/
}
@@ -246,7 +264,7 @@
* @}
*/
-/** @defgroup PCD_Group2 IO operation functions
+/** @addtogroup PCD_Exported_Functions_Group2
* @brief Data transfers functions
*
@verbatim
@@ -332,7 +350,7 @@
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
{
- hpcd->Instance->CNTR &= ~(USB_CNTR_LPMODE);
+ hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
/*set wInterrupt_Mask global variable*/
wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
@@ -377,35 +395,47 @@
/**
* @brief Data out stage callbacks
* @param hpcd: PCD handle
+ * @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
/**
* @brief Data IN stage callbacks
* @param hpcd: PCD handle
+ * @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
/**
* @brief Setup stage callback
- * @param hpcd: ppp handle
+ * @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
@@ -416,8 +446,11 @@
*/
__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
@@ -428,8 +461,11 @@
*/
__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
@@ -441,8 +477,11 @@
*/
__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
@@ -453,32 +492,45 @@
*/
__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
/**
* @brief Incomplete ISO OUT callbacks
* @param hpcd: PCD handle
+ * @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
/**
* @brief Incomplete ISO IN callbacks
* @param hpcd: PCD handle
+ * @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
@@ -489,20 +541,26 @@
*/
__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
/**
* @brief Disconnection event callbacks
- * @param hpcd: ppp handle
+ * @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_DataOutStageCallback could be implenetd in the user file
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
@@ -510,7 +568,8 @@
* @}
*/
-/** @defgroup PCD_Group3 Peripheral Control functions
+
+/** @addtogroup PCD_Exported_Functions_Group3
* @brief management functions
*
@verbatim
@@ -526,10 +585,8 @@
*/
/**
- * @brief Send an amount of data in blocking mode
+ * @brief Connect the USB device
* @param hpcd: PCD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
@@ -544,10 +601,8 @@
}
/**
- * @brief Send an amount of data in blocking mode
+ * @brief Disconnect the USB device
* @param hpcd: PCD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
@@ -555,7 +610,7 @@
__HAL_LOCK(hpcd);
/* Disable DP Pull-Down bit*/
- hpcd->Instance->BCDR &= ~(USB_BCDR_DPPU);
+ hpcd->Instance->BCDR &= ((uint16_t) ~(USB_BCDR_DPPU));
__HAL_UNLOCK(hpcd);
return HAL_OK;
@@ -806,7 +861,7 @@
else
{
/*Set the Double buffer counter*/
- PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+ PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len);
}
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
@@ -870,8 +925,8 @@
}
else
{
- /*Set the Double buffer counter*/
- PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+ /*Set the Double buffer counter */
+ PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len);
/*Write the data to the USB endpoint*/
if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX)
@@ -882,6 +937,7 @@
{
pmabuffer = ep->pmaaddr0;
}
+
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len);
PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in);
}
@@ -1008,23 +1064,24 @@
*/
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
- hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME);
+ hpcd->Instance->CNTR &= ((uint16_t) ~(USB_CNTR_RESUME));
return HAL_OK;
}
+
/**
* @}
*/
-
-/** @defgroup PCD_Group4 Peripheral State functions
- * @brief Peripheral State functions
+
+/** @addtogroup PCD_Exported_Functions_Group4
+ * @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permit to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1033,7 +1090,7 @@
/**
* @brief Return the PCD state
- * @param hpcd : PCD handle
+ * @param hpcd: PCD handle
* @retval HAL state
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
@@ -1045,6 +1102,61 @@
*/
/**
+ * @}
+ */
+
+/** @addtogroup PCD_Private
+ * @{
+ */
+
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx: USB device
+ * @param pbUsrBuf: pointer to user memory area.
+ * @param wPMABufAddr: address into PMA.
+ * @param wNBytes: no. of bytes to be copied.
+ * @retval None
+ */
+void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1;
+ uint32_t i;
+ uint16_t temp1, temp2;
+ uint16_t *pdwVal;
+ pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
+
+ for (i = n; i != 0; i--)
+ {
+ temp1 = (uint16_t) * pbUsrBuf;
+ pbUsrBuf++;
+ temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
+ *pdwVal++ = temp2;
+ pbUsrBuf++;
+ }
+}
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx: USB device
+ * @param pbUsrBuf: pointer to user memory area.
+ * @param wPMABufAddr: address into PMA.
+ * @param wNBytes: no. of bytes to be copied.
+ * @retval None
+ */
+void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1;
+ uint32_t i;
+ uint16_t *pdwVal;
+ pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
+ for (i = n; i != 0; i--)
+ {
+ *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+ pbUsrBuf++;
+ }
+}
+/**
* @brief This function handles PCD Endpoint interrupt request.
* @param hpcd: PCD handle
* @retval HAL status
@@ -1251,51 +1363,6 @@
}
/**
- * @brief Copy a buffer from user memory area to packet memory area (PMA)
- * @param pbUsrBuf: pointer to user memory area.
- * @param wPMABufAddr: address into PMA.
- * @param wNBytes: no. of bytes to be copied.
- * @retval None
- */
-void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
- uint32_t n = (wNBytes + 1) >> 1;
- uint32_t i;
- uint16_t temp1, temp2;
- uint16_t *pdwVal;
- pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
-
- for (i = n; i != 0; i--)
- {
- temp1 = (uint16_t) * pbUsrBuf;
- pbUsrBuf++;
- temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
- *pdwVal++ = temp2;
- pbUsrBuf++;
- }
-}
-
-/**
- * @brief Copy a buffer from user memory area to packet memory area (PMA)
- * @param pbUsrBuf = pointer to user memory area.
- * @param wPMABufAddr: address into PMA.
- * @param wNBytes: no. of bytes to be copied.
- * @retval None
- */
-void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
- uint32_t n = (wNBytes + 1) >> 1;
- uint32_t i;
- uint16_t *pdwVal;
- pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
- for (i = n; i != 0; i--)
- {
- *(uint16_t*)pbUsrBuf++ = *pdwVal++;
- pbUsrBuf++;
- }
-}
-
-/**
* @}
*/
@@ -1307,6 +1374,6 @@
* @}
*/
#endif /* HAL_PCD_MODULE_ENABLED */
-#endif /* #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
+#endif /* #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_pcd.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -45,7 +45,7 @@
extern "C" {
#endif
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal_def.h"
@@ -53,10 +53,13 @@
* @{
*/
-/** @addtogroup PCD
+/** @defgroup PCD PCD
* @{
*/
+/** @defgroup PCD_Exported_Types PCD Exported Types
+ * @{
+ */
/* Exported types ------------------------------------------------------------*/
/**
@@ -64,10 +67,11 @@
*/
typedef enum
{
- PCD_READY = 0x00,
- PCD_ERROR = 0x01,
- PCD_BUSY = 0x02,
- PCD_TIMEOUT = 0x03
+ HAL_PCD_STATE_RESET = 0x00,
+ HAL_PCD_STATE_READY = 0x01,
+ HAL_PCD_STATE_ERROR = 0x02,
+ HAL_PCD_STATE_BUSY = 0x03,
+ HAL_PCD_STATE_TIMEOUT = 0x04
} PCD_StateTypeDef;
typedef enum
@@ -86,20 +90,7 @@
PCD_EP_BUF1
}PCD_EP_BUF_NUM;
-#define PCD_ENDP0 ((uint8_t)0)
-#define PCD_ENDP1 ((uint8_t)1)
-#define PCD_ENDP2 ((uint8_t)2)
-#define PCD_ENDP3 ((uint8_t)3)
-#define PCD_ENDP4 ((uint8_t)4)
-#define PCD_ENDP5 ((uint8_t)5)
-#define PCD_ENDP6 ((uint8_t)6)
-#define PCD_ENDP7 ((uint8_t)7)
-/* Endpoint Kind */
-#define PCD_SNG_BUF 0
-#define PCD_DBL_BUF 1
-
-#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
/**
* @brief PCD Initialization Structure definition
*/
@@ -191,14 +182,44 @@
void *pData; /*!< Pointer to upper stack Handler */
} PCD_HandleTypeDef;
-
+
+/**
+ * @}
+ */
+
+
#include "stm32l0xx_hal_pcd_ex.h"
/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+ * @{
+ */
+
+/** @defgroup PCD_EndPoint PCD End Point
* @{
*/
-/** @defgroup PCD_Speed
+
+#define PCD_ENDP0 ((uint8_t)0)
+#define PCD_ENDP1 ((uint8_t)1)
+#define PCD_ENDP2 ((uint8_t)2)
+#define PCD_ENDP3 ((uint8_t)3)
+#define PCD_ENDP4 ((uint8_t)4)
+#define PCD_ENDP5 ((uint8_t)5)
+#define PCD_ENDP6 ((uint8_t)6)
+#define PCD_ENDP7 ((uint8_t)7)
+
+/* Endpoint Kind */
+#define PCD_SNG_BUF 0
+#define PCD_DBL_BUF 1
+
+#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup PCD_Speed PCD Speed
* @{
*/
#define PCD_SPEED_HIGH 0 /* Not Supported */
@@ -207,7 +228,7 @@
* @}
*/
- /** @defgroup PCD_USB_Core_PHY
+ /** @defgroup PCD_USB_Core_PHY PCD USB Core PHY
* @{
*/
#define PCD_PHY_EMBEDDED 2
@@ -215,7 +236,7 @@
* @}
*/
- /** @defgroup PCD_USB_EP0_MPS
+ /** @defgroup PCD_USB_EP0_MPS PCD USB EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0
@@ -231,7 +252,7 @@
* @}
*/
-/** @defgroup PCD_USB_EP_Type
+/** @defgroup PCD_USB_EP_Type PCD USB EP Type
* @{
*/
#define PCD_EP_TYPE_CTRL 0
@@ -242,20 +263,17 @@
* @}
*/
-/**
- * @}
- */
/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PCD_Interrupt_Clock
+/** @defgroup PCD_Interrupt_Clock PCD Interrupt
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) = ~(__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= (uint16_t) ~(__INTERRUPT__))
-#define USB_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
+#define USB_WAKEUP_EXTI_LINE (EXTI_IMR_IM18) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
@@ -273,6 +291,7 @@
/**
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @param wType: Endpoint Type.
* @retval None
@@ -282,6 +301,7 @@
/**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval Endpoint Type
*/
@@ -290,12 +310,13 @@
/**
* @brief free buffer used from the application realizing it to the line
- toggles bit SW_BUF in the double buffered endpoint register
+ * toggles bit SW_BUF in the double buffered endpoint register
+ * @param USBx: USB device.
* @param bEpNum, bDir
* @retval None
*/
#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
-{\
+do {\
if (bDir == PCD_EP_DBUF_OUT)\
{ /* OUT double buffered endpoint */\
PCD_TX_DTOG(USBx, bEpNum);\
@@ -304,31 +325,33 @@
{ /* IN double buffered endpoint */\
PCD_RX_DTOG(USBx, bEpNum);\
}\
-}
+} while(0)
/**
* @brief gets direction of the double buffered endpoint
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval EP_DBUF_OUT, EP_DBUF_IN,
* EP_DBUF_ERR if the endpoint counter not yet programmed.
*/
#define PCD_GET_DB_DIR(USBx, bEpNum)\
-{\
+do {\
if ((uint16_t)(*PCD_EP_RX_CNT(USBx, bEpNum) & 0xFC00) != 0)\
return(PCD_EP_DBUF_OUT);\
else if (((uint16_t)(*PCD_EP_TX_CNT(USBx, bEpNum)) & 0x03FF) != 0)\
return(PCD_EP_DBUF_IN);\
else\
return(PCD_EP_DBUF_ERR);\
-}
+} while(0)
/**
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @param wState: new state
* @retval None
*/
-#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) {\
+#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do {\
register uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPTX_DTOGMASK;\
@@ -339,15 +362,16 @@
if((USB_EPTX_DTOG2 & wState)!= 0) \
_wRegVal ^= USB_EPTX_DTOG2; \
PCD_SET_ENDPOINT(USBx, bEpNum, (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
- } /* PCD_SET_EP_TX_STATUS */
+ } while(0) /* PCD_SET_EP_TX_STATUS */
/**
* @brief sets the status for rx transfer (bits STAT_TX[1:0])
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @param wState: new state
* @retval None
*/
-#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
+#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do {\
register uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPRX_DTOGMASK;\
@@ -358,16 +382,17 @@
if((USB_EPRX_DTOG2 & wState)!= 0) \
_wRegVal ^= USB_EPRX_DTOG2; \
PCD_SET_ENDPOINT(USBx, bEpNum, (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
- } /* PCD_SET_EP_RX_STATUS */
+ } while(0) /* PCD_SET_EP_RX_STATUS */
/**
* @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @param wStaterx: new state.
* @param wStatetx: new state.
* @retval None
*/
-#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
+#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) do {\
register uint32_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT(USBx, bEpNum) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
@@ -384,11 +409,12 @@
if((USB_EPTX_DTOG2 & wStatetx)!= 0) \
_wRegVal ^= USB_EPTX_DTOG2; \
PCD_SET_ENDPOINT(USBx, bEpNum, _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \
- } /* PCD_SET_EP_TXRX_STATUS */
+ } while(0) /* PCD_SET_EP_TXRX_STATUS */
/**
* @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
* /STAT_RX[1:0])
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval status
*/
@@ -398,6 +424,7 @@
/**
* @brief sets directly the VALID tx/rx-status into the endpoint register
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval None
*/
@@ -407,6 +434,7 @@
/**
* @brief checks stall condition in an endpoint.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval TRUE = endpoint in stall condition.
*/
@@ -417,6 +445,7 @@
/**
* @brief set & clear EP_KIND bit.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval None
*/
@@ -427,6 +456,7 @@
/**
* @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval None
*/
@@ -435,6 +465,7 @@
/**
* @brief Sets/clears directly EP_KIND bit in the endpoint register.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval None
*/
@@ -443,6 +474,7 @@
/**
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval None
*/
@@ -453,6 +485,7 @@
/**
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval None
*/
@@ -463,6 +496,7 @@
/**
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval None
*/
@@ -473,6 +507,7 @@
/**
* @brief Sets address in an endpoint register.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @param bAddr: Address.
* @retval None
@@ -482,6 +517,7 @@
/**
* @brief Gets address in an endpoint register.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval None
*/
@@ -493,6 +529,7 @@
/**
* @brief sets address of the tx/rx buffer.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @param wAddr: address to be set (must be word aligned).
* @retval None
@@ -502,6 +539,7 @@
/**
* @brief Gets address of the tx/rx buffer.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval address of the buffer.
*/
@@ -510,48 +548,51 @@
/**
* @brief Sets counter of rx buffer with no. of blocks.
- * @param bEpNum: Endpoint Number.
+ * @param dwReg: Register.
* @param wCount: Counter.
+ * @param wNBlocks: Nb of block
* @retval None
*/
-#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
+#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) do {\
wNBlocks = wCount >> 5;\
if((wCount & 0x1f) == 0)\
wNBlocks--;\
*pdwReg = (uint16_t)((wNBlocks << 10) | 0x8000);\
- }/* PCD_CALC_BLK32 */
+ } while(0) /* PCD_CALC_BLK32 */
-#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
+#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) do {\
wNBlocks = wCount >> 1;\
if((wCount & 0x1) != 0)\
wNBlocks++;\
*pdwReg = (uint16_t)(wNBlocks << 10);\
- }/* PCD_CALC_BLK2 */
+ } while(0) /* PCD_CALC_BLK2 */
-#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
+#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) do {\
uint16_t wNBlocks;\
if(wCount > 62){PCD_CALC_BLK32(dwReg,wCount,wNBlocks);}\
else {PCD_CALC_BLK2(dwReg,wCount,wNBlocks);}\
- }/* PCD_SET_EP_CNT_RX_REG */
+ } while(0) /* PCD_SET_EP_CNT_RX_REG */
-#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
+#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) do {\
uint16_t *pdwReg = PCD_EP_TX_CNT(USBx, bEpNum); \
PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
- }
+ } while(0)
/**
* @brief sets counter for the tx/rx buffer.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @param wCount: Counter value.
* @retval None
*/
#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT(USBx, bEpNum) = wCount)
-#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) do {\
uint16_t *pdwReg = PCD_EP_RX_CNT(USBx, bEpNum); \
PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
- }
+ } while(0)
/**
* @brief gets counter of the tx buffer.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval Counter value
*/
@@ -560,6 +601,7 @@
/**
* @brief Sets buffer 0/1 address in a double buffer endpoint.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @param wBuf0Addr: buffer 0 address.
* @retval Counter value
@@ -569,6 +611,7 @@
/**
* @brief Sets addresses in a double buffer endpoint.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @param wBuf0Addr: buffer 0 address.
* @param wBuf1Addr = buffer 1 address.
@@ -581,6 +624,7 @@
/**
* @brief Gets buffer 0/1 address of a double buffer endpoint.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval None
*/
@@ -589,9 +633,9 @@
/**
* @brief Gets buffer 0/1 address of a double buffer endpoint.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
- * bDir: endpoint dir EP_DBUF_OUT = OUT
- * EP_DBUF_IN = IN
+ * @param bDir: endpoint dir EP_DBUF_OUT = OUT and EP_DBUF_IN = IN
* @param wCount: Counter value
* @retval None
*/
@@ -613,33 +657,51 @@
*PCD_EP_RX_CNT(USBx, bEpNum) = (uint32_t)wCount; \
} /* SetEPDblBuf1Count */
-#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
+#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do {\
PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount); \
PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount); \
- } /* PCD_SET_EP_DBUF_CNT */
+ } while(0) /* PCD_SET_EP_DBUF_CNT */
/**
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
+ * @param USBx: USB device.
* @param bEpNum: Endpoint Number.
* @retval None
*/
#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT(USBx, bEpNum))
#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT(USBx, bEpNum))
+/**
+ * @}
+ */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+/** @defgroup PCD_Exported_Functions_Group2 IO Data transfers functions
+ * @brief Data transfers functions
+ * @{
+ */
-/* I/O operation functions *****************************************************/
+ /* I/O operation functions *****************************************************/
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
@@ -656,9 +718,14 @@
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
-
+/**
+ * @}
+ */
-
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ * @{
+ */
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
@@ -673,18 +740,46 @@
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+/**
+ * @}
+ */
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ * @{
+ */
+
/* Peripheral State functions **************************************************/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/**
* @}
+ */
+
+/**
+ * @}
+ */
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup PCD_Private PCD Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
+/**
+ * @}
*/
/**
* @}
*/
-#endif /* #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
+#endif /* #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
#ifdef __cplusplus
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd_ex.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd_ex.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_pcd_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Extended PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -39,7 +39,7 @@
******************************************************************************
*/
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal.h"
#ifdef HAL_PCD_MODULE_ENABLED
@@ -47,7 +47,7 @@
* @{
*/
-/** @defgroup PCDEx
+/** @addtogroup PCDEx
* @brief PCDEx HAL module driver
* @{
*/
@@ -62,11 +62,11 @@
/* Private functions ---------------------------------------------------------*/
-/** @defgroup PCDEx_Private_Functions
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
-/** @defgroup PCDEx_Group1 Initialization and de-initialization functions
+/** @addtogroup PCDEx__Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
@@ -79,9 +79,9 @@
/**
* @brief Configure PMA for EP
- * @param pdev : Device instance
+ * @param hpcd : Device instance
* @param ep_addr: endpoint address
- * @param ep_Kind: endpoint Kind
+ * @param ep_kind: endpoint Kind
* USB_SNG_BUF: Single Buffer used
* USB_DBL_BUF: Double Buffer used
* @param pmaadress: EP address in The PMA: In case of single buffer endpoint
@@ -94,6 +94,7 @@
* @retval : status
*/
+
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
uint16_t ep_addr,
uint16_t ep_kind,
@@ -148,5 +149,5 @@
* @}
*/
#endif /* HAL_PCD_MODULE_ENABLED */
-#endif /* #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
+#endif /* #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_pcd.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,19 +50,26 @@
* @{
*/
-/** @addtogroup PCDEx
+/** @defgroup PCDEx PCDEx
* @{
*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Internal macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
+
+/** @defgroup PCDEx__Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ */
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
uint16_t ep_addr,
uint16_t ep_kind,
uint32_t pmaadress);
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief PWR HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -53,7 +53,7 @@
* @{
*/
-/** @addtogroup PWR_Private_Defines
+/** @addtogroup PWR_Private
* @{
*/
@@ -521,7 +521,11 @@
* @note When the voltage regulator operates in low power mode, an additional
* startup delay is incurred when waking up from Stop mode.
* By keeping the internal regulator ON during Stop mode, the consumption
- * is higher although the startup time is reduced.
+ * is higher although the startup time is reduced.
+ * @note Before entering in this function, it is important to ensure that the WUF
+ * wakeup flag is cleared. To perform this action, it is possible to call the
+ * following macro : __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU)
+ *
* @param Regulator: Specifies the regulator state in Stop mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_pwr.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,7 +50,7 @@
* @{
*/
-/** @defgroup PWR
+/** @defgroup PWR PWR
* @{
*/
@@ -74,7 +74,7 @@
* @}
*/
-/** @defgroup PWR_Private_Defines PWR Private Defines
+/** @addtogroup PWR_Private
* @{
*/
@@ -93,7 +93,8 @@
*/
#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1
#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2
-#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#if defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L071xx) || \
+ defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
#define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3
#endif
/**
@@ -184,9 +185,7 @@
#define PWR_FLAG_VOS PWR_CSR_VOSF
#define PWR_FLAG_REGLP PWR_CSR_REGLPF
-#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
- ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \
- ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))
+
/**
* @}
*/
@@ -195,10 +194,15 @@
* @}
*/
-/** @defgroup PWR_Exported_Macro PWR Exported Macro
+/** @defgroup PWR_Exported_Macro PWR Exported Macros
* @{
*/
/** @brief macros configure the main internal regulator output voltage.
+ * When exiting Low Power Run Mode or during dynamic voltage scaling configuration,
+ * the reference manual recommends to poll PWR_FLAG_REGLP bit to wait for the regulator
+ * to reach main mode (resp. to get stabilized) for a transition from 0 to 1.
+ * Only then the clock can be increased.
+ *
* @param __REGULATOR__: specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption when the device does
* not operate at the maximum frequency (refer to the datasheets for more details).
@@ -241,7 +245,7 @@
*/
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
-/** @brief Clear the PWR's pending flags.
+/** @brief Clear the PWR pending flags.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag
@@ -305,14 +309,14 @@
* @brief PVD EXTI line configuration: set rising & falling edge trigger.
* @retval None.
*/
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } while(0);
/**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* This parameter can be:
* @retval None.
*/
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()();
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0);
@@ -333,9 +337,6 @@
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
-/**
- * @}
- */
/**
* @brief Generate a Software interrupt on selected EXTI line.
@@ -347,7 +348,7 @@
* @}
*/
-/** @defgroup PWR_Private_Macros PWR Private Macros
+/** @addtogroup PWR_Private
* @{
*/
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
@@ -364,9 +365,15 @@
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2) || \
((PIN) == PWR_WAKEUP_PIN3))
-#else
+#elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx)
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2))
+#elif defined (STM32L031xx) || defined (STM32L041xx)
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
+ ((PIN) == PWR_WAKEUP_PIN2))
+#elif defined (STM32L011xx) || defined (STM32L021xx)
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
+ ((PIN) == PWR_WAKEUP_PIN3))
#endif
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
@@ -429,6 +436,16 @@
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup PWR_Private PWR Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr_ex.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr_ex.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_pwr_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -52,10 +52,18 @@
* @{
*/
-/** @defgroup PWR_Extended_TimeOut_Value PWR Extended Flag Setting Time Out Value
+/** @addtogroup PWREx_Private
+ * @{
+ */
+
+/** @defgroup PWR_Extended_TimeOut_Value PWREx Flag Setting Time Out Value
* @{
*/
-#define PWR_FLAG_SETTING_DELAY_US 50
+#define PWR_FLAG_SETTING_DELAY_US 50
+/**
+ * @}
+ */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_pwr_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,11 +50,11 @@
* @{
*/
-/** @defgroup PWREx PWR extented module
+/** @defgroup PWREx PWREx
* @{
*/
-/** @defgroup PWREx_Exported_Macros PWRex exported macros
+/** @defgroup PWREx_Exported_Macros PWREx Exported Macros
* @{
*/
@@ -75,7 +75,7 @@
* @}
*/
-/** @defgroup PWREx_Exported_Functions PWRex exported functions
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
* @{
*/
void HAL_PWREx_EnableFastWakeUp(void);
@@ -88,6 +88,16 @@
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup PWREx_Private PWREx Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -54,7 +54,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -88,39 +88,43 @@
* @{
*/
+#ifdef HAL_RCC_MODULE_ENABLED
+
/** @addtogroup RCC
* @brief RCC HAL module driver
* @{
*/
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/** @defgroup RCC_Private_Constants RCC Private constants
+/** @addtogroup RCC_Private
* @{
*/
#define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define RCC_HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define RCC_LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define RCC_PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define RCC_HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define RCC_MSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define RCC_CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
+#define RCC_HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
+#define RCC_LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
+#define RCC_PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
+#define RCC_HSI48_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
+#define RCC_MSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
+#define RCC_CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */
#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define MCO1_GPIO_PORT GPIOA
#define MCO1_PIN GPIO_PIN_8
+
+#define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO2_GPIO_PORT GPIOA
#define MCO2_PIN GPIO_PIN_9
-/**
- * @}
- */
+#if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx)
+#define __MCO3_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
+#define MCO3_GPIO_PORT GPIOB
+#define MCO3_PIN GPIO_PIN_13
+#endif
-/** @defgroup RCC_Private_Vatiables RCC Private Data
- * @{
- */
-static const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+extern const uint8_t PLLMulTable[]; /* Defined in CMSIS (system_stm32l0xx.c)*/
static const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
/**
* @}
*/
@@ -212,7 +216,6 @@
* @note This function does not modify the configuration of the
* @note -Peripheral clocks
* @note -HSI48, LSI, LSE and RTC clocks
- * @param None
* @retval None
*/
__weak void HAL_RCC_DeInit(void)
@@ -226,6 +229,12 @@
* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC Oscillators.
* @note The PLL is not disabled when used as system clock.
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ * supported by this macro. User should request a transition to LSE Off
+ * first and then LSE On or LSE Bypass.
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this macro. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
@@ -234,6 +243,7 @@
uint32_t tickstart = 0;
/* Check the parameters */
+ assert_param(RCC_OscInitStruct != NULL);
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
@@ -250,21 +260,6 @@
}
else
{
- /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
- __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
@@ -363,18 +358,14 @@
}
}
}
- /*----------------------------- MSI Configuration --------------------------*/
+ /*----------------------------- MSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
{
- /* Check the parameters */
- assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
- assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
-
- /* When the MSI is used as system clock it will not disabled */
+ /* When the MSI is used as system clock it will not be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) )
{
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState != RCC_MSI_ON))
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
{
return HAL_ERROR;
}
@@ -382,15 +373,23 @@
/* Otherwise, just the calibration and MSI range change are allowed */
else
{
+ /* Check MSICalibrationValue and MSIClockRange input parameters */
+ assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
+ assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
+
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG (RCC_OscInitStruct->MSIClockRange);
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
+
+ /* Configure the source of time base considering new system clocks settings*/
+ HAL_InitTick (TICK_INT_PRIORITY);
}
}
else
{
/* Check the MSI State */
+ assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
if((RCC_OscInitStruct->MSIState)!= RCC_MSI_OFF)
{
/* Enable the Internal High Speed oscillator (MSI). */
@@ -406,7 +405,12 @@
{
return HAL_TIMEOUT;
}
- }
+ }
+
+ /* Check MSICalibrationValue and MSIClockRange input parameters */
+ assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
+ assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
+
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG (RCC_OscInitStruct->MSIClockRange);
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
@@ -475,7 +479,7 @@
}
}
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/*------------------------------ HSI48 Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
{
@@ -518,48 +522,46 @@
}
}
}
-#endif /* !(STM32L031xx) && !(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)*/
+#endif /* !defined (STM32L011xx) && !defined (STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)*/
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
{
+ FlagStatus pwrclkchanged = RESET;
+ FlagStatus backupchanged = RESET;
+
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
-
- /* Enable write access to Backup domain */
- PWR->CR |= PWR_CR_DBP;
+ /* Update LSE configuration in Backup Domain control register */
+ /* Requires to enable write access to Backup Domain of necessary */
+ if(HAL_IS_BIT_CLR(RCC->APB1ENR, RCC_APB1ENR_PWREN))
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+
+ if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ {
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+ backupchanged = SET;
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while((PWR->CR & PWR_CR_DBP) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
- return HAL_TIMEOUT;
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
-
- /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
- __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
{
@@ -589,6 +591,16 @@
}
}
}
+
+ /* Requires to disable write access to Backup Domain of necessary */
+ if(backupchanged == SET)
+ {
+ CLEAR_BIT(PWR->CR, PWR_CR_DBP);
+ }
+ if(pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
@@ -692,6 +704,7 @@
uint32_t tickstart = 0;
/* Check the parameters */
+ assert_param(RCC_ClkInitStruct != NULL);
assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
assert_param(IS_FLASH_LATENCY(FLatency));
@@ -711,202 +724,107 @@
{
return HAL_ERROR;
}
+ }
+
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
- /*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- {
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- }
-
- /*------------------------- SYSCLK Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
- /* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- /* Check the HSE ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
-
- /* MSI is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
- {
- /* Check the MSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- /* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* HSI is selected as System Clock Source */
- else
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
- /* Check the HSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
}
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
+ }
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
- {
- if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ /* MSI is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
+ {
+ /* Check the MSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- {
- if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
+ return HAL_ERROR;
}
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
+ }
+ /* PLL is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
- {
- if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
- {
- if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
+ return HAL_ERROR;
}
- }
- }
- /* Decreasing the CPU frequency */
- else
- {
- /*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ }
+ /* HSI is selected as System Clock Source */
+ else
{
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- }
-
- /*------------------------- SYSCLK Configuration -------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
- /* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
- /* Check the HSE ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
}
-
- /* MSI is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
- {
- /* Check the MSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- /* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* HSI is selected as System Clock Source */
- else
+ }
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
- /* Check the HSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
{
- return HAL_ERROR;
- }
+ return HAL_TIMEOUT;
+ }
}
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
- {
- if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
{
- if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
+ return HAL_TIMEOUT;
+ }
}
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
+ if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
{
- if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
+ return HAL_TIMEOUT;
+ }
}
- else
+ }
+ else
+ {
+ while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
{
- if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
}
}
-
+ }
+
+ /* Decreasing the CPU frequency */
+ if(FLatency <= (FLASH->ACR & FLASH_ACR_LATENCY))
+ {
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
@@ -916,7 +834,7 @@
{
return HAL_ERROR;
}
- }
+ }
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
@@ -964,6 +882,7 @@
* For STM32L0xx family this parameter can have only one value:
* @arg RCC_MCO1: Clock source to output on MCO pin(PA8).
* @arg RCC_MCO2: Clock source to output on MCO pin(PA9).
+ * @arg RCC_MCO3: Clock source to output on MCO pin(PB13) on STM32L03x/4x/7x/8x .
* @param RCC_MCOSource: specifies the clock source to output.
* This parameter can be one of the following values:
* @arg RCC_MCO1SOURCE_NOCLOCK: No clock selected
@@ -977,7 +896,7 @@
* and in STM32L052xx,STM32L053xx,STM32L062xx, STM32L063xx
* STM32L072xx,STM32L073xx,STM32L082xx, STM32L083xx
* @arg RCC_MCO1SOURCE_HSI48: HSI48 clock selected
- * @param RCC_MCODIV: specifies the MCO DIV.
+ * @param RCC_MCODiv: specifies the MCO DIV.
* This parameter can be one of the following values:
* @arg RCC_MCODIV_1: no division applied to MCO clock
* @arg RCC_MCODIV_2: division by 2 applied to MCO clock
@@ -993,29 +912,45 @@
assert_param(IS_RCC_MCO(RCC_MCOx));
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-
- /* MCO Clock Enable */
- __MCO1_CLK_ENABLE();
-
- /* Configure the MCO1 pin in alternate function mode */
+
+ /* Configure the MCO pin in alternate function mode */
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+
if(RCC_MCOx == RCC_MCO1)
{
+ /* MCO Clock Enable */
+ __MCO1_CLK_ENABLE();
GPIO_InitStruct.Pin = MCO1_PIN;
+ GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+ HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
}
- else
+ else if (RCC_MCOx == RCC_MCO2)
{
+ /* MCO Clock Enable */
+ __MCO2_CLK_ENABLE();
GPIO_InitStruct.Pin = MCO2_PIN;
- }
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
- HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
-
- /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
+ HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
+ }
+#if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx)
+ else
+ {
+ /* MCO Clock Enable */
+ __MCO3_CLK_ENABLE();
+ GPIO_InitStruct.Pin = MCO3_PIN;
+ GPIO_InitStruct.Alternate = GPIO_AF2_MCO;
+ HAL_GPIO_Init(MCO3_GPIO_PORT, &GPIO_InitStruct);
+ }
+#endif
+
+ /* Mask MCO and MCOPRE[2:0] bits then Select MCO clock source and prescaler */
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE), ((RCC_MCOSource | RCC_MCODiv )));
}
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
/**
* @brief Enables the Clock Security System.
* @note If a failure is detected on the HSE oscillator clock, this oscillator
@@ -1023,14 +958,13 @@
* software about the failure (Clock Security System Interrupt, CSSI),
* allowing the MCU to perform rescue operations. The CSSI is linked to
* the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector.
- * @param None
* @retval None
*/
void HAL_RCC_EnableCSS(void)
{
SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ;
}
-
+#endif
/**
* @brief Returns the SYSCLK frequency
@@ -1062,7 +996,6 @@
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
*
- * @param None
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
@@ -1114,17 +1047,17 @@
/* HSI oscillator clock selected as PLL clock source */
if ((RCC->CR & RCC_CR_HSIDIVF) != 0)
{
- sysclockfreq = (HSI_VALUE >> 2) * (pllmul / plldiv);
+ sysclockfreq = (((HSI_VALUE >> 2) * pllmul) / plldiv);
}
else
{
- sysclockfreq =(((HSI_VALUE) * pllmul) / plldiv);
+ sysclockfreq =((HSI_VALUE * pllmul) / plldiv);
}
}
else
{
/* HSE selected as PLL clock source */
- sysclockfreq = (((HSE_VALUE) * pllmul) / plldiv);
+ sysclockfreq = ((HSE_VALUE * pllmul) / plldiv);
}
break;
}
@@ -1144,7 +1077,6 @@
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
- * @param None
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
@@ -1159,7 +1091,6 @@
* @brief Returns the PCLK1 frequency
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
- * @param None
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
@@ -1173,7 +1104,6 @@
* @brief Returns the PCLK2 frequency
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
- * @param None
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
@@ -1195,7 +1125,7 @@
/* Set all possible values for the Oscillator type parameter ---------------*/
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | \
RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
#endif
@@ -1226,7 +1156,7 @@
RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->CR &RCC_ICSCR_MSITRIM) >> 24);
RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR &RCC_ICSCR_MSIRANGE) >> 13);
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/* Get the HSI48 configuration -----------------------------------------------*/
if((RCC->CRRCR &RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
{
@@ -1292,7 +1222,7 @@
/**
* @brief Configures the RCC_ClkInitStruct according to the internal
* RCC configuration registers.
- * @param RCC_OscInitStruct: pointer to an RCC_ClkInitTypeDef structure that
+ * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
* will be configured.
* @param pFLatency: Pointer on the Flash Latency.
* @retval None
@@ -1318,29 +1248,28 @@
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
}
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
/**
* @brief This function handles the RCC CSS interrupt request.
* @note This API should be called under the NMI_Handler().
- * @param None
* @retval None
*/
void HAL_RCC_NMI_IRQHandler(void)
{
/* Check RCC CSSF flag */
- if(__HAL_RCC_GET_IT_SOURCE(RCC_IT_CSS))
+ if(__HAL_RCC_GET_IT(RCC_IT_CSSHSE))
{
/* RCC Clock Security System interrupt user callback */
HAL_RCC_CSSCallback();
/* Clear RCC CSS pending bit */
- __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSSHSE);
}
}
/**
* @brief RCC Clock Security System interrupt callback
- * @param none
- * @retval none
+ * @retval None
*/
__weak void HAL_RCC_CSSCallback(void)
{
@@ -1348,6 +1277,12 @@
the HAL_RCC_CSSCallback could be implemented in the user file
*/
}
+#endif
+
+/**
+ * @}
+ */
+
/**
* @}
@@ -1358,9 +1293,6 @@
*/
#endif /* HAL_RCC_MODULE_ENABLED */
-/**
- * @}
- */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,7 +54,9 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Types RCC Exported Types
+ * @{
+ */
/**
* @brief RCC PLL configuration structure definition
@@ -98,7 +100,8 @@
uint32_t LSIState; /*!< The new state of the LSI.
This parameter can be a value of @ref RCC_LSI_Config */
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
+ !defined (STM32L011xx) && !defined (STM32L021xx)
uint32_t HSI48State; /*!< The new state of the HSI48.
This parameter can be a value of @ref RCC_HSI48_Config */
#endif
@@ -138,8 +141,12 @@
}RCC_ClkInitTypeDef;
-
-/** @defgroup RCC_Private_Constants RCC Private constatnts
+/**
+ * @}
+ */
+
+/* Private constants --------------------------------------------------------*/
+/** @addtogroup RCC_Private
* @brief RCC registers bit address in the alias region
* @{
*/
@@ -159,31 +166,36 @@
/* CIER register byte 0 (Bits[0:8]) base address */
#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10 + 0x00))
-#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
-#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-
/**
* @}
*/
-
+
+/* Exported constants --------------------------------------------------------*/
/** @defgroup RCC_Exported_Constants RCC Exported Constants
* @{
*/
-/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
+/** @defgroup RCC_Timeout_Value Timeout Values
* @{
*/
-#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
-#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
-#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
-#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
-#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
-#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
+#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
+#define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Oscillator_Type Oscillator Type
+ * @{
+ */
+#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) /*!< Oscillator configuration unchanged */
+#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) /*!< HSE to configure */
+#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) /*!< HSI to configure */
+#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) /*!< LSE to configure */
+#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) /*!< LSI to configure */
+#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) /*!< MSI to configure */
#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3F)
-#else
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1F)
#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
/**
@@ -197,8 +209,6 @@
#define RCC_HSE_ON RCC_CR_HSEON
#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
-#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
- ((__HSE__) == RCC_HSE_BYPASS))
/**
* @}
*/
@@ -210,38 +220,12 @@
#define RCC_LSE_ON RCC_CSR_LSEON
#define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP | RCC_CSR_LSEON))
-#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
- ((__LSE__) == RCC_LSE_BYPASS))
/**
* @}
*/
-/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
- * @{
- */
-
-#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */
-#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */
-#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
-#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
-#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */
-#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */
-#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */
-
-#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
- ((__RANGE__) == RCC_MSIRANGE_1) || \
- ((__RANGE__) == RCC_MSIRANGE_2) || \
- ((__RANGE__) == RCC_MSIRANGE_3) || \
- ((__RANGE__) == RCC_MSIRANGE_4) || \
- ((__RANGE__) == RCC_MSIRANGE_5) || \
- ((__RANGE__) == RCC_MSIRANGE_6))
-
-/**
- * @}
- */
-
/** @defgroup RCC_LSI_Config RCC LSI Config
* @{
*/
@@ -250,7 +234,6 @@
#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /* Default MSI calibration trimming value */
-#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
/**
* @}
*/
@@ -264,19 +247,17 @@
#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
-#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
/**
* @}
*/
#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
-/** @defgroup RCC_HSI48_Config
+/** @defgroup RCC_HSI48_Config RCC HSI48 Configuration
* @{
*/
#define RCC_HSI48_OFF ((uint8_t)0x00)
#define RCC_HSI48_ON ((uint8_t)0x01)
-#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
/**
* @}
*/
@@ -289,19 +270,16 @@
#define RCC_PLL_OFF ((uint8_t)0x01)
#define RCC_PLL_ON ((uint8_t)0x02)
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON))
/**
* @}
*/
-/** @defgroup RCC_PLL_Clock_Source PCC PLL Clock Source
+/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
* @{
*/
#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
- ((__SOURCE__) == RCC_PLLSOURCE_HSE))
/**
* @}
@@ -320,11 +298,7 @@
#define RCC_PLLMUL_24 RCC_CFGR_PLLMUL24
#define RCC_PLLMUL_32 RCC_CFGR_PLLMUL32
#define RCC_PLLMUL_48 RCC_CFGR_PLLMUL48
-#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLLMUL_3) || ((__MUL__) == RCC_PLLMUL_4) || \
- ((__MUL__) == RCC_PLLMUL_6) || ((__MUL__) == RCC_PLLMUL_8) || \
- ((__MUL__) == RCC_PLLMUL_12) || ((__MUL__) == RCC_PLLMUL_16) || \
- ((__MUL__) == RCC_PLLMUL_24) || ((__MUL__) == RCC_PLLMUL_32) || \
- ((__MUL__) == RCC_PLLMUL_48))
+
/**
* @}
*/
@@ -336,8 +310,24 @@
#define RCC_PLLDIV_2 RCC_CFGR_PLLDIV2
#define RCC_PLLDIV_3 RCC_CFGR_PLLDIV3
#define RCC_PLLDIV_4 RCC_CFGR_PLLDIV4
-#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLLDIV_2) || ((__DIV__) == RCC_PLLDIV_3) || \
- ((__DIV__) == RCC_PLLDIV_4))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
+ * @{
+ */
+
+#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */
+#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */
+#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
+#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
+#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */
+#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */
+#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */
+
+
/**
* @}
*/
@@ -345,80 +335,63 @@
/** @defgroup RCC_System_Clock_Type RCC System Clock Type
* @{
*/
-#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
-#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
-#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
-#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
-
-#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
+#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */
+#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */
+#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */
+#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */
/**
* @}
*/
-
+
/** @defgroup RCC_System_Clock_Source RCC System Clock Source
* @{
*/
-#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI
-#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
-#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
-#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
-
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
- * @{
- */
-#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
-#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
-
+#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
+#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
/**
* @}
*/
-/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock SOurce
+/** @defgroup RCC_System_Clock_SOURCE_Status RCC System Clock Source Status
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
* @{
*/
-#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
-#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
-#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
-#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
-#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
-#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
-#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
-#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
-#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
-
-#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
- ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
- ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
- ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
- ((__HCLK__) == RCC_SYSCLK_DIV512))
+#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
+#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
+#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
+#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
+#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
+#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
+#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
/**
* @}
- */
-
-/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 Clock Source
+ */
+
+/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source
* @{
*/
-#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
-#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
-#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
-#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
-#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
-
-#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
- ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
- ((__PCLK__) == RCC_HCLK_DIV16))
+#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
+#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
+#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
/**
* @}
- */
+ */
/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
* @{
@@ -426,21 +399,23 @@
#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000)
#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE
#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI
+#define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE
+
#define RCC_RTCCLKSOURCE_HSE_DIV2 RCC_CSR_RTCSEL_HSE
#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)
#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)
#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
+
+#define RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U /*!< HSE is divided by 2 for RTC clock */
+#define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */
+#define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */
+#define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */
+
/**
* @}
*/
-/** @defgroup RCC_MCO_Clock_Source RCC MCo Clock Source
+/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
* @{
*/
@@ -452,22 +427,11 @@
#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) \
+ && !defined (STM32L011xx) && !defined (STM32L021xx)
#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
#endif
-
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
-#else
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
- ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
-#endif
+
/**
* @}
@@ -483,11 +447,6 @@
#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8
#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16
-#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || \
- ((__DIV__) == RCC_MCODIV_2) || \
- ((__DIV__) == RCC_MCODIV_4) || \
- ((__DIV__) == RCC_MCODIV_8) || \
- ((__DIV__) == RCC_MCODIV_16))
/**
* @}
*/
@@ -497,8 +456,11 @@
*/
#define RCC_MCO1 ((uint32_t)0x00000000)
#define RCC_MCO2 ((uint32_t)0x00000001)
+#if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx)
+#define RCC_MCO3 ((uint32_t)0x00000002)
+#endif
-#define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) || ((__MCOx__) == RCC_MCO2))
/**
* @}
*/
@@ -513,50 +475,17 @@
#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF
-#define RCC_IT_LSECSS RCC_CIFR_LSECSSF
-#define RCC_IT_CSS RCC_CIFR_CSSF
-#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
-#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
-
-#define IS_RCC_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \
- ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \
- ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \
- ((__IT__) == RCC_IT_HSI48RDY) || ((__IT__) == RCC_IT_LSECSS))
-
-#define IS_RCC_GET_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \
- ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \
- ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \
- ((__IT__) == RCC_IT_CSS) || ((__IT__) == RCC_IT_HSI48RDY) || \
- ((__IT__) == RCC_IT_LSECSS))
+#define RCC_IT_CSSLSE RCC_CIFR_CSSLSEF
+#define RCC_IT_CSSHSE RCC_CIFR_CSSHSEF
-#define IS_RCC_CLEAR_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \
- ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \
- ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \
- ((__IT__) == RCC_IT_CSS) || ((__IT__) == RCC_IT_HSI48RDY) || \
- ((__IT__) == RCC_IT_LSECSS))
-#else
-#define IS_RCC_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \
- ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \
- ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \
- ((__IT__) == RCC_IT_LSECSS))
-
-#define IS_RCC_GET_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \
- ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \
- ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \
- ((__IT__) == RCC_IT_CSS) || ((__IT__) == RCC_IT_LSECSS))
-
-
-#define IS_RCC_CLEAR_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \
- ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \
- ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \
- ((__IT__) == RCC_IT_CSS) || ((__IT__) == RCC_IT_LSECSS))
-
+#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
/**
* @}
*/
-/** @defgroup RCC_Flag
+/** @defgroup RCC_Flag RCC Flag
* Elements values convention: 0XXYYYYYb
* - YYYYY : Flag position in the register
* - 0XX : Register index
@@ -590,8 +519,6 @@
#define RCC_FLAG_HSI48RDY ((uint8_t)0x61)
#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
-#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
-#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
/**
* @}
@@ -604,11 +531,13 @@
/** @defgroup RCC_Exported_Macros RCC Exported Macros
* @{
*/
-
-/** @brief Enable or disable the AHB peripheral clock.
+
+/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -635,15 +564,20 @@
} while(0)
-#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_DMA1EN))
-#define __HAL_RCC_MIF_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_MIFEN))
-#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRCEN))
+#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
+#define __HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN)
+#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
+/**
+ * @}
+ */
-/** @brief Enable or disable the IOPORT peripheral clock.
+/** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
+ * @brief Enable or disable the IOPORT peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -669,14 +603,6 @@
UNUSED(tmpreg); \
} while(0)
-#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
- UNUSED(tmpreg); \
- } while(0)
-
#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
@@ -686,143 +612,376 @@
} while(0)
-#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOAEN))
-#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOBEN))
-#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOCEN))
-#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIODEN))
-#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOHEN))
+#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
+#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
+#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)
+#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN)
+/**
+ * @}
+ */
-/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
-#define __HAL_RCC_WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
+#define __HAL_RCC_WWDG_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
+#define __HAL_RCC_PWR_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
-#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_PWREN))
+#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
+#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
+/**
+ * @}
+ */
-/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
-#define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
-#define __HAL_RCC_DBGMCU_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN))
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
+#define __HAL_RCC_DBGMCU_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
+
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
+#define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enabled or Disabled Status
+ * @brief Check whether the AHB peripheral clock is enabled or not.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET)
+#define __HAL_RCC_MIF_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_IOPORT_Peripheral_Clock_Enable_Disable_Status IOPORT Peripheral Clock Enabled or Disabled Status
+ * @brief Check whether the IOPORT peripheral clock is enabled or not.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
-#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SYSCFGEN))
-#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_DBGMCUEN))
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) != RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
+ * @brief Check whether the APB1 peripheral clock is enabled or not.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) != RESET)
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) != RESET)
-/** @brief Force or release AHB peripheral reset.
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
+ * @brief Check whether the APB2 peripheral clock is enabled or not.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
+#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) != RESET)
+
+/**
+ * @}
+ */
+
+ /** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
+ * @brief Force or release AHB peripheral reset.
+ * @{
*/
#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
-#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST))
-#define __HAL_RCC_MIF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_MIFRST))
-#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST))
+#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
+#define __HAL_RCC_MIF_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
+#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
-#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRCRST))
-#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_DMA1RST))
-#define __HAL_RCC_MIF_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_MIFRST))
-
-
-/** @brief Force or release IOPORT peripheral reset.
+#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
+#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
+#define __HAL_RCC_MIF_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
+ * @brief Force or release IOPORT peripheral reset.
+ * @{
*/
#define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFF)
-#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOCRST))
-#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIODRST))
-#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOHRST))
+#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
+#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
#define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00)
-#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOCRST))
-#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIODRST))
-#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOHRST))
+#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
+#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
-/** @brief Force or release APB1 peripheral reset.
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
*/
#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
-#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+#define __HAL_RCC_WWDG_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
-#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_PWRRST))
+#define __HAL_RCC_WWDG_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
-/** @brief Force or release APB2 peripheral reset.
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
*/
#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
-#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
-#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
+#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
-#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_DBGMCURST))
-#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
+/**
+ * @}
+ */
+
-/** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
+/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
+ * @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
+ * @{
*/
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_CRCSMEN))
-#define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_MIFSMEN))
-#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_SRAMSMEN))
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_DMA1SMEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
+#define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
+#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
+
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
+#define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
+#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
+ * @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
+ * @{
+ */
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_CRCSMEN))
-#define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_MIFSMEN))
-#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_SRAMSMEN))
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_DMA1SMEN))
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
-/** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
+#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
+#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enabled or Disabled Status
+ * @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET)
+#define __HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) != RESET)
+#define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET)
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable_Status IOPORT Peripheral Clock Sleep Enabled or Disabled Status
+ * @brief Check whether the IOPORT peripheral clock during Low Power (Sleep) mode is enabled or not.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) != RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) != RESET)
+
+/**
+ * @}
*/
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOASMEN))
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOBSMEN))
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOCSMEN))
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIODSMEN))
-#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOHSMEN))
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
+ * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) != RESET)
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) != RESET)
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOASMEN))
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOBSMEN))
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOCSMEN))
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIODSMEN))
-#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOHSMEN))
-
-/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
+ * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
+ * @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
+ */
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
+#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) != RESET)
+
+/**
+ * @}
*/
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_WWDGSMEN))
-#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_PWRSMEN))
+
+/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
+ * @{
+ */
+
+/** @brief Macros to force or release the Backup domain reset.
+ * @note This function resets the RTC peripheral (including the backup registers)
+ * and the RTC clock source selection in RCC_CSR register.
+ * @note The BKPSRAM is not affected by this reset.
+ */
+#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_WWDGSMEN))
-#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_PWRSMEN))
+/**
+ * @}
+ */
-/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral actiated clocks remain enabled during SLEEP mode.
+/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
+ */
+#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
+#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
+
+/**
+ * @}
*/
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_SYSCFGSMEN))
-#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_DBGMCUSMEN))
+
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * It is used (enabled by hardware) as system clock source after startup
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+ * of the HSE used directly or indirectly as system clock (if the Clock
+ * Security System CSS is enabled).
+ * @note HSI can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI.
+ * @note After enabling the HSI, the application software should wait on HSIRDY
+ * flag to be set indicating that HSI clock is stable and can be used as
+ * system clock source.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
+#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SYSCFGSMEN))
-#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_DBGMCUSMEN))
-
+/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * @param __HSICalibrationValue__: specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0x1F.
+ */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
+ RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8))
+
/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
* @note After enabling the HSI, the application software should wait on
* HSIRDY flag to be set indicating that HSI clock is stable and can
@@ -840,25 +999,8 @@
* clock cycles.
*/
#define __HAL_RCC_HSI_CONFIG(__STATE__) \
- MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
-
-/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * It is used (enabled by hardware) as system clock source after startup
- * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
- * of the HSE used directly or indirectly as system clock (if the Clock
- * Security System CSS is enabled).
- * @note HSI can not be stopped if it is used as system clock source. In this case,
- * you have to select another source of the system clock then stop the HSI.
- * @note After enabling the HSI, the application software should wait on HSIRDY
- * flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
-#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
-
+ MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
+
/**
* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
@@ -878,14 +1020,6 @@
#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
-/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * @param __HSICalibrationValue__: specifies the calibration trimming value.
- * This parameter must be a number between 0 and 0x1F.
- */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
- RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8))
/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
* @note The calibration is used to compensate for the variations in voltage
@@ -904,7 +1038,7 @@
* around 2.097 MHz. The MSI clock does not change after wake-up from
* STOP mode.
* @note The MSI clock range can be modified on the fly.
- * @param RCC_MSIRange: specifies the MSI Clock range.
+ * @param __RCC_MSIRange__: specifies the MSI Clock range.
* This parameter must be one of the following values:
* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
@@ -916,6 +1050,21 @@
*/
#define __HAL_RCC_MSI_RANGE_CONFIG(__RCC_MSIRange__) (MODIFY_REG(RCC->ICSCR,\
RCC_ICSCR_MSIRANGE, (uint32_t)(__RCC_MSIRange__) ))
+
+/** @brief Macro to get the Internal Multi Speed oscillator (__MSI__) clock range in run mode
+ * @retval MSI clock range.
+ * This parameter must be one of the following values:
+ * @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
+ * @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
+ * @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
+ * @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
+ * @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
+ * @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
+ * @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
+
+ */
+#define __HAL_RCC_GET_MSI_RANGE() \
+ ((uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE) >> 12))
/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
* @note After enabling the LSI, the application software should wait on
@@ -925,11 +1074,14 @@
* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
* clock cycles.
*/
-#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
+#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
/**
* @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this macro. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
* software should wait on HSERDY flag to be set indicating that HSE clock
* is stable and can be used to clock the PLL and/or system clock.
@@ -949,29 +1101,36 @@
*/
#define __HAL_RCC_HSE_CONFIG(__STATE__) \
do { \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ __IO uint32_t tmpreg; \
if((__STATE__) == RCC_HSE_ON) \
{ \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \
else if((__STATE__) == RCC_HSE_BYPASS) \
{ \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \
else \
{ \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ /* Delay after an RCC peripheral clock */ \
+ tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \
+ UNUSED(tmpreg); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
} \
} while(0)
-
+
/**
* @brief Macro to configure the External Low Speed oscillator (LSE).
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ * supported by this macro. User should request a transition to LSE Off
+ * first and then LSE On or LSE Bypass.
* @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
+ * this domain after reset, you have to enable write access using
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
- * (to be done once after reset).
+ * (to be done once after reset).
* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
* software should wait on LSERDY flag to be set indicating that LSE clock
* is stable and can be used to clock the RTC.
@@ -982,7 +1141,7 @@
* @arg RCC_LSE_ON: turn ON the LSE oscillator.
* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
*/
-#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
do { \
if((__STATE__) == RCC_LSE_ON) \
{ \
@@ -991,6 +1150,7 @@
else if((__STATE__) == RCC_LSE_OFF) \
{ \
CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
} \
else if((__STATE__) == RCC_LSE_BYPASS) \
{ \
@@ -1005,11 +1165,7 @@
} \
} while(0)
-/** @brief Macros to enable or disable the the RTC clock.
- * @note These macros must be used only after the RTC clock source was selected.
- */
-#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
-#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
+
/**
* @brief Configures or Get the RTC and LCD clock (RTCCLK / LCDCLK).
@@ -1021,7 +1177,7 @@
* is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
* @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
*
- * @param RCC_RTCCLKSource: specifies the RTC clock source.
+ * @param __RTCCLKSOURCE__: specifies the RTC clock source.
* This parameter can be one of the following values:
* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
@@ -1037,22 +1193,39 @@
* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
* RTC clock source).
*/
-#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL) ? \
- MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTCCLKSource__) & 0xFFFCFFFF)) : CLEAR_BIT(RCC->CR, RCC_CR_RTCPRE)
+
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSOURCE__) (((__RTCCLKSOURCE__) & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL) ? \
+ MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, (uint32_t)((__RTCCLKSOURCE__) & RCC_CR_RTCPRE)) : \
+ CLEAR_BIT(RCC->CR, RCC_CR_RTCPRE)
-#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
- MODIFY_REG( RCC->CSR, RCC_CSR_RTCSEL, (uint32_t)(__RTCCLKSource__)); \
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSOURCE__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSOURCE__); \
+ MODIFY_REG( RCC->CSR, RCC_CSR_RTCSEL, (uint32_t)((__RTCCLKSOURCE__) & RCC_CSR_RTCSEL)); \
} while (0)
+
+ /**
+ * @brief Get the RTC and LCD clock (RTCCLK / LCDCLK).
+ *
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
+ *
+ */
#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)))
-
-/** @brief Macros to force or release the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_CSR register.
- * @note The BKPSRAM is not affected by this reset.
+
+ /**
+ * @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
+ *
+ * @retval Returned value can be one of the following values:
+ * @arg @ref RCC_RTC_HSE_DIV_2: HSE divided by 2 selected as RTC clock
+ * @arg @ref RCC_RTC_HSE_DIV_4: HSE divided by 4 selected as RTC clock
+ * @arg @ref RCC_RTC_HSE_DIV_8: HSE divided by 8 selected as RTC clock
+ * @arg @ref RCC_RTC_HSE_DIV_16: HSE divided by 16 selected as RTC clock
+ *
*/
-#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
-#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
+#define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
/** @brief Macros to enable or disable the main PLL.
* @note After enabling the main PLL, the application software should wait on
@@ -1061,12 +1234,12 @@
* @note The main PLL can not be disabled if it is used as system clock source
* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
*/
-#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
+#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
* @note This function must be used only when the main PLL is disabled.
- * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
@@ -1091,19 +1264,10 @@
* @arg RCC_PLLDIV_4: PLL clock output = PLLVCO / 4
*/
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__ ,__PLLDIV__ ) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)| (__PLLDIV__)| (__RCC_PLLSource__)))
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PLLMUL__ ,__PLLDIV__ ) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)| (__PLLDIV__)| (__RCC_PLLSOURCE__)))
-/** @brief Macro to get the clock source used as system clock.
- * @retval The clock source used as system clock. The returned value can be one
- * of the following:
- * - RCC_CFGR_SWS_HSI: HSI used as system clock.
- * - RCC_CFGR_SWS_HSE: HSE used as system clock.
- * - RCC_CFGR_SWS_PLL: PLL used as system clock.
- */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
-
-/** @brief Macro to get the oscillator used as PLL clock source.
+ /** @brief Macro to get the oscillator used as PLL clock source.
* @retval The oscillator used as PLL clock source. The returned value can be one
* of the following:
* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
@@ -1111,7 +1275,53 @@
*/
#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC))
-/** @defgroup RCC_Flags_Interrupts_Management
+/**
+ * @brief Macro to configure the system clock source.
+ * @param __SYSCLKSOURCE__: specifies the system clock source.
+ * This parameter can be one of the following values:
+ * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+ * @retval None
+ */
+#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
+
+/** @brief Macro to get the clock source used as system clock.
+ * @retval The clock source used as system clock. The returned value can be one
+ * of the following:
+ * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
+ * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
+ */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
+
+
+/** @brief Macro to configure the MCO clock.
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CFGR_MCO_HSI: HSI clock selected as MCO source
+ * @arg RCC_CFGR_MCO_MSI: MSI clock selected as MCO source
+ * @arg RCC_CFGR_MCO_HSE: HSE clock selected as MCO source
+ * @arg RCC_CFGR_MCO_PLL: PLL clock selected as MCO source
+ * @arg RCC_CFGR_MCO_LSI: LSI clock selected as MCO source
+ * @arg RCC_CFGR_MCO_LSE: LSE clock selected as MCO source
+ * @param __MCODIV__ specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_CFGR_MCO_PRE_1: no division applied to MCO clock
+ * @arg RCC_CFGR_MCO_PRE_2: division by 2 applied to MCO clock
+ * @arg RCC_CFGR_MCO_PRE_4: division by 4 applied to MCO clock
+ * @arg RCC_CFGR_MCO_PRE_8: division by 8 applied to MCO clock
+ * @arg RCC_CFGR_MCO_PRE_16: division by 16 applied to MCO clock
+ */
+
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+
+
+/** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
* @brief macros to manage the specified RCC Flags and interrupts.
* @{
*/
@@ -1132,10 +1342,10 @@
* @arg RCC_IT_HSERDY: HSE ready interrupt
* @arg RCC_IT_PLLRDY: PLL ready interrupt
* @arg RCC_IT_MSIRDY: MSI ready interrupt
- * @arg RCC_IT_LSECSS: LSE CSS interrupt
+ * @arg RCC_IT_CSSLSE: LSE CSS interrupt
* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
*/
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (RCC->CIER |= (__INTERRUPT__))
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to disable
* the selected interrupts).
@@ -1154,10 +1364,10 @@
* @arg RCC_IT_PLLRDY: PLL ready interrupt
* @arg RCC_IT_MSIRDY: MSI ready interrupt
* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
- * @arg RCC_IT_LSECSS: LSE CSS interrupt
+ * @arg RCC_IT_CSSLSE: LSE CSS interrupt
*/
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (RCC->CIER &= ~(__INTERRUPT__))
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
* bits to clear the selected interrupt pending bits.
@@ -1170,8 +1380,8 @@
* @arg RCC_IT_PLLRDY: PLL ready interrupt
* @arg RCC_IT_MSIRDY: MSI ready interrupt
* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
- * @arg RCC_IT_LSECSS: LSE CSS interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @arg RCC_IT_CSSLSE: LSE CSS interrupt
+ * @arg RCC_IT_CSSHSE: Clock Security System interrupt
*/
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
@@ -1184,11 +1394,12 @@
* @arg RCC_IT_HSERDY: HSE ready interrupt
* @arg RCC_IT_PLLRDY: PLL ready interrupt
* @arg RCC_IT_MSIRDY: MSI ready interrupt
- * @arg RCC_IT_LSECSS: LSE CSS interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @arg RCC_IT_CSSLSE: LSE CSS interrupt
+ * @arg RCC_IT_CSSHSE: Clock Security System interrupt
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_RCC_GET_IT_SOURCE(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
/** @brief Set RMVF bit to clear the reset flags.
* The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
@@ -1200,6 +1411,7 @@
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+ * @arg RCC_FLAG_HSIDIV: HSI clock divider flag
* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
* @arg RCC_FLAG_PLLRDY: PLL clock ready
@@ -1216,7 +1428,6 @@
* @arg RCC_FLAG_LPWRRST: Low Power reset
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define RCC_FLAG_MASK ((uint8_t)0x1F)
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->CSR :((((__FLAG__) >> 5) == 3)? \
RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
@@ -1228,6 +1439,119 @@
* @}
*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
+/* Defines used for Flags */
+#define RCC_FLAG_MASK ((uint8_t)0x1F)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+
+#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3F)
+#else
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1F)
+#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
+
+#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
+ ((__HSE__) == RCC_HSE_BYPASS))
+#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
+ ((__LSE__) == RCC_LSE_BYPASS))
+
+#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
+ ((__RANGE__) == RCC_MSIRANGE_1) || \
+ ((__RANGE__) == RCC_MSIRANGE_2) || \
+ ((__RANGE__) == RCC_MSIRANGE_3) || \
+ ((__RANGE__) == RCC_MSIRANGE_4) || \
+ ((__RANGE__) == RCC_MSIRANGE_5) || \
+ ((__RANGE__) == RCC_MSIRANGE_6))
+
+#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
+#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
+#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
+
+#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON))
+
+#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_PLLSOURCE_HSE))
+
+#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLLMUL_3) || ((__MUL__) == RCC_PLLMUL_4) || \
+ ((__MUL__) == RCC_PLLMUL_6) || ((__MUL__) == RCC_PLLMUL_8) || \
+ ((__MUL__) == RCC_PLLMUL_12) || ((__MUL__) == RCC_PLLMUL_16) || \
+ ((__MUL__) == RCC_PLLMUL_24) || ((__MUL__) == RCC_PLLMUL_32) || \
+ ((__MUL__) == RCC_PLLMUL_48))
+
+#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLLDIV_2) || ((__DIV__) == RCC_PLLDIV_3) || \
+ ((__DIV__) == RCC_PLLDIV_4))
+
+#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
+
+#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
+
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV512))
+
+#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
+ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
+ ((__PCLK__) == RCC_HCLK_DIV16))
+
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
+
+#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) \
+ && !defined (STM32L011xx) && !defined (STM32L021xx)
+#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
+#else
+#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
+ ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
+#endif
+
+#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || \
+ ((__DIV__) == RCC_MCODIV_2) || \
+ ((__DIV__) == RCC_MCODIV_4) || \
+ ((__DIV__) == RCC_MCODIV_8) || \
+ ((__DIV__) == RCC_MCODIV_16))
+
+#if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx)
+#define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) || ((__MCOx__) == RCC_MCO2) || ((__MCOx__) == RCC_MCO3))
+#else
+#define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) || ((__MCOx__) == RCC_MCO2))
+
+#endif
+
+#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
+#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
+
+/**
+ * @}
+ */
+
/* Include RCC HAL Extension module */
#include "stm32l0xx_hal_rcc_ex.h"
@@ -1249,7 +1573,9 @@
* @{
*/
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
void HAL_RCC_EnableCSS(void);
+#endif
uint32_t HAL_RCC_GetSysClockFreq(void);
uint32_t HAL_RCC_GetHCLKFreq(void);
uint32_t HAL_RCC_GetPCLK1Freq(void);
@@ -1268,7 +1594,8 @@
/**
* @}
*/
-
+
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Extended RCC HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -24,7 +24,7 @@
(##) Prepare synchronization configuration necessary for HSI48 calibration
(+++) Default values can be set for frequency Error Measurement (reload and error limit)
and also HSI48 oscillator smooth trimming.
- (+++) Macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE can be also used to calculate
+ (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
directly reload value with target and synchronization frequencies values
(##) Call function HAL_RCCEx_CRSConfig which
(+++) Reset CRS registers to their default values.
@@ -60,7 +60,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -94,14 +94,14 @@
* @{
*/
+#ifdef HAL_RCC_MODULE_ENABLED
+
/** @addtogroup RCCEx
* @brief RCC Extension HAL module driver
* @{
*/
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/** @defgroup RCCEx_Private_Constants
+/** @addtogroup RCCEx_Private
* @{
*/
/* Bit position in register */
@@ -109,6 +109,9 @@
#define CRS_CR_TRIM_BITNUMBER 8
#define CRS_ISR_FECAP_BITNUMBER 16
+#if defined(USB)
+extern const uint8_t PLLMulTable[];
+#endif //USB
/**
* @}
*/
@@ -144,25 +147,34 @@
* @note This function does not modify the configuration of the
* @note -Peripheral clocks
* @note -HSI48, LSI, LSE and RTC clocks
- * @param None
* @retval None
*/
void HAL_RCC_DeInit(void)
{
+ __IO uint32_t tmpreg;
+
/* Set MSION bit */
SET_BIT(RCC->CR, RCC_CR_MSION);
#if defined(STM32L073xx) || defined(STM32L083xx) || \
defined(STM32L072xx) || defined(STM32L082xx) || \
- defined(STM32L071xx) || defined(STM32L081xx)
+ defined(STM32L071xx) || defined(STM32L081xx) || \
+ defined(STM32L031xx) || defined(STM32L041xx)
/* Reset HSE, HSI, CSS, PLL */
CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON);
+#elif defined(STM32L011xx) || defined(STM32L021xx)
+ CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
+ RCC_CR_HSEON | RCC_CR_PLLON);
#else
CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \
RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON);
#endif
+ /* Delay after an RCC peripheral clock */ \
+ tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \
+ UNUSED(tmpreg);
+
/* Reset HSEBYP bit */
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
@@ -177,6 +189,8 @@
* @brief Initializes the RCC extended peripherals clocks
* @note Initializes the RCC extended peripherals clocks according to the specified parameters in the
* RCC_PeriphCLKInitTypeDef.
+ * @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with HAL_RCC_OscConfig()
+ * to possibly update HSE divider.
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1,
* I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks).
@@ -184,13 +198,88 @@
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0;
uint32_t tmpreg = 0;
/* Check the parameters */
- assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection));
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*---------------------------- RTC/LCD configuration -------------------------------*/
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
+ || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
+#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
+ )
+ {
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */
+ if( ((RCC->CR & RCC_CR_RTCPRE) != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))
+#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
+ || ((RCC->CR & RCC_CR_RTCPRE) != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE))
+#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
+ )
+ { /* Check HSE State */
+ if (((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE) && HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+ {
+ /*To update HSE divider, first switch-OFF HSE clock oscillator*/
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
-#if !defined (STM32L031xx) && !defined (STM32L041xx)
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */
+ if( ((RCC->CSR & RCC_CSR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL))
+#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
+ || ((RCC->CSR & RCC_CSR_RTCSEL) != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL))
+#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
+ )
+ {
+ /* Store the content of CSR register before the reset of Backup Domain */
+ tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of CSR register */
+ RCC->CSR = tmpreg;
+
+ /* Wait for LSERDY if LSE was enabled */
+ if (HAL_IS_BIT_SET(tmpreg, RCC_CSR_LSERDY))
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* RTC Clock update*/
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+
+ }
+ }
+
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx)
/*------------------------------- USART1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
{
@@ -245,68 +334,7 @@
}
#endif /* defined (STM32L071xx) (STM32L072xx)|| (STM32L073xx)|| (STM32L081xx)|| (STM32L082xx) || (STM32L083xx) */
- /*---------------------------- RTC/LCD configuration -------------------------------*/
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
-#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
- || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
-#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
- )
- {
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
-
- /* Enable write access to Backup domain */
- PWR->CR |= PWR_CR_DBP;
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while((PWR->CR & PWR_CR_DBP) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Reset the Backup domain only if the RTC Clock source selection is modified */
- if(((RCC->CSR & RCC_CSR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL))
-#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
- || (tmpreg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL))
-#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
- )
- {
- /* Store the content of CSR register before the reset of Backup Domain */
- tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
- /* RTC Clock selection can be changed only if the Backup Domain is reset */
- __HAL_RCC_BACKUPRESET_FORCE();
- __HAL_RCC_BACKUPRESET_RELEASE();
- /* Restore the Content of CSR register */
- RCC->CSR = tmpreg;
- }
-
- /* If LSE is selected as RTC clock source, wait for LSE reactivation */
- if((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
-#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
- || (PeriphClkInit->LCDClockSelection == RCC_RTCCLKSOURCE_LSE)
-#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
- )
- {
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- }
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/*---------------------------- USB and RNG configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
{
@@ -337,7 +365,7 @@
{
/* Set all possible values for the extended clock type parameter -----------*/
/* Common part first */
-#if defined(STM32L031xx) || defined(STM32L041xx)
+#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | \
RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPTIM1;
#endif
@@ -372,7 +400,7 @@
RCC_PERIPHCLK_LPTIM1;
#endif
-#if !defined (STM32L031xx) && !defined (STM32L041xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx)
/* Get the USART1 configuration --------------------------------------------*/
PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
#endif
@@ -395,15 +423,373 @@
PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection;
#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/* Get the USB/RNG clock source -----------------------------------------------*/
PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
#endif
}
/**
+ * @brief Return the peripheral clock frequency for some peripherals
+ * @note Return 0 if peripheral clock identifier not managed by this API
+ * @param PeriphClk: Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg RCC_PERIPHCLK_RTC: RTC peripheral clock
+ * @arg RCC_PERIPHCLK_LCD: LCD peripheral clock (*)
+ * @arg RCC_PERIPHCLK_USB: USB or RNG peripheral clock (*)
+ * @arg RCC_PERIPHCLK_USART1: USART1 peripheral clock (*)
+ * @arg RCC_PERIPHCLK_USART2: USART2 peripheral clock
+ * @arg RCC_PERIPHCLK_LPUART1: LPUART1 peripheral clock
+ * @arg RCC_PERIPHCLK_I2C1: I2C1 peripheral clock
+ * @arg RCC_PERIPHCLK_I2C2: I2C2 peripheral clock (*)
+ * @arg RCC_PERIPHCLK_I2C3: I2C3 peripheral clock (*)
+ * @note (*) means that this peripheral is not present on all the STM32L0xx devices
+ * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ uint32_t srcclk = 0, clkprediv = 0, frequency = 0;
+#if defined(USB)
+ uint32_t pllmul = 0, plldiv = 0, pllvco = 0;
+#endif /* USB */
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
+
+ switch(PeriphClk)
+ {
+ case RCC_PERIPHCLK_RTC:
+ {
+ /* Get the current RTC source */
+ srcclk = __HAL_RCC_GET_RTC_SOURCE();
+
+ /* Check if LSE is ready and if RTC clock selection is LSE */
+ if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Check if LSI is ready and if RTC clock selection is LSI */
+ else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
+ {
+ frequency = LSI_VALUE;
+ }
+ /* Check if HSE is ready and if RTC clock selection is HSE*/
+ else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIVX) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
+ {
+ /* Get the current HSE clock divider*/
+ clkprediv=__HAL_RCC_GET_RTC_HSE_PRESCALER();
+
+ switch (clkprediv)
+ {
+ case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */
+ {
+ frequency = HSE_VALUE / 16;
+ break;
+ }
+ case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */
+ {
+ frequency = HSE_VALUE / 8;
+ break;
+ }
+ case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */
+ {
+ frequency = HSE_VALUE / 4;
+ break;
+ }
+ default:
+ {
+ frequency = HSE_VALUE / 2;
+ break;
+ }
+ }
+ }
+ /* Clock not enabled for RTC*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+
+#if defined(LCD)
+
+ case RCC_PERIPHCLK_LCD:
+ {
+ /* Get the current LCD source */
+ srcclk = __HAL_RCC_GET_LCD_SOURCE();
+
+ /* Check if LSE is ready and if LCD clock selection is LSE */
+ if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Check if LSI is ready and if LCD clock selection is LSI */
+ else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
+ {
+ frequency = LSI_VALUE;
+ }
+ /* Check if HSE is ready and if LCD clock selection is HSE*/
+ else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIVX) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
+ {
+ /* Get the current HSE clock divider*/
+ clkprediv=__HAL_RCC_GET_RTC_HSE_PRESCALER();
+
+ switch (clkprediv)
+ {
+ case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */
+ {
+ frequency = HSE_VALUE / 16;
+ break;
+ }
+ case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */
+ {
+ frequency = HSE_VALUE / 8;
+ break;
+ }
+ case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */
+ {
+ frequency = HSE_VALUE / 4;
+ break;
+ }
+ default:
+ {
+ frequency = HSE_VALUE / 2;
+ break;
+ }
+ }
+ }
+ /* Clock not enabled for LCD*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* LCD */
+
+#if defined(USB)
+ case RCC_PERIPHCLK_USB:
+ {
+ /* Get the current USB source */
+ srcclk = __HAL_RCC_GET_USB_SOURCE();
+
+ if((srcclk == RCC_USBCLKSOURCE_PLL) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+ plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+ pllmul = PLLMulTable[(pllmul >> 18)];
+ plldiv = (plldiv >> 22) + 1;
+
+ /* Compute PLL clock input */
+ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)
+ {
+ if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0)
+ {
+ pllvco = (HSI_VALUE >> 2);
+ }
+ else
+ {
+ pllvco = HSI_VALUE;
+ }
+ }
+ else /* HSE source */
+ {
+ pllvco = HSE_VALUE;
+ }
+ /* pllvco * pllmul / plldiv */
+ pllvco = (pllvco * pllmul);
+ frequency = (pllvco/ plldiv);
+
+ }
+ else if((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)))
+ {
+ frequency = HSI48_VALUE;
+ }
+ else /* RCC_USBCLKSOURCE_NONE */
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* USB */
+#if defined(USART1)
+ case RCC_PERIPHCLK_USART1:
+ {
+ /* Get the current USART1 source */
+ srcclk = __HAL_RCC_GET_USART1_SOURCE();
+
+ /* Check if USART1 clock selection is PCLK2 */
+ if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
+ {
+ frequency = HAL_RCC_GetPCLK2Freq();
+ }
+ /* Check if HSI is ready and if USART1 clock selection is HSI */
+ else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if USART1 clock selection is SYSCLK */
+ else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if USART1 clock selection is LSE */
+ else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART1*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* USART1 */
+ case RCC_PERIPHCLK_USART2:
+ {
+ /* Get the current USART2 source */
+ srcclk = __HAL_RCC_GET_USART2_SOURCE();
+
+ /* Check if USART2 clock selection is PCLK1 */
+ if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if USART2 clock selection is HSI */
+ else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if USART2 clock selection is SYSCLK */
+ else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if USART2 clock selection is LSE */
+ else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART2*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+ case RCC_PERIPHCLK_LPUART1:
+ {
+ /* Get the current LPUART1 source */
+ srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
+
+ /* Check if LPUART1 clock selection is PCLK1 */
+ if (srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if LPUART1 clock selection is HSI */
+ else if ((srcclk == RCC_LPUART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if LPUART1 clock selection is SYSCLK */
+ else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if LPUART1 clock selection is LSE */
+ else if ((srcclk == RCC_LPUART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for LPUART1*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+ case RCC_PERIPHCLK_I2C1:
+ {
+ /* Get the current I2C1 source */
+ srcclk = __HAL_RCC_GET_I2C1_SOURCE();
+
+ /* Check if I2C1 clock selection is PCLK1 */
+ if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if I2C1 clock selection is HSI */
+ else if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if I2C1 clock selection is SYSCLK */
+ else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Clock not enabled for I2C1*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#if defined(I2C2)
+ case RCC_PERIPHCLK_I2C2:
+ {
+
+ /* Check if I2C2 on APB1 clock enabled*/
+ if (READ_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))==RCC_APB1ENR_I2C2EN)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* I2C2 */
+
+#if defined(I2C3)
+ case RCC_PERIPHCLK_I2C3:
+ {
+ /* Get the current I2C1 source */
+ srcclk = __HAL_RCC_GET_I2C3_SOURCE();
+
+ /* Check if I2C3 clock selection is PCLK1 */
+ if (srcclk == RCC_I2C3CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if I2C3 clock selection is HSI */
+ else if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if I2C3 clock selection is SYSCLK */
+ else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Clock not enabled for I2C3*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* I2C3 */
+ }
+ return(frequency);
+}
+
+/**
* @brief Enables the LSE Clock Security System.
- * @param None
* @retval None
*/
void HAL_RCCEx_EnableLSECSS(void)
@@ -413,15 +799,64 @@
/**
* @brief Disables the LSE Clock Security System.
- * @param None
* @retval None
*/
void HAL_RCCEx_DisableLSECSS(void)
{
+ /* Disable LSE CSS */
CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
+
+ /* Disable LSE CSS IT */
+ __HAL_RCC_DISABLE_IT(RCC_IT_CSSLSE);
+}
+
+/**
+ * @brief Enable the LSE Clock Security System IT & corresponding EXTI line.
+ * @note LSE Clock Security System IT is mapped on RTC EXTI line 19
+ * @retval None
+ */
+void HAL_RCCEx_EnableLSECSS_IT(void)
+{
+ /* Enable LSE CSS */
+ SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
+
+ /* Enable LSE CSS IT */
+ __HAL_RCC_ENABLE_IT(RCC_IT_CSSLSE);
+
+ /* Enable IT on EXTI Line 19 */
+ __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
+ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
}
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+/**
+ * @brief Handle the RCC LSE Clock Security System interrupt request.
+ * @retval None
+ */
+void HAL_RCCEx_LSECSS_IRQHandler(void)
+{
+ /* Check RCC LSE CSSF flag */
+ if(__HAL_RCC_GET_IT(RCC_IT_CSSLSE))
+ {
+ /* RCC LSE Clock Security System interrupt user callback */
+ HAL_RCCEx_LSECSS_Callback();
+
+ /* Clear RCC LSE CSS pending bit */
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSSLSE);
+ }
+}
+
+/**
+ * @brief RCCEx LSE Clock Security System interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCCEx_LSECSS_Callback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
+ */
+}
+
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/**
* @brief Start automatic synchronization using polling mode
@@ -479,16 +914,15 @@
/* START AUTOMATIC SYNCHRONIZATION*/
/* Enable Automatic trimming */
- __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB();
+ __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE();
/* Enable Frequency error counter */
- __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER();
+ __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE();
}
/**
* @brief Generate the software synchronization event
- * @param None
* @retval None
*/
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
@@ -617,7 +1051,6 @@
}
/**
* @brief Enables Vrefint for the HSI48.
- * @param None
* @note This is functional only if the LOCK is not set
* @retval None
*/
@@ -630,7 +1063,6 @@
/**
* @brief Disables the Vrefint for the HSI48.
- * @param None.
* @note This is functional only if the LOCK is not set
* @retval None
*/
@@ -640,8 +1072,15 @@
/* and the EN_VREFINT bit in the CFGR3 register */
CLEAR_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT));
}
-#endif /* !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
+#endif /* !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/**
* @}
@@ -652,9 +1091,6 @@
*/
#endif /* HAL_RCC_MODULE_ENABLED */
-/**
- * @}
- */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,15 +50,19 @@
* @{
*/
-/** @defgroup RCCEx
+/** @defgroup RCCEx RCCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
+ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+ * @{
+ */
+
/**
* @brief RCC extended clocks structure definition
*/
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
@@ -70,7 +74,7 @@
This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
- This parameter can be a value of @ref RCCEx_LPUART_Clock_Source */
+ This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
uint32_t I2c1ClockSelection; /*!< I2C1 clock source
This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
@@ -95,13 +99,13 @@
}RCC_PeriphCLKInitTypeDef;
-#else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
+#else /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-#if !defined (STM32L031xx) && !defined (STM32L041xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx)
uint32_t Usart1ClockSelection; /*!< USART1 clock source
This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
#endif
@@ -127,11 +131,22 @@
}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32L0x1xx */
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
+/**
+ * @}
+ */
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
-/** @defgroup RCCEx_Exported_Constants
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+
+/** @addtogroup RCCEx_Exported_Constants
* @{
*/
/**
@@ -149,6 +164,10 @@
/**
* @}
*/
+
+ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+ * @{
+ */
/**
* @brief RCC_CRS Init structure definition
*/
@@ -196,17 +215,22 @@
This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
}RCC_CRSSynchroInfoTypeDef;
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+
+/**
+ * @}
+ */
+
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
/* Exported constants --------------------------------------------------------*/
/** @addtogroup RCCEx_Exported_Constants
* @{
*/
-/** @defgroup RCCEx_Periph_Clock_Selection
+/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
* @{
*/
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
@@ -223,34 +247,16 @@
#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
#endif
-#if defined (STM32L052xx) || defined(STM32L062xx)
-#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1))
-#elif defined (STM32L053xx) || defined(STM32L063xx)
-#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD))
-#elif defined (STM32L072xx) || defined(STM32L082xx)
-#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 ))
-#elif defined (STM32L073xx) || defined(STM32L083xx)
-#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 | \
- RCC_PERIPHCLK_LCD))
-#endif
-#else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
+#else /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
-#if !defined(STM32L031xx) && !defined(STM32L041xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
#endif
#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
-#if !defined(STM32L031xx) && !defined(STM32L041xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
#endif
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
@@ -259,100 +265,75 @@
#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
#endif
-#if defined(STM32L031xx) || defined(STM32L041xx)
-#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC ))
-#elif defined(STM32L051xx) || defined(STM32L061xx)
-#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_LPTIM1))
-#elif defined(STM32L071xx) || defined(STM32L081xx)
-#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3))
-#endif
-
-#endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
/**
* @}
*/
-/** @defgroup RCCEx_USART1_Clock_Source
+/** @defgroup RCCEx_USART1_Clock_Source RCC USART1 Clock Source
* @{
*/
#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
-#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
- ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
+
/**
* @}
*/
-/** @defgroup RCCEx_USART2_Clock_Source
+/** @defgroup RCCEx_USART2_Clock_Source RCC USART2 Clock Source
* @{
*/
#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
-#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
+
/**
* @}
*/
-/** @defgroup RCCEx_LPUART_Clock_Source
+/** @defgroup RCCEx_LPUART1_Clock_Source RCC LPUART Clock Source
* @{
*/
#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
-#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
+
/**
* @}
*/
-/** @defgroup RCCEx_I2C1_Clock_Source
+/** @defgroup RCCEx_I2C1_Clock_Source RCC I2C1 Clock Source
* @{
*/
#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
-#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
- ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
+
/**
* @}
*/
#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx)|| defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
-/** @defgroup RCCEx_I2C3_Clock_Source
+/** @defgroup RCCEx_I2C3_Clock_Source RCC I2C3 Clock Source
* @{
*/
#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
-#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
- ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
-#endif /* defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx)|| defined(STM32L082xx) || defined(STM32L083xx) */
/**
* @}
*/
+#endif /* defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx)|| defined(STM32L082xx) || defined(STM32L083xx) */
-/** @defgroup RCCEx_TIM_PRescaler_Selection
+
+
+/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM Prescaler Selection
* @{
*/
#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
@@ -361,32 +342,28 @@
* @}
*/
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
-/** @defgroup RCCEx_USB_Clock_Source
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+/** @defgroup RCCEx_USB_Clock_Source RCC USB Clock Source
* @{
*/
#define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
-#define RCC_USBCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
+#define RCC_USBCLKSOURCE_PLL ((uint32_t)0x00000000)
-#define IS_RCC_USBCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
- ((__SOURCE__) == RCC_USBCLKSOURCE_PLLCLK))
/**
* @}
*/
-/** @defgroup RCCEx_RNG_Clock_Source
+/** @defgroup RCCEx_RNG_Clock_Source RCC RNG Clock Source
* @{
*/
#define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
#define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
-#define IS_RCC_RNGCLKSOURCE(_SOURCE_) (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) || \
- ((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK))
/**
* @}
*/
-/** @defgroup RCCEx_HSI48M_Clock_Source
+/** @defgroup RCCEx_HSI48M_Clock_Source RCC HSI48M Clock Source
* @{
*/
#define RCC_FLAG_HSI48 SYSCFG_CFGR3_REF_HSI48_RDYF
@@ -394,14 +371,13 @@
#define RCC_HSI48M_PLL ((uint32_t)0x00000000)
#define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL
-#define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) || ((__HSI48MCLK__) == RCC_HSI48M_HSI48))
/**
* @}
*/
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
-/** @defgroup RCC_HSI_Config
+/** @defgroup RCC_HSI_Config RCC HSI Configuration
* @{
*/
#define RCC_HSI_OFF ((uint8_t)0x00)
@@ -411,19 +387,13 @@
defined(STM32L072xx) || defined(STM32L082xx) || \
defined(STM32L071xx) || defined(STM32L081xx)
#define RCC_HSI_OUTEN RCC_CR_HSIOUTEN
-
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
- ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_OUTEN ))
-#else
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
- ((__HSI__) == RCC_HSI_DIV4))
#endif
/**
* @}
*/
-/** @defgroup RCCEx_LPTIM1_Clock_Source
+/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
* @{
*/
#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
@@ -431,28 +401,22 @@
#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
-#define IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK) || \
- ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) || \
- ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) || \
- ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
/**
* @}
*/
-/** @defgroup RCCEx_StopWakeUp_Clock
+/** @defgroup RCCEx_StopWakeUp_Clock RCC StopWakeUp Clock
* @{
*/
#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00)
#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
-#define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_StopWakeUpClock_MSI) || \
- ((__SOURCE__) == RCC_StopWakeUpClock_HSI))
/**
* @}
*/
-/** @defgroup RCCEx_LSEDrive_Configuration
+/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
* @{
*/
@@ -460,28 +424,32 @@
#define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0
#define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1
#define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV
-#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
- ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
+
/**
* @}
*/
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
-/** @defgroup RCCEx_CRS_SynchroSource
+/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
+ * @{
+ */
+#define RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19) /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
+/**
+ * @}
+ */
+
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+/** @defgroup RCCEx_CRS_SynchroSource RCC CRS Synchro Source
* @{
*/
#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal source GPIO */
#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
-#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
- ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) ||\
- ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
/**
* @}
*/
-/** @defgroup RCCEx_CRS_SynchroDivider
+/** @defgroup RCCEx_CRS_SynchroDivider RCC CRS Synchro Divider
* @{
*/
#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */
@@ -493,72 +461,61 @@
#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
-#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) ||\
- ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
- ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
- ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
/**
* @}
*/
-/** @defgroup RCCEx_CRS_SynchroPolarity
+/** @defgroup RCCEx_CRS_SynchroPolarity RCC CRS Synchro Polarity
* @{
*/
#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */
#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
-#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
- ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
/**
* @}
*/
-/** @defgroup RCCEx_CRS_ReloadValueDefault
+/** @defgroup RCCEx_CRS_ReloadValueDefault RCC CRS Reload Default Value
* @{
*/
#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
-#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFF))
/**
* @}
*/
-/** @defgroup RCCEx_CRS_ErrorLimitDefault
+/** @defgroup RCCEx_CRS_ErrorLimitDefault RCC CRS Error Limit Default
* @{
*/
#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */
-#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFF))
/**
* @}
*/
-/** @defgroup RCCEx_CRS_HSI48CalibrationDefault
+/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCC CRS HSI48 Calibration Default
* @{
*/
#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
corresponds to a higher output frequency */
-#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3F))
/**
* @}
*/
-/** @defgroup RCCEx_CRS_FreqErrorDirection
+/** @defgroup RCCEx_CRS_FreqErrorDirection RCC CRS Frequency Error Direction
* @{
*/
#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */
#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
-#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
- ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
/**
* @}
*/
-/** @defgroup RCCEx_CRS_Interrupt_Sources
+/** @defgroup RCCEx_CRS_Interrupt_Sources RCC CRS Interrupt Sources
* @{
*/
#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
@@ -573,7 +530,7 @@
* @}
*/
-/** @defgroup RCCEx_CRS_Flags
+/** @defgroup RCCEx_CRS_Flags RCC CRS Flags
* @{
*/
#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
@@ -588,44 +545,142 @@
* @}
*/
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCC Ex Exported Macros
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
* @{
*/
-
-/** @brief Enable or disable the AHB peripheral clock.
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
+ * @brief Enable or disable the AHB peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
-#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx)
-#define __HAL_RCC_AES_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRYPEN))
-#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRYPEN))
-#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
+#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx) || defined(STM32L021xx)
+#define __HAL_RCC_AES_CLK_ENABLE() SET_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN))
+#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN))
+#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx || STM32L041xx || STM32L021xx */
+
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#define __HAL_RCC_TSC_CLK_ENABLE() SET_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
+#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
+
+#define __HAL_RCC_RNG_CLK_ENABLE() SET_BIT(RCC->AHBENR, (RCC_AHBENR_RNGEN))
+#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_RNGEN))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+
+
+/**
+ * @brief Enable interrupt on RCC LSE CSS EXTI Line 19.
+ * @retval None
+ */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Disable interrupt on RCC LSE CSS EXTI Line 19.
+ * @retval None
+ */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
-#define __HAL_RCC_TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
-#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_TSCEN))
+/**
+ * @brief Enable event on RCC LSE CSS EXTI Line 19.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Disable event on RCC LSE CSS EXTI Line 19.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
+
-#define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_RNGEN))
-#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_RNGEN))
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+/**
+ * @brief RCC LSE CSS EXTI line configuration: set falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+ * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
+/**
+ * @brief RCC LSE CSS EXTI line configuration: set rising edge trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
+
+/**
+ * @brief RCC LSE CSS EXTI line configuration: set rising & falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
+ * @retval EXTI RCC LSE CSS Line Status.
+ */
+#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS))
+
+/**
+ * @brief Clear the RCC LSE CSS EXTI flag.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS))
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None.
+ */
+#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)
+
+
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
+ * @brief Enable or disable the IOPORT peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
#if defined(STM32L073xx) || defined(STM32L083xx) || \
defined(STM32L072xx) || defined(STM32L082xx) || \
defined(STM32L071xx) || defined(STM32L081xx)
-/** @brief Enable or disable the IOPORT peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- */
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
@@ -634,105 +689,120 @@
UNUSED(tmpreg); \
} while(0)
-#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOEEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIOEEN))
#endif /* STM32L071xx || STM32L081xx || */
/* STM32L072xx || STM32L082xx || */
/* STM32L073xx || STM32L083xx */
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIODEN))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
+/**
+ * @}
+ */
-/** @brief Enable or disable the APB1 peripheral clock.
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
-#define __HAL_RCC_USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
-#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USBEN))
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#define __HAL_RCC_USB_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
+#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
-#define __HAL_RCC_CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN))
-#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+#define __HAL_RCC_CRS_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_CRSEN))
+#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR,(RCC_APB1ENR_CRSEN))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
-#define __HAL_RCC_LCD_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LCDEN))
-#define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LCDEN))
+#define __HAL_RCC_LCD_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
+#define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
#endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
#if defined(STM32L053xx) || defined(STM32L063xx) || \
defined(STM32L052xx) || defined(STM32L062xx) || \
defined(STM32L051xx) || defined(STM32L061xx)
-#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
-#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
+#define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
-#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
-#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
+#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
#endif /* STM32L051xx || STM32L061xx || */
/* STM32L052xx || STM32L062xx || */
/* STM32L053xx || STM32L063xx || */
-#if defined(STM32L031xx) || defined(STM32L041xx)
-#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
+#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
+#define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
-#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
-#endif /* STM32L031xx || STM32L041xx || */
+#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
+#endif /* STM32L011xx || STM32L021xx || STM32L031xx || STM32L041xx */
#if defined(STM32L073xx) || defined(STM32L083xx) || \
defined(STM32L072xx) || defined(STM32L082xx) || \
defined(STM32L071xx) || defined(STM32L081xx)
-#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_USART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN))
-#define __HAL_RCC_USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN))
-#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
-#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
+#define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_USART4_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
+#define __HAL_RCC_USART5_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
+#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_I2C3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
-#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART4EN))
-#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART5EN))
-#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
-#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
+#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
+#define __HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
+#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
#endif /* STM32L071xx || STM32L081xx || */
/* STM32L072xx || STM32L082xx || */
/* STM32L073xx || STM32L083xx */
@@ -740,232 +810,312 @@
#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) || \
- defined(STM32L031xx) || defined(STM32L041xx)
-
-/** @brief Enable or disable the APB2 peripheral clock.
+ defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L011xx) || defined(STM32L021xx)
+ /**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
-#define __HAL_RCC_TIM21_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM21EN))
-#define __HAL_RCC_TIM22_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM22EN))
-#define __HAL_RCC_FIREWALL_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_MIFIEN))
-#define __HAL_RCC_ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
-#define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
+#define __HAL_RCC_TIM21_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
+#endif
+#define __HAL_RCC_ADC1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_SPI1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_USART1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
-#define __HAL_RCC_TIM21_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM21EN))
-#define __HAL_RCC_TIM22_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM22EN))
-#define __HAL_RCC_FIREWALL_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_MIFIEN))
-#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_ADC1EN))
-#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_USART1EN))
+#define __HAL_RCC_TIM21_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
+#endif
+#define __HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
+#define __HAL_RCC_FIREWALL_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))
+#define __HAL_RCC_FIREWALL_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !STM32L031xx && !STM32L041xx */
#endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */
/* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */
- /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
-
-/** @brief Force or release AHB peripheral reset.
- */
-#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx)
-#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRYPRST))
-#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRYPRST))
-#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
+ /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */
+ /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx */
+
+/**
+ * @}
+ */
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
-#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
-#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_TSCRST))
-#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_RNGRST))
-#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_RNGRST))
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+/** @defgroup RCCEx_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
+ * @brief Force or release AHB peripheral reset.
+ * @{
+ */
+#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx) || defined(STM32L021xx)
+#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST))
+#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST))
+#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx || STM32L041xx || STM32L021xx*/
-/** @brief Force or release IOPORT peripheral reset.
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST))
+#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST))
+#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST))
+#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
+ * @brief Force or release IOPORT peripheral reset.
+ * @{
*/
#if defined(STM32L073xx) || defined(STM32L083xx) || \
defined(STM32L072xx) || defined(STM32L082xx) || \
defined(STM32L071xx) || defined(STM32L081xx)
-#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOERST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOERST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOERST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIOERST))
#endif /* STM32L071xx || STM32L081xx || */
/* STM32L072xx || STM32L082xx || */
/* STM32L073xx || STM32L083xx */
-
-/** @brief Force or release APB1 peripheral reset.
- */
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
+#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIODRST))
+#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIODRST))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
#if defined(STM32L053xx) || defined(STM32L063xx) || \
defined(STM32L052xx) || defined(STM32L062xx) || \
defined(STM32L051xx) || defined(STM32L061xx)
-#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
-#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
+#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
-#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
+#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
#endif /* STM32L051xx || STM32L061xx || */
/* STM32L052xx || STM32L062xx || */
/* STM32L053xx || STM32L063xx */
-#if defined(STM32L031xx) || defined(STM32L041xx)
-#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
+#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
+#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
-#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
-#endif /* STM32L031xx || STM32L041xx || */
+#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
+#endif /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx */
#if defined(STM32L073xx) || defined(STM32L083xx) || \
defined(STM32L072xx) || defined(STM32L082xx) || \
defined(STM32L071xx) || defined(STM32L081xx)
-#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
-#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
-#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
-#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
+#define __HAL_RCC_USART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
+#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
+#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART4RST))
-#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART5RST))
-#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
-#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
+#define __HAL_RCC_USART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
+#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
+#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
#endif /* STM32L071xx || STM32L081xx || */
/* STM32L072xx || STM32L082xx || */
/* STM32L073xx || STM32L083xx || */
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
-#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
-#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USBRST))
-#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
-#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST))
+#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST))
+#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_CRSRST))
+#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR,(RCC_APB1RSTR_CRSRST))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
-#define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))
-#define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LCDRST))
+#define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST))
+#define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST))
#endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
- defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx)
- /** @brief Force or release APB2 peripheral reset.
+ defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
*/
-#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
-#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_TIM21_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM21RST))
-#define __HAL_RCC_TIM22_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM22RST))
+#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
+#endif
-#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_USART1RST))
-#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_ADC1RST))
-#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_TIM21_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM21RST))
-#define __HAL_RCC_TIM22_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM22RST))
+#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
+#endif
#endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */
/* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */
/* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */
+#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
+#define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
+#endif
+#define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
+#endif
+#endif /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx*/
-/** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
+ * @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
*/
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
-#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_TSCSMEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_RNGSMEN))
-#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_TSCSMEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_RNGSMEN))
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
+#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
-#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx)
-#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBSMENR_CRYPSMEN))
-#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~ (RCC_AHBSMENR_CRYPSMEN))
-#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
+#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx)
+#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
+#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
+#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx || STM32L041xx */
-#if defined(STM32L073xx) || defined(STM32L083xx) || \
- defined(STM32L072xx) || defined(STM32L082xx) || \
- defined(STM32L071xx) || defined(STM32L081xx)
-/** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
+ * @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
*/
-
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOESMEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOESMEN))
+#if defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L072xx) || defined(STM32L082xx) || \
+ defined(STM32L071xx) || defined(STM32L081xx)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOESMEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIOESMEN))
#endif /* STM32L071xx || STM32L081xx || */
/* STM32L072xx || STM32L082xx || */
/* STM32L073xx || STM32L083xx || */
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIODSMEN))
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIODSMEN))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
+/**
+ * @}
+ */
-/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+
+/** @defgroup RCCEx_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
+ * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
*/
#if defined(STM32L053xx) || defined(STM32L063xx) || \
defined(STM32L052xx) || defined(STM32L062xx) || \
defined(STM32L051xx) || defined(STM32L061xx)
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM2SMEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM6SMEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_SPI2SMEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART2SMEN))
-#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPUART1SMEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C1SMEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C2SMEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_DACSMEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPTIM1SMEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
-#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
#endif /* STM32L051xx || STM32L061xx || */
/* STM32L052xx || STM32L062xx || */
/* STM32L053xx || STM32L063xx */
@@ -973,87 +1123,142 @@
#if defined(STM32L073xx) || defined(STM32L083xx) || \
defined(STM32L072xx) || defined(STM32L082xx) || \
defined(STM32L071xx) || defined(STM32L081xx)
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM2SMEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM3SMEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM6SMEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM7SMEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_SPI2SMEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART2SMEN))
-#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART4SMEN))
-#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART5SMEN))
-#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPUART1SMEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C1SMEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C2SMEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C3SMEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_DACSMEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPTIM1SMEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
+#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM3SMEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM7SMEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
-#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART4SMEN))
-#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART5SMEN))
-#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C3SMEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
+#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
#endif /* STM32L071xx || STM32L081xx || */
/* STM32L072xx || STM32L082xx || */
/* STM32L073xx || STM32L083xx || */
-
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
-#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USBSMEN))
-#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USBSMEN))
-#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_CRSSMEN))
-#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_CRSSMEN))
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+
+#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
+#endif /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx */
+
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN))
+#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN))
+#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN))
+#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
-#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LCDSMEN))
-#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LCDSMEN))
+#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN))
+#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN))
#endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
- defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx)
-/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+ defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) || \
+ defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L011xx) || defined(STM32L021xx)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
+ * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
+ * @{
*/
-#define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM21SMEN))
-#define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM22SMEN))
-#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_ADC1SMEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_SPI1SMEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_USART1SMEN))
+#define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))
+#endif
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))
-#define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM21SMEN))
-#define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM22SMEN))
-#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_ADC1SMEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SPI1SMEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_USART1SMEN))
+#define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))
+#endif
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))
#endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */
/* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */
/* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */
+ /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx */
-/** @brief macro to configure the I2C1 clock (I2C1CLK).
+/** @brief Macro to configures LCD clock (LCDCLK).
+ * @note LCD and RTC use the same configuration
+ * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
+ * LCD clock source.
+ *
+ * @param __LCD_CLKSOURCE__ specifies the LCD clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock
+ */
+#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
+
+/** @brief macros to get the LCD clock source.
+ */
+#define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE()
+
+/** @brief macros to get the LCD clock pre-scaler.
+ */
+#define __HAL_RCC_GET_LCD_HSE_PRESCALER() __HAL_RCC_GET_RTC_HSE_PRESCALER()
+/**
+ * @}
+ */
+
+/** @brief Macro to configure the I2C1 clock (I2C1CLK).
*
- * @param __I2C1CLKSource__: specifies the I2C1 clock source.
+ * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
* This parameter can be one of the following values:
* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
+ * @retval None
*/
-#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1CLKSource__))
+#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
-/** @brief macro to get the I2C1 clock source.
+/** @brief Macro to get the I2C1 clock source.
* @retval The clock source can be one of the following values:
* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
@@ -1064,18 +1269,19 @@
#if defined (STM32L073xx) || defined(STM32L083xx) || \
defined(STM32L072xx) || defined(STM32L082xx) || \
defined(STM32L071xx) || defined(STM32L081xx)
-/** @brief macro to configure the I2C3 clock (I2C3CLK).
+/** @brief Macro to configure the I2C3 clock (I2C3CLK).
*
- * @param __I2C3CLKSource__: specifies the I2C3 clock source.
+ * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
* This parameter can be one of the following values:
* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
- * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
+ * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
+ * @retval None
*/
-#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3CLKSource__))
+#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
-/** @brief macro to get the I2C3 clock source.
+/** @brief Macro to get the I2C3 clock source.
* @retval The clock source can be one of the following values:
* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
@@ -1087,19 +1293,20 @@
/* STM32L072xx || STM32L082xx || */
/* STM32L073xx || STM32L083xx || */
-/** @brief macro to configure the USART1 clock (USART1CLK).
+/** @brief Macro to configure the USART1 clock (USART1CLK).
*
- * @param __USART1CLKSource__: specifies the USART1 clock source.
+ * @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
* This parameter can be one of the following values:
* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
+ * @retval None
*/
-#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1CLKSource__))
+#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
-/** @brief macro to get the USART1 clock source.
+/** @brief Macro to get the USART1 clock source.
* @retval The clock source can be one of the following values:
* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
@@ -1108,19 +1315,20 @@
*/
#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
-/** @brief macro to configure the USART2 clock (USART2CLK).
+/** @brief Macro to configure the USART2 clock (USART2CLK).
*
- * @param __USART2CLKSource__: specifies the USART2 clock source.
+ * @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
* This parameter can be one of the following values:
* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+ * @retval None
*/
-#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2CLKSource__))
+#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
-/** @brief macro to get the USART2 clock source.
+/** @brief Macro to get the USART2 clock source.
* @retval The clock source can be one of the following values:
* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
@@ -1129,19 +1337,20 @@
*/
#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
-/** @brief macro to configure the LPUART1 clock (LPUART1CLK).
+/** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
*
- * @param __LPUART1CLKSource__: specifies the LPUART1 clock source.
+ * @param __LPUART1_CLKSOURCE__: specifies the LPUART1 clock source.
* This parameter can be one of the following values:
* @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
* @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
* @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
+ * @retval None
*/
-#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
-/** @brief macro to get the LPUART1 clock source.
+/** @brief Macro to get the LPUART1 clock source.
* @retval The clock source can be one of the following values:
* @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
@@ -1150,19 +1359,20 @@
*/
#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
-/** @brief macro to configure the LPTIM1 clock (LPTIM1CLK).
+/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
*
- * @param __LPTIM1CLKSource__: specifies the LPTIM1 clock source.
+ * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
* This parameter can be one of the following values:
* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
* @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPTIM1 clock
* @arg RCC_LPTIM1CLKSOURCE_HSI : LSI selected as LPTIM1 clock
* @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPTIM1 clock
+ * @retval None
*/
-#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
- MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
-/** @brief macro to get the LPTIM1 clock source.
+/** @brief Macro to get the LPTIM1 clock source.
* @retval The clock source can be one of the following values:
* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPUART1 clock
* @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPUART1 clock
@@ -1171,12 +1381,12 @@
*/
#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/** @brief Macro to configure the USB clock (USBCLK).
* @param __USBCLKSource__: specifies the USB clock source.
* This parameter can be one of the following values:
* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
- * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
+ * @arg RCC_USBCLKSOURCE_PLL: PLL Clock selected as USB clock
*/
#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USBCLKSource__))
@@ -1184,7 +1394,7 @@
/** @brief Macro to get the USB clock source.
* @retval The clock source can be one of the following values:
* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
- * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
+ * @arg RCC_USBCLKSOURCE_PLL: PLL Clock selected as USB clock
*/
#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
@@ -1225,13 +1435,12 @@
* @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
*/
#define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
/**
* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
* in STOP mode to be quickly available as kernel clock for USART and I2C.
* @note The Enable of this function has not effect on the HSION bit.
- * This parameter can be: ENABLE or DISABLE.
* @retval None
*/
#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
@@ -1239,7 +1448,7 @@
/**
* @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
- * @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
+ * @param __RCC_LSEDrive__: specifies the new state of the LSE drive capability.
* This parameter can be one of the following values:
* @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
* @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
@@ -1252,7 +1461,7 @@
/**
* @brief Macro to configures the wake up from stop clock.
- * @param RCC_STOPWUCLK: specifies the clock source used after wake up from stop
+ * @param __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop
* This parameter can be one of the following values:
* @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI selected as system clock source
* @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
@@ -1261,7 +1470,7 @@
#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\
RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/**
* @brief Enables the specified CRS interrupts.
* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
@@ -1272,7 +1481,7 @@
* @arg RCC_CRS_IT_ESYNC
* @retval None
*/
-#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR |= (__INTERRUPT__))
+#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
/**
* @brief Disables the specified CRS interrupts.
@@ -1284,7 +1493,7 @@
* @arg RCC_CRS_IT_ESYNC
* @retval None
*/
-#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
+#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR,(__INTERRUPT__))
/** @brief Check the CRS interrupt has occurred or not.
* @param __INTERRUPT__: specifies the CRS interrupt source to check.
@@ -1317,7 +1526,7 @@
/**
* @brief Checks whether the specified CRS flag is set or not.
- * @param _FLAG_: specifies the flag to check.
+ * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg RCC_CRS_FLAG_SYNCOK
* @arg RCC_CRS_FLAG_SYNCWARN
@@ -1354,32 +1563,28 @@
/**
* @brief Enables the oscillator clock for frequency error counter.
* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
- * @param None
* @retval None
*/
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR |= CRS_CR_CEN)
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
/**
* @brief Disables the oscillator clock for frequency error counter.
- * @param None
* @retval None
*/
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR,CRS_CR_CEN)
/**
* @brief Enables the automatic hardware adjustment of TRIM bits.
* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
- * @param None
* @retval None
*/
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR |= CRS_CR_AUTOTRIMEN)
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
/**
* @brief Enables or disables the automatic hardware adjustment of TRIM bits.
- * @param None
* @retval None
*/
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR,CRS_CR_AUTOTRIMEN)
/**
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
@@ -1387,13 +1592,13 @@
* of the synchronization source after prescaling. It is then decreased by one in order to
* reach the expected synchronization on the zero value. The formula is the following:
* RELOAD = (fTARGET / fSYNC) -1
- * @param _FTARGET_ Target frequency (value in Hz)
- * @param _FSYNC_ Synchronization signal frequency (value in Hz)
+ * @param __FTARGET__ Target frequency (value in Hz)
+ * @param __FSYNC__ Synchronization signal frequency (value in Hz)
* @retval None
*/
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1)
+#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1)
-#endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
#if defined(STM32L073xx) || defined(STM32L083xx) || \
defined(STM32L072xx) || defined(STM32L082xx) || \
@@ -1451,16 +1656,21 @@
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
void HAL_RCCEx_EnableLSECSS(void);
void HAL_RCCEx_DisableLSECSS(void);
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+void HAL_RCCEx_EnableLSECSS_IT(void);
+void HAL_RCCEx_LSECSS_IRQHandler(void);
+void HAL_RCCEx_LSECSS_Callback(void);
+
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
void HAL_RCCEx_EnableHSI48_VREFINT(void);
void HAL_RCCEx_DisableHSI48_VREFINT(void);
-#endif /* !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
/**
* @}
@@ -1469,6 +1679,129 @@
* @}
*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Macros
+ * @{
+ */
+
+#if defined (STM32L052xx) || defined(STM32L062xx)
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1))
+#elif defined (STM32L053xx) || defined(STM32L063xx)
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD))
+#elif defined (STM32L072xx) || defined(STM32L082xx)
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 ))
+#elif defined (STM32L073xx) || defined(STM32L083xx)
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_LCD))
+#endif
+
+#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_LPTIM1))
+#elif defined(STM32L051xx) || defined(STM32L061xx)
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_LPTIM1))
+#elif defined(STM32L071xx) || defined(STM32L081xx)
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3))
+#endif
+
+#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
+
+
+#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
+
+#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
+
+#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
+ ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
+
+#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
+ ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
+
+#define IS_RCC_USBCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
+ ((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
+
+#define IS_RCC_RNGCLKSOURCE(_SOURCE_) (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) || \
+ ((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK))
+
+#define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) || ((__HSI48MCLK__) == RCC_HSI48M_HSI48))
+
+#if defined(STM32L073xx) || defined(STM32L083xx) || \
+ defined(STM32L072xx) || defined(STM32L082xx) || \
+ defined(STM32L071xx) || defined(STM32L081xx)
+
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
+ ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_OUTEN ))
+#else
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
+ ((__HSI__) == RCC_HSI_DIV4))
+#endif
+
+#define IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK) || \
+ ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) || \
+ ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) || \
+ ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
+
+#define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_StopWakeUpClock_MSI) || \
+ ((__SOURCE__) == RCC_StopWakeUpClock_HSI))
+
+#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
+ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
+
+#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
+ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) ||\
+ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
+
+#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) ||\
+ ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
+ ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
+ ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
+
+#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
+ ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
+
+#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFF))
+
+#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFF))
+
+#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3F))
+
+#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
+ ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rng.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rng.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_rng.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
@@ -29,7 +29,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,18 +63,19 @@
* @{
*/
-/** @addtogroup RNG
- * @{
- */
-
#ifdef HAL_RNG_MODULE_ENABLED
#if defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) || defined (STM32L063xx) || \
defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
+
+/** @addtogroup RNG
+ * @{
+ */
+
/* Private types -------------------------------------------------------------*/
/* Private Defines -----------------------------------------------------------*/
-/** @addtogroup RNG_Private_Defines
+/** @addtogroup RNG_Private
* @{
*/
#define RNG_TIMEOUT_VALUE 1000
@@ -129,6 +130,9 @@
if(hrng->State == HAL_RNG_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hrng->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
}
@@ -186,6 +190,9 @@
*/
__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_MspInit must be implemented in the user file.
*/
@@ -198,6 +205,9 @@
*/
__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_MspDeInit must be implemented in the user file.
*/
@@ -437,6 +447,9 @@
*/
__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_ReadyDataCallback must be implemented in the user file.
*/
@@ -449,6 +462,9 @@
*/
__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_ErrorCallback must be implemented in the user file.
*/
@@ -490,14 +506,16 @@
* @}
*/
+/**
+ * @}
+ */
+
#endif /* if defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) || defined (STM32L063xx) || \
defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */
#endif /* HAL_RNG_MODULE_ENABLED */
-/**
- * @}
- */
+
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rng.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rng.h Tue Apr 19 11:15:15 2016 +0100
@@ -3,13 +3,13 @@
* @file stm32l0xx_hal_rng.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -280,67 +280,15 @@
* @}
*/
-/* Private types -------------------------------------------------------------*/
-/** @defgroup RNG_Private_Types RNG Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup RNG_Private_Defines RNG Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Variables RNG Private Variables
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup RNG_Private RNG Private
* @{
*/
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Constants RNG Private Constants
- * @{
- */
-
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RNG_Private_Macros RNG Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
- * @{
- */
-
/**
* @}
*/
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Functions RNG Private Functions
- * @{
- */
-
-/**
- * @}
- */
+/**************************************************************/
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@@ -63,65 +63,6 @@
HAL_RTC_SetAlarm_IT() function.
(+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
- *** RTC Wakeup configuration ***
- ================================
- [..]
- (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
- function. You can also configure the RTC Wakeup timer with interrupt mode
- using the HAL_RTC_SetWakeUpTimer_IT() function.
- (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer()
- function.
-
- *** Outputs configuration ***
- =============================
- [..] The RTC has 2 different outputs:
- (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B
- and WaKeUp signals.
- To output the selected RTC signal, use the HAL_RTC_Init() function.
- (+) RTC_CALIB: this output is 512Hz signal or 1Hz.
- To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
- (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB14) managed on
- the RTC_OR register.
- (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
- automatically configured in output alternate function.
-
- *** Smooth digital Calibration configuration ***
- ================================================
- [..]
- (+) Configure the RTC Original Digital Calibration Value and the corresponding
- calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
- function.
-
- *** TimeStamp configuration ***
- ===============================
- [..]
- (+) Enables the RTC TimeStamp using the HAL_RTC_SetTimeStamp() function.
- You can also configure the RTC TimeStamp with interrupt mode using the
- HAL_RTC_SetTimeStamp_IT() function.
- (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
- function.
-
- *** Tamper configuration ***
- ============================
- [..]
- (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge
- or Level according to the Tamper filter (if equal to 0 Edge else Level)
- value, sampling frequency, NoErase, MaskFlag, precharge or discharge and
- Pull-UP using the HAL_RTC_SetTamper() function. You can configure RTC Tamper
- with interrupt mode using HAL_RTC_SetTamper_IT() function.
- (+) The default configuration of the Tamper erases the backup registers. To avoid
- erase, enable the NoErase field on the RTC_TAMPCR register.
-
- *** Backup Data Registers configuration ***
- ===========================================
- [..]
- (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
- function.
- (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
- function.
- (+) The backup registers are reset when a tamper detection event occurs
-
-
##### RTC and low power modes #####
==================================================================
[..] The MCU can be woken up from a low power mode by an RTC alternate
@@ -135,14 +76,14 @@
or the RTC wakeup events.
[..] The RTC provides a programmable time base for waking up from the
Stop or Standby mode at regular intervals.
- Wakeup from STOP and Standby modes is possible only when the RTC clock source
+ Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
is LSE or LSI.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -176,6 +117,7 @@
* @{
*/
+
/** @addtogroup RTC
* @brief RTC HAL module driver
* @{
@@ -229,7 +171,7 @@
*/
/**
- * @brief Initializes the RTC peripheral
+ * @brief Initialize the RTC peripheral
* @param hrtc: RTC handle
* @retval HAL status
*/
@@ -253,6 +195,9 @@
if(hrtc->State == HAL_RTC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hrtc->Lock = HAL_UNLOCKED;
+
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
}
@@ -302,7 +247,7 @@
}
/**
- * @brief DeInitializes the RTC peripheral
+ * @brief DeInitialize the RTC peripheral.
* @param hrtc: RTC handle
* @note This function doesn't reset the RTC Backup Data registers.
* @retval HAL status
@@ -406,26 +351,32 @@
}
/**
- * @brief Initializes the RTC MSP.
+ * @brief Initialize the RTC MSP.
* @param hrtc: RTC handle
* @retval None
*/
__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RTC_MspInit could be implenetd in the user file
- */
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTC_MspInit could be implemented in the user file
+ */
}
/**
- * @brief DeInitializes the RTC MSP.
+ * @brief DeInitialize the RTC MSP.
* @param hrtc: RTC handle
* @retval None
*/
__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RTC_MspDeInit could be implenetd in the user file
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTC_MspDeInit could be implemented in the user file
*/
}
@@ -441,21 +392,20 @@
##### RTC Time and Date functions #####
===============================================================================
- [..] This section provide functions allowing to configure Time and Date features
+ [..] This section provides functions allowing to configure Time and Date features
@endverbatim
* @{
*/
/**
- * @brief Sets RTC current time.
+ * @brief Set RTC current time.
* @param hrtc: RTC handle
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD
-: BCD data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@@ -573,18 +523,24 @@
}
/**
- * @brief Gets RTC current time.
+ * @brief Get RTC current time.
* @param hrtc: RTC handle
- * @param sTime: Pointer to Time structure
+ * @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned
+ * with input format (BIN or BCD), also SubSeconds field returning the
+ * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
+ * factor to be used for second fraction ratio computation.
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD
-: BCD data format
- * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the
- * higher-order calendar shadow registers.
- * Reading RTC current time locks the values in calendar shadow registers until current
- * date is read to ensure consistency between the time and date values.
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
+ * value in second fraction ratio with time unit following generic formula:
+ * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+ * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read
+ * to ensure consistency between the time and date values.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@@ -594,9 +550,12 @@
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- /* Get subseconds values from the correspondent registers*/
+ /* Get subseconds structure field from the corresponding register*/
sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
+ /* Get SecondFraction structure field from the corresponding register field*/
+ sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
+
/* Get the TR register */
tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
@@ -619,14 +578,13 @@
}
/**
- * @brief Sets RTC current date.
+ * @brief Set RTC current date.
* @param hrtc: RTC handle
* @param sDate: Pointer to date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD
-: BCD data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@@ -728,14 +686,16 @@
}
/**
- * @brief Gets RTC current date.
+ * @brief Get RTC current date.
* @param hrtc: RTC handle
* @param sDate: Pointer to Date structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD
-: BCD data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@@ -783,14 +743,13 @@
* @{
*/
/**
- * @brief Sets the specified RTC Alarm.
+ * @brief Set the specified RTC Alarm.
* @param hrtc: RTC handle
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD
-: BCD data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
@@ -965,14 +924,13 @@
}
/**
- * @brief Sets the specified RTC Alarm with Interrupt
+ * @brief Set the specified RTC Alarm with Interrupt.
* @param hrtc: RTC handle
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD
-: BCD data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @note The Alarm register can only be written when the corresponding Alarm
* is disabled (Use the HAL_RTC_DeactivateAlarm()).
* @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
@@ -1155,7 +1113,7 @@
}
/**
- * @brief Deactive the specified RTC Alarm
+ * @brief Deactivate the specified RTC Alarm.
* @param hrtc: RTC handle
* @param Alarm: Specifies the Alarm.
* This parameter can be one of the following values:
@@ -1244,7 +1202,7 @@
}
/**
- * @brief Gets the RTC Alarm value and masks.
+ * @brief Get the RTC Alarm value and masks.
* @param hrtc: RTC handle
* @param sAlarm: Pointer to Date structure
* @param Alarm: Specifies the Alarm.
@@ -1254,8 +1212,7 @@
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD
-: BCD data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
@@ -1314,35 +1271,37 @@
}
/**
- * @brief This function handles Alarm interrupt request.
+ * @brief Handle Alarm interrupt request.
* @param hrtc: RTC handle
* @retval None
*/
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
{
- if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))
+ /* Get the AlarmA interrupt source enable status */
+ if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET)
{
- /* Get the status of the Interrupt */
- if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
+ /* Get the pending status of the AlarmA Interrupt */
+ if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)
{
/* AlarmA callback */
HAL_RTC_AlarmAEventCallback(hrtc);
- /* Clear the Alarm interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
+ /* Clear the AlarmA interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
}
}
- if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))
+ /* Get the AlarmB interrupt source enable status */
+ if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET)
{
- /* Get the status of the Interrupt */
- if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)
+ /* Get the pending status of the AlarmB Interrupt */
+ if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET)
{
/* AlarmB callback */
HAL_RTCEx_AlarmBEventCallback(hrtc);
- /* Clear the Alarm interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
+ /* Clear the AlarmB interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
}
}
@@ -1360,13 +1319,16 @@
*/
__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTC_AlarmAEventCallback could be implemented in the user file
*/
}
/**
- * @brief This function handles AlarmA Polling request.
+ * @brief Handle AlarmA Polling request.
* @param hrtc: RTC handle
* @param Timeout: Timeout duration
* @retval HAL status
@@ -1417,7 +1379,7 @@
*/
/**
- * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
+ * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
* synchronized with RTC APB clock.
* @note The RTC Resynchronization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
@@ -1470,12 +1432,13 @@
* @{
*/
/**
- * @brief Returns the RTC state.
+ * @brief Return the RTC handle state.
* @param hrtc: RTC handle
* @retval HAL state
*/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
{
+ /* Return RTC handle state */
return hrtc->State;
}
@@ -1490,7 +1453,7 @@
* @{
*/
/**
- * @brief Enters the RTC Initialization mode.
+ * @brief Enter the RTC Initialization mode.
* @note The RTC Initialization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
* @param hrtc: RTC handle
@@ -1522,7 +1485,7 @@
/**
- * @brief Converts a 2 digit decimal to BCD format.
+ * @brief Convert a 2 digit decimal to BCD format.
* @param Value: Byte to be converted
* @retval Converted byte
*/
@@ -1540,7 +1503,7 @@
}
/**
- * @brief Converts from 2 digit BCD to Binary.
+ * @brief Convert from 2 digit BCD to Binary.
* @param Value: BCD value to be converted
* @retval Converted word
*/
@@ -1550,12 +1513,12 @@
tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
return (tmp + (Value & (uint8_t)0x0F));
}
+
/**
* @}
*/
#endif /* HAL_RTC_MODULE_ENABLED */
-
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_rtc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -87,7 +87,7 @@
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
- This parameter can be a value of @ref RTC_Output_selection_Definitions */
+ This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
uint32_t OutPutRemap; /*!< Specifies the remap for RTC output.
This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */
@@ -114,12 +114,19 @@
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
- uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
-
+
+ uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
+ This parameter corresponds to a time unit range between [0-1] Second
+ with [1 Sec / SecondFraction +1] granularity */
+
+ uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
+ corresponding to Synchronous pre-scaler factor value (PREDIV_S)
+ This parameter corresponds to a time unit range between [0-1] Second
+ with [1 Sec / SecondFraction +1] granularity.
+ This field will be used only by HAL_RTC_GetTime function */
+
uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
@@ -172,8 +179,8 @@
}RTC_AlarmTypeDef;
/**
- * @brief Time Handle Structure definition
- */
+ * @brief RTC Handle Structure definition
+ */
typedef struct
{
RTC_TypeDef *Instance; /*!< Register base address */
@@ -193,54 +200,17 @@
/** @defgroup RTC_Exported_Constants RTC Exported Constants
* @{
*/
-
-/** @defgroup RTC_Mask_Definition RTC Mask Definition
- * @{
- */
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK ((uint32_t) (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
- RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
- RTC_TR_SU))
-#define RTC_DR_RESERVED_MASK ((uint32_t) (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
- RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \
- RTC_DR_DU))
-
-#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
-
-#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
-
-#define RTC_TIMEOUT_VALUE 1000
-/**
- * @}
- */
-
+
/** @defgroup RTC_Hour_Formats RTC Hour Formats
* @{
*/
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
#define RTC_HOURFORMAT_12 ((uint32_t)RTC_CR_FMT)
-#define IS_RTC_HOUR_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_HOURFORMAT_12) || \
- ((__FORMAT__) == RTC_HOURFORMAT_24))
/**
* @}
*/
-/** @defgroup RTC_Output_selection_Definitions RTC Output selection Definitions
- * @{
- */
-#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
-#define RTC_OUTPUT_ALARMA ((uint32_t)RTC_CR_OSEL_0)
-#define RTC_OUTPUT_ALARMB ((uint32_t)RTC_CR_OSEL_1)
-#define RTC_OUTPUT_WAKEUP ((uint32_t)RTC_CR_OSEL)
-
-#define IS_RTC_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUT_DISABLE) || \
- ((__OUTPUT__) == RTC_OUTPUT_ALARMA) || \
- ((__OUTPUT__) == RTC_OUTPUT_ALARMB) || \
- ((__OUTPUT__) == RTC_OUTPUT_WAKEUP))
-/**
- * @}
- */
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
@@ -248,8 +218,6 @@
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)RTC_CR_POL)
-#define IS_RTC_OUTPUT_POL(__POL__) (((__POL__) == RTC_OUTPUT_POLARITY_HIGH) || \
- ((__POL__) == RTC_OUTPUT_POLARITY_LOW))
/**
* @}
*/
@@ -260,9 +228,6 @@
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)
-#define IS_RTC_OUTPUT_TYPE(__TYPE__) (((__TYPE__) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
- ((__TYPE__) == RTC_OUTPUT_TYPE_PUSHPULL))
-
/**
* @}
*/
@@ -270,51 +235,18 @@
/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
* @{
*/
-#define RTC_OUTPUT_REMAP_PC13 ((uint32_t)0x00000000)
-#define RTC_OUTPUT_REMAP_PB14 ((uint32_t)RTC_OR_OUT_RMP)
-#define IS_RTC_OUTPUT_REMAP(__REMAP__) (((__REMAP__) == RTC_OUTPUT_REMAP_PC13) || \
- ((__REMAP__) == RTC_OUTPUT_REMAP_PB14))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Asynchronous_Predivider RTC Asynchronous Predivider
- * @{
- */
-#define IS_RTC_ASYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)0x7F)
+#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000)
+#define RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP)
/**
* @}
*/
-
-
-/** @defgroup RTC_Synchronous_Predivider RTC Synchronous Predivider
- * @{
- */
-#define IS_RTC_SYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)RTC_PRER_PREDIV_S)
-/**
- * @}
- */
-
-/** @defgroup RTC_Time_Definitions RTC Time Definitions
- * @{
- */
-#define IS_RTC_HOUR12(__HOUR__) (((__HOUR__) > (uint32_t)0) && ((__HOUR__) <= (uint32_t)12))
-#define IS_RTC_HOUR24(__HOUR__) ((__HOUR__) <= (uint32_t)23)
-#define IS_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= (uint32_t)59)
-#define IS_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= (uint32_t)59)
-/**
- * @}
- */
-
+
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
* @{
*/
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
-#define IS_RTC_HOURFORMAT12(__PM__) (((__PM__) == RTC_HOURFORMAT12_AM) || \
- ((__PM__) == RTC_HOURFORMAT12_PM))
/**
* @}
*/
@@ -326,9 +258,6 @@
#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)RTC_CR_ADD1H)
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
-#define IS_RTC_DAYLIGHT_SAVING(__SAVE__) (((__SAVE__) == RTC_DAYLIGHTSAVING_SUB1H) || \
- ((__SAVE__) == RTC_DAYLIGHTSAVING_ADD1H) || \
- ((__SAVE__) == RTC_DAYLIGHTSAVING_NONE))
/**
* @}
*/
@@ -339,8 +268,6 @@
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
#define RTC_STOREOPERATION_SET ((uint32_t)RTC_CR_BCK)
-#define IS_RTC_STORE_OPERATION(__OPERATION__) (((__OPERATION__) == RTC_STOREOPERATION_RESET) || \
- ((__OPERATION__) == RTC_STOREOPERATION_SET))
/**
* @}
*/
@@ -352,16 +279,6 @@
#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
-#define IS_RTC_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Year_Date_Definitions RTC Year Date Definitions
- * @{
- */
-#define IS_RTC_YEAR(__YEAR__) ((__YEAR__) <= (uint32_t)99)
/**
* @}
*/
@@ -384,8 +301,6 @@
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
-#define IS_RTC_MONTH(__MONTH__) (((__MONTH__) >= (uint32_t)1) && ((__MONTH__) <= (uint32_t)12))
-#define IS_RTC_DATE(__DATE__) (((__DATE__) >= (uint32_t)1) && ((__DATE__) <= (uint32_t)31))
/**
* @}
*/
@@ -401,28 +316,6 @@
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
-#define IS_RTC_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \
- ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \
- ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \
- ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || \
- ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || \
- ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \
- ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarm_Definitions RTC Alarm Definitions
- * @{
- */
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >(uint32_t) 0) && ((__DATE__) <= (uint32_t)31))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \
- ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \
- ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \
- ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || \
- ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || \
- ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \
- ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))
/**
* @}
*/
@@ -433,8 +326,6 @@
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
- ((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
/**
* @}
*/
@@ -453,7 +344,6 @@
RTC_ALARMMASK_MINUTES | \
RTC_ALARMMASK_SECONDS))
-#define IS_RTC_ALARM_MASK(__MASK__) (((__MASK__) & ~(RTC_ALARMMASK_ALL)) == (uint32_t)RESET)
/**
* @}
*/
@@ -464,18 +354,10 @@
#define RTC_ALARM_A RTC_CR_ALRAE
#define RTC_ALARM_B RTC_CR_ALRBE
-#define IS_RTC_ALARM(__ALARM__) (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B))
/**
* @}
*/
-/** @defgroup RTC_Alarm_Sub_Seconds_Value RTC Alarm Sub Seconds Value
- * @{
- */
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= RTC_ALRMASSR_SS)
-/**
- * @}
- */
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
* @{
@@ -513,23 +395,6 @@
comparison.Only SS[13:0] are compared */
#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match
to activate alarm. */
-
-#define IS_RTC_ALARM_SUB_SECOND_MASK(__MASK__) (((__MASK__) == RTC_ALARMSUBSECONDMASK_ALL) || \
- ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
- ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
- ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
- ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
- ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
- ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
- ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
- ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
- ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
- ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
- ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
- ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
- ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
- ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14) || \
- ((__MASK__) == RTC_ALARMSUBSECONDMASK_NONE))
/**
* @}
*/
@@ -542,7 +407,20 @@
#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE)
#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE)
#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /* Used only to Enable the Tamper Interrupt */
+
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
+ defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
+
#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE)
+#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) ||
+ * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) ||
+ * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) ||
+ * (STM32L031xx) || (STM32L041xx)
+ */
#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE)
/**
* @}
@@ -553,13 +431,25 @@
*/
#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)
#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)
+
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
+ defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)
+#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) ||
+ * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) ||
+ * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) ||
+ * (STM32L031xx) || (STM32L041xx)
+ */
+
#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)
#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)
#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)
#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)
#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)
-#define RTC_FLAG_INIT ((uint32_t)RTC_ISR_INIT)
#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)
#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)
#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)
@@ -666,7 +556,18 @@
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & RTC_FLAGS_MASK) != RESET)? SET : RESET)
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
+ * This parameter can be:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
/**
* @brief Get the selected RTC Alarm's flag status.
@@ -690,11 +591,7 @@
* @arg RTC_FLAG_ALRBF
* @retval None
*/
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& RTC_FLAGS_MASK) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_IM17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_IM19) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_IM20) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @brief Enable interrupt on the RTC Alarm associated Exti line.
@@ -748,13 +645,13 @@
* @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); } while(0);
/**
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); } while(0);
/**
* @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
@@ -775,13 +672,6 @@
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
-
-
-/**
* @}
*/
@@ -854,15 +744,144 @@
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_Private_Constants RTC Private Constants
+ * @{
+ */
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK ((uint32_t) (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
+ RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
+ RTC_TR_SU))
+#define RTC_DR_RESERVED_MASK ((uint32_t) (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
+ RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \
+ RTC_DR_DU))
+#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
+#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
+
+#define RTC_TIMEOUT_VALUE 1000
+
+#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_IM17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTC_Private_Macros RTC Private Macros
+ * @{
+ */
+
+/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
+ * @{
+ */
+
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
+ ((FORMAT) == RTC_HOURFORMAT_24))
+
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
+ ((POL) == RTC_OUTPUT_POLARITY_LOW))
+
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
+ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+
+#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
+ ((REMAP) == RTC_OUTPUT_REMAP_POS1))
+
+#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \
+ ((PM) == RTC_HOURFORMAT12_PM))
+
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
+ ((OPERATION) == RTC_STOREOPERATION_SET))
+
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
+
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
+
+#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
+ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
+
+#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == (uint32_t)RESET)
+
+#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
+
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
+
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
+
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
+
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
+
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
+
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions -------------------------------------------------------------*/
/** @defgroup RTC_Private_Functions RTC Private Functions
* @{
- */
+ */
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
uint8_t RTC_ByteToBcd2(uint8_t Value);
uint8_t RTC_Bcd2ToByte(uint8_t Value);
/**
* @}
- */
+ */
+
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc_ex.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc_ex.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Extended RTC HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -16,33 +16,6 @@
*
@verbatim
==============================================================================
- ##### Backup Domain Operating Condition #####
- ==============================================================================
- [..] As long as the supply voltage remains in the operating range,
- the RTC never stops, regardless of the device status (Run mode,
- low power modes or under reset).
-
- ##### Backup Domain Reset #####
- ==================================================================
- [..] The backup domain reset sets all RTC registers and the RCC_CSR register
- to their reset values.
- [..] A backup domain reset is generated when one of the following events occurs:
- (+) Software reset, triggered by setting the RTCRST bit in the
- RCC Control Status register (RCC_CSR).
- (+) Power reset (BOR/POR/PDR).
-
- ##### Backup Domain Access #####
- ==================================================================
- [..] After reset, the backup domain (RTC registers and RTC backup data registers)
- is protected against possible unwanted write accesses.
- [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
- (+) Enable the Power Controller (PWR) APB1 interface clock using the
- __HAL_RCC_PWR_CLK_ENABLE() function.
- (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
- (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
- (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
-
-
##### How to use this driver #####
==============================================================================
[..]
@@ -50,20 +23,6 @@
(+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
format using the HAL_RTC_Init() function.
- *** Time and Date configuration ***
- ===================================
- [..]
- (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
- and HAL_RTC_SetDate() functions.
- (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
-
- *** Alarm configuration ***
- ===========================
- [..]
- (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
- You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
- (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
-
*** RTC Wakeup configuration ***
================================
[..]
@@ -81,8 +40,8 @@
To output the selected RTC signal, use the HAL_RTC_Init() function.
(+) RTC_CALIB: this output is 512Hz signal or 1Hz.
To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
- (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB14) managed on
- the RTC_OR register.
+ (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB14) for STM32L05x/6x/7x/8x
+ and (PA2, PB14) for STM32L03x/4x managed on the RTC_OR register.
(+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is
automatically configured in output alternate function.
@@ -96,54 +55,36 @@
*** TimeStamp configuration ***
===============================
[..]
- (+) Enables the RTC TimeStamp using the HAL_RTC_SetTimeStamp() function.
- You can also configure the RTC TimeStamp with interrupt mode using the
- HAL_RTC_SetTimeStamp_IT() function.
- (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
- function.
+ (+) Configure the RTC_AF trigger and enable the RTC TimeStamp using the
+ HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
+ interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
+ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
+ function.
*** Tamper configuration ***
============================
[..]
- (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge
+ (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
or Level according to the Tamper filter (if equal to 0 Edge else Level)
value, sampling frequency, NoErase, MaskFlag, precharge or discharge and
- Pull-UP using the HAL_RTC_SetTamper() function. You can configure RTC Tamper
- with interrupt mode using HAL_RTC_SetTamper_IT() function.
+ Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
+ with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
(+) The default configuration of the Tamper erases the backup registers. To avoid
erase, enable the NoErase field on the RTC_TAMPCR register.
*** Backup Data Registers configuration ***
===========================================
[..]
- (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
- function.
- (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
+ (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
function.
- (+) The backup registers are reset when a tamper detection event occurs
-
-
- ##### RTC and low power modes #####
- ==================================================================
- [..] The MCU can be woken up from a low power mode by an RTC alternate
- function.
- [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
- RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
- These RTC alternate functions can wake up the system from the Stop and
- Standby low power modes.
- [..] The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wakeup mode), by using the RTC alarm
- or the RTC wakeup events.
- [..] The RTC provides a programmable time base for waking up from the
- Stop or Standby mode at regular intervals.
- Wakeup from STOP and Standby modes is possible only when the RTC clock source
- is LSE or LSI.
+ (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
+ function.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -204,14 +145,14 @@
##### RTC TimeStamp and Tamper functions #####
===============================================================================
- [..] This section provide functions allowing to configure TimeStamp feature
+ [..] This section provides functions allowing to configure TimeStamp feature
@endverbatim
* @{
*/
/**
- * @brief Sets TimeStamp.
+ * @brief Set TimeStamp.
* @note This API must be called before enabling the TimeStamp feature.
* @param hrtc: RTC handle
* @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
@@ -223,9 +164,8 @@
* falling edge of the related pin.
* @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
- * The RTC TimeStamp Pin is per default PC13, but for reasons of
- * compatibility, this parameter is used.
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin on STM32L05x/6x/7x/8x
+ * and PA2 on STM32L03x/4x/2x/1x.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
@@ -267,7 +207,7 @@
}
/**
- * @brief Sets TimeStamp with Interrupt.
+ * @brief Set TimeStamp with Interrupt.
* @param hrtc: RTC handle
* @note This API must be called before enabling the TimeStamp feature.
* @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
@@ -279,9 +219,8 @@
* falling edge of the related pin.
* @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
- * The RTC TimeStamp Pin is per default PC13, but for reasons of
- * compatibility, this parameter is used.
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin on STM32L05x/6x/7x/8x
+ * and PA2 on STM32L03x/4x/2x/1x.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
@@ -330,7 +269,7 @@
}
/**
- * @brief Deactivates TimeStamp.
+ * @brief Deactivate TimeStamp.
* @param hrtc: RTC handle
* @retval HAL status
*/
@@ -366,18 +305,16 @@
return HAL_OK;
}
-
/**
- * @brief Gets the RTC TimeStamp value.
+ * @brief Get the RTC TimeStamp value.
* @param hrtc: RTC handle
* @param sTimeStamp: Pointer to Time structure
- * @param sTimeStampDate: Pointer to Date structure
+ * @param sTimeStampDate: Pointer to Date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * RTC_FORMAT_BIN: Binary data format
- * RTC_FORMAT_BCD
-: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
@@ -425,7 +362,7 @@
}
/**
- * @brief Sets Tamper
+ * @brief Set Tamper
* @note By calling this API we disable the tamper interrupt for all tampers.
* @param hrtc: RTC handle
* @param sTamper: Pointer to Tamper Structure.
@@ -460,16 +397,30 @@
if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
{
sTamper->NoErase = 0;
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
+ defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
+
if((sTamper->Tamper & RTC_TAMPER_1) != 0)
{
sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
}
+#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) ||
+ * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) ||
+ * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) ||
+ * (STM32L031xx) || (STM32L041xx)
+ */
+
if((sTamper->Tamper & RTC_TAMPER_2) != 0)
{
sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
}
#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
-defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
if((sTamper->Tamper & RTC_TAMPER_3) != 0)
{
@@ -477,31 +428,46 @@
}
#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
-* (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
-*/
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || (STM32L021xx)
+ */
}
if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
{
sTamper->MaskFlag = 0;
+
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
+ defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
+
if((sTamper->Tamper & RTC_TAMPER_1) != 0)
{
sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
}
+#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) ||
+ * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) ||
+ * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) ||
+ * (STM32L031xx) || (STM32L041xx)
+ */
+
if((sTamper->Tamper & RTC_TAMPER_2) != 0)
{
sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
}
#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
if((sTamper->Tamper & RTC_TAMPER_3) != 0)
{
sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
}
-#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
-* (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
-*/
+#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx)|| (STM32L011xx) || (STM32L021xx)
+ */
}
/* Configure the RTC_TAMPCR register */
@@ -509,34 +475,35 @@
(uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
(uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | (uint32_t)sTamper->TimeStampOnTamperDetection);
-
#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx)
-
hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\
RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\
RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\
RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP1NOERASE | RTC_TAMPCR_TAMP2NOERASE|\
RTC_TAMPCR_TAMP1MF | RTC_TAMPCR_TAMP2MF));
-#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) ||
- * (STM32L053xx) || (STM32L052xx) || (STM32L051xx)
- */
-
-#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
-
+#elif defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\
RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\
RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\
RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE | RTC_TAMPCR_TAMP1NOERASE |\
RTC_TAMPCR_TAMP2NOERASE | RTC_TAMPCR_TAMP3NOERASE | RTC_TAMPCR_TAMP1MF |\
RTC_TAMPCR_TAMP2MF | RTC_TAMPCR_TAMP3MF));
-
-#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
- * (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
- */
-
+
+#elif defined (STM32L011xx) || defined (STM32L021xx)
+ hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\
+ RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\
+ RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE |\
+ RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE |\
+ RTC_TAMPCR_TAMP2NOERASE | RTC_TAMPCR_TAMP3NOERASE |\
+ RTC_TAMPCR_TAMP2MF | RTC_TAMPCR_TAMP3MF));
+
+#endif /* (STM32L011xx) || (STM32L021xx)
+ */
+
hrtc->Instance->TAMPCR |= tmpreg;
hrtc->State = HAL_RTC_STATE_READY;
@@ -548,7 +515,7 @@
}
/**
- * @brief Sets Tamper with interrupt.
+ * @brief Set Tamper with interrupt.
* @note By calling this API we force the tamper interrupt for all tampers.
* @param hrtc: RTC handle
* @param sTamper: Pointer to RTC Tamper.
@@ -584,47 +551,77 @@
if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
{
sTamper->NoErase = 0;
+
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
+ defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
+
if((sTamper->Tamper & RTC_TAMPER_1) != 0)
{
sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
}
+#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) ||
+ * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) ||
+ * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) ||
+ * (STM32L031xx) || (STM32L041xx)
+ */
+
+
if((sTamper->Tamper & RTC_TAMPER_2) != 0)
{
sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
}
#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
-defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
if((sTamper->Tamper & RTC_TAMPER_3) != 0)
{
sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
}
#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
-* (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
-*/
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || (STM32L021xx)
+ */
}
if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
{
sTamper->MaskFlag = 0;
+
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
+ defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
if((sTamper->Tamper & RTC_TAMPER_1) != 0)
{
sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
}
+#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) ||
+ * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) ||
+ * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) ||
+ * (STM32L031xx) || (STM32L041xx)
+ */
+
if((sTamper->Tamper & RTC_TAMPER_2) != 0)
{
sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
}
#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
-defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
if((sTamper->Tamper & RTC_TAMPER_3) != 0)
{
sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
}
#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
-* (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
-*/
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || (STM32L021xx)
+ */
}
/* Configure the RTC_TAMPCR register */
@@ -632,22 +629,17 @@
(uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\
(uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | (uint32_t)sTamper->TimeStampOnTamperDetection);
-
#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx)
-
hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\
RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\
RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\
RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP1NOERASE | RTC_TAMPCR_TAMP2NOERASE |\
RTC_TAMPCR_TAMP1MF | RTC_TAMPCR_TAMP2MF);
-#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) ||
- * (STM32L053xx) || (STM32L052xx) || (STM32L051xx)
- */
-#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
-
+#elif defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\
RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\
RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\
@@ -655,9 +647,16 @@
RTC_TAMPCR_TAMP2NOERASE | RTC_TAMPCR_TAMP3NOERASE | RTC_TAMPCR_TAMP1MF |\
RTC_TAMPCR_TAMP2MF | RTC_TAMPCR_TAMP3MF);
-#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
- * (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
- */
+#elif defined (STM32L011xx) || defined (STM32L021xx)
+ hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\
+ RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\
+ RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE |\
+ RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE |\
+ RTC_TAMPCR_TAMP2NOERASE | RTC_TAMPCR_TAMP3NOERASE |\
+ RTC_TAMPCR_TAMP2MF | RTC_TAMPCR_TAMP3MF);
+
+#endif /* (STM32L011xx) || (STM32L021xx)
+ */
hrtc->Instance->TAMPCR |= tmpreg;
@@ -675,11 +674,11 @@
}
/**
- * @brief Deactivates Tamper.
+ * @brief Deactivate Tamper.
* @param hrtc: RTC handle
* @param Tamper: Selected tamper pin.
- * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2 for NEMO.
- * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3 for BIG NEMO.
+ * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2 for STM32L05x/6x.
+ * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3 for STM32L01x/2x/3x/7x/8x.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
@@ -693,12 +692,25 @@
/* Disable the selected Tamper pin */
hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper);
-
+
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
+ defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
if ((Tamper & RTC_TAMPER_1) != 0)
{
/* Disable the Tamper1 interrupt */
hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1));
}
+
+#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) ||
+ * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) ||
+ * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) ||
+ * (STM32L031xx) || (STM32L041xx)
+ */
+
if ((Tamper & RTC_TAMPER_2) != 0)
{
/* Disable the Tamper2 interrupt */
@@ -706,16 +718,17 @@
}
#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
if ((Tamper & RTC_TAMPER_3) != 0)
{
- /* Disable the Tamper2 interrupt */
+ /* Disable the Tamper3 interrupt */
hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3));
}
#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
- * (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || (STM32L021xx)
*/
hrtc->State = HAL_RTC_STATE_READY;
@@ -727,76 +740,88 @@
}
/**
- * @brief This function handles TimeStamp interrupt request.
+ * @brief Handle TimeStamp interrupt request.
* @param hrtc: RTC handle
* @retval None
*/
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
-{
- if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))
+{
+ /* Get the TimeStamp interrupt source enable status */
+ if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET)
{
- /* Get the status of the Interrupt */
- if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
+ /* Get the pending status of the TIMESTAMP Interrupt */
+ if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)
{
- /* TIMESTAMP callback */
+ /* TIMESTAMP callback */
HAL_RTCEx_TimeStampEventCallback(hrtc);
-
+
/* Clear the TIMESTAMP interrupt pending bit */
- __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
}
}
- /* Get the status of the Interrupt */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== SET)
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
+ defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
+
+ /* Get the Tamper1 interrupts source enable status */
+ if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET)
{
- /* Get the TAMPER Interrupt enable bit and pending bit */
- if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \
- (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP1IE)) != (uint32_t)RESET))
+ /* Get the pending status of the Tamper1 Interrupt */
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)
{
- /* Tamper callback */
+ /* Tamper1 callback */
HAL_RTCEx_Tamper1EventCallback(hrtc);
- /* Clear the Tamper interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
+ /* Clear the Tamper1 interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
}
}
+#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) ||
+ * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) ||
+ * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) ||
+ * (STM32L031xx) || (STM32L041xx)
+ */
- /* Get the status of the Interrupt */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F)== SET)
+ /* Get the Tamper2 interrupts source enable status */
+ if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET)
{
- /* Get the TAMPER Interrupt enable bit and pending bit */
- if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \
- (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP2IE)) != (uint32_t)RESET))
+ /* Get the pending status of the Tamper2 Interrupt */
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)
{
- /* Tamper callback */
+ /* Tamper2 callback */
HAL_RTCEx_Tamper2EventCallback(hrtc);
- /* Clear the Tamper interrupt pending bit */
+ /* Clear the Tamper2 interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
}
}
#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
- /* Get the status of the Interrupt */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F)== SET)
+ /* Get the Tamper3 interrupts source enable status */
+ if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET)
{
- /* Get the TAMPER Interrupt enable bit and pending bit */
- if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \
- (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP3IE)) != (uint32_t)RESET))
+ /* Get the pending status of the Tamper3 Interrupt */
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)
{
- /* Tamper callback */
+ /* Tamper3 callback */
HAL_RTCEx_Tamper3EventCallback(hrtc);
- /* Clear the Tamper interrupt pending bit */
+ /* Clear the Tamper3 interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
}
}
#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
- * (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
- */
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) ||
+ * (STM32L011xx) || (STM32L021xx)
+ */
/* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
@@ -812,7 +837,10 @@
*/
__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
*/
}
@@ -824,7 +852,10 @@
*/
__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
*/
}
@@ -836,14 +867,18 @@
*/
__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
*/
}
#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
/**
* @brief Tamper 3 callback.
@@ -852,18 +887,21 @@
*/
__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
*/
}
#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
- * (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || (STM32L021xx)
*/
/**
- * @brief This function handles TimeStamp polling request.
+ * @brief Handle TimeStamp polling request.
* @param hrtc: RTC handle
* @param Timeout: Timeout duration
* @retval HAL status
@@ -901,8 +939,13 @@
return HAL_OK;
}
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
+ defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
/**
- * @brief This function handles Tamper1 Polling.
+ * @brief Handle Tamper 1 Polling.
* @param hrtc: RTC handle
* @param Timeout: Timeout duration
* @retval HAL status
@@ -932,9 +975,15 @@
return HAL_OK;
}
+#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) ||
+ * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) ||
+ * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) ||
+ * (STM32L031xx) || (STM32L041xx)
+ */
/**
- * @brief This function handles Tamper2 Polling.
+ * @brief Handle Tamper 2 Polling.
* @param hrtc: RTC handle
* @param Timeout: Timeout duration
* @retval HAL status
@@ -967,10 +1016,11 @@
#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
/**
- * @brief This function handles Tamper3 Polling.
+ * @brief Handle Tamper 3 Polling.
* @param hrtc: RTC handle
* @param Timeout: Timeout duration
* @retval HAL status
@@ -1001,7 +1051,7 @@
return HAL_OK;
}
#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
- * (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || (STM32L021xx)
*/
/**
@@ -1015,15 +1065,15 @@
===============================================================================
##### RTC Wake-up functions #####
===============================================================================
-
- [..] This section provide functions allowing to configure Wake-up feature
+
+ [..] This section provides functions allowing to configure Wake-up feature
@endverbatim
* @{
*/
/**
- * @brief Sets wake up timer.
+ * @brief Set wake up timer.
* @param hrtc: RTC handle
* @param WakeUpCounter: Wake up counter
* @param WakeUpClock: Wake up clock
@@ -1044,6 +1094,28 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
@@ -1090,7 +1162,7 @@
}
/**
- * @brief Sets wake up timer with interrupt
+ * @brief Set wake up timer with interrupt.
* @param hrtc: RTC handle
* @param WakeUpCounter: Wake up counter
* @param WakeUpClock: Wake up clock
@@ -1112,6 +1184,28 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
tickstart = HAL_GetTick();
@@ -1165,7 +1259,7 @@
}
/**
- * @brief Deactivates wake up timer counter.
+ * @brief Deactivate wake up timer counter.
* @param hrtc: RTC handle
* @retval HAL status
*/
@@ -1217,7 +1311,7 @@
}
/**
- * @brief Gets wake up timer counter.
+ * @brief Get wake up timer counter.
* @param hrtc: RTC handle
* @retval Counter value
*/
@@ -1228,16 +1322,14 @@
}
/**
- * @brief This function handles Wake Up Timer interrupt request.
+ * @brief Handle Wake Up Timer interrupt request.
* @param hrtc: RTC handle
* @retval None
*/
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
{
- if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))
- {
- /* Get the status of the Interrupt */
- if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
+ /* Get the pending status of the WAKEUPTIMER Interrupt */
+ if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET)
{
/* WAKEUPTIMER callback */
HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
@@ -1245,7 +1337,7 @@
/* Clear the WAKEUPTIMER interrupt pending bit */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
}
- }
+
/* Clear the EXTI's line Flag for RTC WakeUpTimer */
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
@@ -1261,14 +1353,17 @@
*/
__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
*/
}
/**
- * @brief This function handles Wake Up Timer Polling.
+ * @brief Handle Wake Up Timer Polling.
* @param hrtc: RTC handle
* @param Timeout: Timeout duration
* @retval HAL status
@@ -1313,25 +1408,25 @@
===============================================================================
[..]
This subsection provides functions allowing to
- (+) Writes a data in a specified RTC Backup data register
+ (+) Write a data in a specified RTC Backup data register
(+) Read a data in a specified RTC Backup data register
- (+) Sets the Coarse calibration parameters.
- (+) Deactivates the Coarse calibration parameters
- (+) Sets the Smooth calibration parameters.
- (+) Configures the Synchronization Shift Control Settings.
- (+) Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- (+) Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- (+) Enables the RTC reference clock detection.
+ (+) Set the Coarse calibration parameters.
+ (+) Deactivate the Coarse calibration parameters
+ (+) Set the Smooth calibration parameters.
+ (+) Configure the Synchronization Shift Control Settings.
+ (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Enable the RTC reference clock detection.
(+) Disable the RTC reference clock detection.
- (+) Enables the Bypass Shadow feature.
- (+) Disables the Bypass Shadow feature.
+ (+) Enable the Bypass Shadow feature.
+ (+) Disable the Bypass Shadow feature.
@endverbatim
* @{
*/
/**
- * @brief Writes a data in a specified RTC Backup data register.
+ * @brief Write a data in a specified RTC Backup data register.
* @param hrtc: RTC handle
* @param BackupRegister: RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
@@ -1376,16 +1471,16 @@
}
/**
- * @brief Sets the Smooth calibration parameters.
+ * @brief Set the Smooth calibration parameters.
* @param hrtc: RTC handle
* @param SmoothCalibPeriod: Select the Smooth Calibration Period.
* This parameter can be can be one of the following values :
- * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration periode is 32s.
- * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration periode is 16s.
- * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibartion periode is 8s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
* @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
* This parameter can be one of the following values:
- * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK puls every 2*11 pulses.
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
* @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
* @param SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
* This parameter can be one any value from 0 to 0x000001FF.
@@ -1451,7 +1546,7 @@
}
/**
- * @brief Configures the Synchronization Shift Control Settings.
+ * @brief Configure the Synchronization Shift Control Settings.
* @note When REFCKON is set, firmware must not write to Shift control register.
* @param hrtc: RTC handle
* @param ShiftAdd1S: Select to add or not 1 second to the time calendar.
@@ -1547,7 +1642,7 @@
}
/**
- * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
* @param hrtc: RTC handle
* @param CalibOutput : Select the Calibration output Selection .
* This parameter can be one of the following values:
@@ -1589,7 +1684,7 @@
}
/**
- * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
* @param hrtc: RTC handle
* @retval HAL status
*/
@@ -1618,7 +1713,7 @@
}
/**
- * @brief Enables the RTC reference clock detection.
+ * @brief Enable the RTC reference clock detection.
* @param hrtc: RTC handle
* @retval HAL status
*/
@@ -1716,7 +1811,7 @@
}
/**
- * @brief Enables the Bypass Shadow feature.
+ * @brief Enable the Bypass Shadow feature.
* @param hrtc: RTC handle
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
@@ -1748,7 +1843,7 @@
}
/**
- * @brief Disables the Bypass Shadow feature.
+ * @brief Disable the Bypass Shadow feature.
* @param hrtc: RTC handle
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
@@ -1805,14 +1900,16 @@
*/
__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RTC_AlarmBEventCallback could be implemented in the user file
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
*/
}
-
/**
- * @brief This function handles AlarmB Polling request.
+ * @brief Handle Alarm B Polling request.
* @param hrtc: RTC handle
* @param Timeout: Timeout duration
* @retval HAL status
@@ -1849,12 +1946,13 @@
/**
* @}
*/
-
+
#endif /* HAL_RTC_MODULE_ENABLED */
/**
* @}
*/
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_rtc_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of RTC HAL Extended module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -56,7 +56,7 @@
/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Types RTC Extended Exported Types
+/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
* @{
*/
@@ -100,44 +100,23 @@
*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTC Extended Exported Constants
+/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
* @{
*/
-
-/** @defgroup RTCEx_Interrupts_Definitions RTC Extended Interrupts Definitions
+/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
* @{
*/
-#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
-
-#define RTC_IT_TAMP3 RTC_TAMPCR_TAMP3IE
-
-#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
- * (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
- */
+#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
+#define RTC_OUTPUT_ALARMA ((uint32_t)RTC_CR_OSEL_0)
+#define RTC_OUTPUT_ALARMB ((uint32_t)RTC_CR_OSEL_1)
+#define RTC_OUTPUT_WAKEUP ((uint32_t)RTC_CR_OSEL)
+
/**
* @}
*/
-
-
-/** @defgroup RTCEx_Flags_Definitions RTC Extended Flags Definitions
- * @{
- */
-#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
-
-#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F
-
-#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
- * (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
- */
-
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Backup_Registers_Definitions RTC Extended Backup Registers Definition
+
+/** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definition
* @{
*/
#define RTC_BKP_DR0 ((uint32_t)0x00000000)
@@ -145,170 +124,133 @@
#define RTC_BKP_DR2 ((uint32_t)0x00000002)
#define RTC_BKP_DR3 ((uint32_t)0x00000003)
#define RTC_BKP_DR4 ((uint32_t)0x00000004)
-
-#define IS_RTC_BKP(__BKP__) (((__BKP__) == RTC_BKP_DR0) || \
- ((__BKP__) == RTC_BKP_DR1) || \
- ((__BKP__) == RTC_BKP_DR2) || \
- ((__BKP__) == RTC_BKP_DR3) || \
- ((__BKP__) == RTC_BKP_DR4))
/**
* @}
*/
-/** @defgroup RTC_Mask_Definition RTC Mask Definition
- * @{
- */
-/* Masks Definition */
-
-#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
-
-#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
- RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF | \
- RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \
- RTC_FLAG_INIT | RTC_FLAG_INITF | RTC_FLAG_RSF | \
- RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF | \
- RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF))
-
-#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
-
-#else
-
-#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP1F| \
- RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
- RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INIT | \
- RTC_FLAG_INITF | RTC_FLAG_RSF | RTC_FLAG_INITS | \
- RTC_FLAG_SHPF | RTC_FLAG_WUTWF |RTC_FLAG_ALRBWF | \
- RTC_FLAG_ALRAWF))
-
-#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
-
-#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
- * (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
- */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC Extended Time Stamp Edges definition
+/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
* @{
*/
#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
-#define IS_TIMESTAMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TIMESTAMPEDGE_RISING) || \
- ((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING))
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
+ * @{
+ */
+#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
+
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Extended Tamper Pins Definition
+
+/** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definition
* @{
*/
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
+ defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
+
+#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
-#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
+#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) ||
+ * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) ||
+ * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) ||
+ * (STM32L031xx) || (STM32L041xx)
+ */
+
#define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
-
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
+
#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E
#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
- * (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) ||
+ * (STM32L011xx) || (STM32L021xx)
*/
-#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXE))) == 0x00) && ((__TAMPER__) != (uint32_t)RESET))
-
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Extended Tamper Interrupt Definitions
+/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTCEx Tamper Interrupt Definitions
* @{
*/
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
+ defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
#define RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE
-#define RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE
-#define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE
+#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) ||
+ * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) ||
+ * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) ||
+ * (STM32L031xx) || (STM32L041xx)
+ */
+
+#define RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE
#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
-
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
+
#define RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE
-#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) (((__INTERRUPT__) == RTC_TAMPER1_INTERRUPT) || \
- ((__INTERRUPT__) == RTC_TAMPER2_INTERRUPT) || \
- ((__INTERRUPT__) == RTC_TAMPER3_INTERRUPT) || \
- ((__INTERRUPT__) == RTC_ALL_TAMPER_INTERRUPT ))
-
-#else
-
-#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) (((__INTERRUPT__) == RTC_TAMPER1_INTERRUPT) || \
- ((__INTERRUPT__) == RTC_TAMPER2_INTERRUPT) || \
- ((__INTERRUPT__) == RTC_ALL_TAMPER_INTERRUPT ))
#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
- * (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) ||
+ * (STM32L011xx) || (STM32L021xx)
*/
+#define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definitions
+ * @{
+ */
+#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
+#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002)
+#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
+#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
/**
* @}
*/
-/** @defgroup RTCEx_TimeStamp_Pin_Selections RTC Extended TimeStamp Pin Selection
- * @{
- */
-#define RTC_TIMESTAMPPIN_PC13 ((uint32_t)0x00000000)
-
-#define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_PC13))
+/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions
+* @{
+*/
+#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000)
+#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000)
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Extended Tamper Trigger Definition
- * @{
- */
-#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
-#define RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAMPCR_TAMP1TRG
-#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
-#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
-
-#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
- ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
- ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
- ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper MaskFlag Definitions
+* @{
+*/
+#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000)
+#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000)
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTC Extended Tamper EraseBackUp Definitions
-* @{
-*/
-#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000)
-#define RTC_TAMPER_ERASE_BACKUP_DISABLE RTC_TAMPCR_TAMP1NOERASE
-
-#define IS_RTC_TAMPER_ERASE_MODE(__MODE__) (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
- ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTC Extended Tamper MaskFlag Definitions
-* @{
-*/
-#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000)
-#define RTC_TAMPERMASK_FLAG_ENABLE RTC_TAMPCR_TAMP1MF
-
-#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__) (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE ) || \
- ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Extended Tamper Filter Definitions
+/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions
* @{
*/
#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
@@ -320,15 +262,11 @@
#define RTC_TAMPERFILTER_8SAMPLE RTC_TAMPCR_TAMPFLT /*!< Tamper is activated after 8
consecutive samples at the active leve. */
-#define IS_RTC_TAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \
- ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \
- ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \
- ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Extended Tamper Sampling Frequencies Definitions
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions
* @{
*/
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
@@ -349,19 +287,11 @@
RTC_TAMPCR_TAMPFREQ_2)) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 256 */
-#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
- ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
- ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
- ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
- ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
- ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
- ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
- ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Extended Tamper Pin Precharge Duration Definitions
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions
* @{
*/
#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
@@ -373,39 +303,31 @@
#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)(RTC_TAMPCR_TAMPPRCH_0 | RTC_TAMPCR_TAMPPRCH_1)) /*!< Tamper pins are pre-charged before
sampling during 8 RTCCLK cycles */
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION_) (((__DURATION_) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
- ((__DURATION_) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
- ((__DURATION_) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
- ((__DURATION_) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Extended Tamper TimeStampOnTamperDetection Definitions
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStampOnTamperDetection Definitions
* @{
*/
#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAMPCR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */
#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */
-#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__) (((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
- ((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Extended Tamper Pull UP Definitions
+/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definitions
* @{
*/
#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before sampling */
#define RTC_TAMPER_PULLUP_DISABLE RTC_TAMPCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */
-#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \
- ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))
/**
* @}
*/
-/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Extended Wakeup Timer Definitions
+/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
* @{
*/
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
@@ -414,100 +336,103 @@
#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t) (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1))
#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t) (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2))
-
-#define IS_RTC_WAKEUP_CLOCK(__CLOCK__) (((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
- ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
- ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
- ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
- ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
- ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-
-#define IS_RTC_WAKEUP_COUNTER(__COUNTER__) ((__COUNTER__) <= RTC_WUTR_WUT)
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Extended Smooth calib period Definitions
- * @{
- */
-#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
- period is 32s, else 2exp20 RTCCLK pulses */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CAL_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibation
- period is 16s, else 2exp19 RTCCLK pulses */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CAL_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibation
- period is 8s, else 2exp18 RTCCLK pulses */
-
-#define IS_RTC_SMOOTH_CALIB_PERIOD(__PERIOD__) (((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
- ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
- ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_8SEC))
/**
* @}
*/
-/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Extended Smooth calib Plus pulses Definitions
+/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions
* @{
*/
-#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CAL_CALP /*!< The number of RTCCLK pulses added
- during a X -second window = Y - CALM[8:0]
- with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
- during a 32-second window = CALM[8:0] */
+#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 32s, else 2exp20 RTCCLK pulses */
+#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 16s, else 2exp19 RTCCLK pulses */
+#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 8s, else 2exp18 RTCCLK pulses */
-#define IS_RTC_SMOOTH_CALIB_PLUS(__PLUS__) (((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
- ((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
/**
* @}
*/
-/** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions RTC Extended Smooth calib Minus pulses Definitions
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions
* @{
*/
-#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= RTC_CAL_CALM)
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
+ during a X -second window = Y - CALM[8:0]
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
+ during a 32-second window = CALM[8:0] */
+
/**
* @}
*/
-
-/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTC Extended Add 1 Second Parameter Definitions
- * @{
- */
-#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
-#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
-
-#define IS_RTC_SHIFT_ADD1S(__SEL__) (((__SEL__) == RTC_SHIFTADD1S_RESET) || \
- ((__SEL__) == RTC_SHIFTADD1S_SET))
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value RTC Extended Substract Fraction Of Second Value
- * @{
- */
-#define IS_RTC_SHIFT_SUBFS(__FS__) ((__FS__) <= RTC_SHIFTR_SUBFS)
-/**
- * @}
- */
-
- /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Extended Calib Output selection Definitions
+ /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
* @{
*/
#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
-#define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_CALIBOUTPUT_512HZ) || \
- ((__OUTPUT__) == RTC_CALIBOUTPUT_1HZ))
+/**
+ * @}
+ */
+
+
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions
+ * @{
+ */
+#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
+#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
/**
* @}
*/
+ /** @defgroup RTCEx_Interrupts_Definitions RTCEx Interrupts Definitions
+ * @{
+ */
+#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
+
+#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE)
+
+#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) ||
+ * (STM32L011xx) || (STM32L021xx)
+ */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Flags_Definitions RTCEx Flags Definitions
+ * @{
+ */
+#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
+
+#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)
+
+#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) ||
+ * (STM32L011xx) || (STM32L021xx)
+ */
+/**
+ * @}
+ */
+
/**
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTC Extended Exported Macros
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
* @{
*/
+/* ---------------------------------WAKEUPTIMER---------------------------------*/
+/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
+ * @{
+ */
/**
* @brief Enable the RTC WakeUp Timer peripheral.
* @param __HANDLE__: specifies the RTC handle.
@@ -516,13 +441,6 @@
#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
/**
- * @brief Enable the RTC TimeStamp peripheral.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
-
-/**
* @brief Disable the RTC WakeUp Timer peripheral.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
@@ -530,181 +448,65 @@
#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
/**
- * @brief Disable the RTC TimeStamp peripheral.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
-
-/**
- * @brief Enable the RTC calibration output.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
-
-/**
- * @brief Disable the calibration output.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
-
-/**
- * @brief Enable the clock reference detection.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
-
-/**
- * @brief Disable the clock reference detection.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
-
-/**
- * @brief Enable the RTC TimeStamp interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
* @brief Enable the RTC WakeUpTimer interrupt.
* @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
- * @brief Disable the RTC TimeStamp interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
* @brief Disable the RTC WakeUpTimer interrupt.
* @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
- * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
+ * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check.
* This parameter can be:
- * @arg RTC_IT_TAMP1
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
* @retval None
*/
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
-
-/**
- * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
/**
- * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
+ * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
* This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
-
-/**
- * @brief Get the selected RTC TimeStamp's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC TimeStamp Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TSF
- * @arg RTC_FLAG_TSOVF
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
/**
* @brief Get the selected RTC WakeUpTimer's flag status.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC WakeUpTimer Flag sources to be enabled or disabled.
+ * @param __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not.
* This parameter can be:
* @arg RTC_FLAG_WUTF
* @arg RTC_FLAG_WUTWF
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Get the selected RTC Tamper's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Get the selected RTC shift operation's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC shift operation Flag is pending or not.
- * This parameter can be:
- * @arg RTC_FLAG_SHPF
- * @retval None
- */
-#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Clear the RTC Time Stamp's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TSF
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& RTC_FLAGS_MASK)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
- * @brief Clear the RTC Tamper's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @retval None
- */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& RTC_FLAGS_MASK)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
/**
* @brief Clear the RTC Wake Up timer's pending flags.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * @param __FLAG__: specifies the RTC WakeUpTimer Flag to clear.
* This parameter can be:
* @arg RTC_FLAG_WUTF
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& RTC_FLAGS_MASK)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/* WAKE-UP TIMER EXTI */
/* ------------------ */
@@ -760,14 +562,14 @@
* @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); } while(0);
/**
* @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
* This parameter can be:
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); } while(0);
/**
* @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
@@ -786,8 +588,439 @@
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+/**
+ * @}
+ */
+
+/* ---------------------------------TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Timestamp RTC Timestamp
+ * @{
+ */
+/**
+ * @brief Enable the RTC TimeStamp peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
+
+/**
+ * @brief Disable the RTC TimeStamp peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
+
+/**
+ * @brief Enable the RTC TimeStamp interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC TimeStamp interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Get the selected RTC TimeStamp's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC TimeStamp Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @arg RTC_FLAG_TSOVF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Clear the RTC Time Stamp's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+ * @}
+ */
+
+/* ---------------------------------TAMPER------------------------------------*/
+/** @defgroup RTCEx_Tamper RTC Tamper
+ * @{
+ */
+
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
+ defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
+/**
+ * @brief Enable the RTC Tamper1 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
+
+/**
+ * @brief Disable the RTC Tamper1 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
+
+#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) ||
+ * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) ||
+ * (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) ||
+ * (STM32L031xx) || (STM32L041xx)
+ */
+
+/**
+ * @brief Enable the RTC Tamper2 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
+
+/**
+ * @brief Disable the RTC Tamper2 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
+
+
+#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
+
+/**
+ * @brief Enable the RTC Tamper3 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
+
+/**
+ * @brief Disable the RTC Tamper3 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
+
+#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) ||
+ * (STM32L011xx) || (STM32L021xx)
+ */
+/**************************************************************************************************/
+
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx)
+
+/**
+ * @brief Enable the RTC Tamper interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP: All tampers interrupts
+ * @arg RTC_IT_TAMP1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Tamper interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP: All tampers interrupts
+ * @arg RTC_IT_TAMP1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
+
+#elif defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
+
+/**
+ * @brief Enable the RTC Tamper interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP: All tampers interrupts
+ * @arg RTC_IT_TAMP1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @arg RTC_IT_TAMP3: Tamper3 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Tamper interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP: All tampers interrupts
+ * @arg RTC_IT_TAMP1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @arg RTC_IT_TAMP3: Tamper3 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
+
+#elif defined (STM32L011xx) || defined (STM32L021xx)
+
+/**
+ * @brief Enable the RTC Tamper interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP: All tampers interrupts
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @arg RTC_IT_TAMP3: Tamper3 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Tamper interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP: All tampers interrupts
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @arg RTC_IT_TAMP3: Tamper3 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
+
+#endif /* (STM32L011xx) || (STM32L021xx)
+ */
+
+/**************************************************************************************************/
+
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx)
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
+ ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET))
+
+#elif defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @arg RTC_IT_TAMP3: Tamper3 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \
+ ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
+ ((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
+
+#elif defined (STM32L011xx) || defined (STM32L021xx)
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @arg RTC_IT_TAMP3: Tamper3 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \
+ ((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))
+
+
+#endif /* (STM32L011xx) || (STM32L021xx)
+ */
+
+/**************************************************************************************************/
+
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx)
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP: All tampers interrupts
+ * @arg RTC_IT_TAMP1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+
+/**
+ * @brief Get the selected RTC Tamper's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F: Tamper1 flag
+ * @arg RTC_FLAG_TAMP2F: Tamper2 flag
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Clear the RTC Tamper's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F: Tamper1 flag
+ * @arg RTC_FLAG_TAMP2F: Tamper2 flag
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+
+#elif defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP: All tampers interrupts
+ * @arg RTC_IT_TAMP1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @arg RTC_IT_TAMP3: Tamper3 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+
+/**
+ * @brief Get the selected RTC Tamper's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F: Tamper1 flag
+ * @arg RTC_FLAG_TAMP2F: Tamper2 flag
+ * @arg RTC_FLAG_TAMP3F: Tamper3 flag
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Clear the RTC Tamper's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F: Tamper1 flag
+ * @arg RTC_FLAG_TAMP2F: Tamper2 flag
+ * @arg RTC_FLAG_TAMP3F: Tamper3 flag
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+#elif defined (STM32L011xx) || defined (STM32L021xx)
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP: All tampers interrupts
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @arg RTC_IT_TAMP3: Tamper3 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+
+/**
+ * @brief Get the selected RTC Tamper's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP2F: Tamper2 flag
+ * @arg RTC_FLAG_TAMP3F: Tamper3 flag
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Clear the RTC Tamper's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP2F: Tamper2 flag
+ * @arg RTC_FLAG_TAMP3F: Tamper3 flag
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+#endif /* (STM32L011xx) || (STM32L021xx)
+ */
+
+
+/**************************************************************************************************/
+
+/**
+ * @}
+ */
+
+/* --------------------------TAMPER/TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Tamper Timestamp EXTI
+ * @{
+ */
+
/* TAMPER TIMESTAMP EXTI */
/* --------------------- */
/**
@@ -842,20 +1075,20 @@
* @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); } while(0);
/**
* @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
* This parameter can be:
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); } while(0);
/**
* @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
* @retval Line Status.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
* @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
@@ -868,22 +1101,70 @@
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+/**
+ * @}
+ */
+/* ------------------------------Calibration----------------------------------*/
+/** @defgroup RTCEx_Calibration RTC Calibration
+ * @{
+ */
+
+/**
+ * @brief Enable the RTC calibration output.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
+
+/**
+ * @brief Disable the calibration output.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
+
+/**
+ * @brief Enable the clock reference detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
+
+/**
+ * @brief Disable the clock reference detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
+
+/**
+ * @brief Get the selected RTC shift operation's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC shift operation Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_SHPF
+ * @retval None
+ */
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+/**
+ * @}
+ */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Functions RTC Extended Exported Functions
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
* @{
*/
+/* RTC TimeStamp and Tamper functions *****************************************/
/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp and Tamper functions
* @{
*/
-/* RTC TimeStamp and Tamper functions *****************************************/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
@@ -898,12 +1179,14 @@
void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
- * (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) ||
+ * (STM32L011xx) || (STM32L021xx)
*/
void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
@@ -912,27 +1195,29 @@
HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
- defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx)
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) ||
- * (STM32L073xx) || (STM32L072xx) || (STM32L071xx)
+ * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || (STM32L031xx) || (STM32L041xx) ||
+ * (STM32L011xx) || (STM32L021xx)
*/
/**
* @}
*/
+/* RTC Wake-up functions ******************************************************/
/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
* @{
*/
-/* RTC Wake-up functions ******************************************************/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
@@ -940,15 +1225,15 @@
* @}
*/
+/* Extended Control functions ************************************************/
/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
* @{
*/
-/* Extended Control functions ************************************************/
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
@@ -966,6 +1251,175 @@
*/
void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
+ * @{
+ */
+
+/* Masks Definition */
+
+#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \
+ defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx)
+
+#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP1F| \
+ RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
+ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \
+ RTC_FLAG_INITF | RTC_FLAG_RSF | RTC_FLAG_INITS | \
+ RTC_FLAG_SHPF | RTC_FLAG_WUTWF |RTC_FLAG_ALRBWF | \
+ RTC_FLAG_ALRAWF))
+
+#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
+#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | \
+ RTC_ALL_TAMPER_INTERRUPT))
+
+#elif defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+ defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+ defined (STM32L031xx) || defined (STM32L041xx)
+
+#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
+ RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF | \
+ RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \
+ RTC_FLAG_INITF | RTC_FLAG_RSF | \
+ RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF | \
+ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF))
+
+#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))
+#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | \
+ RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))
+
+#elif defined (STM32L011xx) || defined (STM32L021xx)
+
+#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
+ RTC_FLAG_TSOVF | RTC_FLAG_TSF | \
+ RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \
+ RTC_FLAG_INITF | RTC_FLAG_RSF | \
+ RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF | \
+ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF))
+
+#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E))
+#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER2_INTERRUPT | \
+ RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))
+#endif /* (STM32L011xx) || (STM32L021xx)
+ */
+
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_IM19) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_IM20) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
+ * @{
+ */
+
+/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
+ * @{
+ */
+
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
+ ((OUTPUT) == RTC_OUTPUT_WAKEUP))
+
+#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
+
+#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
+ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
+
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXE))) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXIE)) == 0x00) && ((INTERRUPT) != (uint32_t)RESET))
+
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
+
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+
+#define IS_RTC_TAMPER_ERASE_MODE(MODE) (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
+ ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
+
+#define IS_RTC_TAMPER_MASKFLAG_STATE(STATE) (((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \
+ ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE))
+
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
+
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
+
+#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+
+#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
+ ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
+
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
+
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
+
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
+ ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
+
+
+/** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions RTCEx Smooth calib Minus pulses Definitions
+ * @{
+ */
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
+/**
+ * @}
+ */
+
+
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
+ ((SEL) == RTC_SHIFTADD1S_SET))
+
+
+
+/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value RTCEx Substract Fraction Of Second Value
+ * @{
+ */
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
+/**
+ * @}
+ */
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
+ ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
/**
* @}
@@ -975,6 +1429,8 @@
* @}
*/
+
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_smartcard.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief SMARTCARD HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -60,7 +60,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -94,12 +94,16 @@
* @{
*/
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
/** @addtogroup SMARTCARD
* @brief HAL SMARTCARD module driver
* @{
*/
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-
+
+/** @addtogroup SMARTCARD_Private SMARTCARD Private
+ * @{
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define TEACK_REACK_TIMEOUT 1000
@@ -122,6 +126,9 @@
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc);
/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
/** @addtogroup SMARTCARD_Exported_Functions
* @{
@@ -191,6 +198,9 @@
if(hsc->State == HAL_SMARTCARD_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hsc->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, CORTEX */
HAL_SMARTCARD_MspInit(hsc);
}
@@ -261,6 +271,9 @@
*/
__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMARTCARD_MspInit could be implenetd in the user file
*/
@@ -273,6 +286,9 @@
*/
__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMARTCARD_MspDeInit could be implenetd in the user file
*/
@@ -780,6 +796,9 @@
*/
__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
*/
@@ -792,6 +811,9 @@
*/
__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
*/
@@ -804,6 +826,9 @@
*/
__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMARTCARD_ErrorCallback could be implemented in the user file
*/
@@ -994,7 +1019,7 @@
MODIFY_REG(hsc->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
- /* Stop bits are forced to 1.5 (STOP = 11) */
+ /* Stop bits allowed in smartcard mode are 0.5 (receiving mode only) and 1.5 */
tmpreg = hsc->Init.StopBits;
/* Synchronous mode is activated by default */
tmpreg |= (uint32_t) USART_CR2_CLKEN | hsc->Init.CLKPolarity;
@@ -1279,11 +1304,12 @@
* @}
*/
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_smartcard.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -53,7 +53,9 @@
/** @defgroup SMARTCARD SMARTCARD
* @{
*/
-
+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
+ * @{
+ */
/* Exported types ------------------------------------------------------------*/
/**
* @brief SMARTCARD Init Structure definition
@@ -68,7 +70,7 @@
This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
uint32_t StopBits; /*!< Specifies the number of stop bits @ref SMARTCARD_Stop_Bits.
- Only 1.5 stop bits are authorized in SmartCard mode. */
+ Only 0.5 or 1.5 stop bits are authorized in SmartCard mode. */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref SMARTCARD_Parity
@@ -165,17 +167,6 @@
HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
}HAL_SMARTCARD_StateTypeDef;
-/**
- * @brief HAL SMARTCARD Error Code definition
- */
-
-#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
-#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
-#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04) /*!< frame error */
-#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
-#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
-#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x20) /*!< Receiver TimeOut error */
/**
@@ -225,15 +216,37 @@
}SMARTCARD_HandleTypeDef;
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants
* @{
*/
+/**
+ * @brief HAL SMARTCARD Error Code definition
+ */
+/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
+ * @{
+ */
+#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04) /*!< frame error */
+#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
+#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x20) /*!< Receiver TimeOut error */
+
+/**
+ * @}
+ */
+
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
* @{
*/
-#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
+#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
/**
* @}
@@ -242,8 +255,10 @@
/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Stop Bits
* @{
*/
+#define SMARTCARD_STOPBITS_0_5 ((uint32_t)(USART_CR2_STOP_0))
#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP))
-#define IS_SMARTCARD_STOPBITS(STOPBITS) ((STOPBITS) == SMARTCARD_STOPBITS_1_5)
+#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
+ ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
/**
* @}
*/
@@ -451,18 +466,20 @@
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
-#define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000)
-#define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000)
-#define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000)
-#define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000)
-#define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800)
-#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)
-#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040)
-#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)
-#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008)
-#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004)
-#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002)
-#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001)
+#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
+#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
+#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
+#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
+#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
+#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */
+#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
+#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */
+#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
+#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
+#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
+#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
+#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
+
/**
* @}
*/
@@ -478,18 +495,19 @@
* @{
*/
-#define SMARTCARD_IT_PE ((uint16_t)0x0028)
-#define SMARTCARD_IT_TXE ((uint16_t)0x0727)
-#define SMARTCARD_IT_TC ((uint16_t)0x0626)
-#define SMARTCARD_IT_RXNE ((uint16_t)0x0525)
+#define SMARTCARD_IT_PE ((uint16_t)0x0028) /*!< SMARTCARD parity error interruption */
+#define SMARTCARD_IT_TXE ((uint16_t)0x0727) /*!< SMARTCARD transmit data register empty interruption */
+#define SMARTCARD_IT_TC ((uint16_t)0x0626) /*!< SMARTCARD transmission complete interruption */
+#define SMARTCARD_IT_RXNE ((uint16_t)0x0525) /*!< SMARTCARD read data register not empty interruption */
+#define SMARTCARD_IT_IDLE ((uint16_t)0x0424) /*!< SMARTCARD idle line detection interruption */
-#define SMARTCARD_IT_ERR ((uint16_t)0x0060)
-#define SMARTCARD_IT_ORE ((uint16_t)0x0300)
-#define SMARTCARD_IT_NE ((uint16_t)0x0200)
-#define SMARTCARD_IT_FE ((uint16_t)0x0100)
+#define SMARTCARD_IT_ERR ((uint16_t)0x0060) /*!< SMARTCARD error interruption */
+#define SMARTCARD_IT_ORE ((uint16_t)0x0300) /*!< SMARTCARD overrun error interruption */
+#define SMARTCARD_IT_NE ((uint16_t)0x0200) /*!< SMARTCARD noise error interruption */
+#define SMARTCARD_IT_FE ((uint16_t)0x0100) /*!< SMARTCARD frame error interruption */
-#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B)
-#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A)
+#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B) /*!< SMARTCARD end of block interruption */
+#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A) /*!< SMARTCARD receiver timeout interruption */
/**
* @}
*/
@@ -594,7 +612,7 @@
* @arg SMARTCARD_CLEAR_EOBF
* @retval None
*/
-#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ~(__FLAG__))
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** @brief Clear the SMARTCARD PE pending flag.
* @param __HANDLE__: specifies the SMARTCARD Handle.
@@ -640,6 +658,7 @@
* @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
+ * @arg SMARTCARD_FLAG_IDLE: Idle line detection flag
* @arg SMARTCARD_FLAG_ORE: OverRun Error flag
* @arg SMARTCARD_FLAG_NE: Noise Error flag
* @arg SMARTCARD_FLAG_FE: Framing Error flag
@@ -653,11 +672,12 @@
* The Handle Instance which can be USART1 or USART2.
* @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
- * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
+ * @arg SMARTCARD_IT_EOB: End Of Block interrupt
+ * @arg SMARTCARD_IT_RTO: Receive TimeOut interrupt
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
* @arg SMARTCARD_IT_PE: Parity Error interrupt
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
@@ -670,11 +690,12 @@
* The Handle Instance which can be USART1 or USART2.
* @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
- * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
+ * @arg SMARTCARD_IT_EOB: End Of Block interrupt
+ * @arg SMARTCARD_IT_RTO: Receive TimeOut interrupt
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
* @arg SMARTCARD_IT_PE: Parity Error interrupt
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
@@ -688,11 +709,12 @@
* The Handle Instance which can be USART1 or USART2.
* @param __IT__: specifies the SMARTCARD interrupt to check.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
- * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
+ * @arg SMARTCARD_IT_EOB: End Of Block interrupt
+ * @arg SMARTCARD_IT_RTO: Receive TimeOut interrupt
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
* @arg SMARTCARD_IT_ORE: OverRun Error interrupt
* @arg SMARTCARD_IT_NE: Noise Error interrupt
* @arg SMARTCARD_IT_FE: Framing Error interrupt
@@ -706,11 +728,12 @@
* The Handle Instance which can be USART1 or USART2.
* @param __IT__: specifies the SMARTCARD interrupt source to check.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
- * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
+ * @arg SMARTCARD_IT_EOB: End Of Block interrupt
+ * @arg SMARTCARD_IT_RTO: Receive TimeOut interrupt
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
* @arg SMARTCARD_IT_ORE: OverRun Error interrupt
* @arg SMARTCARD_IT_NE: Noise Error interrupt
* @arg SMARTCARD_IT_FE: Framing Error interrupt
@@ -728,13 +751,14 @@
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
- * @arg USART_CLEAR_PEF: Parity Error Clear Flag
- * @arg USART_CLEAR_FEF: Framing Error Clear Flag
- * @arg USART_CLEAR_NEF: Noise detected Clear Flag
- * @arg USART_CLEAR_OREF: OverRun Error Clear Flag
- * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
- * @arg USART_CLEAR_RTOF: Receiver Time Out Clear Flag
- * @arg USART_CLEAR_EOBF: End Of Block Clear Flag
+ * @arg SMARTCARD_CLEAR_PEF: Parity error clear flag
+ * @arg SMARTCARD_CLEAR_FEF: Framing error clear flag
+ * @arg SMARTCARD_CLEAR_NEF: Noise detected clear flag
+ * @arg SMARTCARD_CLEAR_OREF: OverRun error clear flag
+ * @arg SMARTCARD_CLEAR_IDLEF: Idle line detection clear flag
+ * @arg SMARTCARD_CLEAR_TCF: Transmission complete clear flag
+ * @arg SMARTCARD_CLEAR_RTOF: Receiver timeout clear flag
+ * @arg SMARTCARD_CLEAR_EOBF: End of block clear flag
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
@@ -871,6 +895,16 @@
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup SMARTCARD_Private SMARTCARD Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard_ex.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard_ex.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_smartcard_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief SMARTCARD HAL module driver.
*
* This file provides extended firmware functions to manage the following
@@ -25,7 +25,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -59,12 +59,14 @@
* @{
*/
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+
/** @addtogroup SMARTCARDEx
* @brief SMARTCARD Extended HAL module driver
* @{
*/
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -172,11 +174,10 @@
* @}
*/
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
/**
* @}
*/
-
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_smartcard_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -57,13 +57,16 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
-
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Exported_Macros SMARTCARDEx Exported Macros
+ * @{
+ */
/** @brief Reports the SMARTCARD clock source.
* @param __HANDLE__: specifies the USART Handle
* @param __CLOCKSOURCE__ : output variable
* @retval the USART clocking source, written in __CLOCKSOURCE__.
*/
-#if defined (STM32L031xx) || defined (STM32L041xx)
+#if defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART2) \
@@ -88,7 +91,7 @@
} \
} while(0)
-#else /* (STM32L031xx) || defined (STM32L041xx) */
+#else /* (STM32L031xx) || defined (STM32L041xx) || (STM32L011xx) || defined (STM32L021xx) */
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
@@ -133,10 +136,14 @@
} \
} \
} while(0)
-#endif /* (STM32L031xx) || (STM32L041xx) */
+#endif /* (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || defined (STM32L021xx) */
+
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
-/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported functions
+/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_smbus.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief SMBUS HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -38,7 +38,7 @@
Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
(#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
- (+) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ (+) These API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
by calling the customed HAL_SMBUS_MspInit(&hsmbus) API.
(#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
@@ -98,7 +98,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -132,14 +132,18 @@
* @{
*/
-/** @defgroup SMBUS
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/** @addtogroup SMBUS
* @brief SMBUS HAL module driver
* @{
*/
-#ifdef HAL_SMBUS_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
+/** @addtogroup SMBUS_Private
+ * @{
+ */
/* Private define ------------------------------------------------------------*/
#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! SMBUS TIMING clear register Mask */
#define HAL_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
@@ -166,14 +170,17 @@
static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/**
+ * @}
+ */
/* Private functions ---------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Functions
+/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
* @{
*/
-/** @defgroup SMBUS_Group1 Initialization and de-initialization functions
+/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -238,6 +245,9 @@
if(hsmbus->State == HAL_SMBUS_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hsmbus->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_SMBUS_MspInit(hsmbus);
}
@@ -348,6 +358,9 @@
*/
__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMBUS_MspInit could be implemented in the user file
*/
@@ -361,6 +374,9 @@
*/
__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMBUS_MspDeInit could be implemented in the user file
*/
@@ -370,7 +386,7 @@
* @}
*/
-/** @defgroup SMBUS_Group2 IO operation functions
+/** @addtogroup SMBUS_Exported_Functions_Group2
* @brief Data transfers functions
*
@verbatim
@@ -1111,6 +1127,9 @@
*/
__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMBUS_TxCpltCallback could be implemented in the user file
*/
@@ -1124,6 +1143,9 @@
*/
__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMBUS_TxCpltCallback could be implemented in the user file
*/
@@ -1136,6 +1158,9 @@
*/
__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMBUS_TxCpltCallback could be implemented in the user file
*/
@@ -1149,6 +1174,9 @@
*/
__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMBUS_TxCpltCallback could be implemented in the user file
*/
@@ -1164,6 +1192,11 @@
*/
__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+ UNUSED(TransferDirection);
+ UNUSED(AddrMatchCode);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMBUS_AddrCallback could be implemented in the user file
*/
@@ -1177,9 +1210,12 @@
*/
__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMBUS_ListenCpltCallback could be implemented in the user file
- */
+ */
}
/**
@@ -1190,6 +1226,9 @@
*/
__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SMBUS_ErrorCallback could be implemented in the user file
*/
@@ -1199,7 +1238,7 @@
* @}
*/
-/** @defgroup SMBUS_Group3 Peripheral State and Errors functions
+/** @addtogroup SMBUS_Exported_Functions_Group3
* @brief Peripheral State and Errors functions
*
@verbatim
@@ -1240,6 +1279,14 @@
*/
/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Private
+ * @{
+ */
+
+/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
@@ -1805,7 +1852,7 @@
* @arg SMBUS_SOFTEND_MODE: Enable Software end mode and Reload mode.
* @param Request: new state of the SMBUS START condition generation.
* This parameter can be one of the following values:
- * @arg SMBUS_NO_STARTSTOP: Don't Generate stop and start condition.
+ * @arg SMBUS_NO_STARTSTOP: Do not Generate stop and start condition.
* @arg SMBUS_GENERATE_STOP: Generate stop condition (Size should be set to 0).
* @arg SMBUS_GENERATE_START_READ: Generate Restart for read request.
* @arg SMBUS_GENERATE_START_WRITE: Generate Restart for write request.
@@ -1834,11 +1881,7 @@
hsmbus->Instance->CR2 = tmpreg;
}
-/**
- * @}
- */
-#endif /* HAL_SMBUS_MODULE_ENABLED */
/**
* @}
*/
@@ -1847,5 +1890,11 @@
* @}
*/
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_smbus.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of SMBUS HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,11 +50,14 @@
* @{
*/
-/** @addtogroup SMBUS
+/** @defgroup SMBUS SMBUS
* @{
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
+ * @{
+ */
/**
* @brief SMBUS Configuration Structure definition
@@ -105,7 +108,6 @@
* @brief HAL States definition
* @{
*/
-
#define HAL_SMBUS_STATE_RESET 0x00 /*!< SMBUS not yet initialized or disabled */
#define HAL_SMBUS_STATE_READY 0x01 /*!< SMBUS initialized and ready for use */
#define HAL_SMBUS_STATE_BUSY 0x02 /*!< SMBUS internal process is ongoing */
@@ -164,13 +166,17 @@
}SMBUS_HandleTypeDef;
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMBUS_Exported_Constants
+/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
* @{
*/
-/** @defgroup SMBUS_Analog_Filter
+/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
* @{
*/
#define SMBUS_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
@@ -182,7 +188,7 @@
* @}
*/
-/** @defgroup SMBUS_addressing_mode
+/** @defgroup SMBUS_addressing_mode SMBUS Addressing Mode
* @{
*/
#define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
@@ -194,7 +200,7 @@
* @}
*/
-/** @defgroup SMBUS_dual_addressing_mode
+/** @defgroup SMBUS_dual_addressing_mode SMBUS Dual Addressing Mode
* @{
*/
@@ -207,7 +213,7 @@
* @}
*/
-/** @defgroup SMBUS_own_address2_masks
+/** @defgroup SMBUS_own_address2_masks SMBUS Own Address2 Masks
* @{
*/
@@ -233,7 +239,7 @@
*/
-/** @defgroup SMBUS_general_call_addressing_mode
+/** @defgroup SMBUS_general_call_addressing_mode SMBUS General Call Enabling
* @{
*/
#define SMBUS_GENERALCALL_DISABLE ((uint32_t)0x00000000)
@@ -245,7 +251,7 @@
* @}
*/
-/** @defgroup SMBUS_nostretch_mode
+/** @defgroup SMBUS_nostretch_mode SMBUS Nostretch Enabling
* @{
*/
#define SMBUS_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
@@ -257,7 +263,7 @@
* @}
*/
-/** @defgroup SMBUS_packet_error_check_mode
+/** @defgroup SMBUS_packet_error_check_mode SMBUS Packet Error Check Enabling
* @{
*/
#define SMBUS_PEC_DISABLE ((uint32_t)0x00000000)
@@ -269,7 +275,7 @@
* @}
*/
-/** @defgroup SMBUS_peripheral_mode
+/** @defgroup SMBUS_peripheral_mode SMBUS Peripheral Mode
* @{
*/
#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN)
@@ -283,7 +289,7 @@
* @}
*/
-/** @defgroup SMBUS_ReloadEndMode_definition
+/** @defgroup SMBUS_ReloadEndMode_definition SMBUS Mode Definition
* @{
*/
@@ -303,7 +309,7 @@
* @}
*/
-/** @defgroup SMBUS_StartStopMode_definition
+/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStop Mode Definition
* @{
*/
@@ -320,7 +326,7 @@
* @}
*/
-/** @defgroup SMBUS_XferOptions_definition
+/** @defgroup SMBUS_XferOptions_definition SMBUS Transfer Request Definition
* @{
*/
@@ -342,7 +348,7 @@
* @}
*/
-/** @defgroup SMBUS_Interrupt_configuration_definition
+/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt Configuration Definition
* @brief SMBUS Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
@@ -363,7 +369,7 @@
* @}
*/
-/** @defgroup SMBUS_Flag_definition
+/** @defgroup SMBUS_Flag_definition SMBUS Flag Definition
* @brief Flag definition
* Elements values convention: 0xXXXXYYYY
* - XXXXXXXX : Flag mask
@@ -395,6 +401,9 @@
*/
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
+ * @{
+ */
/** @brief Reset SMBUS handle state
* @param __HANDLE__: specifies the SMBUS Handle.
@@ -502,15 +511,33 @@
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
+ * @{
+ */
+
/* Initialization and de-initialization functions ****************************/
+/* IO operation functions ****************************************************/
+/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
-
+/**
+ * @}
+ */
+
/* IO operation functions ****************************************************/
+/** @defgroup SMBUS_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
@@ -542,8 +569,14 @@
#define HAL_SMBUS_ListenCpltCallback HAL_SMBUS_ListenCpltCallback
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
+/**
+ * @}
+ */
/* Peripheral State and Errors functions *************************************/
+/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
@@ -554,7 +587,24 @@
/**
* @}
*/
-
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup SMBUS_Private SMBUS_Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_spi.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief SPI HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -118,7 +118,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -152,29 +152,24 @@
* @{
*/
-/** @defgroup SPI SPI
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/** @addtogroup SPI
* @brief SPI HAL module driver
* @{
*/
-#ifdef HAL_SPI_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
+/** @addtogroup SPI_Private
* @{
*/
#define SPI_TIMEOUT_VALUE 10
-/**
- * @}
- */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
- * @{
- */
+
static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
static void SPI_TxISR(SPI_HandleTypeDef *hspi);
static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
@@ -194,11 +189,11 @@
/* Exported functions ---------------------------------------------------------*/
-/** @defgroup SPI_Exported_Functions SPI Exported Functions
+/** @addtogroup SPI_Exported_Functions SPI Exported Functions
* @{
*/
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -262,6 +257,9 @@
if(hspi->State == HAL_SPI_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hspi->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
}
@@ -285,9 +283,11 @@
/* Configure : CRC Polynomial */
WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-
+#endif
+
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->State = HAL_SPI_STATE_READY;
@@ -333,9 +333,12 @@
*/
__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_MspInit could be implenetd in the user file
- */
+ */
}
/**
@@ -346,6 +349,9 @@
*/
__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_MspDeInit could be implenetd in the user file
*/
@@ -355,7 +361,7 @@
* @}
*/
-/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
+/** @addtogroup SPI_Exported_Functions_Group2
* @brief Data transfers functions
*
@verbatim
@@ -1656,6 +1662,9 @@
*/
__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_TxCpltCallback could be implenetd in the user file
*/
@@ -1669,6 +1678,9 @@
*/
__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_RxCpltCallback() could be implenetd in the user file
*/
@@ -1682,6 +1694,9 @@
*/
__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
*/
@@ -1695,6 +1710,9 @@
*/
__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
*/
@@ -1708,6 +1726,9 @@
*/
__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
*/
@@ -1721,6 +1742,9 @@
*/
__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
*/
@@ -1734,6 +1758,9 @@
*/
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : - This function Should not be modified, when the callback is needed,
the HAL_SPI_ErrorCallback() could be implenetd in the user file.
- The ErrorCode parameter in the hspi handle is updated by the SPI processes
@@ -1745,7 +1772,7 @@
* @}
*/
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief SPI control functions
*
@verbatim
@@ -1792,7 +1819,7 @@
-/** @addtogroup SPI_Private_Functions
+/** @addtogroup SPI_Private
* @{
*/
@@ -2376,11 +2403,12 @@
* @}
*/
-#endif /* HAL_SPI_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_SPI_MODULE_ENABLED */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_spi.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,7 +50,7 @@
* @{
*/
-/** @addtogroup SPI
+/** @defgroup SPI SPI
* @{
*/
@@ -581,12 +581,12 @@
*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions
+/** @defgroup SPI_Exported_Functions SPI Exported Functions
* @{
*/
/* Initialization/de-initialization functions **********************************/
-/** @addtogroup SPI_Exported_Functions_Group1
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
@@ -598,7 +598,7 @@
*/
/* I/O operation functions *****************************************************/
-/** @addtogroup SPI_Exported_Functions_Group2
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
* @{
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -628,7 +628,7 @@
/* Peripheral State and Control functions **************************************/
-/** @addtogroup SPI_Exported_Functions_Group3
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
* @{
*/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
@@ -642,6 +642,23 @@
* @}
*/
+/* Private group definition ------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup SPI_Private SPI Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_tim.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief TIM HAL module driver.
* @brief This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@@ -101,7 +101,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -135,13 +135,16 @@
* @{
*/
+#ifdef HAL_TIM_MODULE_ENABLED
+
/** @addtogroup TIM
* @brief TIM HAL module driver
* @{
*/
-#ifdef HAL_TIM_MODULE_ENABLED
-
+/** @addtogroup TIM_Private
+ * @{
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -164,6 +167,9 @@
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,TIM_SlaveConfigTypeDef * sSlaveConfig);
+/**
+ * @}
+ */
/*******************************************************************************/
/* Exported functions ---------------------------------------------------------*/
@@ -217,6 +223,9 @@
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
}
@@ -267,6 +276,9 @@
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_Base_MspInit could be implemented in the user file
*/
@@ -279,6 +291,9 @@
*/
__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_Base_MspDeInit could be implemented in the user file
*/
@@ -487,6 +502,9 @@
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA*/
HAL_TIM_OC_MspInit(htim);
}
@@ -536,6 +554,9 @@
*/
__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_OC_MspInit could be implemented in the user file
*/
@@ -548,6 +569,9 @@
*/
__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_OC_MspDeInit could be implemented in the user file
*/
@@ -951,6 +975,9 @@
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
}
@@ -1001,6 +1028,9 @@
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
@@ -1013,6 +1043,9 @@
*/
__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspDeInit could be implemented in the user file
*/
@@ -1418,6 +1451,9 @@
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspInit(htim);
}
@@ -1468,6 +1504,9 @@
*/
__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_IC_MspInit could be implemented in the user file
*/
@@ -1480,6 +1519,9 @@
*/
__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_IC_MspDeInit could be implemented in the user file
*/
@@ -1887,6 +1929,9 @@
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OnePulse_MspInit(htim);
}
@@ -1943,6 +1988,9 @@
*/
__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_OnePulse_MspInit could be implemented in the user file
*/
@@ -1955,6 +2003,9 @@
*/
__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
*/
@@ -2137,6 +2188,9 @@
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_Encoder_MspInit(htim);
}
@@ -2227,6 +2281,9 @@
*/
__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_Encoder_MspInit could be implemented in the user file
*/
@@ -2240,6 +2297,9 @@
*/
__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
*/
@@ -3604,6 +3664,9 @@
sClearInputConfig->ClearInputPrescaler,
sClearInputConfig->ClearInputPolarity,
sClearInputConfig->ClearInputFilter);
+
+ /* Set the OCREF clear selection bit */
+ htim->Instance->SMCR |= TIM_SMCR_OCCS;
}
switch (Channel)
@@ -3694,11 +3757,8 @@
htim->State = HAL_TIM_STATE_BUSY;
- /* Check the parameters */
+ /* Check the clock source */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
@@ -3719,6 +3779,9 @@
case TIM_CLOCKSOURCE_ETRMODE1:
{
assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
sClockSourceConfig->ClockPrescaler,
@@ -3738,6 +3801,9 @@
case TIM_CLOCKSOURCE_ETRMODE2:
{
assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
sClockSourceConfig->ClockPrescaler,
@@ -3751,6 +3817,8 @@
case TIM_CLOCKSOURCE_TI1:
{
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
@@ -3760,6 +3828,8 @@
case TIM_CLOCKSOURCE_TI2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
@@ -3769,6 +3839,8 @@
case TIM_CLOCKSOURCE_TI1ED:
{
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
@@ -4018,6 +4090,9 @@
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
@@ -4030,6 +4105,9 @@
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
@@ -4041,6 +4119,9 @@
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
@@ -4053,6 +4134,9 @@
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
@@ -4065,6 +4149,9 @@
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
@@ -4077,6 +4164,9 @@
*/
__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_ErrorCallback could be implemented in the user file
*/
@@ -4256,7 +4346,7 @@
/* Private functions */
/*************************************************************/
-/** @defgroup TIM_Private_Functions TIM Private Functions
+/** @addtogroup TIM_Private TIM Private
* @{
*/
/**
@@ -5009,11 +5099,12 @@
* @}
*/
-#endif /* HAL_TIM_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_TIM_MODULE_ENABLED */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_tim.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -579,15 +579,6 @@
/**
* @}
*/
-#define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFFA0) == 0x00000000) && ((__IT__) != 0x00000000))
-
-#define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) || \
- ((__IT__) == TIM_IT_CC1) || \
- ((__IT__) == TIM_IT_CC2) || \
- ((__IT__) == TIM_IT_CC3) || \
- ((__IT__) == TIM_IT_CC4) || \
- ((__IT__) == TIM_IT_TRIGGER))
-
/** @defgroup TIM_DMA_sources DMA sources
* @{
@@ -636,17 +627,6 @@
/**
* @}
*/
-#define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \
- ((__FLAG__) == TIM_FLAG_CC1) || \
- ((__FLAG__) == TIM_FLAG_CC2) || \
- ((__FLAG__) == TIM_FLAG_CC3) || \
- ((__FLAG__) == TIM_FLAG_CC4) || \
- ((__FLAG__) == TIM_FLAG_TRIGGER) || \
- ((__FLAG__) == TIM_FLAG_CC1OF) || \
- ((__FLAG__) == TIM_FLAG_CC2OF) || \
- ((__FLAG__) == TIM_FLAG_CC3OF) || \
- ((__FLAG__) == TIM_FLAG_CC4OF))
-
/** @defgroup TIM_Clock_Source Clock source
* @{
@@ -1228,9 +1208,9 @@
* @note When the URS bit of the TIMx_CR1 register is reset, any of the
* following events generate an update interrupt or DMA request (if
* enabled):
- * Counter overflow/underflow
- * Setting the UG bit
- * Update generation through the slave mode controller
+ * Counter overflow/underflow
+ * Setting the UG bit
+ * Update generation through the slave mode controller
* @retval None
*/
#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
@@ -1493,6 +1473,16 @@
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup TIM_Private TIM Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim_ex.c Sun Apr 17 17:45:10 2016 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim_ex.c Tue Apr 19 11:15:15 2016 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.2.0 - * @date 06-February-2015 + * @version V1.5.0 + * @date 8-January-2016 * @brief TIM HAL module driver. * @brief This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -55,7 +55,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -183,6 +183,7 @@ * GPIOA(0)_AF5 or GPIOA(5)_AF2 or * GPIOA(15)_AF2 or GPIOE(9)_AF2 * @arg TIM2_ETR_HSI48: TIM2 ETR connected to HSI48 + * @arg TIM2_ETR_HSI16: TIM2 ETR connected to HSI16 * @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE * @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output * @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output @@ -248,6 +249,114 @@ * * @retval HAL status */ +#elif defined (STM32L031xx) || defined (STM32L041xx) + /** + * @brief Configures the remapping of the TIM2, TIM21 and TIM22 inputs. + * The channel inputs (T1..T4) and the Trigger input (ETR) of the + * timers can be remaped thanks to this function. When an input is + * mapped, on a GPIO, refer yourself to the GPIO alternate functions + * for more details. + * + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Remap: specifies the TIM input remapping source. + * This parameter is a combination of the following values + * depending on TIM instance: + * + * For TIM2, the parameter can have the following values: + * @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default): + * GPIOA(0)_AF5 or GPIOA(5)_AF2 or + * GPIOA(15)_AF2 + * @arg TIM2_ETR_HSI16: TIM2 ETR connected to HS16 (HSIOUT) + * @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE + * @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output + * @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output + * @arg TIM2_TI4_GPIO : TIM2 TI4 connected to GPIO (default): + * GPIOA(3)_AF2 or GPIOB(11)_AF2 or + * GPIOB(1)_AF5 + * @arg TIM2_TI4_COMP1_OUT: TIM2 TI4 connected to COMP1 output + * @arg TIM2_TI4_COMP2_OUT: TIM2 TI4 connected to COMP2 output + * + * For TIM21, the parameter can have the following values: + * @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) : + * APB2_PA(1)_AF5 + * @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output + * @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output + * @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE + * @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO + * @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt + * @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC + * @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock + * @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE + * @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI + * @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT + * @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default): + * GPIOA(3)_AF0 or GPIOB(14)_AF6 + * @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output + * + * For TIM22, the parameter can have the following values: + * @arg TIM22_ETR_LSE: TIM22 ETR connected to LSE + * @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output + * @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output + * @arg TIM22_ETR_GPIO: TIM22 ETR connected to GPIO(default): + * GPIOA(4)_AF5 + * @arg TIM22_TI1_GPIO1: TIM22 TI1 connected to GPIO(default): + * GPIOC(0)_AF6 or GPIOA(5)_AF6 or + * GPIOB(4)_AF4 + * @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output + * @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output + * @arg TIM22_TI1_GPIO2: TIM22 TI1 connected to GPIO: + * GPIOA(6)_AF5 or GPIOB(4)_AF4 + * + * @retval HAL status + */ +#elif defined (STM32L011xx) || defined (STM32L021xx) + /** + * @brief Configures the remapping of the TIM2 and TIM21 inputs. + * The channel inputs (T1..T4) and the Trigger input (ETR) of the + * timers can be remaped thanks to this function. When an input is + * mapped, on a GPIO, refer yourself to the GPIO alternate functions + * for more details. + * + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Remap: specifies the TIM input remapping source. + * This parameter is a combination of the following values + * depending on TIM instance: + * + * For TIM2, the parameter can have the following values: + * @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default): + * GPIOA(0)_AF5 or GPIOA(5)_AF2 or + * GPIOA(15)_AF2 + * @arg TIM2_ETR_HSI16: TIM2 ETR connected to HS16 (HSIOUT) + * @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE + * @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output + * @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output + * @arg TIM2_TI4_GPIO : TIM2 TI4 connected to GPIO (default): + * GPIOA(3)_AF2 or GPIOB(11)_AF2 or + * GPIOB(1)_AF5 + * @arg TIM2_TI4_COMP1_OUT: TIM2 TI4 connected to COMP1 output + * @arg TIM2_TI4_COMP2_OUT: TIM2 TI4 connected to COMP2 output + * + * For TIM21, the parameter can have the following values: + * @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) : + * APB2_PA(1)_AF5 + * @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output + * @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output + * @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE + * @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO + * @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt + * @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC + * @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock + * @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE + * @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI + * @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT + * @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default): + * GPIOA(3)_AF0 or GPIOB(14)_AF6 + * @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output + * + * @retval HAL status + */ #else /** * @brief Configures the remapping of the TIM2, TIM21 and TIM22 inputs.
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_tim_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,12 +50,14 @@
* @{
*/
-/** @defgroup TIMEx TIMEx (Timer extended)
+/** @defgroup TIMEx TIMEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
-
+ /** @defgroup TIM_Exported_Types TIM Exported Types
+ * @{
+ */
/**
* @brief TIM Master configuration Structure definition
*/
@@ -66,7 +68,9 @@
This parameter can be a value of @ref TIM_Master_Slave_Mode */
}TIM_MasterConfigTypeDef;
-
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
@@ -101,12 +105,36 @@
/** @defgroup TIMEx_Remap Remaping
* @{
*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+
+#define TIM2_ETR_GPIO ((uint32_t)0x0)
+#define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2
+#define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0)
+#define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0)
+#define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1)
+#define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP
+
+#elif defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx)
+
+#define TIM2_ETR_GPIO ((uint32_t)0x0)
+#define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0)
+#define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0)
+#define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1)
+#define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP
+
+#else
#define TIM2_ETR_GPIO ((uint32_t)0x0)
#define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2
#define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0)
#define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1)
#define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP
+
+#endif
+
+
+
#define TIM2_TI4_GPIO ((uint32_t)0x0)
#define TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_0
#define TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_1
@@ -126,6 +154,7 @@
#define TIM21_TI2_GPIO ((uint32_t)0x0)
#define TIM21_TI2_COMP2_OUT TIM21_OR_TI2_RMP
+#if !defined(STM32L011xx) && !defined(STM32L021xx)
#define TIM22_ETR_LSE ((uint32_t)0x0)
#define TIM22_ETR_COMP2_OUT TIM22_OR_ETR_RMP_0
#define TIM22_ETR_COMP1_OUT TIM22_OR_ETR_RMP_1
@@ -134,6 +163,7 @@
#define TIM22_TI1_COMP2_OUT TIM22_OR_TI1_RMP_0
#define TIM22_TI1_COMP1_OUT TIM22_OR_TI1_RMP_1
#define TIM22_TI1_GPIO2 TIM22_OR_TI1_RMP
+#endif
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
|| defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
@@ -148,8 +178,7 @@
#define TIM3_ETR_HSI TIM3_OR_ETR_RMP_1
#endif /*defined (STM32L07Xxx) or defined (STM32L08Xxx) */
-
-
+
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
|| defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
@@ -174,7 +203,21 @@
((__CHANNEL__) == TIM_CHANNEL_2))) || \
((__INSTANCE__ == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2))))
+
+#elif defined (STM32L011xx) || defined (STM32L021xx)
+#define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \
+ (((__INSTANCE__ == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \
+ ((__INSTANCE__ == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))))
+
+#define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \
+ (((__INSTANCE__ == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \
+ ((__CHANNEL__) == TIM_CHANNEL_4))) || \
+ ((__INSTANCE__ == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2))))
+
#else
#define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \
@@ -229,10 +272,6 @@
/**
* @}
- */
-
-/**
- * @}
*/
/**
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tsc.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tsc.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_tsc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Touch Sensing Controller (TSC) peripheral:
* + Initialization and DeInitialization
@@ -81,7 +81,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -109,7 +109,7 @@
*/
/* Includes ------------------------------------------------------------------*/
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
#include "stm32l0xx_hal.h"
#ifdef HAL_TSC_MODULE_ENABLED
@@ -117,25 +117,30 @@
* @{
*/
-/** @defgroup TSC
+/** @addtogroup TSC
* @brief HAL TSC module driver
* @{
*/
-
+/** @addtogroup TSC_Private TSC Private
+ * @{
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+
static uint32_t TSC_extract_groups(uint32_t iomask);
/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup TSC_Private_Functions
+/**
+ * @}
+ */
+/** @addtogroup TSC_Exported_Functions TSC Exported Functions
* @{
*/
-/** @defgroup TSC_Group1 Initialization/de-initialization functions
+/** @addtogroup HAL_TSC_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
@@ -176,7 +181,13 @@
assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode));
assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
-
+
+ if(htsc->State == HAL_TSC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htsc->Lock = HAL_UNLOCKED;
+ }
+
/* Initialize the TSC state */
htsc->State = HAL_TSC_STATE_BUSY;
@@ -196,7 +207,6 @@
htsc->Init.SpreadSpectrumPrescaler |
htsc->Init.PulseGeneratorPrescaler |
htsc->Init.MaxCountValue |
- htsc->Init.IODefaultMode |
htsc->Init.SynchroPinPolarity |
htsc->Init.AcquisitionMode);
@@ -222,7 +232,7 @@
htsc->Instance->IER &= (uint32_t)(~(TSC_IT_EOA | TSC_IT_MCE));
/* Clear flags */
- htsc->Instance->ICR |= (TSC_FLAG_EOA | TSC_FLAG_MCE);
+ htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE);
/*--------------------------------------------------------------------------*/
@@ -273,6 +283,9 @@
*/
__weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htsc);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TSC_MspInit could be implemented in the user file.
*/
@@ -286,6 +299,9 @@
*/
__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htsc);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TSC_MspDeInit could be implemented in the user file.
*/
@@ -295,12 +311,12 @@
* @}
*/
-/** @defgroup HAL_TSC_Group2 IO operation functions
+/** @addtogroup HAL_TSC_Exported_Functions_Group2
* @brief IO operation functions
*
@verbatim
===============================================================================
- ##### I/O Operation functions #####
+ ##### IO Operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Start acquisition in polling mode.
@@ -336,8 +352,15 @@
/* Clear flags */
__HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
- /* Stop discharging the IOs */
- __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+ /* Set touch sensing IOs not acquired to the specified IODefaultMode */
+ if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
+ {
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+ }
+ else
+ {
+ __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+ }
/* Launch the acquisition */
__HAL_TSC_START_ACQ(htsc);
@@ -383,8 +406,15 @@
/* Clear flags */
__HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
- /* Stop discharging the IOs */
- __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+ /* Set touch sensing IOs not acquired to the specified IODefaultMode */
+ if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
+ {
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+ }
+ else
+ {
+ __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+ }
/* Launch the acquisition */
__HAL_TSC_START_ACQ(htsc);
@@ -413,6 +443,9 @@
/* Stop the acquisition */
__HAL_TSC_STOP_ACQ(htsc);
+ /* Set touch sensing IOs in low power mode (output push-pull) */
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+
/* Clear flags */
__HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
@@ -443,6 +476,9 @@
/* Stop the acquisition */
__HAL_TSC_STOP_ACQ(htsc);
+ /* Set touch sensing IOs in low power mode (output push-pull) */
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+
/* Disable interrupts */
__HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
@@ -470,7 +506,7 @@
{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
- assert_param(IS_GROUP_INDEX(gx_index));
+ assert_param(IS_TSC_GROUP_INDEX(gx_index));
/* Return the group status */
return(__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index));
@@ -487,7 +523,7 @@
{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
- assert_param(IS_GROUP_INDEX(gx_index));
+ assert_param(IS_TSC_GROUP_INDEX(gx_index));
/* Return the group acquisition counter */
return htsc->Instance->IOGXCR[gx_index];
@@ -497,7 +533,7 @@
* @}
*/
-/** @defgroup HAL_TSC_Group3 Peripheral Control functions
+/** @addtogroup HAL_TSC_Exported_Functions_Group3
* @brief Peripheral Control functions
*
@verbatim
@@ -583,7 +619,7 @@
* @}
*/
-/** @defgroup HAL_TSC_Group4 State functions
+/** @addtogroup HAL_TSC_Exported_Functions_Group4
* @brief State functions
*
@verbatim
@@ -700,10 +736,6 @@
}
/**
- * @}
- */
-
-/**
* @brief Acquisition completed callback in non blocking mode
* @param htsc: pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
@@ -711,6 +743,9 @@
*/
__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htsc);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TSC_ConvCpltCallback could be implemented in the user file.
*/
@@ -724,12 +759,27 @@
*/
__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htsc);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TSC_ErrorCallback could be implemented in the user file.
*/
}
/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_Private
+ * @{
+ */
+
+/**
* @brief Utility function used to set the acquired groups mask
* @param iomask: Channels IOs mask
* @retval Acquired groups mask
@@ -763,7 +813,7 @@
* @}
*/
#endif /* HAL_TSC_MODULE_ENABLED */
-#endif /* #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
+#endif /* #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tsc.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tsc.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32l0xx_hal_tsc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief This file contains all the functions prototypes for the TSC firmware
* library.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -36,7 +36,7 @@
******************************************************************************
*/
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L0xx_TSC_H
#define __STM32L0xx_TSC_H
@@ -52,10 +52,13 @@
* @{
*/
-/** @addtogroup TSC
+/** @defgroup TSC TSC
* @{
*/
+ /** @defgroup TSC_Exported_Types TSC Exported Types
+ * @{
+ */
/* Exported types ------------------------------------------------------------*/
/**
@@ -120,13 +123,17 @@
HAL_LockTypeDef Lock; /*!< Lock feature */
} TSC_HandleTypeDef;
+
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup TSC_Exported_Constants
+/** @defgroup TSC_Exported_Constants TSC Exported Constants
* @{
*/
-#define IS_TSC_ALL_INSTANCE(PERIPH) ((PERIPH) == TSC)
#define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28))
#define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28))
@@ -144,22 +151,6 @@
#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28))
#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28))
#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28))
-#define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
- ((VAL) == TSC_CTPH_2CYCLES) || \
- ((VAL) == TSC_CTPH_3CYCLES) || \
- ((VAL) == TSC_CTPH_4CYCLES) || \
- ((VAL) == TSC_CTPH_5CYCLES) || \
- ((VAL) == TSC_CTPH_6CYCLES) || \
- ((VAL) == TSC_CTPH_7CYCLES) || \
- ((VAL) == TSC_CTPH_8CYCLES) || \
- ((VAL) == TSC_CTPH_9CYCLES) || \
- ((VAL) == TSC_CTPH_10CYCLES) || \
- ((VAL) == TSC_CTPH_11CYCLES) || \
- ((VAL) == TSC_CTPH_12CYCLES) || \
- ((VAL) == TSC_CTPH_13CYCLES) || \
- ((VAL) == TSC_CTPH_14CYCLES) || \
- ((VAL) == TSC_CTPH_15CYCLES) || \
- ((VAL) == TSC_CTPH_16CYCLES))
#define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24))
#define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24))
@@ -177,30 +168,9 @@
#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24))
#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24))
#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24))
-#define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
- ((VAL) == TSC_CTPL_2CYCLES) || \
- ((VAL) == TSC_CTPL_3CYCLES) || \
- ((VAL) == TSC_CTPL_4CYCLES) || \
- ((VAL) == TSC_CTPL_5CYCLES) || \
- ((VAL) == TSC_CTPL_6CYCLES) || \
- ((VAL) == TSC_CTPL_7CYCLES) || \
- ((VAL) == TSC_CTPL_8CYCLES) || \
- ((VAL) == TSC_CTPL_9CYCLES) || \
- ((VAL) == TSC_CTPL_10CYCLES) || \
- ((VAL) == TSC_CTPL_11CYCLES) || \
- ((VAL) == TSC_CTPL_12CYCLES) || \
- ((VAL) == TSC_CTPL_13CYCLES) || \
- ((VAL) == TSC_CTPL_14CYCLES) || \
- ((VAL) == TSC_CTPL_15CYCLES) || \
- ((VAL) == TSC_CTPL_16CYCLES))
-
-#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
-
-#define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128)))
#define TSC_SS_PRESC_DIV1 ((uint32_t)0)
#define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)
-#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
#define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12))
#define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12))
@@ -210,15 +180,6 @@
#define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12))
#define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12))
#define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12))
-#define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
- ((VAL) == TSC_PG_PRESC_DIV2) || \
- ((VAL) == TSC_PG_PRESC_DIV4) || \
- ((VAL) == TSC_PG_PRESC_DIV8) || \
- ((VAL) == TSC_PG_PRESC_DIV16) || \
- ((VAL) == TSC_PG_PRESC_DIV32) || \
- ((VAL) == TSC_PG_PRESC_DIV64) || \
- ((VAL) == TSC_PG_PRESC_DIV128))
-
#define TSC_MCV_255 ((uint32_t)(0 << 5))
#define TSC_MCV_511 ((uint32_t)(1 << 5))
#define TSC_MCV_1023 ((uint32_t)(2 << 5))
@@ -226,46 +187,31 @@
#define TSC_MCV_4095 ((uint32_t)(4 << 5))
#define TSC_MCV_8191 ((uint32_t)(5 << 5))
#define TSC_MCV_16383 ((uint32_t)(6 << 5))
-#define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
- ((VAL) == TSC_MCV_511) || \
- ((VAL) == TSC_MCV_1023) || \
- ((VAL) == TSC_MCV_2047) || \
- ((VAL) == TSC_MCV_4095) || \
- ((VAL) == TSC_MCV_8191) || \
- ((VAL) == TSC_MCV_16383))
#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0)
#define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)
-#define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
#define TSC_SYNC_POLARITY_FALLING ((uint32_t)0)
#define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
-#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POL_FALL) || ((VAL) == TSC_SYNC_POL_RISE_HIGH))
#define TSC_ACQ_MODE_NORMAL ((uint32_t)0)
#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
-#define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
#define TSC_IOMODE_UNUSED ((uint32_t)0)
#define TSC_IOMODE_CHANNEL ((uint32_t)1)
#define TSC_IOMODE_SHIELD ((uint32_t)2)
#define TSC_IOMODE_SAMPLING ((uint32_t)3)
-#define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
- ((VAL) == TSC_IOMODE_CHANNEL) || \
- ((VAL) == TSC_IOMODE_SHIELD) || \
- ((VAL) == TSC_IOMODE_SAMPLING))
-/** @defgroup TSC_interrupts_definition
+/** @defgroup TSC_interrupts_definition TSC Interrupts Definition
* @{
*/
#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
-#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
/**
* @}
*/
-/** @defgroup TSC_flags_definition
+/** @defgroup TSC_flags_definition TSC Flags Definition
* @{
*/
#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
@@ -294,7 +240,6 @@
#define TSC_GROUP6_IDX ((uint32_t)5)
#define TSC_GROUP7_IDX ((uint32_t)6)
#define TSC_GROUP8_IDX ((uint32_t)7)
-#define IS_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS)))
#define TSC_GROUP1_IO1 ((uint32_t)0x00000001)
#define TSC_GROUP1_IO2 ((uint32_t)0x00000002)
@@ -350,7 +295,11 @@
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup TSC_Exported_Macros TSC Exported Macros
+ * @{
+ */
/** @brief Reset TSC handle state
* @param __HANDLE__: TSC handle
@@ -541,29 +490,133 @@
#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup TSC_Private_Macros TSC Private Macros
+ * @{
+ */
+#define IS_TSC_ALL_INSTANCE(PERIPH) ((PERIPH) == TSC)
+
+#define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
+ ((VAL) == TSC_CTPH_2CYCLES) || \
+ ((VAL) == TSC_CTPH_3CYCLES) || \
+ ((VAL) == TSC_CTPH_4CYCLES) || \
+ ((VAL) == TSC_CTPH_5CYCLES) || \
+ ((VAL) == TSC_CTPH_6CYCLES) || \
+ ((VAL) == TSC_CTPH_7CYCLES) || \
+ ((VAL) == TSC_CTPH_8CYCLES) || \
+ ((VAL) == TSC_CTPH_9CYCLES) || \
+ ((VAL) == TSC_CTPH_10CYCLES) || \
+ ((VAL) == TSC_CTPH_11CYCLES) || \
+ ((VAL) == TSC_CTPH_12CYCLES) || \
+ ((VAL) == TSC_CTPH_13CYCLES) || \
+ ((VAL) == TSC_CTPH_14CYCLES) || \
+ ((VAL) == TSC_CTPH_15CYCLES) || \
+ ((VAL) == TSC_CTPH_16CYCLES))
+#define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
+ ((VAL) == TSC_CTPL_2CYCLES) || \
+ ((VAL) == TSC_CTPL_3CYCLES) || \
+ ((VAL) == TSC_CTPL_4CYCLES) || \
+ ((VAL) == TSC_CTPL_5CYCLES) || \
+ ((VAL) == TSC_CTPL_6CYCLES) || \
+ ((VAL) == TSC_CTPL_7CYCLES) || \
+ ((VAL) == TSC_CTPL_8CYCLES) || \
+ ((VAL) == TSC_CTPL_9CYCLES) || \
+ ((VAL) == TSC_CTPL_10CYCLES) || \
+ ((VAL) == TSC_CTPL_11CYCLES) || \
+ ((VAL) == TSC_CTPL_12CYCLES) || \
+ ((VAL) == TSC_CTPL_13CYCLES) || \
+ ((VAL) == TSC_CTPL_14CYCLES) || \
+ ((VAL) == TSC_CTPL_15CYCLES) || \
+ ((VAL) == TSC_CTPL_16CYCLES))
+
+#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
+
+#define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128)))
+#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
+#define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
+ ((VAL) == TSC_PG_PRESC_DIV2) || \
+ ((VAL) == TSC_PG_PRESC_DIV4) || \
+ ((VAL) == TSC_PG_PRESC_DIV8) || \
+ ((VAL) == TSC_PG_PRESC_DIV16) || \
+ ((VAL) == TSC_PG_PRESC_DIV32) || \
+ ((VAL) == TSC_PG_PRESC_DIV64) || \
+ ((VAL) == TSC_PG_PRESC_DIV128))
+
+#define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
+ ((VAL) == TSC_MCV_511) || \
+ ((VAL) == TSC_MCV_1023) || \
+ ((VAL) == TSC_MCV_2047) || \
+ ((VAL) == TSC_MCV_4095) || \
+ ((VAL) == TSC_MCV_8191) || \
+ ((VAL) == TSC_MCV_16383))
+#define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
+#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
+#define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
+#define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
+ ((VAL) == TSC_IOMODE_CHANNEL) || \
+ ((VAL) == TSC_IOMODE_SHIELD) || \
+ ((VAL) == TSC_IOMODE_SAMPLING))
+#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
+
+#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS)))
+
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
+/** @defgroup TSC_Exported_Functions TSC Exported Functions
+ * @{
+ */
+
+/** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
+/**
+ * @}
+ */
+/** @defgroup HAL_TSC_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
+/**
+ * @}
+ */
+/** @defgroup HAL_TSC_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
+/**
+ * @}
+ */
+/** @defgroup HAL_TSC_Exported_Functions_Group4 State callback and error Functions
+ * @{
+ */
/* Peripheral State and Error functions ***************************************/
HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
-HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
/* Callback functions *********************************************************/
@@ -572,6 +625,24 @@
/**
* @}
+ */
+
+/**
+ * @}
+ */
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup TSC_Private TSC Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
+/**
+ * @}
*/
/**
@@ -583,7 +654,7 @@
#endif
#endif /*__STM32L0xx_TSC_H */
-#endif /* #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
+#endif /* #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_uart.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief UART HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -126,7 +126,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -160,12 +160,17 @@
* @{
*/
+#ifdef HAL_UART_MODULE_ENABLED
+
+
/** @addtogroup UART
* @brief UART module driver
* @{
*/
-#ifdef HAL_UART_MODULE_ENABLED
-
+
+/** @addtogroup UART_Private
+ * @{
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define UART_TIMEOUT_VALUE ((uint32_t) 22000)
@@ -183,7 +188,9 @@
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
-
+/**
+ * @}
+ */
/* Private functions ---------------------------------------------------------*/
@@ -272,7 +279,10 @@
}
if(huart->State == HAL_UART_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, CORTEX */
HAL_UART_MspInit(huart);
}
@@ -539,6 +549,9 @@
*/
__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_MspInit can be implemented in the user file
*/
@@ -551,6 +564,9 @@
*/
__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_MspDeInit can be implemented in the user file
*/
@@ -811,9 +827,6 @@
/* Enable the UART Parity Error Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_PE);
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
-
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -1134,7 +1147,7 @@
if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET))
{
- __HAL_UART_CLEAR_PEFLAG(huart);
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
huart->ErrorCode |= HAL_UART_ERROR_PE;
/* Set the UART state ready to be able to start again the process */
@@ -1144,7 +1157,7 @@
/* UART frame error interrupt occured --------------------------------------*/
if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
{
- __HAL_UART_CLEAR_FEFLAG(huart);
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
huart->ErrorCode |= HAL_UART_ERROR_FE;
/* Set the UART state ready to be able to start again the process */
@@ -1154,7 +1167,7 @@
/* UART noise error interrupt occured --------------------------------------*/
if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
{
- __HAL_UART_CLEAR_NEFLAG(huart);
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
huart->ErrorCode |= HAL_UART_ERROR_NE;
/* Set the UART state ready to be able to start again the process */
@@ -1164,7 +1177,7 @@
/* UART Over-Run interrupt occured -----------------------------------------*/
if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
{
- __HAL_UART_CLEAR_OREFLAG(huart);
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
huart->ErrorCode |= HAL_UART_ERROR_ORE;
/* Set the UART state ready to be able to start again the process */
@@ -1203,11 +1216,6 @@
{
UART_EndTransmit_IT(huart);
}
-
- if(huart->ErrorCode != HAL_UART_ERROR_NONE)
- {
- HAL_UART_ErrorCallback(huart);
- }
}
/**
@@ -1217,6 +1225,9 @@
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_UART_TxCpltCallback could be implemented in the user file
*/
@@ -1229,6 +1240,9 @@
*/
__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_UART_TxCpltCallback could be implemented in the user file
*/
@@ -1241,6 +1255,9 @@
*/
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_UART_TxCpltCallback could be implemented in the user file
*/
@@ -1253,6 +1270,9 @@
*/
__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_UART_TxCpltCallback could be implemented in the user file
*/
@@ -1265,6 +1285,9 @@
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback can be implemented in the user file
*/
@@ -1404,7 +1427,7 @@
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
{
/* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
/* Process Locked */
__HAL_LOCK(huart);
@@ -1447,10 +1470,17 @@
* @}
*/
+/**
+ * @}
+ */
+
/***************************************************************
* Private functions...
*
***************************************************************/
+/** @addtogroup UART_Private
+ * @{
+ */
/**
* @brief DMA UART transmit process complete callback
* @param hdma: DMA handle
@@ -1459,14 +1489,24 @@
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- huart->TxXferCount = 0;
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ huart->TxXferCount = 0;
- /* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the UART CR3 register */
- huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the UART CR3 register */
+ huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
- /* Enable the UART Transmit Complete Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+ /* Enable the UART Transmit Complete Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+ }
+ /* DMA Circular mode */
+ else
+ {
+ HAL_UART_TxCpltCallback(huart);
+ }
}
@@ -1606,9 +1646,6 @@
}
else
{
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
huart->State = HAL_UART_STATE_READY;
}
@@ -1689,13 +1726,21 @@
uint16_t usartdiv = 0x0000;
/* Check the parameters */
- assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
- assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ if(UART_INSTANCE_LOWPOWER(huart))
+ {
+ assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
+ }
+ else
+ {
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+ }
+
assert_param(IS_UART_PARITY(huart->Init.Parity));
assert_param(IS_UART_MODE(huart->Init.Mode));
assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
- assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
/*-------------------------- USART CR1 Configuration -----------------------*/
@@ -1719,14 +1764,18 @@
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling */
- tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
+ tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+ if (!(UART_INSTANCE_LOWPOWER(huart)))
+ {
+ tmpreg |= huart->Init.OneBitSampling;
+ }
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
-
+
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
/* Check LPUART instace */
- if(huart->Instance == LPUART1)
+ if(UART_INSTANCE_LOWPOWER(huart))
{
switch (clocksource)
{
@@ -1734,7 +1783,14 @@
huart->Instance->BRR = (uint32_t)(__DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_HSI:
- huart->Instance->BRR = (uint32_t)(__DIV_LPUART(HSI_VALUE, huart->Init.BaudRate));
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0)
+ {
+ huart->Instance->BRR = (uint32_t)(__DIV_LPUART((HSI_VALUE >> 2), huart->Init.BaudRate));
+ }
+ else
+ {
+ huart->Instance->BRR = (uint32_t)(__DIV_LPUART(HSI_VALUE, huart->Init.BaudRate));
+ }
break;
case UART_CLOCKSOURCE_SYSCLK:
huart->Instance->BRR = (uint32_t)(__DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
@@ -1758,10 +1814,17 @@
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint32_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0)
+ {
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING8((HSI_VALUE >> 2), huart->Init.BaudRate));
+ }
+ else
+ {
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
+ }
break;
case UART_CLOCKSOURCE_SYSCLK:
- huart->Instance->BRR = (uint32_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
@@ -1785,7 +1848,14 @@
huart->Instance->BRR = (uint32_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_HSI:
- huart->Instance->BRR = (uint32_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0)
+ {
+ huart->Instance->BRR = (uint32_t)(UART_DIV_SAMPLING16((HSI_VALUE >> 2), huart->Init.BaudRate));
+ }
+ else
+ {
+ huart->Instance->BRR = (uint32_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
+ }
break;
case UART_CLOCKSOURCE_SYSCLK:
huart->Instance->BRR = (uint32_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
@@ -1980,11 +2050,12 @@
* @}
*/
-#endif /* HAL_UART_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_UART_MODULE_ENABLED */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_uart.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -263,10 +263,16 @@
/** @defgroup UART_Stop_Bits UART stop bit definition
* @{
*/
-#define UART_STOPBITS_1 ((uint32_t)0x0000)
-#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
-#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
+#define UART_STOPBITS_1 ((uint32_t)0x0000) /*!< USART frame with 1 stop bit */
+#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
+#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
+ ((STOPBITS) == UART_STOPBITS_1_5) || \
((STOPBITS) == UART_STOPBITS_2))
+
+#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
+ ((__STOPBITS__) == UART_STOPBITS_2))
+
/**
* @}
*/
@@ -418,28 +424,28 @@
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
-#define UART_FLAG_REACK ((uint32_t)0x00400000)
-#define UART_FLAG_TEACK ((uint32_t)0x00200000)
-#define UART_FLAG_WUF ((uint32_t)0x00100000)
-#define UART_FLAG_RWU ((uint32_t)0x00080000)
-#define UART_FLAG_SBKF ((uint32_t)0x00040000
-#define UART_FLAG_CMF ((uint32_t)0x00020000)
-#define UART_FLAG_BUSY ((uint32_t)0x00010000)
-#define UART_FLAG_ABRF ((uint32_t)0x00008000)
-#define UART_FLAG_ABRE ((uint32_t)0x00004000)
-#define UART_FLAG_EOBF ((uint32_t)0x00001000)
-#define UART_FLAG_RTOF ((uint32_t)0x00000800)
-#define UART_FLAG_CTS ((uint32_t)0x00000400)
-#define UART_FLAG_CTSIF ((uint32_t)0x00000200)
-#define UART_FLAG_LBDF ((uint32_t)0x00000100)
-#define UART_FLAG_TXE ((uint32_t)0x00000080)
-#define UART_FLAG_TC ((uint32_t)0x00000040)
-#define UART_FLAG_RXNE ((uint32_t)0x00000020)
-#define UART_FLAG_IDLE ((uint32_t)0x00000010)
-#define UART_FLAG_ORE ((uint32_t)0x00000008)
-#define UART_FLAG_NE ((uint32_t)0x00000004)
-#define UART_FLAG_FE ((uint32_t)0x00000002)
-#define UART_FLAG_PE ((uint32_t)0x00000001)
+#define UART_FLAG_REACK USART_ISR_REACK /*!< Receive Enable Acknowledge Flag */
+#define UART_FLAG_TEACK USART_ISR_TEACK /*!< Transmit Enable Acknowledge Flag */
+#define UART_FLAG_WUF USART_ISR_WUF /*!< Wake Up from stop mode Flag */
+#define UART_FLAG_RWU USART_ISR_RWU /*!< Receive Wake Up from mute mode Flag */
+#define UART_FLAG_SBKF USART_ISR_SBKF /*!< Send Break Flag */
+#define UART_FLAG_CMF USART_ISR_CMF /*!< Character Match Flag */
+#define UART_FLAG_BUSY USART_ISR_BUSY /*!< Busy Flag */
+#define UART_FLAG_ABRF USART_ISR_ABRF /*!< Auto-Baud Rate Flag */
+#define UART_FLAG_ABRE USART_ISR_ABRE /*!< Auto-Baud Rate Error */
+#define UART_FLAG_EOBF USART_ISR_EOBF /*!< End Of Block Flag */
+#define UART_FLAG_RTOF USART_ISR_RTOF /*!< Receiver Time Out */
+#define UART_FLAG_CTS USART_ISR_CTS /*!< CTS flag */
+#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
+#define UART_FLAG_LBDF USART_ISR_LBDF /*!< LIN Break Detection Flag */
+#define UART_FLAG_TXE USART_ISR_TXE /*!< Transmit Data Register Empty */
+#define UART_FLAG_TC USART_ISR_TC /*!< Transmission Complete */
+#define UART_FLAG_RXNE USART_ISR_RXNE /*!< Read Data Register Not Empty */
+#define UART_FLAG_IDLE USART_ISR_IDLE /*!< IDLE line detected */
+#define UART_FLAG_ORE USART_ISR_ORE /*!< OverRun Error */
+#define UART_FLAG_NE USART_ISR_NE /*!< Noise detected Flag */
+#define UART_FLAG_FE USART_ISR_FE /*!< Framing Error */
+#define UART_FLAG_PE USART_ISR_PE /*!< Parity Error */
/**
* @}
*/
@@ -754,7 +760,8 @@
* @arg UART_CLEAR_WUF
* @retval None
*/
-#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ~(__FLAG__))
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
/** @brief Clear the UART PE pending flag.
* @param __HANDLE__: specifies the UART Handle.
@@ -1037,11 +1044,16 @@
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
} while(0)
-/** @brief macros to enables or disables the UART's one bit sampling method
+/** @brief macros to enable the UART's one bit sampling method
* @param __HANDLE__: specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ONE_BIT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief macros to disable the UART's one bit sampling method
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
#define __HAL_UART_ONE_BIT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
@@ -1050,8 +1062,8 @@
* @param _BAUD_: Baud rate set by the user
* @retval Division result
*/
-#define __DIV_LPUART(_PCLK_, _BAUD_) (((_PCLK_)*256)/((_BAUD_)))
-
+#define __DIV_LPUART(_PCLK_, _BAUD_) ((uint32_t)(((((uint64_t)_PCLK_)*256.0))/(((uint64_t)_BAUD_))))
+
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode
* @param _PCLK_: UART clock
* @param _BAUD_: Baud rate set by the user
@@ -1066,6 +1078,12 @@
*/
#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_))/((_BAUD_)))
+/** @brief Check whether or not UART instance is Low Power UART.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
+ */
+#define UART_INSTANCE_LOWPOWER(__HANDLE__) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET )
+
/** @brief Check UART Baud rate
* @param BAUDRATE: Baudrate specified by the user
* The maximum Baud Rate is derived from the maximum clock on L0 (i.e. 32 MHz)
@@ -1164,15 +1182,32 @@
/**
* @}
*/
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Private
+ * @{
+ */
void UART_SetConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
-
/**
* @}
*/
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup UART_Private UART Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart_ex.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart_ex.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_uart_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Extended UART HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -30,7 +30,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -64,13 +64,16 @@
* @{
*/
+#ifdef HAL_UART_MODULE_ENABLED
+
/** @addtogroup UARTEx
* @brief UARTEx module driver
* @{
*/
-#ifdef HAL_UART_MODULE_ENABLED
-
+/** @addtogroup UARTEx_Private
+ * @{
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define UART_REACK_TIMEOUT ((uint32_t) 1000)
@@ -80,6 +83,10 @@
static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
+
/** @addtogroup UARTEx_Exported_Functions
* @{
*/
@@ -388,9 +395,31 @@
}
/**
+ * @brief UART wakeup from Stop mode callback
+ * @param huart: uart handle
+ * @retval None
+ */
+ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_WakeupCallback can be implemented in the user file
+ */
+}
+
+/**
* @}
*/
+ /**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Private
+ * @{
+ */
/**
* @brief Initializes the UART wake-up from stop mode parameters when triggered by address detection.
* @param huart: uart handle
@@ -416,30 +445,20 @@
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
}
-/**
- * @brief UART wakeup from Stop mode callback
- * @param huart: uart handle
- * @retval None
- */
- __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
-{
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_WakeupCallback can be implemented in the user file
- */
-}
/**
* @}
*/
-#endif /* HAL_UART_MODULE_ENABLED */
-/**
- * @}
- */
-
/**
* @}
*/
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_uart_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of UART HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,7 +50,7 @@
* @{
*/
-/** @defgroup UARTEx UARTEx Extended HAL module driver
+/** @defgroup UARTEx UARTEx
* @{
*/
@@ -96,9 +96,9 @@
/** @defgroup UARTEx_Word_Length Word length definition
* @{
*/
-#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
+#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define UART_WORDLENGTH_8B ((uint32_t)0x0000)
-#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_7B) || \
((LENGTH) == UART_WORDLENGTH_8B) || \
((LENGTH) == UART_WORDLENGTH_9B))
@@ -159,7 +159,7 @@
* @param __CLOCKSOURCE__ : output variable
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
-#if defined (STM32L031xx) || defined (STM32L041xx)
+#if defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART2) \
@@ -204,7 +204,7 @@
} \
} while(0)
-#else /* (STM32L031xx) || defined (STM32L041xx) */
+#else /* (STM32L031xx) || defined (STM32L041xx) || (STM32L011xx) || defined (STM32L021xx) */
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
@@ -269,7 +269,7 @@
} \
} \
} while(0)
-#endif /* (STM32L031xx) || (STM32L041xx) */
+#endif /* (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || defined (STM32L021xx) */
/** @brief Reports the UART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
@@ -348,6 +348,7 @@
/* Peripheral State functions ************************************************/
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+
/**
* @}
*/
@@ -356,9 +357,15 @@
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup UARTEx_Private UARTEx Private
+ * @{
+ */
/**
* @}
*/
+/**************************************************************/
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_usart.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief USART HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -53,7 +53,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -87,11 +87,17 @@
* @{
*/
+#ifdef HAL_USART_MODULE_ENABLED
+
/** @addtogroup USART
* @brief USART Synchronous module driver
* @{
*/
-#ifdef HAL_USART_MODULE_ENABLED
+
+/** @addtogroup USART_Private
+ * @{
+ */
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define DUMMY_DATA ((uint16_t) 0xFFFF)
@@ -112,13 +118,16 @@
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void USART_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static void USART_SetConfig (USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_SetConfig (USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
-/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
/** @addtogroup USART_Exported_Functions
@@ -186,6 +195,9 @@
if(husart->State == HAL_USART_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ husart->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, CORTEX */
HAL_USART_MspInit(husart);
}
@@ -196,7 +208,10 @@
__HAL_USART_DISABLE(husart);
/* Set the Usart Communication parameters */
- USART_SetConfig(husart);
+ if (USART_SetConfig(husart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
@@ -252,6 +267,9 @@
*/
__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_USART_MspInit could be implenetd in the user file
*/
@@ -264,6 +282,9 @@
*/
__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_USART_MspDeInit could be implenetd in the user file
*/
@@ -1097,6 +1118,9 @@
*/
__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_USART_TxCpltCallback could be implemented in the user file
*/
@@ -1109,6 +1133,9 @@
*/
__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_USART_TxCpltCallback could be implemented in the user file
*/
@@ -1121,6 +1148,9 @@
*/
__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_USART_TxCpltCallback could be implemented in the user file
*/
@@ -1133,6 +1163,9 @@
*/
__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_USART_TxCpltCallback could be implemented in the user file
*/
@@ -1145,6 +1178,9 @@
*/
__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_USART_TxCpltCallback could be implemented in the user file
*/
@@ -1157,6 +1193,9 @@
*/
__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_USART_ErrorCallback could be implemented in the user file
*/
@@ -1210,6 +1249,13 @@
*/
/**
+ * @}
+ */
+
+/** @addtogroup USART_Private
+ * @{
+ */
+/**
* @brief This function handles USART Communication Timeout.
* @param husart: USART handle
* @param Flag: specifies the USART flag to check.
@@ -1285,23 +1331,29 @@
{
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- husart->TxXferCount = 0;
-
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
{
- /* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the USART CR3 register */
- husart->Instance->CR3 &= ~(USART_CR3_DMAT);
+ husart->TxXferCount = 0;
- /* Enable the USART Transmit Complete Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the USART CR3 register */
+ husart->Instance->CR3 &= ~(USART_CR3_DMAT);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ }
}
- /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/
+ /* DMA Circular mode */
else
{
- husart->State= HAL_USART_STATE_BUSY_RX;
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
HAL_USART_TxCpltCallback(husart);
- }
+ }
+ }
}
/**
@@ -1612,12 +1664,16 @@
/**
* @brief Configure the USART peripheral
* @param husart: USART handle
- * @retval None
+ * @retval HAL status
*/
-static void USART_SetConfig(USART_HandleTypeDef *husart)
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
{
- uint32_t tmpreg = 0x0;
- uint32_t clocksource = 0x0;
+ uint32_t tmpreg = 0x0;
+ uint32_t clocksource = 0x0;
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint16_t brrtemp = 0x0000;
+ uint16_t usartdiv = 0x0000;
+
/* Check the parameters */
assert_param(IS_USART_INSTANCE(husart->Instance));
@@ -1659,24 +1715,32 @@
USART_GETCLOCKSOURCE(husart, clocksource);
switch (clocksource)
{
- case USART_CLOCKSOURCE_PCLK1:
- husart->Instance->BRR = (uint16_t)((2 * HAL_RCC_GetPCLK1Freq())/ husart->Init.BaudRate);
- break;
- case USART_CLOCKSOURCE_PCLK2:
- husart->Instance->BRR = (uint16_t)((2 * HAL_RCC_GetPCLK2Freq()) / husart->Init.BaudRate);
- break;
- case USART_CLOCKSOURCE_HSI:
- husart->Instance->BRR = (uint16_t)((2 * HSI_VALUE) / husart->Init.BaudRate);
- break;
- case USART_CLOCKSOURCE_SYSCLK:
- husart->Instance->BRR = (uint16_t)(( 2 * HAL_RCC_GetSysClockFreq()) / husart->Init.BaudRate);
- break;
- case USART_CLOCKSOURCE_LSE:
- husart->Instance->BRR = (uint16_t)((2 * LSE_VALUE) / husart->Init.BaudRate);
- break;
- default:
- break;
- }
+ case USART_CLOCKSOURCE_PCLK1:
+ usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK1Freq()) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_PCLK2:
+ usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK2Freq()) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_HSI:
+ usartdiv = (uint16_t)((2*HSI_VALUE) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_SYSCLK:
+ usartdiv = (uint16_t)((2*HAL_RCC_GetSysClockFreq()) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_LSE:
+ usartdiv = (uint16_t)((2*LSE_VALUE) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ brrtemp = usartdiv & 0xFFF0;
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
+ husart->Instance->BRR = brrtemp;
+
+ return ret;
}
/**
@@ -1719,11 +1783,7 @@
return HAL_OK;
}
-/**
- * @}
- */
-#endif /* HAL_USART_MODULE_ENABLED */
/**
* @}
*/
@@ -1732,5 +1792,11 @@
* @}
*/
+#endif /* HAL_USART_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_usart.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -156,11 +156,12 @@
*/
typedef enum
{
- USART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
- USART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
- USART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
- USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
- USART_CLOCKSOURCE_LSE = 0x08 /*!< LSE clock source */
+ USART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
+ USART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
+ USART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
+ USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
+ USART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
+ USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */
}USART_ClockSourceTypeDef;
/**
* @}
@@ -219,11 +220,9 @@
* @{
*/
#define USART_STOPBITS_1 ((uint32_t)0x0000)
-#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
- ((STOPBITS) == USART_STOPBITS_0_5) || \
((STOPBITS) == USART_STOPBITS_1_5) || \
((STOPBITS) == USART_STOPBITS_2))
/**
@@ -304,20 +303,20 @@
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
-#define USART_FLAG_REACK ((uint32_t)0x00400000)
-#define USART_FLAG_TEACK ((uint32_t)0x00200000)
-#define USART_FLAG_BUSY ((uint32_t)0x00010000)
-#define USART_FLAG_CTS ((uint32_t)0x00000400)
-#define USART_FLAG_CTSIF ((uint32_t)0x00000200)
-#define USART_FLAG_LBDF ((uint32_t)0x00000100)
-#define USART_FLAG_TXE ((uint32_t)0x00000080)
-#define USART_FLAG_TC ((uint32_t)0x00000040)
-#define USART_FLAG_RXNE ((uint32_t)0x00000020)
-#define USART_FLAG_IDLE ((uint32_t)0x00000010)
-#define USART_FLAG_ORE ((uint32_t)0x00000008)
-#define USART_FLAG_NE ((uint32_t)0x00000004)
-#define USART_FLAG_FE ((uint32_t)0x00000002)
-#define USART_FLAG_PE ((uint32_t)0x00000001)
+#define USART_FLAG_REACK USART_ISR_REACK /*!< Receive Enable Acknowledge Flag */
+#define USART_FLAG_TEACK USART_ISR_TEACK /*!< Transmit Enable Acknowledge Flag */
+#define USART_FLAG_BUSY USART_ISR_BUSY /*!< Busy Flag */
+#define USART_FLAG_CTS USART_ISR_CTS /*!< CTS flag */
+#define USART_FLAG_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
+#define USART_FLAG_LBDF USART_ISR_LBDF /*!< LIN Break Detection Flag */
+#define USART_FLAG_TXE USART_ISR_TXE /*!< Transmit Data Register Empty */
+#define USART_FLAG_TC USART_ISR_TC /*!< Transmission Complete */
+#define USART_FLAG_RXNE USART_ISR_RXNE /*!< Read Data Register Not Empty */
+#define USART_FLAG_IDLE USART_ISR_IDLE /*!< IDLE line detected */
+#define USART_FLAG_ORE USART_ISR_ORE /*!< OverRun Error */
+#define USART_FLAG_NE USART_ISR_NE /*!< Noise detected Flag */
+#define USART_FLAG_FE USART_ISR_FE /*!< Framing Error */
+#define USART_FLAG_PE USART_ISR_PE /*!< Parity Error */
/**
* @}
*/
@@ -446,7 +445,7 @@
* @arg USART_CLEAR_WUF
* @retval None
*/
-#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ~(__FLAG__))
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** @brief Clear the USART PE pending flag.
* @param __HANDLE__: specifies the UART Handle.
@@ -664,12 +663,25 @@
/**
* @}
*/
+
/**
* @}
*/
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup USART_Private USART Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
/**
* @}
*/
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart_ex.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart_ex.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32l0xx_hal_usart_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Header file of USART HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -49,7 +49,7 @@
/** @addtogroup STM32L0xx_HAL_Driver
* @{
*/
-/** @defgroup USARTEx USARTEx Extended USART
+/** @defgroup USARTEx USARTEx
* @{
*/
@@ -62,9 +62,9 @@
/** @defgroup USARTEx_Word_Length Word length definition
* @{
*/
-#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
+#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_7B) || \
((LENGTH) == USART_WORDLENGTH_8B) || \
((LENGTH) == USART_WORDLENGTH_9B))
@@ -86,7 +86,7 @@
* @param __CLOCKSOURCE__ : output variable
* @retval the USART clocking source, written in __CLOCKSOURCE__.
*/
-#if defined (STM32L031xx) || defined (STM32L041xx)
+#if defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART2) \
@@ -111,7 +111,7 @@
} \
} while(0)
-#else /* (STM32L031xx) || defined (STM32L041xx) */
+#else /* (STM32L031xx) || defined (STM32L041xx) || (STM32L011xx) || defined (STM32L021xx) */
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
@@ -156,7 +156,7 @@
} \
} \
} while(0)
-#endif /* (STM32L031xx) || (STM32L041xx) */
+#endif /* (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || defined (STM32L021xx) */
/** @brief Reports the USART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_wwdg.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_wwdg.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_wwdg.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
@@ -65,7 +65,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -99,12 +99,13 @@
* @{
*/
+#ifdef HAL_WWDG_MODULE_ENABLED
+
/** @addtogroup WWDG
* @brief WWDG HAL module driver.
* @{
*/
-#ifdef HAL_WWDG_MODULE_ENABLED
/** @addtogroup WWDG_Exported_Functions WWDG Exported Functions
* @{
@@ -153,6 +154,9 @@
if(hwwdg->State == HAL_WWDG_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hwwdg->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
}
@@ -212,6 +216,9 @@
*/
__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hwwdg);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_WWDG_MspInit could be implemented in the user file
*/
@@ -225,6 +232,9 @@
*/
__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hwwdg);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_WWDG_MspDeInit could be implemented in the user file
*/
@@ -358,6 +368,8 @@
*/
__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hwwdg);
}
/**
@@ -398,11 +410,12 @@
* @}
*/
-#endif /* HAL_WWDG_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_wwdg.h Sun Apr 17 17:45:10 2016 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_wwdg.h Tue Apr 19 11:15:15 2016 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_wwdg.h * @author MCD Application Team - * @version V1.2.0 - * @date 06-February-2015 + * @version V1.5.0 + * @date 8-January-2016 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/hal/TARGET_STM/TARGET_STM32L0/rtc_api.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32L0/rtc_api.c Tue Apr 19 11:15:15 2016 +0100
@@ -42,6 +42,7 @@
void rtc_init(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
uint32_t rtc_freq = 0;
#if DEVICE_RTC_LSI
@@ -51,26 +52,30 @@
RtcHandle.Instance = RTC;
-#if !DEVICE_RTC_LSI
- // Enable LSE Oscillator
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
- RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
- // Connect LSE to RTC
- __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
- __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
- rtc_freq = LSE_VALUE;
- } else {
- error("Cannot initialize RTC with LSE\n");
- }
-#else
+ // Note : Due to a change inside stm32l0xx_hal_rcc.c (v1.2 to v1.5) the bit DBP of the register
+ // PWR_CR is now reset by the fonction HAL_RCC_OscConfig().
// Enable Power clock
__PWR_CLK_ENABLE();
// Enable access to Backup domain
HAL_PWR_EnableBkUpAccess();
+#if !DEVICE_RTC_LSI
+ // Enable LSE Oscillator
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ error("Cannot initialize RTC with LSE\n");
+ }
+ // Connect LSE to RTC
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ error("Cannot initialize RTC with LSI\n");
+ }
+ rtc_freq = LSE_VALUE;
+#else
// Reset Backup domain
__HAL_RCC_BACKUPRESET_FORCE();
__HAL_RCC_BACKUPRESET_RELEASE();
@@ -84,8 +89,11 @@
error("RTC error: LSI clock initialization failed.");
}
// Connect LSI to RTC
- __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
- __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ error("Cannot initialize RTC with LSI\n");
+ }
// This value is LSI typical value. To be measured precisely using a timer input capture for example.
rtc_freq = 38000;
#endif
@@ -186,6 +194,8 @@
timeinfo.tm_hour = timeStruct.Hours;
timeinfo.tm_min = timeStruct.Minutes;
timeinfo.tm_sec = timeStruct.Seconds;
+ // Daylight Saving Time information is not available
+ timeinfo.tm_isdst = -1;
// Convert to timestamp
time_t t = mktime(&timeinfo);