Janek Mann
mbed library sources modified for open wear
Dependents: openwear-lifelogger-example
Fork of
mbed-src
by 
mbed official
Revision 256:76fd9a263045, committed 2014-07-15
- Comitter:
- mbed_official
- Date:
- Tue Jul 15 07:45:08 2014 +0100
- Parent:
- 255:20b371a9491b
- Child:
- 257:9258cc0a200d
- Commit message:
- Synchronized with git revision 2031512f69c228e1d13ea89c39409db813af949f
Full URL: https://github.com/mbedmicro/mbed/commit/2031512f69c228e1d13ea89c39409db813af949f/
[LPC4330] Updated LPC4330_M4 port
Changed in this revision
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h Fri Jul 11 10:00:08 2014 +0100
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h Tue Jul 15 07:45:08 2014 +0100
@@ -1,5 +1,5 @@
/*
- * @brief LPC43xx/LPC18xx MCU header
+ * LPC43xx/LPC18xx MCU header
*
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
@@ -26,7 +26,7 @@
* this code.
*
* Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
- * 05/15/13 Micromint USA <support@micromint.com>
+ * 05/15/13 Micromint USA <support@micromint.com>
*/
#ifndef __LPC43XX_H
@@ -36,12 +36,7 @@
extern "C" {
#endif
-/** @defgroup LPC43XX_H: LPC43xx include file
- * @ingroup LPC43XX_Headers
- * @{
- */
-
-/* Treat __CORE_Mx as CORE_Mx for mbed builds */
+/* Treat __CORE_Mx as CORE_Mx */
#if defined(__CORTEX_M0) && !defined(CORE_M0)
#define CORE_M0
#endif
@@ -53,6 +48,14 @@
#define CORE_M4
#endif
+/* Define LPC18XX or LPC43XX according to core type */
+#if (defined(CORE_M4) || defined(CORE_M0)) && !defined(__LPC43XX__)
+ #define __LPC43XX__
+#endif
+#if defined(CORE_M3) && !defined(__LPC18XX__)
+ #define __LPC18XX__
+#endif
+
/* Start of section using anonymous unions */
#if defined(__ARMCC_VERSION)
// Kill warning "#pragma push with no matching #pragma pop"
@@ -70,911 +73,966 @@
#endif
#if defined(CORE_M4)
-/**
- * @brief LPC43xx Cortex CMSIS definitions
+/* ---------------------------------------------------------------------------
+ * LPC43xx (M4 Core) Cortex CMSIS definitions
*/
-#define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present or not */
-#define CHIP_LPC43XX /*!< LPCOPEN */
+#define __CM4_REV 0x0000 /* Cortex-M4 Core Revision */
+#define __MPU_PRESENT 1 /* MPU present or not */
+#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /* FPU present or not */
+#define CHIP_LPC43XX /* LPCOPEN compatibility */
-/**
- * @brief LPC43xx peripheral interrupt numbers
+/* ---------------------------------------------------------------------------
+ * LPC43xx peripheral interrupt numbers
*/
typedef enum {
- /* ------------------------- Cortex-M4 Processor Exceptions Numbers ----------------------------- */
- Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
- BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
- UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SVCall_IRQn = -5,/*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4,/*!< 12 Debug Monitor */
- PendSV_IRQn = -2,/*!< 14 Pendable request for system service */
- SysTick_IRQn = -1,/*!< 15 System Tick Timer */
+ /* --------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
+ Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
+ BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+ UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
+ PendSV_IRQn = -2,/* 14 Pendable request for system service */
+ SysTick_IRQn = -1,/* 15 System Tick Timer */
- /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
- DAC_IRQn = 0,/*!< 0 DAC */
- M0CORE_IRQn = 1,/*!< 1 M0a */
- DMA_IRQn = 2,/*!< 2 DMA */
- RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */
- RESERVED2_IRQn = 4,
- ETHERNET_IRQn = 5,/*!< 5 ETHERNET */
- SDIO_IRQn = 6,/*!< 6 SDIO */
- LCD_IRQn = 7,/*!< 7 LCD */
- USB0_IRQn = 8,/*!< 8 USB0 */
- USB1_IRQn = 9,/*!< 9 USB1 */
- SCT_IRQn = 10,/*!< 10 SCT */
- RITIMER_IRQn = 11,/*!< 11 RITIMER */
- TIMER0_IRQn = 12,/*!< 12 TIMER0 */
- TIMER1_IRQn = 13,/*!< 13 TIMER1 */
- TIMER2_IRQn = 14,/*!< 14 TIMER2 */
- TIMER3_IRQn = 15,/*!< 15 TIMER3 */
- MCPWM_IRQn = 16,/*!< 16 MCPWM */
- ADC0_IRQn = 17,/*!< 17 ADC0 */
- I2C0_IRQn = 18,/*!< 18 I2C0 */
- I2C1_IRQn = 19,/*!< 19 I2C1 */
- SPI_INT_IRQn = 20,/*!< 20 SPI_INT */
- ADC1_IRQn = 21,/*!< 21 ADC1 */
- SSP0_IRQn = 22,/*!< 22 SSP0 */
- SSP1_IRQn = 23,/*!< 23 SSP1 */
- USART0_IRQn = 24,/*!< 24 USART0 */
- UART1_IRQn = 25,/*!< 25 UART1 */
- USART2_IRQn = 26,/*!< 26 USART2 */
- USART3_IRQn = 27,/*!< 27 USART3 */
- I2S0_IRQn = 28,/*!< 28 I2S0 */
- I2S1_IRQn = 29,/*!< 29 I2S1 */
- RESERVED4_IRQn = 30,
- SGPIO_INT_IRQn = 31,/*!< 31 SGPIO_IINT */
- PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */
- PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */
- PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */
- PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */
- PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */
- PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */
- PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */
- PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */
- GINT0_IRQn = 40,/*!< 40 GINT0 */
- GINT1_IRQn = 41,/*!< 41 GINT1 */
- EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */
- C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */
- RESERVED6_IRQn = 44,
- RESERVED7_IRQn = 45,/*!< 45 VADC */
- ATIMER_IRQn = 46,/*!< 46 ATIMER */
- RTC_IRQn = 47,/*!< 47 RTC */
- RESERVED8_IRQn = 48,
- WWDT_IRQn = 49,/*!< 49 WWDT */
- RESERVED9_IRQn = 50,
- C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */
- QEI_IRQn = 52,/*!< 52 QEI */
+ /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
+ DAC_IRQn = 0,/* 0 DAC */
+ M0CORE_IRQn = 1,/* 1 M0a */
+ DMA_IRQn = 2,/* 2 DMA */
+ RESERVED1_IRQn = 3,/* 3 EZH/EDM */
+ RESERVED2_IRQn = 4,
+ ETHERNET_IRQn = 5,/* 5 ETHERNET */
+ SDIO_IRQn = 6,/* 6 SDIO */
+ LCD_IRQn = 7,/* 7 LCD */
+ USB0_IRQn = 8,/* 8 USB0 */
+ USB1_IRQn = 9,/* 9 USB1 */
+ SCT_IRQn = 10,/* 10 SCT */
+ RITIMER_IRQn = 11,/* 11 RITIMER */
+ TIMER0_IRQn = 12,/* 12 TIMER0 */
+ TIMER1_IRQn = 13,/* 13 TIMER1 */
+ TIMER2_IRQn = 14,/* 14 TIMER2 */
+ TIMER3_IRQn = 15,/* 15 TIMER3 */
+ MCPWM_IRQn = 16,/* 16 MCPWM */
+ ADC0_IRQn = 17,/* 17 ADC0 */
+ I2C0_IRQn = 18,/* 18 I2C0 */
+ I2C1_IRQn = 19,/* 19 I2C1 */
+ SPI_INT_IRQn = 20,/* 20 SPI_INT */
+ ADC1_IRQn = 21,/* 21 ADC1 */
+ SSP0_IRQn = 22,/* 22 SSP0 */
+ SSP1_IRQn = 23,/* 23 SSP1 */
+ USART0_IRQn = 24,/* 24 USART0 */
+ UART1_IRQn = 25,/* 25 UART1 */
+ USART2_IRQn = 26,/* 26 USART2 */
+ USART3_IRQn = 27,/* 27 USART3 */
+ I2S0_IRQn = 28,/* 28 I2S0 */
+ I2S1_IRQn = 29,/* 29 I2S1 */
+ RESERVED4_IRQn = 30,
+ SGPIO_INT_IRQn = 31,/* 31 SGPIO_IINT */
+ PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
+ PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
+ PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
+ PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
+ PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
+ PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
+ PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
+ PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
+ GINT0_IRQn = 40,/* 40 GINT0 */
+ GINT1_IRQn = 41,/* 41 GINT1 */
+ EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
+ C_CAN1_IRQn = 43,/* 43 C_CAN1 */
+ RESERVED6_IRQn = 44,
+ RESERVED7_IRQn = 45,/* 45 VADC */
+ ATIMER_IRQn = 46,/* 46 ATIMER */
+ RTC_IRQn = 47,/* 47 RTC */
+ RESERVED8_IRQn = 48,
+ WWDT_IRQn = 49,/* 49 WWDT */
+ RESERVED9_IRQn = 50,
+ C_CAN0_IRQn = 51,/* 51 C_CAN0 */
+ QEI_IRQn = 52,/* 52 QEI */
} IRQn_Type;
-#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#elif defined(CORE_M3)
-/**
- * @brief LPC18xx Cortex CMSIS definitions
+/* ---------------------------------------------------------------------------
+ * LPC18xx (M3 Core) Cortex CMSIS definitions
*/
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 0 /*!< FPU present or not */
-#define CHIP_LPC18XX /*!< LPCOPEN */
+#define __MPU_PRESENT 1 /* MPU present or not */
+#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 0 /* FPU present or not */
+#define CHIP_LPC18XX /* LPCOPEN compatibility */
-/**
- * @brief LPC18xx peripheral interrupt numbers
+/* ---------------------------------------------------------------------------
+ * LPC18xx peripheral interrupt numbers
*/
typedef enum {
- /* ------------------------- Cortex-M3 Processor Exceptions Numbers ----------------------------- */
- Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
- BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
- UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+ /* --------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
+ Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
+ BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+ UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
+ PendSV_IRQn = -2,/* 14 Pendable request for system service */
+ SysTick_IRQn = -1,/* 15 System Tick Timer */
- /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
- DAC_IRQn = 0,/*!< 0 DAC */
- RESERVED0_IRQn = 1,
- DMA_IRQn = 2,/*!< 2 DMA */
- RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */
- RESERVED2_IRQn = 4,
- ETHERNET_IRQn = 5,/*!< 5 ETHERNET */
- SDIO_IRQn = 6,/*!< 6 SDIO */
- LCD_IRQn = 7,/*!< 7 LCD */
- USB0_IRQn = 8,/*!< 8 USB0 */
- USB1_IRQn = 9,/*!< 9 USB1 */
- SCT_IRQn = 10,/*!< 10 SCT */
- RITIMER_IRQn = 11,/*!< 11 RITIMER */
- TIMER0_IRQn = 12,/*!< 12 TIMER0 */
- TIMER1_IRQn = 13,/*!< 13 TIMER1 */
- TIMER2_IRQn = 14,/*!< 14 TIMER2 */
- TIMER3_IRQn = 15,/*!< 15 TIMER3 */
- MCPWM_IRQn = 16,/*!< 16 MCPWM */
- ADC0_IRQn = 17,/*!< 17 ADC0 */
- I2C0_IRQn = 18,/*!< 18 I2C0 */
- I2C1_IRQn = 19,/*!< 19 I2C1 */
- RESERVED3_IRQn = 20,
- ADC1_IRQn = 21,/*!< 21 ADC1 */
- SSP0_IRQn = 22,/*!< 22 SSP0 */
- SSP1_IRQn = 23,/*!< 23 SSP1 */
- USART0_IRQn = 24,/*!< 24 USART0 */
- UART1_IRQn = 25,/*!< 25 UART1 */
- USART2_IRQn = 26,/*!< 26 USART2 */
- USART3_IRQn = 27,/*!< 27 USART3 */
- I2S0_IRQn = 28,/*!< 28 I2S0 */
- I2S1_IRQn = 29,/*!< 29 I2S1 */
- RESERVED4_IRQn = 30,
- RESERVED5_IRQn = 31,
- PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */
- PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */
- PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */
- PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */
- PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */
- PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */
- PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */
- PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */
- GINT0_IRQn = 40,/*!< 40 GINT0 */
- GINT1_IRQn = 41,/*!< 41 GINT1 */
- EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */
- C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */
- RESERVED6_IRQn = 44,
- RESERVED7_IRQn = 45,/*!< 45 VADC */
- ATIMER_IRQn = 46,/*!< 46 ATIMER */
- RTC_IRQn = 47,/*!< 47 RTC */
- RESERVED8_IRQn = 48,
- WWDT_IRQn = 49,/*!< 49 WWDT */
- RESERVED9_IRQn = 50,
- C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */
- QEI_IRQn = 52,/*!< 52 QEI */
+ /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
+ DAC_IRQn = 0,/* 0 DAC */
+ RESERVED0_IRQn = 1,
+ DMA_IRQn = 2,/* 2 DMA */
+ RESERVED1_IRQn = 3,/* 3 EZH/EDM */
+ RESERVED2_IRQn = 4,
+ ETHERNET_IRQn = 5,/* 5 ETHERNET */
+ SDIO_IRQn = 6,/* 6 SDIO */
+ LCD_IRQn = 7,/* 7 LCD */
+ USB0_IRQn = 8,/* 8 USB0 */
+ USB1_IRQn = 9,/* 9 USB1 */
+ SCT_IRQn = 10,/* 10 SCT */
+ RITIMER_IRQn = 11,/* 11 RITIMER */
+ TIMER0_IRQn = 12,/* 12 TIMER0 */
+ TIMER1_IRQn = 13,/* 13 TIMER1 */
+ TIMER2_IRQn = 14,/* 14 TIMER2 */
+ TIMER3_IRQn = 15,/* 15 TIMER3 */
+ MCPWM_IRQn = 16,/* 16 MCPWM */
+ ADC0_IRQn = 17,/* 17 ADC0 */
+ I2C0_IRQn = 18,/* 18 I2C0 */
+ I2C1_IRQn = 19,/* 19 I2C1 */
+ RESERVED3_IRQn = 20,
+ ADC1_IRQn = 21,/* 21 ADC1 */
+ SSP0_IRQn = 22,/* 22 SSP0 */
+ SSP1_IRQn = 23,/* 23 SSP1 */
+ USART0_IRQn = 24,/* 24 USART0 */
+ UART1_IRQn = 25,/* 25 UART1 */
+ USART2_IRQn = 26,/* 26 USART2 */
+ USART3_IRQn = 27,/* 27 USART3 */
+ I2S0_IRQn = 28,/* 28 I2S0 */
+ I2S1_IRQn = 29,/* 29 I2S1 */
+ RESERVED4_IRQn = 30,
+ RESERVED5_IRQn = 31,
+ PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
+ PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
+ PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
+ PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
+ PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
+ PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
+ PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
+ PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
+ GINT0_IRQn = 40,/* 40 GINT0 */
+ GINT1_IRQn = 41,/* 41 GINT1 */
+ EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
+ C_CAN1_IRQn = 43,/* 43 C_CAN1 */
+ RESERVED6_IRQn = 44,
+ RESERVED7_IRQn = 45,/* 45 VADC */
+ ATIMER_IRQn = 46,/* 46 ATIMER */
+ RTC_IRQn = 47,/* 47 RTC */
+ RESERVED8_IRQn = 48,
+ WWDT_IRQn = 49,/* 49 WWDT */
+ RESERVED9_IRQn = 50,
+ C_CAN0_IRQn = 51,/* 51 C_CAN0 */
+ QEI_IRQn = 52,/* 52 QEI */
} IRQn_Type;
-#include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
#elif defined(CORE_M0)
-/**
- * @brief LPC43xx (M0 Core) Cortex CMSIS definitions
+/* ---------------------------------------------------------------------------
+ * LPC43xx (M0 Core) Cortex CMSIS definitions
*/
-#define __MPU_PRESENT 0 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 0 /*!< FPU present or not */
-#define CHIP_LPC43XX /*!< LPCOPEN */
+#define __MPU_PRESENT 0 /* MPU present or not */
+#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 0 /* FPU present or not */
+#define CHIP_LPC43XX /* LPCOPEN compatibility */
-/**
- * @brief LPC43xx (M0 Core) peripheral interrupt numbers
+/* ---------------------------------------------------------------------------
+ * LPC43xx (M0 Core) peripheral interrupt numbers
*/
typedef enum {
- /* ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- */
- Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+ /* --------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
+ Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
+ PendSV_IRQn = -2,/* 14 Pendable request for system service */
+ SysTick_IRQn = -1,/* 15 System Tick Timer */
- /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
- DAC_IRQn = 0,/*!< 0 DAC */
- M0_M4CORE_IRQn = 1,/*!< 1 M0a */
- DMA_IRQn = 2,/*!< 2 DMA r */
- RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */
- FLASHEEPROM_IRQn = 4,/*!< 4 ORed Flash EEPROM Bank A, B, EEPROM */
- ETHERNET_IRQn = 5,/*!< 5 ETHERNET */
- SDIO_IRQn = 6,/*!< 6 SDIO */
- LCD_IRQn = 7,/*!< 7 LCD */
- USB0_IRQn = 8,/*!< 8 USB0 */
- USB1_IRQn = 9,/*!< 9 USB1 */
- SCT_IRQn = 10,/*!< 10 SCT */
- RITIMER_IRQn = 11,/*!< 11 ORed RITIMER, WDT */
- TIMER0_IRQn = 12,/*!< 12 TIMER0 */
- GINT1_IRQn = 13,/*!< 13 GINT1 */
- PIN_INT4_IRQn = 14,/*!< 14 GPIO 4 */
- TIMER3_IRQn = 15,/*!< 15 TIMER3 */
- MCPWM_IRQn = 16,/*!< 16 MCPWM */
- ADC0_IRQn = 17,/*!< 17 ADC0 */
- I2C0_IRQn = 18,/*!< 18 ORed I2C0, I2C1 */
- SGPIO_INT_IRQn = 19,/*!< 19 SGPIO */
- SPI_INT_IRQn = 20,/*!< 20 SPI_INT */
- ADC1_IRQn = 21,/*!< 21 ADC1 */
- SSP0_IRQn = 22,/*!< 22 ORed SSP0, SSP1 */
- EVENTROUTER_IRQn = 23,/*!< 23 EVENTROUTER */
- USART0_IRQn = 24,/*!< 24 USART0 */
- UART1_IRQn = 25,/*!< 25 UART1 */
- USART2_IRQn = 26,/*!< 26 USART2 */
- USART3_IRQn = 27,/*!< 27 USART3 */
- I2S0_IRQn = 28,/*!< 28 ORed I2S0, I2S1 */
- C_CAN0_IRQn = 29,/*!< 29 C_CAN0 */
- I2S1_IRQn = 29,/*!< 29 I2S1 */
- RESERVED2_IRQn = 30,
- RESERVED3_IRQn = 31,
+ /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
+ DAC_IRQn = 0,/* 0 DAC */
+ M0_M4CORE_IRQn = 1,/* 1 M0a */
+ DMA_IRQn = 2,/* 2 DMA r */
+ RESERVED1_IRQn = 3,/* 3 EZH/EDM */
+ FLASHEEPROM_IRQn = 4,/* 4 ORed Flash EEPROM Bank A, B, EEPROM */
+ ETHERNET_IRQn = 5,/* 5 ETHERNET */
+ SDIO_IRQn = 6,/* 6 SDIO */
+ LCD_IRQn = 7,/* 7 LCD */
+ USB0_IRQn = 8,/* 8 USB0 */
+ USB1_IRQn = 9,/* 9 USB1 */
+ SCT_IRQn = 10,/* 10 SCT */
+ RITIMER_IRQn = 11,/* 11 ORed RITIMER, WDT */
+ TIMER0_IRQn = 12,/* 12 TIMER0 */
+ GINT1_IRQn = 13,/* 13 GINT1 */
+ PIN_INT4_IRQn = 14,/* 14 GPIO 4 */
+ TIMER3_IRQn = 15,/* 15 TIMER3 */
+ MCPWM_IRQn = 16,/* 16 MCPWM */
+ ADC0_IRQn = 17,/* 17 ADC0 */
+ I2C0_IRQn = 18,/* 18 ORed I2C0, I2C1 */
+ SGPIO_INT_IRQn = 19,/* 19 SGPIO */
+ SPI_INT_IRQn = 20,/* 20 SPI_INT */
+ ADC1_IRQn = 21,/* 21 ADC1 */
+ SSP0_IRQn = 22,/* 22 ORed SSP0, SSP1 */
+ EVENTROUTER_IRQn = 23,/* 23 EVENTROUTER */
+ USART0_IRQn = 24,/* 24 USART0 */
+ UART1_IRQn = 25,/* 25 UART1 */
+ USART2_IRQn = 26,/* 26 USART2 */
+ USART3_IRQn = 27,/* 27 USART3 */
+ I2S0_IRQn = 28,/* 28 ORed I2S0, I2S1 */
+ C_CAN0_IRQn = 29,/* 29 C_CAN0 */
+ I2S1_IRQn = 29,/* 29 I2S1 */
+ RESERVED2_IRQn = 30,
+ RESERVED3_IRQn = 31,
} IRQn_Type;
-#include "core_cm0.h" /*!< Cortex-M4 processor and core peripherals */
+#include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
#else
#error Please #define CORE_M0, CORE_M3 or CORE_M4
#endif
-#include "system_LPC43xx.h"
+#include "system_LPC43XX.h"
-/**
- * @brief State Configurable Timer register block structure
+/* ---------------------------------------------------------------------------
+ * State Configurable Timer register block structure
*/
#define LPC_SCT_BASE 0x40000000
-#define CONFIG_SCT_nEV (16) /*!< Number of events */
-#define CONFIG_SCT_nRG (16) /*!< Number of match/compare registers */
-#define CONFIG_SCT_nOU (16) /*!< Number of outputs */
+#define CONFIG_SCT_nEV (16) /* Number of events */
+#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
+#define CONFIG_SCT_nOU (16) /* Number of outputs */
typedef struct {
- __IO uint32_t CONFIG; /*!< Configuration Register */
- union {
- __IO uint32_t CTRL_U; /*!< Control Register */
- struct {
- __IO uint16_t CTRL_L; /*!< Low control register */
- __IO uint16_t CTRL_H; /*!< High control register */
- };
+ __IO uint32_t CONFIG; /* Configuration Register */
+ union {
+ __IO uint32_t CTRL_U; /* Control Register */
+ struct {
+ __IO uint16_t CTRL_L; /* Low control register */
+ __IO uint16_t CTRL_H; /* High control register */
+ };
- };
+ };
- __IO uint16_t LIMIT_L; /*!< limit register for counter L */
- __IO uint16_t LIMIT_H; /*!< limit register for counter H */
- __IO uint16_t HALT_L; /*!< halt register for counter L */
- __IO uint16_t HALT_H; /*!< halt register for counter H */
- __IO uint16_t STOP_L; /*!< stop register for counter L */
- __IO uint16_t STOP_H; /*!< stop register for counter H */
- __IO uint16_t START_L; /*!< start register for counter L */
- __IO uint16_t START_H; /*!< start register for counter H */
- uint32_t RESERVED1[10]; /*!< 0x03C reserved */
- union {
- __IO uint32_t COUNT_U; /*!< counter register */
- struct {
- __IO uint16_t COUNT_L; /*!< counter register for counter L */
- __IO uint16_t COUNT_H; /*!< counter register for counter H */
- };
+ __IO uint16_t LIMIT_L; /* limit register for counter L */
+ __IO uint16_t LIMIT_H; /* limit register for counter H */
+ __IO uint16_t HALT_L; /* halt register for counter L */
+ __IO uint16_t HALT_H; /* halt register for counter H */
+ __IO uint16_t STOP_L; /* stop register for counter L */
+ __IO uint16_t STOP_H; /* stop register for counter H */
+ __IO uint16_t START_L; /* start register for counter L */
+ __IO uint16_t START_H; /* start register for counter H */
+ uint32_t RESERVED1[10]; /* 0x03C reserved */
+ union {
+ __IO uint32_t COUNT_U; /* counter register */
+ struct {
+ __IO uint16_t COUNT_L; /* counter register for counter L */
+ __IO uint16_t COUNT_H; /* counter register for counter H */
+ };
- };
+ };
- __IO uint16_t STATE_L; /*!< state register for counter L */
- __IO uint16_t STATE_H; /*!< state register for counter H */
- __I uint32_t INPUT; /*!< input register */
- __IO uint16_t REGMODE_L; /*!< match - capture registers mode register L */
- __IO uint16_t REGMODE_H; /*!< match - capture registers mode register H */
- __IO uint32_t OUTPUT; /*!< output register */
- __IO uint32_t OUTPUTDIRCTRL; /*!< output counter direction Control Register */
- __IO uint32_t RES; /*!< conflict resolution register */
- __IO uint32_t DMA0REQUEST; /*!< DMA0 Request Register */
- __IO uint32_t DMA1REQUEST; /*!< DMA1 Request Register */
- uint32_t RESERVED2[35];
- __IO uint32_t EVEN; /*!< event enable register */
- __IO uint32_t EVFLAG; /*!< event flag register */
- __IO uint32_t CONEN; /*!< conflict enable register */
- __IO uint32_t CONFLAG; /*!< conflict flag register */
- union {
- __IO union { /*!< ... Match / Capture value */
- uint32_t U; /*!< SCTMATCH[i].U Unified 32-bit register */
- struct {
- uint16_t L; /*!< SCTMATCH[i].L Access to L value */
- uint16_t H; /*!< SCTMATCH[i].H Access to H value */
- };
+ __IO uint16_t STATE_L; /* state register for counter L */
+ __IO uint16_t STATE_H; /* state register for counter H */
+ __I uint32_t INPUT; /* input register */
+ __IO uint16_t REGMODE_L; /* match - capture registers mode register L */
+ __IO uint16_t REGMODE_H; /* match - capture registers mode register H */
+ __IO uint32_t OUTPUT; /* output register */
+ __IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
+ __IO uint32_t RES; /* conflict resolution register */
+ __IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
+ __IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
+ uint32_t RESERVED2[35];
+ __IO uint32_t EVEN; /* event enable register */
+ __IO uint32_t EVFLAG; /* event flag register */
+ __IO uint32_t CONEN; /* conflict enable register */
+ __IO uint32_t CONFLAG; /* conflict flag register */
+ union {
+ __IO union { /* ... Match / Capture value */
+ uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCH[i].L Access to L value */
+ uint16_t H; /* SCTMATCH[i].H Access to H value */
+ };
- } MATCH[CONFIG_SCT_nRG];
+ } MATCH[CONFIG_SCT_nRG];
- __I union {
- uint32_t U; /*!< SCTCAP[i].U Unified 32-bit register */
- struct {
- uint16_t L; /*!< SCTCAP[i].L Access to L value */
- uint16_t H; /*!< SCTCAP[i].H Access to H value */
- };
+ __I union {
+ uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAP[i].L Access to L value */
+ uint16_t H; /* SCTCAP[i].H Access to H value */
+ };
- } CAP[CONFIG_SCT_nRG];
+ } CAP[CONFIG_SCT_nRG];
- };
+ };
- uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /*!< ...-0x17C reserved */
- union {
- __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /*!< 0x180-... Match Value L counter */
- __I uint16_t CAP_L[CONFIG_SCT_nRG]; /*!< 0x180-... Capture Value L counter */
- };
+ uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /* ...-0x17C reserved */
+ union {
+ __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
+ __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
+ };
- uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /*!< ...-0x1BE reserved */
- union {
- __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /*!< 0x1C0-... Match Value H counter */
- __I uint16_t CAP_H[CONFIG_SCT_nRG]; /*!< 0x1C0-... Capture Value H counter */
- };
+ uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
+ union {
+ __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
+ __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
+ };
- uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /*!< ...-0x1FE reserved */
- union {
- __IO union { /*!< 0x200-... Match Reload / Capture Control value */
- uint32_t U; /*!< SCTMATCHREL[i].U Unified 32-bit register */
- struct {
- uint16_t L; /*!< SCTMATCHREL[i].L Access to L value */
- uint16_t H; /*!< SCTMATCHREL[i].H Access to H value */
- };
+ uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
+ union {
+ __IO union { /* 0x200-... Match Reload / Capture Control value */
+ uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCHREL[i].L Access to L value */
+ uint16_t H; /* SCTMATCHREL[i].H Access to H value */
+ };
- } MATCHREL[CONFIG_SCT_nRG];
+ } MATCHREL[CONFIG_SCT_nRG];
- __IO union {
- uint32_t U; /*!< SCTCAPCTRL[i].U Unified 32-bit register */
- struct {
- uint16_t L; /*!< SCTCAPCTRL[i].L Access to L value */
- uint16_t H; /*!< SCTCAPCTRL[i].H Access to H value */
- };
+ __IO union {
+ uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAPCTRL[i].L Access to L value */
+ uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
+ };
- } CAPCTRL[CONFIG_SCT_nRG];
+ } CAPCTRL[CONFIG_SCT_nRG];
- };
+ };
- uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /*!< ...-0x27C reserved */
- union {
- __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /*!< 0x280-... Match Reload value L counter */
- __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /*!< 0x280-... Capture Control value L counter */
- };
+ uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /* ...-0x27C reserved */
+ union {
+ __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
+ __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
+ };
- uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /*!< ...-0x2BE reserved */
- union {
- __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /*!< 0x2C0-... Match Reload value H counter */
- __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /*!< 0x2C0-... Capture Control value H counter */
- };
+ uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
+ union {
+ __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
+ __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
+ };
- uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /*!< ...-0x2FE reserved */
- __IO struct { /*!< 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
- uint32_t STATE; /*!< Event State Register */
- uint32_t CTRL; /*!< Event Control Register */
- } EVENT[CONFIG_SCT_nEV];
+ uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
+ __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
+ uint32_t STATE; /* Event State Register */
+ uint32_t CTRL; /* Event Control Register */
+ } EVENT[CONFIG_SCT_nEV];
- uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /*!< ...-0x4FC reserved */
- __IO struct { /*!< 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
- uint32_t SET; /*!< Output n Set Register */
- uint32_t CLR; /*!< Output n Clear Register */
- } OUT[CONFIG_SCT_nOU];
+ uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
+ __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
+ uint32_t SET; /* Output n Set Register */
+ uint32_t CLR; /* Output n Clear Register */
+ } OUT[CONFIG_SCT_nOU];
- uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /*!< ...-0x7F8 reserved */
- __I uint32_t MODULECONTENT; /*!< 0x7FC Module Content */
+ uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
+ __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
} LPC_SCT_T;
-/**
- * @brief GPDMA Channel register block structure
+/* Macro defines for SCT configuration register */
+#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /* Operate as 2 16-bit counters */
+#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /* Operate as 1 32-bit counter */
+
+#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /* Bus clock */
+#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /* SCT clock */
+#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /* Input clock selected in CLKSEL field */
+#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /* Input clock edge selected in CLKSEL field */
+
+#define SCT_CONFIG_NORELOADL_U (0x1 << 7) /* Operate as 1 32-bit counter */
+#define SCT_CONFIG_NORELOADH (0x1 << 8) /* Operate as 1 32-bit counter */
+
+/* Macro defines for SCT control register */
+#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for low or unified counter */
+#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
+
+#define SCT_CTRL_STOP_L (1 << 1) /* Stop low counter */
+#define SCT_CTRL_HALT_L (1 << 2) /* Halt low counter */
+#define SCT_CTRL_CLRCTR_L (1 << 3) /* Clear low or unified counter */
+#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /* Bidirectional bit */
+#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /* Prescale clock for low or unified counter */
+
+#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for high counter */
+#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
+#define SCT_CTRL_STOP_H (1 << 17) /* Stop high counter */
+#define SCT_CTRL_HALT_H (1 << 18) /* Halt high counter */
+#define SCT_CTRL_CLRCTR_H (1 << 19) /* Clear high counter */
+#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
+#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /* Prescale clock for high counter */
+
+/* Macro defines for SCT Conflict resolution register */
+#define SCT_RES_NOCHANGE (0)
+#define SCT_RES_SET_OUTPUT (1)
+#define SCT_RES_CLEAR_OUTPUT (2)
+#define SCT_RES_TOGGLE_OUTPUT (3)
+
+/* ---------------------------------------------------------------------------
+ * GPDMA Channel register block structure
*/
#define LPC_GPDMA_BASE 0x40002000
typedef struct {
- __IO uint32_t SRCADDR; /*!< DMA Channel Source Address Register */
- __IO uint32_t DESTADDR; /*!< DMA Channel Destination Address Register */
- __IO uint32_t LLI; /*!< DMA Channel Linked List Item Register */
- __IO uint32_t CONTROL; /*!< DMA Channel Control Register */
- __IO uint32_t CONFIG; /*!< DMA Channel Configuration Register */
- __I uint32_t RESERVED1[3];
+ __IO uint32_t SRCADDR; /* DMA Channel Source Address Register */
+ __IO uint32_t DESTADDR; /* DMA Channel Destination Address Register */
+ __IO uint32_t LLI; /* DMA Channel Linked List Item Register */
+ __IO uint32_t CONTROL; /* DMA Channel Control Register */
+ __IO uint32_t CONFIG; /* DMA Channel Configuration Register */
+ __I uint32_t RESERVED1[3];
} LPC_GPDMA_CH_T;
#define GPDMA_CHANNELS 8
-/**
- * @brief GPDMA register block
+/* ---------------------------------------------------------------------------
+ * GPDMA register block
*/
-typedef struct { /*!< GPDMA Structure */
- __I uint32_t INTSTAT; /*!< DMA Interrupt Status Register */
- __I uint32_t INTTCSTAT; /*!< DMA Interrupt Terminal Count Request Status Register */
- __O uint32_t INTTCCLEAR; /*!< DMA Interrupt Terminal Count Request Clear Register */
- __I uint32_t INTERRSTAT; /*!< DMA Interrupt Error Status Register */
- __O uint32_t INTERRCLR; /*!< DMA Interrupt Error Clear Register */
- __I uint32_t RAWINTTCSTAT; /*!< DMA Raw Interrupt Terminal Count Status Register */
- __I uint32_t RAWINTERRSTAT; /*!< DMA Raw Error Interrupt Status Register */
- __I uint32_t ENBLDCHNS; /*!< DMA Enabled Channel Register */
- __IO uint32_t SOFTBREQ; /*!< DMA Software Burst Request Register */
- __IO uint32_t SOFTSREQ; /*!< DMA Software Single Request Register */
- __IO uint32_t SOFTLBREQ; /*!< DMA Software Last Burst Request Register */
- __IO uint32_t SOFTLSREQ; /*!< DMA Software Last Single Request Register */
- __IO uint32_t CONFIG; /*!< DMA Configuration Register */
- __IO uint32_t SYNC; /*!< DMA Synchronization Register */
- __I uint32_t RESERVED0[50];
- LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
+typedef struct { /* GPDMA Structure */
+ __I uint32_t INTSTAT; /* DMA Interrupt Status Register */
+ __I uint32_t INTTCSTAT; /* DMA Interrupt Terminal Count Request Status Register */
+ __O uint32_t INTTCCLEAR; /* DMA Interrupt Terminal Count Request Clear Register */
+ __I uint32_t INTERRSTAT; /* DMA Interrupt Error Status Register */
+ __O uint32_t INTERRCLR; /* DMA Interrupt Error Clear Register */
+ __I uint32_t RAWINTTCSTAT; /* DMA Raw Interrupt Terminal Count Status Register */
+ __I uint32_t RAWINTERRSTAT; /* DMA Raw Error Interrupt Status Register */
+ __I uint32_t ENBLDCHNS; /* DMA Enabled Channel Register */
+ __IO uint32_t SOFTBREQ; /* DMA Software Burst Request Register */
+ __IO uint32_t SOFTSREQ; /* DMA Software Single Request Register */
+ __IO uint32_t SOFTLBREQ; /* DMA Software Last Burst Request Register */
+ __IO uint32_t SOFTLSREQ; /* DMA Software Last Single Request Register */
+ __IO uint32_t CONFIG; /* DMA Configuration Register */
+ __IO uint32_t SYNC; /* DMA Synchronization Register */
+ __I uint32_t RESERVED0[50];
+ LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
} LPC_GPDMA_T;
-/**
- * @brief SD/MMC & SDIO register block structure
+/* ---------------------------------------------------------------------------
+ * SPIFI register block structure
+ */
+#define LPC_SPIFI_BASE 0x40003000
+
+typedef struct { /* SPIFI Structure */
+ __IO uint32_t CTRL; /* Control register */
+ __IO uint32_t CMD; /* Command register */
+ __IO uint32_t ADDR; /* Address register */
+ __IO uint32_t IDATA; /* Intermediate data register */
+ __IO uint32_t CLIMIT; /* Cache limit register */
+ union {
+ __IO uint32_t DATA;
+ __IO uint16_t DATA_HWORD;
+ __IO uint8_t DATA_BYTE;
+ }; /* Data register */
+ __IO uint32_t MCMD; /* Memory command register */
+ __IO uint32_t STAT; /* Status register */
+} LPC_SPIFI_T;
+
+/* ---------------------------------------------------------------------------
+ * SD/MMC & SDIO register block structure
*/
#define LPC_SDMMC_BASE 0x40004000
-typedef struct { /*!< SDMMC Structure */
- __IO uint32_t CTRL; /*!< Control Register */
- __IO uint32_t PWREN; /*!< Power Enable Register */
- __IO uint32_t CLKDIV; /*!< Clock Divider Register */
- __IO uint32_t CLKSRC; /*!< SD Clock Source Register */
- __IO uint32_t CLKENA; /*!< Clock Enable Register */
- __IO uint32_t TMOUT; /*!< Timeout Register */
- __IO uint32_t CTYPE; /*!< Card Type Register */
- __IO uint32_t BLKSIZ; /*!< Block Size Register */
- __IO uint32_t BYTCNT; /*!< Byte Count Register */
- __IO uint32_t INTMASK; /*!< Interrupt Mask Register */
- __IO uint32_t CMDARG; /*!< Command Argument Register */
- __IO uint32_t CMD; /*!< Command Register */
- __I uint32_t RESP0; /*!< Response Register 0 */
- __I uint32_t RESP1; /*!< Response Register 1 */
- __I uint32_t RESP2; /*!< Response Register 2 */
- __I uint32_t RESP3; /*!< Response Register 3 */
- __I uint32_t MINTSTS; /*!< Masked Interrupt Status Register */
- __IO uint32_t RINTSTS; /*!< Raw Interrupt Status Register */
- __I uint32_t STATUS; /*!< Status Register */
- __IO uint32_t FIFOTH; /*!< FIFO Threshold Watermark Register */
- __I uint32_t CDETECT; /*!< Card Detect Register */
- __I uint32_t WRTPRT; /*!< Write Protect Register */
- __IO uint32_t GPIO; /*!< General Purpose Input/Output Register */
- __I uint32_t TCBCNT; /*!< Transferred CIU Card Byte Count Register */
- __I uint32_t TBBCNT; /*!< Transferred Host to BIU-FIFO Byte Count Register */
- __IO uint32_t DEBNCE; /*!< Debounce Count Register */
- __IO uint32_t USRID; /*!< User ID Register */
- __I uint32_t VERID; /*!< Version ID Register */
- __I uint32_t RESERVED0;
- __IO uint32_t UHS_REG; /*!< UHS-1 Register */
- __IO uint32_t RST_N; /*!< Hardware Reset */
- __I uint32_t RESERVED1;
- __IO uint32_t BMOD; /*!< Bus Mode Register */
- __O uint32_t PLDMND; /*!< Poll Demand Register */
- __IO uint32_t DBADDR; /*!< Descriptor List Base Address Register */
- __IO uint32_t IDSTS; /*!< Internal DMAC Status Register */
- __IO uint32_t IDINTEN; /*!< Internal DMAC Interrupt Enable Register */
- __I uint32_t DSCADDR; /*!< Current Host Descriptor Address Register */
- __I uint32_t BUFADDR; /*!< Current Buffer Descriptor Address Register */
+typedef struct { /* SDMMC Structure */
+ __IO uint32_t CTRL; /* Control Register */
+ __IO uint32_t PWREN; /* Power Enable Register */
+ __IO uint32_t CLKDIV; /* Clock Divider Register */
+ __IO uint32_t CLKSRC; /* SD Clock Source Register */
+ __IO uint32_t CLKENA; /* Clock Enable Register */
+ __IO uint32_t TMOUT; /* Timeout Register */
+ __IO uint32_t CTYPE; /* Card Type Register */
+ __IO uint32_t BLKSIZ; /* Block Size Register */
+ __IO uint32_t BYTCNT; /* Byte Count Register */
+ __IO uint32_t INTMASK; /* Interrupt Mask Register */
+ __IO uint32_t CMDARG; /* Command Argument Register */
+ __IO uint32_t CMD; /* Command Register */
+ __I uint32_t RESP0; /* Response Register 0 */
+ __I uint32_t RESP1; /* Response Register 1 */
+ __I uint32_t RESP2; /* Response Register 2 */
+ __I uint32_t RESP3; /* Response Register 3 */
+ __I uint32_t MINTSTS; /* Masked Interrupt Status Register */
+ __IO uint32_t RINTSTS; /* Raw Interrupt Status Register */
+ __I uint32_t STATUS; /* Status Register */
+ __IO uint32_t FIFOTH; /* FIFO Threshold Watermark Register */
+ __I uint32_t CDETECT; /* Card Detect Register */
+ __I uint32_t WRTPRT; /* Write Protect Register */
+ __IO uint32_t GPIO; /* General Purpose Input/Output Register */
+ __I uint32_t TCBCNT; /* Transferred CIU Card Byte Count Register */
+ __I uint32_t TBBCNT; /* Transferred Host to BIU-FIFO Byte Count Register */
+ __IO uint32_t DEBNCE; /* Debounce Count Register */
+ __IO uint32_t USRID; /* User ID Register */
+ __I uint32_t VERID; /* Version ID Register */
+ __I uint32_t RESERVED0;
+ __IO uint32_t UHS_REG; /* UHS-1 Register */
+ __IO uint32_t RST_N; /* Hardware Reset */
+ __I uint32_t RESERVED1;
+ __IO uint32_t BMOD; /* Bus Mode Register */
+ __O uint32_t PLDMND; /* Poll Demand Register */
+ __IO uint32_t DBADDR; /* Descriptor List Base Address Register */
+ __IO uint32_t IDSTS; /* Internal DMAC Status Register */
+ __IO uint32_t IDINTEN; /* Internal DMAC Interrupt Enable Register */
+ __I uint32_t DSCADDR; /* Current Host Descriptor Address Register */
+ __I uint32_t BUFADDR; /* Current Buffer Descriptor Address Register */
} LPC_SDMMC_T;
-/**
- * @brief External Memory Controller (EMC) register block structure
+/* ---------------------------------------------------------------------------
+ * External Memory Controller (EMC) register block structure
*/
#define LPC_EMC_BASE 0x40005000
-typedef struct { /*!< EMC Structure */
- __IO uint32_t CONTROL; /*!< Controls operation of the memory controller. */
- __I uint32_t STATUS; /*!< Provides EMC status information. */
- __IO uint32_t CONFIG; /*!< Configures operation of the memory controller. */
- __I uint32_t RESERVED0[5];
- __IO uint32_t DYNAMICCONTROL; /*!< Controls dynamic memory operation. */
- __IO uint32_t DYNAMICREFRESH; /*!< Configures dynamic memory refresh operation. */
- __IO uint32_t DYNAMICREADCONFIG; /*!< Configures the dynamic memory read strategy. */
- __I uint32_t RESERVED1;
- __IO uint32_t DYNAMICRP; /*!< Selects the precharge command period. */
- __IO uint32_t DYNAMICRAS; /*!< Selects the active to precharge command period. */
- __IO uint32_t DYNAMICSREX; /*!< Selects the self-refresh exit time. */
- __IO uint32_t DYNAMICAPR; /*!< Selects the last-data-out to active command time. */
- __IO uint32_t DYNAMICDAL; /*!< Selects the data-in to active command time. */
- __IO uint32_t DYNAMICWR; /*!< Selects the write recovery time. */
- __IO uint32_t DYNAMICRC; /*!< Selects the active to active command period. */
- __IO uint32_t DYNAMICRFC; /*!< Selects the auto-refresh period. */
- __IO uint32_t DYNAMICXSR; /*!< Selects the exit self-refresh to active command time. */
- __IO uint32_t DYNAMICRRD; /*!< Selects the active bank A to active bank B latency. */
- __IO uint32_t DYNAMICMRD; /*!< Selects the load mode register to active command time. */
- __I uint32_t RESERVED2[9];
- __IO uint32_t STATICEXTENDEDWAIT; /*!< Selects time for long static memory read and write transfers. */
- __I uint32_t RESERVED3[31];
- __IO uint32_t DYNAMICCONFIG0; /*!< Selects the configuration information for dynamic memory chip select n. */
- __IO uint32_t DYNAMICRASCAS0; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
- __I uint32_t RESERVED4[6];
- __IO uint32_t DYNAMICCONFIG1; /*!< Selects the configuration information for dynamic memory chip select n. */
- __IO uint32_t DYNAMICRASCAS1; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
- __I uint32_t RESERVED5[6];
- __IO uint32_t DYNAMICCONFIG2; /*!< Selects the configuration information for dynamic memory chip select n. */
- __IO uint32_t DYNAMICRASCAS2; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
- __I uint32_t RESERVED6[6];
- __IO uint32_t DYNAMICCONFIG3; /*!< Selects the configuration information for dynamic memory chip select n. */
- __IO uint32_t DYNAMICRASCAS3; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
- __I uint32_t RESERVED7[38];
- __IO uint32_t STATICCONFIG0; /*!< Selects the memory configuration for static chip select n. */
- __IO uint32_t STATICWAITWEN0; /*!< Selects the delay from chip select n to write enable. */
- __IO uint32_t STATICWAITOEN0; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
- __IO uint32_t STATICWAITRD0; /*!< Selects the delay from chip select n to a read access. */
- __IO uint32_t STATICWAITPAG0; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
- __IO uint32_t STATICWAITWR0; /*!< Selects the delay from chip select n to a write access. */
- __IO uint32_t STATICWAITTURN0; /*!< Selects bus turnaround cycles */
- __I uint32_t RESERVED8;
- __IO uint32_t STATICCONFIG1; /*!< Selects the memory configuration for static chip select n. */
- __IO uint32_t STATICWAITWEN1; /*!< Selects the delay from chip select n to write enable. */
- __IO uint32_t STATICWAITOEN1; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
- __IO uint32_t STATICWAITRD1; /*!< Selects the delay from chip select n to a read access. */
- __IO uint32_t STATICWAITPAG1; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
- __IO uint32_t STATICWAITWR1; /*!< Selects the delay from chip select n to a write access. */
- __IO uint32_t STATICWAITTURN1; /*!< Selects bus turnaround cycles */
- __I uint32_t RESERVED9;
- __IO uint32_t STATICCONFIG2; /*!< Selects the memory configuration for static chip select n. */
- __IO uint32_t STATICWAITWEN2; /*!< Selects the delay from chip select n to write enable. */
- __IO uint32_t STATICWAITOEN2; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
- __IO uint32_t STATICWAITRD2; /*!< Selects the delay from chip select n to a read access. */
- __IO uint32_t STATICWAITPAG2; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
- __IO uint32_t STATICWAITWR2; /*!< Selects the delay from chip select n to a write access. */
- __IO uint32_t STATICWAITTURN2; /*!< Selects bus turnaround cycles */
- __I uint32_t RESERVED10;
- __IO uint32_t STATICCONFIG3; /*!< Selects the memory configuration for static chip select n. */
- __IO uint32_t STATICWAITWEN3; /*!< Selects the delay from chip select n to write enable. */
- __IO uint32_t STATICWAITOEN3; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
- __IO uint32_t STATICWAITRD3; /*!< Selects the delay from chip select n to a read access. */
- __IO uint32_t STATICWAITPAG3; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
- __IO uint32_t STATICWAITWR3; /*!< Selects the delay from chip select n to a write access. */
- __IO uint32_t STATICWAITTURN3; /*!< Selects bus turnaround cycles */
+typedef struct { /* EMC Structure */
+ __IO uint32_t CONTROL; /* Controls operation of the memory controller. */
+ __I uint32_t STATUS; /* Provides EMC status information. */
+ __IO uint32_t CONFIG; /* Configures operation of the memory controller. */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t DYNAMICCONTROL; /* Controls dynamic memory operation. */
+ __IO uint32_t DYNAMICREFRESH; /* Configures dynamic memory refresh operation. */
+ __IO uint32_t DYNAMICREADCONFIG; /* Configures the dynamic memory read strategy. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t DYNAMICRP; /* Selects the precharge command period. */
+ __IO uint32_t DYNAMICRAS; /* Selects the active to precharge command period. */
+ __IO uint32_t DYNAMICSREX; /* Selects the self-refresh exit time. */
+ __IO uint32_t DYNAMICAPR; /* Selects the last-data-out to active command time. */
+ __IO uint32_t DYNAMICDAL; /* Selects the data-in to active command time. */
+ __IO uint32_t DYNAMICWR; /* Selects the write recovery time. */
+ __IO uint32_t DYNAMICRC; /* Selects the active to active command period. */
+ __IO uint32_t DYNAMICRFC; /* Selects the auto-refresh period. */
+ __IO uint32_t DYNAMICXSR; /* Selects the exit self-refresh to active command time. */
+ __IO uint32_t DYNAMICRRD; /* Selects the active bank A to active bank B latency. */
+ __IO uint32_t DYNAMICMRD; /* Selects the load mode register to active command time. */
+ __I uint32_t RESERVED2[9];
+ __IO uint32_t STATICEXTENDEDWAIT; /* Selects time for long static memory read and write transfers. */
+ __I uint32_t RESERVED3[31];
+ __IO uint32_t DYNAMICCONFIG0; /* Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS0; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED4[6];
+ __IO uint32_t DYNAMICCONFIG1; /* Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS1; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED5[6];
+ __IO uint32_t DYNAMICCONFIG2; /* Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS2; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED6[6];
+ __IO uint32_t DYNAMICCONFIG3; /* Selects the configuration information for dynamic memory chip select n. */
+ __IO uint32_t DYNAMICRASCAS3; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
+ __I uint32_t RESERVED7[38];
+ __IO uint32_t STATICCONFIG0; /* Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN0; /* Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN0; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD0; /* Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG0; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR0; /* Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN0; /* Selects bus turnaround cycles */
+ __I uint32_t RESERVED8;
+ __IO uint32_t STATICCONFIG1; /* Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN1; /* Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN1; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD1; /* Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG1; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR1; /* Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN1; /* Selects bus turnaround cycles */
+ __I uint32_t RESERVED9;
+ __IO uint32_t STATICCONFIG2; /* Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN2; /* Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN2; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD2; /* Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG2; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR2; /* Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN2; /* Selects bus turnaround cycles */
+ __I uint32_t RESERVED10;
+ __IO uint32_t STATICCONFIG3; /* Selects the memory configuration for static chip select n. */
+ __IO uint32_t STATICWAITWEN3; /* Selects the delay from chip select n to write enable. */
+ __IO uint32_t STATICWAITOEN3; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
+ __IO uint32_t STATICWAITRD3; /* Selects the delay from chip select n to a read access. */
+ __IO uint32_t STATICWAITPAG3; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+ __IO uint32_t STATICWAITWR3; /* Selects the delay from chip select n to a write access. */
+ __IO uint32_t STATICWAITTURN3; /* Selects bus turnaround cycles */
} LPC_EMC_T;
-/**
- * @brief USB High-Speed register block structure
+/* ---------------------------------------------------------------------------
+ * USB High-Speed register block structure
*/
#define LPC_USB0_BASE 0x40006000
#define LPC_USB1_BASE 0x40007000
-typedef struct { /*!< USB Structure */
- __I uint32_t RESERVED0[64];
- __I uint32_t CAPLENGTH; /*!< Capability register length */
- __I uint32_t HCSPARAMS; /*!< Host controller structural parameters */
- __I uint32_t HCCPARAMS; /*!< Host controller capability parameters */
- __I uint32_t RESERVED1[5];
- __I uint32_t DCIVERSION; /*!< Device interface version number */
- __I uint32_t RESERVED2[7];
- union {
- __IO uint32_t USBCMD_H; /*!< USB command (host mode) */
- __IO uint32_t USBCMD_D; /*!< USB command (device mode) */
- };
+typedef struct { /* USB Structure */
+ __I uint32_t RESERVED0[64];
+ __I uint32_t CAPLENGTH; /* Capability register length */
+ __I uint32_t HCSPARAMS; /* Host controller structural parameters */
+ __I uint32_t HCCPARAMS; /* Host controller capability parameters */
+ __I uint32_t RESERVED1[5];
+ __I uint32_t DCIVERSION; /* Device interface version number */
+ __I uint32_t RESERVED2[7];
+ union {
+ __IO uint32_t USBCMD_H; /* USB command (host mode) */
+ __IO uint32_t USBCMD_D; /* USB command (device mode) */
+ };
- union {
- __IO uint32_t USBSTS_H; /*!< USB status (host mode) */
- __IO uint32_t USBSTS_D; /*!< USB status (device mode) */
- };
+ union {
+ __IO uint32_t USBSTS_H; /* USB status (host mode) */
+ __IO uint32_t USBSTS_D; /* USB status (device mode) */
+ };
- union {
- __IO uint32_t USBINTR_H; /*!< USB interrupt enable (host mode) */
- __IO uint32_t USBINTR_D; /*!< USB interrupt enable (device mode) */
- };
+ union {
+ __IO uint32_t USBINTR_H; /* USB interrupt enable (host mode) */
+ __IO uint32_t USBINTR_D; /* USB interrupt enable (device mode) */
+ };
- union {
- __IO uint32_t FRINDEX_H; /*!< USB frame index (host mode) */
- __I uint32_t FRINDEX_D; /*!< USB frame index (device mode) */
- };
+ union {
+ __IO uint32_t FRINDEX_H; /* USB frame index (host mode) */
+ __I uint32_t FRINDEX_D; /* USB frame index (device mode) */
+ };
- __I uint32_t RESERVED3;
- union {
- __IO uint32_t PERIODICLISTBASE; /*!< Frame list base address */
- __IO uint32_t DEVICEADDR; /*!< USB device address */
- };
+ __I uint32_t RESERVED3;
+ union {
+ __IO uint32_t PERIODICLISTBASE; /* Frame list base address */
+ __IO uint32_t DEVICEADDR; /* USB device address */
+ };
- union {
- __IO uint32_t ASYNCLISTADDR; /*!< Address of endpoint list in memory (host mode) */
- __IO uint32_t ENDPOINTLISTADDR; /*!< Address of endpoint list in memory (device mode) */
- };
+ union {
+ __IO uint32_t ASYNCLISTADDR; /* Address of endpoint list in memory (host mode) */
+ __IO uint32_t ENDPOINTLISTADDR; /* Address of endpoint list in memory (device mode) */
+ };
- __IO uint32_t TTCTRL; /*!< Asynchronous buffer status for embedded TT (host mode) */
- __IO uint32_t BURSTSIZE; /*!< Programmable burst size */
- __IO uint32_t TXFILLTUNING; /*!< Host transmit pre-buffer packet tuning (host mode) */
- __I uint32_t RESERVED4[2];
- __IO uint32_t ULPIVIEWPORT; /*!< ULPI viewport */
- __IO uint32_t BINTERVAL; /*!< Length of virtual frame */
- __IO uint32_t ENDPTNAK; /*!< Endpoint NAK (device mode) */
- __IO uint32_t ENDPTNAKEN; /*!< Endpoint NAK Enable (device mode) */
- __I uint32_t RESERVED5;
- union {
- __IO uint32_t PORTSC1_H; /*!< Port 1 status/control (host mode) */
- __IO uint32_t PORTSC1_D; /*!< Port 1 status/control (device mode) */
- };
+ __IO uint32_t TTCTRL; /* Asynchronous buffer status for embedded TT (host mode) */
+ __IO uint32_t BURSTSIZE; /* Programmable burst size */
+ __IO uint32_t TXFILLTUNING; /* Host transmit pre-buffer packet tuning (host mode) */
+ __I uint32_t RESERVED4[2];
+ __IO uint32_t ULPIVIEWPORT; /* ULPI viewport */
+ __IO uint32_t BINTERVAL; /* Length of virtual frame */
+ __IO uint32_t ENDPTNAK; /* Endpoint NAK (device mode) */
+ __IO uint32_t ENDPTNAKEN; /* Endpoint NAK Enable (device mode) */
+ __I uint32_t RESERVED5;
+ union {
+ __IO uint32_t PORTSC1_H; /* Port 1 status/control (host mode) */
+ __IO uint32_t PORTSC1_D; /* Port 1 status/control (device mode) */
+ };
- __I uint32_t RESERVED6[7];
- __IO uint32_t OTGSC; /*!< OTG status and control */
- union {
- __IO uint32_t USBMODE_H; /*!< USB mode (host mode) */
- __IO uint32_t USBMODE_D; /*!< USB mode (device mode) */
- };
+ __I uint32_t RESERVED6[7];
+ __IO uint32_t OTGSC; /* OTG status and control */
+ union {
+ __IO uint32_t USBMODE_H; /* USB mode (host mode) */
+ __IO uint32_t USBMODE_D; /* USB mode (device mode) */
+ };
- __IO uint32_t ENDPTSETUPSTAT; /*!< Endpoint setup status */
- __IO uint32_t ENDPTPRIME; /*!< Endpoint initialization */
- __IO uint32_t ENDPTFLUSH; /*!< Endpoint de-initialization */
- __I uint32_t ENDPTSTAT; /*!< Endpoint status */
- __IO uint32_t ENDPTCOMPLETE; /*!< Endpoint complete */
- __IO uint32_t ENDPTCTRL[6]; /*!< Endpoint control 0 */
+ __IO uint32_t ENDPTSETUPSTAT; /* Endpoint setup status */
+ __IO uint32_t ENDPTPRIME; /* Endpoint initialization */
+ __IO uint32_t ENDPTFLUSH; /* Endpoint de-initialization */
+ __I uint32_t ENDPTSTAT; /* Endpoint status */
+ __IO uint32_t ENDPTCOMPLETE; /* Endpoint complete */
+ __IO uint32_t ENDPTCTRL[6]; /* Endpoint control 0 */
} LPC_USBHS_T;
-/**
- * @brief LCD Controller register block structure
+/* ---------------------------------------------------------------------------
+ * LCD Controller register block structure
*/
#define LPC_LCD_BASE 0x40008000
-typedef struct { /*!< LCD Structure */
- __IO uint32_t TIMH; /*!< Horizontal Timing Control register */
- __IO uint32_t TIMV; /*!< Vertical Timing Control register */
- __IO uint32_t POL; /*!< Clock and Signal Polarity Control register */
- __IO uint32_t LE; /*!< Line End Control register */
- __IO uint32_t UPBASE; /*!< Upper Panel Frame Base Address register */
- __IO uint32_t LPBASE; /*!< Lower Panel Frame Base Address register */
- __IO uint32_t CTRL; /*!< LCD Control register */
- __IO uint32_t INTMSK; /*!< Interrupt Mask register */
- __I uint32_t INTRAW; /*!< Raw Interrupt Status register */
- __I uint32_t INTSTAT; /*!< Masked Interrupt Status register */
- __O uint32_t INTCLR; /*!< Interrupt Clear register */
- __I uint32_t UPCURR; /*!< Upper Panel Current Address Value register */
- __I uint32_t LPCURR; /*!< Lower Panel Current Address Value register */
- __I uint32_t RESERVED0[115];
- __IO uint16_t PAL[256]; /*!< 256x16-bit Color Palette registers */
- __I uint32_t RESERVED1[256];
- __IO uint32_t CRSR_IMG[256];/*!< Cursor Image registers */
- __IO uint32_t CRSR_CTRL; /*!< Cursor Control register */
- __IO uint32_t CRSR_CFG; /*!< Cursor Configuration register */
- __IO uint32_t CRSR_PAL0; /*!< Cursor Palette register 0 */
- __IO uint32_t CRSR_PAL1; /*!< Cursor Palette register 1 */
- __IO uint32_t CRSR_XY; /*!< Cursor XY Position register */
- __IO uint32_t CRSR_CLIP; /*!< Cursor Clip Position register */
- __I uint32_t RESERVED2[2];
- __IO uint32_t CRSR_INTMSK; /*!< Cursor Interrupt Mask register */
- __O uint32_t CRSR_INTCLR; /*!< Cursor Interrupt Clear register */
- __I uint32_t CRSR_INTRAW; /*!< Cursor Raw Interrupt Status register */
- __I uint32_t CRSR_INTSTAT;/*!< Cursor Masked Interrupt Status register */
+typedef struct { /* LCD Structure */
+ __IO uint32_t TIMH; /* Horizontal Timing Control register */
+ __IO uint32_t TIMV; /* Vertical Timing Control register */
+ __IO uint32_t POL; /* Clock and Signal Polarity Control register */
+ __IO uint32_t LE; /* Line End Control register */
+ __IO uint32_t UPBASE; /* Upper Panel Frame Base Address register */
+ __IO uint32_t LPBASE; /* Lower Panel Frame Base Address register */
+ __IO uint32_t CTRL; /* LCD Control register */
+ __IO uint32_t INTMSK; /* Interrupt Mask register */
+ __I uint32_t INTRAW; /* Raw Interrupt Status register */
+ __I uint32_t INTSTAT; /* Masked Interrupt Status register */
+ __O uint32_t INTCLR; /* Interrupt Clear register */
+ __I uint32_t UPCURR; /* Upper Panel Current Address Value register */
+ __I uint32_t LPCURR; /* Lower Panel Current Address Value register */
+ __I uint32_t RESERVED0[115];
+ __IO uint16_t PAL[256]; /* 256x16-bit Color Palette registers */
+ __I uint32_t RESERVED1[256];
+ __IO uint32_t CRSR_IMG[256];/* Cursor Image registers */
+ __IO uint32_t CRSR_CTRL; /* Cursor Control register */
+ __IO uint32_t CRSR_CFG; /* Cursor Configuration register */
+ __IO uint32_t CRSR_PAL0; /* Cursor Palette register 0 */
+ __IO uint32_t CRSR_PAL1; /* Cursor Palette register 1 */
+ __IO uint32_t CRSR_XY; /* Cursor XY Position register */
+ __IO uint32_t CRSR_CLIP; /* Cursor Clip Position register */
+ __I uint32_t RESERVED2[2];
+ __IO uint32_t CRSR_INTMSK; /* Cursor Interrupt Mask register */
+ __O uint32_t CRSR_INTCLR; /* Cursor Interrupt Clear register */
+ __I uint32_t CRSR_INTRAW; /* Cursor Raw Interrupt Status register */
+ __I uint32_t CRSR_INTSTAT;/* Cursor Masked Interrupt Status register */
} LPC_LCD_T;
-/**
- * @brief EEPROM register block structure
+/* ---------------------------------------------------------------------------
+ * EEPROM register block structure
*/
#define LPC_EEPROM_BASE 0x4000E000
-typedef struct { /* EEPROM Structure */
- __IO uint32_t CMD; /*!< EEPROM command register */
- uint32_t RESERVED0;
- __IO uint32_t RWSTATE; /*!< EEPROM read wait state register */
- __IO uint32_t AUTOPROG; /*!< EEPROM auto programming register */
- __IO uint32_t WSTATE; /*!< EEPROM wait state register */
- __IO uint32_t CLKDIV; /*!< EEPROM clock divider register */
- __IO uint32_t PWRDWN; /*!< EEPROM power-down register */
- uint32_t RESERVED2[1007];
- __O uint32_t INTENCLR; /*!< EEPROM interrupt enable clear */
- __O uint32_t INTENSET; /*!< EEPROM interrupt enable set */
- __I uint32_t INTSTAT; /*!< EEPROM interrupt status */
- __I uint32_t INTEN; /*!< EEPROM interrupt enable */
- __O uint32_t INTSTATCLR; /*!< EEPROM interrupt status clear */
- __O uint32_t INTSTATSET; /*!< EEPROM interrupt status set */
+typedef struct { /* EEPROM Structure */
+ __IO uint32_t CMD; /* EEPROM command register */
+ uint32_t RESERVED0;
+ __IO uint32_t RWSTATE; /* EEPROM read wait state register */
+ __IO uint32_t AUTOPROG; /* EEPROM auto programming register */
+ __IO uint32_t WSTATE; /* EEPROM wait state register */
+ __IO uint32_t CLKDIV; /* EEPROM clock divider register */
+ __IO uint32_t PWRDWN; /* EEPROM power-down register */
+ uint32_t RESERVED2[1007];
+ __O uint32_t INTENCLR; /* EEPROM interrupt enable clear */
+ __O uint32_t INTENSET; /* EEPROM interrupt enable set */
+ __I uint32_t INTSTAT; /* EEPROM interrupt status */
+ __I uint32_t INTEN; /* EEPROM interrupt enable */
+ __O uint32_t INTSTATCLR; /* EEPROM interrupt status clear */
+ __O uint32_t INTSTATSET; /* EEPROM interrupt status set */
} LPC_EEPROM_T;
-/**
- * @brief 10/100 MII & RMII Ethernet with timestamping register block structure
+/* ---------------------------------------------------------------------------
+ * 10/100 MII & RMII Ethernet with timestamping register block structure
*/
#define LPC_ETHERNET_BASE 0x40010000
-typedef struct { /*!< ETHERNET Structure */
- __IO uint32_t MAC_CONFIG; /*!< MAC configuration register */
- __IO uint32_t MAC_FRAME_FILTER; /*!< MAC frame filter */
- __IO uint32_t MAC_HASHTABLE_HIGH; /*!< Hash table high register */
- __IO uint32_t MAC_HASHTABLE_LOW; /*!< Hash table low register */
- __IO uint32_t MAC_MII_ADDR; /*!< MII address register */
- __IO uint32_t MAC_MII_DATA; /*!< MII data register */
- __IO uint32_t MAC_FLOW_CTRL; /*!< Flow control register */
- __IO uint32_t MAC_VLAN_TAG; /*!< VLAN tag register */
- __I uint32_t RESERVED0;
- __I uint32_t MAC_DEBUG; /*!< Debug register */
- __IO uint32_t MAC_RWAKE_FRFLT; /*!< Remote wake-up frame filter */
- __IO uint32_t MAC_PMT_CTRL_STAT; /*!< PMT control and status */
- __I uint32_t RESERVED1[2];
- __I uint32_t MAC_INTR; /*!< Interrupt status register */
- __IO uint32_t MAC_INTR_MASK; /*!< Interrupt mask register */
- __IO uint32_t MAC_ADDR0_HIGH; /*!< MAC address 0 high register */
- __IO uint32_t MAC_ADDR0_LOW; /*!< MAC address 0 low register */
- __I uint32_t RESERVED2[430];
- __IO uint32_t MAC_TIMESTP_CTRL; /*!< Time stamp control register */
- __IO uint32_t SUBSECOND_INCR; /*!< Sub-second increment register */
- __I uint32_t SECONDS; /*!< System time seconds register */
- __I uint32_t NANOSECONDS; /*!< System time nanoseconds register */
- __IO uint32_t SECONDSUPDATE; /*!< System time seconds update register */
- __IO uint32_t NANOSECONDSUPDATE; /*!< System time nanoseconds update register */
- __IO uint32_t ADDEND; /*!< Time stamp addend register */
- __IO uint32_t TARGETSECONDS; /*!< Target time seconds register */
- __IO uint32_t TARGETNANOSECONDS; /*!< Target time nanoseconds register */
- __IO uint32_t HIGHWORD; /*!< System time higher word seconds register */
- __I uint32_t TIMESTAMPSTAT; /*!< Time stamp status register */
- __IO uint32_t PPSCTRL; /*!< PPS control register */
- __I uint32_t AUXNANOSECONDS; /*!< Auxiliary time stamp nanoseconds register */
- __I uint32_t AUXSECONDS; /*!< Auxiliary time stamp seconds register */
- __I uint32_t RESERVED3[562];
- __IO uint32_t DMA_BUS_MODE; /*!< Bus Mode Register */
- __IO uint32_t DMA_TRANS_POLL_DEMAND; /*!< Transmit poll demand register */
- __IO uint32_t DMA_REC_POLL_DEMAND; /*!< Receive poll demand register */
- __IO uint32_t DMA_REC_DES_ADDR; /*!< Receive descriptor list address register */
- __IO uint32_t DMA_TRANS_DES_ADDR; /*!< Transmit descriptor list address register */
- __IO uint32_t DMA_STAT; /*!< Status register */
- __IO uint32_t DMA_OP_MODE; /*!< Operation mode register */
- __IO uint32_t DMA_INT_EN; /*!< Interrupt enable register */
- __I uint32_t DMA_MFRM_BUFOF; /*!< Missed frame and buffer overflow register */
- __IO uint32_t DMA_REC_INT_WDT; /*!< Receive interrupt watchdog timer register */
- __I uint32_t RESERVED4[8];
- __I uint32_t DMA_CURHOST_TRANS_DES; /*!< Current host transmit descriptor register */
- __I uint32_t DMA_CURHOST_REC_DES; /*!< Current host receive descriptor register */
- __I uint32_t DMA_CURHOST_TRANS_BUF; /*!< Current host transmit buffer address register */
- __I uint32_t DMA_CURHOST_REC_BUF; /*!< Current host receive buffer address register */
+typedef struct { /* ETHERNET Structure */
+ __IO uint32_t MAC_CONFIG; /* MAC configuration register */
+ __IO uint32_t MAC_FRAME_FILTER; /* MAC frame filter */
+ __IO uint32_t MAC_HASHTABLE_HIGH; /* Hash table high register */
+ __IO uint32_t MAC_HASHTABLE_LOW; /* Hash table low register */
+ __IO uint32_t MAC_MII_ADDR; /* MII address register */
+ __IO uint32_t MAC_MII_DATA; /* MII data register */
+ __IO uint32_t MAC_FLOW_CTRL; /* Flow control register */
+ __IO uint32_t MAC_VLAN_TAG; /* VLAN tag register */
+ __I uint32_t RESERVED0;
+ __I uint32_t MAC_DEBUG; /* Debug register */
+ __IO uint32_t MAC_RWAKE_FRFLT; /* Remote wake-up frame filter */
+ __IO uint32_t MAC_PMT_CTRL_STAT; /* PMT control and status */
+ __I uint32_t RESERVED1[2];
+ __I uint32_t MAC_INTR; /* Interrupt status register */
+ __IO uint32_t MAC_INTR_MASK; /* Interrupt mask register */
+ __IO uint32_t MAC_ADDR0_HIGH; /* MAC address 0 high register */
+ __IO uint32_t MAC_ADDR0_LOW; /* MAC address 0 low register */
+ __I uint32_t RESERVED2[430];
+ __IO uint32_t MAC_TIMESTP_CTRL; /* Time stamp control register */
+ __IO uint32_t SUBSECOND_INCR; /* Sub-second increment register */
+ __I uint32_t SECONDS; /* System time seconds register */
+ __I uint32_t NANOSECONDS; /* System time nanoseconds register */
+ __IO uint32_t SECONDSUPDATE; /* System time seconds update register */
+ __IO uint32_t NANOSECONDSUPDATE; /* System time nanoseconds update register */
+ __IO uint32_t ADDEND; /* Time stamp addend register */
+ __IO uint32_t TARGETSECONDS; /* Target time seconds register */
+ __IO uint32_t TARGETNANOSECONDS; /* Target time nanoseconds register */
+ __IO uint32_t HIGHWORD; /* System time higher word seconds register */
+ __I uint32_t TIMESTAMPSTAT; /* Time stamp status register */
+ __IO uint32_t PPSCTRL; /* PPS control register */
+ __I uint32_t AUXNANOSECONDS; /* Auxiliary time stamp nanoseconds register */
+ __I uint32_t AUXSECONDS; /* Auxiliary time stamp seconds register */
+ __I uint32_t RESERVED3[562];
+ __IO uint32_t DMA_BUS_MODE; /* Bus Mode Register */
+ __IO uint32_t DMA_TRANS_POLL_DEMAND; /* Transmit poll demand register */
+ __IO uint32_t DMA_REC_POLL_DEMAND; /* Receive poll demand register */
+ __IO uint32_t DMA_REC_DES_ADDR; /* Receive descriptor list address register */
+ __IO uint32_t DMA_TRANS_DES_ADDR; /* Transmit descriptor list address register */
+ __IO uint32_t DMA_STAT; /* Status register */
+ __IO uint32_t DMA_OP_MODE; /* Operation mode register */
+ __IO uint32_t DMA_INT_EN; /* Interrupt enable register */
+ __I uint32_t DMA_MFRM_BUFOF; /* Missed frame and buffer overflow register */
+ __IO uint32_t DMA_REC_INT_WDT; /* Receive interrupt watchdog timer register */
+ __I uint32_t RESERVED4[8];
+ __I uint32_t DMA_CURHOST_TRANS_DES; /* Current host transmit descriptor register */
+ __I uint32_t DMA_CURHOST_REC_DES; /* Current host receive descriptor register */
+ __I uint32_t DMA_CURHOST_TRANS_BUF; /* Current host transmit buffer address register */
+ __I uint32_t DMA_CURHOST_REC_BUF; /* Current host receive buffer address register */
} LPC_ENET_T;
-/**
- * @brief Alarm Timer register block structure
+/* ---------------------------------------------------------------------------
+ * Alarm Timer register block structure
*/
#define LPC_ATIMER_BASE 0x40040000
-typedef struct { /*!< ATIMER Structure */
- __IO uint32_t DOWNCOUNTER; /*!< Downcounter register */
- __IO uint32_t PRESET; /*!< Preset value register */
- __I uint32_t RESERVED0[1012];
- __O uint32_t CLR_EN; /*!< Interrupt clear enable register */
- __O uint32_t SET_EN; /*!< Interrupt set enable register */
- __I uint32_t STATUS; /*!< Status register */
- __I uint32_t ENABLE; /*!< Enable register */
- __O uint32_t CLR_STAT; /*!< Clear register */
- __O uint32_t SET_STAT; /*!< Set register */
+typedef struct { /* ATIMER Structure */
+ __IO uint32_t DOWNCOUNTER; /* Downcounter register */
+ __IO uint32_t PRESET; /* Preset value register */
+ __I uint32_t RESERVED0[1012];
+ __O uint32_t CLR_EN; /* Interrupt clear enable register */
+ __O uint32_t SET_EN; /* Interrupt set enable register */
+ __I uint32_t STATUS; /* Status register */
+ __I uint32_t ENABLE; /* Enable register */
+ __O uint32_t CLR_STAT; /* Clear register */
+ __O uint32_t SET_STAT; /* Set register */
} LPC_ATIMER_T;
-/**
- * @brief Register File register block structure
+/* ---------------------------------------------------------------------------
+ * Register File register block structure
*/
#define LPC_REGFILE_BASE 0x40041000
typedef struct {
- __IO uint32_t REGFILE[64]; /*!< General purpose storage register */
+ __IO uint32_t REGFILE[64]; /* General purpose storage register */
} LPC_REGFILE_T;
-/**
- * @brief Power Management Controller register block structure
+/* ---------------------------------------------------------------------------
+ * Power Management Controller register block structure
*/
#define LPC_PMC_BASE 0x40042000
-typedef struct { /*!< PMC Structure */
- __IO uint32_t PD0_SLEEP0_HW_ENA; /*!< Hardware sleep event enable register */
- __I uint32_t RESERVED0[6];
- __IO uint32_t PD0_SLEEP0_MODE; /*!< Sleep power mode register */
+typedef struct { /* PMC Structure */
+ __IO uint32_t PD0_SLEEP0_HW_ENA; /* Hardware sleep event enable register */
+ __I uint32_t RESERVED0[6];
+ __IO uint32_t PD0_SLEEP0_MODE; /* Sleep power mode register */
} LPC_PMC_T;
-/**
- * @brief CREG Register Block
+/* ---------------------------------------------------------------------------
+ * CREG Register Block
*/
#define LPC_CREG_BASE 0x40043000
-typedef struct { /*!< CREG Structure */
- __I uint32_t RESERVED0;
- __IO uint32_t CREG0; /*!< Chip configuration register 32 kHz oscillator output and BOD control register. */
- __I uint32_t RESERVED1[62];
- __IO uint32_t MXMEMMAP; /*!< ARM Cortex-M3/M4 memory mapping */
+typedef struct { /* CREG Structure */
+ __I uint32_t RESERVED0;
+ __IO uint32_t CREG0; /* Chip configuration register 32 kHz oscillator output and BOD control register. */
+ __I uint32_t RESERVED1[62];
+ __IO uint32_t MXMEMMAP; /* ARM Cortex-M3/M4 memory mapping */
#if defined(CHIP_LPC18XX)
- __I uint32_t RESERVED2[5];
+ __I uint32_t RESERVED2[5];
#else
- __I uint32_t RESERVED2;
- __I uint32_t CREG1; /*!< Configuration Register 1 */
- __I uint32_t CREG2; /*!< Configuration Register 2 */
- __I uint32_t CREG3; /*!< Configuration Register 3 */
- __I uint32_t CREG4; /*!< Configuration Register 4 */
+ __I uint32_t RESERVED2;
+ __I uint32_t CREG1; /* Configuration Register 1 */
+ __I uint32_t CREG2; /* Configuration Register 2 */
+ __I uint32_t CREG3; /* Configuration Register 3 */
+ __I uint32_t CREG4; /* Configuration Register 4 */
#endif
- __IO uint32_t CREG5; /*!< Chip configuration register 5. Controls JTAG access. */
- __IO uint32_t DMAMUX; /*!< DMA muxing control */
- __IO uint32_t FLASHCFGA; /*!< Flash accelerator configuration register for flash bank A */
- __IO uint32_t FLASHCFGB; /*!< Flash accelerator configuration register for flash bank B */
- __IO uint32_t ETBCFG; /*!< ETB RAM configuration */
- __IO uint32_t CREG6; /*!< Chip configuration register 6. */
+ __IO uint32_t CREG5; /* Chip configuration register 5. Controls JTAG access. */
+ __IO uint32_t DMAMUX; /* DMA muxing control */
+ __IO uint32_t FLASHCFGA; /* Flash accelerator configuration register for flash bank A */
+ __IO uint32_t FLASHCFGB; /* Flash accelerator configuration register for flash bank B */
+ __IO uint32_t ETBCFG; /* ETB RAM configuration */
+ __IO uint32_t CREG6; /* Chip configuration register 6. */
#if defined(CHIP_LPC18XX)
- __I uint32_t RESERVED4[52];
+ __I uint32_t RESERVED4[52];
#else
- __IO uint32_t M4TXEVENT; /*!< M4 IPC event register */
- __I uint32_t RESERVED4[51];
+ __IO uint32_t M4TXEVENT; /* M4 IPC event register */
+ __I uint32_t RESERVED4[51];
#endif
- __I uint32_t CHIPID; /*!< Part ID */
+ __I uint32_t CHIPID; /* Part ID */
#if defined(CHIP_LPC18XX)
- __I uint32_t RESERVED5[191];
+ __I uint32_t RESERVED5[191];
#else
- __I uint32_t RESERVED5[127];
- __IO uint32_t M0TXEVENT; /*!< M0 IPC Event register */
- __IO uint32_t M0APPMEMMAP; /*!< ARM Cortex M0 memory mapping */
- __I uint32_t RESERVED6[62];
+ __I uint32_t RESERVED5[127];
+ __IO uint32_t M0TXEVENT; /* M0 IPC Event register */
+ __IO uint32_t M0APPMEMMAP; /* ARM Cortex M0 memory mapping */
+ __I uint32_t RESERVED6[62];
#endif
- __IO uint32_t USB0FLADJ; /*!< USB0 frame length adjust register */
- __I uint32_t RESERVED7[63];
- __IO uint32_t USB1FLADJ; /*!< USB1 frame length adjust register */
+ __IO uint32_t USB0FLADJ; /* USB0 frame length adjust register */
+ __I uint32_t RESERVED7[63];
+ __IO uint32_t USB1FLADJ; /* USB1 frame length adjust register */
} LPC_CREG_T;
-/**
- * @brief Event Router register structure
+/* ---------------------------------------------------------------------------
+ * Event Router register structure
*/
#define LPC_EVRT_BASE 0x40044000
-typedef struct { /*!< EVENTROUTER Structure */
- __IO uint32_t HILO; /*!< Level configuration register */
- __IO uint32_t EDGE; /*!< Edge configuration */
- __I uint32_t RESERVED0[1012];
- __O uint32_t CLR_EN; /*!< Event clear enable register */
- __O uint32_t SET_EN; /*!< Event set enable register */
- __I uint32_t STATUS; /*!< Status register */
- __I uint32_t ENABLE; /*!< Enable register */
- __O uint32_t CLR_STAT; /*!< Clear register */
- __O uint32_t SET_STAT; /*!< Set register */
+typedef struct { /* EVENTROUTER Structure */
+ __IO uint32_t HILO; /* Level configuration register */
+ __IO uint32_t EDGE; /* Edge configuration */
+ __I uint32_t RESERVED0[1012];
+ __O uint32_t CLR_EN; /* Event clear enable register */
+ __O uint32_t SET_EN; /* Event set enable register */
+ __I uint32_t STATUS; /* Status register */
+ __I uint32_t ENABLE; /* Enable register */
+ __O uint32_t CLR_STAT; /* Clear register */
+ __O uint32_t SET_STAT; /* Set register */
} LPC_EVRT_T;
-/**
- * @brief Real Time Clock register block structure
+/* ---------------------------------------------------------------------------
+ * Real Time Clock register block structure
*/
#define LPC_RTC_BASE 0x40046000
-#define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
+#define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
-typedef enum IP_RTC_TIMEINDEX {
- RTC_TIMETYPE_SECOND, /*!< Second */
- RTC_TIMETYPE_MINUTE, /*!< Month */
- RTC_TIMETYPE_HOUR, /*!< Hour */
- RTC_TIMETYPE_DAYOFMONTH, /*!< Day of month */
- RTC_TIMETYPE_DAYOFWEEK, /*!< Day of week */
- RTC_TIMETYPE_DAYOFYEAR, /*!< Day of year */
- RTC_TIMETYPE_MONTH, /*!< Month */
- RTC_TIMETYPE_YEAR, /*!< Year */
- RTC_TIMETYPE_LAST
-} IP_RTC_TIMEINDEX_T;
+typedef enum RTC_TIMEINDEX {
+ RTC_TIMETYPE_SECOND, /* Second */
+ RTC_TIMETYPE_MINUTE, /* Month */
+ RTC_TIMETYPE_HOUR, /* Hour */
+ RTC_TIMETYPE_DAYOFMONTH, /* Day of month */
+ RTC_TIMETYPE_DAYOFWEEK, /* Day of week */
+ RTC_TIMETYPE_DAYOFYEAR, /* Day of year */
+ RTC_TIMETYPE_MONTH, /* Month */
+ RTC_TIMETYPE_YEAR, /* Year */
+ RTC_TIMETYPE_LAST
+} RTC_TIMEINDEX_T;
#if RTC_EV_SUPPORT
typedef enum LPC_RTC_EV_CHANNEL {
- RTC_EV_CHANNEL_1 = 0,
- RTC_EV_CHANNEL_2,
- RTC_EV_CHANNEL_3,
- RTC_EV_CHANNEL_NUM,
+ RTC_EV_CHANNEL_1 = 0,
+ RTC_EV_CHANNEL_2,
+ RTC_EV_CHANNEL_3,
+ RTC_EV_CHANNEL_NUM,
} LPC_RTC_EV_CHANNEL_T;
#endif /*RTC_EV_SUPPORT*/
-typedef struct { /*!< RTC Structure */
- __IO uint32_t ILR; /*!< Interrupt Location Register */
- __I uint32_t RESERVED0;
- __IO uint32_t CCR; /*!< Clock Control Register */
- __IO uint32_t CIIR; /*!< Counter Increment Interrupt Register */
- __IO uint32_t AMR; /*!< Alarm Mask Register */
- __I uint32_t CTIME[3]; /*!< Consolidated Time Register 0,1,2 */
- __IO uint32_t TIME[RTC_TIMETYPE_LAST]; /*!< Timer field registers */
- __IO uint32_t CALIBRATION; /*!< Calibration Value Register */
- __I uint32_t RESERVED1[7];
- __IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /*!< Alarm field registers */
+typedef struct { /* RTC Structure */
+ __IO uint32_t ILR; /* Interrupt Location Register */
+ __I uint32_t RESERVED0;
+ __IO uint32_t CCR; /* Clock Control Register */
+ __IO uint32_t CIIR; /* Counter Increment Interrupt Register */
+ __IO uint32_t AMR; /* Alarm Mask Register */
+ __I uint32_t CTIME[3]; /* Consolidated Time Register 0,1,2 */
+ __IO uint32_t TIME[RTC_TIMETYPE_LAST]; /* Timer field registers */
+ __IO uint32_t CALIBRATION; /* Calibration Value Register */
+ __I uint32_t RESERVED1[7];
+ __IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /* Alarm field registers */
#if RTC_EV_SUPPORT
- __IO uint32_t ERSTATUS; /*!< Event Monitor/Recorder Status register*/
- __IO uint32_t ERCONTROL; /*!< Event Monitor/Recorder Control register*/
- __I uint32_t ERCOUNTERS; /*!< Event Monitor/Recorder Counters register*/
- __I uint32_t RESERVED2;
- __I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /*!<Event Monitor/Recorder First Stamp registers*/
- __I uint32_t RESERVED3;
- __I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /*!<Event Monitor/Recorder Last Stamp registers*/
+ __IO uint32_t ERSTATUS; /* Event Monitor/Recorder Status register*/
+ __IO uint32_t ERCONTROL; /* Event Monitor/Recorder Control register*/
+ __I uint32_t ERCOUNTERS; /* Event Monitor/Recorder Counters register*/
+ __I uint32_t RESERVED2;
+ __I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder First Stamp registers*/
+ __I uint32_t RESERVED3;
+ __I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder Last Stamp registers*/
#endif /*RTC_EV_SUPPORT*/
} LPC_RTC_T;
-/**
- * @brief LPC18XX/43XX CGU register block structure
+/* ---------------------------------------------------------------------------
+ * LPC18XX/43XX CGU register block structure
*/
#define LPC_CGU_BASE 0x40050000
#define LPC_CCU1_BASE 0x40051000
#define LPC_CCU2_BASE 0x40052000
-/**
- * These are possible input clocks for the CGU and can come
- * from both external (crystal) and internal (PLL) sources. These
- * clock inputs can be routed to the base clocks (@ref CGU_BASE_CLK_T).
+/*
+ * Input clocks for the CGU and can come from both external (crystal) and
+ * internal (PLL) sources. Can be routed to the base clocks.
*/
typedef enum CGU_CLKIN {
- CLKIN_32K, /*!< External 32KHz input */
- CLKIN_IRC, /*!< Internal IRC (12MHz) input */
- CLKIN_ENET_RX, /*!< External ENET_RX pin input */
- CLKIN_ENET_TX, /*!< External ENET_TX pin input */
- CLKIN_CLKIN, /*!< External GPCLKIN pin input */
- CLKIN_RESERVED1,
- CLKIN_CRYSTAL, /*!< External (main) crystal pin input */
- CLKIN_USBPLL, /*!< Internal USB PLL input */
- CLKIN_AUDIOPLL, /*!< Internal Audio PLL input */
- CLKIN_MAINPLL, /*!< Internal Main PLL input */
- CLKIN_RESERVED2,
- CLKIN_RESERVED3,
- CLKIN_IDIVA, /*!< Internal divider A input */
- CLKIN_IDIVB, /*!< Internal divider B input */
- CLKIN_IDIVC, /*!< Internal divider C input */
- CLKIN_IDIVD, /*!< Internal divider D input */
- CLKIN_IDIVE, /*!< Internal divider E input */
- CLKINPUT_PD /*!< External 32KHz input */
+ CLKIN_32K, /* External 32KHz input */
+ CLKIN_IRC, /* Internal IRC (12MHz) input */
+ CLKIN_ENET_RX, /* External ENET_RX pin input */
+ CLKIN_ENET_TX, /* External ENET_TX pin input */
+ CLKIN_CLKIN, /* External GPCLKIN pin input */
+ CLKIN_RESERVED1,
+ CLKIN_CRYSTAL, /* External (main) crystal pin input */
+ CLKIN_USBPLL, /* Internal USB PLL input */
+ CLKIN_AUDIOPLL, /* Internal Audio PLL input */
+ CLKIN_MAINPLL, /* Internal Main PLL input */
+ CLKIN_RESERVED2,
+ CLKIN_RESERVED3,
+ CLKIN_IDIVA, /* Internal divider A input */
+ CLKIN_IDIVB, /* Internal divider B input */
+ CLKIN_IDIVC, /* Internal divider C input */
+ CLKIN_IDIVD, /* Internal divider D input */
+ CLKIN_IDIVE, /* Internal divider E input */
+ CLKINPUT_PD /* External 32KHz input */
} CGU_CLKIN_T;
#define CLKIN_PLL0USB CLKIN_USBPLL
#define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
#define CLKIN_PLL1 CLKIN_MAINPLL
-/**
+/*
* CGU base clocks are clocks that are associated with a single input clock
* and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
* clock can be configured to use the CLKIN_MAINPLL input clock, which will in
@@ -982,51 +1040,51 @@
* CLK_PERIPH_SGPIO periphral clocks.
*/
typedef enum CGU_BASE_CLK {
- CLK_BASE_SAFE, /*!< Base clock for WDT oscillator, IRC input only */
- CLK_BASE_USB0, /*!< Base USB clock for USB0, USB PLL input only */
+ CLK_BASE_SAFE, /* Base clock for WDT oscillator, IRC input only */
+ CLK_BASE_USB0, /* Base USB clock for USB0, USB PLL input only */
#if defined(CHIP_LPC43XX)
- CLK_BASE_PERIPH, /*!< Base clock for SGPIO */
+ CLK_BASE_PERIPH, /* Base clock for SGPIO */
#else
- CLK_BASE_RESERVED1,
+ CLK_BASE_RESERVED1,
#endif
- CLK_BASE_USB1, /*!< Base USB clock for USB1 */
- CLK_BASE_MX, /*!< Base clock for CPU core */
- CLK_BASE_SPIFI, /*!< Base clock for SPIFI */
+ CLK_BASE_USB1, /* Base USB clock for USB1 */
+ CLK_BASE_MX, /* Base clock for CPU core */
+ CLK_BASE_SPIFI, /* Base clock for SPIFI */
#if defined(CHIP_LPC43XX)
- CLK_BASE_SPI, /*!< Base clock for SPI */
+ CLK_BASE_SPI, /* Base clock for SPI */
#else
- CLK_BASE_RESERVED2,
+ CLK_BASE_RESERVED2,
#endif
- CLK_BASE_PHY_RX, /*!< Base clock for PHY RX */
- CLK_BASE_PHY_TX, /*!< Base clock for PHY TX */
- CLK_BASE_APB1, /*!< Base clock for APB1 group */
- CLK_BASE_APB3, /*!< Base clock for APB3 group */
- CLK_BASE_LCD, /*!< Base clock for LCD pixel clock */
+ CLK_BASE_PHY_RX, /* Base clock for PHY RX */
+ CLK_BASE_PHY_TX, /* Base clock for PHY TX */
+ CLK_BASE_APB1, /* Base clock for APB1 group */
+ CLK_BASE_APB3, /* Base clock for APB3 group */
+ CLK_BASE_LCD, /* Base clock for LCD pixel clock */
#if defined(CHIP_LPC43XX)
- CLK_BASE_VADC, /*!< Base clock for VADC */
+ CLK_BASE_VADC, /* Base clock for VADC */
#else
- CLK_BASE_RESERVED3,
+ CLK_BASE_RESERVED3,
#endif
- CLK_BASE_SDIO, /*!< Base clock for SDIO */
- CLK_BASE_SSP0, /*!< Base clock for SSP0 */
- CLK_BASE_SSP1, /*!< Base clock for SSP1 */
- CLK_BASE_UART0, /*!< Base clock for UART0 */
- CLK_BASE_UART1, /*!< Base clock for UART1 */
- CLK_BASE_UART2, /*!< Base clock for UART2 */
- CLK_BASE_UART3, /*!< Base clock for UART3 */
- CLK_BASE_OUT, /*!< Base clock for CLKOUT pin */
- CLK_BASE_RESERVED4,
- CLK_BASE_RESERVED5,
- CLK_BASE_RESERVED6,
- CLK_BASE_RESERVED7,
- CLK_BASE_APLL, /*!< Base clock for audio PLL */
- CLK_BASE_CGU_OUT0, /*!< Base clock for CGUOUT0 pin */
- CLK_BASE_CGU_OUT1, /*!< Base clock for CGUOUT1 pin */
- CLK_BASE_LAST,
- CLK_BASE_NONE = CLK_BASE_LAST
+ CLK_BASE_SDIO, /* Base clock for SDIO */
+ CLK_BASE_SSP0, /* Base clock for SSP0 */
+ CLK_BASE_SSP1, /* Base clock for SSP1 */
+ CLK_BASE_UART0, /* Base clock for UART0 */
+ CLK_BASE_UART1, /* Base clock for UART1 */
+ CLK_BASE_UART2, /* Base clock for UART2 */
+ CLK_BASE_UART3, /* Base clock for UART3 */
+ CLK_BASE_OUT, /* Base clock for CLKOUT pin */
+ CLK_BASE_RESERVED4,
+ CLK_BASE_RESERVED5,
+ CLK_BASE_RESERVED6,
+ CLK_BASE_RESERVED7,
+ CLK_BASE_APLL, /* Base clock for audio PLL */
+ CLK_BASE_CGU_OUT0, /* Base clock for CGUOUT0 pin */
+ CLK_BASE_CGU_OUT1, /* Base clock for CGUOUT1 pin */
+ CLK_BASE_LAST,
+ CLK_BASE_NONE = CLK_BASE_LAST
} CGU_BASE_CLK_T;
-/**
+/*
* CGU dividers provide an extra clock state where a specific clock can be
* divided before being routed to a peripheral group. A divider accepts an
* input clock and then divides it. To use the divided clock for a base clock
@@ -1034,649 +1092,691 @@
* use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
*/
typedef enum CGU_IDIV {
- CLK_IDIV_A, /*!< CGU clock divider A */
- CLK_IDIV_B, /*!< CGU clock divider B */
- CLK_IDIV_C, /*!< CGU clock divider A */
- CLK_IDIV_D, /*!< CGU clock divider D */
- CLK_IDIV_E, /*!< CGU clock divider E */
- CLK_IDIV_LAST
+ CLK_IDIV_A, /* CGU clock divider A */
+ CLK_IDIV_B, /* CGU clock divider B */
+ CLK_IDIV_C, /* CGU clock divider A */
+ CLK_IDIV_D, /* CGU clock divider D */
+ CLK_IDIV_E, /* CGU clock divider E */
+ CLK_IDIV_LAST
} CGU_IDIV_T;
-/**
+/*
* Peripheral clocks are individual clocks routed to peripherals. Although
* multiple peripherals may share a same base clock, each peripheral's clock
* can be enabled or disabled individually. Some peripheral clocks also have
* additional dividers associated with them.
*/
typedef enum CCU_CLK {
- /* CCU1 clocks */
- CLK_APB3_BUS, /*!< APB3 bus clock from base clock CLK_BASE_APB3 */
- CLK_APB3_I2C1, /*!< I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_DAC, /*!< DAC peripheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_ADC0, /*!< ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_ADC1, /*!< ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB3_CAN0, /*!< CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
- CLK_APB1_BUS = 32, /*!< APB1 bus clock clock from base clock CLK_BASE_APB1 */
- CLK_APB1_MOTOCON, /*!< Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_APB1_I2C0, /*!< I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_APB1_I2S, /*!< I2S register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_APB1_CAN1, /*!< CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
- CLK_SPIFI = 64, /*!< SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
- CLK_MX_BUS = 96, /*!< M3/M4 BUS core clock from base clock CLK_BASE_MX */
- CLK_MX_SPIFI, /*!< SPIFI register clock from base clock CLK_BASE_MX */
- CLK_MX_GPIO, /*!< GPIO register clock from base clock CLK_BASE_MX */
- CLK_MX_LCD, /*!< LCD register clock from base clock CLK_BASE_MX */
- CLK_MX_ETHERNET, /*!< ETHERNET register clock from base clock CLK_BASE_MX */
- CLK_MX_USB0, /*!< USB0 register clock from base clock CLK_BASE_MX */
- CLK_MX_EMC, /*!< EMC clock from base clock CLK_BASE_MX */
- CLK_MX_SDIO, /*!< SDIO register clock from base clock CLK_BASE_MX */
- CLK_MX_DMA, /*!< DMA register clock from base clock CLK_BASE_MX */
- CLK_MX_MXCORE, /*!< M3/M4 CPU core clock from base clock CLK_BASE_MX */
- RESERVED_ALIGN = CLK_MX_MXCORE + 3,
- CLK_MX_SCT, /*!< SCT register clock from base clock CLK_BASE_MX */
- CLK_MX_USB1, /*!< USB1 register clock from base clock CLK_BASE_MX */
- CLK_MX_EMC_DIV, /*!< ENC divider clock from base clock CLK_BASE_MX */
- CLK_MX_FLASHA, /*!< FLASHA bank clock from base clock CLK_BASE_MX */
- CLK_MX_FLASHB, /*!< FLASHB bank clock from base clock CLK_BASE_MX */
+ /* CCU1 clocks */
+ CLK_APB3_BUS, /* APB3 bus clock from base clock CLK_BASE_APB3 */
+ CLK_APB3_I2C1, /* I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
+ CLK_APB3_DAC, /* DAC peripheral clock from base clock CLK_BASE_APB3 */
+ CLK_APB3_ADC0, /* ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
+ CLK_APB3_ADC1, /* ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
+ CLK_APB3_CAN0, /* CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
+ CLK_APB1_BUS = 32, /* APB1 bus clock clock from base clock CLK_BASE_APB1 */
+ CLK_APB1_MOTOCON, /* Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
+ CLK_APB1_I2C0, /* I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
+ CLK_APB1_I2S, /* I2S register/perigheral clock from base clock CLK_BASE_APB1 */
+ CLK_APB1_CAN1, /* CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
+ CLK_SPIFI = 64, /* SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
+ CLK_MX_BUS = 96, /* M3/M4 BUS core clock from base clock CLK_BASE_MX */
+ CLK_MX_SPIFI, /* SPIFI register clock from base clock CLK_BASE_MX */
+ CLK_MX_GPIO, /* GPIO register clock from base clock CLK_BASE_MX */
+ CLK_MX_LCD, /* LCD register clock from base clock CLK_BASE_MX */
+ CLK_MX_ETHERNET, /* ETHERNET register clock from base clock CLK_BASE_MX */
+ CLK_MX_USB0, /* USB0 register clock from base clock CLK_BASE_MX */
+ CLK_MX_EMC, /* EMC clock from base clock CLK_BASE_MX */
+ CLK_MX_SDIO, /* SDIO register clock from base clock CLK_BASE_MX */
+ CLK_MX_DMA, /* DMA register clock from base clock CLK_BASE_MX */
+ CLK_MX_MXCORE, /* M3/M4 CPU core clock from base clock CLK_BASE_MX */
+ RESERVED_ALIGN = CLK_MX_MXCORE + 3,
+ CLK_MX_SCT, /* SCT register clock from base clock CLK_BASE_MX */
+ CLK_MX_USB1, /* USB1 register clock from base clock CLK_BASE_MX */
+ CLK_MX_EMC_DIV, /* ENC divider clock from base clock CLK_BASE_MX */
+ CLK_MX_FLASHA, /* FLASHA bank clock from base clock CLK_BASE_MX */
+ CLK_MX_FLASHB, /* FLASHB bank clock from base clock CLK_BASE_MX */
#if defined(CHIP_LPC43XX)
- CLK_M4_M0APP, /*!< M0 app CPU core clock from base clock CLK_BASE_MX */
- CLK_MX_VADC, /*!< VADC clock from base clock CLK_BASE_MX */
+ CLK_M4_M0APP, /* M0 app CPU core clock from base clock CLK_BASE_MX */
+ CLK_MX_VADC, /* VADC clock from base clock CLK_BASE_MX */
#else
- CLK_RESERVED1,
- CLK_RESERVED2,
+ CLK_RESERVED1,
+ CLK_RESERVED2,
#endif
- CLK_MX_EEPROM, /*!< EEPROM clock from base clock CLK_BASE_MX */
- CLK_MX_WWDT = 128, /*!< WWDT register clock from base clock CLK_BASE_MX */
- CLK_MX_UART0, /*!< UART0 register clock from base clock CLK_BASE_MX */
- CLK_MX_UART1, /*!< UART1 register clock from base clock CLK_BASE_MX */
- CLK_MX_SSP0, /*!< SSP0 register clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER0, /*!< TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER1, /*!< TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_SCU, /*!< SCU register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_CREG, /*!< CREG clock from base clock CLK_BASE_MX */
- CLK_MX_RITIMER = 160, /*!< RITIMER register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_UART2, /*!< UART3 register clock from base clock CLK_BASE_MX */
- CLK_MX_UART3, /*!< UART4 register clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER2, /*!< TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_TIMER3, /*!< TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
- CLK_MX_SSP1, /*!< SSP1 register clock from base clock CLK_BASE_MX */
- CLK_MX_QEI, /*!< QEI register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_EEPROM, /* EEPROM clock from base clock CLK_BASE_MX */
+ CLK_MX_WWDT = 128, /* WWDT register clock from base clock CLK_BASE_MX */
+ CLK_MX_UART0, /* UART0 register clock from base clock CLK_BASE_MX */
+ CLK_MX_UART1, /* UART1 register clock from base clock CLK_BASE_MX */
+ CLK_MX_SSP0, /* SSP0 register clock from base clock CLK_BASE_MX */
+ CLK_MX_TIMER0, /* TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_TIMER1, /* TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_SCU, /* SCU register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_CREG, /* CREG clock from base clock CLK_BASE_MX */
+ CLK_MX_RITIMER = 160, /* RITIMER register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_UART2, /* UART3 register clock from base clock CLK_BASE_MX */
+ CLK_MX_UART3, /* UART4 register clock from base clock CLK_BASE_MX */
+ CLK_MX_TIMER2, /* TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_TIMER3, /* TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
+ CLK_MX_SSP1, /* SSP1 register clock from base clock CLK_BASE_MX */
+ CLK_MX_QEI, /* QEI register/perigheral clock from base clock CLK_BASE_MX */
#if defined(CHIP_LPC43XX)
- CLK_PERIPH_BUS = 192, /*!< Peripheral bus clock from base clock CLK_BASE_PERIPH */
- CLK_RESERVED3,
- CLK_PERIPH_CORE, /*!< Peripheral core clock from base clock CLK_BASE_PERIPH */
- CLK_PERIPH_SGPIO, /*!< SGPIO clock from base clock CLK_BASE_PERIPH */
+ CLK_PERIPH_BUS = 192, /* Peripheral bus clock from base clock CLK_BASE_PERIPH */
+ CLK_RESERVED3,
+ CLK_PERIPH_CORE, /* Peripheral core clock from base clock CLK_BASE_PERIPH */
+ CLK_PERIPH_SGPIO, /* SGPIO clock from base clock CLK_BASE_PERIPH */
#else
- CLK_RESERVED3 = 192,
- CLK_RESERVED3A,
- CLK_RESERVED4,
- CLK_RESERVED5,
+ CLK_RESERVED3 = 192,
+ CLK_RESERVED3A,
+ CLK_RESERVED4,
+ CLK_RESERVED5,
#endif
- CLK_USB0 = 224, /*!< USB0 clock from base clock CLK_BASE_USB0 */
- CLK_USB1 = 256, /*!< USB1 clock from base clock CLK_BASE_USB1 */
+ CLK_USB0 = 224, /* USB0 clock from base clock CLK_BASE_USB0 */
+ CLK_USB1 = 256, /* USB1 clock from base clock CLK_BASE_USB1 */
#if defined(CHIP_LPC43XX)
- CLK_SPI = 288, /*!< SPI clock from base clock CLK_BASE_SPI */
- CLK_VADC, /*!< VADC clock from base clock CLK_BASE_VADC */
+ CLK_SPI = 288, /* SPI clock from base clock CLK_BASE_SPI */
+ CLK_VADC, /* VADC clock from base clock CLK_BASE_VADC */
#else
- CLK_RESERVED7 = 320,
- CLK_RESERVED8,
+ CLK_RESERVED7 = 320,
+ CLK_RESERVED8,
#endif
- CLK_CCU1_LAST,
+ CLK_CCU1_LAST,
- /* CCU2 clocks */
- CLK_CCU2_START,
- CLK_APLL = CLK_CCU2_START, /*!< Audio PLL clock from base clock CLK_BASE_APLL */
- RESERVED_ALIGNB = CLK_CCU2_START + 31,
- CLK_APB2_UART3, /*!< UART3 clock from base clock CLK_BASE_UART3 */
- RESERVED_ALIGNC = CLK_CCU2_START + 63,
- CLK_APB2_UART2, /*!< UART2 clock from base clock CLK_BASE_UART2 */
- RESERVED_ALIGND = CLK_CCU2_START + 95,
- CLK_APB0_UART1, /*!< UART1 clock from base clock CLK_BASE_UART1 */
- RESERVED_ALIGNE = CLK_CCU2_START + 127,
- CLK_APB0_UART0, /*!< UART0 clock from base clock CLK_BASE_UART0 */
- RESERVED_ALIGNF = CLK_CCU2_START + 159,
- CLK_APB2_SSP1, /*!< SSP1 clock from base clock CLK_BASE_SSP1 */
- RESERVED_ALIGNG = CLK_CCU2_START + 191,
- CLK_APB0_SSP0, /*!< SSP0 clock from base clock CLK_BASE_SSP0 */
- RESERVED_ALIGNH = CLK_CCU2_START + 223,
- CLK_APB2_SDIO, /*!< SDIO clock from base clock CLK_BASE_SDIO */
- CLK_CCU2_LAST
+ /* CCU2 clocks */
+ CLK_CCU2_START,
+ CLK_APLL = CLK_CCU2_START, /* Audio PLL clock from base clock CLK_BASE_APLL */
+ RESERVED_ALIGNB = CLK_CCU2_START + 31,
+ CLK_APB2_UART3, /* UART3 clock from base clock CLK_BASE_UART3 */
+ RESERVED_ALIGNC = CLK_CCU2_START + 63,
+ CLK_APB2_UART2, /* UART2 clock from base clock CLK_BASE_UART2 */
+ RESERVED_ALIGND = CLK_CCU2_START + 95,
+ CLK_APB0_UART1, /* UART1 clock from base clock CLK_BASE_UART1 */
+ RESERVED_ALIGNE = CLK_CCU2_START + 127,
+ CLK_APB0_UART0, /* UART0 clock from base clock CLK_BASE_UART0 */
+ RESERVED_ALIGNF = CLK_CCU2_START + 159,
+ CLK_APB2_SSP1, /* SSP1 clock from base clock CLK_BASE_SSP1 */
+ RESERVED_ALIGNG = CLK_CCU2_START + 191,
+ CLK_APB0_SSP0, /* SSP0 clock from base clock CLK_BASE_SSP0 */
+ RESERVED_ALIGNH = CLK_CCU2_START + 223,
+ CLK_APB2_SDIO, /* SDIO clock from base clock CLK_BASE_SDIO */
+ CLK_CCU2_LAST
} CCU_CLK_T;
-/**
+/*
* Audio or USB PLL selection
*/
typedef enum CHIP_CGU_USB_AUDIO_PLL {
- CGU_USB_PLL,
- CGU_AUDIO_PLL
+ CGU_USB_PLL,
+ CGU_AUDIO_PLL
} CHIP_CGU_USB_AUDIO_PLL_T;
-/**
+/*
* PLL register block
*/
typedef struct {
- __I uint32_t PLL_STAT; /*!< PLL status register */
- __IO uint32_t PLL_CTRL; /*!< PLL control register */
- __IO uint32_t PLL_MDIV; /*!< PLL M-divider register */
- __IO uint32_t PLL_NP_DIV; /*!< PLL N/P-divider register */
+ __I uint32_t PLL_STAT; /* PLL status register */
+ __IO uint32_t PLL_CTRL; /* PLL control register */
+ __IO uint32_t PLL_MDIV; /* PLL M-divider register */
+ __IO uint32_t PLL_NP_DIV; /* PLL N/P-divider register */
} CGU_PLL_REG_T;
-typedef struct { /*!< (@ 0x40050000) CGU Structure */
- __I uint32_t RESERVED0[5];
- __IO uint32_t FREQ_MON; /*!< (@ 0x40050014) Frequency monitor register */
- __IO uint32_t XTAL_OSC_CTRL; /*!< (@ 0x40050018) Crystal oscillator control register */
- CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /*!< (@ 0x4005001C) USB and audio PLL blocks */
- __IO uint32_t PLL0AUDIO_FRAC; /*!< (@ 0x4005003C) PLL0 (audio) */
- __I uint32_t PLL1_STAT; /*!< (@ 0x40050040) PLL1 status register */
- __IO uint32_t PLL1_CTRL; /*!< (@ 0x40050044) PLL1 control register */
- __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/*!< (@ 0x40050048) Integer divider A-E control registers */
- __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /*!< (@ 0x4005005C) Start of base clock registers */
+typedef struct { /* (@ 0x40050000) CGU Structure */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t FREQ_MON; /* (@ 0x40050014) Frequency monitor register */
+ __IO uint32_t XTAL_OSC_CTRL; /* (@ 0x40050018) Crystal oscillator control register */
+ CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /* (@ 0x4005001C) USB and audio PLL blocks */
+ __IO uint32_t PLL0AUDIO_FRAC; /* (@ 0x4005003C) PLL0 (audio) */
+ __I uint32_t PLL1_STAT; /* (@ 0x40050040) PLL1 status register */
+ __IO uint32_t PLL1_CTRL; /* (@ 0x40050044) PLL1 control register */
+ __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/* (@ 0x40050048) Integer divider A-E control registers */
+ __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /* (@ 0x4005005C) Start of base clock registers */
} LPC_CGU_T;
-/**
- * @brief CCU clock config/status register pair
+/* ---------------------------------------------------------------------------
+ * CCU clock config/status register pair
*/
typedef struct {
- __IO uint32_t CFG; /*!< CCU clock configuration register */
- __I uint32_t STAT; /*!< CCU clock status register */
+ __IO uint32_t CFG; /* CCU clock configuration register */
+ __I uint32_t STAT; /* CCU clock status register */
} CCU_CFGSTAT_T;
-/**
- * @brief CCU1 register block structure
+/* ---------------------------------------------------------------------------
+ * CCU1 register block structure
*/
-typedef struct { /*!< (@ 0x40051000) CCU1 Structure */
- __IO uint32_t PM; /*!< (@ 0x40051000) CCU1 power mode register */
- __I uint32_t BASE_STAT; /*!< (@ 0x40051004) CCU1 base clocks status register */
- __I uint32_t RESERVED0[62];
- CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /*!< (@ 0x40051100) Start of CCU1 clock registers */
+typedef struct { /* (@ 0x40051000) CCU1 Structure */
+ __IO uint32_t PM; /* (@ 0x40051000) CCU1 power mode register */
+ __I uint32_t BASE_STAT; /* (@ 0x40051004) CCU1 base clocks status register */
+ __I uint32_t RESERVED0[62];
+ CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /* (@ 0x40051100) Start of CCU1 clock registers */
} LPC_CCU1_T;
-/**
- * @brief CCU2 register block structure
+/* ---------------------------------------------------------------------------
+ * CCU2 register block structure
*/
-typedef struct { /*!< (@ 0x40052000) CCU2 Structure */
- __IO uint32_t PM; /*!< (@ 0x40052000) Power mode register */
- __I uint32_t BASE_STAT; /*!< (@ 0x40052004) CCU base clocks status register */
- __I uint32_t RESERVED0[62];
- CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /*!< (@ 0x40052100) Start of CCU2 clock registers */
+typedef struct { /* (@ 0x40052000) CCU2 Structure */
+ __IO uint32_t PM; /* (@ 0x40052000) Power mode register */
+ __I uint32_t BASE_STAT; /* (@ 0x40052004) CCU base clocks status register */
+ __I uint32_t RESERVED0[62];
+ CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /* (@ 0x40052100) Start of CCU2 clock registers */
} LPC_CCU2_T;
-/**
- * @brief RGU register structure
+/* ---------------------------------------------------------------------------
+ * RGU register structure
*/
#define LPC_RGU_BASE 0x40053000
typedef enum CHIP_RGU_RST {
- RGU_CORE_RST,
- RGU_PERIPH_RST,
- RGU_MASTER_RST,
- RGU_WWDT_RST = 4,
- RGU_CREG_RST,
- RGU_BUS_RST = 8,
- RGU_SCU_RST,
- RGU_M3_RST = 13,
- RGU_LCD_RST = 16,
- RGU_USB0_RST,
- RGU_USB1_RST,
- RGU_DMA_RST,
- RGU_SDIO_RST,
- RGU_EMC_RST,
- RGU_ETHERNET_RST,
- RGU_FLASHA_RST = 25,
- RGU_EEPROM_RST = 27,
- RGU_GPIO_RST,
- RGU_FLASHB_RST,
- RGU_TIMER0_RST = 32,
- RGU_TIMER1_RST,
- RGU_TIMER2_RST,
- RGU_TIMER3_RST,
- RGU_RITIMER_RST,
- RGU_SCT_RST,
- RGU_MOTOCONPWM_RST,
- RGU_QEI_RST,
- RGU_ADC0_RST,
- RGU_ADC1_RST,
- RGU_DAC_RST,
- RGU_UART0_RST = 44,
- RGU_UART1_RST,
- RGU_UART2_RST,
- RGU_UART3_RST,
- RGU_I2C0_RST,
- RGU_I2C1_RST,
- RGU_SSP0_RST,
- RGU_SSP1_RST,
- RGU_I2S_RST,
- RGU_SPIFI_RST,
- RGU_CAN1_RST,
- RGU_CAN0_RST,
+ RGU_CORE_RST,
+ RGU_PERIPH_RST,
+ RGU_MASTER_RST,
+ RGU_WWDT_RST = 4,
+ RGU_CREG_RST,
+ RGU_BUS_RST = 8,
+ RGU_SCU_RST,
+ RGU_M3_RST = 13,
+ RGU_LCD_RST = 16,
+ RGU_USB0_RST,
+ RGU_USB1_RST,
+ RGU_DMA_RST,
+ RGU_SDIO_RST,
+ RGU_EMC_RST,
+ RGU_ETHERNET_RST,
+ RGU_FLASHA_RST = 25,
+ RGU_EEPROM_RST = 27,
+ RGU_GPIO_RST,
+ RGU_FLASHB_RST,
+ RGU_TIMER0_RST = 32,
+ RGU_TIMER1_RST,
+ RGU_TIMER2_RST,
+ RGU_TIMER3_RST,
+ RGU_RITIMER_RST,
+ RGU_SCT_RST,
+ RGU_MOTOCONPWM_RST,
+ RGU_QEI_RST,
+ RGU_ADC0_RST,
+ RGU_ADC1_RST,
+ RGU_DAC_RST,
+ RGU_UART0_RST = 44,
+ RGU_UART1_RST,
+ RGU_UART2_RST,
+ RGU_UART3_RST,
+ RGU_I2C0_RST,
+ RGU_I2C1_RST,
+ RGU_SSP0_RST,
+ RGU_SSP1_RST,
+ RGU_I2S_RST,
+ RGU_SPIFI_RST,
+ RGU_CAN1_RST,
+ RGU_CAN0_RST,
#ifdef CHIP_LPC43XX
- RGU_M0APP_RST,
- RGU_SGPIO_RST,
- RGU_SPI_RST,
+ RGU_M0APP_RST,
+ RGU_SGPIO_RST,
+ RGU_SPI_RST,
#endif
- RGU_LAST_RST = 63,
+ RGU_LAST_RST = 63,
} CHIP_RGU_RST_T;
-typedef struct { /*!< RGU Structure */
- __I uint32_t RESERVED0[64];
- __O uint32_t RESET_CTRL0; /*!< Reset control register 0 */
- __O uint32_t RESET_CTRL1; /*!< Reset control register 1 */
- __I uint32_t RESERVED1[2];
- __IO uint32_t RESET_STATUS0; /*!< Reset status register 0 */
- __IO uint32_t RESET_STATUS1; /*!< Reset status register 1 */
- __IO uint32_t RESET_STATUS2; /*!< Reset status register 2 */
- __IO uint32_t RESET_STATUS3; /*!< Reset status register 3 */
- __I uint32_t RESERVED2[12];
- __I uint32_t RESET_ACTIVE_STATUS0; /*!< Reset active status register 0 */
- __I uint32_t RESET_ACTIVE_STATUS1; /*!< Reset active status register 1 */
- __I uint32_t RESERVED3[170];
- __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/*!< Reset external status registers */
+typedef struct { /* RGU Structure */
+ __I uint32_t RESERVED0[64];
+ __O uint32_t RESET_CTRL0; /* Reset control register 0 */
+ __O uint32_t RESET_CTRL1; /* Reset control register 1 */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t RESET_STATUS0; /* Reset status register 0 */
+ __IO uint32_t RESET_STATUS1; /* Reset status register 1 */
+ __IO uint32_t RESET_STATUS2; /* Reset status register 2 */
+ __IO uint32_t RESET_STATUS3; /* Reset status register 3 */
+ __I uint32_t RESERVED2[12];
+ __I uint32_t RESET_ACTIVE_STATUS0;/* Reset active status register 0 */
+ __I uint32_t RESET_ACTIVE_STATUS1;/* Reset active status register 1 */
+ __I uint32_t RESERVED3[170];
+ __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/* Reset external status registers */
} LPC_RGU_T;
-/**
- * @brief Windowed Watchdog register block structure
+/* ---------------------------------------------------------------------------
+ * Windowed Watchdog register block structure
*/
#define LPC_WWDT_BASE 0x40080000
-typedef struct { /*!< WWDT Structure */
- __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
- __IO uint32_t TC; /*!< Watchdog timer constant register. This register determines the time-out value. */
- __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
- __I uint32_t TV; /*!< Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
+typedef struct { /* WWDT Structure */
+ __IO uint32_t MOD; /* Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+ __IO uint32_t TC; /* Watchdog timer constant register. This register determines the time-out value. */
+ __O uint32_t FEED; /* Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
+ __I uint32_t TV; /* Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
#ifdef WATCHDOG_CLKSEL_SUPPORT
- __IO uint32_t CLKSEL; /*!< Watchdog clock select register. */
+ __IO uint32_t CLKSEL; /* Watchdog clock select register. */
#else
- __I uint32_t RESERVED0;
+ __I uint32_t RESERVED0;
#endif
#ifdef WATCHDOG_WINDOW_SUPPORT
- __IO uint32_t WARNINT; /*!< Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
- __IO uint32_t WINDOW; /*!< Watchdog timer window register. This register contains the Watchdog window value. */
+ __IO uint32_t WARNINT; /* Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
+ __IO uint32_t WINDOW; /* Watchdog timer window register. This register contains the Watchdog window value. */
#endif
} LPC_WWDT_T;
-/**
- * @brief USART register block structure
+/* ---------------------------------------------------------------------------
+ * USART register block structure
*/
#define LPC_USART0_BASE 0x40081000
#define LPC_UART1_BASE 0x40082000
#define LPC_USART2_BASE 0x400C1000
#define LPC_USART3_BASE 0x400C2000
-typedef struct { /*!< USARTn Structure */
+typedef struct { /* USARTn Structure */
- union {
- __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
- __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
- __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
- };
+ union {
+ __IO uint32_t DLL; /* Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+ __O uint32_t THR; /* Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
+ __I uint32_t RBR; /* Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
+ };
- union {
- __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
- __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
- };
+ union {
+ __IO uint32_t IER; /* Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
+ __IO uint32_t DLM; /* Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+ };
- union {
- __O uint32_t FCR; /*!< FIFO Control Register. Controls UART FIFO usage and modes. */
- __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
- };
+ union {
+ __O uint32_t FCR; /* FIFO Control Register. Controls UART FIFO usage and modes. */
+ __I uint32_t IIR; /* Interrupt ID Register. Identifies which interrupt(s) are pending. */
+ };
- __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting and break generation. */
- __IO uint32_t MCR; /*!< Modem Control Register. Only present on USART ports with full modem support. */
- __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive status, including line errors. */
- __I uint32_t MSR; /*!< Modem Status Register. Only present on USART ports with full modem support. */
- __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
- __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud feature. */
- __IO uint32_t ICR; /*!< IrDA control register (not all UARTS) */
- __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the baud rate divider. */
- __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
- __IO uint32_t TER1; /*!< Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
- uint32_t RESERVED0[3];
- __IO uint32_t HDEN; /*!< Half-duplex enable Register- only on some UARTs */
- __I uint32_t RESERVED1[1];
- __IO uint32_t SCICTRL; /*!< Smart card interface control register- only on some UARTs */
- __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
- __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
- __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
- union {
- __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. Only on USARTs. */
- __I uint32_t FIFOLVL; /*!< FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
- };
+ __IO uint32_t LCR; /* Line Control Register. Contains controls for frame formatting and break generation. */
+ __IO uint32_t MCR; /* Modem Control Register. Only present on USART ports with full modem support. */
+ __I uint32_t LSR; /* Line Status Register. Contains flags for transmit and receive status, including line errors. */
+ __I uint32_t MSR; /* Modem Status Register. Only present on USART ports with full modem support. */
+ __IO uint32_t SCR; /* Scratch Pad Register. Eight-bit temporary storage for software. */
+ __IO uint32_t ACR; /* Auto-baud Control Register. Contains controls for the auto-baud feature. */
+ __IO uint32_t ICR; /* IrDA control register (not all UARTS) */
+ __IO uint32_t FDR; /* Fractional Divider Register. Generates a clock input for the baud rate divider. */
+ __IO uint32_t OSR; /* Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
+ __IO uint32_t TER1; /* Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
+ uint32_t RESERVED0[3];
+ __IO uint32_t HDEN; /* Half-duplex enable Register- only on some UARTs */
+ __I uint32_t RESERVED1[1];
+ __IO uint32_t SCICTRL; /* Smart card interface control register- only on some UARTs */
+ __IO uint32_t RS485CTRL; /* RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+ __IO uint32_t RS485ADRMATCH; /* RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+ __IO uint32_t RS485DLY; /* RS-485/EIA-485 direction control delay. */
+ union {
+ __IO uint32_t SYNCCTRL; /* Synchronous mode control register. Only on USARTs. */
+ __I uint32_t FIFOLVL; /* FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
+ };
- __IO uint32_t TER2; /*!< Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
+ __IO uint32_t TER2; /* Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
} LPC_USART_T;
-/**
- * @brief SSP register block structure
+/* ---------------------------------------------------------------------------
+ * SSP register block structure
*/
#define LPC_SSP0_BASE 0x40083000
#define LPC_SSP1_BASE 0x400C5000
-typedef struct { /*!< SSPn Structure */
- __IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type, and data size. */
- __IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */
- __IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
- __I uint32_t SR; /*!< Status Register */
- __IO uint32_t CPSR; /*!< Clock Prescale Register */
- __IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */
- __I uint32_t RIS; /*!< Raw Interrupt Status Register */
- __I uint32_t MIS; /*!< Masked Interrupt Status Register */
- __O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */
- __IO uint32_t DMACR; /*!< SSPn DMA control register */
+typedef struct { /* SSPn Structure */
+ __IO uint32_t CR0; /* Control Register 0. Selects the serial clock rate, bus type, and data size. */
+ __IO uint32_t CR1; /* Control Register 1. Selects master/slave and other modes. */
+ __IO uint32_t DR; /* Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+ __I uint32_t SR; /* Status Register */
+ __IO uint32_t CPSR; /* Clock Prescale Register */
+ __IO uint32_t IMSC; /* Interrupt Mask Set and Clear Register */
+ __I uint32_t RIS; /* Raw Interrupt Status Register */
+ __I uint32_t MIS; /* Masked Interrupt Status Register */
+ __O uint32_t ICR; /* SSPICR Interrupt Clear Register */
+ __IO uint32_t DMACR; /* SSPn DMA control register */
} LPC_SSP_T;
-/**
- * @brief 32-bit Standard timer register block structure
+/* ---------------------------------------------------------------------------
+ * 32-bit Standard timer register block structure
*/
-typedef struct { /*!< TIMERn Structure */
- __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
- __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
- __IO uint32_t TC; /*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
- __IO uint32_t PR; /*!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
- __IO uint32_t PC; /*!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
- __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
- __IO uint32_t MR[4]; /*!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
- __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
- __IO uint32_t CR[4]; /*!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
- __IO uint32_t EMR; /*!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
- __I uint32_t RESERVED0[12];
- __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
-} LPC_TIMER_T;
-
#define LPC_TIMER0_BASE 0x40084000
#define LPC_TIMER1_BASE 0x40085000
#define LPC_TIMER2_BASE 0x400C3000
#define LPC_TIMER3_BASE 0x400C4000
-/**
- * @brief System Control Unit register block
+typedef struct { /* TIMERn Structure */
+ __IO uint32_t IR; /* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+ __IO uint32_t TCR; /* Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+ __IO uint32_t TC; /* Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /* Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+ __IO uint32_t PC; /* Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+ __IO uint32_t MCR; /* Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+ __IO uint32_t MR[4]; /* Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+ __IO uint32_t CCR; /* Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+ __IO uint32_t CR[4]; /* Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
+ __IO uint32_t EMR; /* External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /* Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+} LPC_TIMER_T;
+
+/* ---------------------------------------------------------------------------
+ * System Control Unit register block
*/
#define LPC_SCU_BASE 0x40086000
typedef struct {
- __IO uint32_t SFSP[16][32];
- __I uint32_t RESERVED0[256];
- __IO uint32_t SFSCLK[4]; /*!< Pin configuration register for pins CLK0-3 */
- __I uint32_t RESERVED16[28];
- __IO uint32_t SFSUSB; /*!< Pin configuration register for USB */
- __IO uint32_t SFSI2C0; /*!< Pin configuration register for I2C0-bus pins */
- __IO uint32_t ENAIO[3]; /*!< Analog function select registers */
- __I uint32_t RESERVED17[27];
- __IO uint32_t EMCDELAYCLK; /*!< EMC clock delay register */
- __I uint32_t RESERVED18[63];
- __IO uint32_t PINTSEL0; /*!< Pin interrupt select register for pin interrupts 0 to 3. */
- __IO uint32_t PINTSEL1; /*!< Pin interrupt select register for pin interrupts 4 to 7. */
+ __IO uint32_t SFSP[16][32];
+ __I uint32_t RESERVED0[256];
+ __IO uint32_t SFSCLK[4]; /* Pin configuration register for pins CLK0-3 */
+ __I uint32_t RESERVED16[28];
+ __IO uint32_t SFSUSB; /* Pin configuration register for USB */
+ __IO uint32_t SFSI2C0; /* Pin configuration register for I2C0-bus pins */
+ __IO uint32_t ENAIO[3]; /* Analog function select registers */
+ __I uint32_t RESERVED17[27];
+ __IO uint32_t EMCDELAYCLK; /* EMC clock delay register */
+ __I uint32_t RESERVED18[63];
+ __IO uint32_t PINTSEL0; /* Pin interrupt select register for pin interrupts 0 to 3. */
+ __IO uint32_t PINTSEL1; /* Pin interrupt select register for pin interrupts 4 to 7. */
} LPC_SCU_T;
-/**
+/*
* SCU function and mode selection definitions
* See the User Manual for specific modes and functions supoprted by the
* various LPC18xx/43xx devices. Functionality can vary per device.
*/
-#define SCU_MODE_MODE_INACT (0x0 << 3) /*!< Disable pull-down and pull-up resistor at resistor at pad */
-#define SCU_MODE_MODE_PULLDOWN (0x1 << 3) /*!< Enable pull-down resistor at pad */
-#define SCU_MODE_MODE_PULLUP_DIS (0x2 << 3) /*!< Disable pull-up resistor at pad */
-#define SCU_MODE_MODE_REPEATER (0x3 << 3) /*!< Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
-#define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /*!< Enable high-speed slew */
-#define SCU_MODE_INBUFF_EN (0x1 << 6) /*!< Enable Input buffer */
-#define SCU_MODE_ZIF_DIS (0x1 << 7) /*!< Disable input glitch filter */
-#define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /*!< Normal drive: 4mA drive strength */
-#define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /*!< Medium drive: 8mA drive strength */
-#define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /*!< High drive: 14mA drive strength */
-#define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /*!< Ultra high- drive: 20mA drive strength */
+#define SCU_MODE_PULLUP (0x0 << 3) /* Enable pull-up resistor at pad */
+#define SCU_MODE_REPEATER (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
+#define SCU_MODE_INACT (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
+#define SCU_MODE_PULLDOWN (0x3 << 3) /* Enable pull-down resistor at pad */
+#define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /* Enable high-speed slew */
+#define SCU_MODE_INBUFF_EN (0x1 << 6) /* Enable Input buffer */
+#define SCU_MODE_ZIF_DIS (0x1 << 7) /* Disable input glitch filter */
+#define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /* Normal drive: 4mA drive strength */
+#define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /* Medium drive: 8mA drive strength */
+#define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /* High drive: 14mA drive strength */
+#define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /* Ultra high- drive: 20mA drive strength */
+
+#define SCU_MODE_FUNC0 0x0 /* Selects pin function 0 */
+#define SCU_MODE_FUNC1 0x1 /* Selects pin function 1 */
+#define SCU_MODE_FUNC2 0x2 /* Selects pin function 2 */
+#define SCU_MODE_FUNC3 0x3 /* Selects pin function 3 */
+#define SCU_MODE_FUNC4 0x4 /* Selects pin function 4 */
+#define SCU_MODE_FUNC5 0x5 /* Selects pin function 5 */
+#define SCU_MODE_FUNC6 0x6 /* Selects pin function 6 */
+#define SCU_MODE_FUNC7 0x7 /* Selects pin function 7 */
/* Common SCU configurations */
-#define SCU_PINIO_FAST (SCU_MODE_MODE_PULLUP_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS)
+#define SCU_PINIO_FAST (SCU_MODE_INACT | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS)
#define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
-#define SCU_PINIO_PULLDOWN (SCU_MODE_MODE_PULLDOWN | SCU_MODE_MODE_PULLUP_DIS | SCU_MODE_INBUFF_EN)
-#define SCU_PINIO_PULLNONE (SCU_MODE_MODE_PULLUP_DIS | SCU_MODE_INBUFF_EN)
+#define SCU_PINIO_PULLDOWN (SCU_MODE_PULLDOWN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
+#define SCU_PINIO_PULLNONE (SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
/* Calculate SCU offset and register address from group and pin number */
#define SCU_OFF(group, num) ((0x80 * group) + (0x04 * num))
#define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
/**
- * @brief GPIO pin interrupt register block structure
+ * SCU function and mode selection definitions (old)
+ * For backwards compatibility.
+ */
+#define MD_PUP (0x0 << 3) /* Enable pull-up resistor at pad */
+#define MD_BUK (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
+#define MD_PLN (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
+#define MD_PDN (0x3 << 3) /* Enable pull-down resistor at pad */
+#define MD_EHS (0x1 << 5) /* Enable fast slew rate */
+#define MD_EZI (0x1 << 6) /* Input buffer enable */
+#define MD_ZI (0x1 << 7) /* Disable input glitch filter */
+#define MD_EHD0 (0x1 << 8) /* EHD driver strength low bit */
+#define MD_EHD1 (0x1 << 8) /* EHD driver strength high bit */
+#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
+#define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11) /* Pin configuration for STANDARD/FAST mode I2C */
+#define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11) /* Pin configuration for Fast-mode Plus I2C */
+
+#define FUNC0 0x0 /* Pin function 0 */
+#define FUNC1 0x1 /* Pin function 1 */
+#define FUNC2 0x2 /* Pin function 2 */
+#define FUNC3 0x3 /* Pin function 3 */
+#define FUNC4 0x4 /* Pin function 4 */
+#define FUNC5 0x5 /* Pin function 5 */
+#define FUNC6 0x6 /* Pin function 6 */
+#define FUNC7 0x7 /* Pin function 7 */
+
+#define PORT_OFFSET 0x80 /* Port offset definition */
+#define PIN_OFFSET 0x04 /* Pin offset definition */
+
+/* Returns the SFSP register address in the SCU for a pin and port,
+ recommend using (*(volatile int *) &LPC_SCU->SFSP[po][pi];) */
+#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) \
+ (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
+
+/* Returns the address in the SCU for a SFSCLK clock register,
+ recommend using (*(volatile int *) &LPC_SCU->SFSCLK[c];) */
+#define LPC_SCU_CLK(LPC_SCU_BASE, c) \
+ (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
+
+/* ---------------------------------------------------------------------------
+ * GPIO pin interrupt register block structure
*/
#define LPC_GPIO_PIN_INT_BASE 0x40087000
-typedef struct { /*!< GPIO_PIN_INT Structure */
- __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
- __IO uint32_t IENR; /*!< Pin Interrupt Enable (Rising) register */
- __O uint32_t SIENR; /*!< Set Pin Interrupt Enable (Rising) register */
- __O uint32_t CIENR; /*!< Clear Pin Interrupt Enable (Rising) register */
- __IO uint32_t IENF; /*!< Pin Interrupt Enable Falling Edge / Active Level register */
- __O uint32_t SIENF; /*!< Set Pin Interrupt Enable Falling Edge / Active Level register */
- __O uint32_t CIENF; /*!< Clear Pin Interrupt Enable Falling Edge / Active Level address */
- __IO uint32_t RISE; /*!< Pin Interrupt Rising Edge register */
- __IO uint32_t FALL; /*!< Pin Interrupt Falling Edge register */
- __IO uint32_t IST; /*!< Pin Interrupt Status register */
+typedef struct { /* GPIO_PIN_INT Structure */
+ __IO uint32_t ISEL; /* Pin Interrupt Mode register */
+ __IO uint32_t IENR; /* Pin Interrupt Enable (Rising) register */
+ __O uint32_t SIENR; /* Set Pin Interrupt Enable (Rising) register */
+ __O uint32_t CIENR; /* Clear Pin Interrupt Enable (Rising) register */
+ __IO uint32_t IENF; /* Pin Interrupt Enable Falling Edge / Active Level register */
+ __O uint32_t SIENF; /* Set Pin Interrupt Enable Falling Edge / Active Level register */
+ __O uint32_t CIENF; /* Clear Pin Interrupt Enable Falling Edge / Active Level address */
+ __IO uint32_t RISE; /* Pin Interrupt Rising Edge register */
+ __IO uint32_t FALL; /* Pin Interrupt Falling Edge register */
+ __IO uint32_t IST; /* Pin Interrupt Status register */
} LPC_GPIOPININT_T;
typedef enum LPC_GPIOPININT_MODE {
- GPIOPININT_RISING_EDGE = 0x01,
- GPIOPININT_FALLING_EDGE = 0x02,
- GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
- GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
+ GPIOPININT_RISING_EDGE = 0x01,
+ GPIOPININT_FALLING_EDGE = 0x02,
+ GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
+ GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
} LPC_GPIOPININT_MODE_T;
-/**
- * @brief GPIO grouped interrupt register block structure
+/* ---------------------------------------------------------------------------
+ * GPIO grouped interrupt register block structure
*/
#define LPC_GPIO_GROUP_INT0_BASE 0x40088000
#define LPC_GPIO_GROUP_INT1_BASE 0x40089000
-typedef struct { /*!< GPIO_GROUP_INTn Structure */
- __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
- __I uint32_t RESERVED0[7];
- __IO uint32_t PORT_POL[8]; /*!< GPIO grouped interrupt port polarity register */
- __IO uint32_t PORT_ENA[8]; /*!< GPIO grouped interrupt port m enable register */
+typedef struct { /* GPIO_GROUP_INTn Structure */
+ __IO uint32_t CTRL; /* GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL[8]; /* GPIO grouped interrupt port polarity register */
+ __IO uint32_t PORT_ENA[8]; /* GPIO grouped interrupt port m enable register */
} LPC_GPIOGROUPINT_T;
-/**
- * @brief Motor Control PWM register block structure
+/* ---------------------------------------------------------------------------
+ * Motor Control PWM register block structure
*/
#define LPC_MCPWM_BASE 0x400A0000
-typedef struct { /*!< MCPWM Structure */
- __I uint32_t CON; /*!< PWM Control read address */
- __O uint32_t CON_SET; /*!< PWM Control set address */
- __O uint32_t CON_CLR; /*!< PWM Control clear address */
- __I uint32_t CAPCON; /*!< Capture Control read address */
- __O uint32_t CAPCON_SET; /*!< Capture Control set address */
- __O uint32_t CAPCON_CLR; /*!< Event Control clear address */
- __IO uint32_t TC[3]; /*!< Timer Counter register */
- __IO uint32_t LIM[3]; /*!< Limit register */
- __IO uint32_t MAT[3]; /*!< Match register */
- __IO uint32_t DT; /*!< Dead time register */
- __IO uint32_t CCP; /*!< Communication Pattern register */
- __I uint32_t CAP[3]; /*!< Capture register */
- __I uint32_t INTEN; /*!< Interrupt Enable read address */
- __O uint32_t INTEN_SET; /*!< Interrupt Enable set address */
- __O uint32_t INTEN_CLR; /*!< Interrupt Enable clear address */
- __I uint32_t CNTCON; /*!< Count Control read address */
- __O uint32_t CNTCON_SET; /*!< Count Control set address */
- __O uint32_t CNTCON_CLR; /*!< Count Control clear address */
- __I uint32_t INTF; /*!< Interrupt flags read address */
- __O uint32_t INTF_SET; /*!< Interrupt flags set address */
- __O uint32_t INTF_CLR; /*!< Interrupt flags clear address */
- __O uint32_t CAP_CLR; /*!< Capture clear address */
+typedef struct { /* MCPWM Structure */
+ __I uint32_t CON; /* PWM Control read address */
+ __O uint32_t CON_SET; /* PWM Control set address */
+ __O uint32_t CON_CLR; /* PWM Control clear address */
+ __I uint32_t CAPCON; /* Capture Control read address */
+ __O uint32_t CAPCON_SET; /* Capture Control set address */
+ __O uint32_t CAPCON_CLR; /* Event Control clear address */
+ __IO uint32_t TC[3]; /* Timer Counter register */
+ __IO uint32_t LIM[3]; /* Limit register */
+ __IO uint32_t MAT[3]; /* Match register */
+ __IO uint32_t DT; /* Dead time register */
+ __IO uint32_t CCP; /* Communication Pattern register */
+ __I uint32_t CAP[3]; /* Capture register */
+ __I uint32_t INTEN; /* Interrupt Enable read address */
+ __O uint32_t INTEN_SET; /* Interrupt Enable set address */
+ __O uint32_t INTEN_CLR; /* Interrupt Enable clear address */
+ __I uint32_t CNTCON; /* Count Control read address */
+ __O uint32_t CNTCON_SET; /* Count Control set address */
+ __O uint32_t CNTCON_CLR; /* Count Control clear address */
+ __I uint32_t INTF; /* Interrupt flags read address */
+ __O uint32_t INTF_SET; /* Interrupt flags set address */
+ __O uint32_t INTF_CLR; /* Interrupt flags clear address */
+ __O uint32_t CAP_CLR; /* Capture clear address */
} LPC_MCPWM_T;
-/**
- * @brief I2C register block structure
+/* ---------------------------------------------------------------------------
+ * I2C register block structure
*/
#define LPC_I2C0_BASE 0x400A1000
#define LPC_I2C1_BASE 0x400E0000
-typedef struct { /* I2C0 Structure */
- __IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
- __I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
- __IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
- __IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
- __IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
- __IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
- __O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
- __IO uint32_t MMCTRL; /*!< Monitor mode control register. */
- __IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
- __IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
- __IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
- __I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
- __IO uint32_t MASK[4]; /*!< I2C Slave address mask register */
+typedef struct { /* I2C0 Structure */
+ __IO uint32_t CONSET; /* I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+ __I uint32_t STAT; /* I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
+ __IO uint32_t DAT; /* I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
+ __IO uint32_t ADR0; /* I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t SCLH; /* SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
+ __IO uint32_t SCLL; /* SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
+ __O uint32_t CONCLR; /* I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+ __IO uint32_t MMCTRL; /* Monitor mode control register. */
+ __IO uint32_t ADR1; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t ADR2; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t ADR3; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __I uint32_t DATA_BUFFER; /* Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
+ __IO uint32_t MASK[4]; /* I2C Slave address mask register */
} LPC_I2C_T;
-/**
- * @brief I2S register block structure
+/* ---------------------------------------------------------------------------
+ * I2S register block structure
*/
#define LPC_I2S0_BASE 0x400A2000
#define LPC_I2S1_BASE 0x400A3000
-typedef struct { /*!< I2S Structure */
- __IO uint32_t DAO; /*!< I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
- __IO uint32_t DAI; /*!< I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
- __O uint32_t TXFIFO; /*!< I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
- __I uint32_t RXFIFO; /*!< I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
- __I uint32_t STATE; /*!< I2S Status Feedback Register. Contains status information about the I2S interface */
- __IO uint32_t DMA1; /*!< I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
- __IO uint32_t DMA2; /*!< I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
- __IO uint32_t IRQ; /*!< I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
- __IO uint32_t TXRATE; /*!< I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
- __IO uint32_t RXRATE; /*!< I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
- __IO uint32_t TXBITRATE; /*!< I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
- __IO uint32_t RXBITRATE; /*!< I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
- __IO uint32_t TXMODE; /*!< I2S Transmit mode control */
- __IO uint32_t RXMODE; /*!< I2S Receive mode control */
+typedef struct { /* I2S Structure */
+ __IO uint32_t DAO; /* I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
+ __IO uint32_t DAI; /* I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
+ __O uint32_t TXFIFO; /* I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
+ __I uint32_t RXFIFO; /* I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
+ __I uint32_t STATE; /* I2S Status Feedback Register. Contains status information about the I2S interface */
+ __IO uint32_t DMA1; /* I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
+ __IO uint32_t DMA2; /* I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
+ __IO uint32_t IRQ; /* I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
+ __IO uint32_t TXRATE; /* I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
+ __IO uint32_t RXRATE; /* I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
+ __IO uint32_t TXBITRATE; /* I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
+ __IO uint32_t RXBITRATE; /* I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
+ __IO uint32_t TXMODE; /* I2S Transmit mode control */
+ __IO uint32_t RXMODE; /* I2S Receive mode control */
} LPC_I2S_T;
-/**
- * @brief CCAN Controller Area Network register block structure
+/* ---------------------------------------------------------------------------
+ * CCAN Controller Area Network register block structure
*/
#define LPC_C_CAN1_BASE 0x400A4000
#define LPC_C_CAN0_BASE 0x400E2000
-typedef struct { /*!< C_CAN message interface Structure */
- __IO uint32_t IF_CMDREQ; /*!< Message interface command request */
- union {
- __IO uint32_t IF_CMDMSK_R; /*!< Message interface command mask (read direction) */
- __IO uint32_t IF_CMDMSK_W; /*!< Message interface command mask (write direction) */
- };
+typedef struct { /* C_CAN message interface Structure */
+ __IO uint32_t IF_CMDREQ; /* Message interface command request */
+ union {
+ __IO uint32_t IF_CMDMSK_R; /* Message interface command mask (read direction) */
+ __IO uint32_t IF_CMDMSK_W; /* Message interface command mask (write direction) */
+ };
- __IO uint32_t IF_MSK1; /*!< Message interface mask 1 */
- __IO uint32_t IF_MSK2; /*!< Message interface mask 2 */
- __IO uint32_t IF_ARB1; /*!< Message interface arbitration 1 */
- __IO uint32_t IF_ARB2; /*!< Message interface arbitration 2 */
- __IO uint32_t IF_MCTRL; /*!< Message interface message control */
- __IO uint32_t IF_DA1; /*!< Message interface data A1 */
- __IO uint32_t IF_DA2; /*!< Message interface data A2 */
- __IO uint32_t IF_DB1; /*!< Message interface data B1 */
- __IO uint32_t IF_DB2; /*!< Message interface data B2 */
- __I uint32_t RESERVED[13];
+ __IO uint32_t IF_MSK1; /* Message interface mask 1 */
+ __IO uint32_t IF_MSK2; /* Message interface mask 2 */
+ __IO uint32_t IF_ARB1; /* Message interface arbitration 1 */
+ __IO uint32_t IF_ARB2; /* Message interface arbitration 2 */
+ __IO uint32_t IF_MCTRL; /* Message interface message control */
+ __IO uint32_t IF_DA1; /* Message interface data A1 */
+ __IO uint32_t IF_DA2; /* Message interface data A2 */
+ __IO uint32_t IF_DB1; /* Message interface data B1 */
+ __IO uint32_t IF_DB2; /* Message interface data B2 */
+ __I uint32_t RESERVED[13];
} LPC_CCAN_IF_T;
-typedef struct { /*!< C_CAN Structure */
- __IO uint32_t CNTL; /*!< CAN control */
- __IO uint32_t STAT; /*!< Status register */
- __I uint32_t EC; /*!< Error counter */
- __IO uint32_t BT; /*!< Bit timing register */
- __I uint32_t INT; /*!< Interrupt register */
- __IO uint32_t TEST; /*!< Test register */
- __IO uint32_t BRPE; /*!< Baud rate prescaler extension register */
- __I uint32_t RESERVED0;
- LPC_CCAN_IF_T IF[2];
- __I uint32_t RESERVED2[8];
- __I uint32_t TXREQ1; /*!< Transmission request 1 */
- __I uint32_t TXREQ2; /*!< Transmission request 2 */
- __I uint32_t RESERVED3[6];
- __I uint32_t ND1; /*!< New data 1 */
- __I uint32_t ND2; /*!< New data 2 */
- __I uint32_t RESERVED4[6];
- __I uint32_t IR1; /*!< Interrupt pending 1 */
- __I uint32_t IR2; /*!< Interrupt pending 2 */
- __I uint32_t RESERVED5[6];
- __I uint32_t MSGV1; /*!< Message valid 1 */
- __I uint32_t MSGV2; /*!< Message valid 2 */
- __I uint32_t RESERVED6[6];
- __IO uint32_t CLKDIV; /*!< CAN clock divider register */
+typedef struct { /* C_CAN Structure */
+ __IO uint32_t CNTL; /* CAN control */
+ __IO uint32_t STAT; /* Status register */
+ __I uint32_t EC; /* Error counter */
+ __IO uint32_t BT; /* Bit timing register */
+ __I uint32_t INT; /* Interrupt register */
+ __IO uint32_t TEST; /* Test register */
+ __IO uint32_t BRPE; /* Baud rate prescaler extension register */
+ __I uint32_t RESERVED0;
+ LPC_CCAN_IF_T IF[2];
+ __I uint32_t RESERVED2[8];
+ __I uint32_t TXREQ1; /* Transmission request 1 */
+ __I uint32_t TXREQ2; /* Transmission request 2 */
+ __I uint32_t RESERVED3[6];
+ __I uint32_t ND1; /* New data 1 */
+ __I uint32_t ND2; /* New data 2 */
+ __I uint32_t RESERVED4[6];
+ __I uint32_t IR1; /* Interrupt pending 1 */
+ __I uint32_t IR2; /* Interrupt pending 2 */
+ __I uint32_t RESERVED5[6];
+ __I uint32_t MSGV1; /* Message valid 1 */
+ __I uint32_t MSGV2; /* Message valid 2 */
+ __I uint32_t RESERVED6[6];
+ __IO uint32_t CLKDIV; /* CAN clock divider register */
} LPC_CCAN_T;
-/**
- * @brief Repetitive Interrupt Timer register block structure
+/* ---------------------------------------------------------------------------
+ * Repetitive Interrupt Timer register block structure
*/
#define LPC_RITIMER_BASE 0x400C0000
-typedef struct { /*!< RITIMER Structure */
- __IO uint32_t COMPVAL; /*!< Compare register */
- __IO uint32_t MASK; /*!< Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
- __IO uint32_t CTRL; /*!< Control register. */
- __IO uint32_t COUNTER; /*!< 32-bit counter */
-#if defined(CHIP_LPC1347)
- __IO uint32_t COMPVAL_H; /*!< Compare upper register */
- __IO uint32_t MASK_H; /*!< Mask upper register */
- __I uint32_t RESERVED0[1];
- __IO uint32_t COUNTER_H; /*!< Counter upper register */
-#endif
+typedef struct { /* RITIMER Structure */
+ __IO uint32_t COMPVAL; /* Compare register */
+ __IO uint32_t MASK; /* Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
+ __IO uint32_t CTRL; /* Control register. */
+ __IO uint32_t COUNTER; /* 32-bit counter */
} LPC_RITIMER_T;
-/**
- * @brief Quadrature Encoder Interface register block structure
+/* ---------------------------------------------------------------------------
+ * Quadrature Encoder Interface register block structure
*/
#define LPC_QEI_BASE 0x400C6000
-typedef struct { /*!< QEI Structure */
- __O uint32_t CON; /*!< Control register */
- __I uint32_t STAT; /*!< Encoder status register */
- __IO uint32_t CONF; /*!< Configuration register */
- __I uint32_t POS; /*!< Position register */
- __IO uint32_t MAXPOS; /*!< Maximum position register */
- __IO uint32_t CMPOS0; /*!< position compare register 0 */
- __IO uint32_t CMPOS1; /*!< position compare register 1 */
- __IO uint32_t CMPOS2; /*!< position compare register 2 */
- __I uint32_t INXCNT; /*!< Index count register */
- __IO uint32_t INXCMP0; /*!< Index compare register 0 */
- __IO uint32_t LOAD; /*!< Velocity timer reload register */
- __I uint32_t TIME; /*!< Velocity timer register */
- __I uint32_t VEL; /*!< Velocity counter register */
- __I uint32_t CAP; /*!< Velocity capture register */
- __IO uint32_t VELCOMP; /*!< Velocity compare register */
- __IO uint32_t FILTERPHA; /*!< Digital filter register on input phase A (QEI_A) */
- __IO uint32_t FILTERPHB; /*!< Digital filter register on input phase B (QEI_B) */
- __IO uint32_t FILTERINX; /*!< Digital filter register on input index (QEI_IDX) */
- __IO uint32_t WINDOW; /*!< Index acceptance window register */
- __IO uint32_t INXCMP1; /*!< Index compare register 1 */
- __IO uint32_t INXCMP2; /*!< Index compare register 2 */
- __I uint32_t RESERVED0[993];
- __O uint32_t IEC; /*!< Interrupt enable clear register */
- __O uint32_t IES; /*!< Interrupt enable set register */
- __I uint32_t INTSTAT; /*!< Interrupt status register */
- __I uint32_t IE; /*!< Interrupt enable register */
- __O uint32_t CLR; /*!< Interrupt status clear register */
- __O uint32_t SET; /*!< Interrupt status set register */
+typedef struct { /* QEI Structure */
+ __O uint32_t CON; /* Control register */
+ __I uint32_t STAT; /* Encoder status register */
+ __IO uint32_t CONF; /* Configuration register */
+ __I uint32_t POS; /* Position register */
+ __IO uint32_t MAXPOS; /* Maximum position register */
+ __IO uint32_t CMPOS0; /* position compare register 0 */
+ __IO uint32_t CMPOS1; /* position compare register 1 */
+ __IO uint32_t CMPOS2; /* position compare register 2 */
+ __I uint32_t INXCNT; /* Index count register */
+ __IO uint32_t INXCMP0; /* Index compare register 0 */
+ __IO uint32_t LOAD; /* Velocity timer reload register */
+ __I uint32_t TIME; /* Velocity timer register */
+ __I uint32_t VEL; /* Velocity counter register */
+ __I uint32_t CAP; /* Velocity capture register */
+ __IO uint32_t VELCOMP; /* Velocity compare register */
+ __IO uint32_t FILTERPHA; /* Digital filter register on input phase A (QEI_A) */
+ __IO uint32_t FILTERPHB; /* Digital filter register on input phase B (QEI_B) */
+ __IO uint32_t FILTERINX; /* Digital filter register on input index (QEI_IDX) */
+ __IO uint32_t WINDOW; /* Index acceptance window register */
+ __IO uint32_t INXCMP1; /* Index compare register 1 */
+ __IO uint32_t INXCMP2; /* Index compare register 2 */
+ __I uint32_t RESERVED0[993];
+ __O uint32_t IEC; /* Interrupt enable clear register */
+ __O uint32_t IES; /* Interrupt enable set register */
+ __I uint32_t INTSTAT; /* Interrupt status register */
+ __I uint32_t IE; /* Interrupt enable register */
+ __O uint32_t CLR; /* Interrupt status clear register */
+ __O uint32_t SET; /* Interrupt status set register */
} LPC_QEI_T;
-/**
- * @brief Global Input Multiplexer Array (GIMA) register block structure
+/* ---------------------------------------------------------------------------
+ * Global Input Multiplexer Array (GIMA) register block structure
*/
#define LPC_GIMA_BASE 0x400C7000
-typedef struct { /*!< GIMA Structure */
- __IO uint32_t CAP0_IN[4][4]; /*!< Timer x CAP0_y capture input multiplexer (GIMA output ((x*4)+y)) */
- __IO uint32_t CTIN_IN[8]; /*!< SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
- __IO uint32_t VADC_TRIGGER_IN; /*!< VADC trigger input multiplexer (GIMA output 24) */
- __IO uint32_t EVENTROUTER_13_IN; /*!< Event router input 13 multiplexer (GIMA output 25) */
- __IO uint32_t EVENTROUTER_14_IN; /*!< Event router input 14 multiplexer (GIMA output 26) */
- __IO uint32_t EVENTROUTER_16_IN; /*!< Event router input 16 multiplexer (GIMA output 27) */
- __IO uint32_t ADCSTART0_IN; /*!< ADC start0 input multiplexer (GIMA output 28) */
- __IO uint32_t ADCSTART1_IN; /*!< ADC start1 input multiplexer (GIMA output 29) */
+typedef struct { /* GIMA Structure */
+ __IO uint32_t CAP0_IN[4][4]; /* Timer x CAP0_y capture input multiplexer (GIMA output ((x*4)+y)) */
+ __IO uint32_t CTIN_IN[8]; /* SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
+ __IO uint32_t VADC_TRIGGER_IN; /* VADC trigger input multiplexer (GIMA output 24) */
+ __IO uint32_t EVENTROUTER_13_IN; /* Event router input 13 multiplexer (GIMA output 25) */
+ __IO uint32_t EVENTROUTER_14_IN; /* Event router input 14 multiplexer (GIMA output 26) */
+ __IO uint32_t EVENTROUTER_16_IN; /* Event router input 16 multiplexer (GIMA output 27) */
+ __IO uint32_t ADCSTART0_IN; /* ADC start0 input multiplexer (GIMA output 28) */
+ __IO uint32_t ADCSTART1_IN; /* ADC start1 input multiplexer (GIMA output 29) */
} LPC_GIMA_T;
-/**
- * @brief DAC register block structure
+/* ---------------------------------------------------------------------------
+ * DAC register block structure
*/
#define LPC_DAC_BASE 0x400E1000
-typedef struct { /*!< DAC Structure */
- __IO uint32_t CR; /*!< DAC register. Holds the conversion data. */
- __IO uint32_t CTRL; /*!< DAC control register. */
- __IO uint32_t CNTVAL; /*!< DAC counter value register. */
+typedef struct { /* DAC Structure */
+ __IO uint32_t CR; /* DAC register. Holds the conversion data. */
+ __IO uint32_t CTRL; /* DAC control register. */
+ __IO uint32_t CNTVAL; /* DAC counter value register. */
} LPC_DAC_T;
/* After the selected settling time after this field is written with a
@@ -1684,7 +1784,9 @@
* is VALUE/1024 ? VREF
*/
#define DAC_RANGE 0x3FF
-#define DAC_VALUE(n) ((uint32_t) ((n & DAC_RANGE) << 6))
+#define DAC_SET(n) ((uint32_t) ((n & DAC_RANGE) << 6))
+#define DAC_GET(n) ((uint32_t) ((n >> 6) & DAC_RANGE))
+#define DAC_VALUE(n) DAC_SET(n)
/* If this bit = 0: The settling time of the DAC is 1 microsecond max,
* and the maximum current is 700 microAmpere
* If this bit = 1: The settling time of the DAC is 2.5 microsecond
@@ -1700,93 +1802,112 @@
#define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
/* Current option in DAC configuration option */
-typedef enum IP_DAC_CURRENT_OPT {
- DAC_MAX_UPDATE_RATE_1MHz = 0, /*!< Shorter settling times and higher power consumption;
- allows for a maximum update rate of 1 MHz */
- DAC_MAX_UPDATE_RATE_400kHz /*!< Longer settling times and lower power consumption;
- allows for a maximum update rate of 400 kHz */
-} IP_DAC_CURRENT_OPT_T;
+typedef enum DAC_CURRENT_OPT {
+ DAC_MAX_UPDATE_RATE_1MHz = 0, /* Shorter settling times and higher power consumption;
+ allows for a maximum update rate of 1 MHz */
+ DAC_MAX_UPDATE_RATE_400kHz /* Longer settling times and lower power consumption;
+ allows for a maximum update rate of 400 kHz */
+} DAC_CURRENT_OPT_T;
-/**
- * @brief ADC register block structure
+/* ---------------------------------------------------------------------------
+ * ADC register block structure
*/
#define LPC_ADC0_BASE 0x400E3000
#define LPC_ADC1_BASE 0x400E4000
#define ADC_ACC_10BITS
-/**
- * @brief 10 or 12-bit ADC register block structure
+/* ---------------------------------------------------------------------------
+ * 10 or 12-bit ADC register block structure
*/
-typedef struct { /*!< ADCn Structure */
- __IO uint32_t CR; /*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
- __I uint32_t GDR; /*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */
- __I uint32_t RESERVED0;
- __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
- __I uint32_t DR[8]; /*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
- __I uint32_t STAT; /*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
+typedef struct { /* ADCn Structure */
+ __IO uint32_t CR; /* A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
+ __I uint32_t GDR; /* A/D Global Data Register. Contains the result of the most recent A/D conversion. */
+ __I uint32_t RESERVED0;
+ __IO uint32_t INTEN; /* A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
+ __I uint32_t DR[8]; /* A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
+ __I uint32_t STAT; /* A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
} LPC_ADC_T;
/* ADC register support bitfields and mask */
#define ADC_RANGE 0x3FF
-#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /*!< Mask for getting the 10 bits ADC data read value */
-#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /*!< Number of ADC accuracy bits */
-#define ADC_DR_DONE(n) (((n) >> 31)) /*!< Mask for reading the ADC done status */
-#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /*!< Mask for reading the ADC overrun status */
-#define ADC_CR_CH_SEL(n) ((1UL << (n))) /*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
-#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
-#define ADC_CR_BURST ((1UL << 16)) /*!< Repeated conversions A/D enable bit */
-#define ADC_CR_PDN ((1UL << 21)) /*!< ADC convert is operational */
-#define ADC_CR_START_MASK ((7UL << 24)) /*!< ADC start mask bits */
-#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /*!< Select Start Mode */
-#define ADC_CR_START_NOW ((1UL << 24)) /*!< Start conversion now */
-#define ADC_CR_START_CTOUT15 ((2UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
-#define ADC_CR_START_CTOUT8 ((3UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
-#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
-#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
-#define ADC_CR_START_MCOA2 ((6UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
-#define ADC_CR_EDGE ((1UL << 27)) /*!< Start conversion on a falling edge on the selected CAP/MAT signal */
+#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /* Mask for getting the 10 bits ADC data read value */
+#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /* Number of ADC accuracy bits */
+#define ADC_DR_DONE(n) (((n) >> 31)) /* Mask for reading the ADC done status */
+#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /* Mask for reading the ADC overrun status */
+#define ADC_CR_CH_SEL(n) ((1UL << (n))) /* Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
+#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /* The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
+#define ADC_CR_BURST ((1UL << 16)) /* Repeated conversions A/D enable bit */
+#define ADC_CR_PDN ((1UL << 21)) /* ADC convert is operational */
+#define ADC_CR_START_MASK ((7UL << 24)) /* ADC start mask bits */
+#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /* Select Start Mode */
+#define ADC_CR_START_NOW ((1UL << 24)) /* Start conversion now */
+#define ADC_CR_START_CTOUT15 ((2UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
+#define ADC_CR_START_CTOUT8 ((3UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
+#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
+#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
+#define ADC_CR_START_MCOA2 ((6UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
+#define ADC_CR_EDGE ((1UL << 27)) /* Start conversion on a falling edge on the selected CAP/MAT signal */
#define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07) | ADC_CR_PDN)
-/* ADC status register used for IP drivers */
-typedef enum IP_ADC_STATUS {
- ADC_DR_DONE_STAT, /*!< ADC data register staus */
- ADC_DR_OVERRUN_STAT,/*!< ADC data overrun staus */
- ADC_DR_ADINT_STAT /*!< ADC interrupt status */
-} IP_ADC_STATUS_T;
+/* ADC status register used for IP drivers */
+typedef enum ADC_STATUS {
+ ADC_DR_DONE_STAT, /* ADC data register staus */
+ ADC_DR_OVERRUN_STAT,/* ADC data overrun staus */
+ ADC_DR_ADINT_STAT /* ADC interrupt status */
+} ADC_STATUS_T;
-/**
- * @brief GPIO port register block structure
+/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
+typedef enum ADC_START_MODE {
+ ADC_NO_START = 0,
+ ADC_START_NOW, /* Start conversion now */
+ ADC_START_ON_CTOUT15, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
+ ADC_START_ON_CTOUT8, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
+ ADC_START_ON_ADCTRIG0, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
+ ADC_START_ON_ADCTRIG1, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
+ ADC_START_ON_MCOA2 /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
+} ADC_START_MODE_T;
+
+/* ---------------------------------------------------------------------------
+ * GPIO port register block structure
*/
#define LPC_GPIO_PORT_BASE 0x400F4000
+#define LPC_GPIO0_BASE (LPC_GPIO_PORT_BASE)
+#define LPC_GPIO1_BASE (LPC_GPIO_PORT_BASE + 0x04)
+#define LPC_GPIO2_BASE (LPC_GPIO_PORT_BASE + 0x08)
+#define LPC_GPIO3_BASE (LPC_GPIO_PORT_BASE + 0x0C)
+#define LPC_GPIO4_BASE (LPC_GPIO_PORT_BASE + 0x10)
+#define LPC_GPIO5_BASE (LPC_GPIO_PORT_BASE + 0x14)
+#define LPC_GPIO6_BASE (LPC_GPIO_PORT_BASE + 0x18)
+#define LPC_GPIO7_BASE (LPC_GPIO_PORT_BASE + 0x1C)
-typedef struct { /*!< GPIO_PORT Structure */
- __IO uint8_t B[128][32]; /*!< Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
- __IO uint32_t W[32][32]; /*!< Offset 0x1000: Word pin registers port 0 to n */
- __IO uint32_t DIR[32]; /*!< Offset 0x2000: Direction registers port n */
- __IO uint32_t MASK[32]; /*!< Offset 0x2080: Mask register port n */
- __IO uint32_t PIN[32]; /*!< Offset 0x2100: Portpin register port n */
- __IO uint32_t MPIN[32]; /*!< Offset 0x2180: Masked port register port n */
- __IO uint32_t SET[32]; /*!< Offset 0x2200: Write: Set register for port n Read: output bits for port n */
- __O uint32_t CLR[32]; /*!< Offset 0x2280: Clear port n */
- __O uint32_t NOT[32]; /*!< Offset 0x2300: Toggle port n */
+typedef struct { /* GPIO_PORT Structure */
+ __IO uint8_t B[128][32]; /* Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
+ __IO uint32_t W[32][32]; /* Offset 0x1000: Word pin registers port 0 to n */
+ __IO uint32_t DIR[32]; /* Offset 0x2000: Direction registers port n */
+ __IO uint32_t MASK[32]; /* Offset 0x2080: Mask register port n */
+ __IO uint32_t PIN[32]; /* Offset 0x2100: Portpin register port n */
+ __IO uint32_t MPIN[32]; /* Offset 0x2180: Masked port register port n */
+ __IO uint32_t SET[32]; /* Offset 0x2200: Write: Set register for port n Read: output bits for port n */
+ __O uint32_t CLR[32]; /* Offset 0x2280: Clear port n */
+ __O uint32_t NOT[32]; /* Offset 0x2300: Toggle port n */
} LPC_GPIO_T;
/* Calculate GPIO offset and port register address from group and pin number */
#define GPIO_OFF(port, pin) ((port << 5) + pin)
#define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
-/**
- * @brief SPI register block structure
+/* ---------------------------------------------------------------------------
+ * SPI register block structure
*/
#define LPC_SPI_BASE 0x40100000
-typedef struct { /*!< SPI Structure */
- __IO uint32_t CR; /*!< SPI Control Register. This register controls the operation of the SPI. */
- __I uint32_t SR; /*!< SPI Status Register. This register shows the status of the SPI. */
- __IO uint32_t DR; /*!< SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. */
- __IO uint32_t CCR; /*!< SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
- __I uint32_t RESERVED0[3];
- __IO uint32_t INT; /*!< SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
+typedef struct { /* SPI Structure */
+ __IO uint32_t CR; /* SPI Control Register. This register controls the operation of the SPI. */
+ __I uint32_t SR; /* SPI Status Register. This register shows the status of the SPI. */
+ __IO uint32_t DR; /* SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. */
+ __IO uint32_t CCR; /* SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
+ __I uint32_t RESERVED0[3];
+ __IO uint32_t INT; /* SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
} LPC_SPI_T;
/* SPI CFG Register BitMask */
@@ -1796,36 +1917,36 @@
/* Mask of field of bit controlling */
#define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
/* Set the number of bits per a transfer */
-#define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
+#define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
/* SPI Clock Phase Select*/
-#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
-#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /*Change data on the first edge, Capture data on the following edge*/
+#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
+#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /* Change data on the first edge, Capture data on the following edge*/
/* SPI Clock Polarity Select*/
-#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
-#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
+#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
+#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
/* SPI Slave Mode Select */
#define SPI_CR_SLAVE_EN ((uint32_t) 0)
/* SPI Master Mode Select */
#define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
/* SPI MSB First mode enable */
-#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/
+#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /* Data will be transmitted and received in standard order (MSB first).*/
/* SPI LSB First mode enable */
-#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /*Data will be transmitted and received in reverse order (LSB first).*/
+#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /* Data will be transmitted and received in reverse order (LSB first).*/
/* SPI interrupt enable */
#define SPI_CR_INT_EN ((uint32_t) (1 << 7))
/* SPI STAT Register BitMask */
#define SPI_SR_BITMASK ((uint32_t) 0xF8)
/* Slave abort Flag */
-#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
+#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
/* Mode fault Flag */
-#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
+#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
/* Read overrun flag*/
-#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
+#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
/* Write collision flag. */
-#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
+#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
/* SPI transfer complete flag. */
-#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
-/**SPI error flag */
+#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
+/* SPI error flag */
#define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
/* Enable SPI Test Mode */
#define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
@@ -1836,79 +1957,79 @@
/* SPI Mode*/
typedef enum LPC_SPI_MODE {
- SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
- SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
+ SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
+ SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
} LPC_SPI_MODE_T;
/* SPI Clock Mode*/
typedef enum LPC_SPI_CLOCK_MODE {
- SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, /**< CPHA = 0, CPOL = 0 */
- SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, /**< CPHA = 0, CPOL = 1 */
- SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, /**< CPHA = 1, CPOL = 0 */
- SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, /**< CPHA = 1, CPOL = 1 */
- SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /**< alias */
- SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /**< alias */
- SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /**< alias */
- SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /**< alias */
+ SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 0 */
+ SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 1 */
+ SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 0 */
+ SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 1 */
+ SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /* alias */
+ SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /* alias */
+ SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /* alias */
+ SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /* alias */
} LPC_SPI_CLOCK_MODE_T;
/* SPI Data Order Mode*/
typedef enum LPC_SPI_DATA_ORDER {
- SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
- SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
+ SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
+ SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
} LPC_SPI_DATA_ORDER_T;
-/**
- * @brief Serial GPIO register block structure
+/* ---------------------------------------------------------------------------
+ * Serial GPIO register block structure
*/
#define LPC_SGPIO_BASE 0x40101000
-typedef struct { /*!< SGPIO Structure */
- __IO uint32_t OUT_MUX_CFG[16]; /*!< Pin multiplexer configurationregisters. */
- __IO uint32_t SGPIO_MUX_CFG[16]; /*!< SGPIO multiplexer configuration registers. */
- __IO uint32_t SLICE_MUX_CFG[16]; /*!< Slice multiplexer configuration registers. */
- __IO uint32_t REG[16]; /*!< Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
- __IO uint32_t REG_SS[16]; /*!< Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
- __IO uint32_t PRESET[16]; /*!< Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
- __IO uint32_t COUNT[16]; /*!< Down counter, counts down each clock cycle. */
- __IO uint32_t POS[16]; /*!< Each time COUNT0 reaches 0x0 */
- __IO uint32_t MASK_A; /*!< Mask for pattern match function of slice A */
- __IO uint32_t MASK_H; /*!< Mask for pattern match function of slice H */
- __IO uint32_t MASK_I; /*!< Mask for pattern match function of slice I */
- __IO uint32_t MASK_P; /*!< Mask for pattern match function of slice P */
- __I uint32_t GPIO_INREG; /*!< GPIO input status register */
- __IO uint32_t GPIO_OUTREG; /*!< GPIO output control register */
- __IO uint32_t GPIO_OENREG; /*!< GPIO OE control register */
- __IO uint32_t CTRL_ENABLED; /*!< Enables the slice COUNT counter */
- __IO uint32_t CTRL_DISABLED; /*!< Disables the slice COUNT counter */
- __I uint32_t RESERVED0[823];
- __O uint32_t CLR_EN_0; /*!< Shift clock interrupt clear mask */
- __O uint32_t SET_EN_0; /*!< Shift clock interrupt set mask */
- __I uint32_t ENABLE_0; /*!< Shift clock interrupt enable */
- __I uint32_t STATUS_0; /*!< Shift clock interrupt status */
- __O uint32_t CTR_STATUS_0; /*!< Shift clock interrupt clear status */
- __O uint32_t SET_STATUS_0; /*!< Shift clock interrupt set status */
- __I uint32_t RESERVED1[2];
- __O uint32_t CLR_EN_1; /*!< Capture clock interrupt clear mask */
- __O uint32_t SET_EN_1; /*!< Capture clock interrupt set mask */
- __I uint32_t ENABLE_1; /*!< Capture clock interrupt enable */
- __I uint32_t STATUS_1; /*!< Capture clock interrupt status */
- __O uint32_t CTR_STATUS_1; /*!< Capture clock interrupt clear status */
- __O uint32_t SET_STATUS_1; /*!< Capture clock interrupt set status */
- __I uint32_t RESERVED2[2];
- __O uint32_t CLR_EN_2; /*!< Pattern match interrupt clear mask */
- __O uint32_t SET_EN_2; /*!< Pattern match interrupt set mask */
- __I uint32_t ENABLE_2; /*!< Pattern match interrupt enable */
- __I uint32_t STATUS_2; /*!< Pattern match interrupt status */
- __O uint32_t CTR_STATUS_2; /*!< Pattern match interrupt clear status */
- __O uint32_t SET_STATUS_2; /*!< Pattern match interrupt set status */
- __I uint32_t RESERVED3[2];
- __O uint32_t CLR_EN_3; /*!< Input interrupt clear mask */
- __O uint32_t SET_EN_3; /*!< Input bit match interrupt set mask */
- __I uint32_t ENABLE_3; /*!< Input bit match interrupt enable */
- __I uint32_t STATUS_3; /*!< Input bit match interrupt status */
- __O uint32_t CTR_STATUS_3; /*!< Input bit match interrupt clear status */
- __O uint32_t SET_STATUS_3; /*!< Shift clock interrupt set status */
+typedef struct { /* SGPIO Structure */
+ __IO uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configurationregisters. */
+ __IO uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. */
+ __IO uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. */
+ __IO uint32_t REG[16]; /* Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
+ __IO uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
+ __IO uint32_t PRESET[16]; /* Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
+ __IO uint32_t COUNT[16]; /* Down counter, counts down each clock cycle. */
+ __IO uint32_t POS[16]; /* Each time COUNT0 reaches 0x0 */
+ __IO uint32_t MASK_A; /* Mask for pattern match function of slice A */
+ __IO uint32_t MASK_H; /* Mask for pattern match function of slice H */
+ __IO uint32_t MASK_I; /* Mask for pattern match function of slice I */
+ __IO uint32_t MASK_P; /* Mask for pattern match function of slice P */
+ __I uint32_t GPIO_INREG; /* GPIO input status register */
+ __IO uint32_t GPIO_OUTREG; /* GPIO output control register */
+ __IO uint32_t GPIO_OENREG; /* GPIO OE control register */
+ __IO uint32_t CTRL_ENABLED; /* Enables the slice COUNT counter */
+ __IO uint32_t CTRL_DISABLED; /* Disables the slice COUNT counter */
+ __I uint32_t RESERVED0[823];
+ __O uint32_t CLR_EN_0; /* Shift clock interrupt clear mask */
+ __O uint32_t SET_EN_0; /* Shift clock interrupt set mask */
+ __I uint32_t ENABLE_0; /* Shift clock interrupt enable */
+ __I uint32_t STATUS_0; /* Shift clock interrupt status */
+ __O uint32_t CTR_STATUS_0; /* Shift clock interrupt clear status */
+ __O uint32_t SET_STATUS_0; /* Shift clock interrupt set status */
+ __I uint32_t RESERVED1[2];
+ __O uint32_t CLR_EN_1; /* Capture clock interrupt clear mask */
+ __O uint32_t SET_EN_1; /* Capture clock interrupt set mask */
+ __I uint32_t ENABLE_1; /* Capture clock interrupt enable */
+ __I uint32_t STATUS_1; /* Capture clock interrupt status */
+ __O uint32_t CTR_STATUS_1; /* Capture clock interrupt clear status */
+ __O uint32_t SET_STATUS_1; /* Capture clock interrupt set status */
+ __I uint32_t RESERVED2[2];
+ __O uint32_t CLR_EN_2; /* Pattern match interrupt clear mask */
+ __O uint32_t SET_EN_2; /* Pattern match interrupt set mask */
+ __I uint32_t ENABLE_2; /* Pattern match interrupt enable */
+ __I uint32_t STATUS_2; /* Pattern match interrupt status */
+ __O uint32_t CTR_STATUS_2; /* Pattern match interrupt clear status */
+ __O uint32_t SET_STATUS_2; /* Pattern match interrupt set status */
+ __I uint32_t RESERVED3[2];
+ __O uint32_t CLR_EN_3; /* Input interrupt clear mask */
+ __O uint32_t SET_EN_3; /* Input bit match interrupt set mask */
+ __I uint32_t ENABLE_3; /* Input bit match interrupt enable */
+ __I uint32_t STATUS_3; /* Input bit match interrupt status */
+ __O uint32_t CTR_STATUS_3; /* Input bit match interrupt clear status */
+ __O uint32_t SET_STATUS_3; /* Shift clock interrupt set status */
} LPC_SGPIO_T;
/* End of section using anonymous unions */
@@ -1922,63 +2043,68 @@
/* Leave anonymous unions enabled */
#endif
-/**
- * @brief LPC43xx Peripheral register set declarations
+/* ---------------------------------------------------------------------------
+ * LPC43xx Peripheral register set declarations
*/
-#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
-#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
-#define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
-#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
-#define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
-#define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
-#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
-#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
-#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
-#define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
-#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
-#define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
-#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
-#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
-#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
-#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
-#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
-#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
-#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
-#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
-#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
-#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
-#define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
-#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
-#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
-#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
-#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
-#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
-#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
-#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
-#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
-#define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
-#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
-#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
-#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
-#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
-#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
-#define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
-#define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
-#define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
-#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
-#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
-#define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
-#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
-#define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
-#define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
-#define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
-#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
-#define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
-#define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
-
-/**
- * @}
- */
+#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
+#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
+#define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE)
+#define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
+#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
+#define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
+#define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
+#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
+#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
+#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
+#define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
+#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
+#define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
+#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
+#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
+#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
+#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
+#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
+#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
+#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
+#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
+#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
+#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
+#define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
+#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
+#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
+#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
+#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
+#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
+#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
+#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
+#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
+#define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
+#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
+#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
+#define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
+#define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
+#define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
+#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
+#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
+#define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
+#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
+#define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
+#define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
+#define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
+#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
+#define LPC_GPIO0 ((LPC_GPIO_T *) LPC_GPIO0_BASE)
+#define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
+#define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
+#define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
+#define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
+#define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
+#define LPC_GPIO6 ((LPC_GPIO_T *) LPC_GPIO6_BASE)
+#define LPC_GPIO7 ((LPC_GPIO_T *) LPC_GPIO7_BASE)
+#define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
+#define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
#ifdef __cplusplus
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/LPC43xx_spifi.ini Tue Jul 15 07:45:08 2014 +0100
@@ -0,0 +1,12 @@
+
+FUNC void Setup (unsigned int region) {
+ region &= 0xFF000000;
+ _WDWORD(0x40043100, region); // Set the shadow pointer
+ _WDWORD(0xE000ED08, 0); // Set the vector table offset to 0
+ SP = _RDWORD(0); // Setup Stack Pointer
+ PC = _RDWORD(4); // Setup Program Counter
+}
+
+LOAD %L INCREMENTAL
+Setup(0x14000000); // Get ready to execute image in QSPI
+
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/startup_LPC43xx.s Fri Jul 11 10:00:08 2014 +0100
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/startup_LPC43xx.s Tue Jul 15 07:45:08 2014 +0100
@@ -29,7 +29,8 @@
; * this code.
; */
-__initial_sp EQU 0x10020000 ; Top of first RAM segment for LPC43XX
+; __initial_sp EQU 0x10020000 ; Top of first RAM segment for LPC43XX (IRAM1)
+__initial_sp EQU 0x10092000 ; Top of first RAM segment for LPC43XX (IRAM2)
PRESERVE8
THUMB
@@ -121,19 +122,21 @@
AREA |.text|, CODE, READONLY
+
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
+ LDR R0, =SystemInit
+ BLX R0
LDR R0, =__main
BX R0
ENDP
-; Dummy Exception Handlers (infinite loops which can be modified)
+
+; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/LPC43xx.ld Fri Jul 11 10:00:08 2014 +0100
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/LPC43xx.ld Tue Jul 15 07:45:08 2014 +0100
@@ -1,19 +1,281 @@
-/*
- * LPC43XX Dual core Blinky stand-alone Cortex-M4 LD script
-*/
+/* mbed - LPC4330_M4 linker script
+ * Based linker script generated by Code Red Technologies Red Suite 7.0
+ */
+GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
MEMORY
{
/* Define each memory region */
- RO_MEM (rx) : ORIGIN = 0x14000000, LENGTH = 0x40000 /* 256K */
- RW_MEM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32k */
- RW_MEM1 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x4000 /* 16K */
- SH_MEM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x2000 /* 8k */
- FAT12_MEM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 /* 8k */
+ RamLoc128 (rwx) : ORIGIN = 0x10000118, LENGTH = 0x1FEE8 /* 128K bytes */
+ RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes */
+ RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes */
+ RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes */
+ RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes */
+ SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 0x400000 /* 4M bytes */
+
}
+ /* Define a symbol for the top of each memory region */
+ __top_RamLoc128 = 0x10000000 + 0x20000;
+ __top_RamLoc72 = 0x10080000 + 0x12000;
+ __top_RamAHB32 = 0x20000000 + 0x8000;
+ __top_RamAHB16 = 0x20008000 + 0x4000;
+ __top_RamAHB_ETB16 = 0x2000c000 + 0x4000;
+ __top_SPIFI = 0x14000000 + 0x400000;
- __top_RW_MEM = 0x10000000 + 0x8000;
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ __vectors_start__ = ABSOLUTE(.) ;
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data));
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2));
+ LONG( SIZEOF(.data_RAM2));
+ LONG(LOADADDR(.data_RAM3));
+ LONG( ADDR(.data_RAM3));
+ LONG( SIZEOF(.data_RAM3));
+ LONG(LOADADDR(.data_RAM4));
+ LONG( ADDR(.data_RAM4));
+ LONG( SIZEOF(.data_RAM4));
+ LONG(LOADADDR(.data_RAM5));
+ LONG( ADDR(.data_RAM5));
+ LONG( SIZEOF(.data_RAM5));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ LONG( ADDR(.bss_RAM3));
+ LONG( SIZEOF(.bss_RAM3));
+ LONG( ADDR(.bss_RAM4));
+ LONG( SIZEOF(.bss_RAM4));
+ LONG( ADDR(.bss_RAM5));
+ LONG( SIZEOF(.bss_RAM5));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ } >SPIFI
+
+ .text : ALIGN(4)
+ {
+ *(.text*)
+ *(.rodata .rodata.* .constdata .constdata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ /* End C++ */
+ } > SPIFI
-INCLUDE "lpc43xx_dualcore_lib.ld"
-INCLUDE "lpc43xx_dualcore.ld"
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > SPIFI
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > SPIFI
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ /* DATA section for RamLoc72 */
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.ramfunc.$RAM2)
+ *(.ramfunc.$RamLoc72)
+ *(.data.$RAM2*)
+ *(.data.$RamLoc72*)
+ . = ALIGN(4) ;
+ } > RamLoc72 AT>SPIFI
+
+ /* DATA section for RamAHB32 */
+ .data_RAM3 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.ramfunc.$RAM3)
+ *(.ramfunc.$RamAHB32)
+ *(.data.$RAM3*)
+ *(.data.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32 AT>SPIFI
+
+ /* DATA section for RamAHB16 */
+ .data_RAM4 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.ramfunc.$RAM4)
+ *(.ramfunc.$RamAHB16)
+ *(.data.$RAM4*)
+ *(.data.$RamAHB16*)
+ . = ALIGN(4) ;
+ } > RamAHB16 AT>SPIFI
+
+ /* DATA section for RamAHB_ETB16 */
+ .data_RAM5 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.ramfunc.$RAM5)
+ *(.ramfunc.$RamAHB_ETB16)
+ *(.data.$RAM5*)
+ *(.data.$RamAHB_ETB16*)
+ . = ALIGN(4) ;
+ } > RamAHB_ETB16 AT>SPIFI
+
+ /* MAIN DATA SECTION */
+
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ . = ALIGN(4) ;
+ _end_uninit_RESERVED = .;
+ } > RamLoc128
+
+
+ /* Main DATA section (RamLoc128) */
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = . ;
+ *(vtable)
+ *(.ramfunc*)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = . ;
+ } > RamLoc128 AT>SPIFI
+
+ /* BSS section for RamLoc72 */
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamLoc72*)
+ . = ALIGN(4) ;
+ } > RamLoc72
+ /* BSS section for RamAHB32 */
+ .bss_RAM3 : ALIGN(4)
+ {
+ *(.bss.$RAM3*)
+ *(.bss.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+ /* BSS section for RamAHB16 */
+ .bss_RAM4 : ALIGN(4)
+ {
+ *(.bss.$RAM4*)
+ *(.bss.$RamAHB16*)
+ . = ALIGN(4) ;
+ } > RamAHB16
+ /* BSS section for RamAHB_ETB16 */
+ .bss_RAM5 : ALIGN(4)
+ {
+ *(.bss.$RAM5*)
+ *(.bss.$RamAHB_ETB16*)
+ . = ALIGN(4) ;
+ } > RamAHB_ETB16
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc128
+
+ /* NOINIT section for RamLoc72 */
+ .noinit_RAM2 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM2*)
+ *(.noinit.$RamLoc72*)
+ . = ALIGN(4) ;
+ } > RamLoc72
+ /* NOINIT section for RamAHB32 */
+ .noinit_RAM3 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM3*)
+ *(.noinit.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+ /* NOINIT section for RamAHB16 */
+ .noinit_RAM4 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM4*)
+ *(.noinit.$RamAHB16*)
+ . = ALIGN(4) ;
+ } > RamAHB16
+ /* NOINIT section for RamAHB_ETB16 */
+ .noinit_RAM5 (NOLOAD) : ALIGN(4)
+ {
+ *(.noinit.$RAM5*)
+ *(.noinit.$RamAHB_ETB16*)
+ . = ALIGN(4) ;
+ } > RamAHB_ETB16
+
+ /* DEFAULT NOINIT SECTION */
+ .noinit (NOLOAD): ALIGN(4)
+ {
+ _noinit = .;
+ *(.noinit*)
+ . = ALIGN(4) ;
+ _end_noinit = .;
+ } > RamLoc128
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc128 - 0);
+}
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/startup_LPC43xx.cpp Fri Jul 11 10:00:08 2014 +0100
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/startup_LPC43xx.cpp Tue Jul 15 07:45:08 2014 +0100
@@ -1,10 +1,10 @@
-// *****************************************************************************
-// +--+
-// | ++----+
-// +-++ |
-// | |
-// +-+--+ |
-// | +--+--+
+//*****************************************************************************
+// +--+
+// | ++----+
+// +-++ |
+// | |
+// +-+--+ |
+// | +--+--+
// +----+ Copyright (c) 2011-12 Code Red Technologies Ltd.
//
// LPC43xx Microcontroller Startup code for use with Red Suite
@@ -12,62 +12,58 @@
// Version : 120430
//
// Software License Agreement
-//
+//
// The software is owned by Code Red Technologies and/or its suppliers, and is
-// protected under applicable copyright laws. All rights are reserved. Any
-// use in violation of the foregoing restrictions may subject the user to criminal
-// sanctions under applicable laws, as well as to civil liability for the breach
+// protected under applicable copyright laws. All rights are reserved. Any
+// use in violation of the foregoing restrictions may subject the user to criminal
+// sanctions under applicable laws, as well as to civil liability for the breach
// of the terms and conditions of this license.
-//
+//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
-// CODE RED TECHNOLOGIES LTD.
+// CODE RED TECHNOLOGIES LTD.
//
-// *****************************************************************************
-#if defined(__cplusplus)
+//*****************************************************************************
+#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
-// *****************************************************************************
+//*****************************************************************************
//
// The entry point for the C++ library startup
//
-// *****************************************************************************
+//*****************************************************************************
extern "C" {
-extern void __libc_init_array(void);
-
+ extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
-#define ALIAS(f) __attribute__ ((weak, alias(# f)))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
-//#if defined (__USE_CMSIS)
+// Code Red - if CMSIS is being used, then SystemInit() routine
+// will be called by startup code rather than in application's main()
+#if defined (__USE_CMSIS)
#include "LPC43xx.h"
-//#endif
-
-#if defined(OS_UCOS_III)
-extern void OS_CPU_PendSVHandler(void);
-extern void OS_CPU_SysTickHandler (void);
#endif
-// *****************************************************************************
-#if defined(__cplusplus)
+//*****************************************************************************
+#if defined (__cplusplus)
extern "C" {
#endif
-// *****************************************************************************
+//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
-// When the application defines a handler (with the same name), this will
+// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
-// *****************************************************************************
-void ResetISR(void);
+//*****************************************************************************
+ void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
@@ -79,18 +75,19 @@
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
-// *****************************************************************************
+//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
-// defines a handler (with the same name), this will automatically take
+// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
-// *****************************************************************************
+//*****************************************************************************
void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
-void MX_CORE_IRQHandler(void) ALIAS(IntDefaultHandler);
+void M0CORE_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
-void FLASHEEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
+void EZH_IRQHandler(void) ALIAS(IntDefaultHandler);
+void FLASH_EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler);
void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
@@ -105,8 +102,8 @@
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI_IRQHandler (void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SPI_IRQHandler (void) ALIAS(IntDefaultHandler);
void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
@@ -130,157 +127,130 @@
void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void VADC_IRQHandler(void) ALIAS(IntDefaultHandler);
void ATIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void M0s_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
-// *****************************************************************************
+
+//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
-// *****************************************************************************
-#if defined(__REDLIB__)
+//*****************************************************************************
+#if defined (__REDLIB__)
extern void __main(void);
-
#endif
extern int main(void);
-
-// *****************************************************************************
+//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
-// *****************************************************************************
+//*****************************************************************************
extern void _vStackTop(void);
-// *****************************************************************************
-//
-// Application can define Stack size (If not defined, default stack size will
-// used
-//
-// *****************************************************************************
-#ifndef STACK_SIZE
-#define STACK_SIZE (0x200)
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
#endif
-
-// *****************************************************************************
-//
-// Application can define Heap size (If not defined, default Heap size will
-// used
-//
-// *****************************************************************************
-#ifndef HEAP_SIZE
-#define HEAP_SIZE (0x4000)
-#endif
-
-unsigned int __vStack[STACK_SIZE / sizeof(unsigned int)] __attribute__((section("STACK,\"aw\",%nobits@")));
-unsigned int __vHeap[HEAP_SIZE / sizeof(unsigned int)] __attribute__((section("HEAP,\"aw\",%nobits@")));
-
-// *****************************************************************************
-#if defined(__cplusplus)
-} // extern "C"
-#endif
-// *****************************************************************************
+//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
-// *****************************************************************************
-extern void(*const g_pfnVectors[]) (void);
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
-void(*const g_pfnVectors[]) (void) = {
- // Core Level - CM4/CM3
- &_vStackTop, // The initial stack pointer
- ResetISR, // The reset handler
- NMI_Handler, // The NMI handler
- HardFault_Handler, // The hard fault handler
- MemManage_Handler, // The MPU fault handler
- BusFault_Handler, // The bus fault handler
- UsageFault_Handler, // The usage fault handler
- 0, // Reserved
- 0, // Reserved
- 0, // Reserved
- 0, // Reserved
- SVC_Handler, // SVCall handler
- DebugMon_Handler, // Debug monitor handler
- 0, // Reserved
-#if defined(OS_UCOS_III)
- OS_CPU_PendSVHandler, // uCOS-III PendSV handler
- OS_CPU_SysTickHandler, // uCOS-III SysTick handler
-#else
- PendSV_Handler, // The PendSV handler
- SysTick_Handler, // The SysTick handler
-#endif
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM4
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ NMI_Handler, // The NMI handler
+ HardFault_Handler, // The hard fault handler
+ MemManage_Handler, // The MPU fault handler
+ BusFault_Handler, // The bus fault handler
+ UsageFault_Handler, // The usage fault handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ SVC_Handler, // SVCall handler
+ DebugMon_Handler, // Debug monitor handler
+ 0, // Reserved
+ PendSV_Handler, // The PendSV handler
+ SysTick_Handler, // The SysTick handler
- // Chip Level - LPC18xx/43xx
- DAC_IRQHandler, // 16 D/A Converter
- MX_CORE_IRQHandler, // 17 CortexM4/M0 (LPC43XX ONLY)
- DMA_IRQHandler, // 18 General Purpose DMA
- 0, // 19 Reserved
- FLASHEEPROM_IRQHandler, // 20 ORed flash Bank A, flash Bank B, EEPROM interrupts
- ETH_IRQHandler, // 21 Ethernet
- SDIO_IRQHandler, // 22 SD/MMC
- LCD_IRQHandler, // 23 LCD
- USB0_IRQHandler, // 24 USB0
- USB1_IRQHandler, // 25 USB1
- SCT_IRQHandler, // 26 State Configurable Timer
- RIT_IRQHandler, // 27 Repetitive Interrupt Timer
- TIMER0_IRQHandler, // 28 Timer0
- TIMER1_IRQHandler, // 29 Timer 1
- TIMER2_IRQHandler, // 30 Timer 2
- TIMER3_IRQHandler, // 31 Timer 3
- MCPWM_IRQHandler, // 32 Motor Control PWM
- ADC0_IRQHandler, // 33 A/D Converter 0
- I2C0_IRQHandler, // 34 I2C0
- I2C1_IRQHandler, // 35 I2C1
- SPI_IRQHandler, // 36 SPI (LPC43XX ONLY)
- ADC1_IRQHandler, // 37 A/D Converter 1
- SSP0_IRQHandler, // 38 SSP0
- SSP1_IRQHandler, // 39 SSP1
- UART0_IRQHandler, // 40 UART0
- UART1_IRQHandler, // 41 UART1
- UART2_IRQHandler, // 42 UART2
- UART3_IRQHandler, // 43 USRT3
- I2S0_IRQHandler, // 44 I2S0
- I2S1_IRQHandler, // 45 I2S1
- SPIFI_IRQHandler, // 46 SPI Flash Interface
- SGPIO_IRQHandler, // 47 SGPIO (LPC43XX ONLY)
- GPIO0_IRQHandler, // 48 GPIO0
- GPIO1_IRQHandler, // 49 GPIO1
- GPIO2_IRQHandler, // 50 GPIO2
- GPIO3_IRQHandler, // 51 GPIO3
- GPIO4_IRQHandler, // 52 GPIO4
- GPIO5_IRQHandler, // 53 GPIO5
- GPIO6_IRQHandler, // 54 GPIO6
- GPIO7_IRQHandler, // 55 GPIO7
- GINT0_IRQHandler, // 56 GINT0
- GINT1_IRQHandler, // 57 GINT1
- EVRT_IRQHandler, // 58 Event Router
- CAN1_IRQHandler, // 59 C_CAN1
- 0, // 60 Reserved
- 0, // 61 Reserved
- ATIMER_IRQHandler, // 62 ATIMER
- RTC_IRQHandler, // 63 RTC
- 0, // 64 Reserved
- WDT_IRQHandler, // 65 WDT
- 0, // 66 Reserved
- CAN0_IRQHandler, // 67 C_CAN0
- QEI_IRQHandler, // 68 QEI
-};
+ // Chip Level - LPC43
+ DAC_IRQHandler, // 16
+ M0CORE_IRQHandler, // 17
+ DMA_IRQHandler, // 18
+ EZH_IRQHandler, // 19
+ FLASH_EEPROM_IRQHandler, // 20
+ ETH_IRQHandler, // 21
+ SDIO_IRQHandler, // 22
+ LCD_IRQHandler, // 23
+ USB0_IRQHandler, // 24
+ USB1_IRQHandler, // 25
+ SCT_IRQHandler, // 26
+ RIT_IRQHandler, // 27
+ TIMER0_IRQHandler, // 28
+ TIMER1_IRQHandler, // 29
+ TIMER2_IRQHandler, // 30
+ TIMER3_IRQHandler, // 31
+ MCPWM_IRQHandler, // 32
+ ADC0_IRQHandler, // 33
+ I2C0_IRQHandler, // 34
+ I2C1_IRQHandler, // 35
+ SPI_IRQHandler, // 36
+ ADC1_IRQHandler, // 37
+ SSP0_IRQHandler, // 38
+ SSP1_IRQHandler, // 39
+ UART0_IRQHandler, // 40
+ UART1_IRQHandler, // 41
+ UART2_IRQHandler, // 42
+ UART3_IRQHandler, // 43
+ I2S0_IRQHandler, // 44
+ I2S1_IRQHandler, // 45
+ SPIFI_IRQHandler, // 46
+ SGPIO_IRQHandler, // 47
+ GPIO0_IRQHandler, // 48
+ GPIO1_IRQHandler, // 49
+ GPIO2_IRQHandler, // 50
+ GPIO3_IRQHandler, // 51
+ GPIO4_IRQHandler, // 52
+ GPIO5_IRQHandler, // 53
+ GPIO6_IRQHandler, // 54
+ GPIO7_IRQHandler, // 55
+ GINT0_IRQHandler, // 56
+ GINT1_IRQHandler, // 57
+ EVRT_IRQHandler, // 58
+ CAN1_IRQHandler, // 59
+ 0, // 60
+ VADC_IRQHandler, // 61
+ ATIMER_IRQHandler, // 62
+ RTC_IRQHandler, // 63
+ 0, // 64
+ WDT_IRQHandler, // 65
+ M0s_IRQHandler, // 66
+ CAN0_IRQHandler, // 67
+ QEI_IRQHandler, // 68
+ };
-// *****************************************************************************
+//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
-// *****************************************************************************
+//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
- unsigned int *pulDest = (unsigned int *) start;
- unsigned int *pulSrc = (unsigned int *) romstart;
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
@@ -288,49 +258,94 @@
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
- unsigned int *pulDest = (unsigned int *) start;
+ unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
-// *****************************************************************************
+//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
-// *****************************************************************************
+//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
-// *****************************************************************************
+//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//
-// *****************************************************************************
-
-extern "C" void software_init_hook(void) __attribute__((weak));
-
+//*****************************************************************************
void
ResetISR(void) {
- //
- // Copy the data sections from flash to SRAM.
- //
+// *************************************************************
+// The following conditional block of code manually resets as
+// much of the peripheral set of the LPC43 as possible. This is
+// done because the LPC43 does not provide a means of triggering
+// a full system reset under debugger control, which can cause
+// problems in certain circumstances when debugging.
+//
+// You can prevent this code block being included if you require
+// (for example when creating a final executable which you will
+// not debug) by setting the define 'DONT_RESET_ON_RESTART'.
+//
+#ifndef DONT_RESET_ON_RESTART
+
+ // Disable interrupts
+ __asm volatile ("cpsid i");
+ // equivalent to CMSIS '__disable_irq()' function
+
+ unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
+ // LPC_RGU->RESET_CTRL0 @ 0x40053100
+ // LPC_RGU->RESET_CTRL1 @ 0x40053104
+ // Note that we do not use the CMSIS register access mechanism,
+ // as there is no guarantee that the project has been configured
+ // to use CMSIS.
+
+ // Write to LPC_RGU->RESET_CTRL0
+ *(RESET_CONTROL+0) = 0x10DF0000;
+ // GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
+ // USB1_RST|USB0_RST|LCD_RST
+
+ // Write to LPC_RGU->RESET_CTRL1
+ *(RESET_CONTROL+1) = 0x01DFF7FF;
+ // M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
+ // I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
+ // DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
+ // RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST
+
+ // Clear all pending interrupts in the NVIC
+ volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
+ unsigned int irqpendloop;
+ for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
+ *(NVIC_ICPR+irqpendloop)= 0xFFFFFFFF;
+ }
+
+ // Reenable interrupts
+ __asm volatile ("cpsie i");
+ // equivalent to CMSIS '__enable_irq()' function
+
+#endif // ifndef DONT_RESET_ON_RESTART
+// *************************************************************
+
+
+ //
+ // Copy the data sections from flash to SRAM.
+ //
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
- /* Call SystemInit() for clocking/memory setup prior to scatter load */
- SystemInit();
-
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
- // Copy the data sections from flash to SRAM.
+ // Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
@@ -345,107 +360,141 @@
bss_init(ExeAddr, SectionLen);
}
- if (software_init_hook) // give control to the RTOS
- software_init_hook(); // this will also call __libc_init_array
- else {
- #if defined(__cplusplus)
- //
- // Call C++ library initialisation
- //
- __libc_init_array();
- #endif
+#if defined (__VFP_FP__) && !defined (__SOFTFP__)
+/*
+ * Code to enable the Cortex-M4 FPU only included
+ * if appropriate build options have been selected.
+ * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+ */
+ // CPACR is located at address 0xE000ED88
+ asm("LDR.W R0, =0xE000ED88");
+ // Read CPACR
+ asm("LDR R1, [R0]");
+ // Set bits 20-23 to enable CP10 and CP11 coprocessors
+ asm(" ORR R1, R1, #(0xF << 20)");
+ // Write back the modified value to the CPACR
+ asm("STR R1, [R0]");
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+
+ // ******************************
+ // Check to see if we are running the code from a non-zero
+ // address (eg RAM, external flash), in which case we need
+ // to modify the VTOR register to tell the CPU that the
+ // vector table is located at a non-0x0 address.
- #if defined(__REDLIB__)
- // Call the Redlib library, which in turn calls main()
- __main();
- #else
- main();
- #endif
- }
+ // Note that we do not use the CMSIS register access mechanism,
+ // as there is no guarantee that the project has been configured
+ // to use CMSIS.
+ unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
+ if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
+ // CMSIS : SCB->VTOR = <address of vector table>
+ *pSCB_VTOR = (unsigned int)g_pfnVectors;
+ }
+
+#ifdef __USE_CMSIS
+ SystemInit();
+#endif
+
+#if defined (__cplusplus)
+ //
+ // Call C++ library initialisation
//
- // main() shouldn't return, but if it does, we'll just enter an infinite loop
+ __libc_init_array();
+#endif
+
+#if defined (__REDLIB__)
+ // Call the Redlib library, which in turn calls main()
+ __main() ;
+#else
+ main();
+#endif
+
//
- while (1) {}
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1) {
+ ;
+ }
}
-// *****************************************************************************
+//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
-// *****************************************************************************
+//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void)
{
- while (1) {}
+ while(1)
+ {
+ }
}
-
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void)
{
- while (1) {}
+ while(1)
+ {
+ }
}
-
__attribute__ ((section(".after_vectors")))
void MemManage_Handler(void)
{
- while (1) {}
+ while(1)
+ {
+ }
}
-
__attribute__ ((section(".after_vectors")))
void BusFault_Handler(void)
{
- while (1) {}
+ while(1)
+ {
+ }
}
-
__attribute__ ((section(".after_vectors")))
void UsageFault_Handler(void)
{
- while (1) {}
+ while(1)
+ {
+ }
}
-
__attribute__ ((section(".after_vectors")))
void SVC_Handler(void)
{
- while (1) {}
+ while(1)
+ {
+ }
}
-
__attribute__ ((section(".after_vectors")))
void DebugMon_Handler(void)
{
- while (1) {}
+ while(1)
+ {
+ }
}
-
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void)
{
- while (1) {}
+ while(1)
+ {
+ }
}
-
__attribute__ ((section(".after_vectors")))
void SysTick_Handler(void)
{
- while (1) {}
+ while(1)
+ {
+ }
}
-// *****************************************************************************
+//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//
-// *****************************************************************************
+//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void)
{
- while (1) {}
+ while(1)
+ {
+ }
}
-
-// *****************************************************************************
-//
-// Heap overflow check function required by REDLib_V2 library
-//
-// *****************************************************************************
-extern unsigned int *_pvHeapStart;
-unsigned int __check_heap_overflow (void * new_end_of_heap)
-{
- return (new_end_of_heap >= (void *)&__vHeap[HEAP_SIZE/sizeof(unsigned int)]);
-}
-
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c Fri Jul 11 10:00:08 2014 +0100
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c Tue Jul 15 07:45:08 2014 +0100
@@ -35,8 +35,11 @@
#define COUNT_OF(a) (sizeof(a)/sizeof(a[0]))
/* Clock variables */
-//uint32_t SystemCoreClock = CRYSTAL_MAIN_FREQ_IN; /*!< System Clock Frequency (Core Clock)*/
-uint32_t SystemCoreClock = 204000000;
+#if (CLOCK_SETUP)
+uint32_t SystemCoreClock = MAX_CLOCK_FREQ;
+#else
+uint32_t SystemCoreClock = CRYSTAL_MAIN_FREQ_IN;
+#endif
#if !defined(CORE_M0)
/* SCU pin definitions for pin muxing */
@@ -45,32 +48,80 @@
uint16_t mode; /* SCU pin mode and function */
} PINMUX_GRP_T;
+/* Pins to initialize before clocks are configured */
+static const PINMUX_GRP_T pre_clock_mux[] = {
+ /* SPIFI pins */
+ {SCU_REG(0x3, 3), (SCU_PINIO_FAST | 0x3)}, /* P3_3 SPIFI CLK */
+ {SCU_REG(0x3, 4), (SCU_PINIO_FAST | 0x3)}, /* P3_4 SPIFI D3 */
+ {SCU_REG(0x3, 5), (SCU_PINIO_FAST | 0x3)}, /* P3_5 SPIFI D2 */
+ {SCU_REG(0x3, 6), (SCU_PINIO_FAST | 0x3)}, /* P3_6 SPIFI D1 */
+ {SCU_REG(0x3, 7), (SCU_PINIO_FAST | 0x3)}, /* P3_7 SPIFI D0 */
+ {SCU_REG(0x3, 8), (SCU_PINIO_FAST | 0x3)} /* P3_8 SPIFI CS/SSEL */
+};
+
+/* Pins to initialize after clocks are configured */
+static const PINMUX_GRP_T post_clock_mux[] = {
+ /* Boot pins */
+ {SCU_REG(0x1, 1), (SCU_PINIO_FAST | 0x0)}, /* P1_1 BOOT0 */
+ {SCU_REG(0x1, 2), (SCU_PINIO_FAST | 0x0)}, /* P1_2 BOOT1 */
+ {SCU_REG(0x2, 8), (SCU_PINIO_FAST | 0x0)}, /* P2_8 BOOT2 */
+ {SCU_REG(0x2, 9), (SCU_PINIO_FAST | 0x0)}, /* P2_9 BOOT3 */
+ /* Micromint Bambino 200/210 */
+ {SCU_REG(0x6, 11), (SCU_PINIO_FAST | 0x0)}, /* P6_11 LED1 */
+ {SCU_REG(0x2, 5), (SCU_PINIO_FAST | 0x0)}, /* P2_5 LED2 */
+ {SCU_REG(0x2, 7), (SCU_PINIO_FAST | 0x0)}, /* P2_7 BTN1 */
+ /* Micromint Bambino 210 */
+ {SCU_REG(0x6, 1), (SCU_PINIO_FAST | 0x0)}, /* P6_1 LED3 */
+ {SCU_REG(0x6, 2), (SCU_PINIO_FAST | 0x0)}, /* P6_2 LED4 */
+};
+
+#if (CLOCK_SETUP)
+/* Structure for initial base clock states */
+struct CLK_BASE_STATES {
+ CGU_BASE_CLK_T clk; /* Base clock */
+ CGU_CLKIN_T clkin; /* Base clock source */
+ uint8_t powerdn; /* Set to 1 if base clock is initially powered down */
+};
+
+/* Initial base clock states are mostly on */
+static const struct CLK_BASE_STATES clock_states[] = {
+ {CLK_BASE_SAFE, CLKIN_IRC, 0},
+ {CLK_BASE_APB1, CLKIN_MAINPLL, 0},
+ {CLK_BASE_APB3, CLKIN_MAINPLL, 0},
+ {CLK_BASE_USB0, CLKIN_USBPLL, 1},
+ {CLK_BASE_PERIPH, CLKIN_MAINPLL, 0},
+ {CLK_BASE_SPI, CLKIN_MAINPLL, 0},
+ {CLK_BASE_PHY_TX, CLKIN_ENET_TX, 0},
+#if defined(USE_RMII)
+ {CLK_BASE_PHY_RX, CLKIN_ENET_TX, 0},
+#else
+ {CLK_BASE_PHY_RX, CLKIN_ENET_RX, 0},
+#endif
+ {CLK_BASE_SDIO, CLKIN_MAINPLL, 0},
+ {CLK_BASE_SSP0, CLKIN_MAINPLL, 0},
+ {CLK_BASE_SSP1, CLKIN_MAINPLL, 0},
+ {CLK_BASE_UART0, CLKIN_MAINPLL, 0},
+ {CLK_BASE_UART1, CLKIN_MAINPLL, 0},
+ {CLK_BASE_UART2, CLKIN_MAINPLL, 0},
+ {CLK_BASE_UART3, CLKIN_MAINPLL, 0},
+ {CLK_BASE_OUT, CLKINPUT_PD, 0},
+ {CLK_BASE_APLL, CLKINPUT_PD, 0},
+ {CLK_BASE_CGU_OUT0, CLKINPUT_PD, 0},
+ {CLK_BASE_CGU_OUT1, CLKINPUT_PD, 0},
+
+ /* Clocks derived from dividers */
+ {CLK_BASE_LCD, CLKIN_IDIVC, 0},
+ {CLK_BASE_USB1, CLKIN_IDIVD, 1}
+};
+#endif /* defined(CLOCK_SETUP) */
+
/* Local functions */
-static void SystemCoreClockUpdate(void);
+static uint32_t SystemGetMainPLLHz(void);
static void SystemSetupClock(void);
static void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n);
static void SystemSetupMemory(void);
static void WaitUs(uint32_t us);
-/* Pins to initialize before clocks are configured */
-static const PINMUX_GRP_T pre_clock_mux[] = {
- /* SPIFI pins */
- {SCU_REG(0x3, 3), (SCU_PINIO_FAST | 0x3)}, // P3_3 SPIFI CLK
- {SCU_REG(0x3, 4), (SCU_PINIO_FAST | 0x3)}, // P3_4 SPIFI D3
- {SCU_REG(0x3, 5), (SCU_PINIO_FAST | 0x3)}, // P3_5 SPIFI D2
- {SCU_REG(0x3, 6), (SCU_PINIO_FAST | 0x3)}, // P3_6 SPIFI D1
- {SCU_REG(0x3, 7), (SCU_PINIO_FAST | 0x3)}, // P3_7 SPIFI D0
- {SCU_REG(0x3, 8), (SCU_PINIO_FAST | 0x3)} // P3_8 SPIFI CS/SSEL
-};
-
-/* Pins to initialize after clocks are configured */
-static const PINMUX_GRP_T post_clock_mux[] = {
- /* Boot pins */
- {SCU_REG(0x1, 1), (SCU_PINIO_FAST | 0x0)}, // P1_1 BOOT0
- {SCU_REG(0x1, 2), (SCU_PINIO_FAST | 0x0)}, // P1_2 BOOT1
- {SCU_REG(0x2, 8), (SCU_PINIO_FAST | 0x0)}, // P2_8 BOOT2
- {SCU_REG(0x2, 9), (SCU_PINIO_FAST | 0x0)} // P2_9 BOOT3
-};
#endif /* !defined(CORE_M0) */
/*
@@ -79,33 +130,34 @@
void SystemInit(void)
{
#if !defined(CORE_M0)
- unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
+ /* Initialize vector table in flash */
#if defined(__ARMCC_VERSION)
extern void *__Vectors;
- *pSCB_VTOR = (unsigned int) &__Vectors;
+ SCB->VTOR = (unsigned int) &__Vectors;
#elif defined(__IAR_SYSTEMS_ICC__)
extern void *__vector_table;
- *pSCB_VTOR = (unsigned int) &__vector_table;
+ SCB->VTOR = (unsigned int) &__vector_table;
#elif defined(TOOLCHAIN_GCC_ARM)
extern void *__isr_vector;
- *pSCB_VTOR = (unsigned int) &__isr_vector;
+ SCB->VTOR = (unsigned int) &__isr_vector;
#else /* defined(__GNUC__) and others */
extern void *g_pfnVectors;
- *pSCB_VTOR = (unsigned int) &g_pfnVectors;
+ SCB->VTOR = (unsigned int) &g_pfnVectors;
#endif
+#if !defined(TOOLCHAIN_GCC)
#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
/* Initialize floating point */
fpuInit();
#endif
+#endif
SystemSetupPins(pre_clock_mux, COUNT_OF(pre_clock_mux)); /* Configure pins */
-
SystemSetupClock(); /* Configure processor and peripheral clocks */
SystemSetupPins(post_clock_mux, COUNT_OF(post_clock_mux)); /* Configure pins */
SystemSetupMemory(); /* Configure external memory */
@@ -119,44 +171,125 @@
*/
void SystemCoreClockUpdate(void)
{
+ uint32_t reg, div, rate;
+
+ /* Get main PLL rate */
+ rate = SystemGetMainPLLHz();
+
+ /* Get clock divider */
+ reg = LPC_CCU1->CLKCCU[CLK_MX_MXCORE].CFG;
+ if (((reg >> 5) & 0x7) == 0) {
+ div = 1;
+ }
+ else {
+ div = 2;
+ }
+ rate = rate / div;
+
+ SystemCoreClock = rate;
+}
+
+/* Returns the frequency of the main PLL */
+uint32_t SystemGetMainPLLHz(void)
+{
+ uint32_t PLLReg = LPC_CGU->PLL1_CTRL;
+ uint32_t freq = CRYSTAL_MAIN_FREQ_IN;
+ uint32_t msel, nsel, psel, direct, fbsel;
+ uint32_t m, n, p;
+ const uint8_t ptab[] = {1, 2, 4, 8};
+
+ msel = (PLLReg >> 16) & 0xFF;
+ nsel = (PLLReg >> 12) & 0x3;
+ psel = (PLLReg >> 8) & 0x3;
+ direct = (PLLReg >> 7) & 0x1;
+ fbsel = (PLLReg >> 6) & 0x1;
+
+ m = msel + 1;
+ n = nsel + 1;
+ p = ptab[psel];
+
+ if (direct || fbsel) {
+ return m * (freq / n);
+ }
+
+ return (m / (2 * p)) * (freq / n);
}
#if !defined(CORE_M0)
/*
* SystemSetupClock() - Set processor and peripheral clocks
+ *
+ * Clock Frequency Source
+ * CLK_BASE_MX 204 MHz CLKIN_MAINPLL (CLKIN_PLL1)
+ * CLK_BASE_SPIFI 102 MHz CLKIN_IDIVE
+ * CLK_BASE_USB0 480 MHz CLKIN_USBPLL (Disabled) (CLKIN_PLL0USB)
+ * CLK_BASE_USB1 60 MHz CLKIN_IDIVE (Disabled)
+ * 120 MHz CLKIN_IDIVD (Disabled)
+ *
+ * 12 MHz CLKIN_IDIVB
+ * 12 MHz CLKIN_IDIVC
+ *
*/
void SystemSetupClock(void)
{
#if (CLOCK_SETUP)
- /* Switch main clock to Internal RC (IRC) */
- LPC_CGU->BASE_CLK[CLK_BASE_MX] = ((1 << 11) | (CLKIN_IRC << 24));
+ uint32_t i;
+
+ /* Switch main clock to Internal RC (IRC) while setting up PLL1 */
+ LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_IRC << 24);
/* Enable the oscillator and wait 100 us */
LPC_CGU->XTAL_OSC_CTRL = 0;
WaitUs(100);
#if (SPIFI_INIT)
- /* Switch IDIVA clock to IRC and connect to SPIFI clock */
- LPC_CGU->IDIV_CTRL[CLK_IDIV_A] = ((1 << 11) | (CLKIN_IRC << 24));
- LPC_CGU->BASE_CLK[CLK_BASE_SPIFI] = ((1 << 11) | (CLKIN_IDIVA << 24));
+ /* Setup SPIFI control register and no-opcode mode */
+ LPC_SPIFI->CTRL = (0x100 << 0) | (1 << 16) | (1 << 29) | (1 << 30);
+ LPC_SPIFI->IDATA = 0xA5;
+ /* Switch IDIVE clock to IRC and connect to SPIFI clock */
+ LPC_CGU->IDIV_CTRL[CLK_IDIV_E] = ((1 << 11) | (CLKIN_IRC << 24));
+ LPC_CGU->BASE_CLK[CLK_BASE_SPIFI] = ((1 << 11) | (CLKIN_IDIVE << 24));
#endif /* SPIFI_INIT */
- /* Power down PLL1 */
- LPC_CGU->PLL1_CTRL |= 1;
+ /* Configure PLL1 (MAINPLL) for main clock */
+ LPC_CGU->PLL1_CTRL |= 1; /* Power down PLL1 */
/* Change PLL1 to 108 Mhz (msel=9, 12 MHz*9=108 MHz) */
-// LPC_CGU->PLL1_CTRL = (DIRECT << 7) | (PSEL << 8) | (1 << 11) | (P(NSEL-1) << 12) | ((MSEL-1) << 16) | (CLKIN_PLL1 << 24);
- LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (8 << 16) | (CLKIN_PLL1 << 24);
+ LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (8 << 16)
+ | (CLKIN_MAINPLL << 24);
while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
WaitUs(100);
/* Change PLL1 to 204 Mhz (msel=17, 12 MHz*17=204 MHz) */
- LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (16 << 16) | (CLKIN_PLL1 << 24);
+ LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (16 << 16)
+ | (CLKIN_MAINPLL << 24);
while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
- /* Switch main clock to PLL1 */
- LPC_CGU->BASE_CLK[CLK_BASE_MX] = ((1 << 11) | (CLKIN_PLL1 << 24));
- SystemCoreClock = 204000000;
+ /* Connect main clock to PLL1 */
+ LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_MAINPLL << 24);
+
+ /* Set USB PLL dividers for 480 MHz (for USB0) */
+ LPC_CGU->PLL[CGU_USB_PLL].PLL_MDIV = 0x06167FFA;
+ LPC_CGU->PLL[CGU_USB_PLL].PLL_NP_DIV = 0x00302062;
+ LPC_CGU->PLL[CGU_USB_PLL].PLL_CTRL = 0x0000081D | (CLKIN_CRYSTAL << 24);
+
+ /* Set IDIVE clock to PLL1/2 = 102 MHz */
+ LPC_CGU->IDIV_CTRL[CLK_IDIV_E] = (1 << 2) | (1 << 11) | (CLKIN_MAINPLL << 24); /* PLL1/2 */
+
+ /* Set IDIVD clock to ((USBPLL/4) / 2) = 60 MHz (for USB1) */
+ LPC_CGU->IDIV_CTRL[CLK_IDIV_A] = (3 << 2) | (1 << 11) | (CLKIN_USBPLL << 24); /* USBPLL/4 */
+ LPC_CGU->IDIV_CTRL[CLK_IDIV_D] = (1 << 2) | (1 << 11) | (CLKIN_IDIVA << 24); /* IDIVA/2 */
+
+ /* Configure remaining integer dividers */
+ LPC_CGU->IDIV_CTRL[CLK_IDIV_B] = (0 << 2) | (1 << 11) | (CLKIN_IRC << 24); /* IRC */
+ LPC_CGU->IDIV_CTRL[CLK_IDIV_C] = (1 << 2) | (1 << 11) | (CLKIN_MAINPLL << 24); /* PLL1/2 */
+
+ /* Connect base clocks */
+ for (i = 0; i < COUNT_OF(clock_states); i++) {
+ LPC_CGU->BASE_CLK[clock_states[i].clk] =
+ ( clock_states[i].powerdn << 0)
+ | (1 << 11) | (clock_states[i].clkin << 24);
+ }
#endif /* CLOCK_SETUP */
}
@@ -165,7 +298,7 @@
*/
void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n)
{
- uint16_t i;
+ uint32_t i;
for (i = 0; i < n; i++) {
*(mux[i].reg) = mux[i].mode;
@@ -188,35 +321,36 @@
*/
void fpuInit(void)
{
- // from ARM TRM manual:
- // ; CPACR is located at address 0xE000ED88
- // LDR.W R0, =0xE000ED88
- // ; Read CPACR
- // LDR R1, [R0]
- // ; Set bits 20-23 to enable CP10 and CP11 coprocessors
- // ORR R1, R1, #(0xF << 20)
- // ; Write back the modified value to the CPACR
- // STR R1, [R0]
+ /*
+ * from ARM TRM manual:
+ * ; CPACR is located at address 0xE000ED88
+ * LDR.W R0, =0xE000ED88
+ * ; Read CPACR
+ * LDR R1, [R0]
+ * ; Set bits 20-23 to enable CP10 and CP11 coprocessors
+ * ORR R1, R1, #(0xF << 20)
+ * ; Write back the modified value to the CPACR
+ * STR R1, [R0]
+ */
- volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
- volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
- volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
- volatile uint32_t Cpacr;
- volatile uint32_t Mvfr0;
- volatile uint32_t Mvfr1;
- char vfpPresent = 0;
+ volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
+ volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
+ volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
+ volatile uint32_t Cpacr;
+ volatile uint32_t Mvfr0;
+ volatile uint32_t Mvfr1;
+ char vfpPresent = 0;
- Mvfr0 = *regMvfr0;
- Mvfr1 = *regMvfr1;
+ Mvfr0 = *regMvfr0;
+ Mvfr1 = *regMvfr1;
- vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
+ vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
- if (vfpPresent) {
- Cpacr = *regCpacr;
- Cpacr |= (0xF << 20);
- *regCpacr = Cpacr; // enable CP10 and CP11 for full access
- }
-
+ if (vfpPresent) {
+ Cpacr = *regCpacr;
+ Cpacr |= (0xF << 20);
+ *regCpacr = Cpacr; /* enable CP10 and CP11 for full access */
+ }
}
#endif /* defined(__FPU_PRESENT) && __FPU_PRESENT == 1 */
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.h Fri Jul 11 10:00:08 2014 +0100 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.h Tue Jul 15 07:45:08 2014 +0100 @@ -81,6 +81,7 @@ * Initialize the System and update the SystemCoreClock variable. */ extern void SystemInit (void); +extern void SystemCoreClockUpdate(void); #ifdef __cplusplus }
--- a/targets/hal/TARGET_NXP/TARGET_LPC43XX/PeripheralNames.h Fri Jul 11 10:00:08 2014 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC43XX/PeripheralNames.h Tue Jul 15 07:45:08 2014 +0100
@@ -63,15 +63,22 @@
} I2CName;
typedef enum {
- PWM0_1 = 1,
- PWM0_2,
- PWM0_3,
- PWM1_1,
- PWM1_2,
- PWM1_3,
- PWM2_1,
- PWM2_2,
- PWM2_3
+ PWM_0,
+ PWM_1,
+ PWM_2,
+ PWM_3,
+ PWM_4,
+ PWM_5,
+ PWM_6,
+ PWM_7,
+ PWM_8,
+ PWM_9,
+ PWM_10,
+ PWM_11,
+ PWM_12,
+ PWM_13,
+ PWM_14,
+ PWM_15
} PWMName;
typedef enum {
@@ -79,9 +86,47 @@
CAN_1 = (int)LPC_C_CAN1_BASE
} CANName;
-#define STDIO_UART_TX UART0_TX
-#define STDIO_UART_RX UART0_RX
-#define STDIO_UART UART_0
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_2
+
+// Default peripherals
+#define MBED_SPI0 SPI0_MOSI, SPI0_MISO, SPI0_SCK, SPI0_SSEL
+#define MBED_SPI1 SPI1_MOSI, SPI1_MISO, SPI1_SCK, SPI1_SSEL
+
+#define MBED_UART0 UART0_TX, UART0_RX
+#define MBED_UART1 UART1_TX, UART1_RX
+#define MBED_UART2 UART2_TX, UART2_RX
+#define MBED_UART3 UART3_TX, UART3_RX
+#define MBED_UARTUSB USBTX, USBRX
+
+#define COM1 MBED_UART0
+#define COM2 MBED_UART1
+#define COM3 MBED_UART2
+#define COM4 MBED_UART3
+
+#define MBED_I2C0 I2C0_SDA, I2C0_SCL
+#define MBED_I2C1 I2C1_SDA, I2C1_SCL
+
+#define MBED_CAN0 p30, p29
+
+#define MBED_ANALOGOUT0 DAC0
+
+#define MBED_ANALOGIN0 ADC0
+#define MBED_ANALOGIN1 ADC1
+#define MBED_ANALOGIN2 ADC2
+#define MBED_ANALOGIN3 ADC3
+#define MBED_ANALOGIN4 ADC4
+#define MBED_ANALOGIN5 ADC5
+#define MBED_ANALOGIN6 ADC6
+#define MBED_ANALOGIN7 ADC7
+
+#define MBED_PWMOUT0 p26
+#define MBED_PWMOUT1 p25
+#define MBED_PWMOUT2 p24
+#define MBED_PWMOUT3 p23
+#define MBED_PWMOUT4 p22
+#define MBED_PWMOUT5 p21
#ifdef __cplusplus
}
--- a/targets/hal/TARGET_NXP/TARGET_LPC43XX/PinNames.h Fri Jul 11 10:00:08 2014 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC43XX/PinNames.h Tue Jul 15 07:45:08 2014 +0100
@@ -435,7 +435,7 @@
SFP_CLK1 = MBED_PIN(0x18, 1, 0, 0),
SFP_CLK2 = MBED_PIN(0x18, 2, 0, 0),
SFP_CLK3 = MBED_PIN(0x18, 3, 0, 0),
-
+
// Group 0x19 : USB1, I2C0, ADC0, ADC1
SFP_USB1 = MBED_PIN(0x19, 0, 0, 0),
SFP_I2C0 = MBED_PIN(0x19, 1, 0, 0),
@@ -448,107 +448,245 @@
SFP_INS0 = MBED_PIN(0x1C, 0, 0, 0), // Interrupt select for pin interrupts 0 to 3
SFP_INS1 = MBED_PIN(0x1C, 1, 0, 0), // Interrupt select for pin interrupts 4 to 7
-#define MBED_ADC_NUM(MBED_PIN) ((MBED_PIN >> 5) & 0x0000000F)
-#define MBED_ADC_CHAN(MBED_PIN) (MBED_PIN & 0x0000001F)
+ // Dedicated pin (no GPIO)
+ P_DED = MBED_PIN(0, 0, NO_GPIO, 0),
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+
+ // ---------- Micromint Bambino 200/200E/210/210E (LQFP144) ----------
+ // Base headers - J8, J9, J10 on Bambino 210/210E
+ // n/p = not populated, n/a = not available
+ // 210E 210 200E 200
+ // ---- ---- ---- ----
+ p15 = P7_4, // J8-1 J8-1 S4-3 S4-3
+ p16 = P7_5, // J8-2 J8-2 S4-4 S4-4
+ p17 = P4_1, // J8-3 J8-3 S3-4 S3-4
+ p18 = P7_7, // J8-4 J8-4 S4-5 S4-5
+ p19 = P4_3, // J8-5* J8-5* S3-4 S3-3
+ p20 = P4_4, // J8-6* J8-6* S1-5 S1-5
+ p20b = PF_8, // J8-6** J8-6** S3-5 S3-5
+ // (*) if p20 is configured as DAC, ADC is not available for p19
+ // (**) requires JP2 mod
+
+ p21 = P6_5, // J9-1 J9-1 S2-5 S2-5
+ p22 = P6_4, // J9-2 J9-2 S2=4 S2-4
+ p23 = P1_7, // J9-3 J9-3 S2-3 S2-3
+ p24 = P4_0, // J9-4 J9-4 S3-7 S3-7
+ p25 = P6_9, // J9-5 J9-5 S8-7 n/p
+ p26 = P5_5, // J9-6 J9-6 S3-8 S3-8
+ p27 = P5_7, // J9-7 J9-7 S3-9 S3-9
+ p28 = P7_6, // J9-8 J9-8 S4-6 S4-6
- // Use pseudo-pin ID also for ADCs, although with special handling
- SFP_ADC0_0 = MBED_PIN(0x19, 2, 0, 0), // ADC0_0
- SFP_ADC0_1 = MBED_PIN(0x19, 2, 0, 1), // ADC0_1
- SFP_ADC0_2 = MBED_PIN(0x19, 2, 0, 2), // ADC0_2
- SFP_ADC0_3 = MBED_PIN(0x19, 2, 0, 3), // ADC0_3
- SFP_ADC0_4 = MBED_PIN(0x19, 2, 0, 4), // ADC0_4
- SFP_ADC0_5 = MBED_PIN(0x19, 2, 0, 5), // ADC0_5
- SFP_ADC0_6 = MBED_PIN(0x19, 2, 0, 6), // ADC0_6
+ p29 = P6_12, // J10-1 J10-1 S10-3 n/p
+ p30 = P5_0, // J10-2 J10-2 S1-4 S1-4
+ p31 = P4_6, // J10-3 J10-3 S2-6 S2-6
+ p32 = P4_8, // J10-4 J10-4 S2-7 S2-7
+ p33 = P4_9, // J10-5 J10-5 S2-8 S2-8
+ p34 = P4_10, // J10-6 J10-6 S2-9 S2-9
+ p37 = P2_3, // J10-9 J10-9 S4-8 S4-8
+ p38 = P2_4, // J10-10 J10-10 S4-9 S4-9
- SFP_ADC1_0 = MBED_PIN(0x19, 3, 1, 0), // ADC1_0
- SFP_ADC1_1 = MBED_PIN(0x19, 3, 1, 1), // ADC1_1
- SFP_ADC1_2 = MBED_PIN(0x19, 3, 1, 2), // ADC1_2
- SFP_ADC1_3 = MBED_PIN(0x19, 3, 1, 3), // ADC1_3
- SFP_ADC1_4 = MBED_PIN(0x19, 3, 1, 4), // ADC1_4
- SFP_ADC1_5 = MBED_PIN(0x19, 3, 1, 5), // ADC1_5
- SFP_ADC1_6 = MBED_PIN(0x19, 3, 1, 6), // ADC1_6
- SFP_ADC1_7 = MBED_PIN(0x19, 3, 1, 7), // ADC1_7
+ // Extended headers - J11, J12, J13, J14 on Bambino 210E
+ // 210E 210 200E 200
+ // ---- ---- ---- ----
+ p47 = P6_3, // J11-1 n/p S7-5 n/p
+ p48 = P6_6, // J11-2 n/p S6-7 n/p
+ p49 = P6_7, // J11-3 n/p S6-8 n/p
+ p50 = P6_8, // J11-4 n/p S6-9 n/p
+ p53 = P2_2, // J11-7 n/p S7-7 n/p
+ p54 = P2_1, // J11-8 n/p S7-3 n/p
+
+ p55 = PF_10, // J12-1 n/p n/a n/a
+ p56 = PF_7, // J12-2 n/p n/a n/a
+ p57 = P2_6, // J12-3 n/p S8-6 n/p
+ p58 = P2_8, // J12-4 n/p S8-3 n/p
+ p59 = P6_10, // J12-5 n/p S7-8 n/p
+ p60 = P2_9, // J12-6 n/p S9-3 n/p
+
+ p61 = P7_3, // J13-1 n/p S7-9 n/p
+ p62 = P3_2, // J13-2 n/p S9-4 n/p
+ p63 = P7_2, // J13-3 n/p S4-7 S4-7
+ p64 = P3_1, // J13-4 n/p S9-5 n/p
+ p65 = P7_1, // J13-5 n/p S9-8 n/p
+ p66 = P7_0, // J13-6 n/p S9-9 n/p
+ p67 = P4_2, // J13-7 n/p S4-6 S4-6
+ p68 = P4_5, // J13-8 n/p S1-3 S1-3
- // ---------- Micromint Bambino 200 ----------
- // LQFP144
- // NOTE: Pins marked (*) only available on 200E
- p5 = P1_2, // SPI0 mosi
- p6 = P1_1, // SPI0 miso
- p7 = P3_0, // SPI0 sck
- p8 = P4_5,
- p9 = P6_4, // Serial0 tx, I2C0 sda
- p10 = P6_5, // Serial0 rx, I2C0 scl
- p11 = P1_4, // SPI1 mosi (*)
- p12 = P1_3, // SPI1 miso (*)
- p13 = PF_4, // Serial1 tx, SPI1 sck (*)
- p14 = P1_14, // Serial1 rx
- p15 = P4_3, // ADC0
- p16 = P4_1, // ADC1
- p17 = P7_4, // ADC2
- p18 = SFP_ADC0_0, // ADC3, DAC0
- p19 = P7_5, // ADC4
- p20 = P7_7, // ADC5
- p21 = P4_0, // PWM0
- p22 = P5_5, // PWM1
- p23 = P5_7, // PWM2
- p24 = P4_8, // PWM3
- p25 = P4_9, // PWM4
- p26 = P4_10, // PWM5
- p27 = P2_4, // I2C1 scl, Serial2 rx
- p28 = P2_3, // I2C1 sda, Serial2 tx
- p29 = P3_2, // CAN0 td
- p30 = P3_1, // CAN0 rx
+ p69 = P2_13, // J14-1 n/p S9-7 n/p
+ p70 = P2_12, // J14-2 n/p S9-6 n/p
+ p71 = P9_6, // J14-3 n/p S6-6 n/p
+ p72 = P9_5, // J14-4 n/p S7-4 n/p
+ p73 = P5_3, // J14-5 n/p S6-5 n/p
+ p74 = P1_8, // J14-6 n/p S6-4 n/p
+ p75 = P1_5, // J14-7 n/p S10-6 n/p
+ p76 = P1_4, // J14-8 n/p S10-7 n/p
+ p77 = P1_3, // J14-9 n/p S10-8 n/p
+ p78 = PF_4, // J14-10 n/p S10-9 n/p
+
+ // J16 - PMOD-SSP header (not populated, field installable)
+ p80 = P1_0, // J16-1 J16-1 S1-6 S1-6
+ p81 = P1_2, // J16-2 J16-2 S1-7 S1-7
+ p82 = P1_1, // J16-3 J16-3 S1-8 S1-8
+ p83 = P3_0, // J16-4 J16-4 S1-9 S1-9
+
+ // Arduino pins - J8, J9, J10
+ // 210E 210 200E 200
+ // ---- ---- ---- ----
+ D0 = p21, // J9-1 J9-1 S2-5 S2-5
+ D1 = p22, // J9-2 J9-2 S2-4 S2-4
+ D2 = p23, // J9-3 J9-3 S2-3 S2-3
+ D3 = p24, // J9-4 J9-4 S3-7 S3-7
+ D4 = p25, // J9-5 J9-5 S8-7 n/p
+ D5 = p26, // J9-6 J9-6 S3-8 S3-8
+ D6 = p27, // J9-7 J9-7 S3-9 S3-9
+ D7 = p28, // J9-8 J9-8 S4-6 S4-6
+
+ D8 = p29, // J10-1 J10-1 S10-1 n/p
+ D9 = p30, // J10-2 J10-2 S1-4 S1-4
+ D10 = p31, // J10-3 J10-3 S2-6 S2-6
+ D11 = p32, // J10-4 J10-4 S2-7 S2-7
+ D12 = p33, // J10-5 J10-5 S2-8 S2-8
+ D13 = p34, // J10-6 J10-6 S2-9 S2-9
+ D16 = p37, // J10-9 J10-9 S4-8 S4-8
+ D17 = p38, // J10-10 J10-10 S4-9 S4-9
+
+ A0 = p15, // J8-1 J8-1 S4-3 S4-3
+ A1 = p16, // J8-2 J8-2 S4-4 S4-4
+ A2 = p17, // J8-3 J8-3 S3-4 S3-4
+ A3 = p18, // J8-4 J8-4 S3-4 S3-4
+ A4 = p19, // J8-5* J8-5* S3-3 S3-3
+ A5 = p20, // J8-6* J8-6* S1-5 S1-5
+ A5b = p20b, // J8-6** J8-6** S3-5 S3-5
+ // (*) if A5 is configured as DAC, ADC is not available for A4
+ // (**) requires JP2 mod
+
+ // Extended Arduino pins - J11, J12, J13, J14
+ // 210E 210 200E 200
+ // ---- ---- ---- ----
+ D20 = p61, // J13-1 n/p S7-9 n/p
+ D21 = p62, // J13-2 n/p S9-4 n/p
+ D22 = p63, // J13-3 n/p S4-7 S4-7
+ D23 = p64, // J13-4 n/p S9-5 n/p
+ D24 = p65, // J13-5 n/p S9-8 n/p
+ D25 = p66, // J13-6 n/p S9-9 n/p
+ D26 = p67, // J13-7 n/p S3-7 S3-7
+ D27 = p68, // J13-8 n/p S1-3 S1-3
+
+ D30 = p69, // J14-1 n/p S9-7 n/p
+ D31 = p70, // J14-2 n/p S9-6 n/p
+ D32 = p71, // J14-3 n/p S6-6 n/p
+ D33 = p72, // J14-4 n/p S7-4 n/p
+ D34 = p73, // J14-5 n/p S6-5 n/p
+ D35 = p74, // J14-6 n/p S6-4 n/p
+ D36 = p75, // J14-7 n/p S10-6 n/p
+ D37 = p76, // J14-8 n/p S10-7 n/p
+ D38 = p77, // J14-9 n/p S10-8 n/p
+ D39 = p78, // J14-10 n/p S10-9 n/p
+
+ D40 = p47, // J11-1 n/p S7-5 n/p
+ D41 = p48, // J11-2 n/p S6-7 n/p
+ D42 = p49, // J11-3 n/p S6-8 n/p
+ D43 = p50, // J11-4 n/p S6-9 n/p
+ D46 = p53, // J11-7 n/p S7-7 n/p
+ D47 = p54, // J11-8 n/p S7-3 n/p
+
+ D52 = p57, // J12-3 n/p S8-6 n/p
+ D53 = p58, // J12-4 n/p S8-3 n/p
+ D54 = p59, // J12-5 n/p S7-8 n/p
+ D55 = p60, // J12-6 n/p S9-3 n/p
+
+ A6 = p55, // J12-1 n/p n/a n/a
+ A7 = p56, // J12-2 n/p n/a n/a
// User interfaces: LEDs, buttons
- LED_YELLOW = P6_11,
- LED_GREEN = P2_5,
- LED_RED = LED_YELLOW,
- LED_BLUE = LED_GREEN,
+ // 210E 210 200E 200
+ // ---- ---- ---- ----
+ LED1 = P6_11, // 210/210E/200e/200
+ LED2 = P2_5, // 210/210E/200e/200
+ LED3 = P6_1, // 210/210E only S6-3 n/p
+ LED4 = P6_2, // 210/210E only S7-6 n/p
- LED1 = LED_YELLOW,
- LED2 = LED_GREEN,
- LED3 = LED_GREEN,
- LED4 = LED_GREEN,
+ LED_YELLOW = LED1,
+ LED_GREEN = LED2,
+ LED_RED = LED3,
+ LED_BLUE = LED4,
BTN1 = P2_7,
- // Serial pins
- UART0_TX = P6_4,
- UART0_RX = P6_5,
- UART1_TX = P5_6,
- UART1_RX = P1_14,
- UART2_TX = P2_10,
- UART2_RX = P2_11,
- UART3_TX = P2_3,
- UART3_RX = P2_4,
+ // Serial pins - UART, SPI, I2C
+ // 210E 210 200E 200
+ // ---- ---- ---- ----
+ UART0_TX = P6_4, // J9-2 J9-2 S2-4 S2-4
+ UART0_RX = P6_5, // J9-1 J9-1 S2-5 S2-5
+ UART1_TX = P5_6, // XBEE n/p S5-4/XBEE S5-4
+ UART1_RX = P1_14, // XBEE n/p S5-5/XBEE S5-5
+ UART2_TX = P2_10, // MBEDHDK MBEDHDK S10-4 n/p
+ UART2_RX = P2_11, // MBEDHDK MBEDHDK S10-5 n/p
+ UART3_TX = P2_3, // J10-9 n/p S4-8 S4-8
+ UART3_RX = P2_4, // J10-10 n/p S4-9 S4-9
+
+ COM1_TX = UART0_TX,
+ COM1_RX = UART0_RX,
+ COM2_TX = UART1_TX,
+ COM2_RX = UART1_RX,
+ COM3_TX = UART2_TX,
+ COM3_RX = UART2_RX,
+ COM4_TX = UART3_TX,
+ COM4_RX = UART3_RX,
+
+ // 210E 210 200E 200
+ // ---- ---- ---- ----
+ SPI0_SCK = P3_0, // J16-4 n/p S1-9 S1-9
+ SPI0_MISO = P1_1, // J16-3 n/p S1-8 S1-8
+ SPI0_MOSI = P1_2, // J16-2 n/p S1-7 S1-7
+ SPI0_SSEL = P1_0, // J16-1 n/p S1-6 S1-6
+ SPI1_SCK = PF_4, // J14-10 n/p S10-9 n/p
+ SPI1_MISO = P1_3, // J14-9 n/p S10-8 n/p
+ SPI1_MOSI = P1_4, // J14-8 n/p S10-7 n/p
+ SPI1_SSEL = P1_5, // J14-7 n/p S10-6 n/p
+
+ I2C0_SDA = P_DED, // J15-3 J15-3 S8-8 n/p
+ I2C0_SCL = P_DED, // J15-1 J15-1 S8-9 n/p
+ I2C1_SDA = P2_3, // J10-9 J10-9 S4-8 S4-8
+ I2C1_SCL = P2_4, // J10-10 J10-10 S4-9 S4-9
// Analog pins
- P_ADC0_0 = P4_3,
- P_ADC0_1 = P4_1,
- P_ADC1_0 = SFP_ADC0_0,
- P_ADC0_4 = P7_4,
- P_ADC0_3 = P7_5,
- P_ADC1_6 = P7_7,
-
- P_ADC0 = P_ADC0_0,
- P_ADC1 = P_ADC0_1,
- P_ADC2 = P_ADC1_0,
- P_ADC3 = P_ADC0_4,
- P_ADC4 = P_ADC0_3,
- P_ADC5 = P_ADC1_6,
-
- P_DAC0 = P4_4,
+ ADC0 = P7_4, // J8-1 J8-1 S4-3 S4-3
+ ADC1 = P7_5, // J8-2 J8-2 S4-4 S4-4
+ ADC2 = P4_1, // J8-3 J8-3 S3-4 S3-4
+ ADC3 = P7_7, // J8-4 J8-4 S3-4 S3-4
+ ADC4 = P4_3, // J8-5* J8-5* S3-3 S3-3
+ ADC5 = PF_8, // J8-6** J8-6** S1-5 S1-5
+ ADC6 = PF_10, // J12-1 n/p n/a n/a
+ ADC7 = PF_7, // J12-2 n/p n/a n/a
+ DAC0 = P4_4, // J8-6* J8-6* S3-5 S3-5
+ // (*) if DAC0 is configured, ADC4 is not available
+ // (**) ADC5 requires JP2 mod
// USB pins
- //P_USB0_TX = SFP_USB1,
- //P_USB0_RX = SFP_USB1,
+ // 210E 210 200E 200
+ // ---- ---- ---- ----
+ USBTX = UART2_TX, // MBEDHDK MBEDHDK S10-4 n/p
+ USBRX = UART2_RX, // MBEDHDK MBEDHDK S10-5 n/p
- USBTX = UART0_TX,
- USBRX = UART0_RX,
- // ---------- End of Micromint Bambino 200 ----------
+ // PWM pins
+ // 210E 210 200E 200
+ // ---- ---- ---- ----
+ PWM1 = P1_7, // J9-3 J9-3 S2-3 S2-3
+ PWM2 = P7_6, // J9-8 J9-8 S4-6 S4-6
+ PWM3 = P6_12, // J10-1 J10-1 S10-3 n/p
+ PWM4 = P4_6, // J10-3 J10-3 S2-6 S2-6
+ PWM5 = P7_5, // J8-2 J8-2 S4-4 S4-4
+ PWM6 = P4_1, // J8-3 J8-3 S3-4 S3-4
+ PWM7 = P7_7, // J8-4 J8-4 S4-5 S4-5
+ PWM8 = P2_8, // J12-4 n/p S8-3 n/p
+ PWM9 = P2_9, // J12-6 n/p S9-3 n/p
+ PWM10 = P7_1, // J13-5 n/p S9-8 n/p
+ PWM11 = P7_0, // J13-6 n/p S9-9 n/p
+ PWM12 = P1_5, // J14-7 n/p S10-6 n/p
- // Not connected
- NC = (int)0xFFFFFFFF
+ // ---------- End of Micromint Bambino ----------
} PinName;
typedef enum {
--- a/targets/hal/TARGET_NXP/TARGET_LPC43XX/README.txt Fri Jul 11 10:00:08 2014 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC43XX/README.txt Tue Jul 15 07:45:08 2014 +0100
@@ -1,11 +1,11 @@
mbed port to NXP LPC43xx
========================
-Updated: 06/24/13
+Updated: 07/11/14
-The NXP LPC43xx microcontrollers are the first to include multiple Cortex-M
-cores in a single microcontroller package. This port allows mbed developers
-to take advantage of the LPC43xx in their application using APIs that they
-are familiar with. Some of the key features of the LPC43xx include:
+The NXP LPC43xx microcontrollers includes multiple Cortex-M cores in a single
+microcontroller package. This port allows mbed developers to take advantage
+of the LPC43xx in their application using APIs that they are familiar with.
+Some of the key features of the LPC43xx include:
* Dual core ARM Cortex-M4/M0 both capable of up to 204 MHz
* Up to 264 KB SRAM, 1 MB internal flash
@@ -27,16 +27,13 @@
* This port has been tested with the following boards:
Board MCU RAM/Flash
Micromint Bambino 200 LPC4330 264K SRAM/4 MB SPIFI flash
-
-* Ethernet, USB and microSD filesystem drivers will be available when the
- Bambino 200E is released.
+ Micromint Bambino 200E LPC4330 264K SRAM/8 MB SPIFI flash
+ Micromint Bambino 210 LPC4330 264K SRAM/4 MB SPIFI flash
+ Micromint Bambino 210E LPC4330 264K SRAM/8 MB SPIFI flash
-* This port uses offline toolchains. Development and testing has been done
- mainly with the Keil MDK 4.70. Some testing has been done with IAR 6.5.
- Eventually Keil, IAR and GCC CodeRed will be supported.
-
-* CMSIS-DAP debugging is not currently implemented. To debug use a JTAG.
- The NXP DFU tool can be used for flash programming.
+* CMSIS-DAP debugging is implemented with the Micromint Bambino 210/210E.
+ To debug other LPC4330 targets, use a JTAG. The NXP DFU tool can be used
+ for flash programming.
* This port should support NXP LPC43XX and LPC18XX variants with a single
codebase. The core declaration specifies the binaries to be built:
@@ -52,9 +49,7 @@
building binaries for different targets requires an external project or
Makefile.
-* No testing has been done with LPC18xx hardware. At the very least supporting
- the LPC18xx would require different compiler flags, additional CMSIS core_cm3
- code as well as minor driver code changes.
+* No testing has been done with LPC18xx hardware.
Notes
-----
@@ -68,9 +63,19 @@
MBED_SCU_REG(P6_11) = 0x4008632C MBED_GPIO_PORT(P6_11) = 3
MBED_GPIO_REG(P6_11) = 0x400F4000 MBED_GPIO_PIN(P6_11) = 7
+* Pin names use multiple aliases to support Arduino naming conventions as well
+ as others. For example, to use pin p21 on the Bambino 210 from mbed applications
+ the following aliases are equivalent: p21, D0, UART0_TX, COM1_TX, P6_4.
+ See the board pinout graphic and the PinNames.h for available aliases.
+
* The LPC43xx implements GPIO pin and group interrupts. Any pin in the 8 32-bit
GPIO ports can interrupt (LPC4350 supports up to 164). On group interrupts a
pin can only interrupt on the rising or falling edge, not both as required
by the mbed InterruptIn class. Also, group interrupts can't be cleared
individually. This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
A future implementation may provide group interrupt support.
+
+* The LPC3xx PWM driver uses the State Configurable Timer (SCT). The default
+ build (PWM_MODE=0) uses the unified 32-bit times. Applications that use PWM
+ and require other SCT uses can use the dual 16-bit mode by changing PWM_MODE
+ when building the library.
--- a/targets/hal/TARGET_NXP/TARGET_LPC43XX/analogin_api.c Fri Jul 11 10:00:08 2014 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC43XX/analogin_api.c Tue Jul 15 07:45:08 2014 +0100
@@ -19,6 +19,8 @@
#include "analogin_api.h"
#include "cmsis.h"
#include "pinmap.h"
+#include "error.h"
+#include "gpio_api.h"
#define ANALOGIN_MEDIAN_FILTER 1
@@ -26,68 +28,74 @@
return (x + (y - 1)) / y;
}
-// ToDo: Add support for ADC1
static const PinMap PinMap_ADC[] = {
- {P_ADC0, ADC0_0, 0x08},
- {P_ADC1, ADC0_1, 0x07},
- {P_ADC2, ADC0_2, 0x01},
- {P_ADC3, ADC0_3, 0x08},
- {P_ADC4, ADC0_4, 0x08},
- {P_ADC5, ADC0_5, 0x08},
- {NC , NC , 0 }
+ {P4_3, ADC0_0, 0},
+ {P4_1, ADC0_1, 0},
+ {PF_8, ADC0_2, 0},
+ {P7_5, ADC0_3, 0},
+ {P7_4, ADC0_4, 0},
+ {PF_10, ADC0_5, 0},
+ {PB_6, ADC0_6, 0},
+ {PC_3, ADC1_0, 0},
+ {PC_0, ADC1_1, 0},
+ {PF_9, ADC1_2, 0},
+ {PF_6, ADC1_3, 0},
+ {PF_5, ADC1_4, 0},
+ {PF_11, ADC1_5, 0},
+ {P7_7, ADC1_6, 0},
+ {PF_7, ADC1_7, 0},
+ {NC, NC, 0 }
};
void analogin_init(analogin_t *obj, PinName pin) {
- uint8_t num, chan;
+ ADCName name;
- obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
- MBED_ASSERT(obj->adc != (ADCName)NC);
+ name = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+ MBED_ASSERT(obj->adc != (LPC_ADC_T *)NC);
- // Configure the pin as GPIO input
- if (pin < SFP_AIO0) {
- pin_function(pin, (SCU_PINIO_PULLNONE | 0x0));
- pin_mode(pin, PullNone);
- num = (uint8_t)(obj->adc) / 8; // Heuristic?
- chan = (uint8_t)(obj->adc) % 7;
- } else {
- num = MBED_ADC_NUM(pin);
- chan = MBED_ADC_CHAN(pin);
- }
+ // Set ADC register, number and channel
+ obj->num = (name >> ADC0_7) ? 1 : 0;
+ obj->ch = name % (ADC0_7 + 1);
+ obj->adc = (LPC_ADC_T *) (obj->num > 0) ? LPC_ADC1 : LPC_ADC0;
+ // Reset pin function to GPIO
+ gpio_set(pin);
+ // Select ADC on analog function select register in SCU
+ LPC_SCU->ENAIO[obj->num] |= (1 << obj->ch);
+
// Calculate minimum clock divider
// clkdiv = divider - 1
- uint32_t PCLK = SystemCoreClock;
+ uint32_t PCLK = SystemCoreClock;
uint32_t adcRate = 400000;
uint32_t clkdiv = div_round_up(PCLK, adcRate) - 1;
// Set the generic software-controlled ADC settings
- LPC_ADC0->CR = (0 << 0) // SEL: 0 = no channels selected
+ obj->adc->CR = (0 << 0) // SEL: 0 = no channels selected
| (clkdiv << 8) // CLKDIV:
| (0 << 16) // BURST: 0 = software control
| (1 << 21) // PDN: 1 = operational
| (0 << 24) // START: 0 = no start
| (0 << 27); // EDGE: not applicable
-
- // Select ADC on analog function select register in SCU
- LPC_SCU->ENAIO[num] |= 1UL << chan;
}
static inline uint32_t adc_read(analogin_t *obj) {
+ uint32_t temp;
+ uint8_t channel = obj->ch;
+ LPC_ADC_T *pADC = obj->adc;
+
// Select the appropriate channel and start conversion
- LPC_ADC0->CR &= ~0xFF;
- LPC_ADC0->CR |= 1 << (int)obj->adc;
- LPC_ADC0->CR |= 1 << 24;
+ pADC->CR |= ADC_CR_CH_SEL(channel);
+ temp = pADC->CR & ~ADC_CR_START_MASK;
+ pADC->CR = temp | (ADC_CR_START_MODE_SEL(ADC_START_NOW));
- // Repeatedly get the sample data until DONE bit
- unsigned int data;
- do {
- data = LPC_ADC0->GDR;
- } while ((data & ((unsigned int)1 << 31)) == 0);
+ // Wait for DONE bit and read data
+ while (!(pADC->STAT & ADC_CR_CH_SEL(channel)));
+ temp = pADC->DR[channel];
- // Stop conversion
- LPC_ADC0->CR &= ~(1 << 24);
-
- return (data >> 6) & ADC_RANGE; // 10 bit
+ // Deselect channel and return result
+ pADC->CR &= ~ADC_CR_START_MASK;
+ pADC->CR &= ~ADC_CR_CH_SEL(channel);
+ return ADC_DR_RESULT(temp);
}
static inline void order(uint32_t *a, uint32_t *b) {
--- a/targets/hal/TARGET_NXP/TARGET_LPC43XX/analogout_api.c Fri Jul 11 10:00:08 2014 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC43XX/analogout_api.c Tue Jul 15 07:45:08 2014 +0100
@@ -17,26 +17,30 @@
*/
#include "mbed_assert.h"
#include "analogout_api.h"
+
#include "cmsis.h"
#include "pinmap.h"
+#include "error.h"
+#include "gpio_api.h"
static const PinMap PinMap_DAC[] = {
- {P_DAC0 , DAC_0, 0x0},
- {NC , NC , 0}
+ {P4_4, DAC_0, 0},
+ {NC, NC, 0}
};
void analogout_init(dac_t *obj, PinName pin) {
obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
MBED_ASSERT(obj->dac != (DACName)NC);
- // Configure the pin as GPIO input
- pin_function(pin, (SCU_PINIO_PULLNONE | 0x0));
- pin_mode(pin, PullNone);
+ // Reset pin function to GPIO
+ gpio_set(pin);
// Select DAC on analog function select register in SCU
- LPC_SCU->ENAIO[2] |= 1; // Sets pin P4_4 as DAC
+ LPC_SCU->ENAIO[2] |= 1; // Sets pin as DAC
- // Set Maximum update rate for DAC */
+ // Set bias=0 for maximum DAC update rate (1 MHz)
LPC_DAC->CR &= ~DAC_BIAS_EN;
+ // Enable DAC and DMA
+ LPC_DAC->CTRL |= DAC_DMA_ENA;
analogout_write_u16(obj, 0);
}
@@ -44,16 +48,13 @@
void analogout_free(dac_t *obj) {}
static inline void dac_write(int value) {
- uint32_t tmp;
// Set the DAC output
- tmp = LPC_DAC->CR & DAC_BIAS_EN;
- tmp |= DAC_VALUE(value);
- LPC_DAC->CR = tmp;
+ LPC_DAC->CR = DAC_SET(value);
}
static inline int dac_read() {
- return (DAC_VALUE(LPC_DAC->CR));
+ return (DAC_GET(LPC_DAC->CR));
}
void analogout_write(dac_t *obj, float value) {
--- a/targets/hal/TARGET_NXP/TARGET_LPC43XX/device.h Fri Jul 11 10:00:08 2014 +0100 +++ b/targets/hal/TARGET_NXP/TARGET_LPC43XX/device.h Tue Jul 15 07:45:08 2014 +0100 @@ -26,9 +26,10 @@ #define DEVICE_ANALOGOUT 1 #define DEVICE_SERIAL 1 +//#define DEVICE_SERIAL_FC 1 -#define DEVICE_I2C 0 -#define DEVICE_I2CSLAVE 0 +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 #define DEVICE_SPI 1 #define DEVICE_SPISLAVE 1 @@ -37,9 +38,9 @@ #define DEVICE_RTC 1 -#define DEVICE_ETHERNET 0 +#define DEVICE_ETHERNET 1 -#define DEVICE_PWMOUT 0 +#define DEVICE_PWMOUT 1 #define DEVICE_SEMIHOST 0 #define DEVICE_LOCALFILESYSTEM 0 @@ -52,7 +53,7 @@ #define DEVICE_STDIO_MESSAGES 1 -#define DEVICE_ERROR_RED 1 +#define DEVICE_ERROR_PATTERN 1 #include "objects.h"
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c Tue Jul 15 07:45:08 2014 +0100
@@ -0,0 +1,435 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
+ */
+#include "ethernet_api.h"
+
+#include <string.h>
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "toolchain.h"
+#include "error.h"
+
+#define NEW_LOGIC 0
+#define NEW_ETH_BUFFER 0
+
+#if NEW_ETH_BUFFER
+
+#define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets)
+#define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets)
+
+#define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size
+#define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length)
+
+#else
+
+// Memfree calculation:
+// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
+// (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
+#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
+#define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
+//#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
+
+//#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
+#define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */
+#define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */
+
+const int ethernet_MTU_SIZE = 0x300;
+
+#endif
+
+#define ETHERNET_ADDR_SIZE 6
+
+PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */
+ unsigned int Packet;
+ unsigned int Ctrl;
+};
+typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
+
+PACKED struct RX_STAT_TypeDef { /* RX Status struct */
+ unsigned int Info;
+ unsigned int HashCRC;
+};
+typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
+
+PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */
+ unsigned int Packet;
+ unsigned int Ctrl;
+};
+typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
+
+PACKED struct TX_STAT_TypeDef { /* TX Status struct */
+ unsigned int Info;
+};
+typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
+
+/* MAC Configuration Register 1 */
+#define MAC1_REC_EN 0x00000001 /* Receive Enable */
+#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
+#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
+#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
+#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
+#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
+#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
+#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
+#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
+#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
+#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
+
+/* MAC Configuration Register 2 */
+#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
+#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
+#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
+#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
+#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
+#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
+#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
+#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
+#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
+#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
+#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
+#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
+#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
+
+/* Back-to-Back Inter-Packet-Gap Register */
+#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
+#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
+
+/* Non Back-to-Back Inter-Packet-Gap Register */
+#define IPGR_DEF 0x00000012 /* Recommended value */
+
+/* Collision Window/Retry Register */
+#define CLRT_DEF 0x0000370F /* Default value */
+
+/* PHY Support Register */
+#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
+//#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
+#define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */
+
+/* Test Register */
+#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
+#define TEST_TST_PAUSE 0x00000002 /* Test Pause */
+#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
+
+/* MII Management Configuration Register */
+#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
+#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
+#define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */
+#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
+
+/* MII Management Command Register */
+#define MCMD_READ 0x00000001 /* MII Read */
+#define MCMD_SCAN 0x00000002 /* MII Scan continuously */
+
+#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
+#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
+
+/* MII Management Address Register */
+#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
+#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
+
+/* MII Management Indicators Register */
+#define MIND_BUSY 0x00000001 /* MII is Busy */
+#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
+#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
+#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
+
+/* Command Register */
+#define CR_RX_EN 0x00000001 /* Enable Receive */
+#define CR_TX_EN 0x00000002 /* Enable Transmit */
+#define CR_REG_RES 0x00000008 /* Reset Host Registers */
+#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
+#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
+#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
+#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
+#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
+#define CR_RMII 0x00000200 /* Reduced MII Interface */
+#define CR_FULL_DUP 0x00000400 /* Full Duplex */
+
+/* Status Register */
+#define SR_RX_EN 0x00000001 /* Enable Receive */
+#define SR_TX_EN 0x00000002 /* Enable Transmit */
+
+/* Transmit Status Vector 0 Register */
+#define TSV0_CRC_ERR 0x00000001 /* CRC error */
+#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
+#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
+#define TSV0_DONE 0x00000008 /* Tramsmission Completed */
+#define TSV0_MCAST 0x00000010 /* Multicast Destination */
+#define TSV0_BCAST 0x00000020 /* Broadcast Destination */
+#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
+#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
+#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
+#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
+#define TSV0_GIANT 0x00000400 /* Giant Frame */
+#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
+#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
+#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
+#define TSV0_PAUSE 0x20000000 /* Pause Frame */
+#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
+#define TSV0_VLAN 0x80000000 /* VLAN Frame */
+
+/* Transmit Status Vector 1 Register */
+#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
+#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
+
+/* Receive Status Vector Register */
+#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
+#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
+#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
+#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
+#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
+#define RSV_CRC_ERR 0x00100000 /* CRC Error */
+#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
+#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
+#define RSV_REC_OK 0x00800000 /* Frame Received OK */
+#define RSV_MCAST 0x01000000 /* Multicast Frame */
+#define RSV_BCAST 0x02000000 /* Broadcast Frame */
+#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
+#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
+#define RSV_PAUSE 0x10000000 /* Pause Frame */
+#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
+#define RSV_VLAN 0x40000000 /* VLAN Frame */
+
+/* Flow Control Counter Register */
+#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
+#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
+
+/* Flow Control Status Register */
+#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
+
+/* Receive Filter Control Register */
+#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
+#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
+#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
+#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
+#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
+#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
+#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
+#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
+
+/* Receive Filter WoL Status/Clear Registers */
+#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
+#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
+#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
+#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
+#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
+#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
+#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
+#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
+
+/* Interrupt Status/Enable/Clear/Set Registers */
+#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
+#define INT_RX_ERR 0x00000002 /* Receive Error */
+#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
+#define INT_RX_DONE 0x00000008 /* Receive Done */
+#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
+#define INT_TX_ERR 0x00000020 /* Transmit Error */
+#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
+#define INT_TX_DONE 0x00000080 /* Transmit Done */
+#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
+#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
+
+/* Power Down Register */
+#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
+
+/* RX Descriptor Control Word */
+#define RCTRL_SIZE 0x000007FF /* Buffer size mask */
+#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
+
+/* RX Status Hash CRC Word */
+#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
+#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
+
+/* RX Status Information Word */
+#define RINFO_SIZE 0x000007FF /* Data size in bytes */
+#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
+#define RINFO_VLAN 0x00080000 /* VLAN Frame */
+#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
+#define RINFO_MCAST 0x00200000 /* Multicast Frame */
+#define RINFO_BCAST 0x00400000 /* Broadcast Frame */
+#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
+#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
+#define RINFO_LEN_ERR 0x02000000 /* Length Error */
+#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
+#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
+#define RINFO_OVERRUN 0x10000000 /* Receive overrun */
+#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
+#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
+#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
+
+//#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
+ RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+
+
+/* TX Descriptor Control Word */
+#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
+#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
+#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
+#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
+#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
+#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
+#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
+
+/* TX Status Information Word */
+#define TINFO_COL_CNT 0x01E00000 /* Collision Count */
+#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
+#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
+#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
+#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
+#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
+#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
+#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
+
+/* ENET Device Revision ID */
+#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
+
+/* DP83848C PHY Registers */
+#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
+#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
+#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
+#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
+#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
+#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
+#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
+#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
+
+/* PHY Extended Registers */
+#define PHY_REG_STS 0x10 /* Status Register */
+#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
+#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
+#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
+#define PHY_REG_RECR 0x15 /* Receive Error Counter */
+#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
+#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
+#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
+#define PHY_REG_PHYCR 0x19 /* PHY Control Register */
+#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
+#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
+#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
+
+#define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */
+
+#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
+#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
+#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
+#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
+#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
+
+#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
+#define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */
+
+#define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */
+
+#define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */
+#define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */
+#define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */
+
+#define PHY_BMCR_RESET 0x8000 /* PHY Reset */
+
+#define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */
+
+#define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */
+#define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */
+
+#if defined (__ICCARM__)
+# define AHBSRAM1
+#elif defined(TOOLCHAIN_GCC_CR)
+# define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
+#else
+# define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned))
+#endif
+
+AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
+AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
+AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
+AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
+AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
+AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
+
+#ifndef min
+#define min(x, y) (((x)<(y))?(x):(y))
+#endif
+
+/*----------------------------------------------------------------------------
+ Ethernet Device initialize
+ *----------------------------------------------------------------------------*/
+int ethernet_init() {
+ return 0;
+}
+
+/*----------------------------------------------------------------------------
+ Ethernet Device Uninitialize
+ *----------------------------------------------------------------------------*/
+void ethernet_free() {
+}
+
+// if(TxProduceIndex == TxConsumeIndex) buffer array is empty
+// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
+// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
+// TxConsumeIndex - The buffer that will/is beign sent by hardware
+
+int ethernet_write(const char *data, int slen) {
+ return -1;
+}
+
+int ethernet_send() {
+ return -1;
+}
+
+// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
+// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
+//
+// if(RxConsumeIndex == RxProduceIndex) buffer array is empty
+// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
+
+// Recevies an arrived ethernet packet.
+// Receiving an ethernet packet will drop the last received ethernet packet
+// and make a new ethernet packet ready to read.
+// Returns size of packet, else 0 if nothing to receive
+
+// We read from RxConsumeIndex from position rx_consume_offset
+// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
+// rx_consume_offset = -1 // no frame
+// rx_consume_offset = 0 // start of frame
+// Assumption: A fragment should alway be a whole frame
+
+int ethernet_receive() {
+ return -1;
+}
+
+// Read from an recevied ethernet packet.
+// After receive returnd a number bigger than 0 it is
+// possible to read bytes from this packet.
+// Read will write up to size bytes into data.
+// It is possible to use read multible times.
+// Each time read will start reading after the last read byte before.
+
+int ethernet_read(char *data, int dlen) {
+ return -1;
+}
+
+int ethernet_link(void) {
+ return -1;
+}
+
+void ethernet_address(char *mac) {
+}
+
+void ethernet_set_link(int speed, int duplex) {
+}
--- a/targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_irq_api.c Fri Jul 11 10:00:08 2014 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_irq_api.c Tue Jul 15 07:45:08 2014 +0100
@@ -28,13 +28,13 @@
* A future implementation may provide group interrupt support.
*/
#if !defined(CORE_M0)
-#define CHANNEL_NUM 8
+#define CHANNEL_MAX 8
#else
-#define CHANNEL_NUM 1
+#define CHANNEL_MAX 1
#endif
-static uint32_t channel_ids[CHANNEL_NUM] = {0};
-static uint32_t channel = 0;
+static uint32_t channel_ids[CHANNEL_MAX] = {0};
+static uint8_t channel = 0;
static gpio_irq_handler irq_handler;
static void handle_interrupt_in(void) {
@@ -43,19 +43,21 @@
uint32_t pmask;
int i;
- for (i = 0; i < CHANNEL_NUM; i++) {
+ for (i = 0; i < CHANNEL_MAX; i++) {
pmask = (1 << i);
if (rise & pmask) {
/* Rising edge interrupts */
- if (channel_ids[i] != 0)
+ if (channel_ids[i] != 0) {
irq_handler(channel_ids[i], IRQ_RISE);
+ }
/* Clear rising edge detected */
LPC_GPIO_PIN_INT->RISE = pmask;
}
if (fall & pmask) {
/* Falling edge interrupts */
- if (channel_ids[i] != 0)
+ if (channel_ids[i] != 0) {
irq_handler(channel_ids[i], IRQ_FALL);
+ }
/* Clear falling edge detected */
LPC_GPIO_PIN_INT->FALL = pmask;
}
@@ -100,7 +102,7 @@
// Increment channel number
channel++;
- channel %= CHANNEL_NUM;
+ channel %= CHANNEL_MAX;
return 0;
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC43XX/i2c_api.c Tue Jul 15 07:45:08 2014 +0100
@@ -0,0 +1,391 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
+ */
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_I2C_SDA[] = {
+ {P_DED, I2C_0, 0},
+ {P2_3, I2C_1, 1},
+ {PE_13, I2C_1, 2},
+ {NC, NC, 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+ {P_DED, I2C_0, 0},
+ {P2_4, I2C_1, 1},
+ {PE_14, I2C_1, 2},
+ {NC, NC, 0}
+};
+
+#define I2C_CONSET(x) (x->i2c->CONSET)
+#define I2C_CONCLR(x) (x->i2c->CONCLR)
+#define I2C_STAT(x) (x->i2c->STAT)
+#define I2C_DAT(x) (x->i2c->DAT)
+#define I2C_SCLL(x, val) (x->i2c->SCLL = val)
+#define I2C_SCLH(x, val) (x->i2c->SCLH = val)
+
+static const uint32_t I2C_addr_offset[2][4] = {
+ {0x0C, 0x20, 0x24, 0x28},
+ {0x30, 0x34, 0x38, 0x3C}
+};
+
+static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+ I2C_CONCLR(obj) = (start << 5)
+ | (stop << 4)
+ | (interrupt << 3)
+ | (acknowledge << 2);
+}
+
+static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+ I2C_CONSET(obj) = (start << 5)
+ | (stop << 4)
+ | (interrupt << 3)
+ | (acknowledge << 2);
+}
+
+// Clear the Serial Interrupt (SI)
+static inline void i2c_clear_SI(i2c_t *obj) {
+ i2c_conclr(obj, 0, 0, 1, 0);
+}
+
+static inline int i2c_status(i2c_t *obj) {
+ return I2C_STAT(obj);
+}
+
+// Wait until the Serial Interrupt (SI) is set
+static int i2c_wait_SI(i2c_t *obj) {
+ int timeout = 0;
+ while (!(I2C_CONSET(obj) & (1 << 3))) {
+ timeout++;
+ if (timeout > 100000) return -1;
+ }
+ return 0;
+}
+
+static inline void i2c_interface_enable(i2c_t *obj) {
+ I2C_CONSET(obj) = 0x40;
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+ // determine the SPI to use
+ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+ I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+ obj->i2c = (LPC_I2C_T *)pinmap_merge(i2c_sda, i2c_scl);
+
+ if ((int)obj->i2c == NC) {
+ error("I2C pin mapping failed");
+ }
+
+ // set default frequency at 100k
+ i2c_frequency(obj, 100000);
+ i2c_conclr(obj, 1, 1, 1, 1);
+ i2c_interface_enable(obj);
+
+ // If pins are not dedicated, set SCU functions
+ if (sda != P_DED) {
+ pinmap_pinout(sda, PinMap_I2C_SDA);
+ }
+ if (scl != P_DED) {
+ pinmap_pinout(scl, PinMap_I2C_SCL);
+ }
+}
+
+inline int i2c_start(i2c_t *obj) {
+ int status = 0;
+ // 8.1 Before master mode can be entered, I2CON must be initialised to:
+ // - I2EN STA STO SI AA - -
+ // - 1 0 0 0 x - -
+ // if AA = 0, it can't enter slave mode
+ i2c_conclr(obj, 1, 1, 1, 1);
+
+ // The master mode may now be entered by setting the STA bit
+ // this will generate a start condition when the bus becomes free
+ i2c_conset(obj, 1, 0, 0, 1);
+
+ i2c_wait_SI(obj);
+ status = i2c_status(obj);
+
+ // Clear start bit now transmitted, and interrupt bit
+ i2c_conclr(obj, 1, 0, 0, 0);
+ return status;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+ int timeout = 0;
+
+ // write the stop bit
+ i2c_conset(obj, 0, 1, 0, 0);
+ i2c_clear_SI(obj);
+
+ // wait for STO bit to reset
+ while(I2C_CONSET(obj) & (1 << 4)) {
+ timeout ++;
+ if (timeout > 100000) return 1;
+ }
+
+ return 0;
+}
+
+static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
+ // write the data
+ I2C_DAT(obj) = value;
+
+ // clear SI to init a send
+ i2c_clear_SI(obj);
+
+ // wait and return status
+ i2c_wait_SI(obj);
+ return i2c_status(obj);
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last) {
+ // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
+ if(last) {
+ i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
+ } else {
+ i2c_conset(obj, 0, 0, 0, 1); // send a ACK
+ }
+
+ // accept byte
+ i2c_clear_SI(obj);
+
+ // wait for it to arrive
+ i2c_wait_SI(obj);
+
+ // return the data
+ return (I2C_DAT(obj) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+ // [TODO] set pclk to /4
+ uint32_t PCLK = SystemCoreClock / 4;
+
+ uint32_t pulse = PCLK / (hz * 2);
+
+ // I2C Rate
+ I2C_SCLL(obj, pulse);
+ I2C_SCLH(obj, pulse);
+}
+
+// The I2C does a read or a write as a whole operation
+// There are two types of error conditions it can encounter
+// 1) it can not obtain the bus
+// 2) it gets error responses at part of the transmission
+//
+// We tackle them as follows:
+// 1) we retry until we get the bus. we could have a "timeout" if we can not get it
+// which basically turns it in to a 2)
+// 2) on error, we use the standard error mechanisms to report/debug
+//
+// Therefore an I2C transaction should always complete. If it doesn't it is usually
+// because something is setup wrong (e.g. wiring), and we don't need to programatically
+// check for that
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+ int count, status;
+
+ status = i2c_start(obj);
+
+ if ((status != 0x10) && (status != 0x08)) {
+ i2c_stop(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+
+ status = i2c_do_write(obj, (address | 0x01), 1);
+ if (status != 0x40) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ // Read in all except last byte
+ for (count = 0; count < (length - 1); count++) {
+ int value = i2c_do_read(obj, 0);
+ status = i2c_status(obj);
+ if (status != 0x50) {
+ i2c_stop(obj);
+ return count;
+ }
+ data[count] = (char) value;
+ }
+
+ // read in last byte
+ int value = i2c_do_read(obj, 1);
+ status = i2c_status(obj);
+ if (status != 0x58) {
+ i2c_stop(obj);
+ return length - 1;
+ }
+
+ data[count] = (char) value;
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ }
+
+ return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+ int i, status;
+
+ status = i2c_start(obj);
+
+ if ((status != 0x10) && (status != 0x08)) {
+ i2c_stop(obj);
+ return I2C_ERROR_BUS_BUSY;
+ }
+
+ status = i2c_do_write(obj, (address & 0xFE), 1);
+ if (status != 0x18) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ for (i=0; i<length; i++) {
+ status = i2c_do_write(obj, data[i], 0);
+ if(status != 0x28) {
+ i2c_stop(obj);
+ return i;
+ }
+ }
+
+ // clearing the serial interrupt here might cause an unintended rewrite of the last byte
+ // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
+ // i2c_clear_SI(obj);
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ }
+
+ return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+ i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+ return (i2c_do_read(obj, last) & 0xFF);
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+ int ack;
+ int status = i2c_do_write(obj, (data & 0xFF), 0);
+
+ switch(status) {
+ case 0x18: case 0x28: // Master transmit ACKs
+ ack = 1;
+ break;
+ case 0x40: // Master receive address transmitted ACK
+ ack = 1;
+ break;
+ case 0xB8: // Slave transmit ACK
+ ack = 1;
+ break;
+ default:
+ ack = 0;
+ break;
+ }
+
+ return ack;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+ if (enable_slave != 0) {
+ i2c_conclr(obj, 1, 1, 1, 0);
+ i2c_conset(obj, 0, 0, 0, 1);
+ } else {
+ i2c_conclr(obj, 1, 1, 1, 1);
+ }
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+ int status;
+ int retval;
+
+ status = i2c_status(obj);
+ switch(status) {
+ case 0x60: retval = 3; break;
+ case 0x70: retval = 2; break;
+ case 0xA8: retval = 1; break;
+ default : retval = 0; break;
+ }
+
+ return(retval);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+ int count = 0;
+ int status;
+
+ do {
+ i2c_clear_SI(obj);
+ i2c_wait_SI(obj);
+ status = i2c_status(obj);
+ if((status == 0x80) || (status == 0x90)) {
+ data[count] = I2C_DAT(obj) & 0xFF;
+ }
+ count++;
+ } while (((status == 0x80) || (status == 0x90) ||
+ (status == 0x060) || (status == 0x70)) && (count < length));
+
+ if(status != 0xA0) {
+ i2c_stop(obj);
+ }
+
+ i2c_clear_SI(obj);
+
+ return count;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+ int count = 0;
+ int status;
+
+ if(length <= 0) {
+ return(0);
+ }
+
+ do {
+ status = i2c_do_write(obj, data[count], 0);
+ count++;
+ } while ((count < length) && (status == 0xB8));
+
+ if ((status != 0xC0) && (status != 0xC8)) {
+ i2c_stop(obj);
+ }
+
+ i2c_clear_SI(obj);
+
+ return(count);
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+ uint32_t addr;
+
+ if ((idx >= 0) && (idx <= 3)) {
+ addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
+ *((uint32_t *) addr) = address & 0xFF;
+ addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx];
+ *((uint32_t *) addr) = mask & 0xFE;
+ }
+}
--- a/targets/hal/TARGET_NXP/TARGET_LPC43XX/objects.h Fri Jul 11 10:00:08 2014 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC43XX/objects.h Tue Jul 15 07:45:08 2014 +0100
@@ -20,6 +20,7 @@
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
+#include "gpio_object.h"
#ifdef __cplusplus
extern "C" {
@@ -40,9 +41,8 @@
};
struct pwmout_s {
- __IO uint32_t *MR;
- LPC_MCPWM_T *pwm;
- uint32_t channel;
+ PWMName pwm;
+ uint8_t mr;
};
struct serial_s {
@@ -51,7 +51,9 @@
};
struct analogin_s {
- ADCName adc;
+ LPC_ADC_T *adc;
+ uint8_t num;
+ uint8_t ch;
};
struct dac_s {
@@ -70,8 +72,6 @@
LPC_SSP_T *spi;
};
-#include "gpio_object.h"
-
#ifdef __cplusplus
}
#endif
--- a/targets/hal/TARGET_NXP/TARGET_LPC43XX/pinmap.c Fri Jul 11 10:00:08 2014 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC43XX/pinmap.c Tue Jul 15 07:45:08 2014 +0100
@@ -29,7 +29,7 @@
}
void pin_mode(PinName pin, PinMode mode) {
- MBED_ASSERT((pin != (PinName)NC) && (mode == OpenDrain));
+ MBED_ASSERT(pin != (PinName)NC); // && (mode != OpenDrain));
__IO uint32_t *reg = (__IO uint32_t*) MBED_SCU_REG(pin);
uint32_t tmp = *reg;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC43XX/pwmout_api.c Tue Jul 15 07:45:08 2014 +0100
@@ -0,0 +1,266 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
+ */
+#include "mbed_assert.h"
+#include "pwmout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+// PWM implementation for the LPC43xx using State Configurable Timer (SCT)
+// * PWM_0 to PWM_15 on mbed use CTOUT_0 to CTOUT_15 outputs on LPC43xx
+// * Event 0 is PWM period, events 1 to PWM_EVENT_MAX are PWM channels
+// * Default is unified 32-bit timer, but could be configured to use
+// a 16-bit timer so a timer is available for other SCT functions
+
+// configuration options
+#define PWM_FREQ_BASE 1000000 // Base frequency 1 MHz = 1000000
+#define PWM_MODE 1 // 0 = 32-bit, 1 = 16-bit low, 2 = 16-bit high
+
+// macros
+#define PWM_SETCOUNT(x) (x - 1) // set count value
+#define PWM_GETCOUNT(x) (x + 1) // get count value
+#if (PWM_MODE == 0) // unified 32-bit counter, events 1 to 15
+ #define PWM_EVENT_MAX (CONFIG_SCT_nEV - 1) // Max PWM channels
+ #define PWM_CONFIG SCT_CONFIG_32BIT_COUNTER // default config
+ #define PWM_CTRL &LPC_SCT->CTRL_U // control register
+ #define PWM_HALT SCT_CTRL_HALT_L // halt counter
+ #define PWM_CLEAR SCT_CTRL_CLRCTR_L // clock clear
+ #define PWM_PRE(x) SCT_CTRL_PRE_L(x) // clock prescale
+ #define PWM_EVT_MASK (1 << 12) // event control mask
+ #define PWM_LIMIT &LPC_SCT->LIMIT_L // limit register
+ #define PWM_MATCH(x) &LPC_SCT->MATCH[x].U // match register
+ #define PWM_MR(x) &LPC_SCT->MATCHREL[x].U // 32-bit match reload register
+#elif (PWM_MODE == 1) // 16-bit low counter, events 1 to 7
+ #define PWM_EVENT_MAX (CONFIG_SCT_nEV/2 - 1) // Max PWM channels
+ #define PWM_CONFIG SCT_CONFIG_16BIT_COUNTER // default config
+ #define PWM_CTRL &LPC_SCT->CTRL_L // control register
+ #define PWM_HALT SCT_CTRL_HALT_L // halt counter
+ #define PWM_CLEAR SCT_CTRL_CLRCTR_L // clock clear
+ #define PWM_PRE(x) SCT_CTRL_PRE_L(x) // clock prescale
+ #define PWM_EVT_MASK (1 << 12) // event control mask
+ #define PWM_LIMIT &LPC_SCT->LIMIT_L // limit register
+ #define PWM_MATCH(x) &LPC_SCT->MATCH[x].L // match register
+ #define PWM_MR(x) &LPC_SCT->MATCHREL[x].L // 16-bit match reload register
+#elif (PWM_MODE == 2) // 16-bit high counter, events 1 to 7
+ // [TODO] use events 8 to 15 on mode 2
+ #define PWM_EVENT_MAX (CONFIG_SCT_nEV/2 - 1) // Max PWM channels
+ #define PWM_CONFIG SCT_CONFIG_16BIT_COUNTER // default config
+ #define PWM_CTRL &LPC_SCT->CTRL_H // control register
+ #define PWM_HALT SCT_CTRL_HALT_L // halt counter
+ #define PWM_CLEAR SCT_CTRL_CLRCTR_L // clock clear
+ #define PWM_PRE(x) SCT_CTRL_PRE_L(x) // clock prescale
+ #define PWM_EVT_MASK ((1 << 4) | (1 << 12)) // event control mask
+ #define PWM_LIMIT &LPC_SCT->LIMIT_H // limit register
+ #define PWM_MATCH(x) &LPC_SCT->MATCH[x].H // match register
+ #define PWM_MR(x) &LPC_SCT->MATCHREL[x].H // 16-bit match reload register
+#else
+ #error "PWM mode not implemented"
+#endif
+#define PWM_MR0 PWM_MR(0) // MR register 0 is for period
+
+static uint8_t event = 0;
+
+// PORT ID, PWM ID, Pin function
+static const PinMap PinMap_PWM[] = {
+ {P1_1, PWM_7, (SCU_PINIO_FAST | 1)},
+ {P1_2, PWM_6, (SCU_PINIO_FAST | 1)},
+ {P1_3, PWM_8, (SCU_PINIO_FAST | 1)},
+ {P1_4, PWM_9, (SCU_PINIO_FAST | 1)},
+ {P1_5, PWM_10, (SCU_PINIO_FAST | 1)},
+ {P1_7, PWM_13, (SCU_PINIO_FAST | 2)},
+ {P1_8, PWM_12, (SCU_PINIO_FAST | 2)},
+ {P1_9, PWM_11, (SCU_PINIO_FAST | 2)},
+ {P1_10, PWM_14, (SCU_PINIO_FAST | 2)},
+ {P1_11, PWM_15, (SCU_PINIO_FAST | 2)},
+ {P2_7, PWM_1, (SCU_PINIO_FAST | 1)},
+ {P2_8, PWM_0, (SCU_PINIO_FAST | 1)},
+ {P2_9, PWM_3, (SCU_PINIO_FAST | 1)},
+ {P2_10, PWM_2, (SCU_PINIO_FAST | 1)},
+ {P2_11, PWM_5, (SCU_PINIO_FAST | 1)},
+ {P2_12, PWM_4, (SCU_PINIO_FAST | 1)},
+ {P4_1, PWM_1, (SCU_PINIO_FAST | 1)},
+ {P4_2, PWM_0, (SCU_PINIO_FAST | 1)},
+ {P4_3, PWM_3, (SCU_PINIO_FAST | 1)},
+ {P4_4, PWM_2, (SCU_PINIO_FAST | 1)},
+ {P4_5, PWM_5, (SCU_PINIO_FAST | 1)},
+ {P4_6, PWM_4, (SCU_PINIO_FAST | 1)},
+ {P6_5, PWM_6, (SCU_PINIO_FAST | 1)},
+ {P6_12, PWM_7, (SCU_PINIO_FAST | 1)},
+ {P7_0, PWM_14, (SCU_PINIO_FAST | 1)},
+ {P7_1, PWM_15, (SCU_PINIO_FAST | 1)},
+ {P7_4, PWM_13, (SCU_PINIO_FAST | 1)},
+ {P7_5, PWM_12, (SCU_PINIO_FAST | 1)},
+ {P7_6, PWM_11, (SCU_PINIO_FAST | 1)},
+ {P7_7, PWM_8, (SCU_PINIO_FAST | 1)},
+ {PA_4, PWM_9, (SCU_PINIO_FAST | 1)},
+ {PB_0, PWM_10, (SCU_PINIO_FAST | 1)},
+ {PB_1, PWM_6, (SCU_PINIO_FAST | 5)},
+ {PB_2, PWM_7, (SCU_PINIO_FAST | 5)},
+ {PB_3, PWM_8, (SCU_PINIO_FAST | 5)},
+ {PD_0, PWM_15, (SCU_PINIO_FAST | 1)},
+ {PD_2, PWM_7, (SCU_PINIO_FAST | 1)},
+ {PD_3, PWM_6, (SCU_PINIO_FAST | 1)},
+ {PD_4, PWM_8, (SCU_PINIO_FAST | 1)},
+ {PD_5, PWM_9, (SCU_PINIO_FAST | 1)},
+ {PD_6, PWM_10, (SCU_PINIO_FAST | 1)},
+ {PD_9, PWM_13, (SCU_PINIO_FAST | 1)},
+ {PD_11, PWM_14, (SCU_PINIO_FAST | 6)},
+ {PD_12, PWM_10, (SCU_PINIO_FAST | 6)},
+ {PD_13, PWM_13, (SCU_PINIO_FAST | 6)},
+ {PD_14, PWM_11, (SCU_PINIO_FAST | 6)},
+ {PD_15, PWM_8, (SCU_PINIO_FAST | 6)},
+ {PD_16, PWM_12, (SCU_PINIO_FAST | 6)},
+ {PE_5, PWM_3, (SCU_PINIO_FAST | 1)},
+ {PE_6, PWM_2, (SCU_PINIO_FAST | 1)},
+ {PE_7, PWM_5, (SCU_PINIO_FAST | 1)},
+ {PE_8, PWM_4, (SCU_PINIO_FAST | 1)},
+ {PE_11, PWM_12, (SCU_PINIO_FAST | 1)},
+ {PE_12, PWM_11, (SCU_PINIO_FAST | 1)},
+ {PE_13, PWM_14, (SCU_PINIO_FAST | 1)},
+ {PE_15, PWM_0, (SCU_PINIO_FAST | 1)},
+ {PF_9, PWM_1, (SCU_PINIO_FAST | 2)},
+ {NC, NC, 0}
+};
+
+static unsigned int pwm_clock_mhz;
+
+static void _pwmout_dev_init() {
+ uint32_t i;
+
+ // set SCT clock and config
+ LPC_CCU1->CLKCCU[CLK_MX_SCT].CFG = (1 << 0); // enable SCT clock in CCU1
+ LPC_SCT->CONFIG |= PWM_CONFIG; // set config options
+ *PWM_CTRL |= PWM_HALT; // set HALT bit to stop counter
+ // clear counter and set prescaler for desired freq
+ *PWM_CTRL |= PWM_CLEAR | PWM_PRE(SystemCoreClock / PWM_FREQ_BASE - 1);
+ pwm_clock_mhz = PWM_FREQ_BASE / 1000000;
+
+ // configure SCT events
+ for (i = 0; i < PWM_EVENT_MAX; i++) {
+ *PWM_MATCH(i) = 0; // match register
+ *PWM_MR(i) = 0; // match reload register
+ LPC_SCT->EVENT[i].STATE = 0xFFFFFFFF; // event happens in all states
+ LPC_SCT->EVENT[i].CTRL = (i << 0) | PWM_EVT_MASK; // match condition only
+ }
+ *PWM_LIMIT = (1 << 0) ; // set event 0 as limit
+ // initialize period to 20ms: standard for servos, and fine for e.g. brightness control
+ *PWM_MR0 = PWM_SETCOUNT((uint32_t)(((20 * PWM_FREQ_BASE) / 1000000) * 1000));
+
+ // initialize SCT outputs
+ for (i = 0; i < CONFIG_SCT_nOU; i++) {
+ LPC_SCT->OUT[i].SET = (1 << 0); // event 0 will set SCTOUT_xx
+ LPC_SCT->OUT[i].CLR = 0; // set clear event when duty cycle
+ }
+ LPC_SCT->OUTPUT = 0; // default outputs to clear
+
+ *PWM_CTRL &= ~PWM_HALT; // clear HALT bit to start counter
+}
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+ // determine the channel
+ PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+ MBED_ASSERT((pwm != (PWMName)NC) && (event < PWM_EVENT_MAX));
+
+ // init SCT clock and outputs on first PWM init
+ if (event == 0) {
+ _pwmout_dev_init();
+ }
+ // init PWM object
+ event++;
+ obj->pwm = pwm; // pwm output
+ obj->mr = event; // index of match reload register
+
+ // initial duty cycle is 0
+ pwmout_write(obj, 0);
+
+ // Wire pinout
+ pinmap_pinout(pin, PinMap_PWM);
+}
+
+void pwmout_free(pwmout_t* obj) {
+ // [TODO]
+}
+
+void pwmout_write(pwmout_t* obj, float value) {
+ if (value < 0.0f) {
+ value = 0.0;
+ } else if (value > 1.0f) {
+ value = 1.0;
+ }
+
+ // set new pulse width
+ uint32_t us = (uint32_t)((float)PWM_GETCOUNT(*PWM_MR0) * value) * pwm_clock_mhz;
+ pwmout_pulsewidth_us(obj, us);
+}
+
+float pwmout_read(pwmout_t* obj) {
+ float v = (float)PWM_GETCOUNT(*PWM_MR(obj->mr)) / (float)PWM_GETCOUNT(*PWM_MR0);
+ return (v > 1.0f) ? (1.0f) : (v);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+ pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+ pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us) {
+ // calculate number of ticks
+ uint32_t ticks = pwm_clock_mhz * us;
+ uint32_t old_ticks = PWM_GETCOUNT(*PWM_MR0);
+ uint32_t i, v;
+
+ // set new period
+ *PWM_MR0 = PWM_SETCOUNT(ticks);
+
+ // Scale pulse widths to preserve the duty ratio
+ for (i = 1; i < PWM_EVENT_MAX; i++) {
+ v = PWM_GETCOUNT(*PWM_MR(i));
+ if (v > 1) {
+ v = (v * ticks) / old_ticks;
+ *PWM_MR(i) = PWM_SETCOUNT(v);
+ }
+ }
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+ pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+ pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+ // calculate number of ticks
+ uint32_t v = pwm_clock_mhz * us;
+ //MBED_ASSERT(PWM_GETCOUNT(*PWM_MR0) >= v);
+
+ if (v > 0) {
+ // set new match register value and enable SCT output
+ *PWM_MR(obj->mr) = PWM_SETCOUNT(v);
+ LPC_SCT->OUT[obj->pwm].CLR = (1 << obj->mr); // on event will clear PWM_XX
+ } else {
+ // set match to zero and disable SCT output
+ *PWM_MR(obj->mr) = 0;
+ LPC_SCT->OUT[obj->pwm].CLR = 0;
+ }
+}
--- a/targets/hal/TARGET_NXP/TARGET_LPC43XX/serial_api.c Fri Jul 11 10:00:08 2014 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC43XX/serial_api.c Tue Jul 15 07:45:08 2014 +0100
@@ -24,34 +24,87 @@
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
+#include "gpio_api.h"
/******************************************************************************
* INITIALIZATION
******************************************************************************/
+#define UART_NUM 4
+
static const PinMap PinMap_UART_TX[] = {
- {UART0_TX, UART_0, (SCU_PINIO_PULLDOWN | 2)},
- {UART1_TX, UART_1, (SCU_PINIO_PULLDOWN | 4)},
- {UART2_TX, UART_2, (SCU_PINIO_PULLDOWN | 2)},
- {UART3_TX, UART_3, (SCU_PINIO_PULLDOWN | 2)},
- {NC , NC , 0}
+ {P1_13, UART_1, (SCU_MODE_PULLDOWN | 1)},
+ {P1_15, UART_2, (SCU_MODE_PULLDOWN | 1)},
+ {P2_0, UART_0, (SCU_MODE_PULLDOWN | 1)},
+ {P2_3, UART_3, (SCU_MODE_PULLDOWN | 2)},
+ {P2_10, UART_2, (SCU_MODE_PULLDOWN | 2)},
+ {P3_4, UART_1, (SCU_MODE_PULLDOWN | 4)},
+ {P4_1, UART_3, (SCU_MODE_PULLDOWN | 6)},
+ {P5_6, UART_1, (SCU_MODE_PULLDOWN | 4)},
+ {P6_4, UART_0, (SCU_MODE_PULLDOWN | 2)},
+ {P7_1, UART_2, (SCU_MODE_PULLDOWN | 6)},
+ {P9_3, UART_3, (SCU_MODE_PULLDOWN | 7)},
+ {P9_5, UART_0, (SCU_MODE_PULLDOWN | 7)},
+ {PA_1, UART_2, (SCU_MODE_PULLDOWN | 3)},
+ {PC_13, UART_1, (SCU_MODE_PULLDOWN | 2)},
+ {PE_11, UART_1, (SCU_MODE_PULLDOWN | 2)},
+ {PF_2, UART_3, (SCU_MODE_PULLDOWN | 1)},
+ {PF_10, UART_0, (SCU_MODE_PULLDOWN | 1)},
+ {NC, NC, 0}
};
static const PinMap PinMap_UART_RX[] = {
- {UART0_RX, UART_0, (SCU_PINIO_PULLDOWN | 2)},
- {UART1_RX, UART_1, (SCU_PINIO_PULLDOWN | 1)},
- {UART2_RX, UART_2, (SCU_PINIO_PULLDOWN | 2)},
- {UART3_RX, UART_3, (SCU_PINIO_PULLDOWN | 2)},
- {NC , NC , 0}
+ {P1_14, UART_1, (SCU_PINIO_PULLNONE | 1)},
+ {P1_16, UART_2, (SCU_PINIO_PULLNONE | 1)},
+ {P2_1, UART_0, (SCU_PINIO_PULLNONE | 1)},
+ {P2_4, UART_3, (SCU_PINIO_PULLNONE | 2)},
+ {P2_11, UART_2, (SCU_PINIO_PULLNONE | 2)},
+ {P3_5, UART_1, (SCU_PINIO_PULLNONE | 4)},
+ {P4_2, UART_3, (SCU_PINIO_PULLNONE | 6)},
+ {P5_7, UART_1, (SCU_PINIO_PULLNONE | 4)},
+ {P6_5, UART_0, (SCU_PINIO_PULLNONE | 2)},
+ {P7_2, UART_2, (SCU_PINIO_PULLNONE | 6)},
+ {P9_4, UART_3, (SCU_PINIO_PULLNONE | 7)},
+ {P9_6, UART_0, (SCU_PINIO_PULLNONE | 7)},
+ {PA_2, UART_2, (SCU_PINIO_PULLNONE | 3)},
+ {PC_14, UART_1, (SCU_PINIO_PULLNONE | 2)},
+ {PE_12, UART_1, (SCU_PINIO_PULLNONE | 2)},
+ {PF_3, UART_3, (SCU_PINIO_PULLNONE | 1)},
+ {PF_11, UART_0, (SCU_PINIO_PULLNONE | 1)},
+ {NC, NC, 0}
};
-#define UART_NUM 4
+#if (DEVICE_SERIAL_FC)
+// RTS/CTS PinMap for flow control
+static const PinMap PinMap_UART_RTS[] = {
+ {P1_9, UART_1, (SCU_PINIO_FAST | 1)},
+ {P5_2, UART_1, (SCU_PINIO_FAST | 4)},
+ {PC_3, UART_1, (SCU_PINIO_FAST | 2)},
+ {PE_5, UART_1, (SCU_PINIO_FAST | 2)},
+ {NC, NC, 0}
+};
-static uint32_t serial_irq_ids[UART_NUM] = {0};
+static const PinMap PinMap_UART_CTS[] = {
+ {P1_11, UART_1, (SCU_PINIO_FAST | 1)},
+ {P5_4, UART_1, (SCU_PINIO_FAST | 4),
+ {PC_2, UART_1, (SCU_PINIO_FAST | 2)},
+ {PE_7, UART_1, (SCU_PINIO_FAST | 2)},
+ {NC, NC, 0}
+};
+#endif
+
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
+struct serial_global_data_s {
+ uint32_t serial_irq_id;
+ gpio_t sw_rts, sw_cts;
+ uint8_t count, rx_irq_set_flow, rx_irq_set_api;
+};
+
+static struct serial_global_data_s uart_data[UART_NUM];
+
void serial_init(serial_t *obj, PinName tx, PinName rx) {
int is_stdio_uart = 0;
@@ -77,7 +130,8 @@
| 0 << 2; // Rx Line Status irq enable
// set default baud rate and format
- serial_baud (obj, 9600);
+ is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
+ serial_baud (obj, is_stdio_uart ? 115200 : 9600);
serial_format(obj, 8, ParityNone, 1);
// pinout the chosen uart
@@ -92,15 +146,11 @@
case UART_0: obj->index = 0; break;
case UART_1: obj->index = 1; break;
case UART_2: obj->index = 2; break;
-#if (UART_NUM > 3)
case UART_3: obj->index = 3; break;
-#endif
-#if (UART_NUM > 4)
- case UART_4: obj->index = 4; break;
-#endif
}
-
- is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
+ uart_data[obj->index].sw_rts.pin = NC;
+ uart_data[obj->index].sw_cts.pin = NC;
+ serial_set_flow_control(obj, FlowControlNone, NC, NC);
if (is_stdio_uart) {
stdio_uart_inited = 1;
@@ -109,14 +159,14 @@
}
void serial_free(serial_t *obj) {
- serial_irq_ids[obj->index] = 0;
+ uart_data[obj->index].serial_irq_id = 0;
}
// serial_baud
// set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate) {
uint32_t PCLK = SystemCoreClock;
-
+
// First we check to see if the basic divide with no DivAddVal/MulVal
// ratio gives us an integer result. If it does, we set DivAddVal = 0,
// MulVal = 1. Otherwise, we search the valid ratio value range to find
@@ -192,12 +242,16 @@
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
- MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
- MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits
- MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
- (parity == ParityForced1) || (parity == ParityForced0));
-
+ // 0: 1 stop bits, 1: 2 stop bits
+ if (stop_bits != 1 && stop_bits != 2) {
+ error("Invalid stop bits specified");
+ }
stop_bits -= 1;
+
+ // 0: 5 data bits ... 3: 8 data bits
+ if (data_bits < 5 || data_bits > 8) {
+ error("Invalid number of bits (%d) in serial format, should be 5..8", data_bits);
+ }
data_bits -= 5;
int parity_enable, parity_select;
@@ -208,7 +262,8 @@
case ParityForced1: parity_enable = 1; parity_select = 2; break;
case ParityForced0: parity_enable = 1; parity_select = 3; break;
default:
- break;
+ error("Invalid serial parity setting");
+ return;
}
obj->uart->LCR = data_bits << 0
@@ -220,7 +275,7 @@
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
-static inline void uart_irq(uint32_t iir, uint32_t index) {
+static inline void uart_irq(uint32_t iir, uint32_t index, LPC_USART_T *puart) {
// [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
SerialIrq irq_type;
switch (iir) {
@@ -228,27 +283,33 @@
case 2: irq_type = RxIrq; break;
default: return;
}
-
- if (serial_irq_ids[index] != 0)
- irq_handler(serial_irq_ids[index], irq_type);
+ if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) {
+ gpio_write(&uart_data[index].sw_rts, 1);
+ // Disable interrupt if it wasn't enabled by other part of the application
+ if (!uart_data[index].rx_irq_set_api)
+ puart->IER &= ~(1 << RxIrq);
+ }
+ if (uart_data[index].serial_irq_id != 0)
+ if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
+ irq_handler(uart_data[index].serial_irq_id, irq_type);
}
-void uart0_irq() {uart_irq((LPC_USART0->IIR >> 1) & 0x7, 0);}
-void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1);}
-void uart2_irq() {uart_irq((LPC_USART2->IIR >> 1) & 0x7, 2);}
-void uart3_irq() {uart_irq((LPC_USART3->IIR >> 1) & 0x7, 3);}
+void uart0_irq() {uart_irq((LPC_USART0->IIR >> 1) & 0x7, 0, (LPC_USART_T*)LPC_USART0);}
+void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1, (LPC_USART_T*)LPC_UART1);}
+void uart2_irq() {uart_irq((LPC_USART2->IIR >> 1) & 0x7, 2, (LPC_USART_T*)LPC_USART2);}
+void uart3_irq() {uart_irq((LPC_USART3->IIR >> 1) & 0x7, 3, (LPC_USART_T*)LPC_USART3);}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler;
- serial_irq_ids[obj->index] = id;
+ uart_data[obj->index].serial_irq_id = id;
}
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
switch ((int)obj->uart) {
case UART_0: irq_n=USART0_IRQn; vector = (uint32_t)&uart0_irq; break;
- case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
+ case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
case UART_2: irq_n=USART2_IRQn; vector = (uint32_t)&uart2_irq; break;
case UART_3: irq_n=USART3_IRQn; vector = (uint32_t)&uart3_irq; break;
}
@@ -257,7 +318,7 @@
obj->uart->IER |= 1 << irq;
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
- } else { // disable
+ } else if ((TxIrq == irq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable
int all_disabled = 0;
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
obj->uart->IER &= ~(1 << irq);
@@ -267,17 +328,36 @@
}
}
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+ if (RxIrq == irq)
+ uart_data[obj->index].rx_irq_set_api = enable;
+ serial_irq_set_internal(obj, irq, enable);
+}
+
+#if (DEVICE_SERIAL_FC)
+static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
+ uart_data[obj->index].rx_irq_set_flow = enable;
+ serial_irq_set_internal(obj, RxIrq, enable);
+}
+#endif
+
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj) {
while (!serial_readable(obj));
- return obj->uart->RBR;
+ int data = obj->uart->RBR;
+ if (NC != uart_data[obj->index].sw_rts.pin) {
+ gpio_write(&uart_data[obj->index].sw_rts, 0);
+ obj->uart->IER |= 1 << RxIrq;
+ }
+ return data;
}
void serial_putc(serial_t *obj, int c) {
while (!serial_writable(obj));
obj->uart->THR = c;
+ uart_data[obj->index].count++;
}
int serial_readable(serial_t *obj) {
@@ -285,11 +365,21 @@
}
int serial_writable(serial_t *obj) {
- return obj->uart->LSR & 0x20;
+ int isWritable = 1;
+ if (NC != uart_data[obj->index].sw_cts.pin)
+ isWritable = (gpio_read(&uart_data[obj->index].sw_cts) == 0) && (obj->uart->LSR & 0x40); //If flow control: writable if CTS low + UART done
+ else {
+ if (obj->uart->LSR & 0x20)
+ uart_data[obj->index].count = 0;
+ else if (uart_data[obj->index].count >= 16)
+ isWritable = 0;
+ }
+ return isWritable;
}
void serial_clear(serial_t *obj) {
- obj->uart->FCR = 1 << 1 // rx FIFO reset
+ obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
+ | 1 << 1 // rx FIFO reset
| 1 << 2 // tx FIFO reset
| 0 << 6; // interrupt depth
}
@@ -306,3 +396,7 @@
obj->uart->LCR &= ~(1 << 6);
}
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
+#if (DEVICE_SERIAL_FC)
+#endif
+}
--- a/targets/hal/TARGET_NXP/TARGET_LPC43XX/spi_api.c Fri Jul 11 10:00:08 2014 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC43XX/spi_api.c Tue Jul 15 07:45:08 2014 +0100
@@ -24,27 +24,48 @@
#include "error.h"
static const PinMap PinMap_SPI_SCLK[] = {
- {P3_0 , SPI_0, (SCU_PINIO_FAST | 2)},
- {PF_4 , SPI_1, (SCU_PINIO_FAST | 2)},
- {NC , NC , 0}
+ {P1_19, SPI_1, (SCU_PINIO_FAST | 1)},
+ {P3_0, SPI_0, (SCU_PINIO_FAST | 4)},
+ {P3_3, SPI_0, (SCU_PINIO_FAST | 2)},
+ {PF_0, SPI_0, (SCU_PINIO_FAST | 0)},
+ {PF_4, SPI_1, (SCU_PINIO_FAST | 0)},
+ {NC, NC, 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
- {P1_2 , SPI_0, (SCU_PINIO_FAST | 2)},
- {P1_4 , SPI_1, (SCU_PINIO_FAST | 2)},
- {NC , NC , 0}
+ {P0_1, SPI_1, (SCU_PINIO_FAST | 1)},
+ {P1_2, SPI_0, (SCU_PINIO_FAST | 5)},
+ {P1_4, SPI_1, (SCU_PINIO_FAST | 5)},
+ {P3_7, SPI_0, (SCU_PINIO_FAST | 5)},
+ {P3_8, SPI_0, (SCU_PINIO_FAST | 2)},
+ {P9_2, SPI_0, (SCU_PINIO_FAST | 7)},
+ {PF_3, SPI_0, (SCU_PINIO_FAST | 2)},
+ {PF_7, SPI_1, (SCU_PINIO_FAST | 2)},
+ {NC, NC, 0}
};
static const PinMap PinMap_SPI_MISO[] = {
- {P1_1 , SPI_0, (SCU_PINIO_FAST | 2)},
- {P1_3 , SPI_1, (SCU_PINIO_FAST | 2)},
- {NC , NC , 0}
+ {P0_0, SPI_1, (SCU_PINIO_FAST | 1)},
+ {P1_1, SPI_0, (SCU_PINIO_FAST | 5)},
+ {P1_3, SPI_1, (SCU_PINIO_FAST | 5)},
+ {P3_6, SPI_0, (SCU_PINIO_FAST | 5)},
+ {P3_7, SPI_0, (SCU_PINIO_FAST | 2)},
+ {P9_1, SPI_0, (SCU_PINIO_FAST | 7)},
+ {PF_2, SPI_0, (SCU_PINIO_FAST | 2)},
+ {PF_6, SPI_1, (SCU_PINIO_FAST | 2)},
+ {NC, NC, 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
- {P1_0 , SPI_0, (SCU_PINIO_FAST | 2)},
- {P1_5 , SPI_1, (SCU_PINIO_FAST | 2)},
- {NC , NC , 0}
+ {P1_0, SPI_0, (SCU_PINIO_FAST | 5)},
+ {P1_5, SPI_1, (SCU_PINIO_FAST | 5)},
+ {P1_20, SPI_1, (SCU_PINIO_FAST | 2)},
+ {P3_6, SPI_0, (SCU_PINIO_FAST | 2)},
+ {P3_8, SPI_0, (SCU_PINIO_FAST | 5)},
+ {P9_0, SPI_0, (SCU_PINIO_FAST | 7)},
+ {PF_1, SPI_0, (SCU_PINIO_FAST | 2)},
+ {PF_5, SPI_1, (SCU_PINIO_FAST | 2)},
+ {NC, NC, 0}
};
static inline int ssp_disable(spi_t *obj);