lpc17xx_uart.h

00001 /***********************************************************************//**
00002  * @file    : lpc17xx_uart.h
00003  * @brief    : Contains all macro definitions and function prototypes
00004  *                 support for UART firmware library on LPC17xx
00005  * @version    : 1.0
00006  * @date    : 18. Mar. 2009
00007  * @author    : HieuNguyen
00008  **************************************************************************
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * products. This software is supplied "AS IS" without any warranties.
00012  * NXP Semiconductors assumes no responsibility or liability for the
00013  * use of the software, conveys no license or title under any patent,
00014  * copyright, or mask work right to the product. NXP Semiconductors
00015  * reserves the right to make changes in the software without
00016  * notification. NXP Semiconductors also make no representation or
00017  * warranty that such application will be suitable for the specified
00018  * use without further testing or modification.
00019  **************************************************************************/
00020 
00021 /* Peripheral group ----------------------------------------------------------- */
00022 /** @defgroup UART
00023  * @ingroup LPC1700CMSIS_FwLib_Drivers
00024  * @{
00025  */
00026 
00027 #ifndef __LPC17XX_UART_H
00028 #define __LPC17XX_UART_H
00029 
00030 /* Includes ------------------------------------------------------------------- */
00031 #include "cmsis.h"
00032 #include "lpc_types.h"
00033 
00034 
00035 #ifdef __cplusplus
00036 extern "C"
00037 {
00038 #endif
00039 
00040 
00041 /* Private Macros ------------------------------------------------------------- */
00042 /** @defgroup UART_Private_Macros
00043  * @{
00044  */
00045 
00046 
00047 /** @defgroup UART_REGISTER_BIT_DEFINITIONS
00048  * @{
00049  */
00050 
00051 /* Accepted Error baud rate value (in percent unit) */
00052 #define UART_ACCEPTED_BAUDRATE_ERROR    (3)            /*!< Acceptable UART baudrate error */
00053 
00054 /* Macro defines for UARTn Receiver Buffer Register */
00055 #define UART_RBR_MASKBIT       ((uint8_t)0xFF)         /*!< UART Received Buffer mask bit (8 bits) */
00056 
00057 /* Macro defines for UARTn Transmit Holding Register */
00058 #define UART_THR_MASKBIT       ((uint8_t)0xFF)         /*!< UART Transmit Holding mask bit (8 bits) */
00059 
00060 /* Macro defines for UARTn Divisor Latch LSB register */
00061 #define UART_LOAD_DLL(div)    ((div) & 0xFF)    /**< Macro for loading least significant halfs of divisors */
00062 #define UART_DLL_MASKBIT    ((uint8_t)0xFF)    /*!< Divisor latch LSB bit mask */
00063 
00064 /* Macro defines for UARTn Divisor Latch MSB register */
00065 #define UART_DLM_MASKBIT    ((uint8_t)0xFF)            /*!< Divisor latch MSB bit mask */
00066 #define UART_LOAD_DLM(div)  (((div) >> 8) & 0xFF)    /**< Macro for loading most significant halfs of divisors */
00067 
00068 
00069 /* Macro defines for UART interrupt enable register */
00070 #define UART_IER_RBRINT_EN        ((uint32_t)(1<<0))     /*!< RBR Interrupt enable*/
00071 #define UART_IER_THREINT_EN        ((uint32_t)(1<<1))     /*!< THR Interrupt enable*/
00072 #define UART_IER_RLSINT_EN        ((uint32_t)(1<<2))     /*!< RX line status interrupt enable*/
00073 #define UART1_IER_MSINT_EN        ((uint32_t)(1<<3))    /*!< Modem status interrupt enable */
00074 #define UART1_IER_CTSINT_EN        ((uint32_t)(1<<7))    /*!< CTS1 signal transition interrupt enable */
00075 #define UART_IER_ABEOINT_EN        ((uint32_t)(1<<8))     /*!< Enables the end of auto-baud interrupt */
00076 #define UART_IER_ABTOINT_EN        ((uint32_t)(1<<9))     /*!< Enables the auto-baud time-out interrupt */
00077 #define UART_IER_BITMASK        ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */
00078 #define UART1_IER_BITMASK        ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */
00079 
00080 
00081 /* UART interrupt identification register defines */
00082 #define UART_IIR_INTSTAT_PEND    ((uint32_t)(1<<0))    /*!<Interrupt Status - Active low */
00083 #define UART_IIR_INTID_RLS        ((uint32_t)(3<<1))     /*!<Interrupt identification: Receive line status*/
00084 #define UART_IIR_INTID_RDA        ((uint32_t)(2<<1))     /*!<Interrupt identification: Receive data available*/
00085 #define UART_IIR_INTID_CTI        ((uint32_t)(6<<1))     /*!<Interrupt identification: Character time-out indicator*/
00086 #define UART_IIR_INTID_THRE        ((uint32_t)(1<<1))     /*!<Interrupt identification: THRE interrupt*/
00087 #define UART1_IIR_INTID_MODEM    ((uint32_t)(0<<1))     /*!<Interrupt identification: Modem interrupt*/
00088 #define UART_IIR_INTID_MASK        ((uint32_t)(7<<1))    /*!<Interrupt identification: Interrupt ID mask */
00089 #define UART_IIR_FIFO_EN        ((uint32_t)(3<<6))     /*!<These bits are equivalent to UnFCR[0] */
00090 #define UART_IIR_ABEO_INT        ((uint32_t)(1<<8))     /*!< End of auto-baud interrupt */
00091 #define UART_IIR_ABTO_INT        ((uint32_t)(1<<9))     /*!< Auto-baud time-out interrupt */
00092 #define UART_IIR_BITMASK        ((uint32_t)(0x3CF))    /*!< UART interrupt identification register bit mask */
00093 
00094 
00095 /* Macro defines for UART FIFO control register */
00096 #define UART_FCR_FIFO_EN        ((uint8_t)(1<<0))     /*!< UART FIFO enable */
00097 #define UART_FCR_RX_RS            ((uint8_t)(1<<1))     /*!< UART FIFO RX reset */
00098 #define UART_FCR_TX_RS            ((uint8_t)(1<<2))     /*!< UART FIFO TX reset */
00099 #define UART_FCR_DMAMODE_SEL     ((uint8_t)(1<<3))     /*!< UART DMA mode selection */
00100 #define UART_FCR_TRG_LEV0        ((uint8_t)(0))         /*!< UART FIFO trigger level 0: 1 character */
00101 #define UART_FCR_TRG_LEV1        ((uint8_t)(1<<6))     /*!< UART FIFO trigger level 1: 4 character */
00102 #define UART_FCR_TRG_LEV2        ((uint8_t)(2<<6))     /*!< UART FIFO trigger level 2: 8 character */
00103 #define UART_FCR_TRG_LEV3        ((uint8_t)(3<<6))     /*!< UART FIFO trigger level 3: 14 character */
00104 #define UART_FCR_BITMASK        ((uint8_t)(0xCF))    /*!< UART FIFO control bit mask */
00105 #define UART_TX_FIFO_SIZE        (16)
00106 
00107 /* Macro defines for UART line control register */
00108 #define UART_LCR_WLEN5             ((uint8_t)(0))           /*!< UART 5 bit data mode */
00109 #define UART_LCR_WLEN6             ((uint8_t)(1<<0))       /*!< UART 6 bit data mode */
00110 #define UART_LCR_WLEN7             ((uint8_t)(2<<0))       /*!< UART 7 bit data mode */
00111 #define UART_LCR_WLEN8             ((uint8_t)(3<<0))       /*!< UART 8 bit data mode */
00112 #define UART_LCR_STOPBIT_SEL    ((uint8_t)(1<<2))       /*!< UART Two Stop Bits Select */
00113 #define UART_LCR_PARITY_EN        ((uint8_t)(1<<3))        /*!< UART Parity Enable */
00114 #define UART_LCR_PARITY_ODD        ((uint8_t)(0))             /*!< UART Odd Parity Select */
00115 #define UART_LCR_PARITY_EVEN    ((uint8_t)(1<<4))        /*!< UART Even Parity Select */
00116 #define UART_LCR_PARITY_F_1        ((uint8_t)(2<<4))        /*!< UART force 1 stick parity */
00117 #define UART_LCR_PARITY_F_0        ((uint8_t)(3<<4))        /*!< UART force 0 stick parity */
00118 #define UART_LCR_BREAK_EN        ((uint8_t)(1<<6))        /*!< UART Transmission Break enable */
00119 #define UART_LCR_DLAB_EN        ((uint8_t)(1<<7))        /*!< UART Divisor Latches Access bit enable */
00120 #define UART_LCR_BITMASK        ((uint8_t)(0xFF))        /*!< UART line control bit mask */
00121 
00122 
00123 /* Macro defines for UART1 Modem Control Register */
00124 #define UART1_MCR_DTR_CTRL        ((uint8_t)(1<<0))        /*!< Source for modem output pin DTR */
00125 #define UART1_MCR_RTS_CTRL        ((uint8_t)(1<<1))        /*!< Source for modem output pin RTS */
00126 #define UART1_MCR_LOOPB_EN        ((uint8_t)(1<<4))        /*!< Loop back mode select */
00127 #define UART1_MCR_AUTO_RTS_EN    ((uint8_t)(1<<6))        /*!< Enable Auto RTS flow-control */
00128 #define UART1_MCR_AUTO_CTS_EN    ((uint8_t)(1<<7))        /*!< Enable Auto CTS flow-control */
00129 #define UART1_MCR_BITMASK        ((uint8_t)(0x0F3))        /*!< UART1 bit mask value */
00130 
00131 
00132 /* Macro defines for UART line status register */
00133 #define UART_LSR_RDR        ((uint8_t)(1<<0))     /*!<Line status register: Receive data ready*/
00134 #define UART_LSR_OE            ((uint8_t)(1<<1))     /*!<Line status register: Overrun error*/
00135 #define UART_LSR_PE            ((uint8_t)(1<<2))     /*!<Line status register: Parity error*/
00136 #define UART_LSR_FE            ((uint8_t)(1<<3))     /*!<Line status register: Framing error*/
00137 #define UART_LSR_BI            ((uint8_t)(1<<4))     /*!<Line status register: Break interrupt*/
00138 #define UART_LSR_THRE        ((uint8_t)(1<<5))     /*!<Line status register: Transmit holding register empty*/
00139 #define UART_LSR_TEMT        ((uint8_t)(1<<6))     /*!<Line status register: Transmitter empty*/
00140 #define UART_LSR_RXFE        ((uint8_t)(1<<7))     /*!<Error in RX FIFO*/
00141 #define UART_LSR_BITMASK    ((uint8_t)(0xFF))     /*!<UART Line status bit mask */
00142 
00143 
00144 /* Macro defines for UART Modem (UART1 only) status register */
00145 #define UART1_MSR_DELTA_CTS        ((uint8_t)(1<<0))    /*!< Set upon state change of input CTS */
00146 #define UART1_MSR_DELTA_DSR        ((uint8_t)(1<<1))    /*!< Set upon state change of input DSR */
00147 #define UART1_MSR_LO2HI_RI        ((uint8_t)(1<<2))    /*!< Set upon low to high transition of input RI */
00148 #define UART1_MSR_DELTA_DCD        ((uint8_t)(1<<3))    /*!< Set upon state change of input DCD */
00149 #define UART1_MSR_CTS            ((uint8_t)(1<<4))    /*!< Clear To Send State */
00150 #define UART1_MSR_DSR            ((uint8_t)(1<<5))    /*!< Data Set Ready State */
00151 #define UART1_MSR_RI            ((uint8_t)(1<<6))    /*!< Ring Indicator State */
00152 #define UART1_MSR_DCD            ((uint8_t)(1<<7))    /*!< Data Carrier Detect State */
00153 #define UART1_MSR_BITMASK        ((uint8_t)(0xFF))    /*!< MSR register bit-mask value */
00154 
00155 
00156 /* Macro defines for UART Scratch Pad Register */
00157 #define UART_SCR_BIMASK        ((uint8_t)(0xFF))    /*!< UART Scratch Pad bit mask */
00158 
00159 /* Macro defines for UART Auto baudrate control register */
00160 #define UART_ACR_START                ((uint32_t)(1<<0))    /**< UART Auto-baud start */
00161 #define UART_ACR_MODE                ((uint32_t)(1<<1))    /**< UART Auto baudrate Mode 1 */
00162 #define UART_ACR_AUTO_RESTART        ((uint32_t)(1<<2))    /**< UART Auto baudrate restart */
00163 #define UART_ACR_ABEOINT_CLR        ((uint32_t)(1<<8))    /**< UART End of auto-baud interrupt clear */
00164 #define UART_ACR_ABTOINT_CLR        ((uint32_t)(1<<9))    /**< UART Auto-baud time-out interrupt clear */
00165 #define UART_ACR_BITMASK            ((uint32_t)(0x307))    /**< UART Auto Baudrate register bit mask */
00166 
00167 /* UART IrDA control register defines */
00168 #define UART_ICR_IRDAEN            ((uint32_t)(1<<0))            /**< IrDA mode enable */
00169 #define UART_ICR_IRDAINV        ((uint32_t)(1<<1))            /**< IrDA serial input inverted */
00170 #define UART_ICR_FIXPULSE_EN    ((uint32_t)(1<<2))            /**< IrDA fixed pulse width mode */
00171 #define UART_ICR_PULSEDIV(n)    ((uint32_t)((n&0x07)<<3))    /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */
00172 #define UART_ICR_BITMASK        ((uint32_t)(0x3F))            /*!< UART IRDA bit mask */
00173 
00174 /* Macro defines for UART Fractional divider register */
00175 #define UART_FDR_DIVADDVAL(n)    ((uint32_t)(n&0x0F))        /**< Baud-rate generation pre-scaler divisor */
00176 #define UART_FDR_MULVAL(n)        ((uint32_t)((n<<4)&0xF0))    /**< Baud-rate pre-scaler multiplier value */
00177 #define UART_FDR_BITMASK        ((uint32_t)(0xFF))            /**< UART Fractional Divider register bit mask */
00178 
00179 /* Macro defines for UART Tx Enable register */
00180 #define UART_TER_TXEN            ((uint8_t)(1<<7))         /*!< Transmit enable bit */
00181 #define UART_TER_BITMASK        ((uint8_t)(0x80))        /**< UART Transmit Enable Register bit mask */
00182 
00183 
00184 /* Macro defines for UART1 RS485 Control register */
00185 #define UART1_RS485CTRL_NMM_EN        ((uint32_t)(1<<0))    /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM)
00186                                                         is disabled */
00187 #define UART1_RS485CTRL_RX_DIS        ((uint32_t)(1<<1))    /*!< The receiver is disabled */
00188 #define UART1_RS485CTRL_AADEN        ((uint32_t)(1<<2))    /*!< Auto Address Detect (AAD) is enabled */
00189 #define UART1_RS485CTRL_SEL_DTR        ((uint32_t)(1<<3))    /*!< If direction control is enabled
00190                                                         (bit DCTRL = 1), pin DTR is used for direction control */
00191 #define UART1_RS485CTRL_DCTRL_EN    ((uint32_t)(1<<4))    /*!< Enable Auto Direction Control */
00192 #define UART1_RS485CTRL_OINV_1        ((uint32_t)(1<<5))    /*!< This bit reverses the polarity of the direction
00193                                                         control signal on the RTS (or DTR) pin. The direction control pin
00194                                                         will be driven to logic "1" when the transmitter has data to be sent */
00195 #define UART1_RS485CTRL_BITMASK        ((uint32_t)(0x3F))    /**< RS485 control bit-mask value */
00196 
00197 
00198 /* Macro defines for UART1 RS-485 Address Match register */
00199 #define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF))     /**< Bit mask value */
00200 
00201 /* Macro defines for UART1 RS-485 Delay value register */
00202 #define UART1_RS485DLY_BITMASK        ((uint8_t)(0xFF))     /** Bit mask value */
00203 
00204 
00205 /* Macro defines for UART FIFO Level register */
00206 #define UART_FIFOLVL_RXFIFOLVL(n)    ((uint32_t)(n&0x0F))        /**< Reflects the current level of the UART receiver FIFO */
00207 #define UART_FIFOLVL_TXFIFOLVL(n)    ((uint32_t)((n>>8)&0x0F))    /**< Reflects the current level of the UART transmitter FIFO */
00208 #define UART_FIFOLVL_BITMASK        ((uint32_t)(0x0F0F))        /**< UART FIFO Level Register bit mask */
00209 
00210 /**
00211  * @}
00212  */
00213 
00214 /**
00215  * @}
00216  */
00217 
00218 
00219 /* Public Types --------------------------------------------------------------- */
00220 /** @defgroup UART_Public_Types
00221  * @{
00222  */
00223 
00224 
00225 /**
00226  * @brief UART Databit type definitions
00227  */
00228 typedef enum {
00229     UART_DATABIT_5         = 0,             /*!< UART 5 bit data mode */
00230     UART_DATABIT_6 ,                         /*!< UART 6 bit data mode */
00231     UART_DATABIT_7 ,                         /*!< UART 7 bit data mode */
00232     UART_DATABIT_8                          /*!< UART 8 bit data mode */
00233 } UART_DATABIT_Type;
00234 
00235 /** Macro to check the input UART_DATABIT parameters */
00236 #define PARAM_UART_DATABIT(databit)    ((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\
00237 || (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8))
00238 
00239 /**
00240  * @brief UART Stop bit type definitions
00241  */
00242 typedef enum {
00243     UART_STOPBIT_1         = (0),                       /*!< UART 1 Stop Bits Select */
00244     UART_STOPBIT_2 ,                                     /*!< UART Two Stop Bits Select */
00245 } UART_STOPBIT_Type;
00246 
00247 /** Macro to check the input UART_STOPBIT parameters */
00248 #define PARAM_UART_STOPBIT(stopbit)    ((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2))
00249 
00250 /**
00251  * @brief UART Parity type definitions
00252  */
00253 typedef enum {
00254     UART_PARITY_NONE      = 0,                    /*!< No parity */
00255     UART_PARITY_ODD ,                             /*!< Odd parity */
00256     UART_PARITY_EVEN ,                             /*!< Even parity */
00257     UART_PARITY_SP_1 ,                             /*!< Forced "1" stick parity */
00258     UART_PARITY_SP_0                              /*!< Forced "0" stick parity */
00259 } UART_PARITY_Type;
00260 
00261 /** Macro to check the input UART_PARITY parameters */
00262 #define PARAM_UART_PARITY(parity)    ((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \
00263 || (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \
00264 || (parity==UART_PARITY_SP_0))
00265 
00266 /**
00267  * @brief FIFO Level type definitions
00268  */
00269 typedef enum {
00270     UART_FIFO_TRGLEV0  = 0,    /*!< UART FIFO trigger level 0: 1 character */
00271     UART_FIFO_TRGLEV1 ,         /*!< UART FIFO trigger level 1: 4 character */
00272     UART_FIFO_TRGLEV2 ,        /*!< UART FIFO trigger level 2: 8 character */
00273     UART_FIFO_TRGLEV3         /*!< UART FIFO trigger level 3: 14 character */
00274 } UART_FITO_LEVEL_Type;
00275 
00276 /** Macro to check the input UART_FIFO parameters */
00277 #define PARAM_UART_FIFO_LEVEL(fifo)    ((fifo==UART_FIFO_TRGLEV0) \
00278 || (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \
00279 || (fifo==UART_FIFO_TRGLEV3))
00280 
00281 /********************************************************************//**
00282 * @brief UART Interrupt Type definitions
00283 **********************************************************************/
00284 typedef enum {
00285     UART_INTCFG_RBR  = 0,    /*!< RBR Interrupt enable*/
00286     UART_INTCFG_THRE ,        /*!< THR Interrupt enable*/
00287     UART_INTCFG_RLS ,        /*!< RX line status interrupt enable*/
00288     UART1_INTCFG_MS ,        /*!< Modem status interrupt enable (UART1 only) */
00289     UART1_INTCFG_CTS ,        /*!< CTS1 signal transition interrupt enable (UART1 only) */
00290     UART_INTCFG_ABEO ,        /*!< Enables the end of auto-baud interrupt */
00291     UART_INTCFG_ABTO         /*!< Enables the auto-baud time-out interrupt */
00292 } UART_INT_Type;
00293 
00294 /** Macro to check the input UART_INTCFG parameters */
00295 #define PARAM_UART_INTCFG(IntCfg)    ((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \
00296 || (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \
00297 || (IntCfg==UART_INTCFG_ABTO))
00298 
00299 /** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */
00300 #define PARAM_UART1_INTCFG(IntCfg)    ((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS))
00301 
00302 
00303 /**
00304  * @brief UART Line Status Type definition
00305  */
00306 typedef enum {
00307     UART_LINESTAT_RDR     = UART_LSR_RDR,            /*!<Line status register: Receive data ready*/
00308     UART_LINESTAT_OE     = UART_LSR_OE,            /*!<Line status register: Overrun error*/
00309     UART_LINESTAT_PE     = UART_LSR_PE,            /*!<Line status register: Parity error*/
00310     UART_LINESTAT_FE     = UART_LSR_FE,            /*!<Line status register: Framing error*/
00311     UART_LINESTAT_BI     = UART_LSR_BI,            /*!<Line status register: Break interrupt*/
00312     UART_LINESTAT_THRE     = UART_LSR_THRE,        /*!<Line status register: Transmit holding register empty*/
00313     UART_LINESTAT_TEMT     = UART_LSR_TEMT,        /*!<Line status register: Transmitter empty*/
00314     UART_LINESTAT_RXFE     = UART_LSR_RXFE            /*!<Error in RX FIFO*/
00315 } UART_LS_Type;
00316 
00317 
00318 /**
00319  * @brief UART Auto-baudrate mode type definition
00320  */
00321 typedef enum {
00322     UART_AUTOBAUD_MODE0                = 0,            /**< UART Auto baudrate Mode 0 */
00323     UART_AUTOBAUD_MODE1,                            /**< UART Auto baudrate Mode 1 */
00324 } UART_AB_MODE_Type;
00325 
00326 /** Macro to check the input UART_AUTOBAUD_MODE parameters */
00327 #define PARAM_UART_AUTOBAUD_MODE(ABmode)    ((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1))
00328 
00329 /**
00330  * @brief Auto Baudrate mode configuration type definition
00331  */
00332 typedef struct {
00333     UART_AB_MODE_Type    ABMode;            /**< Autobaudrate mode */
00334     FunctionalState        AutoRestart;    /**< Auto Restart state */
00335 } UART_AB_CFG_Type;
00336 
00337 
00338 /**
00339  * @brief UART End of Auto-baudrate type definition
00340  */
00341 typedef enum {
00342     UART_AUTOBAUD_INTSTAT_ABEO        = UART_IIR_ABEO_INT,        /**< UART End of auto-baud interrupt  */
00343     UART_AUTOBAUD_INTSTAT_ABTO        = UART_IIR_ABTO_INT            /**< UART Auto-baud time-out interrupt  */
00344 }UART_ABEO_Type;
00345 
00346 /** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */
00347 #define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat)    ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || (ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO))
00348 
00349 /**
00350  * UART IrDA Control type Definition
00351  */
00352 typedef enum {
00353     UART_IrDA_PULSEDIV2        = 0,        /**< Pulse width = 2 * Tpclk
00354                                         - Configures the pulse when FixPulseEn = 1 */
00355     UART_IrDA_PULSEDIV4,                /**< Pulse width = 4 * Tpclk
00356                                         - Configures the pulse when FixPulseEn = 1 */
00357     UART_IrDA_PULSEDIV8,                /**< Pulse width = 8 * Tpclk
00358                                         - Configures the pulse when FixPulseEn = 1 */
00359     UART_IrDA_PULSEDIV16,                /**< Pulse width = 16 * Tpclk
00360                                         - Configures the pulse when FixPulseEn = 1 */
00361     UART_IrDA_PULSEDIV32,                /**< Pulse width = 32 * Tpclk
00362                                         - Configures the pulse when FixPulseEn = 1 */
00363     UART_IrDA_PULSEDIV64,                /**< Pulse width = 64 * Tpclk
00364                                         - Configures the pulse when FixPulseEn = 1 */
00365     UART_IrDA_PULSEDIV128,                /**< Pulse width = 128 * Tpclk
00366                                         - Configures the pulse when FixPulseEn = 1 */
00367     UART_IrDA_PULSEDIV256                /**< Pulse width = 256 * Tpclk
00368                                         - Configures the pulse when FixPulseEn = 1 */
00369 } UART_IrDA_PULSE_Type;
00370 
00371 
00372 /** Macro to check the input UART_IrDA_PULSEDIV parameters */
00373 #define PARAM_UART_IrDA_PULSEDIV(PulseDiv)    ((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \
00374 || (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \
00375 || (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \
00376 || (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256))
00377 
00378 /********************************************************************//**
00379 * @brief UART1 Full modem -  Signal states definition
00380 **********************************************************************/
00381 typedef enum {
00382     INACTIVE = 0,            /* In-active state */
00383     ACTIVE = !INACTIVE         /* Active state */
00384 }UART1_SignalState;
00385 
00386 /* Macro to check the input UART1_SignalState parameters */
00387 #define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE))
00388 
00389 /**
00390  * @brief UART modem status type definition
00391  */
00392 typedef enum {
00393     UART1_MODEM_STAT_DELTA_CTS     = UART1_MSR_DELTA_CTS,        /*!< Set upon state change of input CTS */
00394     UART1_MODEM_STAT_DELTA_DSR     = UART1_MSR_DELTA_DSR,        /*!< Set upon state change of input DSR */
00395     UART1_MODEM_STAT_LO2HI_RI     = UART1_MSR_LO2HI_RI,        /*!< Set upon low to high transition of input RI */
00396     UART1_MODEM_STAT_DELTA_DCD     = UART1_MSR_DELTA_DCD,        /*!< Set upon state change of input DCD */
00397     UART1_MODEM_STAT_CTS         = UART1_MSR_CTS,            /*!< Clear To Send State */
00398     UART1_MODEM_STAT_DSR         = UART1_MSR_DSR,            /*!< Data Set Ready State */
00399     UART1_MODEM_STAT_RI             = UART1_MSR_RI,                /*!< Ring Indicator State */
00400     UART1_MODEM_STAT_DCD         = UART1_MSR_DCD                /*!< Data Carrier Detect State */
00401 } UART_MODEM_STAT_type;
00402 
00403 /**
00404  * @brief Modem output pin type definition
00405  */
00406 typedef enum {
00407     UART1_MODEM_PIN_DTR             = 0,        /*!< Source for modem output pin DTR */
00408     UART1_MODEM_PIN_RTS                         /*!< Source for modem output pin RTS */
00409 } UART_MODEM_PIN_Type;
00410 
00411 /** Macro to check the input PARAM_UART1_MODEM_PIN parameters */
00412 #define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS))
00413 
00414 
00415 /**
00416  * @brief UART Modem mode type definition
00417  */
00418 typedef enum {
00419     UART1_MODEM_MODE_LOOPBACK     = 0,        /*!< Loop back mode select */
00420     UART1_MODEM_MODE_AUTO_RTS ,                /*!< Enable Auto RTS flow-control */
00421     UART1_MODEM_MODE_AUTO_CTS                  /*!< Enable Auto CTS flow-control */
00422 } UART_MODEM_MODE_Type;
00423 
00424 /** Macro to check the input PARAM_UART1_MODEM_MODE parameters */
00425 #define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \
00426 || (x==UART1_MODEM_MODE_AUTO_CTS))
00427 
00428 
00429 /**
00430  * @brief UART Direction Control Pin type definition
00431  */
00432 typedef enum {
00433     UART1_RS485_DIRCTRL_RTS = 0,    /**< Pin RTS is used for direction control */
00434     UART1_RS485_DIRCTRL_DTR            /**< Pin DTR is used for direction control */
00435 } UART_RS485_DIRCTRL_PIN_Type;
00436 
00437 /** Macro to check the direction control pin type */
00438 #define PARAM_UART_RS485_DIRCTRL_PIN(x)    ((x==UART1_RS485_DIRCTRL_RTS) || (x==UART1_RS485_DIRCTRL_DTR))
00439 
00440 
00441 /********************************************************************//**
00442 * @brief UART Configuration Structure definition
00443 **********************************************************************/
00444 typedef struct {
00445   uint32_t Baud_rate;           /**< UART baud rate */
00446   UART_PARITY_Type Parity;        /**< Parity selection, should be:
00447                                - UART_PARITY_NONE: No parity
00448                                - UART_PARITY_ODD: Odd parity
00449                                - UART_PARITY_EVEN: Even parity
00450                                - UART_PARITY_SP_1: Forced "1" stick parity
00451                                - UART_PARITY_SP_0: Forced "0" stick parity
00452                                */
00453   UART_DATABIT_Type Databits;   /**< Number of data bits, should be:
00454                                - UART_DATABIT_5: UART 5 bit data mode
00455                                - UART_DATABIT_6: UART 6 bit data mode
00456                                - UART_DATABIT_7: UART 7 bit data mode
00457                                - UART_DATABIT_8: UART 8 bit data mode
00458                                */
00459   UART_STOPBIT_Type Stopbits;   /**< Number of stop bits, should be:
00460                                - UART_STOPBIT_1: UART 1 Stop Bits Select
00461                                - UART_STOPBIT_2: UART 2 Stop Bits Select
00462                                */
00463 } UART_CFG_Type;
00464 
00465 /********************************************************************//**
00466 * @brief UART FIFO Configuration Structure definition
00467 **********************************************************************/
00468 
00469 typedef struct {
00470     FunctionalState FIFO_ResetRxBuf;    /**< Reset Rx FIFO command state , should be:
00471                                          - ENABLE: Reset Rx FIFO in UART
00472                                          - DISABLE: Do not reset Rx FIFO  in UART
00473                                          */
00474     FunctionalState FIFO_ResetTxBuf;    /**< Reset Tx FIFO command state , should be:
00475                                          - ENABLE: Reset Tx FIFO in UART
00476                                          - DISABLE: Do not reset Tx FIFO  in UART
00477                                          */
00478     FunctionalState FIFO_DMAMode;        /**< DMA mode, should be:
00479                                          - ENABLE: Enable DMA mode in UART
00480                                          - DISABLE: Disable DMA mode in UART
00481                                          */
00482     UART_FITO_LEVEL_Type FIFO_Level;    /**< Rx FIFO trigger level, should be:
00483                                         - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
00484                                         - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
00485                                         - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
00486                                         - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
00487                                         */
00488 } UART_FIFO_CFG_Type;
00489 
00490 
00491 /********************************************************************//**
00492 * @brief UART1 Full modem -  RS485 Control configuration type
00493 **********************************************************************/
00494 typedef struct {
00495     FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
00496                                                     - ENABLE: Enable this function.
00497                                                     - DISABLE: Disable this function. */
00498     FunctionalState Rx_State;                    /*!< Receiver State:
00499                                                     - ENABLE: Enable Receiver.
00500                                                     - DISABLE: Disable Receiver. */
00501     FunctionalState AutoAddrDetect_State;        /*!< Auto Address Detect mode state:
00502                                                 - ENABLE: ENABLE this function.
00503                                                 - DISABLE: Disable this function. */
00504     FunctionalState AutoDirCtrl_State;            /*!< Auto Direction Control State:
00505                                                 - ENABLE: Enable this function.
00506                                                 - DISABLE: Disable this function. */
00507     UART_RS485_DIRCTRL_PIN_Type DirCtrlPin;        /*!< If direction control is enabled, state:
00508                                                 - UART1_RS485_DIRCTRL_RTS:
00509                                                 pin RTS is used for direction control.
00510                                                 - UART1_RS485_DIRCTRL_DTR:
00511                                                 pin DTR is used for direction control. */
00512      SetState DirCtrlPol_Level;                    /*!< Polarity of the direction control signal on
00513                                                 the RTS (or DTR) pin:
00514                                                 - RESET: The direction control pin will be driven
00515                                                 to logic "0" when the transmitter has data to be sent.
00516                                                 - SET: The direction control pin will be driven
00517                                                 to logic "1" when the transmitter has data to be sent. */
00518     uint8_t MatchAddrValue ;                    /*!< address match value for RS-485/EIA-485 mode, 8-bit long */
00519     uint8_t DelayValue ;                        /*!< delay time is in periods of the baud clock, 8-bit long */
00520 } UART1_RS485_CTRLCFG_Type;
00521 
00522 
00523 /* UART call-back function type definitions */
00524 /** UART Receive Call-back function type */
00525 typedef void (fnRxCbs_Type)(void);
00526 /** UART Transmit Call-back function type */
00527 typedef void (fnTxCbs_Type)(void);
00528 /** UART Auto-Baudrate Call-back function type */
00529 typedef void (fnABCbs_Type)(uint32_t bABIntType);
00530 /** UART Error Call-back function type */
00531 typedef void (fnErrCbs_Type)(uint8_t bError);
00532 /** UART1 modem status interrupt callback type */
00533 typedef void (fnModemCbs_Type)(uint8_t ModemStatus);
00534 
00535 
00536 /**
00537  * @}
00538  */
00539 
00540 
00541 /* Public Macros -------------------------------------------------------------- */
00542 /** @defgroup UART_Public_Macros
00543  * @{
00544  */
00545 
00546 
00547 /* Macro to determine if it is valid UART port number */
00548 #define PARAM_UARTx(x)    ((((uint32_t *)x)==((uint32_t *)LPC_UART0)) \
00549 || (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \
00550 || (((uint32_t *)x)==((uint32_t *)LPC_UART2)) \
00551 || (((uint32_t *)x)==((uint32_t *)LPC_UART3)))
00552 #define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_UART3))
00553 #define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1))
00554 
00555 
00556 /** Macro to check the input value for UART1_RS485_CFG_MATCHADDRVALUE parameter */
00557 #define PARAM_UART1_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF))
00558 
00559 /** Macro to check the input value for UART1_RS485_CFG_DELAYVALUE parameter */
00560 #define PARAM_UART1_RS485_CFG_DELAYVALUE(x) ((x<0xFF))
00561 
00562 
00563 /** UART time-out definitions in case of using Read() and Write function
00564  * with Blocking Flag mode
00565  */
00566 
00567 #define UART_BLOCKING_TIMEOUT            (0xFFFFFFFFUL)
00568 
00569 /**
00570  * @}
00571  */
00572 
00573 
00574 /* Public Functions ----------------------------------------------------------- */
00575 /** @defgroup UART_Public_Functions
00576  * @{
00577  */
00578 
00579 void UART_DeInit(LPC_UART_TypeDef* UARTx);
00580 void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct);
00581 void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
00582 void UART_SendData(LPC_UART_TypeDef* UARTx, uint8_t Data);
00583 uint8_t UART_ReceiveData(LPC_UART_TypeDef* UARTx);
00584 void UART_ForceBreak(LPC_UART_TypeDef* UARTx);
00585 void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
00586 void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
00587 void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv);
00588 void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \
00589                 FunctionalState NewState);
00590 uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx);
00591 FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx);
00592 void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg);
00593 void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
00594 void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
00595                 FunctionalState NewState);
00596 void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState);
00597 void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \
00598                             UART1_SignalState NewState);
00599 void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \
00600                             FunctionalState NewState);
00601 uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx);
00602 void UART_RS485Config(LPC_UART1_TypeDef *UARTx, \
00603         UART1_RS485_CTRLCFG_Type *RS485ConfigStruct);
00604 void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState);
00605 void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr);
00606 uint32_t UART_RS485SendData(LPC_UART1_TypeDef *UARTx, uint8_t *pData, uint32_t size);
00607 uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf,
00608         uint32_t buflen, TRANSFER_BLOCK_Type flag);
00609 uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \
00610         uint32_t buflen, TRANSFER_BLOCK_Type flag);
00611 void UART_SetupCbs(LPC_UART_TypeDef *UARTx, uint8_t CbType, void *pfnCbs);
00612 void UART0_StdIntHandler(void);
00613 void UART1_StdIntHandler(void);
00614 void UART2_StdIntHandler(void);
00615 void UART3_StdIntHandler(void);
00616 
00617 /**
00618  * @}
00619  */
00620 
00621 
00622 #ifdef __cplusplus
00623 }
00624 #endif
00625 
00626 
00627 #endif /* __LPC17XX_UART_H */
00628 
00629 /**
00630  * @}
00631  */
00632 
00633 /* --------------------------------- End Of File ------------------------------ */