lpc17xx_mcpwm.h

00001 /***********************************************************************//**
00002  * @file    : lpc17xx_mcpwm.h
00003  * @brief    : Contains all macro definitions and function prototypes
00004  *                 support for Motor Control PWM firmware library on LPC17xx
00005  * @version    : 1.0
00006  * @date    : 28. May. 2009
00007  * @author    : HieuNguyen
00008  **************************************************************************
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * products. This software is supplied "AS IS" without any warranties.
00012  * NXP Semiconductors assumes no responsibility or liability for the
00013  * use of the software, conveys no license or title under any patent,
00014  * copyright, or mask work right to the product. NXP Semiconductors
00015  * reserves the right to make changes in the software without
00016  * notification. NXP Semiconductors also make no representation or
00017  * warranty that such application will be suitable for the specified
00018  * use without further testing or modification.
00019  **************************************************************************/
00020 
00021 /* Peripheral group ----------------------------------------------------------- */
00022 /** @defgroup MCPWM
00023  * @ingroup LPC1700CMSIS_FwLib_Drivers
00024  * @{
00025  */
00026 
00027 #ifndef LPC17XX_MCPWM_H_
00028 #define LPC17XX_MCPWM_H_
00029 
00030 /* Includes ------------------------------------------------------------------- */
00031 #include "cmsis.h"
00032 #include "lpc_types.h"
00033 
00034 
00035 #ifdef __cplusplus
00036 extern "C"
00037 {
00038 #endif
00039 
00040 
00041 /* Private Macros ------------------------------------------------------------- */
00042 /** @defgroup MCPWM_Private_Macros
00043  * @{
00044  */
00045 
00046 /** @defgroup MCPWM_REGISTER_BIT_DEFINITIONS
00047  * @{
00048  */
00049 
00050 /* MCPWM Control register, these macro definitions below can be applied for these
00051  * register type:
00052  * - MCPWM Control read address
00053  * - MCPWM Control set address
00054  * - MCPWM Control clear address
00055  */
00056 #define MCPWM_CON_RUN(n)        (((n<=2)) ? ((uint32_t)(1UL<<((n*8)+0))) : (0))        /**< Stops/starts timer channel n */
00057 #define MCPWM_CON_CENTER(n)        (((n<=2)) ? ((uint32_t)(1UL<<((n*8)+1))) : (0))        /**< Edge/center aligned operation for channel n */
00058 #define MCPWM_CON_POLAR(n)        (((n<=2)) ? ((uint32_t)(1UL<<((n*8)+2))) : (0))        /**< Select polarity of the MCOAn and MCOBn pin */
00059 #define MCPWM_CON_DTE(n)        (((n<=2)) ? ((uint32_t)(1UL<<((n*8)+3))) : (0))        /**< Control the dead-time feature for channel n */
00060 #define MCPWM_CON_DISUP(n)        (((n<=2)) ? ((uint32_t)(1UL<<((n*8)+4))) : (0))        /**< Enable/Disable update of functional register for channel n */
00061 #define MCPWM_CON_INVBDC        ((uint32_t)(1<<29))                                        /**< Control the polarity for all 3 channels */
00062 #define MCPWM_CON_ACMODE        ((uint32_t)(1<<30))                                        /**< 3-phase AC mode select */
00063 #define MCPWM_CON_DCMODE        ((uint32_t)(1UL<<31))                                        /**< 3-phase DC mode select */
00064 
00065 /* Capture Control register, these macro definitions below can be applied for these
00066  * register type:
00067  * - MCPWM Capture Control read address
00068  * - MCPWM Capture Control set address
00069  * - MCPWM Capture control clear address
00070  */
00071 /** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */
00072 #define MCPWM_CAPCON_CAPMCI_RE(cap,mci)    (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1UL<<((cap*6)+(mci*2)+0))) : (0))
00073 /** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */
00074 #define MCPWM_CAPCON_CAPMCI_FE(cap,mci)    (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1UL<<((cap*6)+(mci*2)+1))) : (0))
00075 /** TC(n) is reset by channel (n) capture event */
00076 #define MCPWM_CAPCON_RT(n)                (((n<=2)) ? ((uint32_t)(1<<(18+(n)))) : (0))
00077 /** Hardware noise filter: channel (n) capture events are delayed */
00078 #define MCPWM_CAPCON_HNFCAP(n)            (((n<=2)) ? ((uint32_t)(1<<(21+(n)))) : (0))
00079 
00080 /* Interrupt registers, these macro definitions below can be applied for these
00081  * register type:
00082  * - MCPWM Interrupt Enable read address
00083  * - MCPWM Interrupt Enable set address
00084  * - MCPWM Interrupt Enable clear address
00085  * - MCPWM Interrupt Flags read address
00086  * - MCPWM Interrupt Flags set address
00087  * - MCPWM Interrupt Flags clear address
00088  */
00089 /** Limit interrupt for channel (n) */
00090 #define MCPWM_INT_ILIM(n)    (((n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0))
00091 /** Match interrupt for channel (n) */
00092 #define MCPWM_INT_IMAT(n)    (((n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0))
00093 /** Capture interrupt for channel (n) */
00094 #define MCPWM_INT_ICAP(n)    (((n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0))
00095 /** Fast abort interrupt */
00096 #define MCPWM_INT_ABORT        ((uint32_t)(1<<15))
00097 
00098 /* MCPWM Count Control register, these macro definitions below can be applied for these
00099  * register type:
00100  * - MCPWM Count Control read address
00101  * - MCPWM Count Control set address
00102  * - MCPWM Count Control clear address
00103  */
00104 /** Counter(tc) advances on a rising edge on MCI(mci) pin */
00105 #define MCPWM_CNTCON_TCMCI_RE(tc,mci)    (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0))
00106 /** Counter(cnt) advances on a falling edge on MCI(mci) pin */
00107 #define MCPWM_CNTCON_TCMCI_FE(tc,mci)    (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0))
00108 /** Channel (n) is in counter mode */
00109 #define MCPWM_CNTCON_CNTR(n)            (((n<=2)) ? ((uint32_t)(1<<(29+n))) : (0))
00110 
00111 /* MCPWM Timer/Counter 0-2 registers --------------------------------------------------- */
00112 /* MCPWM Limit 0-2 registers ----------------------------------------------------------- */
00113 /* MCPWM Match 0-2 registers ----------------------------------------------------------- */
00114 
00115 /* MCPWM Dead-time register ------------------------------------------------------------ */
00116 /** Dead time value x for channel n */
00117 #define MCPWM_DT(n,x)        (((n<=2)) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0))
00118 
00119 /* MCPWM Communication Pattern register ------------------------------------------------ */
00120 #define MCPWM_CP_A0        ((uint32_t)(1<<0))    /**< MCOA0 tracks internal MCOA0 */
00121 #define MCPWM_CP_B0        ((uint32_t)(1<<1))    /**< MCOB0 tracks internal MCOA0 */
00122 #define MCPWM_CP_A1        ((uint32_t)(1<<2))    /**< MCOA1 tracks internal MCOA0 */
00123 #define MCPWM_CP_B1        ((uint32_t)(1<<3))    /**< MCOB1 tracks internal MCOA0 */
00124 #define MCPWM_CP_A2        ((uint32_t)(1<<4))    /**< MCOA2 tracks internal MCOA0 */
00125 #define MCPWM_CP_B2        ((uint32_t)(1<<5))    /**< MCOB2 tracks internal MCOA0 */
00126 
00127 /* MCPWM Capture Registers ------------------------------------------------------------- */
00128 /* MCPWM Capture read addresses */
00129 
00130 /* MCPWM Capture clear address --------------------------------------------------------- */
00131 /** Clear the MCCAP (n) register */
00132 #define MCPWM_CAPCLR_CAP(n)        (((n<=2)) ? ((uint32_t)(1UL<<n)) : (0))
00133 
00134 
00135 /**
00136  * @}
00137  */
00138 
00139 /**
00140  * @}
00141  */
00142 
00143 
00144 /* Public Types --------------------------------------------------------------- */
00145 /** @defgroup MCPWM_Public_Types
00146  * @{
00147  */
00148 
00149 /**
00150  * @brief Motor Control PWM Channel Configuration structure type definition
00151  */
00152 typedef struct {
00153     uint32_t channelType;                    /**< Edge/center aligned mode for this channel,
00154                                                 should be:
00155                                                 - MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode
00156                                                 - MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode
00157                                                 */
00158     uint32_t channelPolarity;                /**< Polarity of the MCOA and MCOB pins, should be:
00159                                                 - MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH
00160                                                 - MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW
00161                                                 */
00162     uint32_t channelDeadtimeEnable;            /**< Enable/Disable DeadTime function for channel, should be:
00163                                                 - ENABLE.
00164                                                 - DISABLE.
00165                                                 */
00166     uint32_t channelDeadtimeValue;            /**< DeadTime value, should be less than 0x3FF */
00167     uint32_t channelUpdateEnable;            /**< Enable/Disable updates of functional registers,
00168                                                  should be:
00169                                                 - ENABLE.
00170                                                 - DISABLE.
00171                                                 */
00172     uint32_t channelTimercounterValue;        /**< MCPWM Timer Counter value */
00173     uint32_t channelPeriodValue;            /**< MCPWM Period value */
00174     uint32_t channelPulsewidthValue;        /**< MCPWM Pulse Width value */
00175 } MCPWM_CHANNEL_CFG_Type;
00176 
00177 /**
00178  * @brief MCPWM Capture Configuration type definition
00179  */
00180 typedef struct {
00181     uint32_t captureChannel;        /**< Capture Channel Number, should be in range from 0 to 2 */
00182     uint32_t captureRising;            /**< Enable/Disable Capture on Rising Edge event, should be:
00183                                         - ENABLE.
00184                                         - DISABLE.
00185                                         */
00186     uint32_t captureFalling;        /**< Enable/Disable Capture on Falling Edge event, should be:
00187                                         - ENABLE.
00188                                         - DISABLE.
00189                                         */
00190     uint32_t timerReset;            /**< Enable/Disable Timer reset function an capture, should be:
00191                                         - ENABLE.
00192                                         - DISABLE.
00193                                         */
00194     uint32_t hnfEnable;                /**< Enable/Disable Hardware noise filter function, should be:
00195                                         - ENABLE.
00196                                         - DISABLE.
00197                                         */
00198 } MCPWM_CAPTURE_CFG_Type;
00199 
00200 
00201 /**
00202  * @brief MCPWM Count Control Configuration type definition
00203  */
00204 typedef struct {
00205     uint32_t counterChannel;        /**< Counter Channel Number, should be in range from 0 to 2 */
00206     uint32_t countRising;            /**< Enable/Disable Capture on Rising Edge event, should be:
00207                                         - ENABLE.
00208                                         - DISABLE.
00209                                         */
00210     uint32_t countFalling;        /**< Enable/Disable Capture on Falling Edge event, should be:
00211                                         - ENABLE.
00212                                         - DISABLE.
00213                                         */
00214 } MCPWM_COUNT_CFG_Type;
00215 
00216 /**
00217  * @}
00218  */
00219 
00220 
00221 /* Public Macros -------------------------------------------------------------- */
00222 /** @defgroup MCPWM_Public_Macros
00223  * @{
00224  */
00225 
00226 
00227 /** Edge aligned mode for channel in MCPWM */
00228 #define MCPWM_CHANNEL_EDGE_MODE            ((uint32_t)(0))
00229 /** Center aligned mode for channel in MCPWM */
00230 #define MCPWM_CHANNEL_CENTER_MODE        ((uint32_t)(1))
00231 
00232 /** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */
00233 #define MCPWM_CHANNEL_PASSIVE_LO        ((uint32_t)(0))
00234 /** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */
00235 #define MCPWM_CHANNEL_PASSIVE_HI        ((uint32_t)(1))
00236 
00237 /* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of
00238  * the six output pins under the control of the bits in this register */
00239 #define MCPWM_PATENT_A0        ((uint32_t)(1<<0))    /**< MCOA0 tracks internal MCOA0 */
00240 #define MCPWM_PATENT_B0        ((uint32_t)(1<<1))    /**< MCOB0 tracks internal MCOA0 */
00241 #define MCPWM_PATENT_A1        ((uint32_t)(1<<2))    /**< MCOA1 tracks internal MCOA0 */
00242 #define MCPWM_PATENT_B1        ((uint32_t)(1<<3))    /**< MCOB1 tracks internal MCOA0 */
00243 #define MCPWM_PATENT_A2        ((uint32_t)(1<<4))    /**< MCOA2 tracks internal MCOA0 */
00244 #define MCPWM_PATENT_B2        ((uint32_t)(1<<5))    /**< MCOB2 tracks internal MCOA0 */
00245 
00246 /* Interrupt type in MCPWM */
00247 /** Limit interrupt for channel (0) */
00248 #define MCPWM_INTFLAG_LIM0    MCPWM_INT_ILIM(0)
00249 /** Match interrupt for channel (0) */
00250 #define MCPWM_INTFLAG_MAT0    MCPWM_INT_IMAT(0)
00251 /** Capture interrupt for channel (0) */
00252 #define MCPWM_INTFLAG_CAP0    MCPWM_INT_ICAP(0)
00253 
00254 /** Limit interrupt for channel (1) */
00255 #define MCPWM_INTFLAG_LIM1    MCPWM_INT_ILIM(1)
00256 /** Match interrupt for channel (1) */
00257 #define MCPWM_INTFLAG_MAT1    MCPWM_INT_IMAT(1)
00258 /** Capture interrupt for channel (1) */
00259 #define MCPWM_INTFLAG_CAP1    MCPWM_INT_ICAP(1)
00260 
00261 /** Limit interrupt for channel (2) */
00262 #define MCPWM_INTFLAG_LIM2    MCPWM_INT_ILIM(2)
00263 /** Match interrupt for channel (2) */
00264 #define MCPWM_INTFLAG_MAT2    MCPWM_INT_IMAT(2)
00265 /** Capture interrupt for channel (2) */
00266 #define MCPWM_INTFLAG_CAP2    MCPWM_INT_ICAP(2)
00267 
00268 /** Fast abort interrupt */
00269 #define MCPWM_INTFLAG_ABORT    MCPWM_INT_ABORT
00270 
00271 
00272 /**
00273  * @}
00274  */
00275 
00276 
00277 /* Public Functions ----------------------------------------------------------- */
00278 /** @defgroup MCPWM_Public_Functions
00279  * @{
00280  */
00281 
00282 void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx);
00283 void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
00284                         MCPWM_CHANNEL_CFG_Type * channelSetup);
00285 void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
00286                         MCPWM_CHANNEL_CFG_Type *channelSetup);
00287 void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
00288                         MCPWM_CAPTURE_CFG_Type *captureConfig);
00289 void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
00290 uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
00291 void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
00292                     uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig);
00293 void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
00294 void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
00295 void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx,uint32_t acMode);
00296 void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode,
00297                     uint32_t outputInvered, uint32_t outputPattern);
00298 void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState);
00299 void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
00300 void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
00301 FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
00302 
00303 /**
00304  * @}
00305  */
00306 
00307 #ifdef __cplusplus
00308 }
00309 #endif
00310 
00311 #endif /* LPC17XX_MCPWM_H_ */
00312 
00313 /**
00314  * @}
00315  */
00316 
00317 /* --------------------------------- End Of File ------------------------------ */