lpc17xx_gpdma.h

00001 /***********************************************************************//**
00002  * @file    : lpc17xx_gpdma.h
00003  * @brief    : Contains all macro definitions and function prototypes
00004  *                 support for GPDMA firmware library on LPC17xx
00005  * @version    : 1.0
00006  * @date    : 20. Apr. 2009
00007  * @author    : HieuNguyen
00008  **************************************************************************
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * products. This software is supplied "AS IS" without any warranties.
00012  * NXP Semiconductors assumes no responsibility or liability for the
00013  * use of the software, conveys no license or title under any patent,
00014  * copyright, or mask work right to the product. NXP Semiconductors
00015  * reserves the right to make changes in the software without
00016  * notification. NXP Semiconductors also make no representation or
00017  * warranty that such application will be suitable for the specified
00018  * use without further testing or modification.
00019  **************************************************************************/
00020 
00021 /* Peripheral group ----------------------------------------------------------- */
00022 /** @defgroup GPDMA
00023  * @ingroup LPC1700CMSIS_FwLib_Drivers
00024  * @{
00025  */
00026 
00027 #ifndef LPC17XX_GPDMA_H_
00028 #define LPC17XX_GPDMA_H_
00029 
00030 /* Includes ------------------------------------------------------------------- */
00031 #include "cmsis.h"
00032 #include "lpc_types.h"
00033 
00034 
00035 #ifdef __cplusplus
00036 extern "C"
00037 {
00038 #endif
00039 
00040 
00041 /* Private Macros ------------------------------------------------------------- */
00042 /** @defgroup GPDMA_Private_Macros
00043  * @{
00044  */
00045 
00046 /** @defgroup DMA_REGISTER_BIT_DEFINITIONS
00047  * @{
00048  */
00049 
00050 /** Macros define for DMA interrupt */
00051 /** DMA Interrupt Status register */
00052 #define GPDMA_DMACIntStat_Ch(n)            (((1UL<<n)&0xFF))
00053 #define GPDMA_DMACIntStat_BITMASK        ((0xFF))
00054 
00055 /** DMA Interrupt Terminal Count Request Status register */
00056 #define GPDMA_DMACIntTCStat_Ch(n)        (((1UL<<n)&0xFF))
00057 #define GPDMA_DMACIntTCStat_BITMASK        ((0xFF))
00058 
00059 /** DMA Interrupt Terminal Count Request Clear register */
00060 #define GPDMA_DMACIntTCClear_Ch(n)        (((1UL<<n)&0xFF))
00061 #define GPDMA_DMACIntTCClear_BITMASK    ((0xFF))
00062 
00063 /** DMA Interrupt Error Status register */
00064 #define GPDMA_DMACIntErrStat_Ch(n)        (((1UL<<n)&0xFF))
00065 #define GPDMA_DMACIntErrStat_BITMASK    ((0xFF))
00066 
00067 /** DMA Interrupt Error Clear register */
00068 #define GPDMA_DMACIntErrClr_Ch(n)        (((1UL<<n)&0xFF))
00069 #define GPDMA_DMACIntErrClr_BITMASK        ((0xFF))
00070 
00071 /** DMA Raw Interrupt Terminal Count Status register */
00072 #define GPDMA_DMACRawIntTCStat_Ch(n)    (((1UL<<n)&0xFF))
00073 #define GPDMA_DMACRawIntTCStat_BITMASK    ((0xFF))
00074 
00075 /** DMA Raw Error Interrupt Status register */
00076 #define GPDMA_DMACRawIntErrStat_Ch(n)    (((1UL<<n)&0xFF))
00077 #define GPDMA_DMACRawIntErrStat_BITMASK    ((0xFF))
00078 
00079 /** DMA Enabled Channel register */
00080 #define GPDMA_DMACEnbldChns_Ch(n)        (((1UL<<n)&0xFF))
00081 #define GPDMA_DMACEnbldChns_BITMASK        ((0xFF))
00082 
00083 
00084 /** Macro defines for DMA Software Burst Request register */
00085 #define    GPDMA_DMACSoftBReq_Src(n)        (((1UL<<n)&0xFFFF))
00086 #define GPDMA_DMACSoftBReq_BITMASK        ((0xFFFF))
00087 
00088 /** Macro defines for DMA Software Single Request register */
00089 #define GPDMA_DMACSoftSReq_Src(n)         (((1UL<<n)&0xFFFF))
00090 #define GPDMA_DMACSoftSReq_BITMASK        ((0xFFFF))
00091 
00092 /** Macro defines for DMA Software Last Burst Request register */
00093 #define GPDMA_DMACSoftLBReq_Src(n)        (((1UL<<n)&0xFFFF))
00094 #define GPDMA_DMACSoftLBReq_BITMASK        ((0xFFFF))
00095 
00096 /** Macro defines for DMA Software Last Single Request register */
00097 #define GPDMA_DMACSoftLSReq_Src(n)         (((1UL<<n)&0xFFFF))
00098 #define GPDMA_DMACSoftLSReq_BITMASK        ((0xFFFF))
00099 
00100 /** DMA Configuration register bit description*/
00101 #define GPDMA_DMACConfig_E                ((0x01))     /**< DMA Controller enable*/
00102 #define GPDMA_DMACConfig_M                ((0x02))     /**< AHB Master endianness configuration*/
00103 #define GPDMA_DMACConfig_BITMASK        ((0x03))
00104 
00105 
00106 /** Macro defines for DMA Synchronization register */
00107 #define GPDMA_DMACSync_Src(n)            (((1UL<<n)&0xFFFF))
00108 #define GPDMA_DMACSync_BITMASK            ((0xFFFF))
00109 
00110 /**  Macro defines for DMA Request Select register */
00111 #define GPDMA_DMAReqSel_Input(n)        (((1UL<<(n-8))&0xFF))
00112 #define GPDMA_DMAReqSel_BITMASK            ((0xFF))
00113 
00114 /** DMA Channel Linked List Item registers bit mask*/
00115 #define GPDMA_DMACCxLLI_BITMASK         ((0xFFFFFFFC))
00116 
00117 /** DMA channel control registers bit description */
00118 #define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0))     /**< Transfer size*/
00119 #define GPDMA_DMACCxControl_SBSize(n)        (((n&0x07)<<12))     /**< Source burst size*/
00120 #define GPDMA_DMACCxControl_DBSize(n)        (((n&0x07)<<15))     /**< Destination burst size*/
00121 #define GPDMA_DMACCxControl_SWidth(n)        (((n&0x07)<<18))     /**< Source transfer width*/
00122 #define GPDMA_DMACCxControl_DWidth(n)        (((n&0x07)<<21))     /**< Destination transfer width*/
00123 #define GPDMA_DMACCxControl_SI                ((1UL<<26))         /**< Source increment*/
00124 #define GPDMA_DMACCxControl_DI                ((1UL<<27))         /**< Destination increment*/
00125 #define GPDMA_DMACCxControl_Prot1            ((1UL<<28))         /**< Indicates that the access is in user mode or privileged mode*/
00126 #define GPDMA_DMACCxControl_Prot2            ((1UL<<29))         /**< Indicates that the access is bufferable or not bufferable*/
00127 #define GPDMA_DMACCxControl_Prot3            ((1UL<<30))         /**< Indicates that the access is cacheable or not cacheable*/
00128 #define GPDMA_DMACCxControl_I                ((1UL<<31))         /**< Terminal count interrupt enable bit */
00129 /** DMA channel control registers bit mask */
00130 #define GPDMA_DMACCxControl_BITMASK            ((0xFCFFFFFF))
00131 
00132 
00133 /** DMA Channel Configuration registers bit description*/
00134 #define GPDMA_DMACCxConfig_E                     ((1UL<<0))            /**< DMA control enable*/
00135 #define GPDMA_DMACCxConfig_SrcPeripheral(n)     (((n&0x1F)<<1))     /**< Source peripheral*/
00136 #define GPDMA_DMACCxConfig_DestPeripheral(n)     (((n&0x1F)<<6))     /**< Destination peripheral*/
00137 #define GPDMA_DMACCxConfig_TransferType(n)         (((n&0x7)<<11))     /**< This value indicates the type of transfer*/
00138 #define GPDMA_DMACCxConfig_IE                     ((1UL<<14))            /**< Interrupt error mask*/
00139 #define GPDMA_DMACCxConfig_ITC                     ((1UL<<15))         /**< Terminal count interrupt mask*/
00140 #define GPDMA_DMACCxConfig_L                     ((1UL<<16))         /**< Lock*/
00141 #define GPDMA_DMACCxConfig_A                     ((1UL<<17))         /**< Active*/
00142 #define GPDMA_DMACCxConfig_H                     ((1UL<<18))         /**< Halt*/
00143 /** DMA Channel Configuration registers bit mask */
00144 #define GPDMA_DMACCxConfig_BITMASK                ((0x7FFFF))
00145 
00146 
00147 /**
00148  * @}
00149  */
00150 
00151 /**
00152  * @}
00153  */
00154 
00155 
00156 /* Public Types --------------------------------------------------------------- */
00157 /** @defgroup GPDMA_Public_Types
00158  * @{
00159  */
00160 
00161 
00162 /**
00163  * @brief GPDMA Channel configuration structure type definition
00164  */
00165 typedef struct {
00166     uint32_t ChannelNum;     /**< DMA channel number, should be in
00167                                 range from 0 to 7.
00168                                 Note: DMA channel 0 has the highest priority
00169                                 and DMA channel 7 the lowest priority.
00170                                 */
00171     uint32_t TransferSize;    /**< Length/Size of transfer */
00172     uint32_t TransferWidth;    /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
00173     uint32_t SrcMemAddr;    /**< Physical Source Address, used in case TransferType is chosen as
00174                                  GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
00175     uint32_t DstMemAddr;    /**< Physical Destination Address, used in case TransferType is chosen as
00176                                  GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
00177     uint32_t TransferType;    /**< Transfer Type, should be one of the following:
00178                             - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
00179                             - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
00180                             - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
00181                             - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
00182                             */
00183     uint32_t SrcConn;        /**< Peripheral Source Connection type, used in case TransferType is chosen as
00184                             GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
00185                             following:
00186                              - GPDMA_CONN_SSP0_Tx: SSP0, Tx
00187                              - GPDMA_CONN_SSP0_Rx: SSP0, Rx
00188                              - GPDMA_CONN_SSP1_Tx: SSP1, Tx
00189                              - GPDMA_CONN_SSP1_Rx: SSP1, Rx
00190                              - GPDMA_CONN_ADC: ADC
00191                              - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
00192                              - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
00193                              - GPDMA_CONN_DAC: DAC
00194                              - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
00195                              - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
00196                              - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
00197                              - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
00198                              - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
00199                              - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
00200                              - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
00201                              - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
00202                              */
00203     uint32_t DstConn;        /**< Peripheral Destination Connection type, used in case TransferType is chosen as
00204                             GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
00205                             following:
00206                              - GPDMA_CONN_SSP0_Tx: SSP0, Tx
00207                              - GPDMA_CONN_SSP0_Rx: SSP0, Rx
00208                              - GPDMA_CONN_SSP1_Tx: SSP1, Tx
00209                              - GPDMA_CONN_SSP1_Rx: SSP1, Rx
00210                              - GPDMA_CONN_ADC: ADC
00211                              - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
00212                              - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
00213                              - GPDMA_CONN_DAC: DAC
00214                              - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
00215                              - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
00216                              - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
00217                              - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
00218                              - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
00219                              - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
00220                              - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
00221                              - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
00222                              */
00223     uint32_t DMALLI;        /**< Linker List Item structure data address
00224                             if there's no Linker List, set as '0'
00225                             */
00226 } GPDMA_Channel_CFG_Type;
00227 
00228 
00229 /**
00230  * @brief GPDMA Linker List Item structure type definition
00231  */
00232 typedef struct {
00233     uint32_t SrcAddr;    /**< Source Address */
00234     uint32_t DstAddr;    /**< Destination address */
00235     uint32_t NextLLI;    /**< Next LLI address, otherwise set to '0' */
00236     uint32_t Control;    /**< GPDMA Control of this LLI */
00237 } GPDMA_LLI_Type;
00238 
00239 
00240 /** GPDMA call-back function type definitions */
00241 typedef void (fnGPDMACbs_Type)(uint32_t channelStatus);
00242 
00243 
00244 /**
00245  * @}
00246  */
00247 
00248 
00249 /* Public Macros -------------------------------------------------------------- */
00250 /** @defgroup GPDMA_Public_Macros
00251  * @{
00252  */
00253 
00254 #define PARAM_GPDMA_CHANNEL(n)    ((n>=0) && (n<=7))
00255 
00256 /** DMA Connection number definitions */
00257 #define GPDMA_CONN_SSP0_Tx             ((0UL))         /**< SSP0 Tx */
00258 #define GPDMA_CONN_SSP0_Rx             ((1UL))         /**< SSP0 Rx */
00259 #define GPDMA_CONN_SSP1_Tx             ((2UL))         /**< SSP1 Tx */
00260 #define GPDMA_CONN_SSP1_Rx             ((3UL))         /**< SSP1 Rx */
00261 #define GPDMA_CONN_ADC                 ((4UL))         /**< ADC */
00262 #define GPDMA_CONN_I2S_Channel_0     ((5UL))         /**< I2S channel 0 */
00263 #define GPDMA_CONN_I2S_Channel_1     ((6UL))         /**< I2S channel 1 */
00264 #define GPDMA_CONN_DAC                 ((7UL))         /**< DAC */
00265 #define GPDMA_CONN_UART0_Tx            ((8UL))         /**< UART0 Tx */
00266 #define GPDMA_CONN_UART0_Rx            ((9UL))         /**< UART0 Rx */
00267 #define GPDMA_CONN_UART1_Tx            ((10UL))         /**< UART1 Tx */
00268 #define GPDMA_CONN_UART1_Rx            ((11UL))         /**< UART1 Rx */
00269 #define GPDMA_CONN_UART2_Tx            ((12UL))         /**< UART2 Tx */
00270 #define GPDMA_CONN_UART2_Rx            ((13UL))         /**< UART2 Rx */
00271 #define GPDMA_CONN_UART3_Tx            ((14UL))         /**< UART3 Tx */
00272 #define GPDMA_CONN_UART3_Rx            ((15UL))         /**< UART3 Rx */
00273 #define GPDMA_CONN_MAT0_0             ((16UL))         /**< MAT0.0 */
00274 #define GPDMA_CONN_MAT0_1             ((17UL))         /**< MAT0.1 */
00275 #define GPDMA_CONN_MAT1_0             ((18UL))         /**< MAT1.0 */
00276 #define GPDMA_CONN_MAT1_1           ((19UL))         /**< MAT1.1 */
00277 #define GPDMA_CONN_MAT2_0           ((20UL))         /**< MAT2.0 */
00278 #define GPDMA_CONN_MAT2_1           ((21UL))         /**< MAT2.1 */
00279 #define GPDMA_CONN_MAT3_0             ((22UL))         /**< MAT3.0 */
00280 #define GPDMA_CONN_MAT3_1           ((23UL))         /**< MAT3.1 */
00281 
00282 #define PARAM_GPDMA_CONN(n)        ((n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \
00283 || (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \
00284 || (n==GPDMA_CONN_ADC) || (n==GPDMA_CONN_I2S_Channel_0) \
00285 || (n==GPDMA_CONN_I2S_Channel_1) || (n==GPDMA_CONN_DAC) \
00286 || (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \
00287 || (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \
00288 || (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \
00289 || (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \
00290 || (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \
00291 || (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \
00292 || (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \
00293 || (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1))
00294 
00295 
00296 /** GPDMA Transfer type definitions */
00297 #define GPDMA_TRANSFERTYPE_M2M         ((0UL))     /**< Memory to memory - DMA control */
00298 #define GPDMA_TRANSFERTYPE_M2P         ((1UL))     /**< Memory to peripheral - DMA control */
00299 #define GPDMA_TRANSFERTYPE_P2M         ((2UL))     /**< Peripheral to memory - DMA control */
00300 #define GPDMA_TRANSFERTYPE_P2P         ((3UL))     /**< Source peripheral to destination peripheral - DMA control */
00301 
00302 
00303 #define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M)||(n==GPDMA_TRANSFERTYPE_M2P) \
00304 ||(n==GPDMA_TRANSFERTYPE_P2M)||(n==GPDMA_TRANSFERTYPE_P2P))
00305 
00306 
00307 /** Burst size in Source and Destination definitions */
00308 #define GPDMA_BSIZE_1     ((0UL)) /**< Burst size = 1 */
00309 #define GPDMA_BSIZE_4     ((1UL)) /**< Burst size = 4 */
00310 #define GPDMA_BSIZE_8     ((2UL)) /**< Burst size = 8 */
00311 #define GPDMA_BSIZE_16     ((3UL)) /**< Burst size = 16 */
00312 #define GPDMA_BSIZE_32     ((4UL)) /**< Burst size = 32 */
00313 #define GPDMA_BSIZE_64     ((5UL)) /**< Burst size = 64 */
00314 #define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
00315 #define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
00316 
00317 #define PARAM_GPDMA_BSIZE(n)    ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \
00318 || (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \
00319 || (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \
00320 || (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256))
00321 
00322 
00323 /** Width in Source transfer width and Destination transfer width definitions */
00324 #define GPDMA_WIDTH_BYTE         ((0UL)) /**< Width = 1 byte */
00325 #define GPDMA_WIDTH_HALFWORD     ((1UL)) /**< Width = 2 bytes */
00326 #define GPDMA_WIDTH_WORD         ((2UL)) /**< Width = 4 bytes */
00327 
00328 #define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \
00329 || (n==GPDMA_WIDTH_WORD))
00330 
00331 
00332 /** DMA Request Select Mode definitions */
00333 #define GPDMA_REQSEL_UART     ((0UL)) /**< UART TX/RX is selected */
00334 #define GPDMA_REQSEL_TIMER     ((1UL)) /**< Timer match is selected */
00335 
00336 #define PARAM_GPDMA_REQSEL(n)    ((n==GPDMA_REQSEL_UART) || (n==GPDMA_REQSEL_TIMER))
00337 
00338 /** GPDMA Status type definitions */
00339 /** GPDMA Interrupt Status */
00340 #define GPDMA_STAT_INT            ((0UL))
00341 /** GPDMA Interrupt Terminal Count Request Status */
00342 #define GPDMA_STAT_INTTC        ((1UL))
00343 /** GPDMA Interrupt Error Status */
00344 #define GPDMA_STAT_INTERR        ((2UL))
00345 /** GPDMA Raw Interrupt Terminal Count Status */
00346 #define GPDMA_STAT_RAWINTTC        ((3UL))
00347 /** GPDMA Raw Error Interrupt Status */
00348 #define GPDMA_STAT_RAWINTERR    ((4UL))
00349 /** DMA Enabled Channel Status */
00350 #define GPDMA_STAT_ENABLED_CH    ((5UL))
00351 
00352 #define PARAM_GPDMA_STAT(n)    ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \
00353 || (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \
00354 || (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH))
00355 
00356 /** GPDMA status type definition that can be clear */
00357 /** GPDMA Interrupt Terminal Count Request Clear */
00358 #define GPDMA_STATCLR_INTTC        ((0UL))
00359 /** GPDMA Interrupt Error Clear */
00360 #define GPDMA_STATCLR_INTERR    ((1UL))
00361 
00362 #define GPDMA_STATCLR(n)    ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR))
00363 
00364 /**
00365  * @}
00366  */
00367 
00368 
00369 /* Public Functions ----------------------------------------------------------- */
00370 /** @defgroup GPDMA_Public_Functions
00371  * @{
00372  */
00373 
00374 void GPDMA_Init(void);
00375 Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig, fnGPDMACbs_Type *pfnGPDMACbs);
00376 void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
00377 void GPDMA_IntHandler(void);
00378 
00379 /**
00380  * @}
00381  */
00382 
00383 
00384 #ifdef __cplusplus
00385 }
00386 #endif
00387 
00388 #endif /* LPC17XX_GPDMA_H_ */
00389 
00390 /**
00391  * @}
00392  */
00393 
00394 /* --------------------------------- End Of File ------------------------------ */