lpc17xx_clkpwr.h

00001 /***********************************************************************//**
00002  * @file    : lpc17xx_clkpwr.h
00003  * @brief    : Contains all macro definitions and function prototypes
00004  *                 support for Clock and Power Control firmware library on LPC17xx
00005  * @version    : 1.0
00006  * @date    : 18. Mar. 2009
00007  * @author    : HieuNguyen
00008  **************************************************************************
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * products. This software is supplied "AS IS" without any warranties.
00012  * NXP Semiconductors assumes no responsibility or liability for the
00013  * use of the software, conveys no license or title under any patent,
00014  * copyright, or mask work right to the product. NXP Semiconductors
00015  * reserves the right to make changes in the software without
00016  * notification. NXP Semiconductors also make no representation or
00017  * warranty that such application will be suitable for the specified
00018  * use without further testing or modification.
00019  **************************************************************************/
00020 
00021 /* Peripheral group ----------------------------------------------------------- */
00022 /** @defgroup CLKPWR
00023  * @ingroup LPC1700CMSIS_FwLib_Drivers
00024  * @{
00025  */
00026 
00027 #ifndef LPC17XX_CLKPWR_H_
00028 #define LPC17XX_CLKPWR_H_
00029 
00030 /* Includes ------------------------------------------------------------------- */
00031 #include "cmsis.h"
00032 #include "lpc_types.h"
00033 
00034 #ifdef __cplusplus
00035 extern "C"
00036 {
00037 #endif
00038 
00039 
00040 /* Private Macros ------------------------------------------------------------- */
00041 /** @defgroup CLKPWR_Private_Macros
00042  * @{
00043  */
00044 
00045 /** @defgroup CLKPPWR_REGISTER_BIT_DEFINITIONS
00046  * @{
00047  */
00048 
00049 /* Clock source selection multiplexer definition */
00050 /** Internal RC oscillator */
00051 #define CLKPWR_CLKSRCSEL_CLKSRC_IRC            ((uint32_t)(0x00))
00052 /** Main oscillator */
00053 #define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC        ((uint32_t)(0x01))
00054 /** RTC oscillator */
00055 #define CLKPWR_CLKSRCSEL_CLKSRC_RTC            ((uint32_t)(0x02))
00056 /** Clock source selection bit mask */
00057 #define CLKPWR_CLKSRCSEL_BITMASK            ((uint32_t)(0x03))
00058 
00059 
00060 /* Clock Output Configuration register definition */
00061 /** Selects the CPU clock as the CLKOUT source */
00062 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU        ((uint32_t)(0x00))
00063 /** Selects the main oscillator as the CLKOUT source */
00064 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC    ((uint32_t)(0x01))
00065 /** Selects the Internal RC oscillator as the CLKOUT source */
00066 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC        ((uint32_t)(0x02))
00067 /** Selects the USB clock as the CLKOUT source */
00068 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB        ((uint32_t)(0x03))
00069 /** Selects the RTC oscillator as the CLKOUT source */
00070 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC        ((uint32_t)(0x04))
00071 /** Integer value to divide the output clock by, minus one */
00072 #define CLKPWR_CLKOUTCFG_CLKOUTDIV(n)        ((uint32_t)((n&0x0F)<<4))
00073 /** CLKOUT enable control */
00074 #define CLKPWR_CLKOUTCFG_CLKOUT_EN            ((uint32_t)(1<<8))
00075 /** CLKOUT activity indication */
00076 #define CLKPWR_CLKOUTCFG_CLKOUT_ACT            ((uint32_t)(1<<9))
00077 /** Clock source selection bit mask */
00078 #define CLKPWR_CLKOUTCFG_BITMASK            ((uint32_t)(0x3FF))
00079 
00080 
00081 /* PLL 0 control definition */
00082 /** PLL 0 control enable */
00083 #define CLKPWR_PLL0CON_ENABLE        ((uint32_t)(0x01))
00084 /** PLL 0 control connect */
00085 #define CLKPWR_PLL0CON_CONNECT        ((uint32_t)(0x02))
00086 /** PLL 0 control bit mask */
00087 #define CLKPWR_PLL0CON_BITMASK        ((uint32_t)(0x03))
00088 
00089 
00090 /* PLL 0 Configuration register definition */
00091 /** PLL 0 Configuration MSEL field */
00092 #define CLKPWR_PLL0CFG_MSEL(n)        ((uint32_t)(n&0x7FFF))
00093 /** PLL 0 Configuration NSEL field */
00094 #define CLKPWR_PLL0CFG_NSEL(n)        ((uint32_t)((n<<16)&0xFF0000))
00095 /** PLL 0 Configuration bit mask */
00096 #define CLKPWR_PLL0CFG_BITMASK        ((uint32_t)(0xFF7FFF))
00097 
00098 
00099 /* PLL 0 status definition */
00100 /** PLL 0 MSEL value */
00101 #define CLKPWR_PLL0STAT_MSEL(n)        ((uint32_t)(n&0x7FFF))
00102 /** PLL NSEL get value  */
00103 #define CLKPWR_PLL0STAT_NSEL(n)        ((uint32_t)((n>>16)&0xFF))
00104 /** PLL status enable bit */
00105 #define CLKPWR_PLL0STAT_PLLE        ((uint32_t)(1<<24))
00106 /** PLL status Connect bit */
00107 #define CLKPWR_PLL0STAT_PLLC        ((uint32_t)(1<<25))
00108 /** PLL status lock */
00109 #define CLKPWR_PLL0STAT_PLOCK        ((uint32_t)(1<<26))
00110 
00111 
00112 /* PLL0 Feed register definition */
00113 /** PLL0 Feed bit mask */
00114 #define CLKPWR_PLL0FEED_BITMASK            ((uint32_t)0xFF)
00115 
00116 
00117 /* USB PLL control definition */
00118 /** USB PLL control enable */
00119 #define CLKPWR_PLL1CON_ENABLE        ((uint32_t)(0x01))
00120 /** USB PLL control connect */
00121 #define CLKPWR_PLL1CON_CONNECT        ((uint32_t)(0x02))
00122 /** USB PLL control bit mask */
00123 #define CLKPWR_PLL1CON_BITMASK        ((uint32_t)(0x03))
00124 
00125 
00126 /* USB PLL configuration definition */
00127 /** USB PLL MSEL set value */
00128 #define CLKPWR_PLL1CFG_MSEL(n)        ((uint32_t)(n&0x1F))
00129 /** USB PLL PSEL set value */
00130 #define CLKPWR_PLL1CFG_PSEL(n)        ((uint32_t)((n&0x03)<<5))
00131 /** USB PLL configuration bit mask */
00132 #define CLKPWR_PLL1CFG_BITMASK        ((uint32_t)(0x7F))
00133 
00134 
00135 /* USB PLL status definition */
00136 /** USB PLL MSEL get value  */
00137 #define CLKPWR_PLL1STAT_MSEL(n)        ((uint32_t)(n&0x1F))
00138 /** USB PLL PSEL get value  */
00139 #define CLKPWR_PLL1STAT_PSEL(n)        ((uint32_t)((n>>5)&0x03))
00140 /** USB PLL status enable bit */
00141 #define CLKPWR_PLL1STAT_PLLE        ((uint32_t)(1<<8))
00142 /** USB PLL status Connect bit */
00143 #define CLKPWR_PLL1STAT_PLLC        ((uint32_t)(1<<9))
00144 /** USB PLL status lock */
00145 #define CLKPWR_PLL1STAT_PLOCK        ((uint32_t)(1<<10))
00146 
00147 
00148 /* PLL1 Feed register definition */
00149 /** PLL1 Feed bit mask */
00150 #define CLKPWR_PLL1FEED_BITMASK        ((uint32_t)0xFF)
00151 
00152 
00153 /* CPU Clock Configuration register definition */
00154 /** CPU Clock configuration bit mask */
00155 #define CLKPWR_CCLKCFG_BITMASK        ((uint32_t)(0xFF))
00156 
00157 /* USB Clock Configuration register definition */
00158 /** USB Clock Configuration bit mask */
00159 #define CLKPWR_USBCLKCFG_BITMASK    ((uint32_t)(0x0F))
00160 
00161 /* IRC Trim register definition */
00162 /** IRC Trim bit mask */
00163 #define CLKPWR_IRCTRIM_BITMASK        ((uint32_t)(0x0F))
00164 
00165 
00166 /* Peripheral clock divider bit position definition */
00167 /** Peripheral Clock Selection 0 mask bit */
00168 #define CLKPWR_PCLKSEL0_BITMASK        ((uint32_t)(0xFFF3F3FF))
00169 /** Peripheral Clock Selection 1 mask bit */
00170 #define CLKPWR_PCLKSEL1_BITMASK        ((uint32_t)(0xFCF3F0F3))
00171 
00172 
00173 /** Macro to set peripheral clock of each type
00174  * p: position of two bits that hold divider of peripheral clock
00175  * n: value of divider of peripheral clock  to be set */
00176 #define CLKPWR_PCLKSEL_SET(p,n)        _SBF(p,n)
00177 /** Macro to mask peripheral clock of each type */
00178 #define CLKPWR_PCLKSEL_BITMASK(p)    _SBF(p,0x03)
00179 /** Macro to get peripheral clock of each type */
00180 #define CLKPWR_PCLKSEL_GET(p, n)    ((uint32_t)((n>>p)&0x03))
00181 
00182 
00183 /* Power Mode Control register definition */
00184 /** Power mode control bit 0 */
00185 #define CLKPWR_PCON_PM0            ((uint32_t)(1<<0))
00186 /** Power mode control bit 1 */
00187 #define CLKPWR_PCON_PM1            ((uint32_t)(1<<1))
00188 /** Brown-Out Reduced Power Mode */
00189 #define CLKPWR_PCON_BODPDM        ((uint32_t)(1<<2))
00190 /** Brown-Out Global Disable */
00191 #define CLKPWR_PCON_BOGD        ((uint32_t)(1<<3))
00192 /** Brown Out Reset Disable */
00193 #define CLKPWR_PCON_BORD        ((uint32_t)(1<<4))
00194 /** Sleep Mode entry flag */
00195 #define CLKPWR_PCON_SMFLAG        ((uint32_t)(1<<8))
00196 /** Deep Sleep entry flag */
00197 #define CLKPWR_PCON_DSFLAG        ((uint32_t)(1<<9))
00198 /** Power-down entry flag */
00199 #define CLKPWR_PCON_PDFLAG        ((uint32_t)(1<<10))
00200 /** Deep Power-down entry flag */
00201 #define CLKPWR_PCON_DPDFLAG        ((uint32_t)(1<<11))
00202 
00203 
00204 /** Power Control for Peripherals bit mask */
00205 #define CLKPWR_PCONP_BITMASK    0xEFEFF7DE
00206 
00207 /**
00208  * @}
00209  */
00210 
00211 /**
00212  * @}
00213  */
00214 
00215 
00216 /* Public Macros -------------------------------------------------------------- */
00217 /** @defgroup CLKPWR_Public_Macros
00218  * @{
00219  */
00220 
00221 /**********************************************************************
00222  * Peripheral Clock Selection Definitions
00223  **********************************************************************/
00224 /** Peripheral clock divider bit position for WDT */
00225 #define    CLKPWR_PCLKSEL_WDT          ((uint32_t)(0))
00226 /** Peripheral clock divider bit position for TIMER0 */
00227 #define    CLKPWR_PCLKSEL_TIMER0          ((uint32_t)(2))
00228 /** Peripheral clock divider bit position for TIMER1 */
00229 #define    CLKPWR_PCLKSEL_TIMER1          ((uint32_t)(4))
00230 /** Peripheral clock divider bit position for UART0 */
00231 #define    CLKPWR_PCLKSEL_UART0          ((uint32_t)(6))
00232 /** Peripheral clock divider bit position for UART1 */
00233 #define    CLKPWR_PCLKSEL_UART1          ((uint32_t)(8))
00234 /** Peripheral clock divider bit position for PWM1 */
00235 #define    CLKPWR_PCLKSEL_PWM1          ((uint32_t)(12))
00236 /** Peripheral clock divider bit position for I2C0 */
00237 #define    CLKPWR_PCLKSEL_I2C0          ((uint32_t)(14))
00238 /** Peripheral clock divider bit position for SPI */
00239 #define    CLKPWR_PCLKSEL_SPI          ((uint32_t)(16))
00240 /** Peripheral clock divider bit position for SSP1 */
00241 #define    CLKPWR_PCLKSEL_SSP1          ((uint32_t)(20))
00242 /** Peripheral clock divider bit position for DAC */
00243 #define    CLKPWR_PCLKSEL_DAC          ((uint32_t)(22))
00244 /** Peripheral clock divider bit position for ADC */
00245 #define    CLKPWR_PCLKSEL_ADC          ((uint32_t)(24))
00246 /** Peripheral clock divider bit position for CAN1 */
00247 #define    CLKPWR_PCLKSEL_CAN1         ((uint32_t)(26))
00248 /** Peripheral clock divider bit position for CAN2 */
00249 #define    CLKPWR_PCLKSEL_CAN2         ((uint32_t)(28))
00250 /** Peripheral clock divider bit position for ACF */
00251 #define    CLKPWR_PCLKSEL_ACF          ((uint32_t)(30))
00252 /** Peripheral clock divider bit position for QEI */
00253 #define    CLKPWR_PCLKSEL_QEI              ((uint32_t)(32))
00254 /** Peripheral clock divider bit position for PCB */
00255 #define    CLKPWR_PCLKSEL_PCB          ((uint32_t)(36))
00256 /** Peripheral clock divider bit position for  I2C1 */
00257 #define    CLKPWR_PCLKSEL_I2C1          ((uint32_t)(38))
00258 /** Peripheral clock divider bit position for SSP0 */
00259 #define    CLKPWR_PCLKSEL_SSP0          ((uint32_t)(42))
00260 /** Peripheral clock divider bit position for TIMER2 */
00261 #define    CLKPWR_PCLKSEL_TIMER2          ((uint32_t)(44))
00262 /** Peripheral clock divider bit position for  TIMER3 */
00263 #define    CLKPWR_PCLKSEL_TIMER3          ((uint32_t)(46))
00264 /** Peripheral clock divider bit position for UART2 */
00265 #define    CLKPWR_PCLKSEL_UART2          ((uint32_t)(48))
00266 /** Peripheral clock divider bit position for UART3 */
00267 #define    CLKPWR_PCLKSEL_UART3          ((uint32_t)(50))
00268 /** Peripheral clock divider bit position for I2C2 */
00269 #define    CLKPWR_PCLKSEL_I2C2          ((uint32_t)(52))
00270 /** Peripheral clock divider bit position for I2S */
00271 #define    CLKPWR_PCLKSEL_I2S          ((uint32_t)(54))
00272 /** Peripheral clock divider bit position for RIT */
00273 #define    CLKPWR_PCLKSEL_RIT          ((uint32_t)(58))
00274 /** Peripheral clock divider bit position for SYSCON */
00275 #define    CLKPWR_PCLKSEL_SYSCON          ((uint32_t)(60))
00276 /** Peripheral clock divider bit position for MC */
00277 #define    CLKPWR_PCLKSEL_MC              ((uint32_t)(62))
00278 
00279 /** Macro for Peripheral Clock Selection register bit values
00280  * Note: When CCLK_DIV_8, Peripheral&#146;s clock is selected to
00281  * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
00282  * when &#146;11&#146;selects PCLK_xyz = CCLK/6 */
00283 /* Peripheral clock divider is set to 4 from CCLK */
00284 #define    CLKPWR_PCLKSEL_CCLK_DIV_4  ((uint32_t)(0))
00285 /** Peripheral clock divider is the same with CCLK */
00286 #define    CLKPWR_PCLKSEL_CCLK_DIV_1  ((uint32_t)(1))
00287 /** Peripheral clock divider is set to 2 from CCLK */
00288 #define    CLKPWR_PCLKSEL_CCLK_DIV_2  ((uint32_t)(2))
00289 
00290 
00291 /********************************************************************
00292 * Power Control for Peripherals Definitions
00293 **********************************************************************/
00294 /** Timer/Counter 0 power/clock control bit */
00295 #define     CLKPWR_PCONP_PCTIM0    ((uint32_t)(1<<1))
00296 /* Timer/Counter 1 power/clock control bit */
00297 #define     CLKPWR_PCONP_PCTIM1    ((uint32_t)(1<<2))
00298 /** UART0 power/clock control bit */
00299 #define     CLKPWR_PCONP_PCUART0      ((uint32_t)(1<<3))
00300 /** UART1 power/clock control bit */
00301 #define     CLKPWR_PCONP_PCUART1      ((uint32_t)(1<<4))
00302 /** PWM1 power/clock control bit */
00303 #define     CLKPWR_PCONP_PCPWM1    ((uint32_t)(1<<6))
00304 /** The I2C0 interface power/clock control bit */
00305 #define     CLKPWR_PCONP_PCI2C0    ((uint32_t)(1<<7))
00306 /** The SPI interface power/clock control bit */
00307 #define     CLKPWR_PCONP_PCSPI      ((uint32_t)(1<<8))
00308 /** The RTC power/clock control bit */
00309 #define     CLKPWR_PCONP_PCRTC      ((uint32_t)(1<<9))
00310 /** The SSP1 interface power/clock control bit */
00311 #define     CLKPWR_PCONP_PCSSP1    ((uint32_t)(1<<10))
00312 /** A/D converter 0 (ADC0) power/clock control bit */
00313 #define     CLKPWR_PCONP_PCAD      ((uint32_t)(1<<12))
00314 /** CAN Controller 1 power/clock control bit */
00315 #define     CLKPWR_PCONP_PCAN1      ((uint32_t)(1<<13))
00316 /** CAN Controller 2 power/clock control bit */
00317 #define     CLKPWR_PCONP_PCAN2      ((uint32_t)(1<<14))
00318 /** GPIO power/clock control bit */
00319 #define    CLKPWR_PCONP_PCGPIO        ((uint32_t)(1<<15))
00320 /** Repetitive Interrupt Timer power/clock control bit */
00321 #define    CLKPWR_PCONP_PCRIT        ((uint32_t)(1<<16))
00322 /** Motor Control PWM */
00323 #define CLKPWR_PCONP_PCMC        ((uint32_t)(1<<17))
00324 /** Quadrature Encoder Interface power/clock control bit */
00325 #define CLKPWR_PCONP_PCQEI        ((uint32_t)(1<<18))
00326 /** The I2C1 interface power/clock control bit */
00327 #define     CLKPWR_PCONP_PCI2C1      ((uint32_t)(1<<19))
00328 /** The SSP0 interface power/clock control bit */
00329 #define     CLKPWR_PCONP_PCSSP0    ((uint32_t)(1<<21))
00330 /** Timer 2 power/clock control bit */
00331 #define     CLKPWR_PCONP_PCTIM2    ((uint32_t)(1<<22))
00332 /** Timer 3 power/clock control bit */
00333 #define     CLKPWR_PCONP_PCTIM3    ((uint32_t)(1<<23))
00334 /** UART 2 power/clock control bit */
00335 #define     CLKPWR_PCONP_PCUART2      ((uint32_t)(1<<24))
00336 /** UART 3 power/clock control bit */
00337 #define     CLKPWR_PCONP_PCUART3      ((uint32_t)(1<<25))
00338 /** I2C interface 2 power/clock control bit */
00339 #define     CLKPWR_PCONP_PCI2C2    ((uint32_t)(1<<26))
00340 /** I2S interface power/clock control bit*/
00341 #define     CLKPWR_PCONP_PCI2S      ((uint32_t)(1<<27))
00342 /** GP DMA function power/clock control bit*/
00343 #define     CLKPWR_PCONP_PCGPDMA      ((uint32_t)(1<<29))
00344 /** Ethernet block power/clock control bit*/
00345 #define     CLKPWR_PCONP_PCENET    ((uint32_t)(1<<30))
00346 /** USB interface power/clock control bit*/
00347 #define     CLKPWR_PCONP_PCUSB      ((uint32_t)(1<<31))
00348 
00349 
00350 /**
00351  * @}
00352  */
00353 
00354 
00355 /* Public Functions ----------------------------------------------------------- */
00356 /** @defgroup CLKPWR_Public_Functions
00357  * @{
00358  */
00359 
00360 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
00361 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
00362 uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
00363 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
00364 void CLKPWR_Sleep(void);
00365 void CLKPWR_DeepSleep(void);
00366 void CLKPWR_PowerDown(void);
00367 void CLKPWR_DeepPowerDown(void);
00368 
00369 /**
00370  * @}
00371  */
00372 
00373 
00374 #ifdef __cplusplus
00375 }
00376 #endif
00377 
00378 #endif /* LPC17XX_CLKPWR_H_ */
00379 
00380 /**
00381  * @}
00382  */
00383 
00384 /* --------------------------------- End Of File ------------------------------ */