david dicarlo / mbed-src-FLL48

mbed library sources: Modified to operate FRDM-KL25Z at 48MHz from internal 32kHz oscillator (nothing else changed).

Fork of mbed-src by mbed official

The only file that changed is: mbed-src-FLL48/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h

Files at this revision

API Documentation at this revision

Revision 28:32fcdc465df5, committed 2013-09-19

Comitter:
icenyne
Date:
Thu Sep 19 17:13:13 2013 +0000
Parent:
27:3315632cc01d
Child:
29:421d0b2f3ba7
Commit message:
Updated CLOCK_SETUP 0 to run at 48MHz instead of 41MHz from internal oscillator.

Changed in this revision

targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.c Show annotated file Show diff for this revision Revisions of this file 
--- a/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.c	Thu Sep 19 10:00:04 2013 +0100
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.c	Thu Sep 19 17:13:13 2013 +0000
@@ -44,7 +44,7 @@
 
 #define DISABLE_WDOG    1
 
-#define CLOCK_SETUP     1
+#define CLOCK_SETUP     0  /* icenyne: changed from 1 */
 /* Predefined clock setups
    0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
          Reference clock source for MCG module is the slow internal clock source 32.768kHz
@@ -95,15 +95,23 @@
   SIM->COPC = (uint32_t)0x00u;
 #endif /* (DISABLE_WDOG) */
 #if (CLOCK_SETUP == 0)
-  /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
-  SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
+  /**********************************************
+   * icenyne: updated this block to operate at  *
+   * 48MHz from internal 32.768kHz oscillator.  * 
+   * Specific changes noted below...            *
+   **********************************************/
+  /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+  SIM->CLKDIV1 = (uint32_t)0x00010000UL; /* Update system prescalers  [icenyne: changed '2' to '1'] */
   /* Switch to FEI Mode */
   /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
   MCG->C1 = (uint8_t)0x06U;
   /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
   MCG->C2 = (uint8_t)0x00U;
-  /* MCG->C4: DMX32=0,DRST_DRS=1 */
-  MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
+  /* MCG->C4: DMX32=1,DRST_DRS=1 [icenyne: changed this whole statement ] */
+  MCG->C4 = (uint8_t)((MCG->C4 
+            & (uint8_t)~(uint8_t)( MCG_C4_DRST_DRS(0x02))) 
+            | (uint8_t)( MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x01)));                    
+
   /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
   OSC0->CR = (uint8_t)0x80U;
   /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */