embedded RTOS class project.

Fork of RTOS_project by Mike Moore

Files at this revision

API Documentation at this revision

Comitter:
gatedClock
Date:
Tue Sep 17 19:42:49 2013 +0000
Child:
1:a3df81701818
Commit message:
title.

Changed in this revision

C12832_lcd.lib Show annotated file Show diff for this revision Revisions of this file
USBDevice.lib Show annotated file Show diff for this revision Revisions of this file
main.cpp Show annotated file Show diff for this revision Revisions of this file
mbed-rtos.lib Show annotated file Show diff for this revision Revisions of this file
mbed.bld Show annotated file Show diff for this revision Revisions of this file
mmCPUassemblySource/prog_add_list.txt Show annotated file Show diff for this revision Revisions of this file
mmCPUassemblySource/prog_loop_registers.txt Show annotated file Show diff for this revision Revisions of this file
mmPython/invoke.txt Show annotated file Show diff for this revision Revisions of this file
mmPython/mmProject.txt Show annotated file Show diff for this revision Revisions of this file
mmPython/mmUI.txt Show annotated file Show diff for this revision Revisions of this file
mmPython/mmUSBserial.txt Show annotated file Show diff for this revision Revisions of this file
mmRTL/counter_08.txt Show annotated file Show diff for this revision Revisions of this file
mmRTL/cpu.txt Show annotated file Show diff for this revision Revisions of this file
mmRTL/instruction_decoder.txt Show annotated file Show diff for this revision Revisions of this file
mmRTL/main_memory.txt Show annotated file Show diff for this revision Revisions of this file
mmRTL/mux16x2.txt Show annotated file Show diff for this revision Revisions of this file
mmRTL/mux8x16.txt Show annotated file Show diff for this revision Revisions of this file
mmRTL/mux8x8.txt Show annotated file Show diff for this revision Revisions of this file
mmRTL/reg_08.txt Show annotated file Show diff for this revision Revisions of this file
mmRTL/reg_16.txt Show annotated file Show diff for this revision Revisions of this file
mmRTL/scan_08.txt Show annotated file Show diff for this revision Revisions of this file
mmRTL/scan_16.txt Show annotated file Show diff for this revision Revisions of this file
mmRTL/shadow_load_control.txt Show annotated file Show diff for this revision Revisions of this file
mmSPI.lib Show annotated file Show diff for this revision Revisions of this file
mmTestResult/clock_count.txt Show annotated file Show diff for this revision Revisions of this file
mmTestResult/dump_add_list.txt Show annotated file Show diff for this revision Revisions of this file
mmTestResult/testlog.txt Show annotated file Show diff for this revision Revisions of this file
watchdog.lib Show annotated file Show diff for this revision Revisions of this file
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/C12832_lcd.lib	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,1 @@
+http://mbed.org/users/dreschpe/code/C12832_lcd/#468cdccff7af
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USBDevice.lib	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,1 @@
+http://mbed.org/users/mbed_official/code/USBDevice/#335f2506f422
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,918 @@
+/*----------------------------------------------//------------------------------
+    student   : m-moore
+    email     : gated.clock@gmail.com
+    class     : embedded RTOS
+    directory : USB_device_project
+    file      : main.cpp
+    date      : september 19, 2013.
+----copyright-----------------------------------//------------------------------   
+    licensed for personal and academic use.
+    commercial use of original code must be approved by the account-holder of
+    gated.clock@gmail.com
+----revision------------------------------------//------------------------------
+    this is the embedded RTOS class revision.
+    changes made since the USB device class release:
+    
+    1. a 'read all registers' feature has been added, which speeds up
+       CPU execution, since the UI obtains all of the register states after
+       each CPU clock.  originally, each register was individually read.
+       now, all registers are read at once, if so requested by the python code.
+       
+    2. some 'if' statements were changed to 'switch' statements (neatening).
+    
+    3. added watchdog timers for the three threads.  this via a meta-watchdog thread.
+    
+    4. added #defined-based option to either boot on error detection
+       (such as malloc fail) or use error(); function.
+       
+    5. the LCD is updated only if a display value is changed - reduced power
+       usage a little & reduces potential 'blinkieness'.
+       
+    6. BOOT notification on LCD.
+----description---------------------------------//------------------------------
+    overview:
+    program to provide round-trip communication between a python test-control
+    program running on a pc host, and a device-under-test CPU implemented on
+    an altera board.  the pc-host communication is over USBSerial, and the
+    altera communication is over SPI.
+    
+    features:
+    1. multi-threaded design, use of memory-pools to transfer data between threads.
+    2. use of USBDevice library for communication with PC host.
+    3. use of mmSPI custom library for communication with FPGA.
+    4. main thread provides USBSerial communication to/from host.
+    5. SPI processing thread provides SPI communication to/from DUT.
+    6. mmSPI library generates non-overlapping SPI and CPU clocks.
+    7. background diagnostic thread provides LCD & error updates.
+    8. meta watchdog thread monitors itself & the other threads.
+
+    indicators: (led<3:0> = LED<1:4>)
+    1. LCD  provides running counts for SPI and CPU clock cycles.
+    2. led0 indicates main     thread processing.
+    3. led1 indicates SPI      thread processing.
+    4. led2 indicates LCD      thread processing.
+    5. led3 indicates watchdog thread processing.
+    
+    implementation:
+    1. main.processIncomingSerial(): accept incoming serial data from host,
+       and map it into tFromHost structures.
+    2. SPIprocessingThread: take the incoming data structures instances, and
+       feed their content into mmSPI commands.
+    3. mmSPI object: given commands/data passed from caller,
+       map them into SPI outgoing vectors and scan them into the FPGA.
+    4. mmSPI object: receive incoming SPI vectors from FPGA.
+       make FPGA payload data available to caller.
+    5. SPIprocessingThread: load tToHost structures with said FPGA payload data.
+    6. main.processOutgoingSerial(): transfer tToHost structure data into a
+       serial outgoing buffer, and block-transfer it to the host PC.
+       
+    electrical:
+    1. four pins (and ground) attached to the zigbee header,
+       programmed as three SPI pins and the CPU clock.
+    2. each of the four signals over twisted-pair.
+    3. but some ribbon cable is used at the FPGA end.
+    4. best if only the mbed application board USB cable is attached
+       to the host; if the mbed CPU board USB cable is also attached to
+       the host, then the python program may attempt to use the wrong USB
+       connection.
+    5. no particular power sequence is needed for this system to work.
+    
+    timing critical path:  serial processing.  the python code needs
+    a delay between serial access of 40mS conservatively.
+    
+    testing:
+    the python UI provides the main testing mechanism.
+    
+        USB connect.
+    00. press 'CONNECT' button in UI.  verify connection info in shell.
+    
+        CPU register w/r
+    01. type values into {R0,R1,R2,R3,PC,IR} UI entry-forms.
+    02. press 'REG WRITE' UI button.
+    03. press 'REG READ'  UI button.
+    04. verify that the read data is correct.
+    
+        CPU main-memory w/r
+    05. type an address into 'mmADR' UI entry-form.
+    06. type data into 'mmVAL' UI entry-form.
+    07. press 'MM WRITE' UI button.
+    08. type a different address into 'mmADR' UI entry-form.
+    09. type different data into 'mmVAL' UI entry-form.
+    10. press 'MM WRITE' UI button.
+    11. type address from (05) into 'mmADR' UI entry-form.
+    12. press 'MM READ' UI button.
+    13. verify that the data from (06) is seen in the 'mmVAL' entry form.
+    14. type address from (08) into 'mmADR' UI entry-form.
+    15. press 'MM READ' UI button.
+    16. verify that the data from (09) is seen in the 'mmVAL' entry form.  
+    
+        CPU main-memory full load/dump.
+    17. press 'PROGRAM' in the UI.  select a program file in the dialog-popup.  
+    18. watch the load process in the shell text.
+    19. press 'DUMP     in the UI.  select a main-memory dump file in the diaglog-popup.
+    20. watch the dump process in the shell text.
+    
+        CPU step function.
+    21. press 'STEP' in the UI repeatedly, watch the UI display the 
+        CPU register states as the current program is executed one CPU clock
+        at a time.
+        
+        CPU run function.
+    22. press 'RUN'  in the UI.  watch the current program run at high speed.
+    23. press 'SLOW' in the UI.  watch the current program run at slow speed.
+    24. press 'STOP' in the UI.  the program will stop execution.
+    
+        CPU test function.
+    25. press 'TEST' in the UI.  the program will load,execute,dump,compare.
+    26. tail -f testlog.txt to see test status.
+    27. the test will repeat until 'STOP TEST' is pressed.
+    28. long test performed by allowing this mode to continue.
+    
+        UI exit function.
+    29. press 'EXIT' in the UI.  it will exit.
+-----includes-----------------------------------//----------------------------*/
+    #include "mbed.h"                           // general.
+    #include "USBSerial.h"                      // serial over USB.
+    #include "C12832_lcd.h"                     // LCD display.
+    #include "rtos.h"                           // RTOS.
+    #include "mmSPI.h"                          // SPI.
+    #include "watchdog.h"                       // watchdog.
+//---defines------------------------------------//------------------------------
+    #define LCD1 lcd.locate(0, 0);              // LCD line 1.
+    #define LCD2 lcd.locate(0,11);              // LCD line 2.
+    #define LCD3 lcd.locate(0,22);              // LCD line 3.
+    #define LCD3 lcd.locate(0,22);              // LCD line 3.  
+    #define WATCHDOG_S     10                   // watchdog timeout, in seconds.
+    #define ERROR_BOOT      1                   // 1 means boot rather than error().
+    #define SPI_BYTES       8                   // number of SPI bytes. 
+    #define SPI_HZ     100000                   // SPI frequency in Hz.
+    #define SER_BYTES      18                   // serial in/out # of bytes.
+    #define SER_ALIGN       7                   // '$' location in shift-register.
+    #define THREAD_0_WAIT   8                   // multitasking wait mS.
+    #define THREAD_1_WAIT   2                   // multitasking wait mS. 
+    #define THREAD_2_WAIT 128                   // multitasking wait mS. 
+    #define THREAD_3_WAIT 128                   // multitasking wait mS.
+    #define HB_MODULO      64                   // heartbeat slowdown factor.
+    #define POOL_LEN       16                   // memory pool dimension.
+    #define HCMD_SETREG     1                   // host command 'set register'.
+    #define HCMD_GETREG     2                   // host command 'get register'.
+    #define HCMD_SETMM      3                   // host command 'set main-memory.'
+    #define HCMD_GETMM      4                   // host command 'get main-memory.'
+    #define HCMD_STEP       5                   // host command 'step-CPU'.
+    #define HCMD_SETIR      6                   // host command 'set-IR'.
+    #define HCMD_GETALLREG  7                   // host command 'get-all-registers'.
+    #define CPU_REG_0       0                   // CPU register 0.
+    #define CPU_REG_1       1                   // CPU register 1.
+    #define CPU_REG_2       2                   // CPU register 2.
+    #define CPU_REG_3       3                   // CPU register 3.
+    #define CPU_REG_PC      4                   // CPU Program Counter.
+    #define CPU_IR_H        5                   // CPU IR high-byte.
+    #define CPU_IR_L        6                   // CPU IR low-byte.
+//--externals-----------------------------------//------------------------------    
+    extern "C" void mbed_reset();               // processor reset.
+//--global_definitions--------------------------//------------------------------
+    struct tFromHost                            // command from host.
+    {
+      char cCommand;                            // command from host.
+      char cRegisterID;                         // which CPU register.
+      char cRegisterValue;                      // write this to CPU register.
+      char cIRValueH;                           // write this to IR.
+      char cIRValueL;                           // write this to IR.
+      char cMMaddress;                          // access this MM address.
+      char cMMdataH;                            // MM content high byte.
+      char cMMdataL;                            // MM content low  byte.
+    };
+    MemoryPool<tFromHost, POOL_LEN> mPoolFromHost;
+    Queue     <tFromHost, POOL_LEN> qFromHost;
+    
+//----  
+    
+    struct tToHost                              // reply to host.
+    {
+      char cCommand;                            // command executed.
+      char cRegisterID;                         // which CPU register read.
+      char cRegisterValue;                      // data from CPU register.
+      char cMMaddress;                          // which MM address read.
+      char cMMdataH;                            // MM content high byte.
+      char cMMdataL;                            // MM content low  byte.   
+      char cReg0;                               // data from R0.
+      char cReg1;                               // data from R1.
+      char cReg2;                               // data from R2.
+      char cReg3;                               // data from R3.
+      char cPC;                                 // data from program counter.
+      char cIRH;                                // high byte from instruction register.
+      char cIRL;                                // low  byte from instruction register.   
+    };
+    MemoryPool<tToHost, POOL_LEN> mPoolToHost;
+    Queue     <tToHost, POOL_LEN> qToHost;
+    
+    Queue<int, POOL_LEN> queueWatchdogThread_0; // main thread watchdog notice.
+    Queue<int, POOL_LEN> queueWatchdogThread_1; // thread 1    watchdog notice.
+    Queue<int, POOL_LEN> queueWatchdogThread_2; // thread 2    watchdog notice.
+//--global_variables----------------------------//------------------------------ 
+    char          gpcSerialFromHost[SER_BYTES]; // incoming serial buffer.
+    char          gpcSerialToHost  [SER_BYTES]; // outgoing serial buffer.
+    char          gcNewCommand;                 // new command from host.
+    int           gdRoundTrip;                  // +1 from host, -1 to host.
+    tToHost     * gpToHost;                     // to-host structure.
+    osEvent       gqToHostEvent;                // incoming message event.
+    unsigned long gulSPIclkCount;               // SPI clock count.
+    unsigned long gulCPUclkCount;               // CPU clock count.
+//--global_instances----------------------------//------------------------------ 
+    USBSerial  serial;                          // serial over usb.
+    C12832_LCD lcd;                             // LCD display.
+    DigitalOut led0(LED4);                      // thread heartbeat.
+    DigitalOut led1(LED3);                      // thread heartbeat.
+    DigitalOut led2(LED2);                      // thread heartbeat.
+    DigitalOut led3(LED1);                      // SPI reply underflow warning.
+//-------prototypes-----------------------------//------------------------------
+    int  main();                                // main.
+    void processIncomingSerial();               // process incoming host data.    
+    void processOutgoingSerial();               // process outgoing data to host.   
+    void SPIprocessingThread(void const *args); // SPI-side processing.   
+    void diagnosticThread   (void const *args); // LCD and LED notifications.  
+    void watchdogThread     (void const *args); // overall watchdog. 
+    char ascii_nibble_to_binary(char cAscii);   // ascii nibble -> binary.
+    char binary_to_ascii_nibble(char cBinary);  // binary -> ascii nibble.                
+    void clear_tFromHost(tFromHost *ptFromHost);// initialize structure.
+    void clear_tToHost  (tToHost   *ptToHost);  // initialize structure.  
+//==============================================//==============================
+    int main(void)                              // USBSerial processing thread.
+    {
+      int dHeartbeat;                           // heartbeat counter.
+      int dLoop;                                // loop index.
+
+      gpToHost       = NULL;                    // initialize global.
+      gcNewCommand   =    0;                    // initialize global.
+      gdRoundTrip    = 1024;                    // initialize global.
+      gulSPIclkCount =    0;                    // initialize global.
+      gulCPUclkCount =    0;                    // initialize global.
+      led0           =    0;                    // initialize global.
+      led1           =    0;                    // initialize global.
+      led2           =    0;                    // initialize global.
+      led3           =    0;                    // initialize global.
+      dHeartbeat     =    0;                    // initialize local.
+      dLoop          =    0;                    // initialize local.
+      
+                                                // BOOT notification.
+      lcd.cls(); LCD2; lcd.printf("           BOOT"); wait(1.0);
+
+                                                // initialize serial-in shift-register.
+      for (dLoop = 0; dLoop < SER_BYTES; dLoop++) gpcSerialFromHost[dLoop] = 0;
+      
+                                                // thread-out SPI-side processing.
+      Thread thread_1(SPIprocessingThread,NULL,osPriorityHigh,DEFAULT_STACK_SIZE,NULL);
+      
+                                                // thread-out diagnostics.
+      Thread thread_2(diagnosticThread,   NULL,osPriorityIdle,DEFAULT_STACK_SIZE,NULL);
+      
+                                                // thread-out universal watchdog.
+      Thread thread_3(watchdogThread,     NULL,osPriorityIdle,DEFAULT_STACK_SIZE,NULL);
+      
+      while(1)                                  // main loop.
+      {   
+        processIncomingSerial();                // process data in from host.
+        processOutgoingSerial();                // process data out to host.
+                        
+        dHeartbeat++;                           // thread heartbeat.
+        if (!(dHeartbeat % HB_MODULO)) led0 = !led0;
+        queueWatchdogThread_0.put((int *) 0,1); // adds 1mS to wait.
+        Thread::wait(THREAD_0_WAIT - 1);        // multitasking.   
+      }                                         // main loop.
+    }                                           // main.
+/*----------------------------------------------//----------------------------*/
+/*
+   the python program running on the host is sending/receiving ascii characters
+   which represent command/data binary nibbles.  the python program will send
+   the '$' character for command-string alignment.  this function reads-in the
+   incoming serial stream when any serial data is available, into a shift-register,
+   and breaks upon detection of the '$' alignment character for python
+   command-processing. at that point the shift-register will look something like
+   [0] [1] [2] [3] [4] [5] [6] [7]
+   '1' '2' '3' '4'  x   x   x  '$'  (means write 0x34 to CPU R2).
+
+
+    command-host register-number interpretation:
+    0 = CPU R0.
+    1 = CPU R1.
+    2 = CPU R2.
+    3 = CPU R3.
+    4 = CPU program-counter.
+    5 = CPU instruction-register high-byte.
+    6 = CPU instruction-register low-byte.
+    
+    instruction-register write is specially implemented,
+    instruction-register read  is implemented as two standard register-reads.
+
+    host-command shift-register interpretation:
+    
+    gpcSerialFromHost[0] = command.  
+    subsequent interpretation depends on the command.
+    
+----   
+    if command = HCMD_SETREG (write-CPU-register) or HCMD_GETREG (read-CPU-register):
+    
+      gpcSerialFromHost[1] = register number (see above).
+      gpcSerialFromHost[2] = register content, high nibble.
+      gpcSerialFromHost[3] = register content, low  nibble.
+      gpcSerialFromHost[4] = not used.
+      gpcSerialFromHost[5] = not used.
+      gpcSerialFromHost[6] = not used.
+
+----
+    if command = HCMD_SETIR (write-CPU-instruction-register):
+    
+      gpcSerialFromHost[1] = IR register number, implied anyway.
+      gpcSerialFromHost[2] = IR write value high byte high nibble.
+      gpcSerialFromHost[3] = IR write value high byte low  nibble.
+      gpcSerialFromHost[4] = IR write value low  byte high nibble.
+      gpcSerialFromHost[5] = IR write value low  byte low  nibble.
+      gpcSerialFromHost[6] = not used.
+
+----    
+    if command = HCMD_SETMM (write to CPU main-memory) or HCMD_GETMM (read from CPU main-memory):
+    
+      gpcSerialFromHost[1] = MM address high nibble.
+      gpcSerialFromHost[2] = MM address low  nibble.
+      gpcSerialFromHost[3] = MM content high byte high nibble.
+      gpcSerialFromHost[4] = MM content high byte low  nibble.
+      gpcSerialFromHost[5] = MM content low  byte high nibble.
+      gpcSerialFromHost[6] = MM content low  byte low  nibble.
+      
+      the above also applies to function 'processOutgoingSerial'.
+*/
+
+    void processIncomingSerial(void)            // process incoming serial data.
+    {
+      int         dLoop;                        // loop index.
+      tFromHost * pFromHost;                    // from-host structure.
+      
+      while(serial.available())                 // while data from host is available.
+      {
+                                                // shift-in the serial stream.
+        for (dLoop = 0; dLoop < (SER_BYTES - 1); dLoop++)
+        gpcSerialFromHost[dLoop] = gpcSerialFromHost[dLoop + 1];
+        gpcSerialFromHost[SER_BYTES - 1] = serial._getc();
+        
+        if (gpcSerialFromHost[SER_ALIGN] == '$')// data from host is aligned.
+        {
+          gcNewCommand = 1;                     // new host command just recognised.
+          break;                                // need to process aligned data.
+        }                                       // data from host is aligned. 
+      }                                         // while data from host is available.
+      
+                                                // even if more data awaits from the
+                                                // incoming serial stream, we now need
+                                                // to process the aligned data recognised
+                                                // as a command from the host.  
+                                                
+      if (gcNewCommand)                         // execute once per new command.
+      {
+        pFromHost = mPoolFromHost.alloc();      // allocate next pool entry.
+        if (!pFromHost)                         // failure detection.
+        {
+          if (ERROR_BOOT) mbed_reset(); else
+          error("\n\r processIncomingSerial : FATAL malloc error for pFromHost. \n\r"); 
+        }
+        
+        clear_tFromHost(pFromHost);             // initialize structure.
+        
+                                                // copy-in host message.
+        pFromHost->cCommand = ascii_nibble_to_binary(gpcSerialFromHost[0]);
+        
+//----
+
+        switch(pFromHost->cCommand)             // command dependency.
+        {
+          case HCMD_SETREG :                    // host command 'set register'.
+          {
+            pFromHost->cRegisterID    =   ascii_nibble_to_binary(gpcSerialFromHost[1]);
+            pFromHost->cRegisterValue = ((ascii_nibble_to_binary(gpcSerialFromHost[2])) << 4) + 
+                                          ascii_nibble_to_binary(gpcSerialFromHost[3]);          
+            break;
+          }                                     // host command 'set register'.
+        
+          case HCMD_GETREG :                    // host command 'get register'.
+          {
+            pFromHost->cRegisterID    =   ascii_nibble_to_binary(gpcSerialFromHost[1]);
+            pFromHost->cRegisterValue = ((ascii_nibble_to_binary(gpcSerialFromHost[2])) << 4) + 
+                                          ascii_nibble_to_binary(gpcSerialFromHost[3]);   
+            gdRoundTrip++;                      // expected reply to host is pending.       
+            break;
+          }                                     // host command 'get register'.
+                 
+          case HCMD_SETMM :                     // host command 'set main-memory.'
+          {
+            pFromHost->cMMaddress = ((ascii_nibble_to_binary(gpcSerialFromHost[1])) << 4) + 
+                                      ascii_nibble_to_binary(gpcSerialFromHost[2]);  
+            pFromHost->cMMdataH   = ((ascii_nibble_to_binary(gpcSerialFromHost[3])) << 4) + 
+                                      ascii_nibble_to_binary(gpcSerialFromHost[4]);         
+            pFromHost->cMMdataL   = ((ascii_nibble_to_binary(gpcSerialFromHost[5])) << 4) + 
+                                      ascii_nibble_to_binary(gpcSerialFromHost[6]);           
+            break;
+          }                                     // host command 'set main-memory.'
+               
+          case HCMD_GETMM :                     // host command 'get main-memory.'
+          {
+            pFromHost->cMMaddress = ((ascii_nibble_to_binary(gpcSerialFromHost[1])) << 4) + 
+                                      ascii_nibble_to_binary(gpcSerialFromHost[2]);  
+            pFromHost->cMMdataH   = ((ascii_nibble_to_binary(gpcSerialFromHost[3])) << 4) + 
+                                      ascii_nibble_to_binary(gpcSerialFromHost[4]);         
+            pFromHost->cMMdataL   = ((ascii_nibble_to_binary(gpcSerialFromHost[5])) << 4) + 
+                                      ascii_nibble_to_binary(gpcSerialFromHost[6]);    
+                                      
+            gdRoundTrip++;                      // expected reply to host is pending.        
+            break;
+          }                                     // host command 'get main-memory.'
+                
+          case HCMD_STEP :                      // host command 'step-CPU'.
+          {
+            break;
+          }                                     // host command 'step-CPU'.
+            
+          case HCMD_SETIR :                     // host command 'set-IR'.
+          {
+            pFromHost->cIRValueH = ((ascii_nibble_to_binary(gpcSerialFromHost[2])) << 4) + 
+                                     ascii_nibble_to_binary(gpcSerialFromHost[3]);     
+            pFromHost->cIRValueL = ((ascii_nibble_to_binary(gpcSerialFromHost[4])) << 4) + 
+                                     ascii_nibble_to_binary(gpcSerialFromHost[5]);            
+            break;
+          }                                     // host command 'set-IR'.
+            
+          case HCMD_GETALLREG :                 // host command 'get-all-registers'.
+          {
+            gdRoundTrip++;                      // expected reply to host is pending.
+            break;
+          }                                     // host command 'get-all-registers'.
+        
+          default :                             // default.
+          {
+            if (ERROR_BOOT) mbed_reset(); else
+            error("\n\r processIncomingSerial : ERROR unrecognised command from host. \n\r");
+            break;
+          }                                     // default.
+        }                                       // command dependency.
+        
+//----
+                   
+        qFromHost.put(pFromHost);               // send out for processing.    
+        gcNewCommand = 0;                       // don't execute until next new command.
+      }                                         // execute once per new command.
+      Thread::wait(THREAD_0_WAIT);              // multitasking.  
+    }                                           // processIncomingSerial
+/*----------------------------------------------//----------------------------*/
+    void processOutgoingSerial(void)            // prepare/transmit data to host.
+    {
+      int dLoop;                                // loop index.
+
+      gqToHostEvent = qToHost.get(1);           // check for reply back to host.
+          
+                                                // if new reply to host:
+      if (gqToHostEvent.status == osEventMessage) 
+      {
+                                                // bring it in from the queue.
+        gpToHost = (tToHost *) gqToHostEvent.value.p;
+        if (!gpToHost)                         // failure detection.
+        {
+          if (ERROR_BOOT) mbed_reset(); else
+          error("\n\r processOutgoingSerial : FATAL NULL gpToHost pointer. \n\r"); 
+        }
+          
+                                                // clear outgoing buffer.
+        for (dLoop = 0; dLoop < SER_BYTES; dLoop++) gpcSerialToHost[dLoop] = 0;
+                                                                                                           
+        switch(gpToHost->cCommand)              // the from-host command was looped to here.
+        {
+          case HCMD_SETREG :                    // host command 'set register'.
+          {
+            break;
+          }                                     // host command 'set register'.
+        
+          case HCMD_GETREG :                    // host command 'get register'.
+          {
+            gpcSerialToHost[0] = binary_to_ascii_nibble(  gpToHost->cCommand);
+            gpcSerialToHost[1] = binary_to_ascii_nibble(  gpToHost->cRegisterID);
+            gpcSerialToHost[2] = binary_to_ascii_nibble(((gpToHost->cRegisterValue) >> 4) & 0x0F);
+            gpcSerialToHost[3] = binary_to_ascii_nibble(((gpToHost->cRegisterValue) >> 0) & 0x0F);
+            gpcSerialToHost[4] = '\n';          // signals end of transfer.
+             
+                                                // transmit to the host.
+            serial.writeBlock((uint8_t *) gpcSerialToHost, (uint16_t) SER_BYTES);        
+            gdRoundTrip--;                      // expected reply sent to host.       
+            break;
+          }                                     // host command 'get register'.
+                 
+          case HCMD_SETMM :                     // host command 'set main-memory.'
+          {
+            break;
+          }                                     // host command 'set main-memory.'
+               
+          case HCMD_GETMM :                     // host command 'get main-memory.'
+          {
+            gpcSerialToHost[0] = binary_to_ascii_nibble(  gpToHost->cCommand);
+            gpcSerialToHost[1] = binary_to_ascii_nibble(((gpToHost->cMMaddress) >> 4) & 0x0F);
+            gpcSerialToHost[2] = binary_to_ascii_nibble(((gpToHost->cMMaddress) >> 0) & 0x0F);
+            gpcSerialToHost[3] = binary_to_ascii_nibble(((gpToHost->cMMdataH  ) >> 4) & 0x0F);
+            gpcSerialToHost[4] = binary_to_ascii_nibble(((gpToHost->cMMdataH  ) >> 0) & 0x0F);
+            gpcSerialToHost[5] = binary_to_ascii_nibble(((gpToHost->cMMdataL  ) >> 4) & 0x0F);
+            gpcSerialToHost[6] = binary_to_ascii_nibble(((gpToHost->cMMdataL  ) >> 0) & 0x0F);   
+            gpcSerialToHost[7] = '\n';          // signals end of transfer.    
+             
+                                                // transmit to the host.
+            serial.writeBlock((uint8_t *) gpcSerialToHost, (uint16_t) SER_BYTES);    
+            gdRoundTrip--;                      // expected reply sent to host.        
+            break;
+          }                                     // host command 'get main-memory.'
+                
+          case HCMD_STEP :                      // host command 'step-CPU'.
+          {
+            break;
+          }                                     // host command 'step-CPU'.
+            
+          case HCMD_SETIR :                     // host command 'set-IR'.
+          {
+            break;
+          }                                     // host command 'set-IR'.
+            
+          case HCMD_GETALLREG :                 // host command 'get-all-registers'.
+          {
+            gpcSerialToHost[ 0] = binary_to_ascii_nibble(  gpToHost->cCommand);
+            gpcSerialToHost[ 1] = binary_to_ascii_nibble(((gpToHost->cReg0) >> 4) & 0x0F);
+            gpcSerialToHost[ 2] = binary_to_ascii_nibble(((gpToHost->cReg0) >> 0) & 0x0F);
+            gpcSerialToHost[ 3] = binary_to_ascii_nibble(((gpToHost->cReg1) >> 4) & 0x0F);
+            gpcSerialToHost[ 4] = binary_to_ascii_nibble(((gpToHost->cReg1) >> 0) & 0x0F);
+            gpcSerialToHost[ 5] = binary_to_ascii_nibble(((gpToHost->cReg2) >> 4) & 0x0F);
+            gpcSerialToHost[ 6] = binary_to_ascii_nibble(((gpToHost->cReg2) >> 0) & 0x0F);
+            gpcSerialToHost[ 7] = binary_to_ascii_nibble(((gpToHost->cReg3) >> 4) & 0x0F);
+            gpcSerialToHost[ 8] = binary_to_ascii_nibble(((gpToHost->cReg3) >> 0) & 0x0F);
+            gpcSerialToHost[ 9] = binary_to_ascii_nibble(((gpToHost->cPC)   >> 4) & 0x0F);
+            gpcSerialToHost[10] = binary_to_ascii_nibble(((gpToHost->cPC)   >> 0) & 0x0F);
+            gpcSerialToHost[11] = binary_to_ascii_nibble(((gpToHost->cIRH)  >> 4) & 0x0F);
+            gpcSerialToHost[12] = binary_to_ascii_nibble(((gpToHost->cIRH)  >> 0) & 0x0F);          
+            gpcSerialToHost[13] = binary_to_ascii_nibble(((gpToHost->cIRL)  >> 4) & 0x0F);
+            gpcSerialToHost[14] = binary_to_ascii_nibble(((gpToHost->cIRL)  >> 0) & 0x0F);                 
+            gpcSerialToHost[15] = '\n';         // signals end of transfer.         
+          
+                                                // transmit to the host.
+            serial.writeBlock((uint8_t *) gpcSerialToHost, (uint16_t) SER_BYTES);        
+            gdRoundTrip--;                      // expected reply sent to host.  
+            break;
+          }                                     // host command 'get-all-registers'.
+        
+          default :
+          {
+            if (ERROR_BOOT) mbed_reset(); else
+            error("\n\r processOutgoingSerial : ERROR unrecognised command from host. \n\r");
+            break;
+          }                                     // default.
+        }                                       // switch(gpToHost->cCommand)                                         
+                                                
+        mPoolToHost.free(gpToHost);             // done with this queue entry.
+        gpToHost = NULL;                        // clear pointer.
+      }                                         // if new reply to host.     
+    }                                           // processOutgoingSerial.
+/*----------------------------------------------//----------------------------*/      
+//  the pcSendBuffer and pcReceiveBuffer arrays are not used by this function,
+//  but they are declared by this function, and their pointers are passed
+//  down to the mmSPI library for its use of them.
+//  note- the prefix 'pc' means 'pointer of type character', not 'personal computer'.
+
+    void SPIprocessingThread(void const *args)  // process host-commands via SPI.
+    {
+      char        pcSendBuffer   [SPI_BYTES];   // SPI send buffer.
+      char        pcReceiveBuffer[SPI_BYTES];   // SPI receive buffer.
+      char        pcRegisters    [SPI_BYTES];   // fetch-all-registers vector.
+      int         dHeartbeat;                   // heartbeat counter.
+      int         dMemoryRead;                  // read main-memory into this.
+      int         dLoop;                        // loop index.
+      osEvent     qFromHostEvent;               // incoming message event.
+      tFromHost * pFromHost;                    // message structure.
+      tToHost   * gpToHost;                     // message structure.
+      mmSPI     * pSPI;                         // SPI.
+      
+      pFromHost   = NULL;                       // NULL pointers.
+      gpToHost    = NULL;
+      pSPI        = NULL;
+      dHeartbeat  = 0;                          // clear variables.
+      dMemoryRead = 0;
+      dLoop       = 0;
+                                                // clear SPI vectors.
+      for (dLoop = 0; dLoop < SPI_BYTES; dLoop++) pcSendBuffer   [dLoop] = 0;
+      for (dLoop = 0; dLoop < SPI_BYTES; dLoop++) pcReceiveBuffer[dLoop] = 0;
+ 
+      pSPI = new mmSPI;                         // SPI allocation.      
+      if (!pSPI)                                // failure detection.
+      {
+        if (ERROR_BOOT) mbed_reset(); else
+        error("\n\r SPIprocessingThread : FATAL new error for pSPI. \n\r"); 
+      }      
+      
+      pSPI->setSendBuffer   (pcSendBuffer);     // set SPI send buffer.
+      pSPI->setReceiveBuffer(pcReceiveBuffer);  // set SPI receive buffer.
+      pSPI->setNumberOfBytes(SPI_BYTES);        // set SPI number of bytes.
+      pSPI->setSPIfrequency (SPI_HZ);           // set SPI clock frequency.
+      
+      while(1)                                  // thread loop.
+      {
+        qFromHostEvent = qFromHost.get(1);      // check for incoming host command.
+        
+                                                // if new host command:
+        if (qFromHostEvent.status == osEventMessage) 
+        {
+                                                // bring it in from the queue.
+          pFromHost = (tFromHost *) qFromHostEvent.value.p;
+          if (!pFromHost)                       // failure detection.
+          {
+            if (ERROR_BOOT) mbed_reset(); else
+            error("\n\r SPIprocessingThread : FATAL NULL pFromHost pointer. \n\r");  
+          }
+          
+          switch(pFromHost->cCommand)           // host command decode.
+          {
+            case HCMD_SETREG :                  // set CPU register.
+            {
+              switch(pFromHost->cRegisterID)    // which register to write to.
+              {
+                case CPU_REG_0  : {pSPI->write_register(CPU_REG_0 , pFromHost->cRegisterValue); break;}
+                case CPU_REG_1  : {pSPI->write_register(CPU_REG_1 , pFromHost->cRegisterValue); break;}
+                case CPU_REG_2  : {pSPI->write_register(CPU_REG_2 , pFromHost->cRegisterValue); break;}
+                case CPU_REG_3  : {pSPI->write_register(CPU_REG_3 , pFromHost->cRegisterValue); break;}
+                case CPU_REG_PC : {pSPI->write_register(CPU_REG_PC, pFromHost->cRegisterValue); break;}
+                default         : {break;}
+              }                                 // which register to write to.
+              break;
+            }                                   // set CPU register.
+            
+            case HCMD_SETIR:                    // set instruction register.
+            {
+              pSPI->write_IR(pFromHost->cIRValueH, pFromHost->cIRValueL);
+              break;
+            }                                   // set instruction register.
+            
+            case HCMD_GETREG :                  // get CPU register.
+            {
+              gpToHost = mPoolToHost.alloc();   // allocate next pool entry.
+              if (!gpToHost)                    // failure detection.
+              {
+                if (ERROR_BOOT) mbed_reset(); else
+                error("\n\r SPIprocessingThread : FATAL malloc error for gpToHost. \n\r"); 
+              }              
+              
+              clear_tToHost(gpToHost);          // initialize structure.
+            
+              switch(pFromHost->cRegisterID)    // which register to read from.
+              {
+                case CPU_REG_0  : {gpToHost->cRegisterValue = pSPI->read_register(CPU_REG_0 ); break;}
+                case CPU_REG_1  : {gpToHost->cRegisterValue = pSPI->read_register(CPU_REG_1 ); break;}
+                case CPU_REG_2  : {gpToHost->cRegisterValue = pSPI->read_register(CPU_REG_2 ); break;}
+                case CPU_REG_3  : {gpToHost->cRegisterValue = pSPI->read_register(CPU_REG_3 ); break;}
+                case CPU_REG_PC : {gpToHost->cRegisterValue = pSPI->read_register(CPU_REG_PC); break;}
+                case CPU_IR_H   : {gpToHost->cRegisterValue = pSPI->read_register(CPU_IR_H  ); break;}
+                case CPU_IR_L   : {gpToHost->cRegisterValue = pSPI->read_register(CPU_IR_L  ); break;}
+                default         : {break;}    
+              }                                 // which register to read from.
+              
+                                                // loop-back to host.
+              gpToHost->cCommand    = pFromHost->cCommand;
+              gpToHost->cRegisterID = pFromHost->cRegisterID;  
+                          
+              qToHost.put(gpToHost);            // send up for processing.    
+              break; 
+            }                                   // get CPU register.     
+            
+            case HCMD_GETALLREG :               // get all CPU registers.
+            {
+              gpToHost = mPoolToHost.alloc();   // allocate next pool entry.              
+              if (!gpToHost)                    // failure detection.
+              {
+                if (ERROR_BOOT) mbed_reset(); else
+                error("\n\r SPIprocessingThread : FATAL malloc error for gpToHost. \n\r");
+              }              
+              
+              clear_tToHost(gpToHost);          // initialize structure.
+              
+                                                // tell SPI to return all reg content.
+              pSPI->read_all_registers(pcRegisters);
+              
+              gpToHost->cReg0 = pcRegisters[6]; // transfer to outgoing structure.
+              gpToHost->cReg1 = pcRegisters[5];
+              gpToHost->cReg2 = pcRegisters[4];
+              gpToHost->cReg3 = pcRegisters[3];
+              gpToHost->cPC   = pcRegisters[2];
+              gpToHost->cIRH  = pcRegisters[1];
+              gpToHost->cIRL  = pcRegisters[0];
+              
+                                                // loop-back to host.
+              gpToHost->cCommand = pFromHost->cCommand;
+              qToHost.put(gpToHost);            // send up for processing. 
+              
+              break;
+            }                                   // get all CPU registers.
+            
+            case HCMD_SETMM  :                  // do main-memory write.
+            {
+              pSPI->write_memory(pFromHost->cMMdataH, pFromHost->cMMdataL, pFromHost->cMMaddress);     
+              break;
+            }                                   // do main-memory write.                   
+            
+            case HCMD_GETMM  :                  // do main-memory read.
+            {
+              gpToHost = mPoolToHost.alloc();   // allocate next pool entry.   
+              if (!gpToHost)                    // failure detection.
+              {
+                if (ERROR_BOOT) mbed_reset(); else
+                error("\n\r SPIprocessingThread : FATAL malloc error for gpToHost. \n\r"); 
+              }              
+              
+              clear_tToHost(gpToHost);          // initialize structure.
+            
+                                                // read from CPU memory.
+              dMemoryRead = pSPI->read_memory(pFromHost->cMMaddress); 
+              gpToHost->cMMdataH = (dMemoryRead >> 8) & 0xFF;
+              gpToHost->cMMdataL = (dMemoryRead >> 0) & 0xFF;
+              
+                                                // loop-back to host.
+              gpToHost->cCommand   = pFromHost->cCommand;
+              gpToHost->cMMaddress = pFromHost->cMMaddress;
+                      
+              qToHost.put(gpToHost);            // send up for processing.
+              break;
+            }                                   // do main-memory read.
+            
+            case HCMD_STEP   :                  // step the CPU.
+            {
+              pSPI->step();
+              break;
+            }                                   // step the CPU.
+            default          : break;
+          }                                     // host command decode.            
+          mPoolFromHost.free(pFromHost);        // done with this queue entry.
+          pFromHost = NULL;                     // clear pointer.
+        }                                       // if new host command.
+        
+        gulSPIclkCount = pSPI->SPIClockCount(); // propagate to global variable.
+        gulCPUclkCount = pSPI->CPUClockCount(); // propagate to global variable.
+ 
+                                                // thread heartbeat.
+        dHeartbeat++; if (!(dHeartbeat % HB_MODULO)) led1 = !led1;
+        queueWatchdogThread_1.put((int *) 0,1); // adds 1mS to wait.
+        Thread::wait(THREAD_1_WAIT - 1);        // cooperative multitasking.      
+      }                                         // thread loop.
+    }                                           // SPIprocessingThread.
+/*----------------------------------------------//----------------------------*/
+    void diagnosticThread(void const *args)     // LCD notification & error check.
+    {
+                                                // track previous values.
+      static unsigned long ulLastSPIclkCount = 1;      
+      static unsigned long ulLastCPUclkCount = 1;
+      int                  dHeartbeat;          // heartbeat counter.
+      
+      dHeartbeat = 0;                           // initialize.
+            
+      while(1)                                  // thread loop.
+      {
+                                                // if message round trip 
+                                                // count not consistent.
+        if (gdRoundTrip > 1025 || gdRoundTrip < 1024)
+        {
+          if (ERROR_BOOT) mbed_reset(); else
+          error("\n\r diagnosticThread : ERROR serial reply underflow. \n\r");         
+        }
+        
+                                                // update LCD only if a display
+                                                // value has changed.  anti-blink,
+                                                // save a bit of power.
+        if (gulSPIclkCount != ulLastSPIclkCount ||
+            gulCPUclkCount != ulLastCPUclkCount   )
+        {
+          lcd.cls();                            // clear LCD display.
+          LCD1;                                 // lcd line 1.
+          lcd.printf(" RTOS CLASS PROJECT");
+        
+          LCD2;                                 // lcd line 2.
+          lcd.printf(" %11lu = SPI clocks",gulSPIclkCount);
+        
+          LCD3;                                 // lcd line 3.
+          lcd.printf(" %11lu = CPU clocks",gulCPUclkCount);
+        }
+        
+        ulLastSPIclkCount = gulSPIclkCount;     // pipeline.
+        ulLastCPUclkCount = gulCPUclkCount;     // pipeline.
+       
+        dHeartbeat++;                           // thread heartbeat.
+        if (!(dHeartbeat % HB_MODULO)) led2 = !led2;
+        queueWatchdogThread_2.put((int *) 0,1); // adds 1mS to wait.
+        Thread::wait(THREAD_2_WAIT - 1);        // multitasking.
+      }                                         // thread loop.
+    }                                           // diagnosticThread.
+/*----------------------------------------------//----------------------------*/
+                                                // this is its own watchdog.
+
+    void watchdogThread(void const *args)       // overall watchdog.
+    {
+      int      dHeartbeat;                      // heartbeat counter.
+      osEvent  queueEvent;                      // queue event
+      Watchdog watchdog;                        // the one and only watchdog.
+      
+      dHeartbeat = 0;                           // initialize.
+
+      watchdog.kick(WATCHDOG_S);                // initialize watchdog.
+    
+      while (1)                                 // thread loop.
+      {
+                                                // all other threads report-in.
+                                                // blocking wait on all of them.
+        queueEvent = queueWatchdogThread_0.get(osWaitForever); 
+        queueEvent = queueWatchdogThread_1.get(osWaitForever);
+        queueEvent = queueWatchdogThread_2.get(osWaitForever);  
+
+        watchdog.kick();                        // reset watchdog timer.
+        
+        dHeartbeat++;                           // thread heartbeat.
+        if (!(dHeartbeat % HB_MODULO)) led3 = !led3;
+        Thread::wait(THREAD_3_WAIT);            // multitasking.
+      }                                         // thread loop.
+    }
+/*----------------------------------------------//----------------------------*/
+    char ascii_nibble_to_binary(char cAscii)    // ascii nibble -> binary.
+    {
+      char cBinary;                             // converted value.
+      
+      switch(cAscii)
+      {
+        case 'F' : {cBinary = 15; break;}
+        case 'E' : {cBinary = 14; break;}
+        case 'D' : {cBinary = 13; break;}
+        case 'C' : {cBinary = 12; break;}
+        case 'B' : {cBinary = 11; break;}
+        case 'A' : {cBinary = 10; break;}
+        case 'f' : {cBinary = 15; break;}
+        case 'e' : {cBinary = 14; break;}
+        case 'd' : {cBinary = 13; break;}
+        case 'c' : {cBinary = 12; break;}
+        case 'b' : {cBinary = 11; break;}
+        case 'a' : {cBinary = 10; break;}
+        case '9' : {cBinary =  9; break;}
+        case '8' : {cBinary =  8; break;}
+        case '7' : {cBinary =  7; break;}
+        case '6' : {cBinary =  6; break;}
+        case '5' : {cBinary =  5; break;}
+        case '4' : {cBinary =  4; break;}
+        case '3' : {cBinary =  3; break;}
+        case '2' : {cBinary =  2; break;}
+        case '1' : {cBinary =  1; break;}
+        case '0' : {cBinary =  0; break;}
+        default  : {cBinary =  0; break;}
+      }                                         // switch(cAscii).
+      return(cBinary);                          // return the binary.
+    }                                           // ascii_nibble_to_binary.
+/*----------------------------------------------//----------------------------*/
+    char binary_to_ascii_nibble(char cBinary)   // binary -> ascii nibble.
+    {
+      char cAscii;                              // converted value.
+      
+      switch(cBinary)
+      {
+        case 15 : {cAscii = 'F'; break;}
+        case 14 : {cAscii = 'E'; break;}
+        case 13 : {cAscii = 'D'; break;}
+        case 12 : {cAscii = 'C'; break;}
+        case 11 : {cAscii = 'B'; break;}
+        case 10 : {cAscii = 'A'; break;}
+        case  9 : {cAscii = '9'; break;}
+        case  8 : {cAscii = '8'; break;}
+        case  7 : {cAscii = '7'; break;}
+        case  6 : {cAscii = '6'; break;}
+        case  5 : {cAscii = '5'; break;}
+        case  4 : {cAscii = '4'; break;}
+        case  3 : {cAscii = '3'; break;}
+        case  2 : {cAscii = '2'; break;}
+        case  1 : {cAscii = '1'; break;}
+        case  0 : {cAscii = '0'; break;}
+        default : {cAscii = '0'; break;}
+      }                                         // switch(cBinary).
+      return(cAscii);                           // return the binary.
+    }                                           // binary_to_ascii_nibble.
+/*----------------------------------------------//----------------------------*/
+    void clear_tFromHost(tFromHost * ptFromHost)// clear structure.
+    {
+      ptFromHost->cCommand       = 0x00;
+      ptFromHost->cRegisterID    = 0x00;
+      ptFromHost->cRegisterValue = 0x00;
+      ptFromHost->cIRValueH      = 0x00;
+      ptFromHost->cIRValueL      = 0x00;
+      ptFromHost->cMMaddress     = 0x00;
+      ptFromHost->cMMdataH       = 0x00;
+      ptFromHost->cMMdataL       = 0x00;
+    }                                           // clear_tFromHost.
+/*----------------------------------------------//----------------------------*/
+    void clear_tToHost(tToHost * ptToHost)      // clear structure.
+    {
+      ptToHost->cCommand       = 0x00;
+      ptToHost->cRegisterID    = 0x00;
+      ptToHost->cRegisterValue = 0x00;
+      ptToHost->cMMaddress     = 0x00;
+      ptToHost->cMMdataH       = 0x00;
+      ptToHost->cMMdataL       = 0x00;
+    }                                           // clear_tToHost.
+/*----------------------------------------------//----------------------------*/
\ No newline at end of file
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-rtos.lib	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,1 @@
+http://mbed.org/users/mbed_official/code/mbed-rtos/#869ef732a8a2
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed.bld	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,1 @@
+http://mbed.org/users/mbed_official/code/mbed/builds/9c8f0e3462fb
\ No newline at end of file
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmCPUassemblySource/prog_add_list.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,256 @@
+  0x00  0xADD0  ; R3 gets 0xD0 immediate.  ** ====================== 0x*0
+  0x01  0xC500  ; R1 gets mm[R3].
+  0x02  0x2100  ; R0 gets R1.
+  0x03  0xADE0  ; R3 gets 0xE0 immediate.  **
+  0x04  0xC500  ; R1 gets mm[R3].
+  0x05  0x0900  ; R2 gets R0.
+  0x06  0xC100  ; R0 gets R1 + R2.
+  0x07  0xADF0  ; R3 gets 0xF0 immediate.  **
+  0x08  0xA900  ; R2 gets 0x00 immediate.
+  0x09  0x0500  ; R1 gets R0.
+  0x0a  0x0300  ; WE goes high.
+  0x0b  0x0100  ; WE goes low.
+  0x0c  0xADD1  ; R3 gets 0xD1 immediate.  ** ====================== 0x*1
+  0x0d  0xC500  ; R1 gets mm[R3].
+  0x0e  0x2100  ; R0 gets R1.
+  0x0f  0xADE1  ; R3 gets 0xE1 immediate.  **
+  0x10  0xC500  ; R1 gets mm[R3].
+  0x11  0x0900  ; R2 gets R0.
+  0x12  0xC100  ; R0 gets R1 + R2.
+  0x13  0xADF1  ; R3 gets 0xF1 immediate.  **
+  0x14  0xA900  ; R2 gets 0x00 immediate.
+  0x15  0x0500  ; R1 gets R0.
+  0x16  0x0300  ; WE goes high.
+  0x17  0x0100  ; WE goes low.
+  0x18  0xADD2  ; R3 gets 0xD2 immediate.  ** ====================== 0x*2
+  0x19  0xC500  ; R1 gets mm[R3].
+  0x1a  0x2100  ; R0 gets R1.
+  0x1b  0xADE2  ; R3 gets 0xE2 immediate.  **
+  0x1c  0xC500  ; R1 gets mm[R3].
+  0x1d  0x0900  ; R2 gets R0.
+  0x1e  0xC100  ; R0 gets R1 + R2.
+  0x1f  0xADF2  ; R3 gets 0xF2 immediate.  **
+  0x20  0xA900  ; R2 gets 0x00 immediate.
+  0x21  0x0500  ; R1 gets R0.
+  0x22  0x0300  ; WE goes high.
+  0x23  0x0100  ; WE goes low.
+  0x24  0xADD3  ; R3 gets 0xD3 immediate.  ** ====================== 0x*3
+  0x25  0xC500  ; R1 gets mm[R3].
+  0x26  0x2100  ; R0 gets R1.
+  0x27  0xADE3  ; R3 gets 0xE3 immediate.  **
+  0x28  0xC500  ; R1 gets mm[R3].
+  0x29  0x0900  ; R2 gets R0.
+  0x2a  0xC100  ; R0 gets R1 + R2.
+  0x2b  0xADF3  ; R3 gets 0xF3 immediate.  **
+  0x2c  0xA900  ; R2 gets 0x00 immediate.
+  0x2d  0x0500  ; R1 gets R0.
+  0x2e  0x0300  ; WE goes high.
+  0x2f  0x0100  ; WE goes low.
+  0x30  0xADD4  ; R3 gets 0xD4 immediate.  ** ====================== 0x*4
+  0x31  0xC500  ; R1 gets mm[R3].
+  0x32  0x2100  ; R0 gets R1.
+  0x33  0xADE4  ; R3 gets 0xE4 immediate.  **
+  0x34  0xC500  ; R1 gets mm[R3].
+  0x35  0x0900  ; R2 gets R0.
+  0x36  0xC100  ; R0 gets R1 + R2.
+  0x37  0xADF4  ; R3 gets 0xF4 immediate.  **
+  0x38  0xA900  ; R2 gets 0x00 immediate.
+  0x39  0x0500  ; R1 gets R0.
+  0x3a  0x0300  ; WE goes high.
+  0x3b  0x0100  ; WE goes low.
+  0x3c  0xADD5  ; R3 gets 0xD5 immediate.  ** ====================== 0x*5
+  0x3d  0xC500  ; R1 gets mm[R3].
+  0x3e  0x2100  ; R0 gets R1.
+  0x3f  0xADE5  ; R3 gets 0xE5 immediate.  **
+  0x40  0xC500  ; R1 gets mm[R3].
+  0x41  0x0900  ; R2 gets R0.
+  0x42  0xC100  ; R0 gets R1 + R2.
+  0x43  0xADF5  ; R3 gets 0xF5 immediate.  **
+  0x44  0xA900  ; R2 gets 0x00 immediate.
+  0x45  0x0500  ; R1 gets R0.
+  0x46  0x0300  ; WE goes high.
+  0x47  0x0100  ; WE goes low.
+  0x48  0xADD6  ; R3 gets 0xD6 immediate.  ** ====================== 0x*6
+  0x49  0xC500  ; R1 gets mm[R3].
+  0x4a  0x2100  ; R0 gets R1.
+  0x4b  0xADE6  ; R3 gets 0xE6 immediate.  **
+  0x4c  0xC500  ; R1 gets mm[R3].
+  0x4d  0x0900  ; R2 gets R0.
+  0x4e  0xC100  ; R0 gets R1 + R2.
+  0x4f  0xADF6  ; R3 gets 0xF6 immediate.  **
+  0x50  0xA900  ; R2 gets 0x00 immediate.
+  0x51  0x0500  ; R1 gets R0.
+  0x52  0x0300  ; WE goes high.
+  0x53  0x0100  ; WE goes low.
+  0x54  0xADD7  ; R3 gets 0xD7 immediate.  ** ====================== 0x*7
+  0x55  0xC500  ; R1 gets mm[R3].
+  0x56  0x2100  ; R0 gets R1.
+  0x57  0xADE7  ; R3 gets 0xE7 immediate.  **
+  0x58  0xC500  ; R1 gets mm[R3].
+  0x59  0x0900  ; R2 gets R0.
+  0x5a  0xC100  ; R0 gets R1 + R2.
+  0x5b  0xADF7  ; R3 gets 0xF7 immediate.  **
+  0x5c  0xA900  ; R2 gets 0x00 immediate.
+  0x5d  0x0500  ; R1 gets R0.
+  0x5e  0x0300  ; WE goes high.
+  0x5f  0x0100  ; WE goes low.
+  0x60  0xADD8  ; R3 gets 0xD8 immediate.  ** ====================== 0x*8
+  0x61  0xC500  ; R1 gets mm[R3].
+  0x62  0x2100  ; R0 gets R1.
+  0x63  0xADE8  ; R3 gets 0xE8 immediate.  **
+  0x64  0xC500  ; R1 gets mm[R3].
+  0x65  0x0900  ; R2 gets R0.
+  0x66  0xC100  ; R0 gets R1 + R2.
+  0x67  0xADF8  ; R3 gets 0xF8 immediate.  **
+  0x68  0xA900  ; R2 gets 0x00 immediate.
+  0x69  0x0500  ; R1 gets R0.
+  0x6a  0x0300  ; WE goes high.
+  0x6b  0x0100  ; WE goes low.
+  0x6c  0xADD9  ; R3 gets 0xD9 immediate.  ** ====================== 0x*9
+  0x6d  0xC500  ; R1 gets mm[R3].
+  0x6e  0x2100  ; R0 gets R1.
+  0x6f  0xADE9  ; R3 gets 0xE9 immediate.  **
+  0x70  0xC500  ; R1 gets mm[R3].
+  0x71  0x0900  ; R2 gets R0.
+  0x72  0xC100  ; R0 gets R1 + R2.
+  0x73  0xADF9  ; R3 gets 0xF9 immediate.  **
+  0x74  0xA900  ; R2 gets 0x00 immediate.
+  0x75  0x0500  ; R1 gets R0.
+  0x76  0x0300  ; WE goes high.
+  0x77  0x0100  ; WE goes low.
+  0x78  0xADDA  ; R3 gets 0xDA immediate.  ** ====================== 0x*A
+  0x79  0xC500  ; R1 gets mm[R3].
+  0x7a  0x2100  ; R0 gets R1.
+  0x7b  0xADEA  ; R3 gets 0xEA immediate.  **
+  0x7c  0xC500  ; R1 gets mm[R3].
+  0x7d  0x0900  ; R2 gets R0.
+  0x7e  0xC100  ; R0 gets R1 + R2.
+  0x7f  0xADFA  ; R3 gets 0xFA immediate.  **
+  0x80  0xA900  ; R2 gets 0x00 immediate.
+  0x81  0x0500  ; R1 gets R0.
+  0x82  0x0300  ; WE goes high.
+  0x83  0x0100  ; WE goes low.
+  0x84  0xADDB  ; R3 gets 0xDB immediate.  ** ====================== 0x*B
+  0x85  0xC500  ; R1 gets mm[R3].
+  0x86  0x2100  ; R0 gets R1.
+  0x87  0xADEB  ; R3 gets 0xEB immediate.  **
+  0x88  0xC500  ; R1 gets mm[R3].
+  0x89  0x0900  ; R2 gets R0.
+  0x8a  0xC100  ; R0 gets R1 + R2.
+  0x8b  0xADFB  ; R3 gets 0xFB immediate.  **
+  0x8c  0xA900  ; R2 gets 0x00 immediate.
+  0x8d  0x0500  ; R1 gets R0.
+  0x8e  0x0300  ; WE goes high.
+  0x8f  0x0100  ; WE goes low.
+  0x90  0xADDC  ; R3 gets 0xDC immediate.  ** ====================== 0x*C
+  0x91  0xC500  ; R1 gets mm[R3].
+  0x92  0x2100  ; R0 gets R1.
+  0x93  0xADEC  ; R3 gets 0xEC immediate.  **
+  0x94  0xC500  ; R1 gets mm[R3].
+  0x95  0x0900  ; R2 gets R0.
+  0x96  0xC100  ; R0 gets R1 + R2.
+  0x97  0xADFC  ; R3 gets 0xFC immediate.  **
+  0x98  0xA900  ; R2 gets 0x00 immediate.
+  0x99  0x0500  ; R1 gets R0.
+  0x9a  0x0300  ; WE goes high.
+  0x9b  0x0100  ; WE goes low.
+  0x9c  0xADDD  ; R3 gets 0xDD immediate.  ** ====================== 0x*D
+  0x9d  0xC500  ; R1 gets mm[R3].
+  0x9e  0x2100  ; R0 gets R1.
+  0x9f  0xADED  ; R3 gets 0xED immediate.  **
+  0xa0  0xC500  ; R1 gets mm[R3].
+  0xa1  0x0900  ; R2 gets R0.
+  0xa2  0xC100  ; R0 gets R1 + R2.
+  0xa3  0xADFD  ; R3 gets 0xFD immediate.  **
+  0xa4  0xA900  ; R2 gets 0x00 immediate.
+  0xa5  0x0500  ; R1 gets R0.
+  0xa6  0x0300  ; WE goes high.
+  0xa7  0x0100  ; WE goes low.
+  0xa8  0xADDE  ; R3 gets 0xDE immediate.  ** ====================== 0x*E
+  0xa9  0xC500  ; R1 gets mm[R3].
+  0xaa  0x2100  ; R0 gets R1.
+  0xab  0xADEE  ; R3 gets 0xEE immediate.  **
+  0xac  0xC500  ; R1 gets mm[R3].
+  0xad  0x0900  ; R2 gets R0.
+  0xae  0xC100  ; R0 gets R1 + R2.
+  0xaf  0xADFE  ; R3 gets 0xFE immediate.  **
+  0xb0  0xA900  ; R2 gets 0x00 immediate.
+  0xb1  0x0500  ; R1 gets R0.
+  0xb2  0x0300  ; WE goes high.
+  0xb3  0x0100  ; WE goes low.
+  0xb4  0xADDF  ; R3 gets 0xDF immediate.  ** ====================== 0x*F
+  0xb5  0xC500  ; R1 gets mm[R3].
+  0xb6  0x2100  ; R0 gets R1.
+  0xb7  0xADEF  ; R3 gets 0xEF immediate.  **
+  0xb8  0xC500  ; R1 gets mm[R3].
+  0xb9  0x0900  ; R2 gets R0.
+  0xba  0xC100  ; R0 gets R1 + R2.
+  0xbb  0xADFF  ; R3 gets 0xFF immediate.  **
+  0xbc  0xA900  ; R2 gets 0x00 immediate.
+  0xbd  0x0500  ; R1 gets R0.
+  0xbe  0x0300  ; WE goes high.
+  0xbf  0x0100  ; WE goes low.
+  0xc0  0x0100  ; NO-OP.
+  0xc1  0x0100  ; NO-OP.
+  0xc2  0x0100  ; NO-OP.
+  0xc3  0x0100  ; NO-OP.
+  0xc4  0x0100  ; NO-OP.
+  0xc5  0x0100  ; NO-OP.
+  0xc6  0x0100  ; NO-OP.
+  0xc7  0x0100  ; NO-OP.
+  0xc8  0x0000  ; HALT.
+  0xc9  0x0000  ; HALT.
+  0xca  0x0000  ; HALT.
+  0xcb  0x0000  ; HALT.
+  0xcc  0x0000  ; HALT.
+  0xcd  0x0000  ; HALT.
+  0xce  0x0000  ; HALT.
+  0xcf  0x0000  ; HALT.
+  0xd0  0x0011  ; begin   source vector 1.
+  0xd1  0x0027
+  0xd2  0x0014
+  0xd3  0x00e2
+  0xd4  0x0075
+  0xd5  0x0045
+  0xd6  0x009B
+  0xd7  0x00DE
+  0xd8  0x0009
+  0xd9  0x0041
+  0xda  0x009A
+  0xdb  0x0052  
+  0xdc  0x00aa
+  0xdd  0x00bb
+  0xde  0x00cc
+  0xdf  0x00dd  ; end   source vector 1.
+  0xe0  0x0022  ; begin source vector 2.
+  0xe1  0x0058
+  0xe2  0x00B5
+  0xe3  0x009E
+  0xe4  0x0014
+  0xe5  0x002C
+  0xe6  0x00AA
+  0xe7  0x0086
+  0xe8  0x0090
+  0xe9  0x0012
+  0xea  0x0049
+  0xeb  0x0099
+  0xec  0x0027
+  0xed  0x0037
+  0xee  0x0047
+  0xef  0x0057  ; end   source vector 2.
+  0xf0  0x0000  ; begin result vector region.
+  0xf1  0x0000
+  0xf2  0x0000
+  0xf3  0x0000
+  0xf4  0x0000
+  0xf5  0x0000
+  0xf6  0x0000
+  0xf7  0x0000
+  0xf8  0x0000
+  0xf9  0x0000
+  0xfa  0x0000
+  0xfb  0x0000
+  0xfc  0x0000
+  0xfd  0x0000
+  0xfe  0x0000
+  0xff  0x0000  ; end   result vector region.
\ No newline at end of file
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmCPUassemblySource/prog_loop_registers.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,256 @@
+  0x00  0x4D00    ; R3 gets R2 begin register-rotation program.
+  0x01  0x2900    ; R2 gets R1
+  0x02  0x0500    ; R1 gets R0
+  0x03  0x6100    ; R0 gets R3
+  0x04  0xB000    ; PC gets 00
+  0x05  0x8100    ; R0 gets R0 (guard instruction)
+  0x06  0x0000
+  0x07  0x0000
+  0x08  0x0000
+  0x09  0x0000
+  0x0a  0x0000
+  0x0b  0x0000
+  0x0c  0x0000
+  0x0d  0x0000
+  0x0e  0x0000
+  0x0f  0x0000
+  0x10  0x0000
+  0x11  0x0000
+  0x12  0x0000
+  0x13  0x0000
+  0x14  0x0000
+  0x15  0x0000
+  0x16  0x0000
+  0x17  0x0000
+  0x18  0x0000
+  0x19  0x0000
+  0x1a  0x0000
+  0x1b  0x0000
+  0x1c  0x0000
+  0x1d  0x0000
+  0x1e  0x0000
+  0x1f  0x0000
+  0x20  0x0000
+  0x21  0x0000
+  0x22  0x0000
+  0x23  0x0000
+  0x24  0x0000
+  0x25  0x0000
+  0x26  0x0000
+  0x27  0x0000
+  0x28  0x0000
+  0x29  0x0000
+  0x2a  0x0000
+  0x2b  0x0000
+  0x2c  0x0000
+  0x2d  0x0000
+  0x2e  0x0000
+  0x2f  0x0000
+  0x30  0x0000
+  0x31  0x0000
+  0x32  0x0000
+  0x33  0x0000
+  0x34  0x0000
+  0x35  0x0000
+  0x36  0x0000
+  0x37  0x0000
+  0x38  0x0000
+  0x39  0x0000
+  0x3a  0x0000
+  0x3b  0x0000
+  0x3c  0x0000
+  0x3d  0x0000
+  0x3e  0x0000
+  0x3f  0x0000
+  0x40  0x0000
+  0x41  0x0000
+  0x42  0x0000
+  0x43  0x0000
+  0x44  0x0000
+  0x45  0x0000
+  0x46  0x0000
+  0x47  0x0000
+  0x48  0x0000
+  0x49  0x0000
+  0x4a  0x0000
+  0x4b  0x0000
+  0x4c  0x0000
+  0x4d  0x0000
+  0x4e  0x0000
+  0x4f  0x0000
+  0x50  0x0000
+  0x51  0x0000
+  0x52  0x0000
+  0x53  0x0000
+  0x54  0x0000
+  0x55  0x0000
+  0x56  0x0000
+  0x57  0x0000
+  0x58  0x0000
+  0x59  0x0000
+  0x5a  0x0000
+  0x5b  0x0000
+  0x5c  0x0000
+  0x5d  0x0000
+  0x5e  0x0000
+  0x5f  0x0000
+  0x60  0x0000
+  0x61  0x0000
+  0x62  0x0000
+  0x63  0x0000
+  0x64  0x0000
+  0x65  0x0000
+  0x66  0x0000
+  0x67  0x0000
+  0x68  0x0000
+  0x69  0x0000
+  0x6a  0x0000
+  0x6b  0x0000
+  0x6c  0x0000
+  0x6d  0x0000
+  0x6e  0x0000
+  0x6f  0x0000
+  0x70  0x0000
+  0x71  0x0000
+  0x72  0x0000
+  0x73  0x0000
+  0x74  0x0000
+  0x75  0x0000
+  0x76  0x0000
+  0x77  0x0000
+  0x78  0x0000
+  0x79  0x0000
+  0x7a  0x0000
+  0x7b  0x0000
+  0x7c  0x0000
+  0x7d  0x0000
+  0x7e  0x0000
+  0x7f  0x0000
+  0x80  0x0000
+  0x81  0x0000
+  0x82  0x0000
+  0x83  0x0000
+  0x84  0x0000
+  0x85  0x0000
+  0x86  0x0000
+  0x87  0x0000
+  0x88  0x0000
+  0x89  0x0000
+  0x8a  0x0000
+  0x8b  0x0000
+  0x8c  0x0000
+  0x8d  0x0000
+  0x8e  0x0000
+  0x8f  0x0000
+  0x90  0x0000
+  0x91  0x0000
+  0x92  0x0000
+  0x93  0x0000
+  0x94  0x0000
+  0x95  0x0000
+  0x96  0x0000
+  0x97  0x0000
+  0x98  0x0000
+  0x99  0x0000
+  0x9a  0x0000
+  0x9b  0x0000
+  0x9c  0x0000
+  0x9d  0x0000
+  0x9e  0x0000
+  0x9f  0x0000
+  0xa0  0x0000
+  0xa1  0x0000
+  0xa2  0x0000
+  0xa3  0x0000
+  0xa4  0x0000
+  0xa5  0x0000
+  0xa6  0x0000
+  0xa7  0x0000
+  0xa8  0x0000
+  0xa9  0x0000
+  0xaa  0x0000
+  0xab  0x0000
+  0xac  0x0000
+  0xad  0x0000
+  0xae  0x0000
+  0xaf  0x0000
+  0xb0  0x0000
+  0xb1  0x0000
+  0xb2  0x0000
+  0xb3  0x0000
+  0xb4  0x0000
+  0xb5  0x0000
+  0xb6  0x0000
+  0xb7  0x0000
+  0xb8  0x0000
+  0xb9  0x0000
+  0xba  0x0000
+  0xbb  0x0000
+  0xbc  0x0000
+  0xbd  0x0000
+  0xbe  0x0000
+  0xbf  0x0000
+  0xc0  0x0000
+  0xc1  0x0000
+  0xc2  0x0000
+  0xc3  0x0000
+  0xc4  0x0000
+  0xc5  0x0000
+  0xc6  0x0000
+  0xc7  0x0000
+  0xc8  0x0000
+  0xc9  0x0000
+  0xca  0x0000
+  0xcb  0x0000
+  0xcc  0x0000
+  0xcd  0x0000
+  0xce  0x0000
+  0xcf  0x0000
+  0xd0  0x0000
+  0xd1  0x0000
+  0xd2  0x0000
+  0xd3  0x0000
+  0xd4  0x0000
+  0xd5  0x0000
+  0xd6  0x0000
+  0xd7  0x0000
+  0xd8  0x0000
+  0xd9  0x0000
+  0xda  0x0000
+  0xdb  0x0000
+  0xdc  0x0000
+  0xdd  0x0000
+  0xde  0x0000
+  0xdf  0x0000
+  0xe0  0x0000
+  0xe1  0x0000
+  0xe2  0x0000
+  0xe3  0x0000
+  0xe4  0x0000
+  0xe5  0x0000
+  0xe6  0x0000
+  0xe7  0x0000
+  0xe8  0x0000
+  0xe9  0x0000
+  0xea  0x0000
+  0xeb  0x0000
+  0xec  0x0000
+  0xed  0x0000
+  0xee  0x0000
+  0xef  0x0000
+  0xf0  0x0000
+  0xf1  0x0000
+  0xf2  0x0000
+  0xf3  0x0000
+  0xf4  0x0000
+  0xf5  0x0000
+  0xf6  0x0000
+  0xf7  0x0000
+  0xf8  0x0000
+  0xf9  0x0000
+  0xfa  0x0000
+  0xfb  0x0000
+  0xfc  0x0000
+  0xfd  0x0000
+  0xfe  0x0000
+  0xff  0x0000
\ No newline at end of file
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmPython/invoke.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,1 @@
+python ./mmProject.py
\ No newline at end of file
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmPython/mmProject.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,30 @@
+#!/usr/bin/python -tt                           # tt: detect mixed space/tab.
+#---copyright-----------------------------------#-------------------------------
+#   licensed for personal and academic use.
+#   commercial use must be approved by the account-holder of
+#   gated.clock@gmail.com
+#=======imports=================================#===============================
+import os                                       # import os  library.
+import sys                                      # import sys library.
+import usb.core                                 # import PyUSB library.
+from   Tkinter import *                         # Tk library.
+import ttk                                      # from Tk library.
+import tkFileDialog                             # from Tk library.
+import pexpect                                  # not needed here.
+import mmUI                                     # specify file.
+from   mmUI    import *                         # specify module.
+#=======function================================#===============================
+#=======main====================================#===============================
+#-------parameters------------------------------#-------------------------------
+#-------locals----------------------------------#-------------------------------
+#-------execution-------------------------------#-------------------------------
+if (1):
+
+        root = Tk()
+        app  = mmUI(root)
+        root.mainloop()
+        sys.exit(0)
+#-----------------------------------------------#-------------------------------
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmPython/mmUI.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,740 @@
+#!/usr/bin/python -tt                           # tt: detect mixed space/tab.
+#---copyright-----------------------------------#-------------------------------
+#   licensed for personal and academic use.
+#   commercial use must be approved by the account-holder of
+#   gated.clock@gmail.com
+#-------imports---------------------------------#-------------------------------
+from   Tkinter     import *                     # Tk graphics.
+import mmUSBserial                              # USB Serial object.
+from   mmUSBserial import *
+import time                                     # Time object.
+from   time import time, sleep
+import threading                                # Threading object.
+import tkFileDialog                             # File-select dialog object.'
+import os                                       # import os  library.
+#=======class===================================#===============================
+#-----------------------------------------------#-------------------------------
+'''
+        licensed for personal and accedemic use.
+        commercial use must be approved by the account-holder of
+        gated.clock@gmail.com
+'''     
+#-----------------------------------------------#-------------------------------
+'''
+        description: 
+
+        python/Tk code for interfacing with the mbed.org system.
+        this code provides a UI which is used to communicate over USB
+        to the mbed.org processor, and in turn the toy CPU programmed
+        into the altera device.
+
+        this code provides a UI which is used to monitor and write-to the
+        toy CPU's registers and its main memory. 
+
+        I/O capability:
+
+        * R0 write/read.
+        * R1 write/read.
+        * R2 write/read.
+        * R3 write/read.
+        * PC write/read.  (that's 'Program Counter'.)
+        * IR write/read.  (that's 'Instruction Register'.)
+        * MM address.     (that's 'Main Memory.')
+        * MM content.
+
+        Button Controls:
+
+        * USB Connect/Disconnect.
+        * Register Read.
+        * Register Write.
+        * Main Memory Read.
+        * Main Memory Write.
+        * Main Memory Load-From-File.
+        * Main Memory Dump-To-File.
+        * Step CPU.
+        * Run-Fast, Run-Slow, Stop CPU.
+        * Run Test.
+        * Exit.
+
+'''
+#-----------------------------------------------#-------------------------------
+if (1):                                         # allow further indentation.                            
+        class mmUI:                             # UI class.
+#-----------------------------------------------#-------------------------------
+          def __init__(self,masterWidget):      # constructor.
+
+            self.__masterWidget = masterWidget  # promote to object scope.
+
+                                                # master widget title.
+            self.__masterWidget.wm_title("CPU Control")
+
+            self.__frame = Frame(masterWidget)  # create frame widget.
+            self.__frame.grid(column=0, row=0)  # use grid packer.
+
+            self.__connected   = 0              # not yet __connected to USB.
+            self.__isRunning   = 0              # program execution not running.
+            self.__testRunning = 0              # test mode not runing.
+            self.__testIter    = 0              # test mode iteration count.
+            self.__sleepVal    = 0.04           # serial transceive sleep.  3 works.
+
+            
+            self.uiR0      (0, 1, 10)           # label/entry widgets (x, y, width)
+            self.uiR1      (0, 2, 10)
+            self.uiR2      (0, 3, 10)
+            self.uiR3      (0, 4, 10)
+            self.uiPC      (0, 5, 10)
+            self.uiIR      (0, 6, 10)
+            self.uimmADR   (0, 7, 10)
+            self.uimmVAL   (0, 8, 10)
+
+            self.uiConnect (3,  1, 8)           # button widgets (x, y, width)
+            self.uiRegRead (3,  2, 8)
+            self.uiRegWrite(3,  3, 8)
+            self.uimmRead  (3,  4, 8)
+            self.uimmWrite (3,  5, 8)
+            self.uiProg    (3,  6, 8)
+            self.uimmDump  (3,  7, 8)
+            self.uiStep    (3,  8, 8)
+            self.uiRun     (3,  9, 8)
+            self.uiTest    (3, 10, 8)
+            self.uiExit    (3, 11, 8)
+
+            self.refreshUI()                    # initial content display.
+
+#-----------------------------------------------#-------------------------------    
+          def __del__(self):                    # destructor.
+            print "object destroyed."
+#-----------------------------------------------#-------------------------------
+#         WIDGETS: BEGIN LABEL/ENTRY PAIRS.     #===============================
+#-----------------------------------------------#-------------------------------
+          def uiR0(self,dColumn,dRow,dWidth):   # R0.
+
+            dColumnPlusOne = dColumn + 1
+
+            self.__R0Label = Label(self.__frame, text="R0")
+            self.__R0Label.grid(column=dColumn, row=dRow, sticky=(E))
+    
+            self.__R0Entry = Entry(self.__frame, width=dWidth, background="GREEN")
+            self.__R0Entry.grid(column=dColumnPlusOne, row=dRow, sticky=(W))
+#-----------------------------------------------#-------------------------------
+          def uiR1(self,dColumn,dRow,dWidth):   # R1.
+
+            dColumnPlusOne = dColumn + 1
+
+            self.__R1Label = Label(self.__frame, text="R1")
+            self.__R1Label.grid(column=dColumn, row=dRow, sticky=(E))
+    
+            self.__R1Entry = Entry(self.__frame, width=dWidth, background="GREEN")
+            self.__R1Entry.grid(column=dColumnPlusOne, row=dRow, sticky=(W))
+#-----------------------------------------------#-------------------------------
+          def uiR2(self,dColumn,dRow,dWidth):   # R2.
+
+            dColumnPlusOne = dColumn + 1
+
+            self.__R2Label = Label(self.__frame, text="R2")
+            self.__R2Label.grid(column=dColumn, row=dRow, sticky=(E))
+    
+            self.__R2Entry = Entry(self.__frame, width=dWidth, background="GREEN")
+            self.__R2Entry.grid(column=dColumnPlusOne, row=dRow, sticky=(W))
+#-----------------------------------------------#-------------------------------
+          def uiR3(self,dColumn,dRow,dWidth):   # R3.
+
+            dColumnPlusOne = dColumn + 1
+
+            self.__R3Label = Label(self.__frame, text="R3")
+            self.__R3Label.grid(column=dColumn, row=dRow, sticky=(E))
+    
+            self.__R3Entry = Entry(self.__frame, width=dWidth, background="GREEN")
+            self.__R3Entry.grid(column=dColumnPlusOne, row=dRow, sticky=(W))
+#-----------------------------------------------#-------------------------------
+          def uiPC(self,dColumn,dRow,dWidth):   # program counter.
+
+            dColumnPlusOne = dColumn + 1
+
+            self.__PCLabel = Label(self.__frame, text="PC")
+            self.__PCLabel.grid(column=dColumn, row=dRow, sticky=(E))
+    
+            self.__PCEntry = Entry(self.__frame, width=dWidth, background="ORANGE")
+            self.__PCEntry.grid(column=dColumnPlusOne, row=dRow, sticky=(W))
+#-----------------------------------------------#-------------------------------
+          def uiIR(self,dColumn,dRow,dWidth):   # instruction register.
+
+            dColumnPlusOne = dColumn + 1
+
+            self.__IRLabel = Label(self.__frame, text="IR")
+            self.__IRLabel.grid(column=dColumn, row=dRow, sticky=(E))
+    
+            self.__IREntry = Entry(self.__frame, width=dWidth, background="ORANGE")
+            self.__IREntry.grid(column=dColumnPlusOne, row=dRow, sticky=(W))
+#-----------------------------------------------#-------------------------------
+          def uimmADR(self,dColumn,dRow,dWidth):# mmADR.
+
+            dColumnPlusOne = dColumn + 1
+
+            self.__mmADRLabel = Label(self.__frame, text="mmADR")
+            self.__mmADRLabel.grid(column=dColumn, row=dRow, sticky=(E))
+    
+            self.__mmADREntry = Entry(self.__frame, width=dWidth, 
+                                      background="MAROON", foreground="WHITE")
+            self.__mmADREntry.grid(column=dColumnPlusOne, row=dRow, sticky=(W))
+#-----------------------------------------------#-------------------------------        
+          def uimmVAL(self,dColumn,dRow,dWidth):# mmVAL.        
+
+            dColumnPlusOne = dColumn + 1
+
+            self.__mmVALLabel = Label(self.__frame, text="mmVAL")
+            self.__mmVALLabel.grid(column=dColumn, row=dRow, sticky=(E))
+    
+            self.__mmVALEntry = Entry(self.__frame, width=dWidth, 
+                                      background="MAROON", foreground="WHITE")
+            self.__mmVALEntry.grid(column=dColumnPlusOne, row=dRow, sticky=(W))
+#-----------------------------------------------#-------------------------------
+#         WIDGETS: BEGIN BUTTONS.               #===============================
+#-----------------------------------------------#-------------------------------
+                                                # generate the 'connect' button.
+          def uiConnect(self,dColumn,dRow,dWidth):      
+
+            self.__connectButton = Button(self.__frame, text="CONNECT", 
+                                          command=self.selectConnectButtonPressed,
+                                          background="RED",
+                                          width = dWidth)
+
+            self.__connectButton.grid(column=dColumn, row=dRow, sticky=(E))
+#-----------------------------------------------#-------------------------------
+                                                # generate the register-read button.
+          def uiRegRead(self,dColumn,dRow,dWidth):
+            self.__RegReadButton = Button(self.__frame, text="REG READ", 
+                                        command=self.selectRegReadButtonPressed,
+                                        width = dWidth)
+
+            self.__RegReadButton.grid(column=dColumn, row=dRow, sticky=(W))
+#-----------------------------------------------#-------------------------------
+                                                # generate the 'reg write' button.
+          def uiRegWrite(self,dColumn,dRow,dWidth):
+            self.__RegWriteButton = Button(self.__frame, text="REG WRITE", 
+                                        command=self.selectRegWriteButtonPressed, 
+                                        width = dWidth)
+
+            self.__RegWriteButton.grid(column=dColumn, row=dRow, sticky=(W))
+#-----------------------------------------------#-------------------------------
+                                                # generate the mm-read button.
+          def uimmRead(self,dColumn,dRow,dWidth):
+            self.__mmReadButton = Button(self.__frame, text="MM READ", 
+                                        command=self.selectmmReadButtonPressed, 
+                                        width = dWidth)
+
+            self.__mmReadButton.grid(column=dColumn, row=dRow, sticky=(W))
+#-----------------------------------------------#-------------------------------
+                                                # generate the 'mm write' button.
+          def uimmWrite(self,dColumn,dRow,dWidth):
+            self.__mmWriteButton = Button(self.__frame, text="MM WRITE", 
+                                        command=self.selectmmWriteButtonPressed, 
+                                        width = dWidth)
+
+            self.__mmWriteButton.grid(column=dColumn, row=dRow, sticky=(W))
+#-----------------------------------------------#-------------------------------
+          def uiProg(self,dColumn,dRow,dWidth): # generate the 'program' button.
+            self.__ProgButton = Button(self.__frame, text="PROGRAM", 
+                                        command=self.selectProgButtonPressed, 
+                                        width = dWidth)
+
+            self.__ProgButton.grid(column=dColumn, row=dRow, sticky=(W))
+#-----------------------------------------------#-------------------------------
+                                                # generate the 'mm dump' button.
+          def uimmDump(self,dColumn,dRow,dWidth):
+            self.__mmWriteButton = Button(self.__frame, text="DUMP", 
+                                        command=self.selectmmDumpButtonPressed, 
+                                        width = dWidth)
+
+            self.__mmWriteButton.grid(column=dColumn, row=dRow, sticky=(W))
+#-----------------------------------------------#-------------------------------
+          def uiStep(self,dColumn,dRow,dWidth): # generate the 'step' button.
+            self.__StepButton = Button(self.__frame, text="STEP", 
+                                        command=self.selectStepButtonPressed, 
+                                        width = dWidth)
+
+            self.__StepButton.grid(column=dColumn, row=dRow, sticky=(W))
+#-----------------------------------------------#-------------------------------
+          def uiRun(self,dColumn,dRow,dWidth):  # generate the 'run' button.
+            self.__runButton = Button(self.__frame, text="RUN", 
+                                      command=self.selectRunButtonPressed,width = dWidth)
+
+            self.__runButton.grid(column=dColumn, row=dRow, sticky=(E))
+#-----------------------------------------------#-------------------------------
+          def uiTest(self,dColumn,dRow,dWidth): # generate the 'test' button.
+            self.__testButton = Button(self.__frame, text="TEST", 
+                                      command=self.selectTestButtonPressed,width = dWidth)
+
+            self.__testButton.grid(column=dColumn, row=dRow, sticky=(E))
+#-----------------------------------------------#-------------------------------
+          def uiExit(self,dColumn,dRow,dWidth): # generate the 'exit' button.
+
+            self.__isRunning = 0                # end the running thread.
+            sleep(2.0)                          # give thread time to stop.
+
+            self.__exitButton = Button(self.__frame, text="EXIT", 
+                                       command=sys.exit,width = dWidth)
+
+            self.__exitButton.grid(column=dColumn, row=dRow, sticky=(E))
+#-----------------------------------------------#-------------------------------
+#         BEGIN EXECUTE-WHEN-BUTTON-PRESSED CODE#===============================
+#-----------------------------------------------#-------------------------------
+          def selectConnectButtonPressed(self): # execute CONNECT.
+            if (self.__connected == 0):
+              self.__iUSB = mmUSBserial(idVendor=0x1234, idProduct=0x0006)
+              self.__connected = 1
+              self.__connectButton["text"] = "DISCONNECT"
+              self.__connectButton["background"] = self.__frame.cget("background")
+            else:
+              del(self.__iUSB)
+              self.__connected = 0
+              self.__connectButton["text"] = "CONNECT"
+              self.__connectButton["background"] = "RED"
+#-----------------------------------------------#-------------------------------
+          def selectRegReadButtonPressed(self): # REG READ button has been pressed.
+            self.refreshUI()                    # ensure proper text formats.
+
+                                                # real all registers.
+            self.__iUSB.write(self.buildReadAllRegisterCommand())
+            messageVector =   self.__iUSB.read()
+
+                                                # parse-out the register entries.
+            hexTextR0     = "0x" + messageVector[ 1: 3]
+            hexTextR1     = "0x" + messageVector[ 3: 5]
+            hexTextR2     = "0x" + messageVector[ 5: 7]
+            hexTextR3     = "0x" + messageVector[ 7: 9]
+            hexTextPC     = "0x" + messageVector[ 9:11]
+            hexTextIR     = "0x" + messageVector[11:15]
+
+
+            self.__R0Entry.delete(0,99)         # R0 to UI.
+            self.__R0Entry.insert(0,hexTextR0)
+
+            self.__R1Entry.delete(0,99)         # R1 to UI.
+            self.__R1Entry.insert(0,hexTextR1)
+
+            self.__R2Entry.delete(0,99)         # R2 to UI.
+            self.__R2Entry.insert(0,hexTextR2)
+
+            self.__R3Entry.delete(0,99)         # R3 to UI.
+            self.__R3Entry.insert(0,hexTextR3)
+
+            self.__PCEntry.delete(0,99)         # PC to UI.
+            self.__PCEntry.insert(0,hexTextPC)
+
+            self.__IREntry.delete(0,99)         # IR to UI.
+            self.__IREntry.insert(0,hexTextIR)
+
+#----
+            self.refreshUI()                    # ensure proper text formats
+#-----------------------------------------------#-------------------------------
+          def selectmmReadButtonPressed(self):  # MM READ button has been pressed.
+            self.refreshUI()                    # ensure proper text formats.
+
+            transmitmmADRText = self.formatByteStringForTransmit(self.__mmADREntry.get())
+            commandText = self.buildReadMMCommand(transmitmmADRText)
+
+            self.__iUSB.write(commandText)
+
+            fetchTextmmVAL = self.__iUSB.read()
+
+            buildHextmmVALString = fetchTextmmVAL[3:7]
+
+            self.__mmVALEntry.delete(0,99)
+            self.__mmVALEntry.insert(0,buildHextmmVALString)
+#----
+            self.selectRegReadButtonPressed()   # because registers are affected.
+            self.refreshUI()                    # ensure proper text formats
+#-----------------------------------------------#-------------------------------
+#         before writing the register values currently displayed in the UI,
+#         this method will first run that data through a formatter, so that
+#         the data is transformed into '0x##' format.  this is convenient for
+#         the user.  for example, the user can type '12' in a register entry
+#         form, press the 'REG WRITE' button, and that data will be reformatted
+#         to appear as '0x12'.
+
+          def selectRegWriteButtonPressed(self):# REG WRITE button has been pressed.
+
+            self.refreshUI()                    # ensure proper text formats.
+#----
+                                                # place those values in the
+                                                # standard format.
+            R0Val = self.formatByteStringForTransmit(self.__R0Entry.get())
+            R1Val = self.formatByteStringForTransmit(self.__R1Entry.get())
+            R2Val = self.formatByteStringForTransmit(self.__R2Entry.get())
+            R3Val = self.formatByteStringForTransmit(self.__R3Entry.get())
+            PCVal = self.formatByteStringForTransmit(self.__PCEntry.get())
+            IRVal = self.formatWordStringForTransmit(self.__IREntry.get()) 
+#----
+                                                # write those values to the CPU.
+            self.__iUSB.write(self.buildWriteRegisterCommand("0",R0Val))
+            self.__iUSB.write(self.buildWriteRegisterCommand("1",R1Val))
+            self.__iUSB.write(self.buildWriteRegisterCommand("2",R2Val))
+            self.__iUSB.write(self.buildWriteRegisterCommand("3",R3Val))
+            self.__iUSB.write(self.buildWriteRegisterCommand("4",PCVal))
+            self.__iUSB.write(self.buildWriteIRCommand      (    IRVal))
+#-----------------------------------------------#-------------------------------
+#         before writing the main-memory values currently displayed in the UI,
+#         this method will first run that data through a formatter, so that
+#         the data is transformed into '0x##' or '0x####' format.  
+#         this is convenient for the user.  
+#         for example, the user can type '12' in the mmADR entry
+#         form, press the 'MM WRITE' button, and that data will be reformatted
+#         to appear as '0x12'.
+
+          def selectmmWriteButtonPressed(self): # mm WRITE button has been pressed.
+
+            self.refreshUI()                    # ensure proper text formats.
+
+                                                # obtain mm values currently
+                                                # displayed in the UI.
+            self.__transmitmmADRText = self.__mmADREntry.get()
+            self.__transmitmmVALText = self.__mmVALEntry.get()
+
+                                                # place those values in the
+                                                # standard format.
+            mmADRVAL = self.formatByteStringForTransmit(self.__mmADREntry.get())
+            mmVALVal = self.formatWordStringForTransmit(self.__mmVALEntry.get())
+
+                                                # write those values to the CPU.
+            self.__iUSB.write(self.buildWriteMMCommand(mmADRVAL,mmVALVal))
+
+            self.selectRegReadButtonPressed()   # because registers are affected.
+#-----------------------------------------------#-------------------------------
+          def selectProgButtonPressed(self):    # Program button has been pressed.
+
+                                                # ask user for program source file
+                                                # name using a dialog.
+            fileName = tkFileDialog.askopenfilename(defaultextension='.txt')
+
+            print("memory load started.")       # announce to user.
+            self.progamMainMemory(fileName)     # main part of programming.
+            print("memory load completed.")     # announce to user.
+#-----------------------------------------------#-------------------------------
+          def selectmmDumpButtonPressed(self):  # MM dump button has been pressed.
+
+                                                # obtain file-to-write-to name
+                                                # from user, using a dialog.
+            fileName = tkFileDialog.asksaveasfilename(defaultextension='.txt')
+
+            print("memory dump started.")       # announce to user.
+            self.dumpMainMemory(fileName)       # dump main memory to file.
+            print("memory dump completed.")     # announce to user.
+#-----------------------------------------------#-------------------------------
+          def selectStepButtonPressed(self):    # STEP button has been pressed.
+            self.__iUSB.write("50000000")       # the command code.
+            self.selectRegReadButtonPressed()   # monitor the result.
+#-----------------------------------------------#-------------------------------
+          def selectRunButtonPressed(self):     # RUN/STOP button has been pressed.
+
+            if (self.__isRunning == 0):         # start high speed run.
+              self.__isRunning = 1
+              self.__runButton["text"] = "SLOW"
+              self.t = threading.Thread(target=self.doRun)
+              self.t.start()
+
+            elif (self.__isRunning == 1):       # switch to a slower run.
+              self.__isRunning = 2
+              self.__runButton["text"] = "STOP"
+
+            else:                               # stop the CPU.
+              self.__isRunning = 0
+              self.__runButton["text"] = "RUN"
+#-----------------------------------------------#-------------------------------
+          def selectTestButtonPressed(self):    # TEST/STOP button has been pressed.
+
+            if (self.__testRunning == 0):       # start test.
+              self.__testRunning = 1
+              self.__testButton["text"] = "STOP TEST"
+              self.t = threading.Thread(target=self.doTest)
+              self.t.start()
+
+
+            else:                               # stop test.
+              self.__testRunning = 0
+              self.__testButton["text"] = "TEST"
+#-----------------------------------------------#-------------------------------
+#         BEGIN UTILITY CODE.                   #===============================
+#-----------------------------------------------#-------------------------------
+                                                # guarantee 0x## format.
+          def formatByteStringForDisplay(self, byteText):       
+        
+            xIndex = byteText.find("x")         # eliminate any 0x, 0X prefix.
+            XIndex = byteText.find("X")
+
+            theXindex   = 0
+            if (xIndex >= 0): theXindex = xIndex + 1
+            if (XIndex >= 0): theXindex = XIndex + 1
+
+            buildText = byteText[theXindex:]    # any 0x, 0X prefix gone.
+
+                                                # build-out leading 0's.
+            if (len(buildText) == 0): buildText = "0" + buildText
+            if (len(buildText) == 1): buildText = "0" + buildText
+
+                                                # truncate leading characters.
+            if (len(buildText)  > 2): buildText = buildText[-2:]
+
+            buildText = "0x" + buildText        # add leading 0x.
+
+            return(buildText)                   # 0x## format returned.
+#-----------------------------------------------#-------------------------------
+                                                # guarantee 0x#### format.
+          def formatWordStringForDisplay(self, wordText):       
+        
+            xIndex = wordText.find("x")         # eliminate any 0x, 0X prefix.
+            XIndex = wordText.find("X")
+
+            theXindex   = 0
+            if (xIndex >= 0): theXindex = xIndex + 1
+            if (XIndex >= 0): theXindex = XIndex + 1
+
+            buildText = wordText[theXindex:]    # any 0x, 0X prefix gone.
+
+                                                # build-out leading 0's.
+            if (len(buildText) == 0): buildText = "0" + buildText
+            if (len(buildText) == 1): buildText = "0" + buildText
+            if (len(buildText) == 2): buildText = "0" + buildText
+            if (len(buildText) == 3): buildText = "0" + buildText
+
+
+                                                # truncate leading characters.
+            if (len(buildText)  > 4): buildText = buildText[-4:]
+
+            buildText = "0x" + buildText        # add leading 0x.
+
+            return(buildText)                   # 0x## format returned.
+#-----------------------------------------------#-------------------------------
+                                                # guarantee ## format.
+          def formatByteStringForTransmit(self, byteText):
+            buildText = self.formatByteStringForDisplay(byteText)
+            buildText = buildText[-2:]
+            return(buildText)
+#-----------------------------------------------#-------------------------------
+                                                # guarantee #### format.
+          def formatWordStringForTransmit(self, wordText):
+            buildText = self.formatWordStringForDisplay(wordText)
+            buildText = buildText[-4:]
+            return(buildText)
+#-----------------------------------------------#-------------------------------
+          def refreshUI(self):                  # reformat UI text.
+
+                                                # copy-in current form contents.
+            originalR0Entry    = self.__R0Entry.get()
+            originalR1Entry    = self.__R1Entry.get()
+            originalR2Entry    = self.__R2Entry.get()
+            originalR3Entry    = self.__R3Entry.get()
+            originalPCEntry    = self.__PCEntry.get()
+            originalIREntry    = self.__IREntry.get()
+            originalmmADREntry = self.__mmADREntry.get()
+            originalmmVALEntry = self.__mmVALEntry.get()
+
+                                                # reformat form contents.
+            newR0Entry    = self.formatByteStringForDisplay(originalR0Entry)
+            newR1Entry    = self.formatByteStringForDisplay(originalR1Entry)
+            newR2Entry    = self.formatByteStringForDisplay(originalR2Entry)
+            newR3Entry    = self.formatByteStringForDisplay(originalR3Entry)
+            newPCEntry    = self.formatByteStringForDisplay(originalPCEntry)
+            newIREntry    = self.formatWordStringForDisplay(originalIREntry)
+
+            newmmADREntry = self.formatByteStringForDisplay(originalmmADREntry)
+            newmmVALEntry = self.formatWordStringForDisplay(originalmmVALEntry)
+
+                                                
+            self.__R0Entry.   delete(0,99)      # clear form contents.
+            self.__R1Entry.   delete(0,99)
+            self.__R2Entry.   delete(0,99)
+            self.__R3Entry.   delete(0,99)
+            self.__PCEntry.   delete(0,99)
+            self.__IREntry.   delete(0,99)
+            self.__mmADREntry.delete(0,99)
+            self.__mmVALEntry.delete(0,99)
+
+                                                # update form contents.
+            self.__R0Entry.   insert(0,newR0Entry)
+            self.__R1Entry.   insert(0,newR1Entry)
+            self.__R2Entry.   insert(0,newR2Entry)
+            self.__R3Entry.   insert(0,newR3Entry)
+            self.__PCEntry.   insert(0,newPCEntry)
+            self.__IREntry.   insert(0,newIREntry)
+            self.__mmADREntry.insert(0,newmmADREntry)
+            self.__mmVALEntry.insert(0,newmmVALEntry)
+#-----------------------------------------------#-------------------------------
+                                                # build the command string for
+                                                # reading a value from a CPU register.
+          def buildReadRegisterCommand(self,regNum):
+
+            commandText = ""                    # build command for read register.
+            commandText = commandText + "2"     # command-code.
+            commandText = commandText + regNum  # register number.
+            commandText = commandText + "0000000000000"
+            return(commandText)
+#-----------------------------------------------#-------------------------------
+                                                # build the command string for
+                                                # reading all CPU register values.
+          def buildReadAllRegisterCommand(self):
+
+            commandText = ""                    # build command for read register.
+            commandText = commandText + "7"     # command-code.
+            commandText = commandText + "00000000000000"
+            return(commandText)
+#-----------------------------------------------#-------------------------------
+                                                # build the command-string for
+                                                # writing a value to a CPU register.
+          def buildWriteRegisterCommand(self,regNum,regVal):
+
+            commandText = ""
+            commandText = commandText + "1"     # command-code.
+            commandText = commandText + regNum  # register.
+            commandText = commandText + regVal  # content.
+            commandText = commandText + "00000000000"
+            return(commandText)
+#-----------------------------------------------#-------------------------------
+                                                # build the command-string for
+                                                # writing a value to the IR.
+          def buildWriteIRCommand(self,regVal):
+
+            commandText = ""
+            commandText = commandText + "6"     # command-code.
+            commandText = commandText + "5"     # actually a placeholder.
+            commandText = commandText + regVal  # content.
+            commandText = commandText + "000000000"
+            return(commandText)
+#-----------------------------------------------#-------------------------------
+                                                # build the command-string for
+                                                # writing a main-memory value.
+          def buildWriteMMCommand(self,mmADR,mmVAL):
+        
+            commandText = ""
+            commandText = commandText + "3"     # command-code.
+            commandText = commandText + mmADR   # address.
+            commandText = commandText + mmVAL   # value.
+            commandText = commandText + "00000000"
+            return(commandText)
+#-----------------------------------------------#-------------------------------
+          def buildReadMMCommand(self,mmADR):   # build read-mm command-string.
+              commandText = ""                  # build command for read main-memory.
+              commandText = commandText + "4"   # command-code.
+              commandText = commandText + mmADR
+              commandText = commandText + "000000000000"
+              return(commandText)
+#-----------------------------------------------#-------------------------------
+                                                # extract reg value payload.
+          def formatRegValPayload(self,messageVector):
+            buildHex = "0x" + messageVector[2:4]
+            return(buildHex)
+#-----------------------------------------------#-------------------------------
+          def progamMainMemory(self,progFile):  # core of loading program to MM.
+
+            hFile = open(progFile, 'r')
+            fileLineList = hFile.readlines()    # read file into a list.
+            hFile.close()                       # close the file.
+
+                                                # load '0x12 0x3456' memory content
+                                                # format, into a list.
+            for listIndex in range(0, len(fileLineList)):
+              addressStartIndex = fileLineList[listIndex].find("0x") + 2
+              dataStartIndex    = fileLineList[listIndex].find("0x", addressStartIndex)   + 2
+              progAddress = fileLineList[listIndex][addressStartIndex : addressStartIndex + 2]
+              progAddress = format(listIndex,'02x')
+              progData    = fileLineList[listIndex][dataStartIndex    : dataStartIndex    + 4]
+              commandText = self.buildWriteMMCommand(progAddress,progData)
+              self.__iUSB.write(commandText)
+              print(fileLineList[listIndex][0:len(fileLineList[listIndex])-1])
+              sleep(self.__sleepVal)
+#-----------------------------------------------#-------------------------------
+          def dumpMainMemory(self,dumpFile):    # core of dumping MM to file.
+
+            hFile = open(dumpFile, 'w')
+
+            for loopIndex in range(0, 256):     # traverse all of main-memory.
+              transmitmmADRText = "{}".format(hex(loopIndex))
+              transmitmmADRText = transmitmmADRText[2:]
+              if (len(transmitmmADRText) == 1): transmitmmADRText = "0" + transmitmmADRText
+              commandText = self.buildReadMMCommand(transmitmmADRText)
+              self.__iUSB.write(commandText)
+              fetchTextmmVAL = self.__iUSB.read()
+              buildHextmmVALString = fetchTextmmVAL[3:7]
+              buildHexIndex = hex(loopIndex)
+              buildHexIndex = buildHexIndex[2:]
+              if (len(buildHexIndex) == 1): buildHexIndex = "0" + buildHexIndex
+              buildHexIndex = "0x" + buildHexIndex
+              dumpString = "  {}  0x{}\n".format(buildHexIndex,buildHextmmVALString)
+              hFile.write(dumpString)
+              print(dumpString[0:len(dumpString)-1])
+              sleep(self.__sleepVal)
+
+            hFile.close()                       # close the dump file.
+#-----------------------------------------------#-------------------------------
+#         BEGIN THREADED CODE.                  #===============================
+#-----------------------------------------------#-------------------------------
+          def doRun(self):                      # drives the CPU running.
+            while(self.__isRunning):
+              self.selectStepButtonPressed()
+              self.__masterWidget.update_idletasks()    
+              if (self.__isRunning == 2): sleep(1.0)    
+#-----------------------------------------------#-------------------------------
+#         the test consists of loading the add-list program into main memory,
+#         running it, dumping the result to a file, and comparing that file
+#         to the expected result.
+
+          def doTest(self):                     # drives the test.
+            while(self.__testRunning):
+                                                # load program into main memory.
+              self.progamMainMemory("prog_add_list.txt")
+
+                                                # clear instruction register.
+              self.__iUSB.write(self.buildWriteIRCommand("0000"))
+
+                                                # rewind program counter.
+              PCVal          = self.formatByteStringForTransmit("0")
+              writePCcommand = self.buildWriteRegisterCommand("4",PCVal)
+              self.__iUSB.write(writePCcommand)
+              self.selectRegReadButtonPressed()
+
+
+              for stepIndex in range(0, 196):   # step through program.
+                self.selectStepButtonPressed()
+
+                                                # dump result to file.
+              self.dumpMainMemory  ("dump_test.txt")
+
+                                                # build and run test commands.
+              self.__testIter = self.__testIter + 1     
+              iterationText = "test iteration {}".format(self.__testIter)
+              iterationText = "echo '" + iterationText + "' >> testlog.txt"
+              os.system("echo ============================ >> testlog.txt")
+              os.system("date >> testlog.txt")
+              os.system(iterationText)
+              os.system("echo 'compare dump_test.txt against dump_add_list.txt' >> testlog.txt")
+              os.system("diff dump_add_list.txt dump_test.txt >> testlog.txt")
+
+              self.__masterWidget.update_idletasks()    
+#===============================================#===============================
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmPython/mmUSBserial.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,94 @@
+#!/usr/bin/python -tt                           # tt: detect mixed space/tab.
+#---copyright-----------------------------------#-------------------------------
+#   licensed for personal and academic use.
+#   commercial use must be approved by the account-holder of
+#   gated.clock@gmail.com
+#-------imports---------------------------------#-------------------------------
+import serial                                   # serial over USB.
+#=======class===================================#===============================
+if (1):
+        class mmUSBserial():                    # USB class.
+#-----------------------------------------------#-------------------------------
+                                                # constructor.
+          def __init__(self, idVendor, idProduct):      
+
+            self.__idVendor  = idVendor         # promote to object scope.
+            self.__idProduct = idProduct        # promote to object scope.
+
+            openSuccess = 1
+            self.__serialPort = serial.Serial()
+            self.__serialPort.baudrate = 115200 # was 9600
+            self.__serialPort.timeout  =    1   # one-second timeout.
+
+            for portIndex in range(7, -1, -1):
+              portString = "/dev/ttyACM" + "{}".format(portIndex)
+              self.__serialPort.port = portString
+              try:
+                self.__serialPort.open()
+              except:
+                print("failed to open port {}.").format(portString)
+                openSuccess = 0
+
+              if (openSuccess): break
+              openSuccess = 1
+
+            if (openSuccess): print("successfully opened port {}.").format(portString)
+            else:             print("could not open any port.")
+
+            self.__SER_BYTES = 18               # same as mbed program's SER_BYTES.
+#-----------------------------------------------#-------------------------------  
+          def __del__(self):                    # destructor.
+            self.__serialPort.close()
+            print "object destroyed."
+#-----------------------------------------------#-------------------------------
+#         the number of bytes written and read must both be SER_BYTES.
+#         the '$' must be in bit<7> of what's written.
+
+          def write(self,toWrite):              # write a string.
+            nowWrite = toWrite[:7]
+            nowWrite = nowWrite + "$"           # in <7>.
+            if (self.__SER_BYTES > 8):          # flush out with 0's.
+              for loopIndex in range (0, self.__SER_BYTES - 8):
+                nowWrite = nowWrite + "0"
+#           print("nowWrite {}").format(nowWrite)
+            self.__serialPort.write(nowWrite)
+            return(nowWrite)
+#-----------------------------------------------#-------------------------------
+          def read(self):                       # read a string.
+            gotRead = self.__serialPort.read(self.__SER_BYTES)
+#           print("gotRead {}").format(gotRead)
+            return(gotRead)
+#-----------------------------------------------#-------------------------------
+#===============================================#===============================
+
+
+
+
+
+
+
+
+
+
+
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+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/counter_08.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,132 @@
+/*----------------------------------copyright---------------------------------*/
+//      licensed for personal and academic use.
+//      commercial use must be approved by the account-holder of
+//      gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+        module counter_08
+        (
+         oCount,                                // counter state.
+         iParallel7,                            // parallel-input  data.
+         iParallel6,                            // parallel-input  data.
+         iParallel5,                            // parallel-input  data.
+         iParallel4,                            // parallel-input  data.
+         iParallel3,                            // parallel-input  data.
+         iParallel2,                            // parallel-input  data.
+         iParallel1,                            // parallel-input  data.
+         iParallel0,                            // parallel-input  data.
+         iSel,                                  // select the parallel input.
+         oSerial,                               // serial-output data.
+         iSerial,                               // serial-input data.
+         iLoadEnable,                           // parallel-load-enable.
+         iShiftEnable,                          // serial-shift-enable.
+         iCountEnable,                          // count-increment enable.
+         iResetN,                               // synchronous reset*.
+         iClk                                   // module clock.
+        );
+/*--------------------------------description-----------------------------------
+        an 8-bit preloadable counter.
+-------------------------------------notes--------------------------------------
+        shifting is LSB->MSB.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+        output  [ 7:0]  oCount;                 // counter state.
+        input   [ 7:0]  iParallel7;             // parallel-input  data.
+        input   [ 7:0]  iParallel6;             // parallel-input  data.
+        input   [ 7:0]  iParallel5;             // parallel-input  data.
+        input   [ 7:0]  iParallel4;             // parallel-input  data.
+        input   [ 7:0]  iParallel3;             // parallel-input  data.
+        input   [ 7:0]  iParallel2;             // parallel-input  data.
+        input   [ 7:0]  iParallel1;             // parallel-input  data.
+        input   [ 7:0]  iParallel0;             // parallel-input  data.
+        input   [ 2:0]  iSel;                   // select the parallel input.
+        output          oSerial;                // serial-output data.
+        input           iSerial;                // serial-input data.
+        input           iLoadEnable;            // parallel-load-enable.
+        input           iShiftEnable;           // serial-shift-enable.
+        input           iCountEnable;           // count-increment enable.
+        input           iResetN;                // synchronous reset*.
+        input           iClk;                   // module clock.
+/*-----------------------------------wires------------------------------------*/
+        wire    [ 7:0]  oCount;                 // counter state.
+        wire    [ 7:0]  iParallel7;             // parallel-input  data.
+        wire    [ 7:0]  iParallel6;             // parallel-input  data.
+        wire    [ 7:0]  iParallel5;             // parallel-input  data.
+        wire    [ 7:0]  iParallel4;             // parallel-input  data.
+        wire    [ 7:0]  iParallel3;             // parallel-input  data.
+        wire    [ 7:0]  iParallel2;             // parallel-input  data.
+        wire    [ 7:0]  iParallel1;             // parallel-input  data.
+        wire    [ 7:0]  iParallel0;             // parallel-input  data.
+        wire    [ 2:0]  iSel;                   // select the parallel input.
+        wire    [ 7:0]  wParallelIn;            // select the parallel input.
+        wire            oSerial;                // serial-output data.
+        wire            iSerial;                // serial-input data.
+        wire            iLoadEnable;            // parallel-load-enable.
+        wire            iShiftEnable;           // serial-shift-enable.
+        wire            iCountEnable;           // count-increment enable.
+        wire            iResetN;                // synchronous reset*.
+        wire            iClk;                   // module clock.
+/*---------------------------------registers----------------------------------*/
+        reg     [ 7:0]  rRegister;              // the counter state.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+        mux8x8 U01_mux8x8                       // data-input selection.
+        (
+         .iDin7(iParallel7),
+         .iDin6(iParallel6),
+         .iDin5(iParallel5),
+         .iDin4(iParallel4),
+         .iDin3(iParallel3),
+         .iDin2(iParallel2),
+         .iDin1(iParallel1),
+         .iDin0(iParallel0),
+         .iSel (iSel),
+         .oDout(wParallelIn)
+        );
+/*-----------------------------------logic------------------------------------*/
+        always @ (posedge iClk or negedge iResetN)
+        begin
+               if (!iResetN)     rRegister <= 8'h00;
+          else if (iLoadEnable)  rRegister <= wParallelIn;
+          else if (iShiftEnable) rRegister <= {rRegister[6:0], iSerial};
+          else if (iCountEnable) rRegister <= rRegister + 1'b1;
+          else                   rRegister <= rRegister;
+        end
+
+        assign oCount    = rRegister;           // propagate counter state.
+        assign oSerial   = rRegister[7];        // propagate serial-out.
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/cpu.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,531 @@
+/*----------------------------------copyright---//----------------------------*/
+//      licensed for personal and academic use.
+//      commercial use must be approved by the account-holder of
+//      gated.clock@gmail.com
+/*-----------------------------------module-----//----------------------------*/
+        module cpu
+        (
+          iMOSI,
+          oMISO,
+          iSPIclk,
+          iCPUclk,
+          iKEY,
+          iSW,
+          oLEDR,
+          oLEDG,
+          oDummyLoad
+        );
+/*--------------------------------description---//------------------------------
+        the demonstration cpu datapath.
+
+        the CPU consists of
+        R0 -  8-bit register and accumulator.
+        R1 -  8-bit register and main-memory address register.
+        R2 -  8-bit register and main-memory high data byte.
+        R3 -  8-bit register and main-memory low  data byte.
+        PC -  8-bit program counter.
+        IR - 16-bit instruction register.
+        ID -        combinatorial instruction decoder.
+        MM -        16-bit-wide x 256-address Main Memory.
+
+        the instruction words is sixteen bits long, and is comprised of
+        <15:13> = source resource.
+        <12:10> = destination resource.
+        <    9> = write-enable.
+        <    8> = program-counter-enable.
+        < 7: 0> = immediate data.
+
+        the registers (U00 through U05) have a iSel input which define the source.
+        the instruction decoder (U06) enables the loading of the destinations.
+
+        the SPI shadow registers (U19-U25) monitor the CPU state, and can
+        control the CPU state by asserting U19's bits 1 and 2.
+
+        U08 provides a shadow register load-enable pulse which
+            begins at the falling edge of a CPU clock and ends at
+            the falling edge of the next SPI clock, allowing the shadow
+            registers the ability to capture the state of the CPU.
+
+        U30 routes internal nets out to the green LED bank according
+            to the setting of switches SW<3:0>.
+
+-------------------------------------notes------//------------------------------
+
+        fpga board pin assignments.
+
+
+        project:
+        MOSI    P17
+        MISO    D15
+        SPIclk  E20
+        CPUclk  E14
+
+
+        key3    T21
+        key2    T22
+        key1    R21
+        key0    R22     iRstn
+
+        sw9     L2
+        sw8     M1
+        sw7     M2
+        sw6     U11
+        sw5     U12
+        sw4     W12
+        sw3     V12
+        sw2     M22
+        sw1     L21
+        sw0     L22
+
+        ledr9   R17
+        ledr8   R18
+        ledr7   U18
+        ledr6   Y18
+        ledr5   V19
+        ledr4   T18
+        ledr3   Y19
+        ledr2   U19
+        ledr1   R19
+        ledr0   R20
+
+        ledg7   Y21
+        ledg6   Y22
+        ledg5   W21
+        ledg4   W22
+        ledg3   V21
+        ledg2   V22
+        ledg1   U21
+        ledg0   U22
+------------------------------------defines-----//----------------------------*/
+/*-----------------------------------ports------//----------------------------*/
+        input           iMOSI;                  // SPI input.
+        output          oMISO;                  // SPI output.
+        input           iSPIclk;                // SPI clock.
+        input           iCPUclk;                // CPU clock.
+        input   [ 3:0]  iKEY;                   // keypress.
+        input   [ 9:0]  iSW;                    // slide-switches.
+        output  [ 9:0]  oLEDR;                  // red   LED bank.
+        output  [ 7:0]  oLEDG;                  // green LED bank.
+        output          oDummyLoad;             // anti-optimization.
+/*-----------------------------------wires------//----------------------------*/
+        wire            iMOSI;                  // SPI input.
+        wire            oMISO;                  // SPI output.
+        wire            iSPIclk;                // SPI clock.
+        wire            iCPUclk;                // CPU clock.
+        wire    [ 3:0]  iKEY;                   // keypress.
+        wire    [ 9:0]  iSW;                    // slide-switches.
+        wire    [ 9:0]  oLEDR;                  // red   LED bank.
+        wire    [ 7:0]  oLEDG;                  // green LED bank.
+
+        wire            wCEPC;                  // program counter count-enable.
+        wire    [15:0]  wIR;                    // instruction register.
+        wire            wLEIR;                  // instruction register load-enable.
+        wire            wLEPC;                  // program counter load-enable.
+        wire            wLER0;                  // R0 load-enable.
+        wire            wLER1;                  // R1 load-enable.
+        wire            wLER2;                  // R2 load-enable.
+        wire            wLER3;                  // R3 load-enable.
+        wire    [15:0]  wMMD;                   // main-memory data-out.
+        wire    [15:0]  wMMI;                   // main-memory instruction-out.
+        wire    [ 7:0]  wPC;                    // program-counter.
+        wire    [ 7:0]  wR0;                    // R0.
+        wire    [ 7:0]  wR1;                    // R1.
+        wire    [ 7:0]  wR2;                    // R2.
+        wire    [ 7:0]  wR3;                    // R3.
+        wire            wRstn;                  // system reset.
+        wire    [ 2:0]  wSel;                   // common data-in selector.
+        wire    [ 7:0]  wShadow0;               // R0 shadow register.
+        wire    [ 7:0]  wShadow1;               // R1 shadow register.
+        wire    [ 7:0]  wShadow2;               // R2 shadow register.
+        wire    [ 7:0]  wShadow3;               // R3 shadow register.
+        wire    [15:0]  wShadowIR;              // instruction register shadow.
+        wire    [ 7:0]  wShadowPC;              // program counter shadow.
+        wire            wSIR;                   // instruction register shadow shift-up.
+        wire            wSPC;                   // program counter shadow shift-up.
+        wire            wSR0;                   // R0 shadow shift-up.
+        wire            wSR1;                   // R1 shadow shift-up.
+        wire            wSR2;                   // R2 shadow shift-up.
+        wire            wSR3;                   // R3 shadow shift-up.
+        wire            wWE;                    // write-enable pulse.
+        wire    [ 7:0]  wImmediate;             // immediate data.
+        wire    [ 7:0]  wSpiControl;            // from spi control register.
+        wire            wSquelch;               // from spi control register.
+        wire            wBypassIR;              // from spi control register.
+        wire            wLoadShadows;           // shadow registers parallel load.
+
+                                                // not currently used.
+        wire    [ 7:0]  wGreenLEDBus7;          // green LED bus.
+        wire    [ 7:0]  wGreenLEDBus6;          // green LED bus.
+        wire    [ 7:0]  wGreenLEDBus5;          // green LED bus.
+        wire    [ 7:0]  wGreenLEDBus4;          // green LED bus.
+        wire    [ 7:0]  wGreenLEDBus3;          // green LED bus.
+        wire    [ 7:0]  wGreenLEDBus2;          // green LED bus.
+        wire    [ 7:0]  wGreenLEDBus1;          // green LED bus.
+        wire    [ 7:0]  wGreenLEDBus0;          // green LED bus.
+        wire            oDummyLoad;             // anti-optimization.
+        wire    [ 3:0]  wTrigger;               // trigger control.
+/*---------------------------------registers----//----------------------------*/
+/*---------------------------------variables----//----------------------------*/
+/*---------------------------------parameters---//----------------------------*/
+/*-----------------------------------clocks-----//----------------------------*/
+/*---------------------------------instances----//----------------------------*/
+
+//---   begin regular CPU section.
+
+
+        reg_08 U00_R0                           // CPU R0.              
+        (
+         .oParallel   (wR0),
+         .iParallel7  (wShadow0),
+         .iParallel6  (wR1 + wR2),              // adder.
+         .iParallel5  (wImmediate),
+         .iParallel4  (wR0),
+         .iParallel3  (wR3),
+         .iParallel2  (wR2),
+         .iParallel1  (wR1),
+         .iParallel0  (wR0),                    // needed for zero vector no-op.
+         .iSel        (wSel),
+         .oSerial     (),
+         .iSerial     (1'b0),
+         .iLoadEnable (wLER0),
+         .iShiftEnable(1'b0),
+         .iResetN     (wRstn),
+         .iClk        (iCPUclk)
+        );
+
+
+
+        reg_08 U01_R1                           // CPU R1.              
+        (
+         .oParallel   (wR1),
+         .iParallel7  (wShadow1),
+         .iParallel6  (wMMD[7:0]),
+         .iParallel5  (wImmediate),
+         .iParallel4  (wR1),
+         .iParallel3  (wR3),
+         .iParallel2  (wR2),
+         .iParallel1  (wR1),
+         .iParallel0  (wR0),
+         .iSel        (wSel),
+         .oSerial     (),
+         .iSerial     (1'b0),
+         .iLoadEnable (wLER1),
+         .iShiftEnable(1'b0),
+         .iResetN     (wRstn),
+         .iClk        (iCPUclk)
+        );
+
+
+
+        reg_08 U02_R2                           // CPU R2.              
+        (
+         .oParallel   (wR2),
+         .iParallel7  (wShadow2),
+         .iParallel6  (wMMD[15:8]),
+         .iParallel5  (wImmediate),
+         .iParallel4  (wR2),
+         .iParallel3  (wR3),
+         .iParallel2  (wR2),
+         .iParallel1  (wR1),
+         .iParallel0  (wR0),
+         .iSel        (wSel),
+         .oSerial     (),
+         .iSerial     (1'b0),
+         .iLoadEnable (wLER2),
+         .iShiftEnable(1'b0),
+         .iResetN     (wRstn),
+         .iClk        (iCPUclk)
+        );
+
+
+        reg_08 U03_R3                           // CPU R3.              
+        (
+         .oParallel   (wR3),
+         .iParallel7  (wShadow3),
+         .iParallel6  (wMMD[7:0]),
+         .iParallel5  (wImmediate),
+         .iParallel4  (wR3),
+         .iParallel3  (wR3),
+         .iParallel2  (wR2),
+         .iParallel1  (wR1),
+         .iParallel0  (wR0),
+         .iSel        (wSel),
+         .oSerial     (),
+         .iSerial     (1'b0),
+         .iLoadEnable (wLER3),
+         .iShiftEnable(1'b0),
+         .iResetN     (wRstn),
+         .iClk        (iCPUclk)
+        );
+
+
+
+        counter_08 U04_PC                       // CPU program counter.
+        (
+         .oCount      (wPC),
+         .iParallel7  (wShadowPC),
+         .iParallel6  (wMMD[7:0]),
+         .iParallel5  (wImmediate),
+         .iParallel4  (wPC),
+         .iParallel3  (wR3),
+         .iParallel2  (wR2),
+         .iParallel1  (wR1),
+         .iParallel0  (wR0),
+         .iSel        (wSel),
+         .oSerial     (),
+         .iSerial     (1'b0),
+         .iLoadEnable (wLEPC),
+         .iShiftEnable(1'b0),
+         .iCountEnable(wCEPC),
+         .iResetN     (wRstn),
+         .iClk        (iCPUclk)
+        );
+
+
+        reg_16 U05_IR                           // CPU instruction register.
+        (
+         .oParallel   (wIR),                    // IR state.
+         .iParallel1  (wShadowIR),              // IR shadow state.
+         .iParallel0  (wMMI),                   // MM output.
+         .iSel        (wSpiControl[2]),         // special control.
+         .oSerial     (),
+         .iSerial     (1'b0),
+         .iLoadEnable (wLEIR),
+         .iShiftEnable(1'b0),
+         .iResetN     (wRstn),
+         .iClk        (iCPUclk)
+        );
+
+
+        instruction_decoder U06_ID              // instruction decoder.
+        (
+         .iSquelch  (wSquelch),                 // squelch when writing to IR.
+         .iIR       (wIR),                      // instruction register.
+         .iBypass   (wShadowIR),                // IR bypass from SPI.
+         .iBypassIR (wBypassIR),                // bypass the IR.
+         .oSel      (wSel),                     // common data-in selector.
+         .oLER0     (wLER0),                    // R0 load-enable.
+         .oLER1     (wLER1),                    // R1 load-enable.
+         .oLER2     (wLER2),                    // R2 load-enable.
+         .oLER3     (wLER3),                    // R3 load-enable.
+         .oLEPC     (wLEPC),                    // PC load-enable.
+         .oWE       (wWE),                      // write-enable pulse.
+         .oCEPC     (wCEPC),                    // PC count-enable.
+         .oImmediate(wImmediate)                // immediate data.
+        );
+
+
+
+                                                // main memory:
+                                                // the program counter reads from read-port-0.
+                                                // the R2:R1 port reads from read-port-1.
+                                                // the R2:R1 port writes to the write port.
+                                                // the R2:R1 port reads/writes using address from R3.
+
+
+        main_memory U07_MM                      // main-memory.
+        (
+         .iReadAddress1(wR3),                   // from R3.
+         .iReadAddress0(wPC),                   // from PC
+         .iWriteAddress(wR3),                   // from R3
+         .oReadData1   (wMMD),                  // to <R2:R1>
+         .oReadData0   (wMMI),                  // to IR.
+         .iWriteData   ({wR2,wR1}),             // from <R2:R1>.
+         .iWE          (wWE),                   // from the instruction decoder.
+         .iCPUclk      (iCPUclk)
+        );
+
+
+                                                // load shadow-registers upon rising
+                                                // edge of first SPI clock following
+                                                // the falling edge of a CPU clock.
+        shadow_load_control U08_shadow_load     // shadow-register load control.
+        (
+         .iCPUclk(iCPUclk),
+         .iSPIclk(iSPIclk),
+         .iRstn(wRstn), 
+         .oLoadEnable(wLoadShadows)
+        );
+
+
+//---   begin SPI shadow-scan section.
+
+
+                                                // the SPI scan registers are generally
+                                                // given the term 'shadow registers'.
+
+
+        scan_08 U19_spi_control                 // top of SPI scan chain, used for control.
+        (
+         .oParallel   (wSpiControl),            // green LED select 7.
+         .iParallel   (wSpiControl),            // self-refresh.
+         .oSerial     (oMISO),
+         .iSerial     (wSR0),
+         .iLoadEnable (wLoadShadows),
+         .iShiftEnable(1'b1),
+         .iResetN     (wRstn),
+         .iClk        (iSPIclk)
+        );
+
+
+
+        scan_08 U20_shadowR0                    // R0 shadow register.
+        (
+         .oParallel   (wShadow0),               // green LED select 6.
+         .iParallel   (wR0),
+         .oSerial     (wSR0),
+         .iSerial     (wSR1),
+         .iLoadEnable (wLoadShadows),
+         .iShiftEnable(1'b1),
+         .iResetN     (wRstn),
+         .iClk        (iSPIclk)
+        );
+
+        scan_08 U21_shadowR1                    // R1 shadow register.
+        (
+         .oParallel   (wShadow1),               // green LED select 5.
+         .iParallel   (wR1),
+         .oSerial     (wSR1),
+         .iSerial     (wSR2),
+         .iLoadEnable (wLoadShadows),
+         .iShiftEnable(1'b1),
+         .iResetN     (wRstn),
+         .iClk        (iSPIclk)
+        );
+
+        scan_08 U22_shadowR2                    // R2 shadow register.
+        (
+         .oParallel   (wShadow2),               // green LED select 4.
+         .iParallel   (wR2),
+         .oSerial     (wSR2),
+         .iSerial     (wSR3),
+         .iLoadEnable (wLoadShadows),
+         .iShiftEnable(1'b1),
+         .iResetN     (wRstn),
+         .iClk        (iSPIclk)
+        );
+
+        scan_08 U23_shadowR3                    // R3 shadow register.
+        (
+         .oParallel   (wShadow3),               // green LED select 3.
+         .iParallel   (wR3),
+         .oSerial     (wSR3),
+         .iSerial     (wSPC),
+         .iLoadEnable (wLoadShadows),
+         .iShiftEnable(1'b1),
+         .iResetN     (wRstn),
+         .iClk        (iSPIclk)
+        );
+
+        scan_08 U24_shadowPC                    // program-counter shadow register.
+        (
+         .oParallel   (wShadowPC),              // green LED select 2.
+         .iParallel   (wPC),
+         .oSerial     (wSPC),
+         .iSerial     (wSIR),
+         .iLoadEnable (wLoadShadows),
+         .iShiftEnable(1'b1),
+         .iResetN     (wRstn),
+         .iClk        (iSPIclk)
+        );
+
+        scan_16 U25_shadowIR                    // instruction-register shadow register.
+        (
+         .oParallel   (wShadowIR),              // green LED select 1,0.
+         .iParallel   (wIR),
+         .oSerial     (wSIR),
+         .iSerial     (iMOSI),
+         .iLoadEnable (wLoadShadows),
+         .iShiftEnable(1'b1),
+         .iResetN     (wRstn),
+         .iClk        (iSPIclk)
+        );
+
+
+
+//---   begin green LED signal-monitoring section.
+
+
+
+        mux8x16 U30_green_led_mux               // green LED diagnostic mux.
+        (
+         .iDin15({wLER0,wLER1,wLER2,wLER3,wLEPC,wLEIR,wWE,wCEPC}),
+         .iDin14(wIR[15:8]),                    // IR-H.
+         .iDin13(wIR[7:0]),                     // IR-L.
+         .iDin12(wPC),                          // PC.
+         .iDin11(wR3),                          // R3.
+         .iDin10(wR2),                          // R2.
+         .iDin9 (wR1),                          // R1.
+         .iDin8 (wR0),                          // R0.
+         .iDin7 (wSpiControl),                  // SPI control.
+         .iDin6 (wShadowIR[15:8]),              // IR-H shadow.
+         .iDin5 (wShadowIR[7:0]),               // IR-L shadow.
+         .iDin4 (wShadowPC),                    // PC   shadow.
+         .iDin3 (wShadow3),                     // R3   shadow.
+         .iDin2 (wShadow2),                     // R2   shadow.
+         .iDin1 (wShadow1),                     // R1   shadow.
+         .iDin0 (wShadow0),                     // R0   shadow.
+         .iSel  (iSW[3:0]),                     // mux-select.
+         .oDout (oLEDG)                         // to green LED bank.
+        );
+/*-----------------------------------logic------//----------------------------*/
+        assign wRstn     = iKEY[0];             // pushbutton system reset.
+        assign wSquelch  = wSpiControl[2];      // for python squelching ins. decode.
+        assign wBypassIR = wSpiControl[1];      // for python controlling CPU.
+        assign wTrigger  = wSpiControl[7:4];    // for signaltap triggering, not used.
+
+                                                // load instruction register
+                                                // if neither or both shadow
+                                                // control signals asserted.
+        assign wLEIR     = !(wSquelch ^ wBypassIR);
+
+
+        assign oLEDR[9]  = 1'b0;                // red LED hookup.
+        assign oLEDR[8]  = 1'b0;
+        assign oLEDR[7]  = wSel[2];
+        assign oLEDR[6]  = wSel[1];
+        assign oLEDR[5]  = wSel[0];
+        assign oLEDR[4]  = wRstn;
+        assign oLEDR[3]  = iCPUclk;
+        assign oLEDR[2]  = oMISO;
+        assign oLEDR[1]  = iMOSI;
+        assign oLEDR[0]  = iSPIclk;
+
+
+                                                // signals not to be optimized
+                                                // out, place here.
+        assign oDummyLoad = (|wShadowIR) | wSIR | (|wSpiControl) | (|wTrigger);
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/instruction_decoder.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,202 @@
+/*----------------------------------copyright---------------------------------*/
+//      licensed for personal and academic use.
+//      commercial use must be approved by the account-holder of
+//      gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+        module instruction_decoder
+        (
+          iSquelch,                             // disrupt output enables.
+          iIR,                                  // instruction register.
+          iBypass,                              // instruction from SPI.
+          iBypassIR,                            // override the IR.
+          oSel,                                 // common data-in selector.
+          oLER0,                                // R0 load-enable.
+          oLER1,                                // R1 load-enable.
+          oLER2,                                // R2 load-enable.
+          oLER3,                                // R3 load-enable.
+          oLEPC,                                // PC load-enable.
+          oWE,                                  // write-enable pulse.
+          oCEPC,                                // PC count-enable.
+          oImmediate                            // immediate data.
+        );
+/*--------------------------------description-----------------------------------
+        the instruction decoder.  
+-------------------------------------notes--------------------------------------
+        this instruction decoder operates in three different 'modes'.
+        1. nominal mode: the instruction word is decoded as per the CPU spec.
+        2. regular test mode: the instruction register is ignored, and instead
+           this decoder makes use of iBypass, which is the instruction pattern
+           provided by the instruction word shadow register (which is part of
+           the spi scan chain).  this allows the python code to take over the
+           operation of the CPU.
+        3. IR-write test mode: a special-case mode which occurs when python
+           writes to the instruction register.  in this case, the outputs of
+           this decoder which are used to provide load-enables to CPU 
+           resources, must be squelched.  this is because we don't want the
+           python-written instruction register content to be decoded and
+           the decoded signals sent into the CPU.  why?  because most likely
+           the python-write to the IR is only to check that it can be done,
+           and if the result of such a write were allowed to propagate, then
+           the other registers may be arbitrarily updated, confusing the
+           user at the python end.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+        input           iSquelch;               // disrupt output enables.
+        input   [15:0]  iIR;                    // instruction register.
+        input   [15:0]  iBypass;                // instruction from SPI.
+        input           iBypassIR;              // override the IR.
+        output  [ 2:0]  oSel;                   // common data-in selector.
+        output          oLER0;                  // R0 load-enable.
+        output          oLER1;                  // R1 load-enable.
+        output          oLER2;                  // R2 load-enable.
+        output          oLER3;                  // R3 load-enable.
+        output          oLEPC;                  // PC load-enable.
+        output          oWE;                    // write-enable pulse.
+        output          oCEPC;                  // PC count-enable.
+        output  [ 7:0]  oImmediate;             // immediate data.
+/*-----------------------------------wires------------------------------------*/
+        wire            iSquelch;               // disrupt output enables.
+        wire    [15:0]  iIR;                    // instruction register.
+        wire    [15:0]  iBypass;                // instruction from SPI.
+        wire            iBypassIR;              // override the IR.
+        wire    [ 2:0]  oSel;                   // common data-in selector.
+        wire            oLER0;                  // R0 load-enable.
+        wire            oLER1;                  // R1 load-enable.
+        wire            oLER2;                  // R2 load-enable.
+        wire            oLER3;                  // R3 load-enable.
+        wire            oLEPC;                  // PC load-enable.
+        wire            oWE;                    // write-enable pulse.
+        wire            oCEPC;                  // PC count-enable.
+        wire    [ 7:0]  oImmediate;             // immediate data.
+/*---------------------------------registers----------------------------------*/
+        reg     [15:0]  rIR;                    // instruction.
+        reg             rLER0;                  // R0 load-enable.
+        reg             rLER1;                  // R1 load-enable.
+        reg             rLER2;                  // R2 load-enable.
+        reg             rLER3;                  // R3 load-enable.
+        reg             rLEPC;                  // PC load-enable.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+
+
+        always @ (rIR)
+        case     (rIR[12:10])                   // decode the load-enables.
+
+          7 : begin                             // no register.
+                rLER0  = 1'b0;
+                rLER1  = 1'b0;
+                rLER2  = 1'b0;
+                rLER3  = 1'b0;
+                rLEPC  = 1'b0;
+              end
+
+          6 : begin                             // no register.
+                rLER0  = 1'b0;
+                rLER1  = 1'b0;
+                rLER2  = 1'b0;
+                rLER3  = 1'b0;
+                rLEPC  = 1'b0;  
+              end
+
+          5 : begin                             // no register.
+                rLER0  = 1'b0;
+                rLER1  = 1'b0;
+                rLER2  = 1'b0;
+                rLER3  = 1'b0;
+                rLEPC  = 1'b0;          
+              end
+
+          4 : begin                             // PC
+                rLER0  = 1'b0;
+                rLER1  = 1'b0;
+                rLER2  = 1'b0;
+                rLER3  = 1'b0;
+                rLEPC  = 1'b1;                  
+              end
+
+          3 : begin                             // R3
+                rLER0  = 1'b0;
+                rLER1  = 1'b0;
+                rLER2  = 1'b0;
+                rLER3  = 1'b1;                  
+                rLEPC  = 1'b0;
+              end
+
+          2 : begin                             // R2
+                rLER0  = 1'b0;
+                rLER1  = 1'b0;
+                rLER2  = 1'b1;                  
+                rLER3  = 1'b0;
+                rLEPC  = 1'b0;
+              end
+
+          1 : begin                             // R1
+                rLER0  = 1'b0;
+                rLER1  = 1'b1;                  
+                rLER2  = 1'b0;
+                rLER3  = 1'b0;
+                rLEPC  = 1'b0;
+              end
+
+          0 : begin                             // R0
+                rLER0  = 1'b1;                  
+                rLER1  = 1'b0;
+                rLER2  = 1'b0;
+                rLER3  = 1'b0;
+                rLEPC  = 1'b0;
+              end
+
+         
+        endcase
+
+        assign oSel       = rIR[15:13];         // pass-through.
+        assign oLER0      = rLER0 & !iSquelch;  // decode iIR[12:10].
+        assign oLER1      = rLER1 & !iSquelch;  // decode iIR[12:10].
+        assign oLER2      = rLER2 & !iSquelch;  // decode iIR[12:10].
+        assign oLER3      = rLER3 & !iSquelch;  // decode iIR[12:10].
+        assign oLEPC      = rLEPC & !iSquelch;  // decode iIR[12:10].
+        assign oWE        = rIR[9] & !iSquelch; // pass-through.
+        assign oCEPC      = rIR[8] & !iSquelch; // pass-through.
+        assign oImmediate = rIR[7:0];           // pass-through.
+
+
+        always @ (iIR or iBypass or iBypassIR)
+        if (iBypassIR) rIR = iBypass;
+        else rIR = iIR;
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/main_memory.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,74 @@
+/*----------------------------------copyright---------------------------------*/
+//      licensed for personal and academic use.
+//      commercial use must be approved by the account-holder of
+//      gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+        module main_memory
+        (
+         iReadAddress1,                         // read-address 1.
+         iReadAddress0,                         // read-address 0.
+         iWriteAddress,                         // write-address.
+         oReadData1,                            // read-data 1.
+         oReadData0,                            // read-data 0.
+         iWriteData,                            // write-data.
+         iWE,                                   // write-enable.
+         iCPUclk                                // cpu clock.
+        );
+/*--------------------------------description-----------------------------------
+        CPU main memory.
+        two read-ports, one write-port.
+-------------------------------------notes--------------------------------------
+        level-sensitive write-enable.
+        the memory needs to be sixteen bits wide in order to hold
+        immediate data for the instruction set.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+        input   [ 7:0]  iReadAddress1;          // read-address 1.
+        input   [ 7:0]  iReadAddress0;          // read-address 0.
+        input   [ 7:0]  iWriteAddress;          // write-address.
+        output  [15:0]  oReadData1;             // read-data 1.
+        output  [15:0]  oReadData0;             // read-data 0.
+        input   [15:0]  iWriteData;             // write-data.
+        input           iWE;                    // write-enable.
+        input           iCPUclk;                // cpu clock.
+/*-----------------------------------wires------------------------------------*/
+        wire    [ 7:0]  iReadAddress1;          // read-address 1.
+        wire    [ 7:0]  iReadAddress0;          // read-address 0.
+        wire    [ 7:0]  iWriteAddress;          // write-address.
+        wire    [15:0]  oReadData1;             // read-data 1.
+        wire    [15:0]  oReadData0;             // read-data 0.
+        wire    [15:0]  iWriteData;             // write-data.
+        wire            iWE;                    // write-enable.
+        wire            iCPUclk;                // cpu clock.
+/*---------------------------------registers----------------------------------*/
+        reg     [15:0] mem_bank [0:255];        // memory bank.
+        reg     [15:0] rData1;                  // data-out-1 register.
+        reg     [15:0] rData0;                  // data-out-0 register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+        always @ (posedge iCPUclk) 
+        if (iWE) mem_bank[iWriteAddress] = iWriteData;
+        else     mem_bank[iWriteAddress] = mem_bank[iWriteAddress];
+
+        assign oReadData1 = mem_bank[iReadAddress1];
+        assign oReadData0 = mem_bank[iReadAddress0];
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/mux16x2.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,65 @@
+/*----------------------------------copyright---------------------------------*/
+//      licensed for personal and academic use.
+//      commercial use must be approved by the account-holder of
+//      gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+        module mux16x2
+        (
+          iDin1,                                // data-input 1.
+          iDin0,                                // data-input 0.
+          iSel,                                 // multiplexor select.
+          oDout                                 // data-out.
+        );
+/*--------------------------------description-----------------------------------
+        a 16-bit-wide, 2-selection multiplexor.
+-------------------------------------notes--------------------------------------
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+        input   [15:0]  iDin1;                  // data-input 1.
+        input   [15:0]  iDin0;                  // data-input 0.
+        input           iSel;                   // multiplexor select.
+        output  [15:0]  oDout;                  // data-out.
+/*-----------------------------------wires------------------------------------*/
+        wire    [15:0]  iDin1;                  // data-input 1.
+        wire    [15:0]  iDin0;                  // data-input 0.
+        wire            iSel;                   // multiplexor select.
+        wire    [15:0]  oDout;                  // data-out.
+/*---------------------------------registers----------------------------------*/
+        reg     [15:0]  rDout;                  // output register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+        always @ (iDin1 or iDin0 or iSel)
+        case (iSel)
+        1 : rDout = iDin1;
+        0 : rDout = iDin0;
+        endcase
+
+        assign oDout = rDout;                   // propagate output.
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/mux8x16.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,120 @@
+/*----------------------------------copyright---------------------------------*/
+//      licensed for personal and academic use.
+//      commercial use must be approved by the account-holder of
+//      gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+        module mux8x16
+        (
+          iDin15,                               // data-input 15.
+          iDin14,                               // data-input 14.
+          iDin13,                               // data-input 13.
+          iDin12,                               // data-input 12.
+          iDin11,                               // data-input 11.
+          iDin10,                               // data-input 10.
+          iDin9,                                // data-input 9.
+          iDin8,                                // data-input 8.
+          iDin7,                                // data-input 7.
+          iDin6,                                // data-input 6.
+          iDin5,                                // data-input 5.
+          iDin4,                                // data-input 4.
+          iDin3,                                // data-input 3.
+          iDin2,                                // data-input 2.
+          iDin1,                                // data-input 1.
+          iDin0,                                // data-input 0.
+          iSel,                                 // multiplexor select.
+          oDout                                 // data-out.
+        );
+/*--------------------------------description-----------------------------------
+        a 8-bit-wide, 16-selection multiplexor.
+-------------------------------------notes--------------------------------------
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+        input   [ 7:0]  iDin15;                 // data-input 15.
+        input   [ 7:0]  iDin14;                 // data-input 14.
+        input   [ 7:0]  iDin13;                 // data-input 13.
+        input   [ 7:0]  iDin12;                 // data-input 12.
+        input   [ 7:0]  iDin11;                 // data-input 11.
+        input   [ 7:0]  iDin10;                 // data-input 10.
+        input   [ 7:0]  iDin9;                  // data-input 9.
+        input   [ 7:0]  iDin8;                  // data-input 8.
+        input   [ 7:0]  iDin7;                  // data-input 7.
+        input   [ 7:0]  iDin6;                  // data-input 6.
+        input   [ 7:0]  iDin5;                  // data-input 5.
+        input   [ 7:0]  iDin4;                  // data-input 4.
+        input   [ 7:0]  iDin3;                  // data-input 3.
+        input   [ 7:0]  iDin2;                  // data-input 2.
+        input   [ 7:0]  iDin1;                  // data-input 1.
+        input   [ 7:0]  iDin0;                  // data-input 0.
+        input   [ 3:0]  iSel;                   // multiplexor select.
+        output  [ 7:0]  oDout;                  // data-out.
+/*-----------------------------------wires------------------------------------*/
+        wire    [ 7:0]  iDin15;                 // data-input 15.
+        wire    [ 7:0]  iDin14;                 // data-input 14.
+        wire    [ 7:0]  iDin13;                 // data-input 13.
+        wire    [ 7:0]  iDin12;                 // data-input 12.
+        wire    [ 7:0]  iDin11;                 // data-input 11.
+        wire    [ 7:0]  iDin10;                 // data-input 10.
+        wire    [ 7:0]  iDin9;                  // data-input 9.
+        wire    [ 7:0]  iDin8;                  // data-input 8.
+        wire    [ 7:0]  iDin7;                  // data-input 7.
+        wire    [ 7:0]  iDin6;                  // data-input 6.
+        wire    [ 7:0]  iDin5;                  // data-input 5.
+        wire    [ 7:0]  iDin4;                  // data-input 4.
+        wire    [ 7:0]  iDin3;                  // data-input 3.
+        wire    [ 7:0]  iDin2;                  // data-input 2.
+        wire    [ 7:0]  iDin1;                  // data-input 1.
+        wire    [ 7:0]  iDin0;                  // data-input 0.
+        wire    [ 3:0]  iSel;                   // multiplexor select.
+        wire    [ 7:0]  oDout;                  // data-out.
+/*---------------------------------registers----------------------------------*/
+        reg     [ 7:0]  rDout;                  // output register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+
+        always @ (iDin15 or iDin14 or iDin13 or iDin12 or
+                  iDin11 or iDin10 or iDin9  or iDin8  or
+                  iDin7  or iDin6  or iDin5  or iDin4  or
+                  iDin3  or iDin2  or iDin1  or iDin0  or iSel)
+        case (iSel)
+        15 : rDout = iDin15;
+        14 : rDout = iDin14;
+        13 : rDout = iDin13;
+        12 : rDout = iDin12;
+        11 : rDout = iDin11;
+        10 : rDout = iDin10;
+         9 : rDout = iDin9;
+         8 : rDout = iDin8;
+         7 : rDout = iDin7;
+         6 : rDout = iDin6;
+         5 : rDout = iDin5;
+         4 : rDout = iDin4;
+         3 : rDout = iDin3;
+         2 : rDout = iDin2;
+         1 : rDout = iDin1;
+         0 : rDout = iDin0;
+        endcase
+
+        assign oDout = rDout;                   // propagate output.
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/mux8x8.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,87 @@
+/*----------------------------------copyright---------------------------------*/
+//      licensed for personal and academic use.
+//      commercial use must be approved by the account-holder of
+//      gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+        module mux8x8
+        (
+          iDin7,                                // data-input 7.
+          iDin6,                                // data-input 6.
+          iDin5,                                // data-input 5.
+          iDin4,                                // data-input 4.
+          iDin3,                                // data-input 3.
+          iDin2,                                // data-input 2.
+          iDin1,                                // data-input 1.
+          iDin0,                                // data-input 0.
+          iSel,                                 // multiplexor select.
+          oDout                                 // data-out.
+        );
+/*--------------------------------description-----------------------------------
+        an 8-bit-wide, 8-selection multiplexor.
+-------------------------------------notes--------------------------------------
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+        input   [ 7:0]  iDin7;                  // data-input 7.
+        input   [ 7:0]  iDin6;                  // data-input 6.
+        input   [ 7:0]  iDin5;                  // data-input 5.
+        input   [ 7:0]  iDin4;                  // data-input 4.
+        input   [ 7:0]  iDin3;                  // data-input 3.
+        input   [ 7:0]  iDin2;                  // data-input 2.
+        input   [ 7:0]  iDin1;                  // data-input 1.
+        input   [ 7:0]  iDin0;                  // data-input 0.
+        input   [ 2:0]  iSel;                   // multiplexor select.
+        output  [ 7:0]  oDout;                  // data-out.
+/*-----------------------------------wires------------------------------------*/
+        wire    [ 7:0]  iDin7;                  // data-input 7.
+        wire    [ 7:0]  iDin6;                  // data-input 6.
+        wire    [ 7:0]  iDin5;                  // data-input 5.
+        wire    [ 7:0]  iDin4;                  // data-input 4.
+        wire    [ 7:0]  iDin3;                  // data-input 3.
+        wire    [ 7:0]  iDin2;                  // data-input 2.
+        wire    [ 7:0]  iDin1;                  // data-input 1.
+        wire    [ 7:0]  iDin0;                  // data-input 0.
+        wire    [ 2:0]  iSel;                   // multiplexor select.
+        wire    [ 7:0]  oDout;                  // data-out.
+/*---------------------------------registers----------------------------------*/
+        reg     [ 7:0]  rDout;                  // output register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+        always @ (iDin7 or iDin6 or iDin5 or iDin4 or
+                  iDin3 or iDin2 or iDin1 or iDin0 or iSel)
+        case (iSel)
+        7 : rDout = iDin7;
+        6 : rDout = iDin6;
+        5 : rDout = iDin5;
+        4 : rDout = iDin4;
+        3 : rDout = iDin3;
+        2 : rDout = iDin2;
+        1 : rDout = iDin1;
+        0 : rDout = iDin0;
+        endcase
+
+        assign oDout = rDout;                   // propagate output.
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/reg_08.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,128 @@
+/*----------------------------------copyright---------------------------------*/
+//      licensed for personal and academic use.
+//      commercial use must be approved by the account-holder of
+//      gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+        module reg_08
+        (
+         oParallel,                             // parallel-output data.
+         iParallel7,                            // parallel-input  data.
+         iParallel6,                            // parallel-input  data.
+         iParallel5,                            // parallel-input  data.
+         iParallel4,                            // parallel-input  data.
+         iParallel3,                            // parallel-input  data.
+         iParallel2,                            // parallel-input  data.
+         iParallel1,                            // parallel-input  data.
+         iParallel0,                            // parallel-input  data.
+         iSel,                                  // select the parallel input.
+         oSerial,                               // serial-output data.
+         iSerial,                               // serial-input data.
+         iLoadEnable,                           // parallel-load-enable.
+         iShiftEnable,                          // serial-shift-enable.
+         iResetN,                               // synchronous reset*.
+         iClk                                   // module clock.
+        );
+/*--------------------------------description-----------------------------------
+        an 8-bit parallel shift-register with 8 selectable input buses.
+-------------------------------------notes--------------------------------------
+        shifting is LSB->MSB.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+        output  [ 7:0]  oParallel;              // parallel-output data.
+        input   [ 7:0]  iParallel7;             // parallel-input  data.
+        input   [ 7:0]  iParallel6;             // parallel-input  data.
+        input   [ 7:0]  iParallel5;             // parallel-input  data.
+        input   [ 7:0]  iParallel4;             // parallel-input  data.
+        input   [ 7:0]  iParallel3;             // parallel-input  data.
+        input   [ 7:0]  iParallel2;             // parallel-input  data.
+        input   [ 7:0]  iParallel1;             // parallel-input  data.
+        input   [ 7:0]  iParallel0;             // parallel-input  data.
+        input   [ 2:0]  iSel;                   // select the parallel input.
+        output          oSerial;                // serial-output data.
+        input           iSerial;                // serial-input data.
+        input           iLoadEnable;            // parallel-load-enable.
+        input           iShiftEnable;           // serial-shift-enable.
+        input           iResetN;                // synchronous reset*.
+        input           iClk;                   // module clock.
+/*-----------------------------------wires------------------------------------*/
+        wire    [ 7:0]  oParallel;              // parallel-output data.
+        wire    [ 7:0]  iParallel7;             // parallel-input  data.
+        wire    [ 7:0]  iParallel6;             // parallel-input  data.
+        wire    [ 7:0]  iParallel5;             // parallel-input  data.
+        wire    [ 7:0]  iParallel4;             // parallel-input  data.
+        wire    [ 7:0]  iParallel3;             // parallel-input  data.
+        wire    [ 7:0]  iParallel2;             // parallel-input  data.
+        wire    [ 7:0]  iParallel1;             // parallel-input  data.
+        wire    [ 7:0]  iParallel0;             // parallel-input  data.
+        wire    [ 2:0]  iSel;                   // select the parallel input.
+        wire    [ 7:0]  wParallelIn;            // select the parallel input.
+        wire            oSerial;                // serial-output data.
+        wire            iSerial;                // serial-input data.
+        wire            iLoadEnable;            // parallel-load-enable.
+        wire            iShiftEnable;           // serial-shift-enable.
+        wire            iResetN;                // synchronous reset*.
+        wire            iClk;                   // module clock.
+/*---------------------------------registers----------------------------------*/
+        reg     [ 7:0]  rRegister;              // the register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+        mux8x8 U01_mux8x8                       // data-input selection.
+        (
+         .iDin7(iParallel7),
+         .iDin6(iParallel6),
+         .iDin5(iParallel5),
+         .iDin4(iParallel4),
+         .iDin3(iParallel3),
+         .iDin2(iParallel2),
+         .iDin1(iParallel1),
+         .iDin0(iParallel0),
+         .iSel (iSel),
+         .oDout(wParallelIn)
+        );
+/*-----------------------------------logic------------------------------------*/
+        always @ (posedge iClk or negedge iResetN)
+        begin
+               if (!iResetN)     rRegister <= 8'h00;
+          else if (iLoadEnable)  rRegister <= wParallelIn;
+          else if (iShiftEnable) rRegister <= {rRegister[6:0], iSerial};
+          else                   rRegister <= rRegister;
+        end
+
+        assign oParallel = rRegister;           // propagate parallel-out.
+        assign oSerial   = rRegister[7];        // propagate serial-out.
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/reg_16.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,72 @@
+/*----------------------------------copyright---------------------------------*/
+//      licensed for personal and academic use.
+//      commercial use must be approved by the account-holder of
+//      gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+        module reg_16
+        (
+         oParallel,                             // parallel-output data.
+         iParallel1,                            // parallel-input  data.
+         iParallel0,                            // parallel-input  data.
+         iSel,                                  // select the parallel input.
+         oSerial,                               // serial-output data.
+         iSerial,                               // serial-input data.
+         iLoadEnable,                           // parallel-load-enable.
+         iShiftEnable,                          // serial-shift-enable.
+         iResetN,                               // synchronous reset*.
+         iClk                                   // module clock.
+        );
+/*--------------------------------description-----------------------------------
+        a 16-bit parallel shift-register with 2 selectable input buses.
+-------------------------------------notes--------------------------------------
+        shifting is LSB->MSB.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+        output  [15:0]  oParallel;              // parallel-output data.
+        input   [15:0]  iParallel1;             // parallel-input  data.
+        input   [15:0]  iParallel0;             // parallel-input  data.
+        input           iSel;                   // select the parallel input.
+        output          oSerial;                // serial-output data.
+        input           iSerial;                // serial-input data.
+        input           iLoadEnable;            // parallel-load-enable.
+        input           iShiftEnable;           // serial-shift-enable.
+        input           iResetN;                // synchronous reset*.
+        input           iClk;                   // module clock.
+/*-----------------------------------wires------------------------------------*/
+        wire    [15:0]  oParallel;              // parallel-output data.
+        wire    [15:0]  iParallel1;             // parallel-input  data.
+        wire    [15:0]  iParallel0;             // parallel-input  data.
+        wire            iSel;                   // select the parallel input.
+        wire    [15:0]  wParallelIn;            // select the parallel input.
+        wire            oSerial;                // serial-output data.
+        wire            iSerial;                // serial-input data.
+        wire            iLoadEnable;            // parallel-load-enable.
+        wire            iShiftEnable;           // serial-shift-enable.
+        wire            iResetN;                // synchronous reset*.
+        wire            iClk;                   // module clock.
+/*---------------------------------registers----------------------------------*/
+        reg     [15:0]  rRegister;              // the register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+        mux16x2 U0_mux16x2                      // data-input selection.
+        (
+         .iDin1(iParallel1),
+         .iDin0(iParallel0),
+         .iSel (iSel),
+         .oDout(wParallelIn)
+        );
+/*-----------------------------------logic------------------------------------*/
+        always @ (posedge iClk or negedge iResetN)
+        begin
+               if (!iResetN)     rRegister <= 16'h0000;
+          else if (iLoadEnable)  rRegister <= wParallelIn;
+          else if (iShiftEnable) rRegister <= {rRegister[14:0], iSerial};
+          else                   rRegister <= rRegister;
+        end
+
+        assign oParallel = rRegister;           // propagate parallel-out.
+        assign oSerial   = rRegister[15];       // propagate serial-out.
+/*-------------------------------*/endmodule/*--------------------------------*/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/scan_08.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,75 @@
+/*----------------------------------copyright---------------------------------*/
+//      licensed for personal and academic use.
+//      commercial use must be approved by the account-holder of
+//      gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+        module scan_08                          // shadow register.
+        (
+         oParallel,                             // parallel-output data.
+         iParallel,                             // parallel-input  data.
+         oSerial,                               // serial-output data.
+         iSerial,                               // serial-input data.
+         iLoadEnable,                           // parallel-load-enable.
+         iShiftEnable,                          // serial-shift-enable.
+         iResetN,                               // synchronous reset*.
+         iClk                                   // module clock.
+        );
+/*--------------------------------description-----------------------------------
+        an 8-bit parallel shift-register.
+-------------------------------------notes--------------------------------------
+        shifting is LSB->MSB.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+        output  [ 7:0]  oParallel;              // parallel-output data.
+        input   [ 7:0]  iParallel;              // parallel-input  data.
+        output          oSerial;                // serial-output data.
+        input           iSerial;                // serial-input data.
+        input           iLoadEnable;            // parallel-load-enable.
+        input           iShiftEnable;           // serial-shift-enable.
+        input           iResetN;                // synchronous reset*.
+        input           iClk;                   // module clock.
+/*-----------------------------------wires------------------------------------*/
+        wire    [ 7:0]  oParallel;              // parallel-output data.
+        wire    [ 7:0]  iParallel;              // parallel-input  data.
+        wire    [ 7:0]  wParallelIn;            // select the parallel input.
+        wire            oSerial;                // serial-output data.
+        wire            iSerial;                // serial-input data.
+        wire            iLoadEnable;            // parallel-load-enable.
+        wire            iShiftEnable;           // serial-shift-enable.
+        wire            iResetN;                // synchronous reset*.
+        wire            iClk;                   // module clock.
+/*---------------------------------registers----------------------------------*/
+        reg     [ 7:0]  rRegister;              // the register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+        always @ (posedge iClk or negedge iResetN)
+        begin
+               if (!iResetN)     rRegister <= 8'h00;
+          else if (iLoadEnable)  rRegister <= iParallel;
+          else if (iShiftEnable) rRegister <= {rRegister[6:0], iSerial};
+          else                   rRegister <= rRegister;
+        end
+
+        assign oParallel = rRegister;           // propagate parallel-out.
+        assign oSerial   = rRegister[7];        // propagate serial-out.
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/scan_16.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,77 @@
+/*----------------------------------copyright---------------------------------*/
+//      licensed for personal and academic use.
+//      commercial use must be approved by the account-holder of
+//      gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+        module scan_16                          // shadow register.
+        (
+         oParallel,                             // parallel-output data.
+         iParallel,                             // parallel-input  data.
+         oSerial,                               // serial-output data.
+         iSerial,                               // serial-input data.
+         iLoadEnable,                           // parallel-load-enable.
+         iShiftEnable,                          // serial-shift-enable.
+         iResetN,                               // synchronous reset*.
+         iClk                                   // module clock.
+        );
+/*--------------------------------description-----------------------------------
+        a 16-bit parallel shift-register.
+-------------------------------------notes--------------------------------------
+        shifting is LSB->MSB.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+        output  [15:0]  oParallel;              // parallel-output data.
+        input   [15:0]  iParallel;              // parallel-input  data.
+        output          oSerial;                // serial-output data.
+        input           iSerial;                // serial-input data.
+        input           iLoadEnable;            // parallel-load-enable.
+        input           iShiftEnable;           // serial-shift-enable.
+        input           iResetN;                // synchronous reset*.
+        input           iClk;                   // module clock.
+/*-----------------------------------wires------------------------------------*/
+        wire    [15:0]  oParallel;              // parallel-output data.
+        wire    [15:0]  iParallel;              // parallel-input  data.
+        wire    [15:0]  wParallelIn;            // select the parallel input.
+        wire            oSerial;                // serial-output data.
+        wire            iSerial;                // serial-input data.
+        wire            iLoadEnable;            // parallel-load-enable.
+        wire            iShiftEnable;           // serial-shift-enable.
+        wire            iResetN;                // synchronous reset*.
+        wire            iClk;                   // module clock.
+/*---------------------------------registers----------------------------------*/
+        reg     [15:0]  rRegister;              // the register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+        always @ (posedge iClk or negedge iResetN)
+        begin
+               if (!iResetN)     rRegister[15:0] <= 16'h0000;
+          else if (iLoadEnable)  rRegister[15:0] <= iParallel[15:0];
+          else if (iShiftEnable) rRegister[15:0] <= {rRegister[14:0], iSerial};
+          else                   rRegister[15:0] <= rRegister[15:0];
+        end
+
+                                                // propagate parallel-out.
+        assign oParallel[15:0] = rRegister[15:0];               
+        assign oSerial   = rRegister[15];       // propagate serial-out.
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/shadow_load_control.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,82 @@
+/*----------------------------------copyright---------------------------------*/
+//      licensed for personal and academic use.
+//      commercial use must be approved by the account-holder of
+//      gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+        module shadow_load_control
+        (
+          iCPUclk,
+          iSPIclk,
+          iRstn,                                // direct clear.
+          oLoadEnable                           // shadow registers load enable.
+        );
+/*--------------------------------description-----------------------------------
+        when the CPU clock goes low, the CPU state is stable, and its time
+        for the SPI shadow registers to do a parallel load of the CPU state,
+        so its time to turn on the load-enable signal.
+
+        when the first SPI clock goes high, the parallel load completes and
+        its time to turn off the load-enable signal.
+-------------------------------------notes--------------------------------------
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+        input           iCPUclk;
+        input           iSPIclk;
+        input           iRstn;                  // direct clear.
+        output          oLoadEnable;            // shadow registers load enable.
+/*-----------------------------------wires------------------------------------*/
+        wire            iCPUclk;
+        wire            iSPIclk;
+        wire            iRstn;                  // direct clear.
+        wire            oLoadEnable;            // shadow registers load enable.
+
+        wire            wOrClock;               // OR the clocks.
+/*---------------------------------registers----------------------------------*/
+        reg            rRegister;
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+        always @ (negedge wOrClock or negedge iRstn)
+        begin
+               if (!iRstn   ) rRegister <= 1'b0;
+          else if (!wOrClock) rRegister <= !iSPIclk;
+        end
+
+        assign wOrClock    =  iCPUclk | iSPIclk;
+        assign oLoadEnable =  rRegister;
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmSPI.lib	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,1 @@
+mmSPI#adca2b413bf1
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmTestResult/clock_count.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,5 @@
+    related to testlog.txt,
+    the number of clock cycles was
+
+    326,480,840 SPI clocks.
+      4,798,920 CPU clocks.
\ No newline at end of file
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmTestResult/dump_add_list.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,256 @@
+  0x00  0xADD0
+  0x01  0xC500
+  0x02  0x2100
+  0x03  0xADE0
+  0x04  0xC500
+  0x05  0x0900
+  0x06  0xC100
+  0x07  0xADF0
+  0x08  0xA900
+  0x09  0x0500
+  0x0a  0x0300
+  0x0b  0x0100
+  0x0c  0xADD1
+  0x0d  0xC500
+  0x0e  0x2100
+  0x0f  0xADE1
+  0x10  0xC500
+  0x11  0x0900
+  0x12  0xC100
+  0x13  0xADF1
+  0x14  0xA900
+  0x15  0x0500
+  0x16  0x0300
+  0x17  0x0100
+  0x18  0xADD2
+  0x19  0xC500
+  0x1a  0x2100
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+  0xfc  0x00D1
+  0xfd  0x00F2
+  0xfe  0x0013
+  0xff  0x0034
\ No newline at end of file
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmTestResult/testlog.txt	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,4640 @@
+============================
+Sat Aug 31 21:16:10 PDT 2013
+test iteration 1
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:17:00 PDT 2013
+test iteration 2
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:17:50 PDT 2013
+test iteration 3
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:18:40 PDT 2013
+test iteration 4
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:19:30 PDT 2013
+test iteration 5
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:20:20 PDT 2013
+test iteration 6
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:21:10 PDT 2013
+test iteration 7
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:22:00 PDT 2013
+test iteration 8
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:22:50 PDT 2013
+test iteration 9
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:23:40 PDT 2013
+test iteration 10
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:24:30 PDT 2013
+test iteration 11
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:25:20 PDT 2013
+test iteration 12
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:26:10 PDT 2013
+test iteration 13
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:27:00 PDT 2013
+test iteration 14
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:27:50 PDT 2013
+test iteration 15
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:28:40 PDT 2013
+test iteration 16
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:29:30 PDT 2013
+test iteration 17
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:30:20 PDT 2013
+test iteration 18
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:31:10 PDT 2013
+test iteration 19
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:32:00 PDT 2013
+test iteration 20
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:32:50 PDT 2013
+test iteration 21
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:33:40 PDT 2013
+test iteration 22
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:34:30 PDT 2013
+test iteration 23
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:35:20 PDT 2013
+test iteration 24
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:36:10 PDT 2013
+test iteration 25
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:36:59 PDT 2013
+test iteration 26
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:37:49 PDT 2013
+test iteration 27
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:38:39 PDT 2013
+test iteration 28
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:39:29 PDT 2013
+test iteration 29
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:40:19 PDT 2013
+test iteration 30
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:41:09 PDT 2013
+test iteration 31
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:41:59 PDT 2013
+test iteration 32
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:42:49 PDT 2013
+test iteration 33
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:43:39 PDT 2013
+test iteration 34
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:44:29 PDT 2013
+test iteration 35
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:45:19 PDT 2013
+test iteration 36
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:46:09 PDT 2013
+test iteration 37
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:46:59 PDT 2013
+test iteration 38
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:47:49 PDT 2013
+test iteration 39
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:48:39 PDT 2013
+test iteration 40
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:49:29 PDT 2013
+test iteration 41
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:50:19 PDT 2013
+test iteration 42
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:51:09 PDT 2013
+test iteration 43
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:51:59 PDT 2013
+test iteration 44
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:52:49 PDT 2013
+test iteration 45
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:53:39 PDT 2013
+test iteration 46
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:54:29 PDT 2013
+test iteration 47
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:55:19 PDT 2013
+test iteration 48
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:56:09 PDT 2013
+test iteration 49
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:56:59 PDT 2013
+test iteration 50
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:57:49 PDT 2013
+test iteration 51
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:58:39 PDT 2013
+test iteration 52
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 21:59:29 PDT 2013
+test iteration 53
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:00:18 PDT 2013
+test iteration 54
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:01:08 PDT 2013
+test iteration 55
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:01:58 PDT 2013
+test iteration 56
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:02:48 PDT 2013
+test iteration 57
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:03:38 PDT 2013
+test iteration 58
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:04:28 PDT 2013
+test iteration 59
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:05:18 PDT 2013
+test iteration 60
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:06:08 PDT 2013
+test iteration 61
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:06:58 PDT 2013
+test iteration 62
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:07:48 PDT 2013
+test iteration 63
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:08:38 PDT 2013
+test iteration 64
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:09:28 PDT 2013
+test iteration 65
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:10:18 PDT 2013
+test iteration 66
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:11:08 PDT 2013
+test iteration 67
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:11:58 PDT 2013
+test iteration 68
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:12:48 PDT 2013
+test iteration 69
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:13:38 PDT 2013
+test iteration 70
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:14:28 PDT 2013
+test iteration 71
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:15:18 PDT 2013
+test iteration 72
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:16:08 PDT 2013
+test iteration 73
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:16:58 PDT 2013
+test iteration 74
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:17:48 PDT 2013
+test iteration 75
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:18:38 PDT 2013
+test iteration 76
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:19:28 PDT 2013
+test iteration 77
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:20:18 PDT 2013
+test iteration 78
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:21:07 PDT 2013
+test iteration 79
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:21:57 PDT 2013
+test iteration 80
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:22:47 PDT 2013
+test iteration 81
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:23:37 PDT 2013
+test iteration 82
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:24:27 PDT 2013
+test iteration 83
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:25:17 PDT 2013
+test iteration 84
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:26:07 PDT 2013
+test iteration 85
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:26:57 PDT 2013
+test iteration 86
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:27:47 PDT 2013
+test iteration 87
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:28:37 PDT 2013
+test iteration 88
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:29:27 PDT 2013
+test iteration 89
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:30:17 PDT 2013
+test iteration 90
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:31:07 PDT 2013
+test iteration 91
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:31:57 PDT 2013
+test iteration 92
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:32:47 PDT 2013
+test iteration 93
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:33:37 PDT 2013
+test iteration 94
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:34:27 PDT 2013
+test iteration 95
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:35:17 PDT 2013
+test iteration 96
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:36:07 PDT 2013
+test iteration 97
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:36:57 PDT 2013
+test iteration 98
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:37:47 PDT 2013
+test iteration 99
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:38:37 PDT 2013
+test iteration 100
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:39:27 PDT 2013
+test iteration 101
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:40:17 PDT 2013
+test iteration 102
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:41:07 PDT 2013
+test iteration 103
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:41:56 PDT 2013
+test iteration 104
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:42:46 PDT 2013
+test iteration 105
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:43:36 PDT 2013
+test iteration 106
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:44:26 PDT 2013
+test iteration 107
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:45:16 PDT 2013
+test iteration 108
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:46:06 PDT 2013
+test iteration 109
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:46:56 PDT 2013
+test iteration 110
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:47:46 PDT 2013
+test iteration 111
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:48:36 PDT 2013
+test iteration 112
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:49:26 PDT 2013
+test iteration 113
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:50:16 PDT 2013
+test iteration 114
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:51:06 PDT 2013
+test iteration 115
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:51:56 PDT 2013
+test iteration 116
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:52:46 PDT 2013
+test iteration 117
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:53:36 PDT 2013
+test iteration 118
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:54:26 PDT 2013
+test iteration 119
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:55:16 PDT 2013
+test iteration 120
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:56:06 PDT 2013
+test iteration 121
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:56:56 PDT 2013
+test iteration 122
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:57:46 PDT 2013
+test iteration 123
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:58:36 PDT 2013
+test iteration 124
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 22:59:26 PDT 2013
+test iteration 125
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 23:00:16 PDT 2013
+test iteration 126
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 23:01:06 PDT 2013
+test iteration 127
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 23:01:55 PDT 2013
+test iteration 128
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 23:02:45 PDT 2013
+test iteration 129
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 23:03:35 PDT 2013
+test iteration 130
+compare dump_test.txt against dump_add_list.txt
+============================
+Sat Aug 31 23:04:25 PDT 2013
+test iteration 131
+compare dump_test.txt against dump_add_list.txt
+============================
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+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:10:46 PDT 2013
+test iteration 715
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:11:36 PDT 2013
+test iteration 716
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:12:26 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:13:16 PDT 2013
+test iteration 718
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:14:06 PDT 2013
+test iteration 719
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:14:55 PDT 2013
+test iteration 720
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:15:45 PDT 2013
+test iteration 721
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:16:35 PDT 2013
+test iteration 722
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:17:25 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:18:15 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:19:05 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:19:55 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:20:45 PDT 2013
+test iteration 727
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:21:35 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:22:25 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:23:15 PDT 2013
+test iteration 730
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:24:05 PDT 2013
+test iteration 731
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:24:55 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:25:45 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:26:35 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:27:25 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:28:15 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:29:05 PDT 2013
+test iteration 737
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:29:55 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:30:45 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:34:55 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:35:45 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:37:25 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:38:14 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:39:04 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:39:54 PDT 2013
+test iteration 750
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:40:44 PDT 2013
+test iteration 751
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:41:34 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:43:14 PDT 2013
+test iteration 754
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:44:04 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:44:54 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:45:44 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:46:34 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:47:24 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:48:14 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:49:54 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:50:44 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:51:34 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:52:24 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:53:14 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:54:04 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:54:54 PDT 2013
+test iteration 768
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:55:44 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:58:14 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:59:04 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 07:59:53 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:00:43 PDT 2013
+test iteration 775
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:01:33 PDT 2013
+test iteration 776
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:02:23 PDT 2013
+test iteration 777
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:03:13 PDT 2013
+test iteration 778
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:04:03 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:04:53 PDT 2013
+test iteration 780
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:05:43 PDT 2013
+test iteration 781
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:06:33 PDT 2013
+test iteration 782
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:07:23 PDT 2013
+test iteration 783
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:08:13 PDT 2013
+test iteration 784
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:09:03 PDT 2013
+test iteration 785
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:09:53 PDT 2013
+test iteration 786
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:10:43 PDT 2013
+test iteration 787
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:11:33 PDT 2013
+test iteration 788
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:12:23 PDT 2013
+test iteration 789
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:13:13 PDT 2013
+test iteration 790
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:14:03 PDT 2013
+test iteration 791
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:14:53 PDT 2013
+test iteration 792
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:15:43 PDT 2013
+test iteration 793
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:16:33 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:17:23 PDT 2013
+test iteration 795
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:18:13 PDT 2013
+test iteration 796
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:19:03 PDT 2013
+test iteration 797
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:19:53 PDT 2013
+test iteration 798
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:20:43 PDT 2013
+test iteration 799
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:21:33 PDT 2013
+test iteration 800
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:22:22 PDT 2013
+test iteration 801
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:23:12 PDT 2013
+test iteration 802
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:24:02 PDT 2013
+test iteration 803
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:24:52 PDT 2013
+test iteration 804
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:25:42 PDT 2013
+test iteration 805
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:26:32 PDT 2013
+test iteration 806
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:27:22 PDT 2013
+test iteration 807
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:28:12 PDT 2013
+test iteration 808
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:29:02 PDT 2013
+test iteration 809
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:29:52 PDT 2013
+test iteration 810
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:30:42 PDT 2013
+test iteration 811
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:31:32 PDT 2013
+test iteration 812
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:32:22 PDT 2013
+test iteration 813
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:33:12 PDT 2013
+test iteration 814
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:34:02 PDT 2013
+test iteration 815
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:34:52 PDT 2013
+test iteration 816
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:35:42 PDT 2013
+test iteration 817
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:36:32 PDT 2013
+test iteration 818
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:37:22 PDT 2013
+test iteration 819
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:38:12 PDT 2013
+test iteration 820
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:39:02 PDT 2013
+test iteration 821
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:39:52 PDT 2013
+test iteration 822
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:40:42 PDT 2013
+test iteration 823
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:41:32 PDT 2013
+test iteration 824
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:42:22 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:43:12 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:44:02 PDT 2013
+test iteration 827
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:44:52 PDT 2013
+test iteration 828
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:45:42 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:46:32 PDT 2013
+test iteration 830
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:47:22 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:48:12 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:49:02 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:49:51 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:50:41 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:51:31 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:52:21 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:53:11 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:54:01 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:54:51 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:55:41 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:56:31 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:58:11 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:59:01 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 08:59:51 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:00:41 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:01:31 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:02:21 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:03:11 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:04:01 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:04:51 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:05:41 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:06:31 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:07:21 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:08:11 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:09:01 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:09:51 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:10:41 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:11:31 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:12:21 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:13:11 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:14:00 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:14:50 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:15:40 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:16:30 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:19:00 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:19:50 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:20:40 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:21:30 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:22:20 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:24:50 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:25:40 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:28:10 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:29:50 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:30:40 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:31:30 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:32:20 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:33:10 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:34:50 PDT 2013
+test iteration 888
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:35:40 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:36:30 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:37:20 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:38:10 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:39:00 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:39:50 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:40:39 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:41:29 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:42:19 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:44:49 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:45:39 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:46:29 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:47:19 PDT 2013
+test iteration 903
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:48:09 PDT 2013
+test iteration 904
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 09:48:59 PDT 2013
+test iteration 905
+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 11:08:06 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 11:08:55 PDT 2013
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+============================
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+============================
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+============================
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+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+============================
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+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
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+============================
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+============================
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+============================
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+============================
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+============================
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+============================
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+============================
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+============================
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+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:27:12 PDT 2013
+test iteration 1095
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:28:02 PDT 2013
+test iteration 1096
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:28:52 PDT 2013
+test iteration 1097
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:29:42 PDT 2013
+test iteration 1098
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:30:32 PDT 2013
+test iteration 1099
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:31:22 PDT 2013
+test iteration 1100
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:32:12 PDT 2013
+test iteration 1101
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:33:02 PDT 2013
+test iteration 1102
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:33:52 PDT 2013
+test iteration 1103
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:34:42 PDT 2013
+test iteration 1104
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:35:32 PDT 2013
+test iteration 1105
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:36:22 PDT 2013
+test iteration 1106
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:37:12 PDT 2013
+test iteration 1107
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:38:02 PDT 2013
+test iteration 1108
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:38:52 PDT 2013
+test iteration 1109
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:39:42 PDT 2013
+test iteration 1110
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:40:32 PDT 2013
+test iteration 1111
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:41:22 PDT 2013
+test iteration 1112
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:42:12 PDT 2013
+test iteration 1113
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:43:02 PDT 2013
+test iteration 1114
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:43:52 PDT 2013
+test iteration 1115
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:44:41 PDT 2013
+test iteration 1116
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:45:31 PDT 2013
+test iteration 1117
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:46:21 PDT 2013
+test iteration 1118
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:47:11 PDT 2013
+test iteration 1119
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:48:01 PDT 2013
+test iteration 1120
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:48:51 PDT 2013
+test iteration 1121
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:49:41 PDT 2013
+test iteration 1122
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:50:31 PDT 2013
+test iteration 1123
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:51:21 PDT 2013
+test iteration 1124
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:52:11 PDT 2013
+test iteration 1125
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:53:01 PDT 2013
+test iteration 1126
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:53:51 PDT 2013
+test iteration 1127
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:54:41 PDT 2013
+test iteration 1128
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:55:31 PDT 2013
+test iteration 1129
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:56:21 PDT 2013
+test iteration 1130
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:57:11 PDT 2013
+test iteration 1131
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:58:01 PDT 2013
+test iteration 1132
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:58:51 PDT 2013
+test iteration 1133
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 12:59:41 PDT 2013
+test iteration 1134
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:00:31 PDT 2013
+test iteration 1135
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:01:21 PDT 2013
+test iteration 1136
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:02:11 PDT 2013
+test iteration 1137
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:03:01 PDT 2013
+test iteration 1138
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:03:51 PDT 2013
+test iteration 1139
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:04:41 PDT 2013
+test iteration 1140
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:05:31 PDT 2013
+test iteration 1141
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:06:21 PDT 2013
+test iteration 1142
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:07:11 PDT 2013
+test iteration 1143
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:08:01 PDT 2013
+test iteration 1144
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:08:51 PDT 2013
+test iteration 1145
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:09:41 PDT 2013
+test iteration 1146
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:10:30 PDT 2013
+test iteration 1147
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:11:20 PDT 2013
+test iteration 1148
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:12:10 PDT 2013
+test iteration 1149
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:13:00 PDT 2013
+test iteration 1150
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:13:50 PDT 2013
+test iteration 1151
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:14:40 PDT 2013
+test iteration 1152
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:15:30 PDT 2013
+test iteration 1153
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:16:20 PDT 2013
+test iteration 1154
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:17:10 PDT 2013
+test iteration 1155
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:18:00 PDT 2013
+test iteration 1156
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:18:50 PDT 2013
+test iteration 1157
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:19:40 PDT 2013
+test iteration 1158
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:20:30 PDT 2013
+test iteration 1159
+compare dump_test.txt against dump_add_list.txt
+============================
+Sun Sep  1 13:21:20 PDT 2013
+test iteration 1160
+compare dump_test.txt against dump_add_list.txt
\ No newline at end of file
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/watchdog.lib	Tue Sep 17 19:42:49 2013 +0000
@@ -0,0 +1,1 @@
+watchdog#f27d373a8e28