Fawwaz Nadzmy
mbed library sources. Supersedes mbed-src.
Fork of
mbed-dev
by 
mbed official
Revision 107:414e9c822e99, committed 2016-04-05
- Comitter:
- mbed_official
- Date:
- Tue Apr 05 18:15:12 2016 +0100
- Parent:
- 106:c405d2eb506d
- Child:
- 108:e46d5651bd87
- Commit message:
- Synchronized with git revision dd3c5f7fa8473776950ec6e15c0e4adedb21cf2f
Full URL: https://github.com/mbedmicro/mbed/commit/dd3c5f7fa8473776950ec6e15c0e4adedb21cf2f/
* * Base Commit for SAMG55J19. No errors and no implementations.
* * Added gpio files.
* * Added pinmap files.
* * Base commit for usticker implementation.
* * Added gcc_arm export functionality
* * added files for usticker.
* added template file for samd55j19
* * GPIO IRQ base commit.
* * updated with changes in gpio irq driver.
* * Reverted back unexpected commit in SAM0 gpio driver.
* * updated gpio_irq driver.
* * correction in gpio and gpio_irq drivers.
* added support for some test for gpio.
* * base commit for peripheralpins for usart.
* update in serial apis.
* * updated serial apis.
* * updated serial apis and test.
* * update serial apis for asynch apis.
* * updated peripheral pins for i2c and spi.
* added test support for serial flow control
* * Base commit for low power ticker implementation.
* * base commit for port apis.
* update in lp ticker apis.
* * Added test support for port.
* * base commit for sleep apis.
* * Base commit for spi.
* * updated with corrections in gpio irq.
* usticker file updated with latest source.
* * updated with corrections for unexpected board reset.
* updated gpio irq apis and added test for the same.
* * updated sleep api for deepsleep.
* * updated serial apis.
* Added uc_ticker and SPI api implementations
* Removed unused SPI pin map
* Updated review feedback
* * implemented lpticker with TC module.
* updated files for KnR Coding Statndard.
* updated serial and usticker apis.
* * Base commit for AnalogueIn apis.
* * RTC apis base commit without implementation.
* * Updated with corrections in lpticker implementations.
* * Added implementation for rtc apis.
* * updated with implementations for pwm.
* changed usticker from TC0 to TC1.
* Added I2C support
* * removed setvector usage from usticker and lpticker implementations
* added tests for SAMG55J19
* * Removed unwanted .o and .d files.
* Updated I2C files for KnR Coding Standards.
* Update for reducing compiler warnings in peripheralpins,c
* Updated with PWM free implementation.
* * Removed unwanted headers file inclusion.
* Compiler warning corrections in serial_api.c
* * Updated ADC with 16 bit mode initialization and code refinements.
* Updated PWM with code refinements.
* Updated I2C review feedback and fixed style
* Updated target name for SAMG55
* * Added Test Support for I2C with AT30TSE75X and Added Support for SAMG55J19 in atmelstudio project exporter
* * Added Test Support for I2C with AT30TSE75X and Added Support for SAMG55J19 in atmelstudio project exporter
* Used NVIC_SetVector for interrupt callback
* Removed Target macro define in test
* Updated test cases to have SAMG55 support
* * Updated with corrections in Serial and SPI asynchronous implementations.
* Updated deepsleep api implementation
* Merged LP_Ticker with latest code from mbed 3.0 repository.
* * updated with corrections in I2C Asynch implementation.
Changed in this revision
--- a/hal/i2c_api.h Mon Apr 04 22:15:11 2016 +0100 +++ b/hal/i2c_api.h Tue Apr 05 18:15:12 2016 +0100 @@ -18,6 +18,7 @@ #include "device.h" #include "buffer.h" +#include "dma_api.h" #if DEVICE_I2C
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55/TARGET_SAMG55J19/TOOLCHAIN_GCC_ARM/samg55j19.ld Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,118 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY {
+ rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000
+ ram (rwx) : ORIGIN = 0x20000000 + 0x108, LENGTH = 0x00028000 - 0x108
+ }
+
+ /* The stack size used by the application. NOTE: you need to adjust according to your application. */
+ STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x3000;
+
+ /* Section Definitions */
+ SECTIONS {
+.text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+.ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+.relocate :
+ AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ .heap (NOLOAD) :
+ {
+ . = ALIGN(4);
+ __end__ = . ;
+ . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55/TARGET_SAMG55J19/TOOLCHAIN_GCC_ARM/startup_samg55.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,257 @@
+/**
+ * \file
+ *
+ * \brief Startup file for SAMG55.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "samg55.h"
+
+#if __FPU_USED /* CMSIS defined value to indicate usage of FPU */
+#include "fpu.h"
+#endif
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAMG55_FLEXCOM7_INSTANCE_
+void FLEXCOM7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAMG55_FLEXCOM7_INSTANCE_*/
+void FLEXCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void FLEXCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PDMIC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void FLEXCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MEM2MEM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void I2SC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void I2SC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PDMIC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void FLEXCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void FLEXCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void FLEXCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void FLEXCOM6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ARM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UHP_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDP_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+ /* Configure Initial Stack Pointer, using linker-generated symbols */
+ .pvStack = (void*) (&_estack),
+
+ .pfnReset_Handler = (void*) Reset_Handler,
+ .pfnNMI_Handler = (void*) NMI_Handler,
+ .pfnHardFault_Handler = (void*) HardFault_Handler,
+ .pfnMemManage_Handler = (void*) MemManage_Handler,
+ .pfnBusFault_Handler = (void*) BusFault_Handler,
+ .pfnUsageFault_Handler = (void*) UsageFault_Handler,
+ .pfnReserved1_Handler = (void*) (0UL), /* Reserved */
+ .pfnReserved2_Handler = (void*) (0UL), /* Reserved */
+ .pfnReserved3_Handler = (void*) (0UL), /* Reserved */
+ .pfnReserved4_Handler = (void*) (0UL), /* Reserved */
+ .pfnSVC_Handler = (void*) SVC_Handler,
+ .pfnDebugMon_Handler = (void*) DebugMon_Handler,
+ .pfnReserved5_Handler = (void*) (0UL), /* Reserved */
+ .pfnPendSV_Handler = (void*) PendSV_Handler,
+ .pfnSysTick_Handler = (void*) SysTick_Handler,
+
+ /* Configurable interrupts */
+ .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */
+ .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */
+ .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real Time Clock */
+ .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real Time Timer */
+ .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */
+ .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */
+ .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Enhanced Flash Controller */
+#ifdef _SAMG55_FLEXCOM7_INSTANCE_
+ .pfnFLEXCOM7_Handler = (void*) FLEXCOM7_Handler, /* 7 FLEXCOM 7 */
+#else
+ .pvReserved7 = (void*) (0UL), /* 7 Reserved */
+#endif /* _SAMG55_FLEXCOM7_INSTANCE_ */
+ .pfnFLEXCOM0_Handler = (void*) FLEXCOM0_Handler, /* 8 FLEXCOM 0 */
+ .pfnFLEXCOM1_Handler = (void*) FLEXCOM1_Handler, /* 9 FLEXCOM 1 */
+ .pvReserved10 = (void*) (0UL), /* 10 Reserved */
+ .pfnPIOA_Handler = (void*) PIOA_Handler, /* 11 Parallel I/O Controller A */
+ .pfnPIOB_Handler = (void*) PIOB_Handler, /* 12 Parallel I/O Controller B */
+ .pfnPDMIC0_Handler = (void*) PDMIC0_Handler, /* 13 PDM 0 */
+ .pfnFLEXCOM2_Handler = (void*) FLEXCOM2_Handler, /* 14 FLEXCOM2 */
+ .pfnMEM2MEM_Handler = (void*) MEM2MEM_Handler, /* 15 MEM2MEM */
+ .pfnI2SC0_Handler = (void*) I2SC0_Handler, /* 16 I2SC0 */
+ .pfnI2SC1_Handler = (void*) I2SC1_Handler, /* 17 I2SC1 */
+ .pfnPDMIC1_Handler = (void*) PDMIC1_Handler, /* 18 PDM 1 */
+ .pfnFLEXCOM3_Handler = (void*) FLEXCOM3_Handler, /* 19 FLEXCOM3 */
+ .pfnFLEXCOM4_Handler = (void*) FLEXCOM4_Handler, /* 20 FLEXCOM4 */
+ .pfnFLEXCOM5_Handler = (void*) FLEXCOM5_Handler, /* 21 FLEXCOM5 */
+ .pfnFLEXCOM6_Handler = (void*) FLEXCOM6_Handler, /* 22 FLEXCOM6 */
+ .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer/Counter 0 */
+ .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer/Counter 1 */
+ .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer/Counter 2 */
+ .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer/Counter 3 */
+ .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer/Counter 4 */
+ .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer/Counter 5 */
+ .pfnADC_Handler = (void*) ADC_Handler, /* 29 Analog To Digital Converter */
+ .pfnARM_Handler = (void*) ARM_Handler, /* 30 FPU */
+ .pvReserved31 = (void*) (0UL), /* 31 Reserved */
+ .pvReserved32 = (void*) (0UL), /* 32 Reserved */
+ .pvReserved33 = (void*) (0UL), /* 33 Reserved */
+ .pvReserved34 = (void*) (0UL), /* 34 Reserved */
+ .pvReserved35 = (void*) (0UL), /* 35 Reserved */
+ .pvReserved36 = (void*) (0UL), /* 36 Reserved */
+ .pvReserved37 = (void*) (0UL), /* 37 Reserved */
+ .pvReserved38 = (void*) (0UL), /* 38 Reserved */
+ .pvReserved39 = (void*) (0UL), /* 39 Reserved */
+ .pvReserved40 = (void*) (0UL), /* 40 Reserved */
+ .pvReserved41 = (void*) (0UL), /* 41 Reserved */
+ .pvReserved42 = (void*) (0UL), /* 42 Reserved */
+ .pvReserved43 = (void*) (0UL), /* 43 Reserved */
+ .pvReserved44 = (void*) (0UL), /* 44 Reserved */
+ .pvReserved45 = (void*) (0UL), /* 45 Reserved */
+ .pvReserved46 = (void*) (0UL), /* 46 Reserved */
+ .pfnUHP_Handler = (void*) UHP_Handler, /* 47 USB OHCI */
+ .pfnUDP_Handler = (void*) UDP_Handler, /* 48 USB Device FS */
+ .pfnCRCCU_Handler = (void*) CRCCU_Handler /* 49 CRCCU */
+};
+
+/* TEMPORARY PATCH FOR SCB */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+ uint32_t *pSrc, *pDest;
+
+ /* Initialize the relocate segment */
+ pSrc = &_etext;
+ pDest = &_srelocate;
+
+ if (pSrc != pDest) {
+ for (; pDest < &_erelocate;) {
+ *pDest++ = *pSrc++;
+ }
+ }
+
+ /* Clear the zero segment */
+ for (pDest = &_szero; pDest < &_ezero;) {
+ *pDest++ = 0;
+ }
+
+ /* Set the vector table base address */
+ pSrc = (uint32_t *) & _sfixed;
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+#if __FPU_USED
+ fpu_enable();
+#endif
+
+ if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+ SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
+ }
+
+ /* Initialize the C library */
+ __libc_init_array();
+
+ /* Branch to main function */
+ main();
+
+ /* Infinite loop */
+ while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+ while (1) {
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55/cmsis.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in samd21j18a specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "samg55.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55/cmsis_nvic.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x00400000)// Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55/cmsis_nvic.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 +50) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_adc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,411 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. */
+/* */
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_ADC_COMPONENT_
+#define _SAMG55_ADC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Analog-to-Digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAMG55_ADC Analog-to-Digital Converter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Adc hardware registers */
+typedef struct {
+ __O uint32_t ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */
+ __IO uint32_t ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */
+ __IO uint32_t ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
+ __I uint32_t Reserved1[1];
+ __O uint32_t ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+ __O uint32_t ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+ __I uint32_t ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */
+ __I uint32_t Reserved2[1];
+ __I uint32_t ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+ __O uint32_t ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+ __O uint32_t ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+ __I uint32_t ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+ __I uint32_t ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
+ __IO uint32_t ADC_LCTMR; /**< \brief (Adc Offset: 0x34) Last Channel Trigger Mode Register */
+ __IO uint32_t ADC_LCCWR; /**< \brief (Adc Offset: 0x38) Last Channel Compare Window Register */
+ __I uint32_t ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
+ __IO uint32_t ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */
+ __IO uint32_t ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */
+ __I uint32_t Reserved3[1];
+ __IO uint32_t ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */
+ __I uint32_t ADC_CDR[8]; /**< \brief (Adc Offset: 0x50) Channel Data Register */
+ __I uint32_t Reserved4[29];
+ __IO uint32_t ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protection Mode Register */
+ __I uint32_t ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protection Status Register */
+ __I uint32_t Reserved5[5];
+ __IO uint32_t ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
+ __IO uint32_t ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */
+ __I uint32_t Reserved6[2];
+ __IO uint32_t ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
+ __IO uint32_t ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
+ __I uint32_t Reserved7[2];
+ __O uint32_t ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */
+ __I uint32_t ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+#define ADC_CR_AUTOCAL (0x1u << 3) /**< \brief (ADC_CR) Automatic Calibration of ADC */
+#define ADC_CR_CMPRST (0x1u << 4) /**< \brief (ADC_CR) Comparison Restart */
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
+#define ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
+#define ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */
+#define ADC_MR_TRGSEL_Pos 1
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
+#define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) ADTRG External trigger */
+#define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIOA0 Output of the Timer Counter Channel 0 */
+#define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIOA1 Output of the Timer Counter Channel 1 */
+#define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIOA2 Output of the Timer Counter Channel 2 */
+#define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) RTCOUT0 */
+#define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) RTTINC */
+#define ADC_MR_TRGSEL_ADC_TRIG6 (0x6u << 1) /**< \brief (ADC_MR) RTTEVENT */
+#define ADC_MR_TRGSEL_ADC_TRIG7 (0x7u << 1) /**< \brief (ADC_MR) - */
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
+#define ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC core and reference voltage circuitry are kept ON between conversions. */
+#define ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The wake-up time can be modified by programming FWUP bit. */
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */
+#define ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) If SLEEP is 1, then both ADC core and reference voltage circuitry are OFF between conversions */
+#define ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) If SLEEP is 1, then Fast Wake-up Sleep mode: The voltage reference is ON between conversions and ADC core is OFF */
+#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */
+#define ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */
+#define ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */
+#define ADC_MR_PRESCAL_Pos 8
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
+#define ADC_MR_STARTUP_Pos 16
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
+#define ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCCLK */
+#define ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCCLK */
+#define ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCCLK */
+#define ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCCLK */
+#define ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCCLK */
+#define ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCCLK */
+#define ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCCLK */
+#define ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCCLK */
+#define ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCCLK */
+#define ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCCLK */
+#define ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCCLK */
+#define ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCCLK */
+#define ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCCLK */
+#define ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCCLK */
+#define ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCCLK */
+#define ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCCLK */
+#define ADC_MR_SETTLING_Pos 20
+#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */
+#define ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCCLK */
+#define ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCCLK */
+#define ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCCLK */
+#define ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCCLK */
+#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */
+#define ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, and OFF0 are used for all channels. */
+#define ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_COR registers. */
+#define ADC_MR_TRACKTIM_Pos 24
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
+#define ADC_MR_TRANSFER_Pos 28
+#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */
+#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */
+#define ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. */
+#define ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 register and can be used to convert the same channel several times. */
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
+#define ADC_SEQR1_USCH1_Pos 0
+#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
+#define ADC_SEQR1_USCH2_Pos 4
+#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
+#define ADC_SEQR1_USCH3_Pos 8
+#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
+#define ADC_SEQR1_USCH4_Pos 12
+#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
+#define ADC_SEQR1_USCH5_Pos 16
+#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
+#define ADC_SEQR1_USCH6_Pos 20
+#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
+#define ADC_SEQR1_USCH7_Pos 24
+#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0xffffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+#define ADC_LCDR_CHNBOSR_Pos 24
+#define ADC_LCDR_CHNBOSR_Msk (0x1fu << ADC_LCDR_CHNBOSR_Pos) /**< \brief (ADC_LCDR) Channel Number in Oversampling Mode */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_LCCHG (0x1u << 19) /**< \brief (ADC_IER) Last Channel Change Interrupt Enable */
+#define ADC_IER_EOCAL (0x1u << 23) /**< \brief (ADC_IER) End of Calibration Sequence */
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
+#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
+#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_LCCHG (0x1u << 19) /**< \brief (ADC_IDR) Last Channel Change Interrupt Disable */
+#define ADC_IDR_EOCAL (0x1u << 23) /**< \brief (ADC_IDR) End of Calibration Sequence */
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
+#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_LCCHG (0x1u << 19) /**< \brief (ADC_IMR) Last Channel Change Interrupt Mask */
+#define ADC_IMR_EOCAL (0x1u << 23) /**< \brief (ADC_IMR) End of Calibration Sequence */
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
+#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 (automatically set / cleared) */
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 (automatically set / cleared) */
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 (automatically set / cleared) */
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 (automatically set / cleared) */
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 (automatically set / cleared) */
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 (automatically set / cleared) */
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 (automatically set / cleared) */
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 (automatically set / cleared) */
+#define ADC_ISR_LCCHG (0x1u << 19) /**< \brief (ADC_ISR) Last Channel Change (cleared on read) */
+#define ADC_ISR_EOCAL (0x1u << 23) /**< \brief (ADC_ISR) End of Calibration Sequence */
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready (automatically set / cleared) */
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error (cleared on read) */
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Event (cleared on read) */
+#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of Receiver Transfer (automatically set / cleared) */
+#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) Reception Buffer Full (automatically set / cleared) */
+/* -------- ADC_LCTMR : (ADC Offset: 0x34) Last Channel Trigger Mode Register -------- */
+#define ADC_LCTMR_DUALTRIG (0x1u << 0) /**< \brief (ADC_LCTMR) Dual Trigger ON */
+#define ADC_LCTMR_CMPMOD_Pos 4
+#define ADC_LCTMR_CMPMOD_Msk (0x3u << ADC_LCTMR_CMPMOD_Pos) /**< \brief (ADC_LCTMR) Last Channel Comparison Mode */
+#define ADC_LCTMR_CMPMOD_LOW (0x0u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is lower than the low threshold of the window. */
+#define ADC_LCTMR_CMPMOD_HIGH (0x1u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is higher than the high threshold of the window. */
+#define ADC_LCTMR_CMPMOD_IN (0x2u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is in the comparison window. */
+#define ADC_LCTMR_CMPMOD_OUT (0x3u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is out of the comparison window. */
+/* -------- ADC_LCCWR : (ADC Offset: 0x38) Last Channel Compare Window Register -------- */
+#define ADC_LCCWR_LOWTHRES_Pos 0
+#define ADC_LCCWR_LOWTHRES_Msk (0xfffu << ADC_LCCWR_LOWTHRES_Pos) /**< \brief (ADC_LCCWR) Low Threshold */
+#define ADC_LCCWR_LOWTHRES(value) ((ADC_LCCWR_LOWTHRES_Msk & ((value) << ADC_LCCWR_LOWTHRES_Pos)))
+#define ADC_LCCWR_HIGHTHRES_Pos 16
+#define ADC_LCCWR_HIGHTHRES_Msk (0xfffu << ADC_LCCWR_HIGHTHRES_Pos) /**< \brief (ADC_LCCWR) High Threshold */
+#define ADC_LCCWR_HIGHTHRES(value) ((ADC_LCCWR_HIGHTHRES_Msk & ((value) << ADC_LCCWR_HIGHTHRES_Pos)))
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
+#define ADC_EMR_CMPMODE_Pos 0
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
+#define ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
+#define ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
+#define ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
+#define ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
+#define ADC_EMR_CMPTYPE (0x1u << 2) /**< \brief (ADC_EMR) Comparison Type */
+#define ADC_EMR_CMPTYPE_FLAG_ONLY (0x0u << 2) /**< \brief (ADC_EMR) Any conversion is performed and comparison function drives the COMPE flag. */
+#define ADC_EMR_CMPTYPE_START_CONDITION (0x1u << 2) /**< \brief (ADC_EMR) Comparison conditions must be met to start the storage of all conversions until the CMPRST bit is set. */
+#define ADC_EMR_CMPSEL_Pos 4
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
+#define ADC_EMR_CMPFILTER_Pos 12
+#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */
+#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos)))
+#define ADC_EMR_OSR_Pos 16
+#define ADC_EMR_OSR_Msk (0x7u << ADC_EMR_OSR_Pos) /**< \brief (ADC_EMR) Over Sampling Rate */
+#define ADC_EMR_OSR_NO_AVERAGE (0x0u << 16) /**< \brief (ADC_EMR) No averaging. ADC sample rate is maximum. */
+#define ADC_EMR_OSR_OSR4 (0x1u << 16) /**< \brief (ADC_EMR) 1-bit enhanced resolution by averaging. ADC sample rate divided by 4. */
+#define ADC_EMR_OSR_OSR16 (0x2u << 16) /**< \brief (ADC_EMR) 2-bit enhanced resolution by averaging. ADC sample rate divided by 16. */
+#define ADC_EMR_OSR_OSR64 (0x3u << 16) /**< \brief (ADC_EMR) 3-bit enhanced resolution by averaging. ADC sample rate divided by 64. */
+#define ADC_EMR_OSR_OSR256 (0x4u << 16) /**< \brief (ADC_EMR) 4-bit enhanced resolution by averaging. ADC sample rate divided by 256. */
+#define ADC_EMR_ASTE (0x1u << 20) /**< \brief (ADC_EMR) Averaging on Single Trigger Event */
+#define ADC_EMR_ASTE_MULTI_TRIG_AVERAGE (0x0u << 20) /**< \brief (ADC_EMR) The average requests several trigger events. */
+#define ADC_EMR_ASTE_SINGLE_TRIG_AVERAGE (0x1u << 20) /**< \brief (ADC_EMR) The average requests only one trigger event. */
+#define ADC_EMR_SRCCLK (0x1u << 21) /**< \brief (ADC_EMR) External Clock Selection */
+#define ADC_EMR_SRCCLK_PERIPH_CLK (0x0u << 21) /**< \brief (ADC_EMR) The peripheral clock is the source for the ADC prescaler. */
+#define ADC_EMR_SRCCLK_PMC_PCK (0x1u << 21) /**< \brief (ADC_EMR) PMC PCKx is the source clock for the ADC prescaler, thus the ADC clock can be independent of the core/peripheral clock. */
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) Tag of the ADC_LCDR */
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
+#define ADC_CWR_LOWTHRES_Pos 0
+#define ADC_CWR_LOWTHRES_Msk (0xffffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
+#define ADC_CWR_HIGHTHRES_Pos 16
+#define ADC_CWR_HIGHTHRES_Msk (0xffffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
+/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */
+#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for Channel 0 */
+#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for Channel 1 */
+#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for Channel 2 */
+#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for Channel 3 */
+#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for Channel 4 */
+#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for Channel 5 */
+#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for Channel 6 */
+#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for Channel 7 */
+#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential Inputs for Channel 0 */
+#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential Inputs for Channel 1 */
+#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential Inputs for Channel 2 */
+#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential Inputs for Channel 3 */
+#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential Inputs for Channel 4 */
+#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential Inputs for Channel 5 */
+#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential Inputs for Channel 6 */
+#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential Inputs for Channel 7 */
+/* -------- ADC_CDR[8] : (ADC Offset: 0x50) Channel Data Register -------- */
+#define ADC_CDR_DATA_Pos 0
+#define ADC_CDR_DATA_Msk (0xffffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[8]) Converted Data */
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protection Mode Register -------- */
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protection Enable */
+#define ADC_WPMR_WPKEY_Pos 8
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protection Key */
+#define ADC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (ADC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protection Status Register -------- */
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protection Violation Status */
+#define ADC_WPSR_WPVSRC_Pos 8
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protection Violation Source */
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
+#define ADC_RPR_RXPTR_Pos 0
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
+#define ADC_RCR_RXCTR_Pos 0
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC_RNPR_RXNPTR_Pos 0
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC_RNCR_RXNCTR_Pos 0
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
+#define ADC_PTCR_RXCBEN (0x1u << 16) /**< \brief (ADC_PTCR) Receiver Circular Buffer Enable */
+#define ADC_PTCR_RXCBDIS (0x1u << 17) /**< \brief (ADC_PTCR) Receiver Circular Buffer Disable */
+#define ADC_PTCR_TXCBEN (0x1u << 18) /**< \brief (ADC_PTCR) Transmitter Circular Buffer Enable */
+#define ADC_PTCR_TXCBDIS (0x1u << 19) /**< \brief (ADC_PTCR) Transmitter Circular Buffer Disable */
+#define ADC_PTCR_ERRCLR (0x1u << 24) /**< \brief (ADC_PTCR) Transfer Bus Error Clear */
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+#define ADC_PTSR_RXCBEN (0x1u << 16) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXCBEN (0x1u << 18) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+#define ADC_PTSR_ERR (0x1u << 24) /**< \brief (ADC_PTSR) Transfer Bus Error (clear on read) */
+
+/*@}*/
+
+
+
+#endif /* _SAMG55_ADC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_chipid.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,134 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_CHIPID_COMPONENT_
+#define _SAMG55_CHIPID_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAMG55_CHIPID Chip Identifier */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Chipid hardware registers */
+typedef struct {
+ __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+ __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */
+#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */
+#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */
+#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */
+#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */
+#define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */
+#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */
+#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */
+#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */
+#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
+#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */
+#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */
+#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */
+#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */
+#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */
+#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */
+#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */
+#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */
+#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define CHIPID_CIDR_ARCH_SAMG55 (0x44u << 20) /**< \brief (CHIPID_CIDR) SAM G55 (49-lead version) */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */
+#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+
+#endif /* _SAMG55_CHIPID_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_cmcc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,134 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_CMCC_COMPONENT_
+#define _SAMG55_CMCC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Cortex-M Cache Controller */
+/* ============================================================================= */
+/** \addtogroup SAMG55_CMCC Cortex-M Cache Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Cmcc hardware registers */
+typedef struct {
+ __I uint32_t CMCC_TYPE; /**< \brief (Cmcc Offset: 0x00) Cache Controller Type Register */
+ __IO uint32_t CMCC_CFG; /**< \brief (Cmcc Offset: 0x04) Cache Controller Configuration Register */
+ __O uint32_t CMCC_CTRL; /**< \brief (Cmcc Offset: 0x08) Cache Controller Control Register */
+ __I uint32_t CMCC_SR; /**< \brief (Cmcc Offset: 0x0C) Cache Controller Status Register */
+ __I uint32_t Reserved1[4];
+ __O uint32_t CMCC_MAINT0; /**< \brief (Cmcc Offset: 0x20) Cache Controller Maintenance Register 0 */
+ __O uint32_t CMCC_MAINT1; /**< \brief (Cmcc Offset: 0x24) Cache Controller Maintenance Register 1 */
+ __IO uint32_t CMCC_MCFG; /**< \brief (Cmcc Offset: 0x28) Cache Controller Monitor Configuration Register */
+ __IO uint32_t CMCC_MEN; /**< \brief (Cmcc Offset: 0x2C) Cache Controller Monitor Enable Register */
+ __O uint32_t CMCC_MCTRL; /**< \brief (Cmcc Offset: 0x30) Cache Controller Monitor Control Register */
+ __I uint32_t CMCC_MSR; /**< \brief (Cmcc Offset: 0x34) Cache Controller Monitor Status Register */
+} Cmcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CMCC_TYPE : (CMCC Offset: 0x00) Cache Controller Type Register -------- */
+#define CMCC_TYPE_AP (0x1u << 0) /**< \brief (CMCC_TYPE) Access Port Access Allowed */
+#define CMCC_TYPE_GCLK (0x1u << 1) /**< \brief (CMCC_TYPE) Dynamic Clock Gating Supported */
+#define CMCC_TYPE_RANDP (0x1u << 2) /**< \brief (CMCC_TYPE) Random Selection Policy Supported */
+#define CMCC_TYPE_LRUP (0x1u << 3) /**< \brief (CMCC_TYPE) Least Recently Used Policy Supported */
+#define CMCC_TYPE_RRP (0x1u << 4) /**< \brief (CMCC_TYPE) Random Selection Policy Supported */
+#define CMCC_TYPE_WAYNUM_Pos 5
+#define CMCC_TYPE_WAYNUM_Msk (0x3u << CMCC_TYPE_WAYNUM_Pos) /**< \brief (CMCC_TYPE) Number of Ways */
+#define CMCC_TYPE_WAYNUM_DMAPPED (0x0u << 5) /**< \brief (CMCC_TYPE) Direct Mapped Cache */
+#define CMCC_TYPE_WAYNUM_ARCH2WAY (0x1u << 5) /**< \brief (CMCC_TYPE) 2-way set associative */
+#define CMCC_TYPE_WAYNUM_ARCH4WAY (0x2u << 5) /**< \brief (CMCC_TYPE) 4-way set associative */
+#define CMCC_TYPE_WAYNUM_ARCH8WAY (0x3u << 5) /**< \brief (CMCC_TYPE) 8-way set associative */
+#define CMCC_TYPE_LCKDOWN (0x1u << 7) /**< \brief (CMCC_TYPE) Lockdown Supported */
+#define CMCC_TYPE_CSIZE_Pos 8
+#define CMCC_TYPE_CSIZE_Msk (0x7u << CMCC_TYPE_CSIZE_Pos) /**< \brief (CMCC_TYPE) Data Cache Size */
+#define CMCC_TYPE_CSIZE_CSIZE_1KB (0x0u << 8) /**< \brief (CMCC_TYPE) Data cache size is 1 Kbyte */
+#define CMCC_TYPE_CSIZE_CSIZE_2KB (0x1u << 8) /**< \brief (CMCC_TYPE) Data cache size is 2 Kbytes */
+#define CMCC_TYPE_CSIZE_CSIZE_4KB (0x2u << 8) /**< \brief (CMCC_TYPE) Data cache size is 4 Kbytes */
+#define CMCC_TYPE_CSIZE_CSIZE_8KB (0x3u << 8) /**< \brief (CMCC_TYPE) Data cache size is 8 Kbytes */
+#define CMCC_TYPE_CLSIZE_Pos 11
+#define CMCC_TYPE_CLSIZE_Msk (0x7u << CMCC_TYPE_CLSIZE_Pos) /**< \brief (CMCC_TYPE) Cache LIne Size */
+#define CMCC_TYPE_CLSIZE_CLSIZE_1KB (0x0u << 11) /**< \brief (CMCC_TYPE) Cache line size is 4 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_2KB (0x1u << 11) /**< \brief (CMCC_TYPE) Cache line size is 8 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_4KB (0x2u << 11) /**< \brief (CMCC_TYPE) Cache line size is 16 bytes */
+#define CMCC_TYPE_CLSIZE_CLSIZE_8KB (0x3u << 11) /**< \brief (CMCC_TYPE) Cache line size is 32 bytes */
+/* -------- CMCC_CFG : (CMCC Offset: 0x04) Cache Controller Configuration Register -------- */
+#define CMCC_CFG_GCLKDIS (0x1u << 0) /**< \brief (CMCC_CFG) Disable Clock Gating */
+#define CMCC_CFG_ICDIS (0x1u << 1) /**< \brief (CMCC_CFG) */
+#define CMCC_CFG_DCDIS (0x1u << 2) /**< \brief (CMCC_CFG) */
+#define CMCC_CFG_PRGCSIZE_Pos 4
+#define CMCC_CFG_PRGCSIZE_Msk (0x7u << CMCC_CFG_PRGCSIZE_Pos) /**< \brief (CMCC_CFG) */
+#define CMCC_CFG_PRGCSIZE(value) ((CMCC_CFG_PRGCSIZE_Msk & ((value) << CMCC_CFG_PRGCSIZE_Pos)))
+/* -------- CMCC_CTRL : (CMCC Offset: 0x08) Cache Controller Control Register -------- */
+#define CMCC_CTRL_CEN (0x1u << 0) /**< \brief (CMCC_CTRL) Cache Controller Enable */
+/* -------- CMCC_SR : (CMCC Offset: 0x0C) Cache Controller Status Register -------- */
+#define CMCC_SR_CSTS (0x1u << 0) /**< \brief (CMCC_SR) Cache Controller Status */
+/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) Cache Controller Maintenance Register 0 -------- */
+#define CMCC_MAINT0_INVALL (0x1u << 0) /**< \brief (CMCC_MAINT0) Cache Controller Invalidate All */
+/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) Cache Controller Maintenance Register 1 -------- */
+#define CMCC_MAINT1_INDEX_Pos 4
+#define CMCC_MAINT1_INDEX_Msk (0x1fu << CMCC_MAINT1_INDEX_Pos) /**< \brief (CMCC_MAINT1) Invalidate Index */
+#define CMCC_MAINT1_INDEX(value) ((CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)))
+#define CMCC_MAINT1_WAY_Pos 30
+#define CMCC_MAINT1_WAY_Msk (0x3u << CMCC_MAINT1_WAY_Pos) /**< \brief (CMCC_MAINT1) Invalidate Way */
+#define CMCC_MAINT1_WAY_WAY0 (0x0u << 30) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */
+#define CMCC_MAINT1_WAY_WAY1 (0x1u << 30) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */
+#define CMCC_MAINT1_WAY_WAY2 (0x2u << 30) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */
+#define CMCC_MAINT1_WAY_WAY3 (0x3u << 30) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */
+/* -------- CMCC_MCFG : (CMCC Offset: 0x28) Cache Controller Monitor Configuration Register -------- */
+#define CMCC_MCFG_MODE_Pos 0
+#define CMCC_MCFG_MODE_Msk (0x3u << CMCC_MCFG_MODE_Pos) /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */
+#define CMCC_MCFG_MODE_CYCLE_COUNT (0x0u << 0) /**< \brief (CMCC_MCFG) Cycle counter */
+#define CMCC_MCFG_MODE_IHIT_COUNT (0x1u << 0) /**< \brief (CMCC_MCFG) Instruction hit counter */
+#define CMCC_MCFG_MODE_DHIT_COUNT (0x2u << 0) /**< \brief (CMCC_MCFG) Data hit counter */
+/* -------- CMCC_MEN : (CMCC Offset: 0x2C) Cache Controller Monitor Enable Register -------- */
+#define CMCC_MEN_MENABLE (0x1u << 0) /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */
+/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) Cache Controller Monitor Control Register -------- */
+#define CMCC_MCTRL_SWRST (0x1u << 0) /**< \brief (CMCC_MCTRL) Monitor */
+/* -------- CMCC_MSR : (CMCC Offset: 0x34) Cache Controller Monitor Status Register -------- */
+#define CMCC_MSR_EVENT_CNT_Pos 0
+#define CMCC_MSR_EVENT_CNT_Msk (0xffffffffu << CMCC_MSR_EVENT_CNT_Pos) /**< \brief (CMCC_MSR) Monitor Event Counter */
+
+/*@}*/
+
+#endif /* _SAMG55_CMCC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_crccu.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,125 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_CRCCU_COMPONENT_
+#define _SAMG55_CRCCU_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */
+/* ============================================================================= */
+/** \addtogroup SAMG55_CRCCU Cyclic Redundancy Check Calculation Unit */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Crccu hardware registers */
+typedef struct {
+ __IO uint32_t CRCCU_DSCR; /**< \brief (Crccu Offset: 0x000) CRCCU Descriptor Base Register */
+ __I uint32_t Reserved1[1];
+ __O uint32_t CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x008) CRCCU DMA Enable Register */
+ __O uint32_t CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x00C) CRCCU DMA Disable Register */
+ __I uint32_t CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x010) CRCCU DMA Status Register */
+ __O uint32_t CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x014) CRCCU DMA Interrupt Enable Register */
+ __O uint32_t CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x018) CRCCU DMA Interrupt Disable Register */
+ __I uint32_t CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x001C) CRCCU DMA Interrupt Mask Register */
+ __I uint32_t CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x020) CRCCU DMA Interrupt Status Register */
+ __I uint32_t Reserved2[4];
+ __O uint32_t CRCCU_CR; /**< \brief (Crccu Offset: 0x034) CRCCU Control Register */
+ __IO uint32_t CRCCU_MR; /**< \brief (Crccu Offset: 0x038) CRCCU Mode Register */
+ __I uint32_t CRCCU_SR; /**< \brief (Crccu Offset: 0x03C) CRCCU Status Register */
+ __O uint32_t CRCCU_IER; /**< \brief (Crccu Offset: 0x040) CRCCU Interrupt Enable Register */
+ __O uint32_t CRCCU_IDR; /**< \brief (Crccu Offset: 0x044) CRCCU Interrupt Disable Register */
+ __I uint32_t CRCCU_IMR; /**< \brief (Crccu Offset: 0x048) CRCCU Interrupt Mask Register */
+ __I uint32_t CRCCU_ISR; /**< \brief (Crccu Offset: 0x004C) CRCCU Interrupt Status Register */
+} Crccu;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CRCCU_DSCR : (CRCCU Offset: 0x000) CRCCU Descriptor Base Register -------- */
+#define CRCCU_DSCR_DSCR_Pos 9
+#define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */
+#define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos)))
+/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x008) CRCCU DMA Enable Register -------- */
+#define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable */
+/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x00C) CRCCU DMA Disable Register -------- */
+#define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable */
+/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x010) CRCCU DMA Status Register -------- */
+#define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status */
+/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x014) CRCCU DMA Interrupt Enable Register -------- */
+#define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable */
+/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x018) CRCCU DMA Interrupt Disable Register -------- */
+#define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable */
+/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x001C) CRCCU DMA Interrupt Mask Register -------- */
+#define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask */
+/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x020) CRCCU DMA Interrupt Status Register -------- */
+#define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status */
+/* -------- CRCCU_CR : (CRCCU Offset: 0x034) CRCCU Control Register -------- */
+#define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */
+/* -------- CRCCU_MR : (CRCCU Offset: 0x038) CRCCU Mode Register -------- */
+#define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */
+#define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */
+#define CRCCU_MR_PTYPE_Pos 2
+#define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */
+#define CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */
+#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */
+#define CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */
+#define CRCCU_MR_DIVIDER_Pos 4
+#define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */
+#define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos)))
+#define CRCCU_MR_BITORDER (0x1u << 17) /**< \brief (CRCCU_MR) Precomputation Bit Swap Operation of the CRC */
+#define CRCCU_MR_BITORDER_MSBFIRST (0x0u << 17) /**< \brief (CRCCU_MR) CRC computation is performed from the most significant bit to the least significant bit */
+#define CRCCU_MR_BITORDER_LSBFIRST (0x1u << 17) /**< \brief (CRCCU_MR) CRC computation is performed from the least significant bit to the most significant bit */
+/* -------- CRCCU_SR : (CRCCU Offset: 0x03C) CRCCU Status Register -------- */
+#define CRCCU_SR_CRC_Pos 0
+#define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */
+/* -------- CRCCU_IER : (CRCCU Offset: 0x040) CRCCU Interrupt Enable Register -------- */
+#define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */
+/* -------- CRCCU_IDR : (CRCCU Offset: 0x044) CRCCU Interrupt Disable Register -------- */
+#define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */
+/* -------- CRCCU_IMR : (CRCCU Offset: 0x048) CRCCU Interrupt Mask Register -------- */
+#define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */
+/* -------- CRCCU_ISR : (CRCCU Offset: 0x004C) CRCCU Interrupt Status Register -------- */
+#define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */
+
+/*@}*/
+
+
+#endif /* _SAMG55_CRCCU_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_efc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,119 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_EFC_COMPONENT_
+#define _SAMG55_EFC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */
+/* ============================================================================= */
+/** \addtogroup SAMG55_EFC Embedded Flash Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Efc hardware registers */
+typedef struct {
+ __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
+ __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
+ __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
+ __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
+ __I uint32_t Reserved1[53];
+ __IO uint32_t EEFC_WPMR; /**< \brief (Efc Offset: 0xE4) Write Protection Mode Register */
+} Efc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Flash Ready Interrupt Enable */
+#define EEFC_FMR_FWS_Pos 8
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
+#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loop Optimization Enable */
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
+#define EEFC_FCR_FCMD_Pos 0
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
+#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash descriptor */
+#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */
+#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */
+#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */
+#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */
+#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */
+#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase pages */
+#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set lock bit */
+#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear lock bit */
+#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get lock bit */
+#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM bit */
+#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM bit */
+#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM bit */
+#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start read unique identifier */
+#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop read unique identifier */
+#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB bit */
+#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase sector */
+#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write user signature */
+#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase user signature */
+#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start read user signature */
+#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop read user signature */
+#define EEFC_FCR_FARG_Pos 8
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
+#define EEFC_FCR_FKEY_Pos 24
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
+#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
+#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status */
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
+#define EEFC_FRR_FVALUE_Pos 0
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
+/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */
+#define EEFC_WPMR_WPEN (0x1u << 0) /**< \brief (EEFC_WPMR) Write Protection Enable */
+#define EEFC_WPMR_WPKEY_Pos 8
+#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos) /**< \brief (EEFC_WPMR) Write Protection Key */
+#define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8) /**< \brief (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */
+
+/*@}*/
+
+#endif /* _SAMG55_EFC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_flexcom.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,82 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_FLEXCOM_COMPONENT_
+#define _SAMG55_FLEXCOM_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Flexible Serial Communication */
+/* ============================================================================= */
+/** \addtogroup SAMG55_FLEXCOM Flexible Serial Communication */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Flexcom hardware registers */
+typedef struct {
+ __IO uint32_t FLEXCOM_MR; /**< \brief (Flexcom Offset: 0x0000) FLEXCOM Mode register */
+ __I uint32_t Reserved1[3];
+ __I uint32_t FLEXCOM_RHR; /**< \brief (Flexcom Offset: 0x0010) FLEXCOM Receive Holding Register */
+ __I uint32_t Reserved2[3];
+ __IO uint32_t FLEXCOM_THR; /**< \brief (Flexcom Offset: 0x0020) FLEXCOM Transmit Holding Register */
+} Flexcom;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- FLEXCOM_MR : (FLEXCOM Offset: 0x0000) FLEXCOM Mode register -------- */
+#define FLEXCOM_MR_OPMODE_Pos 0
+#define FLEXCOM_MR_OPMODE_Msk (0x3u << FLEXCOM_MR_OPMODE_Pos) /**< \brief (FLEXCOM_MR) FLEXCOM Operating Mode */
+#define FLEXCOM_MR_OPMODE_NO_COM (0x0u << 0) /**< \brief (FLEXCOM_MR) No communication */
+#define FLEXCOM_MR_OPMODE_USART (0x1u << 0) /**< \brief (FLEXCOM_MR) All related USART related protocols are selected (RS232, RS485, ISO7816, LIN,)All SPI/TWI related registers are not accessible and have no impact on IOs. */
+#define FLEXCOM_MR_OPMODE_SPI (0x2u << 0) /**< \brief (FLEXCOM_MR) SPI operating mode is selected.All USART/TWI related registers are not accessible and have no impact on IOs. */
+#define FLEXCOM_MR_OPMODE_TWI (0x3u << 0) /**< \brief (FLEXCOM_MR) All related TWI protocols are selected (TWI, SMBUS). All USART/SPI related registers are not accessible and have no impact on IOs. */
+/* -------- FLEXCOM_RHR : (FLEXCOM Offset: 0x0010) FLEXCOM Receive Holding Register -------- */
+#define FLEXCOM_RHR_RXDATA_Pos 0
+#define FLEXCOM_RHR_RXDATA_Msk (0xffffu << FLEXCOM_RHR_RXDATA_Pos) /**< \brief (FLEXCOM_RHR) Receive Data */
+/* -------- FLEXCOM_THR : (FLEXCOM Offset: 0x0020) FLEXCOM Transmit Holding Register -------- */
+#define FLEXCOM_THR_TXDATA_Pos 0
+#define FLEXCOM_THR_TXDATA_Msk (0xffffu << FLEXCOM_THR_TXDATA_Pos) /**< \brief (FLEXCOM_THR) Transmit Data */
+#define FLEXCOM_THR_TXDATA(value) ((FLEXCOM_THR_TXDATA_Msk & ((value) << FLEXCOM_THR_TXDATA_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAMG55_FLEXCOM_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_gpbr.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,68 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_GPBR_COMPONENT_
+#define _SAMG55_GPBR_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */
+/* ============================================================================= */
+/** \addtogroup SAMG55_GPBR General Purpose Backup Registers */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Gpbr hardware registers */
+typedef struct {
+ __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
+} Gpbr;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
+#define SYS_GPBR_GPBR_VALUE_Pos 0
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAMG55_GPBR_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_i2sc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,246 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_I2SC_COMPONENT_
+#define _SAMG55_I2SC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Inter-IC Sound Controller */
+/* ============================================================================= */
+/** \addtogroup SAMG55_I2SC Inter-IC Sound Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief I2sc hardware registers */
+typedef struct {
+ __O uint32_t I2SC_CR; /**< \brief (I2sc Offset: 0x00) Control Register */
+ __IO uint32_t I2SC_MR; /**< \brief (I2sc Offset: 0x04) Mode Register */
+ __I uint32_t I2SC_SR; /**< \brief (I2sc Offset: 0x08) Status Register */
+ __O uint32_t I2SC_SCR; /**< \brief (I2sc Offset: 0x0C) Status Clear Register */
+ __O uint32_t I2SC_SSR; /**< \brief (I2sc Offset: 0x10) Status Set Register */
+ __O uint32_t I2SC_IER; /**< \brief (I2sc Offset: 0x14) Interrupt Enable Register */
+ __O uint32_t I2SC_IDR; /**< \brief (I2sc Offset: 0x18) Interrupt Disable Register */
+ __I uint32_t I2SC_IMR; /**< \brief (I2sc Offset: 0x1C) Interrupt Mask Register */
+ __I uint32_t I2SC_RHR; /**< \brief (I2sc Offset: 0x20) Receiver Holding Register */
+ __O uint32_t I2SC_THR; /**< \brief (I2sc Offset: 0x24) Transmitter Holding Register */
+ __I uint32_t Reserved1[54];
+ __IO uint32_t I2SC_RPR; /**< \brief (I2sc Offset: 0x100) Receive Pointer Register */
+ __IO uint32_t I2SC_RCR; /**< \brief (I2sc Offset: 0x104) Receive Counter Register */
+ __IO uint32_t I2SC_TPR; /**< \brief (I2sc Offset: 0x108) Transmit Pointer Register */
+ __IO uint32_t I2SC_TCR; /**< \brief (I2sc Offset: 0x10C) Transmit Counter Register */
+ __IO uint32_t I2SC_RNPR; /**< \brief (I2sc Offset: 0x110) Receive Next Pointer Register */
+ __IO uint32_t I2SC_RNCR; /**< \brief (I2sc Offset: 0x114) Receive Next Counter Register */
+ __IO uint32_t I2SC_TNPR; /**< \brief (I2sc Offset: 0x118) Transmit Next Pointer Register */
+ __IO uint32_t I2SC_TNCR; /**< \brief (I2sc Offset: 0x11C) Transmit Next Counter Register */
+ __O uint32_t I2SC_PTCR; /**< \brief (I2sc Offset: 0x120) Transfer Control Register */
+ __I uint32_t I2SC_PTSR; /**< \brief (I2sc Offset: 0x124) Transfer Status Register */
+} I2sc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- I2SC_CR : (I2SC Offset: 0x00) Control Register -------- */
+#define I2SC_CR_RXEN (0x1u << 0) /**< \brief (I2SC_CR) Receiver Enable */
+#define I2SC_CR_RXDIS (0x1u << 1) /**< \brief (I2SC_CR) Receiver Disable */
+#define I2SC_CR_CKEN (0x1u << 2) /**< \brief (I2SC_CR) Clocks Enable */
+#define I2SC_CR_CKDIS (0x1u << 3) /**< \brief (I2SC_CR) Clocks Disable */
+#define I2SC_CR_TXEN (0x1u << 4) /**< \brief (I2SC_CR) Transmitter Enable */
+#define I2SC_CR_TXDIS (0x1u << 5) /**< \brief (I2SC_CR) Transmitter Disable */
+#define I2SC_CR_SWRST (0x1u << 7) /**< \brief (I2SC_CR) Software Reset */
+/* -------- I2SC_MR : (I2SC Offset: 0x04) Mode Register -------- */
+#define I2SC_MR_MODE (0x1u << 0) /**< \brief (I2SC_MR) Inter-IC Sound Controller Mode */
+#define I2SC_MR_MODE_SLAVE (0x0u << 0) /**< \brief (I2SC_MR) I2SCK and i2SWS pin inputs used as bit clock and word select/frame synchronization. */
+#define I2SC_MR_MODE_MASTER (0x1u << 0) /**< \brief (I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SCK and I2SWS pins. MCK is output as master clock on I2SMCK if IMCKMODE bit of I2SC_MR is set. */
+#define I2SC_MR_DATALENGTH_Pos 2
+#define I2SC_MR_DATALENGTH_Msk (0x7u << I2SC_MR_DATALENGTH_Pos) /**< \brief (I2SC_MR) Data Word Length */
+#define I2SC_MR_DATALENGTH_32_BITS (0x0u << 2) /**< \brief (I2SC_MR) Data length is set to 32 bits */
+#define I2SC_MR_DATALENGTH_24_BITS (0x1u << 2) /**< \brief (I2SC_MR) Data length is set to 24 bits */
+#define I2SC_MR_DATALENGTH_20_BITS (0x2u << 2) /**< \brief (I2SC_MR) Data length is set to 20 bits */
+#define I2SC_MR_DATALENGTH_18_BITS (0x3u << 2) /**< \brief (I2SC_MR) Data length is set to 18 bits */
+#define I2SC_MR_DATALENGTH_16_BITS (0x4u << 2) /**< \brief (I2SC_MR) Data length is set to 16 bits */
+#define I2SC_MR_DATALENGTH_16_BITS_COMPACT (0x5u << 2) /**< \brief (I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. */
+#define I2SC_MR_DATALENGTH_8_BITS (0x6u << 2) /**< \brief (I2SC_MR) Data length is set to 8 bits */
+#define I2SC_MR_DATALENGTH_8_BITS_COMPACT (0x7u << 2) /**< \brief (I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. */
+#define I2SC_MR_RXMONO (0x1u << 8) /**< \brief (I2SC_MR) Receive Mono */
+#define I2SC_MR_RXDMA (0x1u << 9) /**< \brief (I2SC_MR) Single or Multiple PDC Channels for Receiver */
+#define I2SC_MR_RXLOOP (0x1u << 10) /**< \brief (I2SC_MR) Loop-back Test Mode */
+#define I2SC_MR_TXMONO (0x1u << 12) /**< \brief (I2SC_MR) Transmit Mono */
+#define I2SC_MR_TXDMA (0x1u << 13) /**< \brief (I2SC_MR) Single or Multiple PDC Channels for Transmitter */
+#define I2SC_MR_TXSAME (0x1u << 14) /**< \brief (I2SC_MR) Transmit Data when Underrun */
+#define I2SC_MR_IMCKDIV_Pos 16
+#define I2SC_MR_IMCKDIV_Msk (0x3fu << I2SC_MR_IMCKDIV_Pos) /**< \brief (I2SC_MR) Peripheral Clock to I2SC Master Clock Ratio */
+#define I2SC_MR_IMCKDIV(value) ((I2SC_MR_IMCKDIV_Msk & ((value) << I2SC_MR_IMCKDIV_Pos)))
+#define I2SC_MR_IMCKFS_Pos 24
+#define I2SC_MR_IMCKFS_Msk (0x3fu << I2SC_MR_IMCKFS_Pos) /**< \brief (I2SC_MR) Master Clock to fs Ratio */
+#define I2SC_MR_IMCKFS_M2SF16 (0x0u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 16 */
+#define I2SC_MR_IMCKFS_M2SF32 (0x1u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 32 */
+#define I2SC_MR_IMCKFS_M2SF48 (0x2u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 48 */
+#define I2SC_MR_IMCKFS_M2SF64 (0x3u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 64 */
+#define I2SC_MR_IMCKFS_M2SF96 (0x5u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 96 */
+#define I2SC_MR_IMCKFS_M2SF128 (0x7u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 128 */
+#define I2SC_MR_IMCKFS_M2SF192 (0xBu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 192 */
+#define I2SC_MR_IMCKFS_M2SF256 (0xFu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 256 */
+#define I2SC_MR_IMCKFS_M2SF384 (0x17u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 384 */
+#define I2SC_MR_IMCKFS_M2SF512 (0x1Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 512 */
+#define I2SC_MR_IMCKFS_M2SF768 (0x2Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 768 */
+#define I2SC_MR_IMCKFS_M2SF1024 (0x3Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 1024 */
+#define I2SC_MR_IMCKMODE (0x1u << 30) /**< \brief (I2SC_MR) Master Clock Mode */
+#define I2SC_MR_IWS (0x1u << 31) /**< \brief (I2SC_MR) I2SWS TDM Slot Width */
+/* -------- I2SC_SR : (I2SC Offset: 0x08) Status Register -------- */
+#define I2SC_SR_RXEN (0x1u << 0) /**< \brief (I2SC_SR) Receiver Enabled */
+#define I2SC_SR_RXRDY (0x1u << 1) /**< \brief (I2SC_SR) Receive Ready */
+#define I2SC_SR_RXOR (0x1u << 2) /**< \brief (I2SC_SR) Receive Overrun */
+#define I2SC_SR_ENDRX (0x1u << 3) /**< \brief (I2SC_SR) End of Receiver Transfer */
+#define I2SC_SR_TXEN (0x1u << 4) /**< \brief (I2SC_SR) Transmitter Enabled */
+#define I2SC_SR_TXRDY (0x1u << 5) /**< \brief (I2SC_SR) Transmit Ready */
+#define I2SC_SR_TXUR (0x1u << 6) /**< \brief (I2SC_SR) Transmit Underrun */
+#define I2SC_SR_ENDTX (0x1u << 7) /**< \brief (I2SC_SR) End of Transmitter Transfer */
+#define I2SC_SR_RXORCH_Pos 8
+#define I2SC_SR_RXORCH_Msk (0x3u << I2SC_SR_RXORCH_Pos) /**< \brief (I2SC_SR) Receive Overrun Channel */
+#define I2SC_SR_RXBUFF (0x1u << 19) /**< \brief (I2SC_SR) Receive Buffer Full */
+#define I2SC_SR_TXURCH_Pos 20
+#define I2SC_SR_TXURCH_Msk (0x3u << I2SC_SR_TXURCH_Pos) /**< \brief (I2SC_SR) Transmit Underrun Channel */
+#define I2SC_SR_TXBUFE (0x1u << 31) /**< \brief (I2SC_SR) Transmit Buffer Empty */
+/* -------- I2SC_SCR : (I2SC Offset: 0x0C) Status Clear Register -------- */
+#define I2SC_SCR_RXOR (0x1u << 2) /**< \brief (I2SC_SCR) Receive Overrun Status Clear */
+#define I2SC_SCR_TXUR (0x1u << 6) /**< \brief (I2SC_SCR) Transmit Underrun Status Clear */
+#define I2SC_SCR_RXORCH_Pos 8
+#define I2SC_SCR_RXORCH_Msk (0x3u << I2SC_SCR_RXORCH_Pos) /**< \brief (I2SC_SCR) Receive Overrun Per Channel Status Clear */
+#define I2SC_SCR_RXORCH(value) ((I2SC_SCR_RXORCH_Msk & ((value) << I2SC_SCR_RXORCH_Pos)))
+#define I2SC_SCR_TXURCH_Pos 20
+#define I2SC_SCR_TXURCH_Msk (0x3u << I2SC_SCR_TXURCH_Pos) /**< \brief (I2SC_SCR) Transmit Underrun Per Channel Status Clear */
+#define I2SC_SCR_TXURCH(value) ((I2SC_SCR_TXURCH_Msk & ((value) << I2SC_SCR_TXURCH_Pos)))
+/* -------- I2SC_SSR : (I2SC Offset: 0x10) Status Set Register -------- */
+#define I2SC_SSR_RXOR (0x1u << 2) /**< \brief (I2SC_SSR) Receive Overrun Status Set */
+#define I2SC_SSR_TXUR (0x1u << 6) /**< \brief (I2SC_SSR) Transmit Underrun Status Set */
+#define I2SC_SSR_RXORCH_Pos 8
+#define I2SC_SSR_RXORCH_Msk (0x3u << I2SC_SSR_RXORCH_Pos) /**< \brief (I2SC_SSR) Receive Overrun Per Channel Status Set */
+#define I2SC_SSR_RXORCH(value) ((I2SC_SSR_RXORCH_Msk & ((value) << I2SC_SSR_RXORCH_Pos)))
+#define I2SC_SSR_TXURCH_Pos 20
+#define I2SC_SSR_TXURCH_Msk (0x3u << I2SC_SSR_TXURCH_Pos) /**< \brief (I2SC_SSR) Transmit Underrun Per Channel Status Set */
+#define I2SC_SSR_TXURCH(value) ((I2SC_SSR_TXURCH_Msk & ((value) << I2SC_SSR_TXURCH_Pos)))
+/* -------- I2SC_IER : (I2SC Offset: 0x14) Interrupt Enable Register -------- */
+#define I2SC_IER_RXRDY (0x1u << 1) /**< \brief (I2SC_IER) Receiver Ready Interrupt Enable */
+#define I2SC_IER_RXOR (0x1u << 2) /**< \brief (I2SC_IER) Receiver Overrun Interrupt Enable */
+#define I2SC_IER_ENDRX (0x1u << 3) /**< \brief (I2SC_IER) End of Reception Interrupt Enable */
+#define I2SC_IER_TXRDY (0x1u << 5) /**< \brief (I2SC_IER) Transmit Ready Interrupt Enable */
+#define I2SC_IER_TXUR (0x1u << 6) /**< \brief (I2SC_IER) Transmit Underflow Interrupt Enable */
+#define I2SC_IER_ENDTX (0x1u << 7) /**< \brief (I2SC_IER) End of Transmission Interrupt Enable */
+#define I2SC_IER_RXFULL (0x1u << 19) /**< \brief (I2SC_IER) Receive Buffer Full Interrupt Enable */
+#define I2SC_IER_TXEMPTY (0x1u << 31) /**< \brief (I2SC_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- I2SC_IDR : (I2SC Offset: 0x18) Interrupt Disable Register -------- */
+#define I2SC_IDR_RXRDY (0x1u << 1) /**< \brief (I2SC_IDR) Receiver Ready Interrupt Disable */
+#define I2SC_IDR_RXOR (0x1u << 2) /**< \brief (I2SC_IDR) Receiver Overrun Interrupt Disable */
+#define I2SC_IDR_ENDRX (0x1u << 3) /**< \brief (I2SC_IDR) End of Reception Interrupt Disable */
+#define I2SC_IDR_TXRDY (0x1u << 5) /**< \brief (I2SC_IDR) Transmit Ready Interrupt Disable */
+#define I2SC_IDR_TXUR (0x1u << 6) /**< \brief (I2SC_IDR) Transmit Underflow Interrupt Disable */
+#define I2SC_IDR_ENDTX (0x1u << 7) /**< \brief (I2SC_IDR) End of Transmission Interrupt Disable */
+#define I2SC_IDR_RXFULL (0x1u << 19) /**< \brief (I2SC_IDR) Receive Buffer Full Interrupt Disable */
+#define I2SC_IDR_TXEMPTY (0x1u << 31) /**< \brief (I2SC_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- I2SC_IMR : (I2SC Offset: 0x1C) Interrupt Mask Register -------- */
+#define I2SC_IMR_RXRDY (0x1u << 1) /**< \brief (I2SC_IMR) Receiver Ready Interrupt Disable */
+#define I2SC_IMR_RXOR (0x1u << 2) /**< \brief (I2SC_IMR) Receiver Overrun Interrupt Disable */
+#define I2SC_IMR_ENDRX (0x1u << 3) /**< \brief (I2SC_IMR) End of Reception Interrupt Disable */
+#define I2SC_IMR_TXRDY (0x1u << 5) /**< \brief (I2SC_IMR) Transmit Ready Interrupt Disable */
+#define I2SC_IMR_TXUR (0x1u << 6) /**< \brief (I2SC_IMR) Transmit Underflow Interrupt Disable */
+#define I2SC_IMR_ENDTX (0x1u << 7) /**< \brief (I2SC_IMR) End of Transmission Interrupt Disable */
+#define I2SC_IMR_RXFULL (0x1u << 19) /**< \brief (I2SC_IMR) Receive Buffer Full Interrupt Disable */
+#define I2SC_IMR_TXEMPTY (0x1u << 31) /**< \brief (I2SC_IMR) Transmit Buffer Empty Interrupt Disable */
+/* -------- I2SC_RHR : (I2SC Offset: 0x20) Receiver Holding Register -------- */
+#define I2SC_RHR_RHR_Pos 0
+#define I2SC_RHR_RHR_Msk (0xffffffffu << I2SC_RHR_RHR_Pos) /**< \brief (I2SC_RHR) Receiver Holding Register */
+/* -------- I2SC_THR : (I2SC Offset: 0x24) Transmitter Holding Register -------- */
+#define I2SC_THR_THR_Pos 0
+#define I2SC_THR_THR_Msk (0xffffffffu << I2SC_THR_THR_Pos) /**< \brief (I2SC_THR) Transmitter Holding Register */
+#define I2SC_THR_THR(value) ((I2SC_THR_THR_Msk & ((value) << I2SC_THR_THR_Pos)))
+/* -------- I2SC_RPR : (I2SC Offset: 0x100) Receive Pointer Register -------- */
+#define I2SC_RPR_RXPTR_Pos 0
+#define I2SC_RPR_RXPTR_Msk (0xffffffffu << I2SC_RPR_RXPTR_Pos) /**< \brief (I2SC_RPR) Receive Pointer Register */
+#define I2SC_RPR_RXPTR(value) ((I2SC_RPR_RXPTR_Msk & ((value) << I2SC_RPR_RXPTR_Pos)))
+/* -------- I2SC_RCR : (I2SC Offset: 0x104) Receive Counter Register -------- */
+#define I2SC_RCR_RXCTR_Pos 0
+#define I2SC_RCR_RXCTR_Msk (0xffffu << I2SC_RCR_RXCTR_Pos) /**< \brief (I2SC_RCR) Receive Counter Register */
+#define I2SC_RCR_RXCTR(value) ((I2SC_RCR_RXCTR_Msk & ((value) << I2SC_RCR_RXCTR_Pos)))
+/* -------- I2SC_TPR : (I2SC Offset: 0x108) Transmit Pointer Register -------- */
+#define I2SC_TPR_TXPTR_Pos 0
+#define I2SC_TPR_TXPTR_Msk (0xffffffffu << I2SC_TPR_TXPTR_Pos) /**< \brief (I2SC_TPR) Transmit Counter Register */
+#define I2SC_TPR_TXPTR(value) ((I2SC_TPR_TXPTR_Msk & ((value) << I2SC_TPR_TXPTR_Pos)))
+/* -------- I2SC_TCR : (I2SC Offset: 0x10C) Transmit Counter Register -------- */
+#define I2SC_TCR_TXCTR_Pos 0
+#define I2SC_TCR_TXCTR_Msk (0xffffu << I2SC_TCR_TXCTR_Pos) /**< \brief (I2SC_TCR) Transmit Counter Register */
+#define I2SC_TCR_TXCTR(value) ((I2SC_TCR_TXCTR_Msk & ((value) << I2SC_TCR_TXCTR_Pos)))
+/* -------- I2SC_RNPR : (I2SC Offset: 0x110) Receive Next Pointer Register -------- */
+#define I2SC_RNPR_RXNPTR_Pos 0
+#define I2SC_RNPR_RXNPTR_Msk (0xffffffffu << I2SC_RNPR_RXNPTR_Pos) /**< \brief (I2SC_RNPR) Receive Next Pointer */
+#define I2SC_RNPR_RXNPTR(value) ((I2SC_RNPR_RXNPTR_Msk & ((value) << I2SC_RNPR_RXNPTR_Pos)))
+/* -------- I2SC_RNCR : (I2SC Offset: 0x114) Receive Next Counter Register -------- */
+#define I2SC_RNCR_RXNCTR_Pos 0
+#define I2SC_RNCR_RXNCTR_Msk (0xffffu << I2SC_RNCR_RXNCTR_Pos) /**< \brief (I2SC_RNCR) Receive Next Counter */
+#define I2SC_RNCR_RXNCTR(value) ((I2SC_RNCR_RXNCTR_Msk & ((value) << I2SC_RNCR_RXNCTR_Pos)))
+/* -------- I2SC_TNPR : (I2SC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define I2SC_TNPR_TXNPTR_Pos 0
+#define I2SC_TNPR_TXNPTR_Msk (0xffffffffu << I2SC_TNPR_TXNPTR_Pos) /**< \brief (I2SC_TNPR) Transmit Next Pointer */
+#define I2SC_TNPR_TXNPTR(value) ((I2SC_TNPR_TXNPTR_Msk & ((value) << I2SC_TNPR_TXNPTR_Pos)))
+/* -------- I2SC_TNCR : (I2SC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define I2SC_TNCR_TXNCTR_Pos 0
+#define I2SC_TNCR_TXNCTR_Msk (0xffffu << I2SC_TNCR_TXNCTR_Pos) /**< \brief (I2SC_TNCR) Transmit Counter Next */
+#define I2SC_TNCR_TXNCTR(value) ((I2SC_TNCR_TXNCTR_Msk & ((value) << I2SC_TNCR_TXNCTR_Pos)))
+/* -------- I2SC_PTCR : (I2SC Offset: 0x120) Transfer Control Register -------- */
+#define I2SC_PTCR_RXTEN (0x1u << 0) /**< \brief (I2SC_PTCR) Receiver Transfer Enable */
+#define I2SC_PTCR_RXTDIS (0x1u << 1) /**< \brief (I2SC_PTCR) Receiver Transfer Disable */
+#define I2SC_PTCR_TXTEN (0x1u << 8) /**< \brief (I2SC_PTCR) Transmitter Transfer Enable */
+#define I2SC_PTCR_TXTDIS (0x1u << 9) /**< \brief (I2SC_PTCR) Transmitter Transfer Disable */
+#define I2SC_PTCR_RXCBEN (0x1u << 16) /**< \brief (I2SC_PTCR) Receiver Circular Buffer Enable */
+#define I2SC_PTCR_RXCBDIS (0x1u << 17) /**< \brief (I2SC_PTCR) Receiver Circular Buffer Disable */
+#define I2SC_PTCR_TXCBEN (0x1u << 18) /**< \brief (I2SC_PTCR) Transmitter Circular Buffer Enable */
+#define I2SC_PTCR_TXCBDIS (0x1u << 19) /**< \brief (I2SC_PTCR) Transmitter Circular Buffer Disable */
+#define I2SC_PTCR_ERRCLR (0x1u << 24) /**< \brief (I2SC_PTCR) Transfer Bus Error Clear */
+/* -------- I2SC_PTSR : (I2SC Offset: 0x124) Transfer Status Register -------- */
+#define I2SC_PTSR_RXTEN (0x1u << 0) /**< \brief (I2SC_PTSR) Receiver Transfer Enable */
+#define I2SC_PTSR_TXTEN (0x1u << 8) /**< \brief (I2SC_PTSR) Transmitter Transfer Enable */
+#define I2SC_PTSR_RXCBEN (0x1u << 16) /**< \brief (I2SC_PTSR) Receiver Transfer Enable */
+#define I2SC_PTSR_TXCBEN (0x1u << 18) /**< \brief (I2SC_PTSR) Transmitter Transfer Enable */
+#define I2SC_PTSR_ERR (0x1u << 24) /**< \brief (I2SC_PTSR) Transfer Bus Error (clear on read) */
+
+/*@}*/
+
+
+#endif /* _SAMG55_I2SC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_matrix.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,216 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_MATRIX_COMPONENT_
+#define _SAMG55_MATRIX_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAMG55_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Matrix hardware registers */
+typedef struct {
+ __IO uint32_t MATRIX_MCFG[3]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
+ __I uint32_t Reserved1[13];
+ __IO uint32_t MATRIX_SCFG[4]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
+ __I uint32_t Reserved2[12];
+ __IO uint32_t MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
+ __I uint32_t Reserved3[1];
+ __IO uint32_t MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
+ __I uint32_t Reserved4[1];
+ __IO uint32_t MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
+ __I uint32_t Reserved5[1];
+ __IO uint32_t MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
+ __I uint32_t Reserved6[1];
+ __I uint32_t Reserved7[28];
+ __IO uint32_t CCFG_RDMMEM; /**< \brief (Matrix Offset: 0x0110) Embedded Memories Read Margin Values Register */
+ __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration Register */
+ __IO uint32_t CCFG_DYNCKG; /**< \brief (Matrix Offset: 0x0118) Dynamic Clock Gating Register */
+ __IO uint32_t CCFG_I2SCLKSEL; /**< \brief (Matrix Offset: 0x011C) I2S Clock Source Selection Register */
+ __IO uint32_t CCFG_USBMR; /**< \brief (Matrix Offset: 0x0120) USB Management Register */
+ __I uint32_t Reserved8[48];
+ __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protection Mode Register */
+ __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protection Status Register */
+} Matrix;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- MATRIX_MCFG[3] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
+#define MATRIX_MCFG_ULBT_Pos 0
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[3]) Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
+#define MATRIX_MCFG_ULBT_INFINITE (0x0u << 0) /**< \brief (MATRIX_MCFG[3]) No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken. */
+#define MATRIX_MCFG_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG[3]) The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst. */
+#define MATRIX_MCFG_ULBT_FOUR_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG[3]) The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end. */
+#define MATRIX_MCFG_ULBT_EIGHT_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG[3]) The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end. */
+#define MATRIX_MCFG_ULBT_SIXTEEN_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG[3]) The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end. */
+/* -------- MATRIX_SCFG[4] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[4]) Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[4]) Default Master Type */
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_NO_DEFAULT (0x0u << 16) /**< \brief (MATRIX_SCFG[4]) At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in having a one cycle latency for the first access of a burst transfer or for a single access. */
+#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG[4]) At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having the one cycle latency when the last master tries to access the slave again. */
+#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG[4]) At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having the one cycle latency when the fixed master tries to access the slave again. */
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[4]) Fixed Default Master */
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
+#define MATRIX_SCFG_ARBT_Pos 24
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[4]) Arbitration Type */
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
+#define MATRIX_SCFG_ARBT_ROUND_ROBIN (0x0u << 24) /**< \brief (MATRIX_SCFG[4]) Round-robin arbitration */
+#define MATRIX_SCFG_ARBT_FIXED_PRIORITY (0x1u << 24) /**< \brief (MATRIX_SCFG[4]) Fixed priority arbitration */
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS0_M0PR_Pos 0
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
+#define MATRIX_PRAS0_M1PR_Pos 4
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
+#define MATRIX_PRAS0_M2PR_Pos 8
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
+#define MATRIX_PRAS0_M3PR_Pos 12
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
+#define MATRIX_PRAS1_M0PR_Pos 0
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
+#define MATRIX_PRAS1_M1PR_Pos 4
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
+#define MATRIX_PRAS1_M2PR_Pos 8
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
+#define MATRIX_PRAS1_M3PR_Pos 12
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
+#define MATRIX_PRAS2_M0PR_Pos 0
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
+#define MATRIX_PRAS2_M1PR_Pos 4
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
+#define MATRIX_PRAS2_M2PR_Pos 8
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
+#define MATRIX_PRAS2_M3PR_Pos 12
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
+#define MATRIX_PRAS3_M0PR_Pos 0
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
+#define MATRIX_PRAS3_M1PR_Pos 4
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
+#define MATRIX_PRAS3_M2PR_Pos 8
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
+#define MATRIX_PRAS3_M3PR_Pos 12
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
+/* -------- CCFG_RDMMEM : (MATRIX Offset: 0x0110) Embedded Memories Read Margin Values Register -------- */
+#define CCFG_RDMMEM_READ_MARGIN_ROM_Pos 0
+#define CCFG_RDMMEM_READ_MARGIN_ROM_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_ROM_Pos) /**< \brief (CCFG_RDMMEM) ROM Read Margin Value Selection */
+#define CCFG_RDMMEM_READ_MARGIN_ROM(value) ((CCFG_RDMMEM_READ_MARGIN_ROM_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_ROM_Pos)))
+#define CCFG_RDMMEM_READ_MARGIN_DPRAM_Pos 4
+#define CCFG_RDMMEM_READ_MARGIN_DPRAM_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_DPRAM_Pos) /**< \brief (CCFG_RDMMEM) DPRAM Read Margin Value Selection */
+#define CCFG_RDMMEM_READ_MARGIN_DPRAM(value) ((CCFG_RDMMEM_READ_MARGIN_DPRAM_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_DPRAM_Pos)))
+#define CCFG_RDMMEM_READ_MARGIN_RAM32k_Pos 8
+#define CCFG_RDMMEM_READ_MARGIN_RAM32k_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_RAM32k_Pos) /**< \brief (CCFG_RDMMEM) RAM32k Read Margin Value Selection */
+#define CCFG_RDMMEM_READ_MARGIN_RAM32k(value) ((CCFG_RDMMEM_READ_MARGIN_RAM32k_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_RAM32k_Pos)))
+#define CCFG_RDMMEM_READ_MARGIN_RAM16k_Pos 12
+#define CCFG_RDMMEM_READ_MARGIN_RAM16k_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_RAM16k_Pos) /**< \brief (CCFG_RDMMEM) RAM16k Read Margin Value Selection */
+#define CCFG_RDMMEM_READ_MARGIN_RAM16k(value) ((CCFG_RDMMEM_READ_MARGIN_RAM16k_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_RAM16k_Pos)))
+#define CCFG_RDMMEM_READ_MARGIN_RAM8k_Pos 16
+#define CCFG_RDMMEM_READ_MARGIN_RAM8k_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_RAM8k_Pos) /**< \brief (CCFG_RDMMEM) RAM8k Read Margin Value Selection */
+#define CCFG_RDMMEM_READ_MARGIN_RAM8k(value) ((CCFG_RDMMEM_READ_MARGIN_RAM8k_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_RAM8k_Pos)))
+#define CCFG_RDMMEM_READ_MARGIN_RAM4k_Pos 20
+#define CCFG_RDMMEM_READ_MARGIN_RAM4k_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_RAM4k_Pos) /**< \brief (CCFG_RDMMEM) RAM4k Read Margin Value Selection */
+#define CCFG_RDMMEM_READ_MARGIN_RAM4k(value) ((CCFG_RDMMEM_READ_MARGIN_RAM4k_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_RAM4k_Pos)))
+#define CCFG_RDMMEM_READ_MARGIN_REGFILE0_Pos 24
+#define CCFG_RDMMEM_READ_MARGIN_REGFILE0_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_REGFILE0_Pos) /**< \brief (CCFG_RDMMEM) REGFILE0 Read Margin Value Selection */
+#define CCFG_RDMMEM_READ_MARGIN_REGFILE0(value) ((CCFG_RDMMEM_READ_MARGIN_REGFILE0_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_REGFILE0_Pos)))
+#define CCFG_RDMMEM_READ_MARGIN_REGFILE1_Pos 28
+#define CCFG_RDMMEM_READ_MARGIN_REGFILE1_Msk (0xfu << CCFG_RDMMEM_READ_MARGIN_REGFILE1_Pos) /**< \brief (CCFG_RDMMEM) REGFILE1 Read Margin Value Selection */
+#define CCFG_RDMMEM_READ_MARGIN_REGFILE1(value) ((CCFG_RDMMEM_READ_MARGIN_REGFILE1_Msk & ((value) << CCFG_RDMMEM_READ_MARGIN_REGFILE1_Pos)))
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration Register -------- */
+#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */
+#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */
+#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */
+#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */
+#define CCFG_SYSIO_SYSIO10 (0x1u << 10) /**< \brief (CCFG_SYSIO) PA21 or DM Assignment */
+#define CCFG_SYSIO_SYSIO11 (0x1u << 11) /**< \brief (CCFG_SYSIO) PA22 or DP Assignment */
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */
+/* -------- CCFG_DYNCKG : (MATRIX Offset: 0x0118) Dynamic Clock Gating Register -------- */
+#define CCFG_DYNCKG_MATCKG (0x1u << 0) /**< \brief (CCFG_DYNCKG) MATRIX Dynamic Clock Gating */
+#define CCFG_DYNCKG_BRIDCKG (0x1u << 1) /**< \brief (CCFG_DYNCKG) Bridge Dynamic Clock Gating Enable */
+#define CCFG_DYNCKG_EFCCKG (0x1u << 2) /**< \brief (CCFG_DYNCKG) EFC Dynamic Clock Gating Enable */
+/* -------- CCFG_I2SCLKSEL : (MATRIX Offset: 0x011C) I2S Clock Source Selection Register -------- */
+#define CCFG_I2SCLKSEL_CLKSEL0 (0x1u << 0) /**< \brief (CCFG_I2SCLKSEL) I2S0 clock source */
+#define CCFG_I2SCLKSEL_CLKSEL1 (0x1u << 1) /**< \brief (CCFG_I2SCLKSEL) I2S1 clock source */
+/* -------- CCFG_USBMR : (MATRIX Offset: 0x0120) USB Management Register -------- */
+#define CCFG_USBMR_DEVICE (0x1u << 0) /**< \brief (CCFG_USBMR) USB device mode */
+#define CCFG_USBMR_USBHTSSC (0x1u << 1) /**< \brief (CCFG_USBMR) USB Transceiver Suspend Software Control */
+#define CCFG_USBMR_USBHTSC (0x1u << 2) /**< \brief (CCFG_USBMR) USB Host Transceiver Suspend Control */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protection Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key */
+#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protection Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAMG55_MATRIX_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_mem2mem.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,150 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_MEM2MEM_COMPONENT_
+#define _SAMG55_MEM2MEM_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Memory to Memory */
+/* ============================================================================= */
+/** \addtogroup SAMG55_MEM2MEM Memory to Memory */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Mem2mem hardware registers */
+typedef struct {
+ __IO uint32_t MEM2MEM_THR; /**< \brief (Mem2mem Offset: 0x00) Memory to Memory Transfer Holding Register */
+ __IO uint32_t MEM2MEM_MR; /**< \brief (Mem2mem Offset: 0x04) Memory to Memory Mode Register */
+ __O uint32_t MEM2MEM_IER; /**< \brief (Mem2mem Offset: 0x08) Memory to Memory Interrupt Enable Register */
+ __O uint32_t MEM2MEM_IDR; /**< \brief (Mem2mem Offset: 0x0C) Memory to Memory Interrupt Disable Register */
+ __I uint32_t MEM2MEM_IMR; /**< \brief (Mem2mem Offset: 0x10) Memory to Memory Interrupt Mask Register */
+ __I uint32_t MEM2MEM_ISR; /**< \brief (Mem2mem Offset: 0x14) Memory to Memory Interrupt Status Register */
+ __I uint32_t Reserved1[58];
+ __IO uint32_t MEM2MEM_RPR; /**< \brief (Mem2mem Offset: 0x100) Receive Pointer Register */
+ __IO uint32_t MEM2MEM_RCR; /**< \brief (Mem2mem Offset: 0x104) Receive Counter Register */
+ __IO uint32_t MEM2MEM_TPR; /**< \brief (Mem2mem Offset: 0x108) Transmit Pointer Register */
+ __IO uint32_t MEM2MEM_TCR; /**< \brief (Mem2mem Offset: 0x10C) Transmit Counter Register */
+ __IO uint32_t MEM2MEM_RNPR; /**< \brief (Mem2mem Offset: 0x110) Receive Next Pointer Register */
+ __IO uint32_t MEM2MEM_RNCR; /**< \brief (Mem2mem Offset: 0x114) Receive Next Counter Register */
+ __IO uint32_t MEM2MEM_TNPR; /**< \brief (Mem2mem Offset: 0x118) Transmit Next Pointer Register */
+ __IO uint32_t MEM2MEM_TNCR; /**< \brief (Mem2mem Offset: 0x11C) Transmit Next Counter Register */
+ __O uint32_t MEM2MEM_PTCR; /**< \brief (Mem2mem Offset: 0x120) Transfer Control Register */
+ __I uint32_t MEM2MEM_PTSR; /**< \brief (Mem2mem Offset: 0x124) Transfer Status Register */
+} Mem2mem;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- MEM2MEM_THR : (MEM2MEM Offset: 0x00) Memory to Memory Transfer Holding Register -------- */
+#define MEM2MEM_THR_THDATA_Pos 0
+#define MEM2MEM_THR_THDATA_Msk (0xffffffffu << MEM2MEM_THR_THDATA_Pos) /**< \brief (MEM2MEM_THR) Transfer Holding Data */
+#define MEM2MEM_THR_THDATA(value) ((MEM2MEM_THR_THDATA_Msk & ((value) << MEM2MEM_THR_THDATA_Pos)))
+/* -------- MEM2MEM_MR : (MEM2MEM Offset: 0x04) Memory to Memory Mode Register -------- */
+#define MEM2MEM_MR_TSIZE_Pos 0
+#define MEM2MEM_MR_TSIZE_Msk (0x3u << MEM2MEM_MR_TSIZE_Pos) /**< \brief (MEM2MEM_MR) Transfer Size */
+#define MEM2MEM_MR_TSIZE_T_8BIT (0x0u << 0) /**< \brief (MEM2MEM_MR) The buffer size is defined in byte. */
+#define MEM2MEM_MR_TSIZE_T_16BIT (0x1u << 0) /**< \brief (MEM2MEM_MR) The buffer size is defined in half-word (16-bit). */
+#define MEM2MEM_MR_TSIZE_T_32BIT (0x2u << 0) /**< \brief (MEM2MEM_MR) The buffer size is defined in word (32-bit). Default value. */
+/* -------- MEM2MEM_IER : (MEM2MEM Offset: 0x08) Memory to Memory Interrupt Enable Register -------- */
+#define MEM2MEM_IER_RXEND (0x1u << 0) /**< \brief (MEM2MEM_IER) End of Transfer Interrupt Enable */
+#define MEM2MEM_IER_RXBUFF (0x1u << 1) /**< \brief (MEM2MEM_IER) Buffer Full Interrupt Enable */
+/* -------- MEM2MEM_IDR : (MEM2MEM Offset: 0x0C) Memory to Memory Interrupt Disable Register -------- */
+#define MEM2MEM_IDR_RXEND (0x1u << 0) /**< \brief (MEM2MEM_IDR) End of Transfer Interrupt Disable */
+#define MEM2MEM_IDR_RXBUFF (0x1u << 1) /**< \brief (MEM2MEM_IDR) Buffer Full Interrupt Disable */
+/* -------- MEM2MEM_IMR : (MEM2MEM Offset: 0x10) Memory to Memory Interrupt Mask Register -------- */
+#define MEM2MEM_IMR_RXEND (0x1u << 0) /**< \brief (MEM2MEM_IMR) End of Transfer Interrupt Mask */
+#define MEM2MEM_IMR_RXBUFF (0x1u << 1) /**< \brief (MEM2MEM_IMR) Buffer Full Interrupt Mask */
+/* -------- MEM2MEM_ISR : (MEM2MEM Offset: 0x14) Memory to Memory Interrupt Status Register -------- */
+#define MEM2MEM_ISR_RXEND (0x1u << 0) /**< \brief (MEM2MEM_ISR) End of Transfer */
+#define MEM2MEM_ISR_RXBUFF (0x1u << 1) /**< \brief (MEM2MEM_ISR) Buffer Full */
+/* -------- MEM2MEM_RPR : (MEM2MEM Offset: 0x100) Receive Pointer Register -------- */
+#define MEM2MEM_RPR_RXPTR_Pos 0
+#define MEM2MEM_RPR_RXPTR_Msk (0xffffffffu << MEM2MEM_RPR_RXPTR_Pos) /**< \brief (MEM2MEM_RPR) Receive Pointer Register */
+#define MEM2MEM_RPR_RXPTR(value) ((MEM2MEM_RPR_RXPTR_Msk & ((value) << MEM2MEM_RPR_RXPTR_Pos)))
+/* -------- MEM2MEM_RCR : (MEM2MEM Offset: 0x104) Receive Counter Register -------- */
+#define MEM2MEM_RCR_RXCTR_Pos 0
+#define MEM2MEM_RCR_RXCTR_Msk (0xffffu << MEM2MEM_RCR_RXCTR_Pos) /**< \brief (MEM2MEM_RCR) Receive Counter Register */
+#define MEM2MEM_RCR_RXCTR(value) ((MEM2MEM_RCR_RXCTR_Msk & ((value) << MEM2MEM_RCR_RXCTR_Pos)))
+/* -------- MEM2MEM_TPR : (MEM2MEM Offset: 0x108) Transmit Pointer Register -------- */
+#define MEM2MEM_TPR_TXPTR_Pos 0
+#define MEM2MEM_TPR_TXPTR_Msk (0xffffffffu << MEM2MEM_TPR_TXPTR_Pos) /**< \brief (MEM2MEM_TPR) Transmit Counter Register */
+#define MEM2MEM_TPR_TXPTR(value) ((MEM2MEM_TPR_TXPTR_Msk & ((value) << MEM2MEM_TPR_TXPTR_Pos)))
+/* -------- MEM2MEM_TCR : (MEM2MEM Offset: 0x10C) Transmit Counter Register -------- */
+#define MEM2MEM_TCR_TXCTR_Pos 0
+#define MEM2MEM_TCR_TXCTR_Msk (0xffffu << MEM2MEM_TCR_TXCTR_Pos) /**< \brief (MEM2MEM_TCR) Transmit Counter Register */
+#define MEM2MEM_TCR_TXCTR(value) ((MEM2MEM_TCR_TXCTR_Msk & ((value) << MEM2MEM_TCR_TXCTR_Pos)))
+/* -------- MEM2MEM_RNPR : (MEM2MEM Offset: 0x110) Receive Next Pointer Register -------- */
+#define MEM2MEM_RNPR_RXNPTR_Pos 0
+#define MEM2MEM_RNPR_RXNPTR_Msk (0xffffffffu << MEM2MEM_RNPR_RXNPTR_Pos) /**< \brief (MEM2MEM_RNPR) Receive Next Pointer */
+#define MEM2MEM_RNPR_RXNPTR(value) ((MEM2MEM_RNPR_RXNPTR_Msk & ((value) << MEM2MEM_RNPR_RXNPTR_Pos)))
+/* -------- MEM2MEM_RNCR : (MEM2MEM Offset: 0x114) Receive Next Counter Register -------- */
+#define MEM2MEM_RNCR_RXNCTR_Pos 0
+#define MEM2MEM_RNCR_RXNCTR_Msk (0xffffu << MEM2MEM_RNCR_RXNCTR_Pos) /**< \brief (MEM2MEM_RNCR) Receive Next Counter */
+#define MEM2MEM_RNCR_RXNCTR(value) ((MEM2MEM_RNCR_RXNCTR_Msk & ((value) << MEM2MEM_RNCR_RXNCTR_Pos)))
+/* -------- MEM2MEM_TNPR : (MEM2MEM Offset: 0x118) Transmit Next Pointer Register -------- */
+#define MEM2MEM_TNPR_TXNPTR_Pos 0
+#define MEM2MEM_TNPR_TXNPTR_Msk (0xffffffffu << MEM2MEM_TNPR_TXNPTR_Pos) /**< \brief (MEM2MEM_TNPR) Transmit Next Pointer */
+#define MEM2MEM_TNPR_TXNPTR(value) ((MEM2MEM_TNPR_TXNPTR_Msk & ((value) << MEM2MEM_TNPR_TXNPTR_Pos)))
+/* -------- MEM2MEM_TNCR : (MEM2MEM Offset: 0x11C) Transmit Next Counter Register -------- */
+#define MEM2MEM_TNCR_TXNCTR_Pos 0
+#define MEM2MEM_TNCR_TXNCTR_Msk (0xffffu << MEM2MEM_TNCR_TXNCTR_Pos) /**< \brief (MEM2MEM_TNCR) Transmit Counter Next */
+#define MEM2MEM_TNCR_TXNCTR(value) ((MEM2MEM_TNCR_TXNCTR_Msk & ((value) << MEM2MEM_TNCR_TXNCTR_Pos)))
+/* -------- MEM2MEM_PTCR : (MEM2MEM Offset: 0x120) Transfer Control Register -------- */
+#define MEM2MEM_PTCR_RXTEN (0x1u << 0) /**< \brief (MEM2MEM_PTCR) Receiver Transfer Enable */
+#define MEM2MEM_PTCR_RXTDIS (0x1u << 1) /**< \brief (MEM2MEM_PTCR) Receiver Transfer Disable */
+#define MEM2MEM_PTCR_TXTEN (0x1u << 8) /**< \brief (MEM2MEM_PTCR) Transmitter Transfer Enable */
+#define MEM2MEM_PTCR_TXTDIS (0x1u << 9) /**< \brief (MEM2MEM_PTCR) Transmitter Transfer Disable */
+#define MEM2MEM_PTCR_RXCBEN (0x1u << 16) /**< \brief (MEM2MEM_PTCR) Receiver Circular Buffer Enable */
+#define MEM2MEM_PTCR_RXCBDIS (0x1u << 17) /**< \brief (MEM2MEM_PTCR) Receiver Circular Buffer Disable */
+#define MEM2MEM_PTCR_TXCBEN (0x1u << 18) /**< \brief (MEM2MEM_PTCR) Transmitter Circular Buffer Enable */
+#define MEM2MEM_PTCR_TXCBDIS (0x1u << 19) /**< \brief (MEM2MEM_PTCR) Transmitter Circular Buffer Disable */
+#define MEM2MEM_PTCR_ERRCLR (0x1u << 24) /**< \brief (MEM2MEM_PTCR) Transfer Bus Error Clear */
+/* -------- MEM2MEM_PTSR : (MEM2MEM Offset: 0x124) Transfer Status Register -------- */
+#define MEM2MEM_PTSR_RXTEN (0x1u << 0) /**< \brief (MEM2MEM_PTSR) Receiver Transfer Enable */
+#define MEM2MEM_PTSR_TXTEN (0x1u << 8) /**< \brief (MEM2MEM_PTSR) Transmitter Transfer Enable */
+#define MEM2MEM_PTSR_RXCBEN (0x1u << 16) /**< \brief (MEM2MEM_PTSR) Receiver Transfer Enable */
+#define MEM2MEM_PTSR_TXCBEN (0x1u << 18) /**< \brief (MEM2MEM_PTSR) Transmitter Transfer Enable */
+#define MEM2MEM_PTSR_ERR (0x1u << 24) /**< \brief (MEM2MEM_PTSR) Transfer Bus Error (clear on read) */
+
+/*@}*/
+
+
+#endif /* _SAMG55_MEM2MEM_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pdc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,121 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_PDC_COMPONENT_
+#define _SAMG55_PDC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAMG55_PDC Peripheral DMA Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pdc hardware registers */
+typedef struct {
+ __IO uint32_t PERIPH_RPR; /**< \brief (Pdc Offset: 0x00) Receive Pointer Register */
+ __IO uint32_t PERIPH_RCR; /**< \brief (Pdc Offset: 0x04) Receive Counter Register */
+ __IO uint32_t PERIPH_TPR; /**< \brief (Pdc Offset: 0x08) Transmit Pointer Register */
+ __IO uint32_t PERIPH_TCR; /**< \brief (Pdc Offset: 0x0C) Transmit Counter Register */
+ __IO uint32_t PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
+ __IO uint32_t PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
+ __IO uint32_t PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
+ __IO uint32_t PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
+ __O uint32_t PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
+ __I uint32_t PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
+} Pdc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PERIPH_RPR : (PDC Offset: 0x00) Receive Pointer Register -------- */
+#define PERIPH_RPR_RXPTR_Pos 0
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
+/* -------- PERIPH_RCR : (PDC Offset: 0x04) Receive Counter Register -------- */
+#define PERIPH_RCR_RXCTR_Pos 0
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
+/* -------- PERIPH_TPR : (PDC Offset: 0x08) Transmit Pointer Register -------- */
+#define PERIPH_TPR_TXPTR_Pos 0
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
+/* -------- PERIPH_TCR : (PDC Offset: 0x0C) Transmit Counter Register -------- */
+#define PERIPH_TCR_TXCTR_Pos 0
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
+#define PERIPH_RNPR_RXNPTR_Pos 0
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
+#define PERIPH_RNCR_RXNCTR_Pos 0
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
+#define PERIPH_TNPR_TXNPTR_Pos 0
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
+#define PERIPH_TNCR_TXNCTR_Pos 0
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
+#define PERIPH_PTCR_RXCBEN (0x1u << 16) /**< \brief (PERIPH_PTCR) Receiver Circular Buffer Enable */
+#define PERIPH_PTCR_RXCBDIS (0x1u << 17) /**< \brief (PERIPH_PTCR) Receiver Circular Buffer Disable */
+#define PERIPH_PTCR_TXCBEN (0x1u << 18) /**< \brief (PERIPH_PTCR) Transmitter Circular Buffer Enable */
+#define PERIPH_PTCR_TXCBDIS (0x1u << 19) /**< \brief (PERIPH_PTCR) Transmitter Circular Buffer Disable */
+#define PERIPH_PTCR_ERRCLR (0x1u << 24) /**< \brief (PERIPH_PTCR) Transfer Bus Error Clear */
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+#define PERIPH_PTSR_RXCBEN (0x1u << 16) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXCBEN (0x1u << 18) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+#define PERIPH_PTSR_ERR (0x1u << 24) /**< \brief (PERIPH_PTSR) Transfer Bus Error (clear on read) */
+
+/*@}*/
+
+
+#endif /* _SAMG55_PDC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pdmic.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,180 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_PDMIC_COMPONENT_
+#define _SAMG55_PDMIC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Pulse Density Modulation Interface Controller */
+/* ============================================================================= */
+/** \addtogroup SAMG55_PDMIC Pulse Density Modulation Interface Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pdmic hardware registers */
+typedef struct {
+ __IO uint32_t PDMIC_CR; /**< \brief (Pdmic Offset: 0x00) Control Register */
+ __IO uint32_t PDMIC_MR; /**< \brief (Pdmic Offset: 0x04) Mode Register */
+ __I uint32_t Reserved1[3];
+ __I uint32_t PDMIC_CDR; /**< \brief (Pdmic Offset: 0x14) Converted Data Register */
+ __O uint32_t PDMIC_IER; /**< \brief (Pdmic Offset: 0x18) Interrupt Enable Register */
+ __O uint32_t PDMIC_IDR; /**< \brief (Pdmic Offset: 0x1C) Interrupt Disable Register */
+ __I uint32_t PDMIC_IMR; /**< \brief (Pdmic Offset: 0x20) Interrupt Mask Register */
+ __I uint32_t PDMIC_ISR; /**< \brief (Pdmic Offset: 0x24) Interrupt Status Register */
+ __I uint32_t Reserved2[12];
+ __IO uint32_t PDMIC_DSPR0; /**< \brief (Pdmic Offset: 0x58) DSP Configuration Register 0 */
+ __IO uint32_t PDMIC_DSPR1; /**< \brief (Pdmic Offset: 0x5C) DSP Configuration Register 1 */
+ __I uint32_t Reserved3[33];
+ __IO uint32_t PDMIC_WPMR; /**< \brief (Pdmic Offset: 0xE4) Write Protection Mode Register */
+ __I uint32_t PDMIC_WPSR; /**< \brief (Pdmic Offset: 0xE8) Write Protection Status Register */
+ __I uint32_t Reserved4[5];
+ __IO uint32_t PDMIC_RPR; /**< \brief (Pdmic Offset: 0x100) Receive Pointer Register */
+ __IO uint32_t PDMIC_RCR; /**< \brief (Pdmic Offset: 0x104) Receive Counter Register */
+ __I uint32_t Reserved5[2];
+ __IO uint32_t PDMIC_RNPR; /**< \brief (Pdmic Offset: 0x110) Receive Next Pointer Register */
+ __IO uint32_t PDMIC_RNCR; /**< \brief (Pdmic Offset: 0x114) Receive Next Counter Register */
+ __I uint32_t Reserved6[2];
+ __O uint32_t PDMIC_PTCR; /**< \brief (Pdmic Offset: 0x120) Transfer Control Register */
+ __I uint32_t PDMIC_PTSR; /**< \brief (Pdmic Offset: 0x124) Transfer Status Register */
+} Pdmic;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PDMIC_CR : (PDMIC Offset: 0x00) Control Register -------- */
+#define PDMIC_CR_SWRST (0x1u << 0) /**< \brief (PDMIC_CR) Software Reset */
+#define PDMIC_CR_ENPDM (0x1u << 4) /**< \brief (PDMIC_CR) Enable PDM */
+/* -------- PDMIC_MR : (PDMIC Offset: 0x04) Mode Register -------- */
+#define PDMIC_MR_PRESCAL_Pos 8
+#define PDMIC_MR_PRESCAL_Msk (0x7fu << PDMIC_MR_PRESCAL_Pos) /**< \brief (PDMIC_MR) Prescaler Rate Selection */
+#define PDMIC_MR_PRESCAL(value) ((PDMIC_MR_PRESCAL_Msk & ((value) << PDMIC_MR_PRESCAL_Pos)))
+/* -------- PDMIC_CDR : (PDMIC Offset: 0x14) Converted Data Register -------- */
+#define PDMIC_CDR_DATA_Pos 0
+#define PDMIC_CDR_DATA_Msk (0xffffffffu << PDMIC_CDR_DATA_Pos) /**< \brief (PDMIC_CDR) Data Converted */
+/* -------- PDMIC_IER : (PDMIC Offset: 0x18) Interrupt Enable Register -------- */
+#define PDMIC_IER_DRDY (0x1u << 24) /**< \brief (PDMIC_IER) Data Ready Interrupt Enable */
+#define PDMIC_IER_OVRE (0x1u << 25) /**< \brief (PDMIC_IER) Overrun Error Interrupt Enable */
+#define PDMIC_IER_ENDRX (0x1u << 27) /**< \brief (PDMIC_IER) End of Receive Buffer Interrupt Enable */
+#define PDMIC_IER_RXBUFF (0x1u << 28) /**< \brief (PDMIC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- PDMIC_IDR : (PDMIC Offset: 0x1C) Interrupt Disable Register -------- */
+#define PDMIC_IDR_DRDY (0x1u << 24) /**< \brief (PDMIC_IDR) Data Ready Interrupt Disable */
+#define PDMIC_IDR_OVRE (0x1u << 25) /**< \brief (PDMIC_IDR) General Overrun Error Interrupt Disable */
+#define PDMIC_IDR_ENDRX (0x1u << 27) /**< \brief (PDMIC_IDR) End of Receive Buffer Interrupt Disable */
+#define PDMIC_IDR_RXBUFF (0x1u << 28) /**< \brief (PDMIC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- PDMIC_IMR : (PDMIC Offset: 0x20) Interrupt Mask Register -------- */
+#define PDMIC_IMR_DRDY (0x1u << 24) /**< \brief (PDMIC_IMR) Data Ready Interrupt Mask */
+#define PDMIC_IMR_OVRE (0x1u << 25) /**< \brief (PDMIC_IMR) General Overrun Error Interrupt Mask */
+#define PDMIC_IMR_ENDRX (0x1u << 27) /**< \brief (PDMIC_IMR) End of Receive Buffer Interrupt Mask */
+#define PDMIC_IMR_RXBUFF (0x1u << 28) /**< \brief (PDMIC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- PDMIC_ISR : (PDMIC Offset: 0x24) Interrupt Status Register -------- */
+#define PDMIC_ISR_FIFOCNT_Pos 16
+#define PDMIC_ISR_FIFOCNT_Msk (0xffu << PDMIC_ISR_FIFOCNT_Pos) /**< \brief (PDMIC_ISR) FIFO Count */
+#define PDMIC_ISR_DRDY (0x1u << 24) /**< \brief (PDMIC_ISR) Data Ready */
+#define PDMIC_ISR_OVRE (0x1u << 25) /**< \brief (PDMIC_ISR) Overrun Error */
+#define PDMIC_ISR_ENDRX (0x1u << 27) /**< \brief (PDMIC_ISR) End of RX Buffer */
+#define PDMIC_ISR_RXBUFF (0x1u << 28) /**< \brief (PDMIC_ISR) RX Buffer Full */
+/* -------- PDMIC_DSPR0 : (PDMIC Offset: 0x58) DSP Configuration Register 0 -------- */
+#define PDMIC_DSPR0_HPFBYP (0x1u << 1) /**< \brief (PDMIC_DSPR0) High-Pass Filter Bypass */
+#define PDMIC_DSPR0_SINBYP (0x1u << 2) /**< \brief (PDMIC_DSPR0) SINCC Filter Bypass */
+#define PDMIC_DSPR0_SIZE (0x1u << 3) /**< \brief (PDMIC_DSPR0) Data Size */
+#define PDMIC_DSPR0_OSR_Pos 4
+#define PDMIC_DSPR0_OSR_Msk (0x7u << PDMIC_DSPR0_OSR_Pos) /**< \brief (PDMIC_DSPR0) Oversampling Ratio */
+#define PDMIC_DSPR0_OSR_128 (0x0u << 4) /**< \brief (PDMIC_DSPR0) Oversampling ratio is 128 */
+#define PDMIC_DSPR0_OSR_64 (0x1u << 4) /**< \brief (PDMIC_DSPR0) Oversampling ratio is 64 */
+#define PDMIC_DSPR0_SCALE_Pos 8
+#define PDMIC_DSPR0_SCALE_Msk (0xfu << PDMIC_DSPR0_SCALE_Pos) /**< \brief (PDMIC_DSPR0) Data Scale */
+#define PDMIC_DSPR0_SCALE(value) ((PDMIC_DSPR0_SCALE_Msk & ((value) << PDMIC_DSPR0_SCALE_Pos)))
+#define PDMIC_DSPR0_SHIFT_Pos 12
+#define PDMIC_DSPR0_SHIFT_Msk (0xfu << PDMIC_DSPR0_SHIFT_Pos) /**< \brief (PDMIC_DSPR0) Data Shift */
+#define PDMIC_DSPR0_SHIFT(value) ((PDMIC_DSPR0_SHIFT_Msk & ((value) << PDMIC_DSPR0_SHIFT_Pos)))
+/* -------- PDMIC_DSPR1 : (PDMIC Offset: 0x5C) DSP Configuration Register 1 -------- */
+#define PDMIC_DSPR1_DGAIN_Pos 0
+#define PDMIC_DSPR1_DGAIN_Msk (0x7fffu << PDMIC_DSPR1_DGAIN_Pos) /**< \brief (PDMIC_DSPR1) Gain Correction */
+#define PDMIC_DSPR1_DGAIN(value) ((PDMIC_DSPR1_DGAIN_Msk & ((value) << PDMIC_DSPR1_DGAIN_Pos)))
+#define PDMIC_DSPR1_OFFSET_Pos 16
+#define PDMIC_DSPR1_OFFSET_Msk (0xffffu << PDMIC_DSPR1_OFFSET_Pos) /**< \brief (PDMIC_DSPR1) Offset Correction */
+#define PDMIC_DSPR1_OFFSET(value) ((PDMIC_DSPR1_OFFSET_Msk & ((value) << PDMIC_DSPR1_OFFSET_Pos)))
+/* -------- PDMIC_WPMR : (PDMIC Offset: 0xE4) Write Protection Mode Register -------- */
+#define PDMIC_WPMR_WPEN (0x1u << 0) /**< \brief (PDMIC_WPMR) Write Protection Enable */
+#define PDMIC_WPMR_WPKEY_Pos 8
+#define PDMIC_WPMR_WPKEY_Msk (0xffffffu << PDMIC_WPMR_WPKEY_Pos) /**< \brief (PDMIC_WPMR) Write Protect Key */
+#define PDMIC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (PDMIC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
+/* -------- PDMIC_WPSR : (PDMIC Offset: 0xE8) Write Protection Status Register -------- */
+#define PDMIC_WPSR_WPVS (0x1u << 0) /**< \brief (PDMIC_WPSR) Write Protection Violation Status */
+#define PDMIC_WPSR_WPVSRC_Pos 8
+#define PDMIC_WPSR_WPVSRC_Msk (0xffffu << PDMIC_WPSR_WPVSRC_Pos) /**< \brief (PDMIC_WPSR) Write Protection Violation Source */
+/* -------- PDMIC_RPR : (PDMIC Offset: 0x100) Receive Pointer Register -------- */
+#define PDMIC_RPR_RXPTR_Pos 0
+#define PDMIC_RPR_RXPTR_Msk (0xffffffffu << PDMIC_RPR_RXPTR_Pos) /**< \brief (PDMIC_RPR) Receive Pointer Register */
+#define PDMIC_RPR_RXPTR(value) ((PDMIC_RPR_RXPTR_Msk & ((value) << PDMIC_RPR_RXPTR_Pos)))
+/* -------- PDMIC_RCR : (PDMIC Offset: 0x104) Receive Counter Register -------- */
+#define PDMIC_RCR_RXCTR_Pos 0
+#define PDMIC_RCR_RXCTR_Msk (0xffffu << PDMIC_RCR_RXCTR_Pos) /**< \brief (PDMIC_RCR) Receive Counter Register */
+#define PDMIC_RCR_RXCTR(value) ((PDMIC_RCR_RXCTR_Msk & ((value) << PDMIC_RCR_RXCTR_Pos)))
+/* -------- PDMIC_RNPR : (PDMIC Offset: 0x110) Receive Next Pointer Register -------- */
+#define PDMIC_RNPR_RXNPTR_Pos 0
+#define PDMIC_RNPR_RXNPTR_Msk (0xffffffffu << PDMIC_RNPR_RXNPTR_Pos) /**< \brief (PDMIC_RNPR) Receive Next Pointer */
+#define PDMIC_RNPR_RXNPTR(value) ((PDMIC_RNPR_RXNPTR_Msk & ((value) << PDMIC_RNPR_RXNPTR_Pos)))
+/* -------- PDMIC_RNCR : (PDMIC Offset: 0x114) Receive Next Counter Register -------- */
+#define PDMIC_RNCR_RXNCTR_Pos 0
+#define PDMIC_RNCR_RXNCTR_Msk (0xffffu << PDMIC_RNCR_RXNCTR_Pos) /**< \brief (PDMIC_RNCR) Receive Next Counter */
+#define PDMIC_RNCR_RXNCTR(value) ((PDMIC_RNCR_RXNCTR_Msk & ((value) << PDMIC_RNCR_RXNCTR_Pos)))
+/* -------- PDMIC_PTCR : (PDMIC Offset: 0x120) Transfer Control Register -------- */
+#define PDMIC_PTCR_RXTEN (0x1u << 0) /**< \brief (PDMIC_PTCR) Receiver Transfer Enable */
+#define PDMIC_PTCR_RXTDIS (0x1u << 1) /**< \brief (PDMIC_PTCR) Receiver Transfer Disable */
+#define PDMIC_PTCR_TXTEN (0x1u << 8) /**< \brief (PDMIC_PTCR) Transmitter Transfer Enable */
+#define PDMIC_PTCR_TXTDIS (0x1u << 9) /**< \brief (PDMIC_PTCR) Transmitter Transfer Disable */
+#define PDMIC_PTCR_RXCBEN (0x1u << 16) /**< \brief (PDMIC_PTCR) Receiver Circular Buffer Enable */
+#define PDMIC_PTCR_RXCBDIS (0x1u << 17) /**< \brief (PDMIC_PTCR) Receiver Circular Buffer Disable */
+#define PDMIC_PTCR_TXCBEN (0x1u << 18) /**< \brief (PDMIC_PTCR) Transmitter Circular Buffer Enable */
+#define PDMIC_PTCR_TXCBDIS (0x1u << 19) /**< \brief (PDMIC_PTCR) Transmitter Circular Buffer Disable */
+#define PDMIC_PTCR_ERRCLR (0x1u << 24) /**< \brief (PDMIC_PTCR) Transfer Bus Error Clear */
+/* -------- PDMIC_PTSR : (PDMIC Offset: 0x124) Transfer Status Register -------- */
+#define PDMIC_PTSR_RXTEN (0x1u << 0) /**< \brief (PDMIC_PTSR) Receiver Transfer Enable */
+#define PDMIC_PTSR_TXTEN (0x1u << 8) /**< \brief (PDMIC_PTSR) Transmitter Transfer Enable */
+#define PDMIC_PTSR_RXCBEN (0x1u << 16) /**< \brief (PDMIC_PTSR) Receiver Transfer Enable */
+#define PDMIC_PTSR_TXCBEN (0x1u << 18) /**< \brief (PDMIC_PTSR) Transmitter Transfer Enable */
+#define PDMIC_PTSR_ERR (0x1u << 24) /**< \brief (PDMIC_PTSR) Transfer Bus Error (clear on read) */
+
+/*@}*/
+
+
+#endif /* _SAMG55_PDMIC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pio.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,1555 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_PIO_COMPONENT_
+#define _SAMG55_PIO_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
+/* ============================================================================= */
+/** \addtogroup SAMG55_PIO Parallel Input/Output Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pio hardware registers */
+typedef struct {
+ __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
+ __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
+ __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */
+ __I uint32_t Reserved1[1];
+ __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */
+ __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */
+ __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */
+ __I uint32_t Reserved2[1];
+ __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
+ __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
+ __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
+ __I uint32_t Reserved3[1];
+ __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
+ __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
+ __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
+ __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
+ __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
+ __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
+ __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
+ __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
+ __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
+ __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
+ __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
+ __I uint32_t Reserved4[1];
+ __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
+ __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
+ __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
+ __I uint32_t Reserved5[1];
+ __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */
+ __I uint32_t Reserved6[2];
+ __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */
+ __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */
+ __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */
+ __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
+ __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */
+ __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */
+ __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */
+ __I uint32_t Reserved7[1];
+ __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
+ __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
+ __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
+ __I uint32_t Reserved8[1];
+ __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
+ __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */
+ __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
+ __I uint32_t Reserved9[1];
+ __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
+ __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */
+ __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
+ __I uint32_t Reserved10[1];
+ __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */
+ __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/High-Level Select Register */
+ __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
+ __I uint32_t Reserved11[2];
+ __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */
+ __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */
+ __I uint32_t Reserved12[5];
+ __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */
+ __I uint32_t Reserved13[3];
+ __IO uint32_t PIO_DRIVER; /**< \brief (Pio Offset: 0x0110) I/O Drive Register */
+} Pio;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-Drive Enable */
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-Drive Enable */
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-Drive Disable */
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-Drive Status */
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-Drive Status */
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */
+/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */
+#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
+/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */
+#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
+/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */
+#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
+/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */
+#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
+#define PIO_SCDR_DIV_Pos 0
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
+/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */
+#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */
+/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */
+#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */
+#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */
+/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */
+#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */
+#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status */
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High-Level Select Register -------- */
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */
+#define PIO_WPMR_WPKEY_Pos 8
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key. */
+#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */
+#define PIO_WPSR_WPVSRC_Pos 8
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */
+/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */
+#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
+
+/*@}*/
+
+
+#endif /* _SAMG55_PIO_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_pmc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,593 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_PMC_COMPONENT_
+#define _SAMG55_PMC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAMG55_PMC Power Management Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pmc hardware registers */
+typedef struct {
+ __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+ __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+ __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+ __I uint32_t Reserved1[1];
+ __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+ __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+ __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+ __I uint32_t Reserved2[1];
+ __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+ __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+ __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+ __IO uint32_t CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */
+ __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+ __I uint32_t Reserved3[1];
+ __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
+ __I uint32_t Reserved4[1];
+ __IO uint32_t PMC_PCK[8]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+ __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+ __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+ __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */
+ __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+ __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
+ __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
+ __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+ __I uint32_t Reserved5[26];
+ __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register */
+ __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */
+ __I uint32_t PMC_ADDRSIZE; /**< \brief (Pmc Offset: 0x00EC) Address Size Register */
+ __I uint32_t PMC_IPNAME[2]; /**< \brief (Pmc Offset: 0x00F0) IP Name1 Register */
+ __I uint32_t PMC_FEATURES; /**< \brief (Pmc Offset: 0x00F8) Features Register */
+ __I uint32_t PMC_VERSION; /**< \brief (Pmc Offset: 0x00FC) Version Register */
+ __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */
+ __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */
+ __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */
+ __I uint32_t Reserved7[1];
+ __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */
+ __O uint32_t PMC_SLPWK_ER0; /**< \brief (Pmc Offset: 0x114) SleepWalking Enable Register 0 */
+ __O uint32_t PMC_SLPWK_DR0; /**< \brief (Pmc Offset: 0x118) SleepWalking Disable Register 0 */
+ __I uint32_t PMC_SLPWK_SR0; /**< \brief (Pmc Offset: 0x11C) SleepWalking Status Register 0 */
+ __I uint32_t PMC_SLPWK_ASR0; /**< \brief (Pmc Offset: 0x120) SleepWalking Activity Status Register 0 */
+ __I uint32_t Reserved8[3];
+ __IO uint32_t PMC_PMMR; /**< \brief (Pmc Offset: 0x130) PLL Maximum Multiplier Value Register */
+} Pmc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_UHP (0x1u << 6) /**< \brief (PMC_SCER) USB Host Port Clock Enable */
+#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+#define PMC_SCER_PCK3 (0x1u << 11) /**< \brief (PMC_SCER) Programmable Clock 3 Output Enable */
+#define PMC_SCER_PCK4 (0x1u << 12) /**< \brief (PMC_SCER) Programmable Clock 4 Output Enable */
+#define PMC_SCER_PCK5 (0x1u << 13) /**< \brief (PMC_SCER) Programmable Clock 5 Output Enable */
+#define PMC_SCER_PCK6 (0x1u << 14) /**< \brief (PMC_SCER) Programmable Clock 6 Output Enable */
+#define PMC_SCER_PCK7 (0x1u << 15) /**< \brief (PMC_SCER) Programmable Clock 7 Output Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_UHP (0x1u << 6) /**< \brief (PMC_SCDR) USB Host Port Clock Disable */
+#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+#define PMC_SCDR_PCK3 (0x1u << 11) /**< \brief (PMC_SCDR) Programmable Clock 3 Output Disable */
+#define PMC_SCDR_PCK4 (0x1u << 12) /**< \brief (PMC_SCDR) Programmable Clock 4 Output Disable */
+#define PMC_SCDR_PCK5 (0x1u << 13) /**< \brief (PMC_SCDR) Programmable Clock 5 Output Disable */
+#define PMC_SCDR_PCK6 (0x1u << 14) /**< \brief (PMC_SCDR) Programmable Clock 6 Output Disable */
+#define PMC_SCDR_PCK7 (0x1u << 15) /**< \brief (PMC_SCDR) Programmable Clock 7 Output Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_UHP (0x1u << 6) /**< \brief (PMC_SCSR) USB Host Port Clock Status */
+#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+#define PMC_SCSR_PCK3 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 3 Output Status */
+#define PMC_SCSR_PCK4 (0x1u << 12) /**< \brief (PMC_SCSR) Programmable Clock 4 Output Status */
+#define PMC_SCSR_PCK5 (0x1u << 13) /**< \brief (PMC_SCSR) Programmable Clock 5 Output Status */
+#define PMC_SCSR_PCK6 (0x1u << 14) /**< \brief (PMC_SCSR) Programmable Clock 6 Output Status */
+#define PMC_SCSR_PCK7 (0x1u << 15) /**< \brief (PMC_SCSR) Programmable Clock 7 Output Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
+#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
+#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
+#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
+#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
+#define CKGR_MOR_MOSCRCF_Pos 4
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
+#define CKGR_MOR_MOSCRCF_8_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz (default) */
+#define CKGR_MOR_MOSCRCF_16_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 16 MHz */
+#define CKGR_MOR_MOSCRCF_24_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 24 MHz */
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */
+#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
+#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_PLLAEN_Pos 0
+#define CKGR_PLLAR_PLLAEN_Msk (0xffu << CKGR_PLLAR_PLLAEN_Pos) /**< \brief (CKGR_PLLAR) PLLA Control */
+#define CKGR_PLLAR_PLLAEN(value) ((CKGR_PLLAR_PLLAEN_Msk & ((value) << CKGR_PLLAR_PLLAEN_Pos)))
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_MULA_Pos 16
+#define CKGR_PLLAR_MULA_Msk (0x1fffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+/* -------- CKGR_PLLBR : (PMC Offset: 0x002c) PLLB Register -------- */
+#define CKGR_PLLBR_PLLBEN_Pos 0
+#define CKGR_PLLBR_PLLBEN_Msk (0xffu << CKGR_PLLBR_PLLBEN_Pos) /**< \brief (CKGR_PLLBR) PLLB Control */
+#define CKGR_PLLBR_PLLBEN(value) ((CKGR_PLLBR_PLLBEN_Msk & ((value) << CKGR_PLLBR_PLLBEN_Pos)))
+#define CKGR_PLLBR_PLLBCOUNT_Pos 8
+#define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */
+#define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos)))
+#define CKGR_PLLBR_MULB_Pos 16
+#define CKGR_PLLBR_MULB_Msk (0xfffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */
+#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos)))
+
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
+#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
+#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
+#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
+#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
+#define PMC_MCKR_PLLBDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */
+#define PMC_USB_USBDIV_Pos 8
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock */
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
+/* -------- PMC_PCK[8] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
+#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
+#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
+#define PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */
+#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
+#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
+#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
+#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
+#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
+#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
+#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
+#define PMC_IER_LOCKB (0x1u << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable */
+#define PMC_IER_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IER) Programmable Clock Ready 4 Interrupt Enable */
+#define PMC_IER_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IER) Programmable Clock Ready 5 Interrupt Enable */
+#define PMC_IER_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IER) Programmable Clock Ready 6 Interrupt Enable */
+#define PMC_IER_PCKRDY7 (0x1u << 15) /**< \brief (PMC_IER) Programmable Clock Ready 7 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
+#define PMC_IDR_LOCKB (0x1u << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable */
+#define PMC_IDR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable */
+#define PMC_IDR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable */
+#define PMC_IDR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable */
+#define PMC_IDR_PCKRDY7 (0x1u << 15) /**< \brief (PMC_IDR) Programmable Clock Ready 7 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
+#define PMC_SR_LOCKB (0x1u << 2) /**< \brief (PMC_SR) PLLB Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY7 (0x1u << 15) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
+#define PMC_IMR_LOCKB (0x1u << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */
+#define PMC_FSMR_FLPM_Pos 21
+#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low-power Mode */
+#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */
+#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in deep-power-down mode when system enters Wait Mode */
+#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) idle mode */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */
+#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */
+/* -------- PMC_ADDRSIZE : (PMC Offset: 0x00EC) Address Size Register -------- */
+#define PMC_ADDRSIZE_ADDRSIZE_Pos 0
+#define PMC_ADDRSIZE_ADDRSIZE_Msk (0xffffu << PMC_ADDRSIZE_ADDRSIZE_Pos) /**< \brief (PMC_ADDRSIZE) Peripheral Bus Address Area Size */
+/* -------- PMC_IPNAME[2] : (PMC Offset: 0x00F0) IP Name1 Register -------- */
+#define PMC_IPNAME_IPNAME_Pos 0
+#define PMC_IPNAME_IPNAME_Msk (0xffffffffu << PMC_IPNAME_IPNAME_Pos) /**< \brief (PMC_IPNAME[2]) IP Name in ASCII Format */
+/* -------- PMC_VERSION : (PMC Offset: 0x00FC) Version Register -------- */
+#define PMC_VERSION_VERSION_Pos 0
+#define PMC_VERSION_VERSION_Msk (0xfffu << PMC_VERSION_VERSION_Pos) /**< \brief (PMC_VERSION) Version of the Hardware Module */
+#define PMC_VERSION_MFN_Pos 16
+#define PMC_VERSION_MFN_Msk (0x7u << PMC_VERSION_MFN_Pos) /**< \brief (PMC_VERSION) Metal Fix Number */
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
+#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */
+#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */
+#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */
+#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */
+#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */
+#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */
+#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */
+#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */
+#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */
+#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */
+#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */
+#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */
+#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */
+#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */
+#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
+#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */
+#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */
+#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */
+#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */
+#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */
+#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */
+#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */
+#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */
+#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */
+#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */
+#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */
+#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */
+#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */
+#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */
+#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
+#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */
+#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */
+#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */
+#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */
+#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */
+#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */
+#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */
+#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */
+#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */
+#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */
+#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */
+#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */
+#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */
+#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */
+#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */
+/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
+#define PMC_OCR_CAL8_Pos 0
+#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */
+#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
+#define PMC_OCR_SEL8 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */
+#define PMC_OCR_CAL16_Pos 8
+#define PMC_OCR_CAL16_Msk (0x7fu << PMC_OCR_CAL16_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 16 MHz */
+#define PMC_OCR_CAL16(value) ((PMC_OCR_CAL16_Msk & ((value) << PMC_OCR_CAL16_Pos)))
+#define PMC_OCR_SEL16 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 16 MHz */
+#define PMC_OCR_CAL24_Pos 16
+#define PMC_OCR_CAL24_Msk (0x7fu << PMC_OCR_CAL24_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 24 MHz */
+#define PMC_OCR_CAL24(value) ((PMC_OCR_CAL24_Msk & ((value) << PMC_OCR_CAL24_Pos)))
+#define PMC_OCR_SEL24 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 24 MHz */
+/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x114) SleepWalking Enable Register 0 -------- */
+#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable */
+#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable */
+/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x118) SleepWalking Disable Register 0 -------- */
+#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable */
+#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable */
+/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x11C) SleepWalking Status Register 0 -------- */
+#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status */
+#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status */
+/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x120) SleepWalking Activity Status Register 0 -------- */
+#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status */
+#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status */
+#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status */
+#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status */
+#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status */
+#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status */
+#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status */
+#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status */
+#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status */
+#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status */
+#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status */
+#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status */
+#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status */
+#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status */
+#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status */
+#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status */
+#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status */
+#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status */
+#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status */
+#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status */
+#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status */
+#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status */
+/* -------- PMC_PMMR : (PMC Offset: 0x130) PLL Maximum Multiplier Value Register -------- */
+#define PMC_PMMR_PLLA_MMAX_Pos 0
+#define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos) /**< \brief (PMC_PMMR) PLLA Maximum Allowed Multiplier Value */
+#define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAMG55_PMC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rstc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,95 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_RSTC_COMPONENT_
+#define _SAMG55_RSTC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAMG55_RSTC Reset Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rstc hardware registers */
+typedef struct {
+ __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+ __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+ __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */
+#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up reset */
+#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */
+#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */
+#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */
+#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */
+#define RSTC_SR_RSTTYP_SLCK_XTAL_RST (0x7u << 8) /**< \brief (RSTC_SR) Slow Crystal Failure Detection fault occured */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_SCKSW (0x1u << 1) /**< \brief (RSTC_MR) Slow Clock Switching */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_Pos 8
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */
+#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */
+
+/*@}*/
+
+
+#endif /* _SAMG55_RSTC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rtc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,226 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_RTC_COMPONENT_
+#define _SAMG55_RTC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAMG55_RTC Real-time Clock */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtc hardware registers */
+typedef struct {
+ __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */
+ __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */
+ __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */
+ __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+ __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+ __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+ __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */
+ __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+ __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+ __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+ __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+ __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+ __I uint32_t Reserved1[40];
+ __I uint32_t RTC_MSR; /**< \brief (Rtc Offset: 0xD0) Milliseconds Register */
+ __I uint32_t Reserved2[4];
+ __IO uint32_t RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protection Mode Register */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */
+#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */
+#define RTC_MR_CORRECTION_Pos 8
+#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */
+#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))
+#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */
+#define RTC_MR_OUT0_Pos 16
+#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) All ADC Channel Trigger Event Source Selection */
+#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */
+#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */
+#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */
+#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */
+#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */
+#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */
+#define RTC_MR_OUT1_Pos 20
+#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) ADC Last Channel Trigger Event Source Selection */
+#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */
+#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */
+#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */
+#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */
+#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */
+#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */
+#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */
+#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */
+#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */
+#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */
+#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */
+#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */
+#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */
+#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+/* -------- RTC_MSR : (RTC Offset: 0xD0) Milliseconds Register -------- */
+#define RTC_MSR_MS_Pos 0
+#define RTC_MSR_MS_Msk (0x3ffu << RTC_MSR_MS_Pos) /**< \brief (RTC_MSR) Number of 1/1024 seconds elapsed within 1 second */
+/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */
+#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protection Enable */
+#define RTC_WPMR_WPKEY_Pos 8
+#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) Write Protection Key */
+#define RTC_WPMR_WPKEY_PASSWD (0x525443u << 8) /**< \brief (RTC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
+
+/*@}*/
+
+
+#endif /* _SAMG55_RTC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rtt.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_RTT_COMPONENT_
+#define _SAMG55_RTT_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Real-time Timer */
+/* ============================================================================= */
+/** \addtogroup SAMG55_RTT Real-time Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtt hardware registers */
+typedef struct {
+ __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
+ __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
+ __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
+ __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
+ __IO uint32_t RTT_MODR; /**< \brief (Rtt Offset: 0x10) Modulo Selection Register */
+} Rtt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
+#define RTT_MR_RTPRES_Pos 0
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */
+#define RTT_MR_INC2AEN (0x1u << 21) /**< \brief (RTT_MR) RTTINC2 Alarm Enable */
+#define RTT_MR_EVAEN (0x1u << 22) /**< \brief (RTT_MR) Trigger Event Alarm Enable */
+#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
+#define RTT_AR_ALMV_Pos 0
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
+#define RTT_VR_CRTV_Pos 0
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Prescaler Roll-over Status */
+#define RTT_SR_RTTINC2 (0x1u << 2) /**< \brief (RTT_SR) Predefined Number of Prescaler Roll-over Status */
+/* -------- RTT_MODR : (RTT Offset: 0x10) Modulo Selection Register -------- */
+#define RTT_MODR_SELINC2_Pos 0
+#define RTT_MODR_SELINC2_Msk (0x7u << RTT_MODR_SELINC2_Pos) /**< \brief (RTT_MODR) Selection of the 32-bit Counter Modulo to generate RTTINC2 flag */
+#define RTT_MODR_SELINC2_NO_RTTINC2 (0x0u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag never rises */
+#define RTT_MODR_SELINC2_MOD64 (0x1u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag is set when CRTV modulo 64 equals 0 */
+#define RTT_MODR_SELINC2_MOD128 (0x2u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag is set when CRTV modulo 128 equals 0 */
+#define RTT_MODR_SELINC2_MOD256 (0x3u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag is set when CRTV modulo 256 equals 0 */
+#define RTT_MODR_SELINC2_MOD512 (0x4u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag is set when CRTV modulo 512 equals 0 */
+#define RTT_MODR_SELINC2_MOD1024 (0x5u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag is set when CRTV modulo 1024 equals 0.Example: If RTPRES=32 then RTTINC2 flag rises once per second if the slow clock is 32.768 kHz. */
+#define RTT_MODR_SELINC2_MOD2048 (0x6u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag is set when CRTV modulo 2048 equals 0 */
+#define RTT_MODR_SELINC2_MOD4096 (0x7u << 0) /**< \brief (RTT_MODR) The RTTINC2 flag is set when CRTV modulo 4096 equals 0 */
+#define RTT_MODR_SELTRGEV_Pos 8
+#define RTT_MODR_SELTRGEV_Msk (0x7u << RTT_MODR_SELTRGEV_Pos) /**< \brief (RTT_MODR) Selection of the 32-bit Counter Modulo to generate the trigger event */
+#define RTT_MODR_SELTRGEV_NO_EVENT (0x0u << 8) /**< \brief (RTT_MODR) No event generated */
+#define RTT_MODR_SELTRGEV_MOD2 (0x1u << 8) /**< \brief (RTT_MODR) Event occurs when CRTV modulo 2 equals 0 */
+#define RTT_MODR_SELTRGEV_MOD4 (0x2u << 8) /**< \brief (RTT_MODR) Event occurs when CRTV modulo 4 equals 0 */
+#define RTT_MODR_SELTRGEV_MOD8 (0x3u << 8) /**< \brief (RTT_MODR) Event occurs when CRTV modulo 8 equals 0 */
+#define RTT_MODR_SELTRGEV_MOD16 (0x4u << 8) /**< \brief (RTT_MODR) Event occurs when CRTV modulo 16 equals 0 */
+#define RTT_MODR_SELTRGEV_MOD32 (0x5u << 8) /**< \brief (RTT_MODR) Event occurs when CRTV modulo 32 equals 0 */
+#define RTT_MODR_SELTRGEV_MOD64 (0x6u << 8) /**< \brief (RTT_MODR) Event occurs when CRTV modulo 64 equals 0 */
+#define RTT_MODR_SELTRGEV_MOD128 (0x7u << 8) /**< \brief (RTT_MODR) Event occurs when CRTV modulo 128 equals 0 */
+
+/*@}*/
+
+
+#endif /* _SAMG55_RTT_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_spi.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,269 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_SPI_COMPONENT_
+#define _SAMG55_SPI_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAMG55_SPI Serial Peripheral Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Spi hardware registers */
+typedef struct {
+ __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x000) SPI Control Register */
+ __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x004) SPI Mode Register */
+ __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x008) SPI Receive Data Register */
+ __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x00C) SPI Transmit Data Register */
+ __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x010) SPI Status Register */
+ __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x014) SPI Interrupt Enable Register */
+ __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x018) SPI Interrupt Disable Register */
+ __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x01C) SPI Interrupt Mask Register */
+ __I uint32_t Reserved1[4];
+ __IO uint32_t SPI_CSR[2]; /**< \brief (Spi Offset: 0x030) SPI Chip Select Register */
+ __I uint32_t Reserved2[4];
+ __IO uint32_t SPI_CMPR; /**< \brief (Spi Offset: 0x048) SPI Comparison Register */
+ __I uint32_t Reserved3[38];
+ __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0x0E4) SPI Write Protection Mode Register */
+ __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0x0E8) SPI Write Protection Status Register */
+ __I uint32_t Reserved4[5];
+ __IO uint32_t SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */
+ __IO uint32_t SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */
+ __IO uint32_t SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */
+ __IO uint32_t SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */
+ __IO uint32_t SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */
+ __IO uint32_t SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */
+ __IO uint32_t SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */
+ __IO uint32_t SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */
+ __O uint32_t SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */
+ __I uint32_t SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */
+} Spi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SPI_CR : (SPI Offset: 0x000) SPI Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_REQCLR (0x1u << 12) /**< \brief (SPI_CR) Request to Clear the Comparison Trigger */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x004) SPI Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_BRSRCCLK (0x1u << 3) /**< \brief (SPI_MR) Bit Rate Source Clock */
+#define SPI_MR_BRSRCCLK_PERIPH_CLK (0x0u << 3) /**< \brief (SPI_MR) The peripheral clock is the source clock for the bit rate generation. */
+#define SPI_MR_BRSRCCLK_PMC_PCK (0x1u << 3) /**< \brief (SPI_MR) PMC PCKx is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock. */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_CMPMODE (0x1u << 12) /**< \brief (SPI_MR) Comparison Mode */
+#define SPI_MR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (SPI_MR) Any character is received and comparison function drives CMP flag. */
+#define SPI_MR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (SPI_MR) Comparison condition must be met to start reception of all incoming characters until REQCLR is set. */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0x3u << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x008) SPI Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+/* -------- SPI_TDR : (SPI Offset: 0x00C) SPI Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+/* -------- SPI_SR : (SPI Offset: 0x010) SPI Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (automatically set/cleared) */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (automatically set/cleared) */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */
+#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer (automatically set/cleared) */
+#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer (automatically set/cleared) */
+#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full (automatically set/cleared) */
+#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty (automatically set/cleared) */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (automatically set/cleared) */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (slave mode only) (cleared on read) */
+#define SPI_SR_CMP (0x1u << 11) /**< \brief (SPI_SR) Comparison Status (cleared on read) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status (automatically set/cleared) */
+/* -------- SPI_IER : (SPI Offset: 0x014) SPI Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */
+#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */
+#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */
+#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+#define SPI_IER_CMP (0x1u << 11) /**< \brief (SPI_IER) Comparison Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x018) SPI Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */
+#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */
+#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */
+#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+#define SPI_IDR_CMP (0x1u << 11) /**< \brief (SPI_IDR) Comparison Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x01C) SPI Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */
+#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */
+#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */
+#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+#define SPI_IMR_CMP (0x1u << 11) /**< \brief (SPI_IMR) Comparison Interrupt Mask */
+/* -------- SPI_CSR[2] : (SPI Offset: 0x030) SPI Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[2]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[2]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[2]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[2]) Chip Select Active After Transfer */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[2]) Bits Per Transfer */
+#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[2]) 8 bits for transfer */
+#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[2]) 9 bits for transfer */
+#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[2]) 10 bits for transfer */
+#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[2]) 11 bits for transfer */
+#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[2]) 12 bits for transfer */
+#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[2]) 13 bits for transfer */
+#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[2]) 14 bits for transfer */
+#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[2]) 15 bits for transfer */
+#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[2]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[2]) Serial Clock Bit Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[2]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[2]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_CMPR : (SPI Offset: 0x048) SPI Comparison Register -------- */
+#define SPI_CMPR_VAL1_Pos 0
+#define SPI_CMPR_VAL1_Msk (0xffffu << SPI_CMPR_VAL1_Pos) /**< \brief (SPI_CMPR) First Comparison Value for Received Character */
+#define SPI_CMPR_VAL1(value) ((SPI_CMPR_VAL1_Msk & ((value) << SPI_CMPR_VAL1_Pos)))
+#define SPI_CMPR_VAL2_Pos 16
+#define SPI_CMPR_VAL2_Msk (0xffffu << SPI_CMPR_VAL2_Pos) /**< \brief (SPI_CMPR) Second Comparison Value for Received Character */
+#define SPI_CMPR_VAL2(value) ((SPI_CMPR_VAL2_Msk & ((value) << SPI_CMPR_VAL2_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0x0E4) SPI Write Protection Mode Register -------- */
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */
+#define SPI_WPMR_WPKEY_Pos 8
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protect Key */
+#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */
+/* -------- SPI_WPSR : (SPI Offset: 0x0E8) SPI Write Protection Status Register -------- */
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */
+#define SPI_WPSR_WPVSRC_Pos 8
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */
+/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */
+#define SPI_RPR_RXPTR_Pos 0
+#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */
+#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))
+/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */
+#define SPI_RCR_RXCTR_Pos 0
+#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */
+#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))
+/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */
+#define SPI_TPR_TXPTR_Pos 0
+#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */
+#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))
+/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */
+#define SPI_TCR_TXCTR_Pos 0
+#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */
+#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))
+/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */
+#define SPI_RNPR_RXNPTR_Pos 0
+#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */
+#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))
+/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */
+#define SPI_RNCR_RXNCTR_Pos 0
+#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */
+#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))
+/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define SPI_TNPR_TXNPTR_Pos 0
+#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */
+#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))
+/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define SPI_TNCR_TXNCTR_Pos 0
+#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */
+#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))
+/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */
+#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */
+#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */
+#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */
+#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */
+#define SPI_PTCR_RXCBEN (0x1u << 16) /**< \brief (SPI_PTCR) Receiver Circular Buffer Enable */
+#define SPI_PTCR_RXCBDIS (0x1u << 17) /**< \brief (SPI_PTCR) Receiver Circular Buffer Disable */
+#define SPI_PTCR_TXCBEN (0x1u << 18) /**< \brief (SPI_PTCR) Transmitter Circular Buffer Enable */
+#define SPI_PTCR_TXCBDIS (0x1u << 19) /**< \brief (SPI_PTCR) Transmitter Circular Buffer Disable */
+#define SPI_PTCR_ERRCLR (0x1u << 24) /**< \brief (SPI_PTCR) Transfer Bus Error Clear */
+/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */
+#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */
+#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */
+#define SPI_PTSR_RXCBEN (0x1u << 16) /**< \brief (SPI_PTSR) Receiver Transfer Enable */
+#define SPI_PTSR_TXCBEN (0x1u << 18) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */
+#define SPI_PTSR_ERR (0x1u << 24) /**< \brief (SPI_PTSR) Transfer Bus Error (clear on read) */
+
+/*@}*/
+
+
+#endif /* _SAMG55_SPI_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_supc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,343 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_SUPC_COMPONENT_
+#define _SAMG55_SUPC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Supply Controller */
+/* ============================================================================= */
+/** \addtogroup SAMG55_SUPC Supply Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Supc hardware registers */
+typedef struct {
+ __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
+ __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
+ __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
+ __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */
+ __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */
+ __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
+ __I uint32_t Reserved1[1];
+ __IO uint32_t SUPC_PWMR; /**< \brief (Supc Offset: 0x1C) Supply Controller Power Mode Register */
+} Supc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
+#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) No effect. */
+#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) If KEY is correct, asserts the system reset signal and stops the voltage regulator. */
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
+#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) No effect. */
+#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) If KEY is correct, switches the slow clock on the crystal oscillator output. */
+#define SUPC_CR_KEY_Pos 24
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
+#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation.Always reads as 0. */
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
+#define SUPC_SMMR_SMTH_Pos 0
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
+#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos)))
+#define SUPC_SMMR_SMSMPL_Pos 8
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
+#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
+#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
+#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enables one SLCK period every 32 SLCK periods */
+#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enables one SLCK period every 256 SLCK periods */
+#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enables one SLCK period every 2,048 SLCK periods */
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
+#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is asserted when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
+#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) POR Core Reset Enable */
+#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */
+#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is asserted when a brownout detection occurs. */
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) POR Core Disable */
+#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) The core brownout detector is enabled. */
+#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) The core brownout detector is disabled. */
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
+#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) No effect. Clock selection depends on XTALSEL value. */
+#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) The 32 kHz crystal oscillator is selected and put in bypass mode. */
+#define SUPC_MR_CDPSWITCH (0x1u << 21) /**< \brief (SUPC_MR) Cache Data SRAM Power Switch */
+#define SUPC_MR_CDPSWITCH_OFF (0x0u << 21) /**< \brief (SUPC_MR) The cache data SRAM is not powered. */
+#define SUPC_MR_CDPSWITCH_ON (0x1u << 21) /**< \brief (SUPC_MR) The cache data SRAM is powered. */
+#define SUPC_MR_CTPSWITCH (0x1u << 22) /**< \brief (SUPC_MR) Cache Tag SRAM Power Switch */
+#define SUPC_MR_CTPSWITCH_OFF (0x0u << 22) /**< \brief (SUPC_MR) The cache tag SRAM is not powered. */
+#define SUPC_MR_CTPSWITCH_ON (0x1u << 22) /**< \brief (SUPC_MR) The cache tag SRAM is powered. */
+#define SUPC_MR_ONE (0x1u << 23) /**< \brief (SUPC_MR) This bit must always be set to 1. */
+#define SUPC_MR_KEY_Pos 24
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
+#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */
+#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection has no wake-up effect. */
+#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real-time Timer Wake-up Enable */
+#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real-time Clock Wake-up Enable */
+#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */
+#define SUPC_WUMR_WKUPDBC_Pos 12
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */
+#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 */
+#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 1 */
+#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 2 */
+#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 3 */
+#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 4 */
+#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 5 */
+#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 6 */
+#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 7 */
+#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 8 */
+#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 9 */
+#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 10 */
+#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 11 */
+#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 12 */
+#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 13 */
+#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake-up Input Enable 14 */
+#define SUPC_WUIR_WKUPEN14_DISABLE (0x0u << 14) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake-up Input Enable 15 */
+#define SUPC_WUIR_WKUPEN15_DISABLE (0x0u << 15) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 */
+#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 1 */
+#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 2 */
+#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 3 */
+#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 4 */
+#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 5 */
+#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 6 */
+#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 7 */
+#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 8 */
+#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 9 */
+#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 10 */
+#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 11 */
+#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 12 */
+#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 13 */
+#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake-up Input Type 14 */
+#define SUPC_WUIR_WKUPT14_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT14_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake-up Input Type 15 */
+#define SUPC_WUIR_WKUPT15_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) A low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SUPC_WUIR_WKUPT15_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) A high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status */
+#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
+#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
+#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
+#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
+#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */
+#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
+#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) The slow clock SLCK is generated by the embedded 32 kHz RC oscillator. */
+#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) The slow clock SLCK is generated by the 32 kHz crystal oscillator. */
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
+#define SUPC_SR_WKUPIS0_DISABLED (0x0u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS0_ENABLED (0x1u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
+#define SUPC_SR_WKUPIS1_DISABLED (0x0u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS1_ENABLED (0x1u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
+#define SUPC_SR_WKUPIS2_DISABLED (0x0u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS2_ENABLED (0x1u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
+#define SUPC_SR_WKUPIS3_DISABLED (0x0u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS3_ENABLED (0x1u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
+#define SUPC_SR_WKUPIS4_DISABLED (0x0u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS4_ENABLED (0x1u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
+#define SUPC_SR_WKUPIS5_DISABLED (0x0u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS5_ENABLED (0x1u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
+#define SUPC_SR_WKUPIS6_DISABLED (0x0u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS6_ENABLED (0x1u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
+#define SUPC_SR_WKUPIS7_DISABLED (0x0u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS7_ENABLED (0x1u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
+#define SUPC_SR_WKUPIS8_DISABLED (0x0u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS8_ENABLED (0x1u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
+#define SUPC_SR_WKUPIS9_DISABLED (0x0u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS9_ENABLED (0x1u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
+#define SUPC_SR_WKUPIS10_DISABLED (0x0u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS10_ENABLED (0x1u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
+#define SUPC_SR_WKUPIS11_DISABLED (0x0u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS11_ENABLED (0x1u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
+#define SUPC_SR_WKUPIS12_DISABLED (0x0u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS12_ENABLED (0x1u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
+#define SUPC_SR_WKUPIS13_DISABLED (0x0u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS13_ENABLED (0x1u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
+#define SUPC_SR_WKUPIS14_DISABLED (0x0u << 30) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS14_ENABLED (0x1u << 30) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
+#define SUPC_SR_WKUPIS15_DISABLED (0x0u << 31) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define SUPC_SR_WKUPIS15_ENABLED (0x1u << 31) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+/* -------- SUPC_PWMR : (SUPC Offset: 0x1C) Supply Controller Power Mode Register -------- */
+#define SUPC_PWMR_LPOWERS (0x1u << 0) /**< \brief (SUPC_PWMR) Low Power Value Selection */
+#define SUPC_PWMR_LPOWERS_FACTORY (0x0u << 0) /**< \brief (SUPC_PWMR) The trimming value applied to the regulator when the device is in wait mode. This value is factory-defined. */
+#define SUPC_PWMR_LPOWERS_USER (0x1u << 0) /**< \brief (SUPC_PWMR) The trimming value applied to the regulator is defined by the value programmed in the LPOWERx bits. */
+#define SUPC_PWMR_LPOWER0 (0x1u << 1) /**< \brief (SUPC_PWMR) Low Power Value */
+#define SUPC_PWMR_LPOWER1 (0x1u << 2) /**< \brief (SUPC_PWMR) Low Power Value */
+#define SUPC_PWMR_LPOWER2 (0x1u << 3) /**< \brief (SUPC_PWMR) Low Power Value */
+#define SUPC_PWMR_LPOWER3 (0x1u << 4) /**< \brief (SUPC_PWMR) Low Power Value */
+#define SUPC_PWMR_STUPTIME (0x1u << 7) /**< \brief (SUPC_PWMR) Start-up Time when Resuming from Wait Mode */
+#define SUPC_PWMR_STUPTIME_FAST (0x0u << 7) /**< \brief (SUPC_PWMR) Fast start-up. */
+#define SUPC_PWMR_STUPTIME_SLOW (0x1u << 7) /**< \brief (SUPC_PWMR) Slow start-up. */
+#define SUPC_PWMR_ECPWRS (0x1u << 8) /**< \brief (SUPC_PWMR) Enhanced Custom Power Value Selection */
+#define SUPC_PWMR_ECPWRS_FACTORY (0x0u << 8) /**< \brief (SUPC_PWMR) The trimming value applied to the regulator when the device is in active mode. This value is factory-defined. */
+#define SUPC_PWMR_ECPWRS_USER (0x1u << 8) /**< \brief (SUPC_PWMR) The trimming value applied to the regulator is defined by the value programmed in ECPWRx bits. */
+#define SUPC_PWMR_ECPWR0 (0x1u << 9) /**< \brief (SUPC_PWMR) Enhanced Custom Power Value */
+#define SUPC_PWMR_ECPWR1 (0x1u << 10) /**< \brief (SUPC_PWMR) Enhanced Custom Power Value */
+#define SUPC_PWMR_ECPWR2 (0x1u << 11) /**< \brief (SUPC_PWMR) Enhanced Custom Power Value */
+#define SUPC_PWMR_ECPWR3 (0x1u << 12) /**< \brief (SUPC_PWMR) Enhanced Custom Power Value */
+#define SUPC_PWMR_SRAM0ON (0x1u << 16) /**< \brief (SUPC_PWMR) SRAM Power Control */
+#define SUPC_PWMR_SRAM0ON_OFF (0x0u << 16) /**< \brief (SUPC_PWMR) SRAMx is not powered. */
+#define SUPC_PWMR_SRAM0ON_ON (0x1u << 16) /**< \brief (SUPC_PWMR) SRAMx is powered. */
+#define SUPC_PWMR_SRAM1ON (0x1u << 17) /**< \brief (SUPC_PWMR) SRAM Power Control */
+#define SUPC_PWMR_SRAM1ON_OFF (0x0u << 17) /**< \brief (SUPC_PWMR) SRAMx is not powered. */
+#define SUPC_PWMR_SRAM1ON_ON (0x1u << 17) /**< \brief (SUPC_PWMR) SRAMx is powered. */
+#define SUPC_PWMR_SRAM2ON (0x1u << 18) /**< \brief (SUPC_PWMR) SRAM Power Control */
+#define SUPC_PWMR_SRAM2ON_OFF (0x0u << 18) /**< \brief (SUPC_PWMR) SRAMx is not powered. */
+#define SUPC_PWMR_SRAM2ON_ON (0x1u << 18) /**< \brief (SUPC_PWMR) SRAMx is powered. */
+#define SUPC_PWMR_SRAM3ON (0x1u << 19) /**< \brief (SUPC_PWMR) SRAM Power Control */
+#define SUPC_PWMR_SRAM3ON_OFF (0x0u << 19) /**< \brief (SUPC_PWMR) SRAMx is not powered. */
+#define SUPC_PWMR_SRAM3ON_ON (0x1u << 19) /**< \brief (SUPC_PWMR) SRAMx is powered. */
+#define SUPC_PWMR_SRAM4ON (0x1u << 20) /**< \brief (SUPC_PWMR) SRAM Power Control */
+#define SUPC_PWMR_SRAM4ON_OFF (0x0u << 20) /**< \brief (SUPC_PWMR) SRAMx is not powered. */
+#define SUPC_PWMR_SRAM4ON_ON (0x1u << 20) /**< \brief (SUPC_PWMR) SRAMx is powered. */
+#define SUPC_PWMR_SRAM5ON (0x1u << 21) /**< \brief (SUPC_PWMR) SRAM Power Control */
+#define SUPC_PWMR_SRAM5ON_OFF (0x0u << 21) /**< \brief (SUPC_PWMR) SRAMx is not powered. */
+#define SUPC_PWMR_SRAM5ON_ON (0x1u << 21) /**< \brief (SUPC_PWMR) SRAMx is powered. */
+#define SUPC_PWMR_SRAM6ON (0x1u << 22) /**< \brief (SUPC_PWMR) SRAM Power Control */
+#define SUPC_PWMR_SRAM6ON_OFF (0x0u << 22) /**< \brief (SUPC_PWMR) SRAMx is not powered. */
+#define SUPC_PWMR_SRAM6ON_ON (0x1u << 22) /**< \brief (SUPC_PWMR) SRAMx is powered. */
+#define SUPC_PWMR_DPRAMON (0x1u << 23) /**< \brief (SUPC_PWMR) Dual-port RAM Power Control */
+#define SUPC_PWMR_DPRAMON_OFF (0x0u << 23) /**< \brief (SUPC_PWMR) USB dual-port RAM is not powered. */
+#define SUPC_PWMR_DPRAMON_ON (0x1u << 23) /**< \brief (SUPC_PWMR) USB dual-port RAM is powered. */
+#define SUPC_PWMR_KEY_Pos 24
+#define SUPC_PWMR_KEY_Msk (0xffu << SUPC_PWMR_KEY_Pos) /**< \brief (SUPC_PWMR) Password Key */
+#define SUPC_PWMR_KEY_PASSWD (0x5Au << 24) /**< \brief (SUPC_PWMR) Writing any other value in this field aborts the write operation.Always reads as 0. */
+
+/*@}*/
+
+
+#endif /* _SAMG55_SUPC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_tc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,328 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_TC_COMPONENT_
+#define _SAMG55_TC_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAMG55_TC Timer Counter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief TcChannel hardware registers */
+typedef struct {
+ __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+ __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+ __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
+ __I uint32_t Reserved1[1];
+ __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */
+ __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */
+ __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */
+ __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */
+ __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */
+ __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+ __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+ __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+ __I uint32_t Reserved2[4];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+ TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+ __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */
+ __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+ __I uint32_t Reserved1[7];
+ __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */
+ __I uint32_t Reserved2[6];
+ __IO uint32_t TC_RPR0; /**< \brief (Tc Offset: 0x100) Receive Pointer Register (pdc = 0) */
+ __IO uint32_t TC_RCR0; /**< \brief (Tc Offset: 0x104) Receive Counter Register (pdc = 0) */
+ __I uint32_t Reserved3[2];
+ __IO uint32_t TC_RNPR0; /**< \brief (Tc Offset: 0x110) Receive Next Pointer Register (pdc = 0) */
+ __IO uint32_t TC_RNCR0; /**< \brief (Tc Offset: 0x114) Receive Next Counter Register (pdc = 0) */
+ __I uint32_t Reserved4[2];
+ __O uint32_t TC_PTCR0; /**< \brief (Tc Offset: 0x120) Transfer Control Register (pdc = 0) */
+ __I uint32_t TC_PTSR0; /**< \brief (Tc Offset: 0x124) Transfer Status Register (pdc = 0) */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal TIMER_CLOCK1 clock signal (from PMC) */
+#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal TIMER_CLOCK2 clock signal (from PMC) */
+#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal TIMER_CLOCK3 clock signal (from PMC) */
+#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal TIMER_CLOCK4 clock signal (from PMC) */
+#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal TIMER_CLOCK5 clock signal (from PMC) */
+#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
+#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
+#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
+#define TC_SR_ENDRX (0x1u << 8) /**< \brief (TC_SR) End of Receiver Transfer */
+#define TC_SR_RXBUFF (0x1u << 9) /**< \brief (TC_SR) Reception Buffer Full */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+#define TC_IER_ENDRX (0x1u << 8) /**< \brief (TC_IER) End of Receiver Transfer */
+#define TC_IER_RXBUFF (0x1u << 9) /**< \brief (TC_IER) Reception Buffer Full */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+#define TC_IDR_ENDRX (0x1u << 8) /**< \brief (TC_IDR) End of Receiver Transfer */
+#define TC_IDR_RXBUFF (0x1u << 9) /**< \brief (TC_IDR) Reception Buffer Full */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+#define TC_IMR_ENDRX (0x1u << 8) /**< \brief (TC_IMR) End of Receiver Transfer */
+#define TC_IMR_RXBUFF (0x1u << 9) /**< \brief (TC_IMR) Reception Buffer Full */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */
+#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */
+#define TC_WPMR_WPKEY_Pos 8
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */
+#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
+/* -------- TC_RPR0 : (TC Offset: 0x100) Receive Pointer Register (pdc = 0) -------- */
+#define TC_RPR0_RXPTR_Pos 0
+#define TC_RPR0_RXPTR_Msk (0xffffffffu << TC_RPR0_RXPTR_Pos) /**< \brief (TC_RPR0) Receive Pointer Register */
+#define TC_RPR0_RXPTR(value) ((TC_RPR0_RXPTR_Msk & ((value) << TC_RPR0_RXPTR_Pos)))
+/* -------- TC_RCR0 : (TC Offset: 0x104) Receive Counter Register (pdc = 0) -------- */
+#define TC_RCR0_RXCTR_Pos 0
+#define TC_RCR0_RXCTR_Msk (0xffffu << TC_RCR0_RXCTR_Pos) /**< \brief (TC_RCR0) Receive Counter Register */
+#define TC_RCR0_RXCTR(value) ((TC_RCR0_RXCTR_Msk & ((value) << TC_RCR0_RXCTR_Pos)))
+/* -------- TC_RNPR0 : (TC Offset: 0x110) Receive Next Pointer Register (pdc = 0) -------- */
+#define TC_RNPR0_RXNPTR_Pos 0
+#define TC_RNPR0_RXNPTR_Msk (0xffffffffu << TC_RNPR0_RXNPTR_Pos) /**< \brief (TC_RNPR0) Receive Next Pointer */
+#define TC_RNPR0_RXNPTR(value) ((TC_RNPR0_RXNPTR_Msk & ((value) << TC_RNPR0_RXNPTR_Pos)))
+/* -------- TC_RNCR0 : (TC Offset: 0x114) Receive Next Counter Register (pdc = 0) -------- */
+#define TC_RNCR0_RXNCTR_Pos 0
+#define TC_RNCR0_RXNCTR_Msk (0xffffu << TC_RNCR0_RXNCTR_Pos) /**< \brief (TC_RNCR0) Receive Next Counter */
+#define TC_RNCR0_RXNCTR(value) ((TC_RNCR0_RXNCTR_Msk & ((value) << TC_RNCR0_RXNCTR_Pos)))
+/* -------- TC_PTCR0 : (TC Offset: 0x120) Transfer Control Register (pdc = 0) -------- */
+#define TC_PTCR0_RXTEN (0x1u << 0) /**< \brief (TC_PTCR0) Receiver Transfer Enable */
+#define TC_PTCR0_RXTDIS (0x1u << 1) /**< \brief (TC_PTCR0) Receiver Transfer Disable */
+#define TC_PTCR0_TXTEN (0x1u << 8) /**< \brief (TC_PTCR0) Transmitter Transfer Enable */
+#define TC_PTCR0_TXTDIS (0x1u << 9) /**< \brief (TC_PTCR0) Transmitter Transfer Disable */
+#define TC_PTCR0_RXCBEN (0x1u << 16) /**< \brief (TC_PTCR0) Receiver Circular Buffer Enable */
+#define TC_PTCR0_RXCBDIS (0x1u << 17) /**< \brief (TC_PTCR0) Receiver Circular Buffer Disable */
+#define TC_PTCR0_TXCBEN (0x1u << 18) /**< \brief (TC_PTCR0) Transmitter Circular Buffer Enable */
+#define TC_PTCR0_TXCBDIS (0x1u << 19) /**< \brief (TC_PTCR0) Transmitter Circular Buffer Disable */
+#define TC_PTCR0_ERRCLR (0x1u << 24) /**< \brief (TC_PTCR0) Transfer Bus Error Clear */
+/* -------- TC_PTSR0 : (TC Offset: 0x124) Transfer Status Register (pdc = 0) -------- */
+#define TC_PTSR0_RXTEN (0x1u << 0) /**< \brief (TC_PTSR0) Receiver Transfer Enable */
+#define TC_PTSR0_TXTEN (0x1u << 8) /**< \brief (TC_PTSR0) Transmitter Transfer Enable */
+#define TC_PTSR0_RXCBEN (0x1u << 16) /**< \brief (TC_PTSR0) Receiver Transfer Enable */
+#define TC_PTSR0_TXCBEN (0x1u << 18) /**< \brief (TC_PTSR0) Transmitter Transfer Enable */
+#define TC_PTSR0_ERR (0x1u << 24) /**< \brief (TC_PTSR0) Transfer Bus Error (clear on read) */
+
+/*@}*/
+
+
+#endif /* _SAMG55_TC_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_twi.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,358 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_TWI_COMPONENT_
+#define _SAMG55_TWI_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Two wire Interface */
+/* ============================================================================= */
+/** \addtogroup SAMG55_TWI Two wire Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Twi hardware registers */
+typedef struct {
+ __O uint32_t TWI_CR; /**< \brief (Twi Offset: 0x000) TWI Control Register */
+ __IO uint32_t TWI_MMR; /**< \brief (Twi Offset: 0x004) TWI Master Mode Register */
+ __IO uint32_t TWI_SMR; /**< \brief (Twi Offset: 0x008) TWI Slave Mode Register */
+ __IO uint32_t TWI_IADR; /**< \brief (Twi Offset: 0x00C) TWI Internal Address Register */
+ __IO uint32_t TWI_CWGR; /**< \brief (Twi Offset: 0x010) TWI Clock Waveform Generator Register */
+ __I uint32_t Reserved1[3];
+ __I uint32_t TWI_SR; /**< \brief (Twi Offset: 0x020) TWI Status Register */
+ __O uint32_t TWI_IER; /**< \brief (Twi Offset: 0x024) TWI Interrupt Enable Register */
+ __O uint32_t TWI_IDR; /**< \brief (Twi Offset: 0x028) TWI Interrupt Disable Register */
+ __I uint32_t TWI_IMR; /**< \brief (Twi Offset: 0x02C) TWI Interrupt Mask Register */
+ __I uint32_t TWI_RHR; /**< \brief (Twi Offset: 0x030) TWI Receive Holding Register */
+ __O uint32_t TWI_THR; /**< \brief (Twi Offset: 0x034) TWI Transmit Holding Register */
+ __IO uint32_t TWI_SMBTR; /**< \brief (Twi Offset: 0x038) TWI SMBus Timing Register */
+ __I uint32_t Reserved2[1];
+ __IO uint32_t TWI_ACR; /**< \brief (Twi Offset: 0x040) TWI Alternative Command Register */
+ __IO uint32_t TWI_FILTR; /**< \brief (Twi Offset: 0x044) TWI Filter Register */
+ __I uint32_t Reserved3[1];
+ __IO uint32_t TWI_SWMR; /**< \brief (Twi Offset: 0x04C) TWI SleepWalking Matching Register */
+ __I uint32_t Reserved4[37];
+ __IO uint32_t TWI_WPMR; /**< \brief (Twi Offset: 0x0E4) TWI Write Protection Mode Register */
+ __I uint32_t TWI_WPSR; /**< \brief (Twi Offset: 0x0E8) TWI Write Protection Status Register */
+ __I uint32_t Reserved5[5];
+ __IO uint32_t TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
+ __IO uint32_t TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */
+ __IO uint32_t TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
+ __IO uint32_t TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
+ __IO uint32_t TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
+ __IO uint32_t TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
+ __IO uint32_t TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
+ __IO uint32_t TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
+ __O uint32_t TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */
+ __I uint32_t TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */
+} Twi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TWI_CR : (TWI Offset: 0x000) TWI Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+#define TWI_CR_HSEN (0x1u << 8) /**< \brief (TWI_CR) TWI High-Speed Mode Enabled */
+#define TWI_CR_HSDIS (0x1u << 9) /**< \brief (TWI_CR) TWI High-Speed Mode Disabled */
+#define TWI_CR_SMBEN (0x1u << 10) /**< \brief (TWI_CR) SMBus Mode Enabled */
+#define TWI_CR_SMBDIS (0x1u << 11) /**< \brief (TWI_CR) SMBus Mode Disabled */
+#define TWI_CR_PECEN (0x1u << 12) /**< \brief (TWI_CR) Packet Error Checking Enable */
+#define TWI_CR_PECDIS (0x1u << 13) /**< \brief (TWI_CR) Packet Error Checking Disable */
+#define TWI_CR_PECRQ (0x1u << 14) /**< \brief (TWI_CR) PEC Request */
+#define TWI_CR_CLEAR (0x1u << 15) /**< \brief (TWI_CR) Bus CLEAR Command */
+#define TWI_CR_ACMEN (0x1u << 16) /**< \brief (TWI_CR) Alternative Command Mode Enable */
+#define TWI_CR_ACMDIS (0x1u << 17) /**< \brief (TWI_CR) Alternative Command Mode Disable */
+#define TWI_CR_THRCLR (0x1u << 24) /**< \brief (TWI_CR) Transmit Holding Register Clear */
+#define TWI_CR_LOCKCLR (0x1u << 26) /**< \brief (TWI_CR) Lock Clear */
+/* -------- TWI_MMR : (TWI Offset: 0x004) TWI Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x008) TWI Slave Mode Register -------- */
+#define TWI_SMR_NACKEN (0x1u << 0) /**< \brief (TWI_SMR) Slave Receiver Data Phase NACK Enable */
+#define TWI_SMR_SMDA (0x1u << 2) /**< \brief (TWI_SMR) SMBus Default Address */
+#define TWI_SMR_SMHH (0x1u << 3) /**< \brief (TWI_SMR) SMBus Host Header */
+#define TWI_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWI_SMR) Clock Wait State Disable */
+#define TWI_SMR_MASK_Pos 8
+#define TWI_SMR_MASK_Msk (0x7fu << TWI_SMR_MASK_Pos) /**< \brief (TWI_SMR) Slave Address Mask */
+#define TWI_SMR_MASK(value) ((TWI_SMR_MASK_Msk & ((value) << TWI_SMR_MASK_Pos)))
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+#define TWI_SMR_SADR1EN (0x1u << 28) /**< \brief (TWI_SMR) Slave Address 1 Enable */
+#define TWI_SMR_SADR2EN (0x1u << 29) /**< \brief (TWI_SMR) Slave Address 2 Enable */
+#define TWI_SMR_SADR3EN (0x1u << 30) /**< \brief (TWI_SMR) Slave Address 3 Enable */
+#define TWI_SMR_DATAMEN (0x1u << 31) /**< \brief (TWI_SMR) Data Matching Enable */
+/* -------- TWI_IADR : (TWI Offset: 0x00C) TWI Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x010) TWI Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+#define TWI_CWGR_BRSRCCLK (0x1u << 20) /**< \brief (TWI_CWGR) Bit Rate Source Clock */
+#define TWI_CWGR_BRSRCCLK_PERIPH_CLK (0x0u << 20) /**< \brief (TWI_CWGR) The peripheral clock is the source clock for the bit rate generation. */
+#define TWI_CWGR_BRSRCCLK_PMC_PCK (0x1u << 20) /**< \brief (TWI_CWGR) PMC PCKx is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock. */
+#define TWI_CWGR_HOLD_Pos 24
+#define TWI_CWGR_HOLD_Msk (0x1fu << TWI_CWGR_HOLD_Pos) /**< \brief (TWI_CWGR) TWD Hold Time Versus TWCK Falling */
+#define TWI_CWGR_HOLD(value) ((TWI_CWGR_HOLD_Msk & ((value) << TWI_CWGR_HOLD_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x020) TWI Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
+#define TWI_SR_UNRE (0x1u << 7) /**< \brief (TWI_SR) Underrun Error (clear on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX Buffer */
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX Buffer */
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
+#define TWI_SR_MCACK (0x1u << 16) /**< \brief (TWI_SR) Master Code Acknowledge */
+#define TWI_SR_TOUT (0x1u << 18) /**< \brief (TWI_SR) Timeout Error */
+#define TWI_SR_PECERR (0x1u << 19) /**< \brief (TWI_SR) PEC Error */
+#define TWI_SR_SMBDAM (0x1u << 20) /**< \brief (TWI_SR) SMBus Default Address Match */
+#define TWI_SR_SMBHHM (0x1u << 21) /**< \brief (TWI_SR) SMBus Host Header Address Match */
+#define TWI_SR_LOCK (0x1u << 23) /**< \brief (TWI_SR) TWI Lock due to Frame Errors */
+#define TWI_SR_SCL (0x1u << 24) /**< \brief (TWI_SR) SCL line value */
+#define TWI_SR_SDA (0x1u << 25) /**< \brief (TWI_SR) SDA line value */
+/* -------- TWI_IER : (TWI Offset: 0x024) TWI Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_UNRE (0x1u << 7) /**< \brief (TWI_IER) Underrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+#define TWI_IER_MCACK (0x1u << 16) /**< \brief (TWI_IER) Master Code Acknowledge Interrupt Enable */
+#define TWI_IER_TOUT (0x1u << 18) /**< \brief (TWI_IER) Timeout Error Interrupt Enable */
+#define TWI_IER_PECERR (0x1u << 19) /**< \brief (TWI_IER) PEC Error Interrupt Enable */
+#define TWI_IER_SMBDAM (0x1u << 20) /**< \brief (TWI_IER) SMBus Default Address Match Interrupt Enable */
+#define TWI_IER_SMBHHM (0x1u << 21) /**< \brief (TWI_IER) SMBus Host Header Address Match Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x028) TWI Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_UNRE (0x1u << 7) /**< \brief (TWI_IDR) Underrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+#define TWI_IDR_MCACK (0x1u << 16) /**< \brief (TWI_IDR) Master Code Acknowledge Interrupt Disable */
+#define TWI_IDR_TOUT (0x1u << 18) /**< \brief (TWI_IDR) Timeout Error Interrupt Disable */
+#define TWI_IDR_PECERR (0x1u << 19) /**< \brief (TWI_IDR) PEC Error Interrupt Disable */
+#define TWI_IDR_SMBDAM (0x1u << 20) /**< \brief (TWI_IDR) SMBus Default Address Match Interrupt Disable */
+#define TWI_IDR_SMBHHM (0x1u << 21) /**< \brief (TWI_IDR) SMBus Host Header Address Match Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x02C) TWI Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_UNRE (0x1u << 7) /**< \brief (TWI_IMR) Underrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+#define TWI_IMR_MCACK (0x1u << 16) /**< \brief (TWI_IMR) Master Code Acknowledge Interrupt Mask */
+#define TWI_IMR_TOUT (0x1u << 18) /**< \brief (TWI_IMR) Timeout Error Interrupt Mask */
+#define TWI_IMR_PECERR (0x1u << 19) /**< \brief (TWI_IMR) PEC Error Interrupt Mask */
+#define TWI_IMR_SMBDAM (0x1u << 20) /**< \brief (TWI_IMR) SMBus Default Address Match Interrupt Mask */
+#define TWI_IMR_SMBHHM (0x1u << 21) /**< \brief (TWI_IMR) SMBus Host Header Address Match Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x030) TWI Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+/* -------- TWI_THR : (TWI Offset: 0x034) TWI Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+/* -------- TWI_SMBTR : (TWI Offset: 0x038) TWI SMBus Timing Register -------- */
+#define TWI_SMBTR_PRESC_Pos 0
+#define TWI_SMBTR_PRESC_Msk (0xfu << TWI_SMBTR_PRESC_Pos) /**< \brief (TWI_SMBTR) SMBus Clock Prescaler */
+#define TWI_SMBTR_PRESC(value) ((TWI_SMBTR_PRESC_Msk & ((value) << TWI_SMBTR_PRESC_Pos)))
+#define TWI_SMBTR_TLOWS_Pos 8
+#define TWI_SMBTR_TLOWS_Msk (0xffu << TWI_SMBTR_TLOWS_Pos) /**< \brief (TWI_SMBTR) Slave Clock Stretch Maximum Cycles */
+#define TWI_SMBTR_TLOWS(value) ((TWI_SMBTR_TLOWS_Msk & ((value) << TWI_SMBTR_TLOWS_Pos)))
+#define TWI_SMBTR_TLOWM_Pos 16
+#define TWI_SMBTR_TLOWM_Msk (0xffu << TWI_SMBTR_TLOWM_Pos) /**< \brief (TWI_SMBTR) Master Clock Stretch Maximum Cycles */
+#define TWI_SMBTR_TLOWM(value) ((TWI_SMBTR_TLOWM_Msk & ((value) << TWI_SMBTR_TLOWM_Pos)))
+#define TWI_SMBTR_THMAX_Pos 24
+#define TWI_SMBTR_THMAX_Msk (0xffu << TWI_SMBTR_THMAX_Pos) /**< \brief (TWI_SMBTR) Clock High Maximum Cycles */
+#define TWI_SMBTR_THMAX(value) ((TWI_SMBTR_THMAX_Msk & ((value) << TWI_SMBTR_THMAX_Pos)))
+/* -------- TWI_ACR : (TWI Offset: 0x040) TWI Alternative Command Register -------- */
+#define TWI_ACR_DATAL_Pos 0
+#define TWI_ACR_DATAL_Msk (0xffu << TWI_ACR_DATAL_Pos) /**< \brief (TWI_ACR) Data Length */
+#define TWI_ACR_DATAL(value) ((TWI_ACR_DATAL_Msk & ((value) << TWI_ACR_DATAL_Pos)))
+#define TWI_ACR_DIR (0x1u << 8) /**< \brief (TWI_ACR) Transfer Direction */
+#define TWI_ACR_PEC (0x1u << 9) /**< \brief (TWI_ACR) PEC Request (SMBus Mode only) */
+#define TWI_ACR_NDATAL_Pos 16
+#define TWI_ACR_NDATAL_Msk (0xffu << TWI_ACR_NDATAL_Pos) /**< \brief (TWI_ACR) Next Data Length */
+#define TWI_ACR_NDATAL(value) ((TWI_ACR_NDATAL_Msk & ((value) << TWI_ACR_NDATAL_Pos)))
+#define TWI_ACR_NDIR (0x1u << 24) /**< \brief (TWI_ACR) Next Transfer Direction */
+#define TWI_ACR_NPEC (0x1u << 25) /**< \brief (TWI_ACR) Next PEC Request (SMBus Mode only) */
+/* -------- TWI_FILTR : (TWI Offset: 0x044) TWI Filter Register -------- */
+#define TWI_FILTR_FILT (0x1u << 0) /**< \brief (TWI_FILTR) RX Digital Filter */
+#define TWI_FILTR_PADFEN (0x1u << 1) /**< \brief (TWI_FILTR) PAD Filter Enable */
+#define TWI_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWI_FILTR) PAD Filter Config */
+#define TWI_FILTR_THRES_Pos 8
+#define TWI_FILTR_THRES_Msk (0x7u << TWI_FILTR_THRES_Pos) /**< \brief (TWI_FILTR) Digital Filter Threshold */
+#define TWI_FILTR_THRES(value) ((TWI_FILTR_THRES_Msk & ((value) << TWI_FILTR_THRES_Pos)))
+/* -------- TWI_SWMR : (TWI Offset: 0x04C) TWI SleepWalking Matching Register -------- */
+#define TWI_SWMR_SADR1_Pos 0
+#define TWI_SWMR_SADR1_Msk (0x7fu << TWI_SWMR_SADR1_Pos) /**< \brief (TWI_SWMR) Slave Address 1 */
+#define TWI_SWMR_SADR1(value) ((TWI_SWMR_SADR1_Msk & ((value) << TWI_SWMR_SADR1_Pos)))
+#define TWI_SWMR_SADR2_Pos 8
+#define TWI_SWMR_SADR2_Msk (0x7fu << TWI_SWMR_SADR2_Pos) /**< \brief (TWI_SWMR) Slave Address 2 */
+#define TWI_SWMR_SADR2(value) ((TWI_SWMR_SADR2_Msk & ((value) << TWI_SWMR_SADR2_Pos)))
+#define TWI_SWMR_SADR3_Pos 16
+#define TWI_SWMR_SADR3_Msk (0x7fu << TWI_SWMR_SADR3_Pos) /**< \brief (TWI_SWMR) Slave Address 3 */
+#define TWI_SWMR_SADR3(value) ((TWI_SWMR_SADR3_Msk & ((value) << TWI_SWMR_SADR3_Pos)))
+#define TWI_SWMR_DATAM_Pos 24
+#define TWI_SWMR_DATAM_Msk (0xffu << TWI_SWMR_DATAM_Pos) /**< \brief (TWI_SWMR) Data Match */
+#define TWI_SWMR_DATAM(value) ((TWI_SWMR_DATAM_Msk & ((value) << TWI_SWMR_DATAM_Pos)))
+/* -------- TWI_WPMR : (TWI Offset: 0x0E4) TWI Write Protection Mode Register -------- */
+#define TWI_WPMR_WPEN (0x1u << 0) /**< \brief (TWI_WPMR) Write Protection Enable */
+#define TWI_WPMR_WPKEY_Pos 8
+#define TWI_WPMR_WPKEY_Msk (0xffffffu << TWI_WPMR_WPKEY_Pos) /**< \brief (TWI_WPMR) Write Protection Key */
+#define TWI_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */
+/* -------- TWI_WPSR : (TWI Offset: 0x0E8) TWI Write Protection Status Register -------- */
+#define TWI_WPSR_WPVS (0x1u << 0) /**< \brief (TWI_WPSR) Write Protect Violation Status */
+#define TWI_WPSR_WPVSRC_Pos 8
+#define TWI_WPSR_WPVSRC_Msk (0xffffffu << TWI_WPSR_WPVSRC_Pos) /**< \brief (TWI_WPSR) Write Protection Violation Source */
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
+#define TWI_RPR_RXPTR_Pos 0
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
+#define TWI_RCR_RXCTR_Pos 0
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
+#define TWI_TPR_TXPTR_Pos 0
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
+#define TWI_TCR_TXCTR_Pos 0
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
+#define TWI_RNPR_RXNPTR_Pos 0
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
+#define TWI_RNCR_RXNCTR_Pos 0
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define TWI_TNPR_TXNPTR_Pos 0
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define TWI_TNCR_TXNCTR_Pos 0
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
+#define TWI_PTCR_RXCBEN (0x1u << 16) /**< \brief (TWI_PTCR) Receiver Circular Buffer Enable */
+#define TWI_PTCR_RXCBDIS (0x1u << 17) /**< \brief (TWI_PTCR) Receiver Circular Buffer Disable */
+#define TWI_PTCR_TXCBEN (0x1u << 18) /**< \brief (TWI_PTCR) Transmitter Circular Buffer Enable */
+#define TWI_PTCR_TXCBDIS (0x1u << 19) /**< \brief (TWI_PTCR) Transmitter Circular Buffer Disable */
+#define TWI_PTCR_ERRCLR (0x1u << 24) /**< \brief (TWI_PTCR) Transfer Bus Error Clear */
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+#define TWI_PTSR_RXCBEN (0x1u << 16) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXCBEN (0x1u << 18) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+#define TWI_PTSR_ERR (0x1u << 24) /**< \brief (TWI_PTSR) Transfer Bus Error (clear on read) */
+
+/*@}*/
+
+
+#endif /* _SAMG55_TWI_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_udp.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,191 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_UDP_COMPONENT_
+#define _SAMG55_UDP_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR USB Device Port */
+/* ============================================================================= */
+/** \addtogroup SAMG55_UDP USB Device Port */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Udp hardware registers */
+typedef struct {
+ __I uint32_t UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */
+ __IO uint32_t UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */
+ __IO uint32_t UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */
+ __I uint32_t Reserved1[1];
+ __O uint32_t UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */
+ __O uint32_t UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */
+ __I uint32_t UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */
+ __I uint32_t UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */
+ __O uint32_t UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */
+ __I uint32_t Reserved2[1];
+ __IO uint32_t UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */
+ __I uint32_t Reserved3[1];
+ __IO uint32_t UDP_CSR[6]; /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */
+ __I uint32_t Reserved4[2];
+ __IO uint32_t UDP_FDR[6]; /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */
+ __I uint32_t Reserved5[3];
+ __IO uint32_t UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */
+} Udp;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */
+#define UDP_FRM_NUM_FRM_NUM_Pos 0
+#define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */
+#define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */
+#define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */
+/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */
+#define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */
+#define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */
+#define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */
+#define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT) */
+#define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */
+/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */
+#define UDP_FADDR_FADD_Pos 0
+#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */
+#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos)))
+#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */
+/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */
+#define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */
+#define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */
+#define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */
+#define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */
+#define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */
+#define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */
+#define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */
+#define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */
+#define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER) */
+#define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */
+#define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */
+/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */
+#define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */
+#define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */
+#define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */
+#define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */
+#define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */
+#define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */
+#define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */
+#define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */
+#define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR) */
+#define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */
+#define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */
+/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */
+#define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */
+#define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */
+#define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */
+#define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */
+#define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */
+#define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */
+#define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */
+#define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */
+#define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR) */
+#define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */
+#define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */
+#define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */
+/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */
+#define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */
+#define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */
+#define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */
+#define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */
+#define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */
+#define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */
+#define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */
+#define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
+#define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR) */
+#define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */
+#define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */
+#define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
+/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */
+#define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */
+#define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */
+#define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR) */
+#define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */
+#define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */
+#define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */
+/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */
+#define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */
+#define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */
+#define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */
+#define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */
+#define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */
+#define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */
+/* -------- UDP_CSR[6] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */
+#define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[6]) Generates an IN Packet with Data Previously Written in the DPR */
+#define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[6]) Receive Data Bank 0 */
+#define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[6]) Received Setup */
+#define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[6]) Stall Sent */
+#define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[6]) Transmit Packet Ready */
+#define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[6]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */
+#define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[6]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */
+#define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[6]) Transfer Direction (only available for control endpoints) */
+#define UDP_CSR_EPTYPE_Pos 8
+#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[6]) Endpoint Type */
+#define UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[6]) Control */
+#define UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[6]) Isochronous OUT */
+#define UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[6]) Bulk OUT */
+#define UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[6]) Interrupt OUT */
+#define UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[6]) Isochronous IN */
+#define UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[6]) Bulk IN */
+#define UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[6]) Interrupt IN */
+#define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[6]) Data Toggle */
+#define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[6]) Endpoint Enable Disable */
+#define UDP_CSR_RXBYTECNT_Pos 16
+#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[6]) Number of Bytes Available in the FIFO */
+#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos)))
+#define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[6]) A CRC error has been detected in an isochronous transfer */
+/* -------- UDP_FDR[6] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */
+#define UDP_FDR_FIFO_DATA_Pos 0
+#define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[6]) FIFO Data Value */
+#define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos)))
+/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */
+#define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */
+#define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pull-up On */
+
+/*@}*/
+
+
+#endif /* _SAMG55_UDP_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_uhp.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,253 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_UHP_COMPONENT_
+#define _SAMG55_UHP_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR USB Host Port */
+/* ============================================================================= */
+/** \addtogroup SAMG55_UHP USB Host Port */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Uhp hardware registers */
+typedef struct {
+ __I uint32_t UHP_HCREVISION; /**< \brief (Uhp Offset: 0x00) OHCI Revision Number Register */
+ __IO uint32_t UHP_HCCONTROL; /**< \brief (Uhp Offset: 0x04) HC Operating Mode Register */
+ __IO uint32_t UHP_HCCOMMANDSTATUS; /**< \brief (Uhp Offset: 0x08) HC Command and Status Register */
+ __IO uint32_t UHP_HCINTERRUPTSTATUS; /**< \brief (Uhp Offset: 0x0C) HC Interrupt and Status Register */
+ __IO uint32_t UHP_HCINTERRUPTENABLE; /**< \brief (Uhp Offset: 0x10) HC Interrupt Enable Register */
+ __IO uint32_t UHP_HCINTERRUPTDISABLE; /**< \brief (Uhp Offset: 0x14) HC Interrupt Disable Register */
+ __IO uint32_t UHP_HCHCCA; /**< \brief (Uhp Offset: 0x18) HC HCCA Address Register */
+ __I uint32_t UHP_HCPERIODCURRENTED; /**< \brief (Uhp Offset: 0x1C) HC Current Periodic Register */
+ __IO uint32_t UHP_HCCONTROLHEADED; /**< \brief (Uhp Offset: 0x20) HC Head Control Register */
+ __IO uint32_t UHP_HCCONTROLCURRENTED; /**< \brief (Uhp Offset: 0x24) HC Current Control Register */
+ __IO uint32_t UHP_HCBULKHEADED; /**< \brief (Uhp Offset: 0x28) HC Head Bulk Register */
+ __IO uint32_t UHP_HCBULKCURRENTED; /**< \brief (Uhp Offset: 0x2C) HC Current Bulk Register */
+ __I uint32_t UHP_HCDONEHEAD; /**< \brief (Uhp Offset: 0x30) HC Head Done Register */
+ __IO uint32_t UHP_HCFMINTERVAL; /**< \brief (Uhp Offset: 0x34) HC Frame Interval Register */
+ __I uint32_t UHP_HCFMREMAINING; /**< \brief (Uhp Offset: 0x38) HC Frame Remaining Register */
+ __I uint32_t UHP_HCFMNUMBER; /**< \brief (Uhp Offset: 0x3C) HC Frame Number Register */
+ __IO uint32_t UHP_HCPERIODICSTART; /**< \brief (Uhp Offset: 0x40) HC Periodic Start Register */
+ __IO uint32_t UHP_HCLSTHRESHOLD; /**< \brief (Uhp Offset: 0x44) HC Low-Speed Threshold Register */
+ __IO uint32_t UHP_HCRHDESCRIPTORA; /**< \brief (Uhp Offset: 0x48) HC Root Hub A Register */
+ __IO uint32_t UHP_HCRHDESCRIPTORB; /**< \brief (Uhp Offset: 0x4C) HC Root Hub B Register */
+ __IO uint32_t UHP_HCRHSTATUS; /**< \brief (Uhp Offset: 0x50) HC Root Hub Status Register */
+ __IO uint32_t UHP_HCRHPORTSTATUS[2]; /**< \brief (Uhp Offset: 0x54) HC Port 1 Status and Control Register */
+} Uhp;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UHP_HCREVISION : (UHP Offset: 0x00) OHCI Revision Number Register -------- */
+#define UHP_HCREVISION_REV_Pos 0
+#define UHP_HCREVISION_REV_Msk (0xffu << UHP_HCREVISION_REV_Pos) /**< \brief (UHP_HCREVISION) OHCI revision number */
+/* -------- UHP_HCCONTROL : (UHP Offset: 0x04) HC Operating Mode Register -------- */
+#define UHP_HCCONTROL_CBSR_Pos 0
+#define UHP_HCCONTROL_CBSR_Msk (0x3u << UHP_HCCONTROL_CBSR_Pos) /**< \brief (UHP_HCCONTROL) Control/bulk service ratio */
+#define UHP_HCCONTROL_CBSR(value) ((UHP_HCCONTROL_CBSR_Msk & ((value) << UHP_HCCONTROL_CBSR_Pos)))
+#define UHP_HCCONTROL_PLE (0x1u << 2) /**< \brief (UHP_HCCONTROL) Periodic list enable */
+#define UHP_HCCONTROL_IE (0x1u << 3) /**< \brief (UHP_HCCONTROL) Isochronous enable */
+#define UHP_HCCONTROL_CLE (0x1u << 4) /**< \brief (UHP_HCCONTROL) Control list enable */
+#define UHP_HCCONTROL_BLE (0x1u << 5) /**< \brief (UHP_HCCONTROL) Bulk list enable */
+#define UHP_HCCONTROL_HCFS_Pos 6
+#define UHP_HCCONTROL_HCFS_Msk (0x3u << UHP_HCCONTROL_HCFS_Pos) /**< \brief (UHP_HCCONTROL) Host controller functional state */
+#define UHP_HCCONTROL_HCFS(value) ((UHP_HCCONTROL_HCFS_Msk & ((value) << UHP_HCCONTROL_HCFS_Pos)))
+#define UHP_HCCONTROL_IR (0x1u << 8) /**< \brief (UHP_HCCONTROL) Interrupt routing */
+#define UHP_HCCONTROL_RWC (0x1u << 9) /**< \brief (UHP_HCCONTROL) Remote wake-up connected */
+#define UHP_HCCONTROL_RWE (0x1u << 10) /**< \brief (UHP_HCCONTROL) Remote wake-up enable */
+/* -------- UHP_HCCOMMANDSTATUS : (UHP Offset: 0x08) HC Command and Status Register -------- */
+#define UHP_HCCOMMANDSTATUS_HCR (0x1u << 0) /**< \brief (UHP_HCCOMMANDSTATUS) Host controller reset (read/write) */
+#define UHP_HCCOMMANDSTATUS_CLF (0x1u << 1) /**< \brief (UHP_HCCOMMANDSTATUS) Control list filled (read/write) */
+#define UHP_HCCOMMANDSTATUS_BLF (0x1u << 2) /**< \brief (UHP_HCCOMMANDSTATUS) Bulk list filled (read/write) */
+#define UHP_HCCOMMANDSTATUS_OCR (0x1u << 3) /**< \brief (UHP_HCCOMMANDSTATUS) Ownership change request (read/write) */
+#define UHP_HCCOMMANDSTATUS_SOC_Pos 16
+#define UHP_HCCOMMANDSTATUS_SOC_Msk (0x3u << UHP_HCCOMMANDSTATUS_SOC_Pos) /**< \brief (UHP_HCCOMMANDSTATUS) Scheduling overrun count (read-only) */
+#define UHP_HCCOMMANDSTATUS_SOC(value) ((UHP_HCCOMMANDSTATUS_SOC_Msk & ((value) << UHP_HCCOMMANDSTATUS_SOC_Pos)))
+/* -------- UHP_HCINTERRUPTSTATUS : (UHP Offset: 0x0C) HC Interrupt and Status Register -------- */
+#define UHP_HCINTERRUPTSTATUS_SO (0x1u << 0) /**< \brief (UHP_HCINTERRUPTSTATUS) Scheduling overrun (read/write, write '1' to clear) */
+#define UHP_HCINTERRUPTSTATUS_WDH (0x1u << 1) /**< \brief (UHP_HCINTERRUPTSTATUS) Write done head (read/write, write '1' to clear) */
+#define UHP_HCINTERRUPTSTATUS_SF (0x1u << 2) /**< \brief (UHP_HCINTERRUPTSTATUS) Start of frame (read/write, write '1' to clear) */
+#define UHP_HCINTERRUPTSTATUS_RD (0x1u << 3) /**< \brief (UHP_HCINTERRUPTSTATUS) Resume detected (read/write, write '1' to clear) */
+#define UHP_HCINTERRUPTSTATUS_UE (0x1u << 4) /**< \brief (UHP_HCINTERRUPTSTATUS) Unrecoverable error (read/write, write '1' to clear) */
+#define UHP_HCINTERRUPTSTATUS_FNO (0x1u << 5) /**< \brief (UHP_HCINTERRUPTSTATUS) Frame number overflow (read/write, write '1' to clear) */
+#define UHP_HCINTERRUPTSTATUS_RHSC (0x1u << 6) /**< \brief (UHP_HCINTERRUPTSTATUS) Root hub status change (read/write, write '1' to clear) */
+#define UHP_HCINTERRUPTSTATUS_OC (0x1u << 30) /**< \brief (UHP_HCINTERRUPTSTATUS) Ownership change (read-only) */
+/* -------- UHP_HCINTERRUPTENABLE : (UHP Offset: 0x10) HC Interrupt Enable Register -------- */
+#define UHP_HCINTERRUPTENABLE_SO (0x1u << 0) /**< \brief (UHP_HCINTERRUPTENABLE) Scheduling overrun (read/write, write '1' to set) */
+#define UHP_HCINTERRUPTENABLE_WDH (0x1u << 1) /**< \brief (UHP_HCINTERRUPTENABLE) Write done head (read/write, write '1' to set) */
+#define UHP_HCINTERRUPTENABLE_SF (0x1u << 2) /**< \brief (UHP_HCINTERRUPTENABLE) Start of frame (read/write, write '1' to set) */
+#define UHP_HCINTERRUPTENABLE_RD (0x1u << 3) /**< \brief (UHP_HCINTERRUPTENABLE) Resume detected (read/write, write '1' to set) */
+#define UHP_HCINTERRUPTENABLE_UE (0x1u << 4) /**< \brief (UHP_HCINTERRUPTENABLE) Unrecoverable error (read/write, write '1' to set) */
+#define UHP_HCINTERRUPTENABLE_FNO (0x1u << 5) /**< \brief (UHP_HCINTERRUPTENABLE) Frame number overflow (read/write, write '1' to set) */
+#define UHP_HCINTERRUPTENABLE_RHSC (0x1u << 6) /**< \brief (UHP_HCINTERRUPTENABLE) Root hub status change (read/write, write '1' to set) */
+#define UHP_HCINTERRUPTENABLE_OC (0x1u << 30) /**< \brief (UHP_HCINTERRUPTENABLE) Ownership change (read-only) */
+#define UHP_HCINTERRUPTENABLE_MIE (0x1u << 31) /**< \brief (UHP_HCINTERRUPTENABLE) Master interrupt enable (read/write, write '1' to set) */
+/* -------- UHP_HCINTERRUPTDISABLE : (UHP Offset: 0x14) HC Interrupt Disable Register -------- */
+#define UHP_HCINTERRUPTDISABLE_SO (0x1u << 0) /**< \brief (UHP_HCINTERRUPTDISABLE) Scheduling overrun (read/write) */
+#define UHP_HCINTERRUPTDISABLE_WDH (0x1u << 1) /**< \brief (UHP_HCINTERRUPTDISABLE) Write done head (read/write) */
+#define UHP_HCINTERRUPTDISABLE_SF (0x1u << 2) /**< \brief (UHP_HCINTERRUPTDISABLE) Start of frame (read/write) */
+#define UHP_HCINTERRUPTDISABLE_RD (0x1u << 3) /**< \brief (UHP_HCINTERRUPTDISABLE) Resume detected (read/write) */
+#define UHP_HCINTERRUPTDISABLE_UE (0x1u << 4) /**< \brief (UHP_HCINTERRUPTDISABLE) Unrecoverable error (read/write) */
+#define UHP_HCINTERRUPTDISABLE_FNO (0x1u << 5) /**< \brief (UHP_HCINTERRUPTDISABLE) Frame number overflow (read/write) */
+#define UHP_HCINTERRUPTDISABLE_RHSC (0x1u << 6) /**< \brief (UHP_HCINTERRUPTDISABLE) Root hub status change (read/write) */
+#define UHP_HCINTERRUPTDISABLE_OC (0x1u << 30) /**< \brief (UHP_HCINTERRUPTDISABLE) Ownership change (read-only) */
+#define UHP_HCINTERRUPTDISABLE_MIE (0x1u << 31) /**< \brief (UHP_HCINTERRUPTDISABLE) Master interrupt enable (read/write) */
+/* -------- UHP_HCHCCA : (UHP Offset: 0x18) HC HCCA Address Register -------- */
+#define UHP_HCHCCA_HCCA_Pos 8
+#define UHP_HCHCCA_HCCA_Msk (0xffffffu << UHP_HCHCCA_HCCA_Pos) /**< \brief (UHP_HCHCCA) Physical address of the beginning of the HCCA */
+#define UHP_HCHCCA_HCCA(value) ((UHP_HCHCCA_HCCA_Msk & ((value) << UHP_HCHCCA_HCCA_Pos)))
+/* -------- UHP_HCPERIODCURRENTED : (UHP Offset: 0x1C) HC Current Periodic Register -------- */
+#define UHP_HCPERIODCURRENTED_PCED_Pos 4
+#define UHP_HCPERIODCURRENTED_PCED_Msk (0xfffffffu << UHP_HCPERIODCURRENTED_PCED_Pos) /**< \brief (UHP_HCPERIODCURRENTED) Physical address of the current ED on the periodic ED list */
+/* -------- UHP_HCCONTROLHEADED : (UHP Offset: 0x20) HC Head Control Register -------- */
+#define UHP_HCCONTROLHEADED_CHED_Pos 4
+#define UHP_HCCONTROLHEADED_CHED_Msk (0xfffffffu << UHP_HCCONTROLHEADED_CHED_Pos) /**< \brief (UHP_HCCONTROLHEADED) Physical address of the head ED on the control ED list */
+#define UHP_HCCONTROLHEADED_CHED(value) ((UHP_HCCONTROLHEADED_CHED_Msk & ((value) << UHP_HCCONTROLHEADED_CHED_Pos)))
+/* -------- UHP_HCCONTROLCURRENTED : (UHP Offset: 0x24) HC Current Control Register -------- */
+#define UHP_HCCONTROLCURRENTED_CCED_Pos 4
+#define UHP_HCCONTROLCURRENTED_CCED_Msk (0xfffffffu << UHP_HCCONTROLCURRENTED_CCED_Pos) /**< \brief (UHP_HCCONTROLCURRENTED) Physical address of the current ED on the control ED list */
+#define UHP_HCCONTROLCURRENTED_CCED(value) ((UHP_HCCONTROLCURRENTED_CCED_Msk & ((value) << UHP_HCCONTROLCURRENTED_CCED_Pos)))
+/* -------- UHP_HCBULKHEADED : (UHP Offset: 0x28) HC Head Bulk Register -------- */
+#define UHP_HCBULKHEADED_BHED_Pos 4
+#define UHP_HCBULKHEADED_BHED_Msk (0xfffffffu << UHP_HCBULKHEADED_BHED_Pos) /**< \brief (UHP_HCBULKHEADED) Physical address of the head ED on the bulk ED list */
+#define UHP_HCBULKHEADED_BHED(value) ((UHP_HCBULKHEADED_BHED_Msk & ((value) << UHP_HCBULKHEADED_BHED_Pos)))
+/* -------- UHP_HCBULKCURRENTED : (UHP Offset: 0x2C) HC Current Bulk Register -------- */
+#define UHP_HCBULKCURRENTED_BCED_Pos 4
+#define UHP_HCBULKCURRENTED_BCED_Msk (0xfffffffu << UHP_HCBULKCURRENTED_BCED_Pos) /**< \brief (UHP_HCBULKCURRENTED) Physical address of the current ED on the bulk ED list */
+#define UHP_HCBULKCURRENTED_BCED(value) ((UHP_HCBULKCURRENTED_BCED_Msk & ((value) << UHP_HCBULKCURRENTED_BCED_Pos)))
+/* -------- UHP_HCDONEHEAD : (UHP Offset: 0x30) HC Head Done Register -------- */
+#define UHP_HCDONEHEAD_DH_Pos 4
+#define UHP_HCDONEHEAD_DH_Msk (0xfffffffu << UHP_HCDONEHEAD_DH_Pos) /**< \brief (UHP_HCDONEHEAD) Physical address of the last TD that has added to the done queue */
+/* -------- UHP_HCFMINTERVAL : (UHP Offset: 0x34) HC Frame Interval Register -------- */
+#define UHP_HCFMINTERVAL_FRAMEINTERVAL_Pos 0
+#define UHP_HCFMINTERVAL_FRAMEINTERVAL_Msk (0x3fffu << UHP_HCFMINTERVAL_FRAMEINTERVAL_Pos) /**< \brief (UHP_HCFMINTERVAL) Frame interval */
+#define UHP_HCFMINTERVAL_FRAMEINTERVAL(value) ((UHP_HCFMINTERVAL_FRAMEINTERVAL_Msk & ((value) << UHP_HCFMINTERVAL_FRAMEINTERVAL_Pos)))
+#define UHP_HCFMINTERVAL_FSMPS_Pos 16
+#define UHP_HCFMINTERVAL_FSMPS_Msk (0x7fffu << UHP_HCFMINTERVAL_FSMPS_Pos) /**< \brief (UHP_HCFMINTERVAL) Largest data packet */
+#define UHP_HCFMINTERVAL_FSMPS(value) ((UHP_HCFMINTERVAL_FSMPS_Msk & ((value) << UHP_HCFMINTERVAL_FSMPS_Pos)))
+#define UHP_HCFMINTERVAL_FIT (0x1u << 31) /**< \brief (UHP_HCFMINTERVAL) Frame interval toggle */
+/* -------- UHP_HCFMREMAINING : (UHP Offset: 0x38) HC Frame Remaining Register -------- */
+#define UHP_HCFMREMAINING_FR_Pos 0
+#define UHP_HCFMREMAINING_FR_Msk (0x3fffu << UHP_HCFMREMAINING_FR_Pos) /**< \brief (UHP_HCFMREMAINING) Frame remaining */
+#define UHP_HCFMREMAINING_FRT (0x1u << 31) /**< \brief (UHP_HCFMREMAINING) Frame remaining toggle */
+/* -------- UHP_HCFMNUMBER : (UHP Offset: 0x3C) HC Frame Number Register -------- */
+#define UHP_HCFMNUMBER_FN_Pos 0
+#define UHP_HCFMNUMBER_FN_Msk (0xffffu << UHP_HCFMNUMBER_FN_Pos) /**< \brief (UHP_HCFMNUMBER) Frame number */
+/* -------- UHP_HCPERIODICSTART : (UHP Offset: 0x40) HC Periodic Start Register -------- */
+#define UHP_HCPERIODICSTART_PS_Pos 0
+#define UHP_HCPERIODICSTART_PS_Msk (0x3fffu << UHP_HCPERIODICSTART_PS_Pos) /**< \brief (UHP_HCPERIODICSTART) Periodic start */
+#define UHP_HCPERIODICSTART_PS(value) ((UHP_HCPERIODICSTART_PS_Msk & ((value) << UHP_HCPERIODICSTART_PS_Pos)))
+/* -------- UHP_HCLSTHRESHOLD : (UHP Offset: 0x44) HC Low-Speed Threshold Register -------- */
+#define UHP_HCLSTHRESHOLD_LST_Pos 0
+#define UHP_HCLSTHRESHOLD_LST_Msk (0x3fffu << UHP_HCLSTHRESHOLD_LST_Pos) /**< \brief (UHP_HCLSTHRESHOLD) Low-speed threshold */
+#define UHP_HCLSTHRESHOLD_LST(value) ((UHP_HCLSTHRESHOLD_LST_Msk & ((value) << UHP_HCLSTHRESHOLD_LST_Pos)))
+/* -------- UHP_HCRHDESCRIPTORA : (UHP Offset: 0x48) HC Root Hub A Register -------- */
+#define UHP_HCRHDESCRIPTORA_NDP_Pos 0
+#define UHP_HCRHDESCRIPTORA_NDP_Msk (0xffu << UHP_HCRHDESCRIPTORA_NDP_Pos) /**< \brief (UHP_HCRHDESCRIPTORA) Number of downstream ports (read-only) */
+#define UHP_HCRHDESCRIPTORA_NDP(value) ((UHP_HCRHDESCRIPTORA_NDP_Msk & ((value) << UHP_HCRHDESCRIPTORA_NDP_Pos)))
+#define UHP_HCRHDESCRIPTORA_PSM (0x1u << 8) /**< \brief (UHP_HCRHDESCRIPTORA) Power switching mode (read/write) */
+#define UHP_HCRHDESCRIPTORA_NPS (0x1u << 9) /**< \brief (UHP_HCRHDESCRIPTORA) No power switching (read/write) */
+#define UHP_HCRHDESCRIPTORA_DT (0x1u << 10) /**< \brief (UHP_HCRHDESCRIPTORA) Device type (read-only) */
+#define UHP_HCRHDESCRIPTORA_OCPM (0x1u << 11) /**< \brief (UHP_HCRHDESCRIPTORA) Overcurrent protection mode (read/write) */
+#define UHP_HCRHDESCRIPTORA_NOCP (0x1u << 12) /**< \brief (UHP_HCRHDESCRIPTORA) No overcurrent protection (read/write) */
+#define UHP_HCRHDESCRIPTORA_POTPG_Pos 24
+#define UHP_HCRHDESCRIPTORA_POTPG_Msk (0xffu << UHP_HCRHDESCRIPTORA_POTPG_Pos) /**< \brief (UHP_HCRHDESCRIPTORA) Power-on to power-good time (read/write) */
+#define UHP_HCRHDESCRIPTORA_POTPG(value) ((UHP_HCRHDESCRIPTORA_POTPG_Msk & ((value) << UHP_HCRHDESCRIPTORA_POTPG_Pos)))
+/* -------- UHP_HCRHDESCRIPTORB : (UHP Offset: 0x4C) HC Root Hub B Register -------- */
+#define UHP_HCRHDESCRIPTORB_DR0 (0x1u << 0) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_DR1 (0x1u << 1) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_DR2 (0x1u << 2) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_DR3 (0x1u << 3) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_DR4 (0x1u << 4) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_DR5 (0x1u << 5) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_DR6 (0x1u << 6) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_DR7 (0x1u << 7) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_DR8 (0x1u << 8) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_DR9 (0x1u << 9) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_DR10 (0x1u << 10) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_DR11 (0x1u << 11) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_DR12 (0x1u << 12) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_DR13 (0x1u << 13) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_DR14 (0x1u << 14) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_DR15 (0x1u << 15) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM0 (0x1u << 16) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM1 (0x1u << 17) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM2 (0x1u << 18) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM3 (0x1u << 19) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM4 (0x1u << 20) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM5 (0x1u << 21) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM6 (0x1u << 22) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM7 (0x1u << 23) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM8 (0x1u << 24) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM9 (0x1u << 25) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM10 (0x1u << 26) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM11 (0x1u << 27) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM12 (0x1u << 28) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM13 (0x1u << 29) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM14 (0x1u << 30) /**< \brief (UHP_HCRHDESCRIPTORB) */
+#define UHP_HCRHDESCRIPTORB_PPCM15 (0x1u << 31) /**< \brief (UHP_HCRHDESCRIPTORB) */
+/* -------- UHP_HCRHSTATUS : (UHP Offset: 0x50) HC Root Hub Status Register -------- */
+#define UHP_HCRHSTATUS_LPS (0x1u << 0) /**< \brief (UHP_HCRHSTATUS) Local power status (read/write) */
+#define UHP_HCRHSTATUS_OCI (0x1u << 1) /**< \brief (UHP_HCRHSTATUS) Overcurrent indicator (read-only) */
+#define UHP_HCRHSTATUS_DRWE (0x1u << 15) /**< \brief (UHP_HCRHSTATUS) Device remote wake-up enable (read/write) */
+#define UHP_HCRHSTATUS_LPSC (0x1u << 16) /**< \brief (UHP_HCRHSTATUS) Local power status change (read/write) */
+#define UHP_HCRHSTATUS_OCIC (0x1u << 17) /**< \brief (UHP_HCRHSTATUS) Overcurrent indication change (read/write) */
+#define UHP_HCRHSTATUS_CRWE (0x1u << 31) /**< \brief (UHP_HCRHSTATUS) Clear remote wake-up enable (read/write) */
+/* -------- UHP_HCRHPORTSTATUS[2] : (UHP Offset: 0x54) HC Port 1 Status and Control Register -------- */
+#define UHP_HCRHPORTSTATUS_CCS_CPE (0x1u << 0) /**< \brief (UHP_HCRHPORTSTATUS[2]) */
+#define UHP_HCRHPORTSTATUS_PES_SPE (0x1u << 1) /**< \brief (UHP_HCRHPORTSTATUS[2]) */
+#define UHP_HCRHPORTSTATUS_PSS_SPS (0x1u << 2) /**< \brief (UHP_HCRHPORTSTATUS[2]) */
+#define UHP_HCRHPORTSTATUS_POCI_CSS (0x1u << 3) /**< \brief (UHP_HCRHPORTSTATUS[2]) */
+#define UHP_HCRHPORTSTATUS_PRS_SPR (0x1u << 4) /**< \brief (UHP_HCRHPORTSTATUS[2]) */
+#define UHP_HCRHPORTSTATUS_PPS_SPP (0x1u << 8) /**< \brief (UHP_HCRHPORTSTATUS[2]) */
+#define UHP_HCRHPORTSTATUS_LSDA_CPP (0x1u << 9) /**< \brief (UHP_HCRHPORTSTATUS[2]) */
+#define UHP_HCRHPORTSTATUS_CSC (0x1u << 16) /**< \brief (UHP_HCRHPORTSTATUS[2]) Port 1 connect status change (read/write, write '1' to clear) */
+#define UHP_HCRHPORTSTATUS_PESC (0x1u << 17) /**< \brief (UHP_HCRHPORTSTATUS[2]) Port 1 enable status change (read/write, write '1' to clear) */
+#define UHP_HCRHPORTSTATUS_PSSC (0x1u << 18) /**< \brief (UHP_HCRHPORTSTATUS[2]) Port 1 suspend status change (read/write, write '1' to clear) */
+#define UHP_HCRHPORTSTATUS_OCIC (0x1u << 19) /**< \brief (UHP_HCRHPORTSTATUS[2]) Port 1 overcurrent indicator change (read/write) */
+#define UHP_HCRHPORTSTATUS_PRSC (0x1u << 20) /**< \brief (UHP_HCRHPORTSTATUS[2]) Port 1 reset status change (read/write, write '1' to clear) */
+
+/*@}*/
+
+
+#endif /* _SAMG55_UHP_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_usart.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,416 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_USART_COMPONENT_
+#define _SAMG55_USART_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAMG55_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Usart hardware registers */
+typedef struct {
+ __O uint32_t US_CR; /**< \brief (Usart Offset: 0x000) USART Control Register */
+ __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x004) USART Mode Register */
+ __O uint32_t US_IER; /**< \brief (Usart Offset: 0x008) USART Interrupt Enable Register */
+ __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x00C) USART Interrupt Disable Register */
+ __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x010) USART Interrupt Mask Register */
+ __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x014) USART Channel Status Register */
+ __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x018) USART Receive Holding Register */
+ __O uint32_t US_THR; /**< \brief (Usart Offset: 0x01C) USART Transmit Holding Register */
+ __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x020) USART Baud Rate Generator Register */
+ __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x024) USART Receiver Time-out Register */
+ __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x028) USART Transmitter Timeguard Register */
+ __I uint32_t Reserved1[5];
+ __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x040) USART FI DI Ratio Register */
+ __I uint32_t US_NER; /**< \brief (Usart Offset: 0x044) USART Number of Errors Register */
+ __I uint32_t Reserved2[3];
+ __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x054) USART LIN Mode Register */
+ __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x058) USART LIN Identifier Register */
+ __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x05C) USART LIN Baud Rate Register */
+ __I uint32_t Reserved3[12];
+ __IO uint32_t US_CMPR; /**< \brief (Usart Offset: 0x090) USART Comparison Register */
+ __I uint32_t Reserved4[20];
+ __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x0E4) USART Write Protection Mode Register */
+ __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x0E8) USART Write Protection Status Register */
+ __I uint32_t Reserved5[5];
+ __IO uint32_t US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
+ __IO uint32_t US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */
+ __IO uint32_t US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
+ __IO uint32_t US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
+ __IO uint32_t US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
+ __IO uint32_t US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
+ __IO uint32_t US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
+ __IO uint32_t US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
+ __O uint32_t US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */
+ __I uint32_t US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */
+} Usart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- US_CR : (USART Offset: 0x000) USART Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */
+#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */
+#define US_CR_REQCLR (0x1u << 28) /**< \brief (US_CR) Request to Clear the Comparison Trigger */
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
+/* -------- US_MR : (USART Offset: 0x004) USART Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */
+#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 mode */
+#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define US_MR_USART_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_MR) LIN master mode */
+#define US_MR_USART_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_MR) LIN Slave mode */
+#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master mode */
+#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave mode */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */
+#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock Divided (DIV=8) is selected */
+#define US_MR_USCLKS_PMC_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock (PCK) is selected.If the SCK pin is driven (CLKO=1), the CD field must be greater than 1. */
+#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) External pin (SCK) is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */
+#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bits (SYNC = 0) or reserved (SYNC = 1) */
+#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */
+#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
+#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */
+/* -------- US_IER : (USART Offset: 0x008) USART Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Buffer Interrupt Enable (available in all USART modes of operation) */
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Buffer Interrupt Enable (available in all USART modes of operation) */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation) */
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Receive Buffer Full Interrupt Enable (available in all USART modes of operation) */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+#define US_IER_CMP (0x1u << 22) /**< \brief (US_IER) Comparison Interrupt Enable */
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */
+#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */
+#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */
+#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */
+#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */
+#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */
+#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */
+#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */
+#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */
+#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */
+#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x00C) USART Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Buffer Interrupt Enable (available in all USART modes of operation) */
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Buffer Interrupt Disable (available in all USART modes of operation) */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation) */
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Receive Buffer Full Interrupt Enable (available in all USART modes of operation) */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+#define US_IDR_CMP (0x1u << 22) /**< \brief (US_IDR) Comparison Interrupt Disable */
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */
+#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */
+#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */
+#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */
+#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */
+#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */
+#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */
+#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */
+#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */
+#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */
+#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x010) USART Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Buffer Interrupt Mask (available in all USART modes of operation) */
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Buffer Interrupt Mask (available in all USART modes of operation) */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Transmit Buffer Empty Interrupt Mask (available in all USART modes of operation) */
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Receive Buffer Full Interrupt Mask (available in all USART modes of operation) */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+#define US_IMR_CMP (0x1u << 22) /**< \brief (US_IMR) Comparison Interrupt Mask */
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */
+#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */
+#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */
+#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */
+#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */
+#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */
+#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */
+#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */
+#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */
+#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */
+#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x014) USART Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (automatically set / cleared) */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (automatically set / cleared) */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break (cleared by US_CR.RSTSTA command) */
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of RX Buffer (automatically set / cleared) */
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of TX Buffer (automatically set / cleared) */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error (cleared by US_CR.RSTSTA command) */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error (cleared by US_CR.RSTSTA command) */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error (cleared by US_CR.RSTSTA command) */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out (cleared by US_CR.STTTO command) */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (automatically set / cleared) */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached (cleared by US_CR.RSTIT command) */
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) TX Buffer Empty (automatically set / cleared) */
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) RX Buffer Full (automatically set / cleared) */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt (cleared by US_CR.RSTNACK command) */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag (clear on read) */
+#define US_CSR_CMP (0x1u << 22) /**< \brief (US_CSR) Comparison Status (cleared by US_CR.RSTSTA command) */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input (automatically set / cleared) */
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error (cleared by US_CR.RSTSTA) */
+#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received (cleared by US_CR.RSTSTA command) */
+#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by US_CR.RSTSTA command) */
+#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed (cleared by US_CR.RSTSTA command) */
+#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */
+#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error (cleared by US_CR.RSTSTA command) */
+#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error (cleared by US_CR.RSTSTA command) */
+#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error (cleared by US_CR.RSTSTA command) */
+#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error (cleared by US_CR.RSTSTA command) */
+#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error (cleared by US_CR.RSTSTA command) */
+#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error (cleared by US_CR.RSTSTA command) */
+#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error (cleared by US_CR.RSTSTA command) */
+/* -------- US_RHR : (USART Offset: 0x018) USART Receive Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+/* -------- US_THR : (USART Offset: 0x01C) USART Transmit Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */
+/* -------- US_BRGR : (USART Offset: 0x020) USART Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x024) USART Receiver Time-out Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x028) USART Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x040) USART FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x044) USART Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_LINMR : (USART Offset: 0x054) USART LIN Mode Register -------- */
+#define US_LINMR_NACT_Pos 0
+#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */
+#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */
+#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */
+#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */
+#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */
+#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */
+#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */
+#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */
+#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */
+#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */
+#define US_LINMR_DLC_Pos 8
+#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */
+#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))
+#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) PDC Mode */
+#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */
+/* -------- US_LINIR : (USART Offset: 0x058) USART LIN Identifier Register -------- */
+#define US_LINIR_IDCHR_Pos 0
+#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */
+#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))
+/* -------- US_LINBRR : (USART Offset: 0x05C) USART LIN Baud Rate Register -------- */
+#define US_LINBRR_LINCD_Pos 0
+#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */
+#define US_LINBRR_LINFP_Pos 16
+#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */
+/* -------- US_CMPR : (USART Offset: 0x090) USART Comparison Register -------- */
+#define US_CMPR_VAL1_Pos 0
+#define US_CMPR_VAL1_Msk (0x1ffu << US_CMPR_VAL1_Pos) /**< \brief (US_CMPR) First Comparison Value for Received Character */
+#define US_CMPR_VAL1(value) ((US_CMPR_VAL1_Msk & ((value) << US_CMPR_VAL1_Pos)))
+#define US_CMPR_CMPMODE (0x1u << 12) /**< \brief (US_CMPR) Comparison Mode */
+#define US_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (US_CMPR) Any character is received and comparison function drives CMP flag. */
+#define US_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (US_CMPR) Comparison condition must be met to start reception of all incoming charactersuntil REQCLR is set. */
+#define US_CMPR_CMPPAR (0x1u << 14) /**< \brief (US_CMPR) Compare Parity */
+#define US_CMPR_VAL2_Pos 16
+#define US_CMPR_VAL2_Msk (0x1ffu << US_CMPR_VAL2_Pos) /**< \brief (US_CMPR) Second Comparison Value for Received Character */
+#define US_CMPR_VAL2(value) ((US_CMPR_VAL2_Msk & ((value) << US_CMPR_VAL2_Pos)))
+/* -------- US_WPMR : (USART Offset: 0x0E4) USART Write Protection Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */
+#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
+/* -------- US_WPSR : (USART Offset: 0x0E8) USART Write Protection Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
+#define US_RPR_RXPTR_Pos 0
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
+#define US_RCR_RXCTR_Pos 0
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
+#define US_TPR_TXPTR_Pos 0
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
+#define US_TCR_TXCTR_Pos 0
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
+#define US_RNPR_RXNPTR_Pos 0
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
+#define US_RNCR_RXNCTR_Pos 0
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define US_TNPR_TXNPTR_Pos 0
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define US_TNCR_TXNCTR_Pos 0
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
+#define US_PTCR_RXCBEN (0x1u << 16) /**< \brief (US_PTCR) Receiver Circular Buffer Enable */
+#define US_PTCR_RXCBDIS (0x1u << 17) /**< \brief (US_PTCR) Receiver Circular Buffer Disable */
+#define US_PTCR_TXCBEN (0x1u << 18) /**< \brief (US_PTCR) Transmitter Circular Buffer Enable */
+#define US_PTCR_TXCBDIS (0x1u << 19) /**< \brief (US_PTCR) Transmitter Circular Buffer Disable */
+#define US_PTCR_ERRCLR (0x1u << 24) /**< \brief (US_PTCR) Transfer Bus Error Clear */
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+#define US_PTSR_RXCBEN (0x1u << 16) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXCBEN (0x1u << 18) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+#define US_PTSR_ERR (0x1u << 24) /**< \brief (US_PTSR) Transfer Bus Error (clear on read) */
+
+/*@}*/
+
+
+#endif /* _SAMG55_USART_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_wdt.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,87 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55_WDT_COMPONENT_
+#define _SAMG55_WDT_COMPONENT_
+
+/* ============================================================================= */
+/** SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAMG55_WDT Watchdog Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Wdt hardware registers */
+typedef struct {
+ __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+ __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+ __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password. */
+#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
+
+/*@}*/
+
+
+#endif /* _SAMG55_WDT_COMPONENT_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_adc.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,105 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_ADC_INSTANCE_ +#define _SAMG55_ADC_INSTANCE_ + +/* ========== Register definition for ADC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ADC_CR (0x40038000U) /**< \brief (ADC) Control Register */ +#define REG_ADC_MR (0x40038004U) /**< \brief (ADC) Mode Register */ +#define REG_ADC_SEQR1 (0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */ +#define REG_ADC_CHER (0x40038010U) /**< \brief (ADC) Channel Enable Register */ +#define REG_ADC_CHDR (0x40038014U) /**< \brief (ADC) Channel Disable Register */ +#define REG_ADC_CHSR (0x40038018U) /**< \brief (ADC) Channel Status Register */ +#define REG_ADC_LCDR (0x40038020U) /**< \brief (ADC) Last Converted Data Register */ +#define REG_ADC_IER (0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ +#define REG_ADC_IDR (0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ +#define REG_ADC_IMR (0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ +#define REG_ADC_ISR (0x40038030U) /**< \brief (ADC) Interrupt Status Register */ +#define REG_ADC_LCTMR (0x40038034U) /**< \brief (ADC) Last Channel Trigger Mode Register */ +#define REG_ADC_LCCWR (0x40038038U) /**< \brief (ADC) Last Channel Compare Window Register */ +#define REG_ADC_OVER (0x4003803CU) /**< \brief (ADC) Overrun Status Register */ +#define REG_ADC_EMR (0x40038040U) /**< \brief (ADC) Extended Mode Register */ +#define REG_ADC_CWR (0x40038044U) /**< \brief (ADC) Compare Window Register */ +#define REG_ADC_COR (0x4003804CU) /**< \brief (ADC) Channel Offset Register */ +#define REG_ADC_CDR (0x40038050U) /**< \brief (ADC) Channel Data Register */ +#define REG_ADC_WPMR (0x400380E4U) /**< \brief (ADC) Write Protection Mode Register */ +#define REG_ADC_WPSR (0x400380E8U) /**< \brief (ADC) Write Protection Status Register */ +#define REG_ADC_RPR (0x40038100U) /**< \brief (ADC) Receive Pointer Register */ +#define REG_ADC_RCR (0x40038104U) /**< \brief (ADC) Receive Counter Register */ +#define REG_ADC_RNPR (0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ +#define REG_ADC_RNCR (0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ +#define REG_ADC_PTCR (0x40038120U) /**< \brief (ADC) Transfer Control Register */ +#define REG_ADC_PTSR (0x40038124U) /**< \brief (ADC) Transfer Status Register */ +#else +#define REG_ADC_CR (*(__O uint32_t*)0x40038000U) /**< \brief (ADC) Control Register */ +#define REG_ADC_MR (*(__IO uint32_t*)0x40038004U) /**< \brief (ADC) Mode Register */ +#define REG_ADC_SEQR1 (*(__IO uint32_t*)0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */ +#define REG_ADC_CHER (*(__O uint32_t*)0x40038010U) /**< \brief (ADC) Channel Enable Register */ +#define REG_ADC_CHDR (*(__O uint32_t*)0x40038014U) /**< \brief (ADC) Channel Disable Register */ +#define REG_ADC_CHSR (*(__I uint32_t*)0x40038018U) /**< \brief (ADC) Channel Status Register */ +#define REG_ADC_LCDR (*(__I uint32_t*)0x40038020U) /**< \brief (ADC) Last Converted Data Register */ +#define REG_ADC_IER (*(__O uint32_t*)0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ +#define REG_ADC_IDR (*(__O uint32_t*)0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ +#define REG_ADC_IMR (*(__I uint32_t*)0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ +#define REG_ADC_ISR (*(__I uint32_t*)0x40038030U) /**< \brief (ADC) Interrupt Status Register */ +#define REG_ADC_LCTMR (*(__IO uint32_t*)0x40038034U) /**< \brief (ADC) Last Channel Trigger Mode Register */ +#define REG_ADC_LCCWR (*(__IO uint32_t*)0x40038038U) /**< \brief (ADC) Last Channel Compare Window Register */ +#define REG_ADC_OVER (*(__I uint32_t*)0x4003803CU) /**< \brief (ADC) Overrun Status Register */ +#define REG_ADC_EMR (*(__IO uint32_t*)0x40038040U) /**< \brief (ADC) Extended Mode Register */ +#define REG_ADC_CWR (*(__IO uint32_t*)0x40038044U) /**< \brief (ADC) Compare Window Register */ +#define REG_ADC_COR (*(__IO uint32_t*)0x4003804CU) /**< \brief (ADC) Channel Offset Register */ +#define REG_ADC_CDR (*(__I uint32_t*)0x40038050U) /**< \brief (ADC) Channel Data Register */ +#define REG_ADC_WPMR (*(__IO uint32_t*)0x400380E4U) /**< \brief (ADC) Write Protection Mode Register */ +#define REG_ADC_WPSR (*(__I uint32_t*)0x400380E8U) /**< \brief (ADC) Write Protection Status Register */ +#define REG_ADC_RPR (*(__IO uint32_t*)0x40038100U) /**< \brief (ADC) Receive Pointer Register */ +#define REG_ADC_RCR (*(__IO uint32_t*)0x40038104U) /**< \brief (ADC) Receive Counter Register */ +#define REG_ADC_RNPR (*(__IO uint32_t*)0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ +#define REG_ADC_RNCR (*(__IO uint32_t*)0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ +#define REG_ADC_PTCR (*(__O uint32_t*)0x40038120U) /**< \brief (ADC) Transfer Control Register */ +#define REG_ADC_PTSR (*(__I uint32_t*)0x40038124U) /**< \brief (ADC) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_ADC_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_chipid.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,57 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_CHIPID_INSTANCE_ +#define _SAMG55_CHIPID_INSTANCE_ + +/* ========== Register definition for CHIPID peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CHIPID_CIDR (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ +#define REG_CHIPID_EXID (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ +#else +#define REG_CHIPID_CIDR (*(__I uint32_t*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ +#define REG_CHIPID_EXID (*(__I uint32_t*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_CHIPID_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_cmcc.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,73 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_CMCC_INSTANCE_ +#define _SAMG55_CMCC_INSTANCE_ + +/* ========== Register definition for CMCC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CMCC_TYPE (0x4003C000U) /**< \brief (CMCC) Cache Controller Type Register */ +#define REG_CMCC_CFG (0x4003C004U) /**< \brief (CMCC) Cache Controller Configuration Register */ +#define REG_CMCC_CTRL (0x4003C008U) /**< \brief (CMCC) Cache Controller Control Register */ +#define REG_CMCC_SR (0x4003C00CU) /**< \brief (CMCC) Cache Controller Status Register */ +#define REG_CMCC_MAINT0 (0x4003C020U) /**< \brief (CMCC) Cache Controller Maintenance Register 0 */ +#define REG_CMCC_MAINT1 (0x4003C024U) /**< \brief (CMCC) Cache Controller Maintenance Register 1 */ +#define REG_CMCC_MCFG (0x4003C028U) /**< \brief (CMCC) Cache Controller Monitor Configuration Register */ +#define REG_CMCC_MEN (0x4003C02CU) /**< \brief (CMCC) Cache Controller Monitor Enable Register */ +#define REG_CMCC_MCTRL (0x4003C030U) /**< \brief (CMCC) Cache Controller Monitor Control Register */ +#define REG_CMCC_MSR (0x4003C034U) /**< \brief (CMCC) Cache Controller Monitor Status Register */ +#else +#define REG_CMCC_TYPE (*(__I uint32_t*)0x4003C000U) /**< \brief (CMCC) Cache Controller Type Register */ +#define REG_CMCC_CFG (*(__IO uint32_t*)0x4003C004U) /**< \brief (CMCC) Cache Controller Configuration Register */ +#define REG_CMCC_CTRL (*(__O uint32_t*)0x4003C008U) /**< \brief (CMCC) Cache Controller Control Register */ +#define REG_CMCC_SR (*(__I uint32_t*)0x4003C00CU) /**< \brief (CMCC) Cache Controller Status Register */ +#define REG_CMCC_MAINT0 (*(__O uint32_t*)0x4003C020U) /**< \brief (CMCC) Cache Controller Maintenance Register 0 */ +#define REG_CMCC_MAINT1 (*(__O uint32_t*)0x4003C024U) /**< \brief (CMCC) Cache Controller Maintenance Register 1 */ +#define REG_CMCC_MCFG (*(__IO uint32_t*)0x4003C028U) /**< \brief (CMCC) Cache Controller Monitor Configuration Register */ +#define REG_CMCC_MEN (*(__IO uint32_t*)0x4003C02CU) /**< \brief (CMCC) Cache Controller Monitor Enable Register */ +#define REG_CMCC_MCTRL (*(__O uint32_t*)0x4003C030U) /**< \brief (CMCC) Cache Controller Monitor Control Register */ +#define REG_CMCC_MSR (*(__I uint32_t*)0x4003C034U) /**< \brief (CMCC) Cache Controller Monitor Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_CMCC_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_crccu.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,83 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_CRCCU_INSTANCE_ +#define _SAMG55_CRCCU_INSTANCE_ + +/* ========== Register definition for CRCCU peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CRCCU_DSCR (0x40048000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ +#define REG_CRCCU_DMA_EN (0x40048008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ +#define REG_CRCCU_DMA_DIS (0x4004800CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ +#define REG_CRCCU_DMA_SR (0x40048010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ +#define REG_CRCCU_DMA_IER (0x40048014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ +#define REG_CRCCU_DMA_IDR (0x40048018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ +#define REG_CRCCU_DMA_IMR (0x4004801CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ +#define REG_CRCCU_DMA_ISR (0x40048020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ +#define REG_CRCCU_CR (0x40048034U) /**< \brief (CRCCU) CRCCU Control Register */ +#define REG_CRCCU_MR (0x40048038U) /**< \brief (CRCCU) CRCCU Mode Register */ +#define REG_CRCCU_SR (0x4004803CU) /**< \brief (CRCCU) CRCCU Status Register */ +#define REG_CRCCU_IER (0x40048040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ +#define REG_CRCCU_IDR (0x40048044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ +#define REG_CRCCU_IMR (0x40048048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ +#define REG_CRCCU_ISR (0x4004804CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ +#else +#define REG_CRCCU_DSCR (*(__IO uint32_t*)0x40048000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ +#define REG_CRCCU_DMA_EN (*(__O uint32_t*)0x40048008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ +#define REG_CRCCU_DMA_DIS (*(__O uint32_t*)0x4004800CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ +#define REG_CRCCU_DMA_SR (*(__I uint32_t*)0x40048010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ +#define REG_CRCCU_DMA_IER (*(__O uint32_t*)0x40048014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ +#define REG_CRCCU_DMA_IDR (*(__O uint32_t*)0x40048018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ +#define REG_CRCCU_DMA_IMR (*(__I uint32_t*)0x4004801CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ +#define REG_CRCCU_DMA_ISR (*(__I uint32_t*)0x40048020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ +#define REG_CRCCU_CR (*(__O uint32_t*)0x40048034U) /**< \brief (CRCCU) CRCCU Control Register */ +#define REG_CRCCU_MR (*(__IO uint32_t*)0x40048038U) /**< \brief (CRCCU) CRCCU Mode Register */ +#define REG_CRCCU_SR (*(__I uint32_t*)0x4004803CU) /**< \brief (CRCCU) CRCCU Status Register */ +#define REG_CRCCU_IER (*(__O uint32_t*)0x40048040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ +#define REG_CRCCU_IDR (*(__O uint32_t*)0x40048044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ +#define REG_CRCCU_IMR (*(__I uint32_t*)0x40048048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ +#define REG_CRCCU_ISR (*(__I uint32_t*)0x4004804CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_CRCCU_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_efc.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,63 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_EFC_INSTANCE_ +#define _SAMG55_EFC_INSTANCE_ + +/* ========== Register definition for EFC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EFC_FMR (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ +#define REG_EFC_FCR (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ +#define REG_EFC_FSR (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ +#define REG_EFC_FRR (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ +#define REG_EFC_WPMR (0x400E0AE4U) /**< \brief (EFC) Write Protection Mode Register */ +#else +#define REG_EFC_FMR (*(__IO uint32_t*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ +#define REG_EFC_FCR (*(__O uint32_t*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ +#define REG_EFC_FSR (*(__I uint32_t*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ +#define REG_EFC_FRR (*(__I uint32_t*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ +#define REG_EFC_WPMR (*(__IO uint32_t*)0x400E0AE4U) /**< \brief (EFC) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_EFC_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom0.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,59 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_FLEXCOM0_INSTANCE_ +#define _SAMG55_FLEXCOM0_INSTANCE_ + +/* ========== Register definition for FLEXCOM0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_FLEXCOM0_MR (0x4000C000U) /**< \brief (FLEXCOM0) FLEXCOM Mode register */ +#define REG_FLEXCOM0_RHR (0x4000C010U) /**< \brief (FLEXCOM0) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM0_THR (0x4000C020U) /**< \brief (FLEXCOM0) FLEXCOM Transmit Holding Register */ +#else +#define REG_FLEXCOM0_MR (*(__IO uint32_t*)0x4000C000U) /**< \brief (FLEXCOM0) FLEXCOM Mode register */ +#define REG_FLEXCOM0_RHR (*(__I uint32_t*)0x4000C010U) /**< \brief (FLEXCOM0) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM0_THR (*(__IO uint32_t*)0x4000C020U) /**< \brief (FLEXCOM0) FLEXCOM Transmit Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_FLEXCOM0_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom1.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,59 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_FLEXCOM1_INSTANCE_ +#define _SAMG55_FLEXCOM1_INSTANCE_ + +/* ========== Register definition for FLEXCOM1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_FLEXCOM1_MR (0x40020000U) /**< \brief (FLEXCOM1) FLEXCOM Mode register */ +#define REG_FLEXCOM1_RHR (0x40020010U) /**< \brief (FLEXCOM1) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM1_THR (0x40020020U) /**< \brief (FLEXCOM1) FLEXCOM Transmit Holding Register */ +#else +#define REG_FLEXCOM1_MR (*(__IO uint32_t*)0x40020000U) /**< \brief (FLEXCOM1) FLEXCOM Mode register */ +#define REG_FLEXCOM1_RHR (*(__I uint32_t*)0x40020010U) /**< \brief (FLEXCOM1) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM1_THR (*(__IO uint32_t*)0x40020020U) /**< \brief (FLEXCOM1) FLEXCOM Transmit Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_FLEXCOM1_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom2.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,59 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_FLEXCOM2_INSTANCE_ +#define _SAMG55_FLEXCOM2_INSTANCE_ + +/* ========== Register definition for FLEXCOM2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_FLEXCOM2_MR (0x40024000U) /**< \brief (FLEXCOM2) FLEXCOM Mode register */ +#define REG_FLEXCOM2_RHR (0x40024010U) /**< \brief (FLEXCOM2) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM2_THR (0x40024020U) /**< \brief (FLEXCOM2) FLEXCOM Transmit Holding Register */ +#else +#define REG_FLEXCOM2_MR (*(__IO uint32_t*)0x40024000U) /**< \brief (FLEXCOM2) FLEXCOM Mode register */ +#define REG_FLEXCOM2_RHR (*(__I uint32_t*)0x40024010U) /**< \brief (FLEXCOM2) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM2_THR (*(__IO uint32_t*)0x40024020U) /**< \brief (FLEXCOM2) FLEXCOM Transmit Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_FLEXCOM2_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom3.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,59 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_FLEXCOM3_INSTANCE_ +#define _SAMG55_FLEXCOM3_INSTANCE_ + +/* ========== Register definition for FLEXCOM3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_FLEXCOM3_MR (0x40018000U) /**< \brief (FLEXCOM3) FLEXCOM Mode register */ +#define REG_FLEXCOM3_RHR (0x40018010U) /**< \brief (FLEXCOM3) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM3_THR (0x40018020U) /**< \brief (FLEXCOM3) FLEXCOM Transmit Holding Register */ +#else +#define REG_FLEXCOM3_MR (*(__IO uint32_t*)0x40018000U) /**< \brief (FLEXCOM3) FLEXCOM Mode register */ +#define REG_FLEXCOM3_RHR (*(__I uint32_t*)0x40018010U) /**< \brief (FLEXCOM3) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM3_THR (*(__IO uint32_t*)0x40018020U) /**< \brief (FLEXCOM3) FLEXCOM Transmit Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_FLEXCOM3_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom4.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,59 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_FLEXCOM4_INSTANCE_ +#define _SAMG55_FLEXCOM4_INSTANCE_ + +/* ========== Register definition for FLEXCOM4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_FLEXCOM4_MR (0x4001C000U) /**< \brief (FLEXCOM4) FLEXCOM Mode register */ +#define REG_FLEXCOM4_RHR (0x4001C010U) /**< \brief (FLEXCOM4) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM4_THR (0x4001C020U) /**< \brief (FLEXCOM4) FLEXCOM Transmit Holding Register */ +#else +#define REG_FLEXCOM4_MR (*(__IO uint32_t*)0x4001C000U) /**< \brief (FLEXCOM4) FLEXCOM Mode register */ +#define REG_FLEXCOM4_RHR (*(__I uint32_t*)0x4001C010U) /**< \brief (FLEXCOM4) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM4_THR (*(__IO uint32_t*)0x4001C020U) /**< \brief (FLEXCOM4) FLEXCOM Transmit Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_FLEXCOM4_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom5.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,59 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_FLEXCOM5_INSTANCE_ +#define _SAMG55_FLEXCOM5_INSTANCE_ + +/* ========== Register definition for FLEXCOM5 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_FLEXCOM5_MR (0x40008000U) /**< \brief (FLEXCOM5) FLEXCOM Mode register */ +#define REG_FLEXCOM5_RHR (0x40008010U) /**< \brief (FLEXCOM5) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM5_THR (0x40008020U) /**< \brief (FLEXCOM5) FLEXCOM Transmit Holding Register */ +#else +#define REG_FLEXCOM5_MR (*(__IO uint32_t*)0x40008000U) /**< \brief (FLEXCOM5) FLEXCOM Mode register */ +#define REG_FLEXCOM5_RHR (*(__I uint32_t*)0x40008010U) /**< \brief (FLEXCOM5) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM5_THR (*(__IO uint32_t*)0x40008020U) /**< \brief (FLEXCOM5) FLEXCOM Transmit Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_FLEXCOM5_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom6.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,59 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_FLEXCOM6_INSTANCE_ +#define _SAMG55_FLEXCOM6_INSTANCE_ + +/* ========== Register definition for FLEXCOM6 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_FLEXCOM6_MR (0x40040000U) /**< \brief (FLEXCOM6) FLEXCOM Mode register */ +#define REG_FLEXCOM6_RHR (0x40040010U) /**< \brief (FLEXCOM6) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM6_THR (0x40040020U) /**< \brief (FLEXCOM6) FLEXCOM Transmit Holding Register */ +#else +#define REG_FLEXCOM6_MR (*(__IO uint32_t*)0x40040000U) /**< \brief (FLEXCOM6) FLEXCOM Mode register */ +#define REG_FLEXCOM6_RHR (*(__I uint32_t*)0x40040010U) /**< \brief (FLEXCOM6) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM6_THR (*(__IO uint32_t*)0x40040020U) /**< \brief (FLEXCOM6) FLEXCOM Transmit Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_FLEXCOM6_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_flexcom7.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,59 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_FLEXCOM7_INSTANCE_ +#define _SAMG55_FLEXCOM7_INSTANCE_ + +/* ========== Register definition for FLEXCOM7 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_FLEXCOM7_MR (0x40034000U) /**< \brief (FLEXCOM7) FLEXCOM Mode register */ +#define REG_FLEXCOM7_RHR (0x40034010U) /**< \brief (FLEXCOM7) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM7_THR (0x40034020U) /**< \brief (FLEXCOM7) FLEXCOM Transmit Holding Register */ +#else +#define REG_FLEXCOM7_MR (*(__IO uint32_t*)0x40034000U) /**< \brief (FLEXCOM7) FLEXCOM Mode register */ +#define REG_FLEXCOM7_RHR (*(__I uint32_t*)0x40034010U) /**< \brief (FLEXCOM7) FLEXCOM Receive Holding Register */ +#define REG_FLEXCOM7_THR (*(__IO uint32_t*)0x40034020U) /**< \brief (FLEXCOM7) FLEXCOM Transmit Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_FLEXCOM7_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_gpbr.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,55 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_GPBR_INSTANCE_ +#define _SAMG55_GPBR_INSTANCE_ + +/* ========== Register definition for GPBR peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_GPBR_GPBR (0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */ +#else +#define REG_GPBR_GPBR (*(__IO uint32_t*)0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_GPBR_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_i2sc0.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,93 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_I2SC0_INSTANCE_ +#define _SAMG55_I2SC0_INSTANCE_ + +/* ========== Register definition for I2SC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_I2SC0_CR (0x40000000U) /**< \brief (I2SC0) Control Register */ +#define REG_I2SC0_MR (0x40000004U) /**< \brief (I2SC0) Mode Register */ +#define REG_I2SC0_SR (0x40000008U) /**< \brief (I2SC0) Status Register */ +#define REG_I2SC0_SCR (0x4000000CU) /**< \brief (I2SC0) Status Clear Register */ +#define REG_I2SC0_SSR (0x40000010U) /**< \brief (I2SC0) Status Set Register */ +#define REG_I2SC0_IER (0x40000014U) /**< \brief (I2SC0) Interrupt Enable Register */ +#define REG_I2SC0_IDR (0x40000018U) /**< \brief (I2SC0) Interrupt Disable Register */ +#define REG_I2SC0_IMR (0x4000001CU) /**< \brief (I2SC0) Interrupt Mask Register */ +#define REG_I2SC0_RHR (0x40000020U) /**< \brief (I2SC0) Receiver Holding Register */ +#define REG_I2SC0_THR (0x40000024U) /**< \brief (I2SC0) Transmitter Holding Register */ +#define REG_I2SC0_RPR (0x40000100U) /**< \brief (I2SC0) Receive Pointer Register */ +#define REG_I2SC0_RCR (0x40000104U) /**< \brief (I2SC0) Receive Counter Register */ +#define REG_I2SC0_TPR (0x40000108U) /**< \brief (I2SC0) Transmit Pointer Register */ +#define REG_I2SC0_TCR (0x4000010CU) /**< \brief (I2SC0) Transmit Counter Register */ +#define REG_I2SC0_RNPR (0x40000110U) /**< \brief (I2SC0) Receive Next Pointer Register */ +#define REG_I2SC0_RNCR (0x40000114U) /**< \brief (I2SC0) Receive Next Counter Register */ +#define REG_I2SC0_TNPR (0x40000118U) /**< \brief (I2SC0) Transmit Next Pointer Register */ +#define REG_I2SC0_TNCR (0x4000011CU) /**< \brief (I2SC0) Transmit Next Counter Register */ +#define REG_I2SC0_PTCR (0x40000120U) /**< \brief (I2SC0) Transfer Control Register */ +#define REG_I2SC0_PTSR (0x40000124U) /**< \brief (I2SC0) Transfer Status Register */ +#else +#define REG_I2SC0_CR (*(__O uint32_t*)0x40000000U) /**< \brief (I2SC0) Control Register */ +#define REG_I2SC0_MR (*(__IO uint32_t*)0x40000004U) /**< \brief (I2SC0) Mode Register */ +#define REG_I2SC0_SR (*(__I uint32_t*)0x40000008U) /**< \brief (I2SC0) Status Register */ +#define REG_I2SC0_SCR (*(__O uint32_t*)0x4000000CU) /**< \brief (I2SC0) Status Clear Register */ +#define REG_I2SC0_SSR (*(__O uint32_t*)0x40000010U) /**< \brief (I2SC0) Status Set Register */ +#define REG_I2SC0_IER (*(__O uint32_t*)0x40000014U) /**< \brief (I2SC0) Interrupt Enable Register */ +#define REG_I2SC0_IDR (*(__O uint32_t*)0x40000018U) /**< \brief (I2SC0) Interrupt Disable Register */ +#define REG_I2SC0_IMR (*(__I uint32_t*)0x4000001CU) /**< \brief (I2SC0) Interrupt Mask Register */ +#define REG_I2SC0_RHR (*(__I uint32_t*)0x40000020U) /**< \brief (I2SC0) Receiver Holding Register */ +#define REG_I2SC0_THR (*(__O uint32_t*)0x40000024U) /**< \brief (I2SC0) Transmitter Holding Register */ +#define REG_I2SC0_RPR (*(__IO uint32_t*)0x40000100U) /**< \brief (I2SC0) Receive Pointer Register */ +#define REG_I2SC0_RCR (*(__IO uint32_t*)0x40000104U) /**< \brief (I2SC0) Receive Counter Register */ +#define REG_I2SC0_TPR (*(__IO uint32_t*)0x40000108U) /**< \brief (I2SC0) Transmit Pointer Register */ +#define REG_I2SC0_TCR (*(__IO uint32_t*)0x4000010CU) /**< \brief (I2SC0) Transmit Counter Register */ +#define REG_I2SC0_RNPR (*(__IO uint32_t*)0x40000110U) /**< \brief (I2SC0) Receive Next Pointer Register */ +#define REG_I2SC0_RNCR (*(__IO uint32_t*)0x40000114U) /**< \brief (I2SC0) Receive Next Counter Register */ +#define REG_I2SC0_TNPR (*(__IO uint32_t*)0x40000118U) /**< \brief (I2SC0) Transmit Next Pointer Register */ +#define REG_I2SC0_TNCR (*(__IO uint32_t*)0x4000011CU) /**< \brief (I2SC0) Transmit Next Counter Register */ +#define REG_I2SC0_PTCR (*(__O uint32_t*)0x40000120U) /**< \brief (I2SC0) Transfer Control Register */ +#define REG_I2SC0_PTSR (*(__I uint32_t*)0x40000124U) /**< \brief (I2SC0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_I2SC0_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_i2sc1.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,93 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_I2SC1_INSTANCE_ +#define _SAMG55_I2SC1_INSTANCE_ + +/* ========== Register definition for I2SC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_I2SC1_CR (0x40004000U) /**< \brief (I2SC1) Control Register */ +#define REG_I2SC1_MR (0x40004004U) /**< \brief (I2SC1) Mode Register */ +#define REG_I2SC1_SR (0x40004008U) /**< \brief (I2SC1) Status Register */ +#define REG_I2SC1_SCR (0x4000400CU) /**< \brief (I2SC1) Status Clear Register */ +#define REG_I2SC1_SSR (0x40004010U) /**< \brief (I2SC1) Status Set Register */ +#define REG_I2SC1_IER (0x40004014U) /**< \brief (I2SC1) Interrupt Enable Register */ +#define REG_I2SC1_IDR (0x40004018U) /**< \brief (I2SC1) Interrupt Disable Register */ +#define REG_I2SC1_IMR (0x4000401CU) /**< \brief (I2SC1) Interrupt Mask Register */ +#define REG_I2SC1_RHR (0x40004020U) /**< \brief (I2SC1) Receiver Holding Register */ +#define REG_I2SC1_THR (0x40004024U) /**< \brief (I2SC1) Transmitter Holding Register */ +#define REG_I2SC1_RPR (0x40004100U) /**< \brief (I2SC1) Receive Pointer Register */ +#define REG_I2SC1_RCR (0x40004104U) /**< \brief (I2SC1) Receive Counter Register */ +#define REG_I2SC1_TPR (0x40004108U) /**< \brief (I2SC1) Transmit Pointer Register */ +#define REG_I2SC1_TCR (0x4000410CU) /**< \brief (I2SC1) Transmit Counter Register */ +#define REG_I2SC1_RNPR (0x40004110U) /**< \brief (I2SC1) Receive Next Pointer Register */ +#define REG_I2SC1_RNCR (0x40004114U) /**< \brief (I2SC1) Receive Next Counter Register */ +#define REG_I2SC1_TNPR (0x40004118U) /**< \brief (I2SC1) Transmit Next Pointer Register */ +#define REG_I2SC1_TNCR (0x4000411CU) /**< \brief (I2SC1) Transmit Next Counter Register */ +#define REG_I2SC1_PTCR (0x40004120U) /**< \brief (I2SC1) Transfer Control Register */ +#define REG_I2SC1_PTSR (0x40004124U) /**< \brief (I2SC1) Transfer Status Register */ +#else +#define REG_I2SC1_CR (*(__O uint32_t*)0x40004000U) /**< \brief (I2SC1) Control Register */ +#define REG_I2SC1_MR (*(__IO uint32_t*)0x40004004U) /**< \brief (I2SC1) Mode Register */ +#define REG_I2SC1_SR (*(__I uint32_t*)0x40004008U) /**< \brief (I2SC1) Status Register */ +#define REG_I2SC1_SCR (*(__O uint32_t*)0x4000400CU) /**< \brief (I2SC1) Status Clear Register */ +#define REG_I2SC1_SSR (*(__O uint32_t*)0x40004010U) /**< \brief (I2SC1) Status Set Register */ +#define REG_I2SC1_IER (*(__O uint32_t*)0x40004014U) /**< \brief (I2SC1) Interrupt Enable Register */ +#define REG_I2SC1_IDR (*(__O uint32_t*)0x40004018U) /**< \brief (I2SC1) Interrupt Disable Register */ +#define REG_I2SC1_IMR (*(__I uint32_t*)0x4000401CU) /**< \brief (I2SC1) Interrupt Mask Register */ +#define REG_I2SC1_RHR (*(__I uint32_t*)0x40004020U) /**< \brief (I2SC1) Receiver Holding Register */ +#define REG_I2SC1_THR (*(__O uint32_t*)0x40004024U) /**< \brief (I2SC1) Transmitter Holding Register */ +#define REG_I2SC1_RPR (*(__IO uint32_t*)0x40004100U) /**< \brief (I2SC1) Receive Pointer Register */ +#define REG_I2SC1_RCR (*(__IO uint32_t*)0x40004104U) /**< \brief (I2SC1) Receive Counter Register */ +#define REG_I2SC1_TPR (*(__IO uint32_t*)0x40004108U) /**< \brief (I2SC1) Transmit Pointer Register */ +#define REG_I2SC1_TCR (*(__IO uint32_t*)0x4000410CU) /**< \brief (I2SC1) Transmit Counter Register */ +#define REG_I2SC1_RNPR (*(__IO uint32_t*)0x40004110U) /**< \brief (I2SC1) Receive Next Pointer Register */ +#define REG_I2SC1_RNCR (*(__IO uint32_t*)0x40004114U) /**< \brief (I2SC1) Receive Next Counter Register */ +#define REG_I2SC1_TNPR (*(__IO uint32_t*)0x40004118U) /**< \brief (I2SC1) Transmit Next Pointer Register */ +#define REG_I2SC1_TNCR (*(__IO uint32_t*)0x4000411CU) /**< \brief (I2SC1) Transmit Next Counter Register */ +#define REG_I2SC1_PTCR (*(__O uint32_t*)0x40004120U) /**< \brief (I2SC1) Transfer Control Register */ +#define REG_I2SC1_PTSR (*(__I uint32_t*)0x40004124U) /**< \brief (I2SC1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_I2SC1_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_matrix.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,79 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_MATRIX_INSTANCE_ +#define _SAMG55_MATRIX_INSTANCE_ + +/* ========== Register definition for MATRIX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MATRIX_MCFG (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ +#define REG_MATRIX_SCFG (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ +#define REG_MATRIX_PRAS0 (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRAS1 (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRAS2 (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRAS3 (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ +#define REG_CCFG_RDMMEM (0x400E0310U) /**< \brief (MATRIX) Embedded Memories Read Margin Values Register */ +#define REG_CCFG_SYSIO (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration Register */ +#define REG_CCFG_DYNCKG (0x400E0318U) /**< \brief (MATRIX) Dynamic Clock Gating Register */ +#define REG_CCFG_I2SCLKSEL (0x400E031CU) /**< \brief (MATRIX) I2S Clock Source Selection Register */ +#define REG_CCFG_USBMR (0x400E0320U) /**< \brief (MATRIX) USB Management Register */ +#define REG_MATRIX_WPMR (0x400E03E4U) /**< \brief (MATRIX) Write Protection Mode Register */ +#define REG_MATRIX_WPSR (0x400E03E8U) /**< \brief (MATRIX) Write Protection Status Register */ +#else +#define REG_MATRIX_MCFG (*(__IO uint32_t*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ +#define REG_MATRIX_SCFG (*(__IO uint32_t*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ +#define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ +#define REG_CCFG_RDMMEM (*(__IO uint32_t*)0x400E0310U) /**< \brief (MATRIX) Embedded Memories Read Margin Values Register */ +#define REG_CCFG_SYSIO (*(__IO uint32_t*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration Register */ +#define REG_CCFG_DYNCKG (*(__IO uint32_t*)0x400E0318U) /**< \brief (MATRIX) Dynamic Clock Gating Register */ +#define REG_CCFG_I2SCLKSEL (*(__IO uint32_t*)0x400E031CU) /**< \brief (MATRIX) I2S Clock Source Selection Register */ +#define REG_CCFG_USBMR (*(__IO uint32_t*)0x400E0320U) /**< \brief (MATRIX) USB Management Register */ +#define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400E03E4U) /**< \brief (MATRIX) Write Protection Mode Register */ +#define REG_MATRIX_WPSR (*(__I uint32_t*)0x400E03E8U) /**< \brief (MATRIX) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_MATRIX_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_mem2mem.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,85 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_MEM2MEM_INSTANCE_ +#define _SAMG55_MEM2MEM_INSTANCE_ + +/* ========== Register definition for MEM2MEM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MEM2MEM_THR (0x40028000U) /**< \brief (MEM2MEM) Memory to Memory Transfer Holding Register */ +#define REG_MEM2MEM_MR (0x40028004U) /**< \brief (MEM2MEM) Memory to Memory Mode Register */ +#define REG_MEM2MEM_IER (0x40028008U) /**< \brief (MEM2MEM) Memory to Memory Interrupt Enable Register */ +#define REG_MEM2MEM_IDR (0x4002800CU) /**< \brief (MEM2MEM) Memory to Memory Interrupt Disable Register */ +#define REG_MEM2MEM_IMR (0x40028010U) /**< \brief (MEM2MEM) Memory to Memory Interrupt Mask Register */ +#define REG_MEM2MEM_ISR (0x40028014U) /**< \brief (MEM2MEM) Memory to Memory Interrupt Status Register */ +#define REG_MEM2MEM_RPR (0x40028100U) /**< \brief (MEM2MEM) Receive Pointer Register */ +#define REG_MEM2MEM_RCR (0x40028104U) /**< \brief (MEM2MEM) Receive Counter Register */ +#define REG_MEM2MEM_TPR (0x40028108U) /**< \brief (MEM2MEM) Transmit Pointer Register */ +#define REG_MEM2MEM_TCR (0x4002810CU) /**< \brief (MEM2MEM) Transmit Counter Register */ +#define REG_MEM2MEM_RNPR (0x40028110U) /**< \brief (MEM2MEM) Receive Next Pointer Register */ +#define REG_MEM2MEM_RNCR (0x40028114U) /**< \brief (MEM2MEM) Receive Next Counter Register */ +#define REG_MEM2MEM_TNPR (0x40028118U) /**< \brief (MEM2MEM) Transmit Next Pointer Register */ +#define REG_MEM2MEM_TNCR (0x4002811CU) /**< \brief (MEM2MEM) Transmit Next Counter Register */ +#define REG_MEM2MEM_PTCR (0x40028120U) /**< \brief (MEM2MEM) Transfer Control Register */ +#define REG_MEM2MEM_PTSR (0x40028124U) /**< \brief (MEM2MEM) Transfer Status Register */ +#else +#define REG_MEM2MEM_THR (*(__IO uint32_t*)0x40028000U) /**< \brief (MEM2MEM) Memory to Memory Transfer Holding Register */ +#define REG_MEM2MEM_MR (*(__IO uint32_t*)0x40028004U) /**< \brief (MEM2MEM) Memory to Memory Mode Register */ +#define REG_MEM2MEM_IER (*(__O uint32_t*)0x40028008U) /**< \brief (MEM2MEM) Memory to Memory Interrupt Enable Register */ +#define REG_MEM2MEM_IDR (*(__O uint32_t*)0x4002800CU) /**< \brief (MEM2MEM) Memory to Memory Interrupt Disable Register */ +#define REG_MEM2MEM_IMR (*(__I uint32_t*)0x40028010U) /**< \brief (MEM2MEM) Memory to Memory Interrupt Mask Register */ +#define REG_MEM2MEM_ISR (*(__I uint32_t*)0x40028014U) /**< \brief (MEM2MEM) Memory to Memory Interrupt Status Register */ +#define REG_MEM2MEM_RPR (*(__IO uint32_t*)0x40028100U) /**< \brief (MEM2MEM) Receive Pointer Register */ +#define REG_MEM2MEM_RCR (*(__IO uint32_t*)0x40028104U) /**< \brief (MEM2MEM) Receive Counter Register */ +#define REG_MEM2MEM_TPR (*(__IO uint32_t*)0x40028108U) /**< \brief (MEM2MEM) Transmit Pointer Register */ +#define REG_MEM2MEM_TCR (*(__IO uint32_t*)0x4002810CU) /**< \brief (MEM2MEM) Transmit Counter Register */ +#define REG_MEM2MEM_RNPR (*(__IO uint32_t*)0x40028110U) /**< \brief (MEM2MEM) Receive Next Pointer Register */ +#define REG_MEM2MEM_RNCR (*(__IO uint32_t*)0x40028114U) /**< \brief (MEM2MEM) Receive Next Counter Register */ +#define REG_MEM2MEM_TNPR (*(__IO uint32_t*)0x40028118U) /**< \brief (MEM2MEM) Transmit Next Pointer Register */ +#define REG_MEM2MEM_TNCR (*(__IO uint32_t*)0x4002811CU) /**< \brief (MEM2MEM) Transmit Next Counter Register */ +#define REG_MEM2MEM_PTCR (*(__O uint32_t*)0x40028120U) /**< \brief (MEM2MEM) Transfer Control Register */ +#define REG_MEM2MEM_PTSR (*(__I uint32_t*)0x40028124U) /**< \brief (MEM2MEM) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_MEM2MEM_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pdmic0.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,87 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_PDMIC0_INSTANCE_ +#define _SAMG55_PDMIC0_INSTANCE_ + +/* ========== Register definition for PDMIC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PDMIC0_CR (0x4002C000U) /**< \brief (PDMIC0) Control Register */ +#define REG_PDMIC0_MR (0x4002C004U) /**< \brief (PDMIC0) Mode Register */ +#define REG_PDMIC0_CDR (0x4002C014U) /**< \brief (PDMIC0) Converted Data Register */ +#define REG_PDMIC0_IER (0x4002C018U) /**< \brief (PDMIC0) Interrupt Enable Register */ +#define REG_PDMIC0_IDR (0x4002C01CU) /**< \brief (PDMIC0) Interrupt Disable Register */ +#define REG_PDMIC0_IMR (0x4002C020U) /**< \brief (PDMIC0) Interrupt Mask Register */ +#define REG_PDMIC0_ISR (0x4002C024U) /**< \brief (PDMIC0) Interrupt Status Register */ +#define REG_PDMIC0_DSPR0 (0x4002C058U) /**< \brief (PDMIC0) DSP Configuration Register 0 */ +#define REG_PDMIC0_DSPR1 (0x4002C05CU) /**< \brief (PDMIC0) DSP Configuration Register 1 */ +#define REG_PDMIC0_WPMR (0x4002C0E4U) /**< \brief (PDMIC0) Write Protection Mode Register */ +#define REG_PDMIC0_WPSR (0x4002C0E8U) /**< \brief (PDMIC0) Write Protection Status Register */ +#define REG_PDMIC0_RPR (0x4002C100U) /**< \brief (PDMIC0) Receive Pointer Register */ +#define REG_PDMIC0_RCR (0x4002C104U) /**< \brief (PDMIC0) Receive Counter Register */ +#define REG_PDMIC0_RNPR (0x4002C110U) /**< \brief (PDMIC0) Receive Next Pointer Register */ +#define REG_PDMIC0_RNCR (0x4002C114U) /**< \brief (PDMIC0) Receive Next Counter Register */ +#define REG_PDMIC0_PTCR (0x4002C120U) /**< \brief (PDMIC0) Transfer Control Register */ +#define REG_PDMIC0_PTSR (0x4002C124U) /**< \brief (PDMIC0) Transfer Status Register */ +#else +#define REG_PDMIC0_CR (*(__IO uint32_t*)0x4002C000U) /**< \brief (PDMIC0) Control Register */ +#define REG_PDMIC0_MR (*(__IO uint32_t*)0x4002C004U) /**< \brief (PDMIC0) Mode Register */ +#define REG_PDMIC0_CDR (*(__I uint32_t*)0x4002C014U) /**< \brief (PDMIC0) Converted Data Register */ +#define REG_PDMIC0_IER (*(__O uint32_t*)0x4002C018U) /**< \brief (PDMIC0) Interrupt Enable Register */ +#define REG_PDMIC0_IDR (*(__O uint32_t*)0x4002C01CU) /**< \brief (PDMIC0) Interrupt Disable Register */ +#define REG_PDMIC0_IMR (*(__I uint32_t*)0x4002C020U) /**< \brief (PDMIC0) Interrupt Mask Register */ +#define REG_PDMIC0_ISR (*(__I uint32_t*)0x4002C024U) /**< \brief (PDMIC0) Interrupt Status Register */ +#define REG_PDMIC0_DSPR0 (*(__IO uint32_t*)0x4002C058U) /**< \brief (PDMIC0) DSP Configuration Register 0 */ +#define REG_PDMIC0_DSPR1 (*(__IO uint32_t*)0x4002C05CU) /**< \brief (PDMIC0) DSP Configuration Register 1 */ +#define REG_PDMIC0_WPMR (*(__IO uint32_t*)0x4002C0E4U) /**< \brief (PDMIC0) Write Protection Mode Register */ +#define REG_PDMIC0_WPSR (*(__I uint32_t*)0x4002C0E8U) /**< \brief (PDMIC0) Write Protection Status Register */ +#define REG_PDMIC0_RPR (*(__IO uint32_t*)0x4002C100U) /**< \brief (PDMIC0) Receive Pointer Register */ +#define REG_PDMIC0_RCR (*(__IO uint32_t*)0x4002C104U) /**< \brief (PDMIC0) Receive Counter Register */ +#define REG_PDMIC0_RNPR (*(__IO uint32_t*)0x4002C110U) /**< \brief (PDMIC0) Receive Next Pointer Register */ +#define REG_PDMIC0_RNCR (*(__IO uint32_t*)0x4002C114U) /**< \brief (PDMIC0) Receive Next Counter Register */ +#define REG_PDMIC0_PTCR (*(__O uint32_t*)0x4002C120U) /**< \brief (PDMIC0) Transfer Control Register */ +#define REG_PDMIC0_PTSR (*(__I uint32_t*)0x4002C124U) /**< \brief (PDMIC0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_PDMIC0_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pdmic1.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,87 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_PDMIC1_INSTANCE_ +#define _SAMG55_PDMIC1_INSTANCE_ + +/* ========== Register definition for PDMIC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PDMIC1_CR (0x40030000U) /**< \brief (PDMIC1) Control Register */ +#define REG_PDMIC1_MR (0x40030004U) /**< \brief (PDMIC1) Mode Register */ +#define REG_PDMIC1_CDR (0x40030014U) /**< \brief (PDMIC1) Converted Data Register */ +#define REG_PDMIC1_IER (0x40030018U) /**< \brief (PDMIC1) Interrupt Enable Register */ +#define REG_PDMIC1_IDR (0x4003001CU) /**< \brief (PDMIC1) Interrupt Disable Register */ +#define REG_PDMIC1_IMR (0x40030020U) /**< \brief (PDMIC1) Interrupt Mask Register */ +#define REG_PDMIC1_ISR (0x40030024U) /**< \brief (PDMIC1) Interrupt Status Register */ +#define REG_PDMIC1_DSPR0 (0x40030058U) /**< \brief (PDMIC1) DSP Configuration Register 0 */ +#define REG_PDMIC1_DSPR1 (0x4003005CU) /**< \brief (PDMIC1) DSP Configuration Register 1 */ +#define REG_PDMIC1_WPMR (0x400300E4U) /**< \brief (PDMIC1) Write Protection Mode Register */ +#define REG_PDMIC1_WPSR (0x400300E8U) /**< \brief (PDMIC1) Write Protection Status Register */ +#define REG_PDMIC1_RPR (0x40030100U) /**< \brief (PDMIC1) Receive Pointer Register */ +#define REG_PDMIC1_RCR (0x40030104U) /**< \brief (PDMIC1) Receive Counter Register */ +#define REG_PDMIC1_RNPR (0x40030110U) /**< \brief (PDMIC1) Receive Next Pointer Register */ +#define REG_PDMIC1_RNCR (0x40030114U) /**< \brief (PDMIC1) Receive Next Counter Register */ +#define REG_PDMIC1_PTCR (0x40030120U) /**< \brief (PDMIC1) Transfer Control Register */ +#define REG_PDMIC1_PTSR (0x40030124U) /**< \brief (PDMIC1) Transfer Status Register */ +#else +#define REG_PDMIC1_CR (*(__IO uint32_t*)0x40030000U) /**< \brief (PDMIC1) Control Register */ +#define REG_PDMIC1_MR (*(__IO uint32_t*)0x40030004U) /**< \brief (PDMIC1) Mode Register */ +#define REG_PDMIC1_CDR (*(__I uint32_t*)0x40030014U) /**< \brief (PDMIC1) Converted Data Register */ +#define REG_PDMIC1_IER (*(__O uint32_t*)0x40030018U) /**< \brief (PDMIC1) Interrupt Enable Register */ +#define REG_PDMIC1_IDR (*(__O uint32_t*)0x4003001CU) /**< \brief (PDMIC1) Interrupt Disable Register */ +#define REG_PDMIC1_IMR (*(__I uint32_t*)0x40030020U) /**< \brief (PDMIC1) Interrupt Mask Register */ +#define REG_PDMIC1_ISR (*(__I uint32_t*)0x40030024U) /**< \brief (PDMIC1) Interrupt Status Register */ +#define REG_PDMIC1_DSPR0 (*(__IO uint32_t*)0x40030058U) /**< \brief (PDMIC1) DSP Configuration Register 0 */ +#define REG_PDMIC1_DSPR1 (*(__IO uint32_t*)0x4003005CU) /**< \brief (PDMIC1) DSP Configuration Register 1 */ +#define REG_PDMIC1_WPMR (*(__IO uint32_t*)0x400300E4U) /**< \brief (PDMIC1) Write Protection Mode Register */ +#define REG_PDMIC1_WPSR (*(__I uint32_t*)0x400300E8U) /**< \brief (PDMIC1) Write Protection Status Register */ +#define REG_PDMIC1_RPR (*(__IO uint32_t*)0x40030100U) /**< \brief (PDMIC1) Receive Pointer Register */ +#define REG_PDMIC1_RCR (*(__IO uint32_t*)0x40030104U) /**< \brief (PDMIC1) Receive Counter Register */ +#define REG_PDMIC1_RNPR (*(__IO uint32_t*)0x40030110U) /**< \brief (PDMIC1) Receive Next Pointer Register */ +#define REG_PDMIC1_RNCR (*(__IO uint32_t*)0x40030114U) /**< \brief (PDMIC1) Receive Next Counter Register */ +#define REG_PDMIC1_PTCR (*(__O uint32_t*)0x40030120U) /**< \brief (PDMIC1) Transfer Control Register */ +#define REG_PDMIC1_PTSR (*(__I uint32_t*)0x40030124U) /**< \brief (PDMIC1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_PDMIC1_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pioa.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,145 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_PIOA_INSTANCE_ +#define _SAMG55_PIOA_INSTANCE_ + +/* ========== Register definition for PIOA peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ +#define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ +#define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ +#define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */ +#define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ +#define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ +#define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ +#define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ +#define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ +#define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ +#define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ +#define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */ +#define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ +#define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ +#define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */ +#define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */ +#define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */ +#define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */ +#define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ +#else +#define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ +#define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ +#define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ +#define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */ +#define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ +#define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ +#define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ +#define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ +#define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ +#define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ +#define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ +#define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */ +#define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ +#define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ +#define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */ +#define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */ +#define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */ +#define REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */ +#define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_PIOA_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_piob.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,145 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_PIOB_INSTANCE_ +#define _SAMG55_PIOB_INSTANCE_ + +/* ========== Register definition for PIOB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */ +#define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */ +#define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */ +#define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */ +#define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ +#define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ +#define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ +#define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ +#define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ +#define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ +#define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ +#define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */ +#define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ +#define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */ +#define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */ +#define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */ +#define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */ +#define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */ +#define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ +#else +#define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */ +#define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */ +#define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */ +#define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) /**< \brief (PIOB) Output Status Register */ +#define REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ +#define REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ +#define REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ +#define REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ +#define REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ +#define REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ +#define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ +#define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */ +#define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ +#define REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */ +#define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */ +#define REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */ +#define REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */ +#define REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */ +#define REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_PIOB_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_pmc.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,111 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_PMC_INSTANCE_ +#define _SAMG55_PMC_INSTANCE_ + +/* ========== Register definition for PMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PMC_SCER (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR (0x400E0408U) /**< \brief (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ +#define REG_CKGR_MOR (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ +#define REG_CKGR_MCFR (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ +#define REG_CKGR_PLLAR (0x400E0428U) /**< \brief (PMC) PLLA Register */ +#define REG_CKGR_PLLBR (0x400E042CU) /**< \brief (PMC) PLLB Register */ +#define REG_PMC_MCKR (0x400E0430U) /**< \brief (PMC) Master Clock Register */ +#define REG_PMC_USB (0x400E0438U) /**< \brief (PMC) USB Clock Register */ +#define REG_PMC_PCK (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ +#define REG_PMC_IER (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ +#define REG_PMC_SR (0x400E0468U) /**< \brief (PMC) Status Register */ +#define REG_PMC_IMR (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ +#define REG_PMC_FSMR (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ +#define REG_PMC_FSPR (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ +#define REG_PMC_FOCR (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ +#define REG_PMC_WPMR (0x400E04E4U) /**< \brief (PMC) Write Protection Mode Register */ +#define REG_PMC_WPSR (0x400E04E8U) /**< \brief (PMC) Write Protection Status Register */ +#define REG_PMC_PCR (0x400E050CU) /**< \brief (PMC) Peripheral Control Register */ +#define REG_PMC_OCR (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ +#define REG_PMC_SLPWK_ER0 (0x400E0514U) /**< \brief (PMC) SleepWalking Enable Register 0 */ +#define REG_PMC_SLPWK_DR0 (0x400E0518U) /**< \brief (PMC) SleepWalking Disable Register 0 */ +#define REG_PMC_SLPWK_SR0 (0x400E051CU) /**< \brief (PMC) SleepWalking Status Register 0 */ +#define REG_PMC_SLPWK_ASR0 (0x400E0520U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */ +#define REG_PMC_PMMR (0x400E0530U) /**< \brief (PMC) PLL Maximum Multiplier Value Register */ +#else +#define REG_PMC_SCER (*(__O uint32_t*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR (*(__O uint32_t*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR (*(__I uint32_t*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ +#define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ +#define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ +#define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0428U) /**< \brief (PMC) PLLA Register */ +#define REG_CKGR_PLLBR (*(__IO uint32_t*)0x400E042CU) /**< \brief (PMC) PLLB Register */ +#define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0430U) /**< \brief (PMC) Master Clock Register */ +#define REG_PMC_USB (*(__IO uint32_t*)0x400E0438U) /**< \brief (PMC) USB Clock Register */ +#define REG_PMC_PCK (*(__IO uint32_t*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ +#define REG_PMC_IER (*(__O uint32_t*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR (*(__O uint32_t*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ +#define REG_PMC_SR (*(__I uint32_t*)0x400E0468U) /**< \brief (PMC) Status Register */ +#define REG_PMC_IMR (*(__I uint32_t*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ +#define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ +#define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ +#define REG_PMC_FOCR (*(__O uint32_t*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ +#define REG_PMC_WPMR (*(__IO uint32_t*)0x400E04E4U) /**< \brief (PMC) Write Protection Mode Register */ +#define REG_PMC_WPSR (*(__I uint32_t*)0x400E04E8U) /**< \brief (PMC) Write Protection Status Register */ +#define REG_PMC_PCR (*(__IO uint32_t*)0x400E050CU) /**< \brief (PMC) Peripheral Control Register */ +#define REG_PMC_OCR (*(__IO uint32_t*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ +#define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0514U) /**< \brief (PMC) SleepWalking Enable Register 0 */ +#define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0518U) /**< \brief (PMC) SleepWalking Disable Register 0 */ +#define REG_PMC_SLPWK_SR0 (*(__I uint32_t*)0x400E051CU) /**< \brief (PMC) SleepWalking Status Register 0 */ +#define REG_PMC_SLPWK_ASR0 (*(__I uint32_t*)0x400E0520U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */ +#define REG_PMC_PMMR (*(__IO uint32_t*)0x400E0530U) /**< \brief (PMC) PLL Maximum Multiplier Value Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_PMC_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_rstc.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,59 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_RSTC_INSTANCE_ +#define _SAMG55_RSTC_INSTANCE_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RSTC_CR (0x400E1400U) /**< \brief (RSTC) Control Register */ +#define REG_RSTC_SR (0x400E1404U) /**< \brief (RSTC) Status Register */ +#define REG_RSTC_MR (0x400E1408U) /**< \brief (RSTC) Mode Register */ +#else +#define REG_RSTC_CR (*(__O uint32_t*)0x400E1400U) /**< \brief (RSTC) Control Register */ +#define REG_RSTC_SR (*(__I uint32_t*)0x400E1404U) /**< \brief (RSTC) Status Register */ +#define REG_RSTC_MR (*(__IO uint32_t*)0x400E1408U) /**< \brief (RSTC) Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_RSTC_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_rtc.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,81 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_RTC_INSTANCE_ +#define _SAMG55_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTC_CR (0x400E1460U) /**< \brief (RTC) Control Register */ +#define REG_RTC_MR (0x400E1464U) /**< \brief (RTC) Mode Register */ +#define REG_RTC_TIMR (0x400E1468U) /**< \brief (RTC) Time Register */ +#define REG_RTC_CALR (0x400E146CU) /**< \brief (RTC) Calendar Register */ +#define REG_RTC_TIMALR (0x400E1470U) /**< \brief (RTC) Time Alarm Register */ +#define REG_RTC_CALALR (0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ +#define REG_RTC_SR (0x400E1478U) /**< \brief (RTC) Status Register */ +#define REG_RTC_SCCR (0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ +#define REG_RTC_IER (0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR (0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR (0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ +#define REG_RTC_VER (0x400E148CU) /**< \brief (RTC) Valid Entry Register */ +#define REG_RTC_MSR (0x400E1530U) /**< \brief (RTC) Milliseconds Register */ +#define REG_RTC_WPMR (0x400E1544U) /**< \brief (RTC) Write Protection Mode Register */ +#else +#define REG_RTC_CR (*(__IO uint32_t*)0x400E1460U) /**< \brief (RTC) Control Register */ +#define REG_RTC_MR (*(__IO uint32_t*)0x400E1464U) /**< \brief (RTC) Mode Register */ +#define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1468U) /**< \brief (RTC) Time Register */ +#define REG_RTC_CALR (*(__IO uint32_t*)0x400E146CU) /**< \brief (RTC) Calendar Register */ +#define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1470U) /**< \brief (RTC) Time Alarm Register */ +#define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ +#define REG_RTC_SR (*(__I uint32_t*)0x400E1478U) /**< \brief (RTC) Status Register */ +#define REG_RTC_SCCR (*(__O uint32_t*)0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ +#define REG_RTC_IER (*(__O uint32_t*)0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR (*(__O uint32_t*)0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR (*(__I uint32_t*)0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ +#define REG_RTC_VER (*(__I uint32_t*)0x400E148CU) /**< \brief (RTC) Valid Entry Register */ +#define REG_RTC_MSR (*(__I uint32_t*)0x400E1530U) /**< \brief (RTC) Milliseconds Register */ +#define REG_RTC_WPMR (*(__IO uint32_t*)0x400E1544U) /**< \brief (RTC) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_RTC_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_rtt.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,63 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_RTT_INSTANCE_ +#define _SAMG55_RTT_INSTANCE_ + +/* ========== Register definition for RTT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTT_MR (0x400E1430U) /**< \brief (RTT) Mode Register */ +#define REG_RTT_AR (0x400E1434U) /**< \brief (RTT) Alarm Register */ +#define REG_RTT_VR (0x400E1438U) /**< \brief (RTT) Value Register */ +#define REG_RTT_SR (0x400E143CU) /**< \brief (RTT) Status Register */ +#define REG_RTT_MODR (0x400E1440U) /**< \brief (RTT) Modulo Selection Register */ +#else +#define REG_RTT_MR (*(__IO uint32_t*)0x400E1430U) /**< \brief (RTT) Mode Register */ +#define REG_RTT_AR (*(__IO uint32_t*)0x400E1434U) /**< \brief (RTT) Alarm Register */ +#define REG_RTT_VR (*(__I uint32_t*)0x400E1438U) /**< \brief (RTT) Value Register */ +#define REG_RTT_SR (*(__I uint32_t*)0x400E143CU) /**< \brief (RTT) Status Register */ +#define REG_RTT_MODR (*(__IO uint32_t*)0x400E1440U) /**< \brief (RTT) Modulo Selection Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_RTT_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi0.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,97 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_SPI0_INSTANCE_ +#define _SAMG55_SPI0_INSTANCE_ + +/* ========== Register definition for SPI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI0_CR (0x4000C400U) /**< \brief (SPI0) SPI Control Register */ +#define REG_SPI0_MR (0x4000C404U) /**< \brief (SPI0) SPI Mode Register */ +#define REG_SPI0_RDR (0x4000C408U) /**< \brief (SPI0) SPI Receive Data Register */ +#define REG_SPI0_TDR (0x4000C40CU) /**< \brief (SPI0) SPI Transmit Data Register */ +#define REG_SPI0_SR (0x4000C410U) /**< \brief (SPI0) SPI Status Register */ +#define REG_SPI0_IER (0x4000C414U) /**< \brief (SPI0) SPI Interrupt Enable Register */ +#define REG_SPI0_IDR (0x4000C418U) /**< \brief (SPI0) SPI Interrupt Disable Register */ +#define REG_SPI0_IMR (0x4000C41CU) /**< \brief (SPI0) SPI Interrupt Mask Register */ +#define REG_SPI0_CSR (0x4000C430U) /**< \brief (SPI0) SPI Chip Select Register */ +#define REG_SPI0_CMPR (0x4000C448U) /**< \brief (SPI0) SPI Comparison Register */ +#define REG_SPI0_WPMR (0x4000C4E4U) /**< \brief (SPI0) SPI Write Protection Mode Register */ +#define REG_SPI0_WPSR (0x4000C4E8U) /**< \brief (SPI0) SPI Write Protection Status Register */ +#define REG_SPI0_RPR (0x4000C500U) /**< \brief (SPI0) Receive Pointer Register */ +#define REG_SPI0_RCR (0x4000C504U) /**< \brief (SPI0) Receive Counter Register */ +#define REG_SPI0_TPR (0x4000C508U) /**< \brief (SPI0) Transmit Pointer Register */ +#define REG_SPI0_TCR (0x4000C50CU) /**< \brief (SPI0) Transmit Counter Register */ +#define REG_SPI0_RNPR (0x4000C510U) /**< \brief (SPI0) Receive Next Pointer Register */ +#define REG_SPI0_RNCR (0x4000C514U) /**< \brief (SPI0) Receive Next Counter Register */ +#define REG_SPI0_TNPR (0x4000C518U) /**< \brief (SPI0) Transmit Next Pointer Register */ +#define REG_SPI0_TNCR (0x4000C51CU) /**< \brief (SPI0) Transmit Next Counter Register */ +#define REG_SPI0_PTCR (0x4000C520U) /**< \brief (SPI0) Transfer Control Register */ +#define REG_SPI0_PTSR (0x4000C524U) /**< \brief (SPI0) Transfer Status Register */ +#else +#define REG_SPI0_CR (*(__O uint32_t*)0x4000C400U) /**< \brief (SPI0) SPI Control Register */ +#define REG_SPI0_MR (*(__IO uint32_t*)0x4000C404U) /**< \brief (SPI0) SPI Mode Register */ +#define REG_SPI0_RDR (*(__I uint32_t*)0x4000C408U) /**< \brief (SPI0) SPI Receive Data Register */ +#define REG_SPI0_TDR (*(__O uint32_t*)0x4000C40CU) /**< \brief (SPI0) SPI Transmit Data Register */ +#define REG_SPI0_SR (*(__I uint32_t*)0x4000C410U) /**< \brief (SPI0) SPI Status Register */ +#define REG_SPI0_IER (*(__O uint32_t*)0x4000C414U) /**< \brief (SPI0) SPI Interrupt Enable Register */ +#define REG_SPI0_IDR (*(__O uint32_t*)0x4000C418U) /**< \brief (SPI0) SPI Interrupt Disable Register */ +#define REG_SPI0_IMR (*(__I uint32_t*)0x4000C41CU) /**< \brief (SPI0) SPI Interrupt Mask Register */ +#define REG_SPI0_CSR (*(__IO uint32_t*)0x4000C430U) /**< \brief (SPI0) SPI Chip Select Register */ +#define REG_SPI0_CMPR (*(__IO uint32_t*)0x4000C448U) /**< \brief (SPI0) SPI Comparison Register */ +#define REG_SPI0_WPMR (*(__IO uint32_t*)0x4000C4E4U) /**< \brief (SPI0) SPI Write Protection Mode Register */ +#define REG_SPI0_WPSR (*(__I uint32_t*)0x4000C4E8U) /**< \brief (SPI0) SPI Write Protection Status Register */ +#define REG_SPI0_RPR (*(__IO uint32_t*)0x4000C500U) /**< \brief (SPI0) Receive Pointer Register */ +#define REG_SPI0_RCR (*(__IO uint32_t*)0x4000C504U) /**< \brief (SPI0) Receive Counter Register */ +#define REG_SPI0_TPR (*(__IO uint32_t*)0x4000C508U) /**< \brief (SPI0) Transmit Pointer Register */ +#define REG_SPI0_TCR (*(__IO uint32_t*)0x4000C50CU) /**< \brief (SPI0) Transmit Counter Register */ +#define REG_SPI0_RNPR (*(__IO uint32_t*)0x4000C510U) /**< \brief (SPI0) Receive Next Pointer Register */ +#define REG_SPI0_RNCR (*(__IO uint32_t*)0x4000C514U) /**< \brief (SPI0) Receive Next Counter Register */ +#define REG_SPI0_TNPR (*(__IO uint32_t*)0x4000C518U) /**< \brief (SPI0) Transmit Next Pointer Register */ +#define REG_SPI0_TNCR (*(__IO uint32_t*)0x4000C51CU) /**< \brief (SPI0) Transmit Next Counter Register */ +#define REG_SPI0_PTCR (*(__O uint32_t*)0x4000C520U) /**< \brief (SPI0) Transfer Control Register */ +#define REG_SPI0_PTSR (*(__I uint32_t*)0x4000C524U) /**< \brief (SPI0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_SPI0_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi1.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,97 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_SPI1_INSTANCE_ +#define _SAMG55_SPI1_INSTANCE_ + +/* ========== Register definition for SPI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI1_CR (0x40020400U) /**< \brief (SPI1) SPI Control Register */ +#define REG_SPI1_MR (0x40020404U) /**< \brief (SPI1) SPI Mode Register */ +#define REG_SPI1_RDR (0x40020408U) /**< \brief (SPI1) SPI Receive Data Register */ +#define REG_SPI1_TDR (0x4002040CU) /**< \brief (SPI1) SPI Transmit Data Register */ +#define REG_SPI1_SR (0x40020410U) /**< \brief (SPI1) SPI Status Register */ +#define REG_SPI1_IER (0x40020414U) /**< \brief (SPI1) SPI Interrupt Enable Register */ +#define REG_SPI1_IDR (0x40020418U) /**< \brief (SPI1) SPI Interrupt Disable Register */ +#define REG_SPI1_IMR (0x4002041CU) /**< \brief (SPI1) SPI Interrupt Mask Register */ +#define REG_SPI1_CSR (0x40020430U) /**< \brief (SPI1) SPI Chip Select Register */ +#define REG_SPI1_CMPR (0x40020448U) /**< \brief (SPI1) SPI Comparison Register */ +#define REG_SPI1_WPMR (0x400204E4U) /**< \brief (SPI1) SPI Write Protection Mode Register */ +#define REG_SPI1_WPSR (0x400204E8U) /**< \brief (SPI1) SPI Write Protection Status Register */ +#define REG_SPI1_RPR (0x40020500U) /**< \brief (SPI1) Receive Pointer Register */ +#define REG_SPI1_RCR (0x40020504U) /**< \brief (SPI1) Receive Counter Register */ +#define REG_SPI1_TPR (0x40020508U) /**< \brief (SPI1) Transmit Pointer Register */ +#define REG_SPI1_TCR (0x4002050CU) /**< \brief (SPI1) Transmit Counter Register */ +#define REG_SPI1_RNPR (0x40020510U) /**< \brief (SPI1) Receive Next Pointer Register */ +#define REG_SPI1_RNCR (0x40020514U) /**< \brief (SPI1) Receive Next Counter Register */ +#define REG_SPI1_TNPR (0x40020518U) /**< \brief (SPI1) Transmit Next Pointer Register */ +#define REG_SPI1_TNCR (0x4002051CU) /**< \brief (SPI1) Transmit Next Counter Register */ +#define REG_SPI1_PTCR (0x40020520U) /**< \brief (SPI1) Transfer Control Register */ +#define REG_SPI1_PTSR (0x40020524U) /**< \brief (SPI1) Transfer Status Register */ +#else +#define REG_SPI1_CR (*(__O uint32_t*)0x40020400U) /**< \brief (SPI1) SPI Control Register */ +#define REG_SPI1_MR (*(__IO uint32_t*)0x40020404U) /**< \brief (SPI1) SPI Mode Register */ +#define REG_SPI1_RDR (*(__I uint32_t*)0x40020408U) /**< \brief (SPI1) SPI Receive Data Register */ +#define REG_SPI1_TDR (*(__O uint32_t*)0x4002040CU) /**< \brief (SPI1) SPI Transmit Data Register */ +#define REG_SPI1_SR (*(__I uint32_t*)0x40020410U) /**< \brief (SPI1) SPI Status Register */ +#define REG_SPI1_IER (*(__O uint32_t*)0x40020414U) /**< \brief (SPI1) SPI Interrupt Enable Register */ +#define REG_SPI1_IDR (*(__O uint32_t*)0x40020418U) /**< \brief (SPI1) SPI Interrupt Disable Register */ +#define REG_SPI1_IMR (*(__I uint32_t*)0x4002041CU) /**< \brief (SPI1) SPI Interrupt Mask Register */ +#define REG_SPI1_CSR (*(__IO uint32_t*)0x40020430U) /**< \brief (SPI1) SPI Chip Select Register */ +#define REG_SPI1_CMPR (*(__IO uint32_t*)0x40020448U) /**< \brief (SPI1) SPI Comparison Register */ +#define REG_SPI1_WPMR (*(__IO uint32_t*)0x400204E4U) /**< \brief (SPI1) SPI Write Protection Mode Register */ +#define REG_SPI1_WPSR (*(__I uint32_t*)0x400204E8U) /**< \brief (SPI1) SPI Write Protection Status Register */ +#define REG_SPI1_RPR (*(__IO uint32_t*)0x40020500U) /**< \brief (SPI1) Receive Pointer Register */ +#define REG_SPI1_RCR (*(__IO uint32_t*)0x40020504U) /**< \brief (SPI1) Receive Counter Register */ +#define REG_SPI1_TPR (*(__IO uint32_t*)0x40020508U) /**< \brief (SPI1) Transmit Pointer Register */ +#define REG_SPI1_TCR (*(__IO uint32_t*)0x4002050CU) /**< \brief (SPI1) Transmit Counter Register */ +#define REG_SPI1_RNPR (*(__IO uint32_t*)0x40020510U) /**< \brief (SPI1) Receive Next Pointer Register */ +#define REG_SPI1_RNCR (*(__IO uint32_t*)0x40020514U) /**< \brief (SPI1) Receive Next Counter Register */ +#define REG_SPI1_TNPR (*(__IO uint32_t*)0x40020518U) /**< \brief (SPI1) Transmit Next Pointer Register */ +#define REG_SPI1_TNCR (*(__IO uint32_t*)0x4002051CU) /**< \brief (SPI1) Transmit Next Counter Register */ +#define REG_SPI1_PTCR (*(__O uint32_t*)0x40020520U) /**< \brief (SPI1) Transfer Control Register */ +#define REG_SPI1_PTSR (*(__I uint32_t*)0x40020524U) /**< \brief (SPI1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_SPI1_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi2.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,97 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_SPI2_INSTANCE_ +#define _SAMG55_SPI2_INSTANCE_ + +/* ========== Register definition for SPI2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI2_CR (0x40024400U) /**< \brief (SPI2) SPI Control Register */ +#define REG_SPI2_MR (0x40024404U) /**< \brief (SPI2) SPI Mode Register */ +#define REG_SPI2_RDR (0x40024408U) /**< \brief (SPI2) SPI Receive Data Register */ +#define REG_SPI2_TDR (0x4002440CU) /**< \brief (SPI2) SPI Transmit Data Register */ +#define REG_SPI2_SR (0x40024410U) /**< \brief (SPI2) SPI Status Register */ +#define REG_SPI2_IER (0x40024414U) /**< \brief (SPI2) SPI Interrupt Enable Register */ +#define REG_SPI2_IDR (0x40024418U) /**< \brief (SPI2) SPI Interrupt Disable Register */ +#define REG_SPI2_IMR (0x4002441CU) /**< \brief (SPI2) SPI Interrupt Mask Register */ +#define REG_SPI2_CSR (0x40024430U) /**< \brief (SPI2) SPI Chip Select Register */ +#define REG_SPI2_CMPR (0x40024448U) /**< \brief (SPI2) SPI Comparison Register */ +#define REG_SPI2_WPMR (0x400244E4U) /**< \brief (SPI2) SPI Write Protection Mode Register */ +#define REG_SPI2_WPSR (0x400244E8U) /**< \brief (SPI2) SPI Write Protection Status Register */ +#define REG_SPI2_RPR (0x40024500U) /**< \brief (SPI2) Receive Pointer Register */ +#define REG_SPI2_RCR (0x40024504U) /**< \brief (SPI2) Receive Counter Register */ +#define REG_SPI2_TPR (0x40024508U) /**< \brief (SPI2) Transmit Pointer Register */ +#define REG_SPI2_TCR (0x4002450CU) /**< \brief (SPI2) Transmit Counter Register */ +#define REG_SPI2_RNPR (0x40024510U) /**< \brief (SPI2) Receive Next Pointer Register */ +#define REG_SPI2_RNCR (0x40024514U) /**< \brief (SPI2) Receive Next Counter Register */ +#define REG_SPI2_TNPR (0x40024518U) /**< \brief (SPI2) Transmit Next Pointer Register */ +#define REG_SPI2_TNCR (0x4002451CU) /**< \brief (SPI2) Transmit Next Counter Register */ +#define REG_SPI2_PTCR (0x40024520U) /**< \brief (SPI2) Transfer Control Register */ +#define REG_SPI2_PTSR (0x40024524U) /**< \brief (SPI2) Transfer Status Register */ +#else +#define REG_SPI2_CR (*(__O uint32_t*)0x40024400U) /**< \brief (SPI2) SPI Control Register */ +#define REG_SPI2_MR (*(__IO uint32_t*)0x40024404U) /**< \brief (SPI2) SPI Mode Register */ +#define REG_SPI2_RDR (*(__I uint32_t*)0x40024408U) /**< \brief (SPI2) SPI Receive Data Register */ +#define REG_SPI2_TDR (*(__O uint32_t*)0x4002440CU) /**< \brief (SPI2) SPI Transmit Data Register */ +#define REG_SPI2_SR (*(__I uint32_t*)0x40024410U) /**< \brief (SPI2) SPI Status Register */ +#define REG_SPI2_IER (*(__O uint32_t*)0x40024414U) /**< \brief (SPI2) SPI Interrupt Enable Register */ +#define REG_SPI2_IDR (*(__O uint32_t*)0x40024418U) /**< \brief (SPI2) SPI Interrupt Disable Register */ +#define REG_SPI2_IMR (*(__I uint32_t*)0x4002441CU) /**< \brief (SPI2) SPI Interrupt Mask Register */ +#define REG_SPI2_CSR (*(__IO uint32_t*)0x40024430U) /**< \brief (SPI2) SPI Chip Select Register */ +#define REG_SPI2_CMPR (*(__IO uint32_t*)0x40024448U) /**< \brief (SPI2) SPI Comparison Register */ +#define REG_SPI2_WPMR (*(__IO uint32_t*)0x400244E4U) /**< \brief (SPI2) SPI Write Protection Mode Register */ +#define REG_SPI2_WPSR (*(__I uint32_t*)0x400244E8U) /**< \brief (SPI2) SPI Write Protection Status Register */ +#define REG_SPI2_RPR (*(__IO uint32_t*)0x40024500U) /**< \brief (SPI2) Receive Pointer Register */ +#define REG_SPI2_RCR (*(__IO uint32_t*)0x40024504U) /**< \brief (SPI2) Receive Counter Register */ +#define REG_SPI2_TPR (*(__IO uint32_t*)0x40024508U) /**< \brief (SPI2) Transmit Pointer Register */ +#define REG_SPI2_TCR (*(__IO uint32_t*)0x4002450CU) /**< \brief (SPI2) Transmit Counter Register */ +#define REG_SPI2_RNPR (*(__IO uint32_t*)0x40024510U) /**< \brief (SPI2) Receive Next Pointer Register */ +#define REG_SPI2_RNCR (*(__IO uint32_t*)0x40024514U) /**< \brief (SPI2) Receive Next Counter Register */ +#define REG_SPI2_TNPR (*(__IO uint32_t*)0x40024518U) /**< \brief (SPI2) Transmit Next Pointer Register */ +#define REG_SPI2_TNCR (*(__IO uint32_t*)0x4002451CU) /**< \brief (SPI2) Transmit Next Counter Register */ +#define REG_SPI2_PTCR (*(__O uint32_t*)0x40024520U) /**< \brief (SPI2) Transfer Control Register */ +#define REG_SPI2_PTSR (*(__I uint32_t*)0x40024524U) /**< \brief (SPI2) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_SPI2_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi3.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,97 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_SPI3_INSTANCE_ +#define _SAMG55_SPI3_INSTANCE_ + +/* ========== Register definition for SPI3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI3_CR (0x40018400U) /**< \brief (SPI3) SPI Control Register */ +#define REG_SPI3_MR (0x40018404U) /**< \brief (SPI3) SPI Mode Register */ +#define REG_SPI3_RDR (0x40018408U) /**< \brief (SPI3) SPI Receive Data Register */ +#define REG_SPI3_TDR (0x4001840CU) /**< \brief (SPI3) SPI Transmit Data Register */ +#define REG_SPI3_SR (0x40018410U) /**< \brief (SPI3) SPI Status Register */ +#define REG_SPI3_IER (0x40018414U) /**< \brief (SPI3) SPI Interrupt Enable Register */ +#define REG_SPI3_IDR (0x40018418U) /**< \brief (SPI3) SPI Interrupt Disable Register */ +#define REG_SPI3_IMR (0x4001841CU) /**< \brief (SPI3) SPI Interrupt Mask Register */ +#define REG_SPI3_CSR (0x40018430U) /**< \brief (SPI3) SPI Chip Select Register */ +#define REG_SPI3_CMPR (0x40018448U) /**< \brief (SPI3) SPI Comparison Register */ +#define REG_SPI3_WPMR (0x400184E4U) /**< \brief (SPI3) SPI Write Protection Mode Register */ +#define REG_SPI3_WPSR (0x400184E8U) /**< \brief (SPI3) SPI Write Protection Status Register */ +#define REG_SPI3_RPR (0x40018500U) /**< \brief (SPI3) Receive Pointer Register */ +#define REG_SPI3_RCR (0x40018504U) /**< \brief (SPI3) Receive Counter Register */ +#define REG_SPI3_TPR (0x40018508U) /**< \brief (SPI3) Transmit Pointer Register */ +#define REG_SPI3_TCR (0x4001850CU) /**< \brief (SPI3) Transmit Counter Register */ +#define REG_SPI3_RNPR (0x40018510U) /**< \brief (SPI3) Receive Next Pointer Register */ +#define REG_SPI3_RNCR (0x40018514U) /**< \brief (SPI3) Receive Next Counter Register */ +#define REG_SPI3_TNPR (0x40018518U) /**< \brief (SPI3) Transmit Next Pointer Register */ +#define REG_SPI3_TNCR (0x4001851CU) /**< \brief (SPI3) Transmit Next Counter Register */ +#define REG_SPI3_PTCR (0x40018520U) /**< \brief (SPI3) Transfer Control Register */ +#define REG_SPI3_PTSR (0x40018524U) /**< \brief (SPI3) Transfer Status Register */ +#else +#define REG_SPI3_CR (*(__O uint32_t*)0x40018400U) /**< \brief (SPI3) SPI Control Register */ +#define REG_SPI3_MR (*(__IO uint32_t*)0x40018404U) /**< \brief (SPI3) SPI Mode Register */ +#define REG_SPI3_RDR (*(__I uint32_t*)0x40018408U) /**< \brief (SPI3) SPI Receive Data Register */ +#define REG_SPI3_TDR (*(__O uint32_t*)0x4001840CU) /**< \brief (SPI3) SPI Transmit Data Register */ +#define REG_SPI3_SR (*(__I uint32_t*)0x40018410U) /**< \brief (SPI3) SPI Status Register */ +#define REG_SPI3_IER (*(__O uint32_t*)0x40018414U) /**< \brief (SPI3) SPI Interrupt Enable Register */ +#define REG_SPI3_IDR (*(__O uint32_t*)0x40018418U) /**< \brief (SPI3) SPI Interrupt Disable Register */ +#define REG_SPI3_IMR (*(__I uint32_t*)0x4001841CU) /**< \brief (SPI3) SPI Interrupt Mask Register */ +#define REG_SPI3_CSR (*(__IO uint32_t*)0x40018430U) /**< \brief (SPI3) SPI Chip Select Register */ +#define REG_SPI3_CMPR (*(__IO uint32_t*)0x40018448U) /**< \brief (SPI3) SPI Comparison Register */ +#define REG_SPI3_WPMR (*(__IO uint32_t*)0x400184E4U) /**< \brief (SPI3) SPI Write Protection Mode Register */ +#define REG_SPI3_WPSR (*(__I uint32_t*)0x400184E8U) /**< \brief (SPI3) SPI Write Protection Status Register */ +#define REG_SPI3_RPR (*(__IO uint32_t*)0x40018500U) /**< \brief (SPI3) Receive Pointer Register */ +#define REG_SPI3_RCR (*(__IO uint32_t*)0x40018504U) /**< \brief (SPI3) Receive Counter Register */ +#define REG_SPI3_TPR (*(__IO uint32_t*)0x40018508U) /**< \brief (SPI3) Transmit Pointer Register */ +#define REG_SPI3_TCR (*(__IO uint32_t*)0x4001850CU) /**< \brief (SPI3) Transmit Counter Register */ +#define REG_SPI3_RNPR (*(__IO uint32_t*)0x40018510U) /**< \brief (SPI3) Receive Next Pointer Register */ +#define REG_SPI3_RNCR (*(__IO uint32_t*)0x40018514U) /**< \brief (SPI3) Receive Next Counter Register */ +#define REG_SPI3_TNPR (*(__IO uint32_t*)0x40018518U) /**< \brief (SPI3) Transmit Next Pointer Register */ +#define REG_SPI3_TNCR (*(__IO uint32_t*)0x4001851CU) /**< \brief (SPI3) Transmit Next Counter Register */ +#define REG_SPI3_PTCR (*(__O uint32_t*)0x40018520U) /**< \brief (SPI3) Transfer Control Register */ +#define REG_SPI3_PTSR (*(__I uint32_t*)0x40018524U) /**< \brief (SPI3) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_SPI3_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi4.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,97 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_SPI4_INSTANCE_ +#define _SAMG55_SPI4_INSTANCE_ + +/* ========== Register definition for SPI4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI4_CR (0x4001C400U) /**< \brief (SPI4) SPI Control Register */ +#define REG_SPI4_MR (0x4001C404U) /**< \brief (SPI4) SPI Mode Register */ +#define REG_SPI4_RDR (0x4001C408U) /**< \brief (SPI4) SPI Receive Data Register */ +#define REG_SPI4_TDR (0x4001C40CU) /**< \brief (SPI4) SPI Transmit Data Register */ +#define REG_SPI4_SR (0x4001C410U) /**< \brief (SPI4) SPI Status Register */ +#define REG_SPI4_IER (0x4001C414U) /**< \brief (SPI4) SPI Interrupt Enable Register */ +#define REG_SPI4_IDR (0x4001C418U) /**< \brief (SPI4) SPI Interrupt Disable Register */ +#define REG_SPI4_IMR (0x4001C41CU) /**< \brief (SPI4) SPI Interrupt Mask Register */ +#define REG_SPI4_CSR (0x4001C430U) /**< \brief (SPI4) SPI Chip Select Register */ +#define REG_SPI4_CMPR (0x4001C448U) /**< \brief (SPI4) SPI Comparison Register */ +#define REG_SPI4_WPMR (0x4001C4E4U) /**< \brief (SPI4) SPI Write Protection Mode Register */ +#define REG_SPI4_WPSR (0x4001C4E8U) /**< \brief (SPI4) SPI Write Protection Status Register */ +#define REG_SPI4_RPR (0x4001C500U) /**< \brief (SPI4) Receive Pointer Register */ +#define REG_SPI4_RCR (0x4001C504U) /**< \brief (SPI4) Receive Counter Register */ +#define REG_SPI4_TPR (0x4001C508U) /**< \brief (SPI4) Transmit Pointer Register */ +#define REG_SPI4_TCR (0x4001C50CU) /**< \brief (SPI4) Transmit Counter Register */ +#define REG_SPI4_RNPR (0x4001C510U) /**< \brief (SPI4) Receive Next Pointer Register */ +#define REG_SPI4_RNCR (0x4001C514U) /**< \brief (SPI4) Receive Next Counter Register */ +#define REG_SPI4_TNPR (0x4001C518U) /**< \brief (SPI4) Transmit Next Pointer Register */ +#define REG_SPI4_TNCR (0x4001C51CU) /**< \brief (SPI4) Transmit Next Counter Register */ +#define REG_SPI4_PTCR (0x4001C520U) /**< \brief (SPI4) Transfer Control Register */ +#define REG_SPI4_PTSR (0x4001C524U) /**< \brief (SPI4) Transfer Status Register */ +#else +#define REG_SPI4_CR (*(__O uint32_t*)0x4001C400U) /**< \brief (SPI4) SPI Control Register */ +#define REG_SPI4_MR (*(__IO uint32_t*)0x4001C404U) /**< \brief (SPI4) SPI Mode Register */ +#define REG_SPI4_RDR (*(__I uint32_t*)0x4001C408U) /**< \brief (SPI4) SPI Receive Data Register */ +#define REG_SPI4_TDR (*(__O uint32_t*)0x4001C40CU) /**< \brief (SPI4) SPI Transmit Data Register */ +#define REG_SPI4_SR (*(__I uint32_t*)0x4001C410U) /**< \brief (SPI4) SPI Status Register */ +#define REG_SPI4_IER (*(__O uint32_t*)0x4001C414U) /**< \brief (SPI4) SPI Interrupt Enable Register */ +#define REG_SPI4_IDR (*(__O uint32_t*)0x4001C418U) /**< \brief (SPI4) SPI Interrupt Disable Register */ +#define REG_SPI4_IMR (*(__I uint32_t*)0x4001C41CU) /**< \brief (SPI4) SPI Interrupt Mask Register */ +#define REG_SPI4_CSR (*(__IO uint32_t*)0x4001C430U) /**< \brief (SPI4) SPI Chip Select Register */ +#define REG_SPI4_CMPR (*(__IO uint32_t*)0x4001C448U) /**< \brief (SPI4) SPI Comparison Register */ +#define REG_SPI4_WPMR (*(__IO uint32_t*)0x4001C4E4U) /**< \brief (SPI4) SPI Write Protection Mode Register */ +#define REG_SPI4_WPSR (*(__I uint32_t*)0x4001C4E8U) /**< \brief (SPI4) SPI Write Protection Status Register */ +#define REG_SPI4_RPR (*(__IO uint32_t*)0x4001C500U) /**< \brief (SPI4) Receive Pointer Register */ +#define REG_SPI4_RCR (*(__IO uint32_t*)0x4001C504U) /**< \brief (SPI4) Receive Counter Register */ +#define REG_SPI4_TPR (*(__IO uint32_t*)0x4001C508U) /**< \brief (SPI4) Transmit Pointer Register */ +#define REG_SPI4_TCR (*(__IO uint32_t*)0x4001C50CU) /**< \brief (SPI4) Transmit Counter Register */ +#define REG_SPI4_RNPR (*(__IO uint32_t*)0x4001C510U) /**< \brief (SPI4) Receive Next Pointer Register */ +#define REG_SPI4_RNCR (*(__IO uint32_t*)0x4001C514U) /**< \brief (SPI4) Receive Next Counter Register */ +#define REG_SPI4_TNPR (*(__IO uint32_t*)0x4001C518U) /**< \brief (SPI4) Transmit Next Pointer Register */ +#define REG_SPI4_TNCR (*(__IO uint32_t*)0x4001C51CU) /**< \brief (SPI4) Transmit Next Counter Register */ +#define REG_SPI4_PTCR (*(__O uint32_t*)0x4001C520U) /**< \brief (SPI4) Transfer Control Register */ +#define REG_SPI4_PTSR (*(__I uint32_t*)0x4001C524U) /**< \brief (SPI4) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_SPI4_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi5.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,97 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_SPI5_INSTANCE_ +#define _SAMG55_SPI5_INSTANCE_ + +/* ========== Register definition for SPI5 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI5_CR (0x40008400U) /**< \brief (SPI5) SPI Control Register */ +#define REG_SPI5_MR (0x40008404U) /**< \brief (SPI5) SPI Mode Register */ +#define REG_SPI5_RDR (0x40008408U) /**< \brief (SPI5) SPI Receive Data Register */ +#define REG_SPI5_TDR (0x4000840CU) /**< \brief (SPI5) SPI Transmit Data Register */ +#define REG_SPI5_SR (0x40008410U) /**< \brief (SPI5) SPI Status Register */ +#define REG_SPI5_IER (0x40008414U) /**< \brief (SPI5) SPI Interrupt Enable Register */ +#define REG_SPI5_IDR (0x40008418U) /**< \brief (SPI5) SPI Interrupt Disable Register */ +#define REG_SPI5_IMR (0x4000841CU) /**< \brief (SPI5) SPI Interrupt Mask Register */ +#define REG_SPI5_CSR (0x40008430U) /**< \brief (SPI5) SPI Chip Select Register */ +#define REG_SPI5_CMPR (0x40008448U) /**< \brief (SPI5) SPI Comparison Register */ +#define REG_SPI5_WPMR (0x400084E4U) /**< \brief (SPI5) SPI Write Protection Mode Register */ +#define REG_SPI5_WPSR (0x400084E8U) /**< \brief (SPI5) SPI Write Protection Status Register */ +#define REG_SPI5_RPR (0x40008500U) /**< \brief (SPI5) Receive Pointer Register */ +#define REG_SPI5_RCR (0x40008504U) /**< \brief (SPI5) Receive Counter Register */ +#define REG_SPI5_TPR (0x40008508U) /**< \brief (SPI5) Transmit Pointer Register */ +#define REG_SPI5_TCR (0x4000850CU) /**< \brief (SPI5) Transmit Counter Register */ +#define REG_SPI5_RNPR (0x40008510U) /**< \brief (SPI5) Receive Next Pointer Register */ +#define REG_SPI5_RNCR (0x40008514U) /**< \brief (SPI5) Receive Next Counter Register */ +#define REG_SPI5_TNPR (0x40008518U) /**< \brief (SPI5) Transmit Next Pointer Register */ +#define REG_SPI5_TNCR (0x4000851CU) /**< \brief (SPI5) Transmit Next Counter Register */ +#define REG_SPI5_PTCR (0x40008520U) /**< \brief (SPI5) Transfer Control Register */ +#define REG_SPI5_PTSR (0x40008524U) /**< \brief (SPI5) Transfer Status Register */ +#else +#define REG_SPI5_CR (*(__O uint32_t*)0x40008400U) /**< \brief (SPI5) SPI Control Register */ +#define REG_SPI5_MR (*(__IO uint32_t*)0x40008404U) /**< \brief (SPI5) SPI Mode Register */ +#define REG_SPI5_RDR (*(__I uint32_t*)0x40008408U) /**< \brief (SPI5) SPI Receive Data Register */ +#define REG_SPI5_TDR (*(__O uint32_t*)0x4000840CU) /**< \brief (SPI5) SPI Transmit Data Register */ +#define REG_SPI5_SR (*(__I uint32_t*)0x40008410U) /**< \brief (SPI5) SPI Status Register */ +#define REG_SPI5_IER (*(__O uint32_t*)0x40008414U) /**< \brief (SPI5) SPI Interrupt Enable Register */ +#define REG_SPI5_IDR (*(__O uint32_t*)0x40008418U) /**< \brief (SPI5) SPI Interrupt Disable Register */ +#define REG_SPI5_IMR (*(__I uint32_t*)0x4000841CU) /**< \brief (SPI5) SPI Interrupt Mask Register */ +#define REG_SPI5_CSR (*(__IO uint32_t*)0x40008430U) /**< \brief (SPI5) SPI Chip Select Register */ +#define REG_SPI5_CMPR (*(__IO uint32_t*)0x40008448U) /**< \brief (SPI5) SPI Comparison Register */ +#define REG_SPI5_WPMR (*(__IO uint32_t*)0x400084E4U) /**< \brief (SPI5) SPI Write Protection Mode Register */ +#define REG_SPI5_WPSR (*(__I uint32_t*)0x400084E8U) /**< \brief (SPI5) SPI Write Protection Status Register */ +#define REG_SPI5_RPR (*(__IO uint32_t*)0x40008500U) /**< \brief (SPI5) Receive Pointer Register */ +#define REG_SPI5_RCR (*(__IO uint32_t*)0x40008504U) /**< \brief (SPI5) Receive Counter Register */ +#define REG_SPI5_TPR (*(__IO uint32_t*)0x40008508U) /**< \brief (SPI5) Transmit Pointer Register */ +#define REG_SPI5_TCR (*(__IO uint32_t*)0x4000850CU) /**< \brief (SPI5) Transmit Counter Register */ +#define REG_SPI5_RNPR (*(__IO uint32_t*)0x40008510U) /**< \brief (SPI5) Receive Next Pointer Register */ +#define REG_SPI5_RNCR (*(__IO uint32_t*)0x40008514U) /**< \brief (SPI5) Receive Next Counter Register */ +#define REG_SPI5_TNPR (*(__IO uint32_t*)0x40008518U) /**< \brief (SPI5) Transmit Next Pointer Register */ +#define REG_SPI5_TNCR (*(__IO uint32_t*)0x4000851CU) /**< \brief (SPI5) Transmit Next Counter Register */ +#define REG_SPI5_PTCR (*(__O uint32_t*)0x40008520U) /**< \brief (SPI5) Transfer Control Register */ +#define REG_SPI5_PTSR (*(__I uint32_t*)0x40008524U) /**< \brief (SPI5) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_SPI5_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi6.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,97 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_SPI6_INSTANCE_ +#define _SAMG55_SPI6_INSTANCE_ + +/* ========== Register definition for SPI6 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI6_CR (0x40040400U) /**< \brief (SPI6) SPI Control Register */ +#define REG_SPI6_MR (0x40040404U) /**< \brief (SPI6) SPI Mode Register */ +#define REG_SPI6_RDR (0x40040408U) /**< \brief (SPI6) SPI Receive Data Register */ +#define REG_SPI6_TDR (0x4004040CU) /**< \brief (SPI6) SPI Transmit Data Register */ +#define REG_SPI6_SR (0x40040410U) /**< \brief (SPI6) SPI Status Register */ +#define REG_SPI6_IER (0x40040414U) /**< \brief (SPI6) SPI Interrupt Enable Register */ +#define REG_SPI6_IDR (0x40040418U) /**< \brief (SPI6) SPI Interrupt Disable Register */ +#define REG_SPI6_IMR (0x4004041CU) /**< \brief (SPI6) SPI Interrupt Mask Register */ +#define REG_SPI6_CSR (0x40040430U) /**< \brief (SPI6) SPI Chip Select Register */ +#define REG_SPI6_CMPR (0x40040448U) /**< \brief (SPI6) SPI Comparison Register */ +#define REG_SPI6_WPMR (0x400404E4U) /**< \brief (SPI6) SPI Write Protection Mode Register */ +#define REG_SPI6_WPSR (0x400404E8U) /**< \brief (SPI6) SPI Write Protection Status Register */ +#define REG_SPI6_RPR (0x40040500U) /**< \brief (SPI6) Receive Pointer Register */ +#define REG_SPI6_RCR (0x40040504U) /**< \brief (SPI6) Receive Counter Register */ +#define REG_SPI6_TPR (0x40040508U) /**< \brief (SPI6) Transmit Pointer Register */ +#define REG_SPI6_TCR (0x4004050CU) /**< \brief (SPI6) Transmit Counter Register */ +#define REG_SPI6_RNPR (0x40040510U) /**< \brief (SPI6) Receive Next Pointer Register */ +#define REG_SPI6_RNCR (0x40040514U) /**< \brief (SPI6) Receive Next Counter Register */ +#define REG_SPI6_TNPR (0x40040518U) /**< \brief (SPI6) Transmit Next Pointer Register */ +#define REG_SPI6_TNCR (0x4004051CU) /**< \brief (SPI6) Transmit Next Counter Register */ +#define REG_SPI6_PTCR (0x40040520U) /**< \brief (SPI6) Transfer Control Register */ +#define REG_SPI6_PTSR (0x40040524U) /**< \brief (SPI6) Transfer Status Register */ +#else +#define REG_SPI6_CR (*(__O uint32_t*)0x40040400U) /**< \brief (SPI6) SPI Control Register */ +#define REG_SPI6_MR (*(__IO uint32_t*)0x40040404U) /**< \brief (SPI6) SPI Mode Register */ +#define REG_SPI6_RDR (*(__I uint32_t*)0x40040408U) /**< \brief (SPI6) SPI Receive Data Register */ +#define REG_SPI6_TDR (*(__O uint32_t*)0x4004040CU) /**< \brief (SPI6) SPI Transmit Data Register */ +#define REG_SPI6_SR (*(__I uint32_t*)0x40040410U) /**< \brief (SPI6) SPI Status Register */ +#define REG_SPI6_IER (*(__O uint32_t*)0x40040414U) /**< \brief (SPI6) SPI Interrupt Enable Register */ +#define REG_SPI6_IDR (*(__O uint32_t*)0x40040418U) /**< \brief (SPI6) SPI Interrupt Disable Register */ +#define REG_SPI6_IMR (*(__I uint32_t*)0x4004041CU) /**< \brief (SPI6) SPI Interrupt Mask Register */ +#define REG_SPI6_CSR (*(__IO uint32_t*)0x40040430U) /**< \brief (SPI6) SPI Chip Select Register */ +#define REG_SPI6_CMPR (*(__IO uint32_t*)0x40040448U) /**< \brief (SPI6) SPI Comparison Register */ +#define REG_SPI6_WPMR (*(__IO uint32_t*)0x400404E4U) /**< \brief (SPI6) SPI Write Protection Mode Register */ +#define REG_SPI6_WPSR (*(__I uint32_t*)0x400404E8U) /**< \brief (SPI6) SPI Write Protection Status Register */ +#define REG_SPI6_RPR (*(__IO uint32_t*)0x40040500U) /**< \brief (SPI6) Receive Pointer Register */ +#define REG_SPI6_RCR (*(__IO uint32_t*)0x40040504U) /**< \brief (SPI6) Receive Counter Register */ +#define REG_SPI6_TPR (*(__IO uint32_t*)0x40040508U) /**< \brief (SPI6) Transmit Pointer Register */ +#define REG_SPI6_TCR (*(__IO uint32_t*)0x4004050CU) /**< \brief (SPI6) Transmit Counter Register */ +#define REG_SPI6_RNPR (*(__IO uint32_t*)0x40040510U) /**< \brief (SPI6) Receive Next Pointer Register */ +#define REG_SPI6_RNCR (*(__IO uint32_t*)0x40040514U) /**< \brief (SPI6) Receive Next Counter Register */ +#define REG_SPI6_TNPR (*(__IO uint32_t*)0x40040518U) /**< \brief (SPI6) Transmit Next Pointer Register */ +#define REG_SPI6_TNCR (*(__IO uint32_t*)0x4004051CU) /**< \brief (SPI6) Transmit Next Counter Register */ +#define REG_SPI6_PTCR (*(__O uint32_t*)0x40040520U) /**< \brief (SPI6) Transfer Control Register */ +#define REG_SPI6_PTSR (*(__I uint32_t*)0x40040524U) /**< \brief (SPI6) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_SPI6_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_spi7.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,97 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_SPI7_INSTANCE_ +#define _SAMG55_SPI7_INSTANCE_ + +/* ========== Register definition for SPI7 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI7_CR (0x40034400U) /**< \brief (SPI7) SPI Control Register */ +#define REG_SPI7_MR (0x40034404U) /**< \brief (SPI7) SPI Mode Register */ +#define REG_SPI7_RDR (0x40034408U) /**< \brief (SPI7) SPI Receive Data Register */ +#define REG_SPI7_TDR (0x4003440CU) /**< \brief (SPI7) SPI Transmit Data Register */ +#define REG_SPI7_SR (0x40034410U) /**< \brief (SPI7) SPI Status Register */ +#define REG_SPI7_IER (0x40034414U) /**< \brief (SPI7) SPI Interrupt Enable Register */ +#define REG_SPI7_IDR (0x40034418U) /**< \brief (SPI7) SPI Interrupt Disable Register */ +#define REG_SPI7_IMR (0x4003441CU) /**< \brief (SPI7) SPI Interrupt Mask Register */ +#define REG_SPI7_CSR (0x40034430U) /**< \brief (SPI7) SPI Chip Select Register */ +#define REG_SPI7_CMPR (0x40034448U) /**< \brief (SPI7) SPI Comparison Register */ +#define REG_SPI7_WPMR (0x400344E4U) /**< \brief (SPI7) SPI Write Protection Mode Register */ +#define REG_SPI7_WPSR (0x400344E8U) /**< \brief (SPI7) SPI Write Protection Status Register */ +#define REG_SPI7_RPR (0x40034500U) /**< \brief (SPI7) Receive Pointer Register */ +#define REG_SPI7_RCR (0x40034504U) /**< \brief (SPI7) Receive Counter Register */ +#define REG_SPI7_TPR (0x40034508U) /**< \brief (SPI7) Transmit Pointer Register */ +#define REG_SPI7_TCR (0x4003450CU) /**< \brief (SPI7) Transmit Counter Register */ +#define REG_SPI7_RNPR (0x40034510U) /**< \brief (SPI7) Receive Next Pointer Register */ +#define REG_SPI7_RNCR (0x40034514U) /**< \brief (SPI7) Receive Next Counter Register */ +#define REG_SPI7_TNPR (0x40034518U) /**< \brief (SPI7) Transmit Next Pointer Register */ +#define REG_SPI7_TNCR (0x4003451CU) /**< \brief (SPI7) Transmit Next Counter Register */ +#define REG_SPI7_PTCR (0x40034520U) /**< \brief (SPI7) Transfer Control Register */ +#define REG_SPI7_PTSR (0x40034524U) /**< \brief (SPI7) Transfer Status Register */ +#else +#define REG_SPI7_CR (*(__O uint32_t*)0x40034400U) /**< \brief (SPI7) SPI Control Register */ +#define REG_SPI7_MR (*(__IO uint32_t*)0x40034404U) /**< \brief (SPI7) SPI Mode Register */ +#define REG_SPI7_RDR (*(__I uint32_t*)0x40034408U) /**< \brief (SPI7) SPI Receive Data Register */ +#define REG_SPI7_TDR (*(__O uint32_t*)0x4003440CU) /**< \brief (SPI7) SPI Transmit Data Register */ +#define REG_SPI7_SR (*(__I uint32_t*)0x40034410U) /**< \brief (SPI7) SPI Status Register */ +#define REG_SPI7_IER (*(__O uint32_t*)0x40034414U) /**< \brief (SPI7) SPI Interrupt Enable Register */ +#define REG_SPI7_IDR (*(__O uint32_t*)0x40034418U) /**< \brief (SPI7) SPI Interrupt Disable Register */ +#define REG_SPI7_IMR (*(__I uint32_t*)0x4003441CU) /**< \brief (SPI7) SPI Interrupt Mask Register */ +#define REG_SPI7_CSR (*(__IO uint32_t*)0x40034430U) /**< \brief (SPI7) SPI Chip Select Register */ +#define REG_SPI7_CMPR (*(__IO uint32_t*)0x40034448U) /**< \brief (SPI7) SPI Comparison Register */ +#define REG_SPI7_WPMR (*(__IO uint32_t*)0x400344E4U) /**< \brief (SPI7) SPI Write Protection Mode Register */ +#define REG_SPI7_WPSR (*(__I uint32_t*)0x400344E8U) /**< \brief (SPI7) SPI Write Protection Status Register */ +#define REG_SPI7_RPR (*(__IO uint32_t*)0x40034500U) /**< \brief (SPI7) Receive Pointer Register */ +#define REG_SPI7_RCR (*(__IO uint32_t*)0x40034504U) /**< \brief (SPI7) Receive Counter Register */ +#define REG_SPI7_TPR (*(__IO uint32_t*)0x40034508U) /**< \brief (SPI7) Transmit Pointer Register */ +#define REG_SPI7_TCR (*(__IO uint32_t*)0x4003450CU) /**< \brief (SPI7) Transmit Counter Register */ +#define REG_SPI7_RNPR (*(__IO uint32_t*)0x40034510U) /**< \brief (SPI7) Receive Next Pointer Register */ +#define REG_SPI7_RNCR (*(__IO uint32_t*)0x40034514U) /**< \brief (SPI7) Receive Next Counter Register */ +#define REG_SPI7_TNPR (*(__IO uint32_t*)0x40034518U) /**< \brief (SPI7) Transmit Next Pointer Register */ +#define REG_SPI7_TNCR (*(__IO uint32_t*)0x4003451CU) /**< \brief (SPI7) Transmit Next Counter Register */ +#define REG_SPI7_PTCR (*(__O uint32_t*)0x40034520U) /**< \brief (SPI7) Transfer Control Register */ +#define REG_SPI7_PTSR (*(__I uint32_t*)0x40034524U) /**< \brief (SPI7) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_SPI7_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_supc.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,67 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_SUPC_INSTANCE_ +#define _SAMG55_SUPC_INSTANCE_ + +/* ========== Register definition for SUPC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SUPC_CR (0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ +#define REG_SUPC_SMMR (0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ +#define REG_SUPC_MR (0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ +#define REG_SUPC_WUMR (0x400E141CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ +#define REG_SUPC_WUIR (0x400E1420U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ +#define REG_SUPC_SR (0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ +#define REG_SUPC_PWMR (0x400E142CU) /**< \brief (SUPC) Supply Controller Power Mode Register */ +#else +#define REG_SUPC_CR (*(__O uint32_t*)0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ +#define REG_SUPC_SMMR (*(__IO uint32_t*)0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ +#define REG_SUPC_MR (*(__IO uint32_t*)0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ +#define REG_SUPC_WUMR (*(__IO uint32_t*)0x400E141CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ +#define REG_SUPC_WUIR (*(__IO uint32_t*)0x400E1420U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ +#define REG_SUPC_SR (*(__I uint32_t*)0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ +#define REG_SUPC_PWMR (*(__IO uint32_t*)0x400E142CU) /**< \brief (SUPC) Supply Controller Power Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_SUPC_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_tc0.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,137 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_TC0_INSTANCE_ +#define _SAMG55_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC0_CCR0 (0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ +#define REG_TC0_CMR0 (0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ +#define REG_TC0_SMMR0 (0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC0_CV0 (0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ +#define REG_TC0_RA0 (0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ +#define REG_TC0_RB0 (0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ +#define REG_TC0_RC0 (0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ +#define REG_TC0_SR0 (0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ +#define REG_TC0_IER0 (0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ +#define REG_TC0_IDR0 (0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ +#define REG_TC0_IMR0 (0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ +#define REG_TC0_CCR1 (0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ +#define REG_TC0_CMR1 (0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ +#define REG_TC0_SMMR1 (0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC0_CV1 (0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ +#define REG_TC0_RA1 (0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ +#define REG_TC0_RB1 (0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ +#define REG_TC0_RC1 (0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ +#define REG_TC0_SR1 (0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ +#define REG_TC0_IER1 (0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ +#define REG_TC0_IDR1 (0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ +#define REG_TC0_IMR1 (0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ +#define REG_TC0_CCR2 (0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ +#define REG_TC0_CMR2 (0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ +#define REG_TC0_SMMR2 (0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC0_CV2 (0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ +#define REG_TC0_RA2 (0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ +#define REG_TC0_RB2 (0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ +#define REG_TC0_RC2 (0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ +#define REG_TC0_SR2 (0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ +#define REG_TC0_IER2 (0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ +#define REG_TC0_IDR2 (0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ +#define REG_TC0_IMR2 (0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ +#define REG_TC0_BCR (0x400100C0U) /**< \brief (TC0) Block Control Register */ +#define REG_TC0_BMR (0x400100C4U) /**< \brief (TC0) Block Mode Register */ +#define REG_TC0_WPMR (0x400100E4U) /**< \brief (TC0) Write Protection Mode Register */ +#define REG_TC0_RPR0 (0x40010100U) /**< \brief (TC0) Receive Pointer Register (pdc = 0) */ +#define REG_TC0_RCR0 (0x40010104U) /**< \brief (TC0) Receive Counter Register (pdc = 0) */ +#define REG_TC0_RNPR0 (0x40010110U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 0) */ +#define REG_TC0_RNCR0 (0x40010114U) /**< \brief (TC0) Receive Next Counter Register (pdc = 0) */ +#define REG_TC0_PTCR0 (0x40010120U) /**< \brief (TC0) Transfer Control Register (pdc = 0) */ +#define REG_TC0_PTSR0 (0x40010124U) /**< \brief (TC0) Transfer Status Register (pdc = 0) */ +#else +#define REG_TC0_CCR0 (*(__O uint32_t*)0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ +#define REG_TC0_CMR0 (*(__IO uint32_t*)0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ +#define REG_TC0_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC0_CV0 (*(__I uint32_t*)0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ +#define REG_TC0_RA0 (*(__IO uint32_t*)0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ +#define REG_TC0_RB0 (*(__IO uint32_t*)0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ +#define REG_TC0_RC0 (*(__IO uint32_t*)0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ +#define REG_TC0_SR0 (*(__I uint32_t*)0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ +#define REG_TC0_IER0 (*(__O uint32_t*)0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ +#define REG_TC0_IDR0 (*(__O uint32_t*)0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ +#define REG_TC0_IMR0 (*(__I uint32_t*)0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ +#define REG_TC0_CCR1 (*(__O uint32_t*)0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ +#define REG_TC0_CMR1 (*(__IO uint32_t*)0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ +#define REG_TC0_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC0_CV1 (*(__I uint32_t*)0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ +#define REG_TC0_RA1 (*(__IO uint32_t*)0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ +#define REG_TC0_RB1 (*(__IO uint32_t*)0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ +#define REG_TC0_RC1 (*(__IO uint32_t*)0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ +#define REG_TC0_SR1 (*(__I uint32_t*)0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ +#define REG_TC0_IER1 (*(__O uint32_t*)0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ +#define REG_TC0_IDR1 (*(__O uint32_t*)0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ +#define REG_TC0_IMR1 (*(__I uint32_t*)0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ +#define REG_TC0_CCR2 (*(__O uint32_t*)0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ +#define REG_TC0_CMR2 (*(__IO uint32_t*)0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ +#define REG_TC0_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC0_CV2 (*(__I uint32_t*)0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ +#define REG_TC0_RA2 (*(__IO uint32_t*)0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ +#define REG_TC0_RB2 (*(__IO uint32_t*)0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ +#define REG_TC0_RC2 (*(__IO uint32_t*)0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ +#define REG_TC0_SR2 (*(__I uint32_t*)0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ +#define REG_TC0_IER2 (*(__O uint32_t*)0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ +#define REG_TC0_IDR2 (*(__O uint32_t*)0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ +#define REG_TC0_IMR2 (*(__I uint32_t*)0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ +#define REG_TC0_BCR (*(__O uint32_t*)0x400100C0U) /**< \brief (TC0) Block Control Register */ +#define REG_TC0_BMR (*(__IO uint32_t*)0x400100C4U) /**< \brief (TC0) Block Mode Register */ +#define REG_TC0_WPMR (*(__IO uint32_t*)0x400100E4U) /**< \brief (TC0) Write Protection Mode Register */ +#define REG_TC0_RPR0 (*(__IO uint32_t*)0x40010100U) /**< \brief (TC0) Receive Pointer Register (pdc = 0) */ +#define REG_TC0_RCR0 (*(__IO uint32_t*)0x40010104U) /**< \brief (TC0) Receive Counter Register (pdc = 0) */ +#define REG_TC0_RNPR0 (*(__IO uint32_t*)0x40010110U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 0) */ +#define REG_TC0_RNCR0 (*(__IO uint32_t*)0x40010114U) /**< \brief (TC0) Receive Next Counter Register (pdc = 0) */ +#define REG_TC0_PTCR0 (*(__O uint32_t*)0x40010120U) /**< \brief (TC0) Transfer Control Register (pdc = 0) */ +#define REG_TC0_PTSR0 (*(__I uint32_t*)0x40010124U) /**< \brief (TC0) Transfer Status Register (pdc = 0) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_TC0_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_tc1.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,125 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_TC1_INSTANCE_ +#define _SAMG55_TC1_INSTANCE_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC1_CCR0 (0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ +#define REG_TC1_CMR0 (0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ +#define REG_TC1_SMMR0 (0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC1_CV0 (0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ +#define REG_TC1_RA0 (0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ +#define REG_TC1_RB0 (0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ +#define REG_TC1_RC0 (0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ +#define REG_TC1_SR0 (0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ +#define REG_TC1_IER0 (0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ +#define REG_TC1_IDR0 (0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ +#define REG_TC1_IMR0 (0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ +#define REG_TC1_CCR1 (0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ +#define REG_TC1_CMR1 (0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ +#define REG_TC1_SMMR1 (0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC1_CV1 (0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ +#define REG_TC1_RA1 (0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ +#define REG_TC1_RB1 (0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ +#define REG_TC1_RC1 (0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ +#define REG_TC1_SR1 (0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ +#define REG_TC1_IER1 (0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ +#define REG_TC1_IDR1 (0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ +#define REG_TC1_IMR1 (0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ +#define REG_TC1_CCR2 (0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ +#define REG_TC1_CMR2 (0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ +#define REG_TC1_SMMR2 (0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC1_CV2 (0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ +#define REG_TC1_RA2 (0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ +#define REG_TC1_RB2 (0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ +#define REG_TC1_RC2 (0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ +#define REG_TC1_SR2 (0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ +#define REG_TC1_IER2 (0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ +#define REG_TC1_IDR2 (0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ +#define REG_TC1_IMR2 (0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ +#define REG_TC1_BCR (0x400140C0U) /**< \brief (TC1) Block Control Register */ +#define REG_TC1_BMR (0x400140C4U) /**< \brief (TC1) Block Mode Register */ +#define REG_TC1_WPMR (0x400140E4U) /**< \brief (TC1) Write Protection Mode Register */ +#else +#define REG_TC1_CCR0 (*(__O uint32_t*)0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ +#define REG_TC1_CMR0 (*(__IO uint32_t*)0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ +#define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC1_CV0 (*(__I uint32_t*)0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ +#define REG_TC1_RA0 (*(__IO uint32_t*)0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ +#define REG_TC1_RB0 (*(__IO uint32_t*)0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ +#define REG_TC1_RC0 (*(__IO uint32_t*)0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ +#define REG_TC1_SR0 (*(__I uint32_t*)0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ +#define REG_TC1_IER0 (*(__O uint32_t*)0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ +#define REG_TC1_IDR0 (*(__O uint32_t*)0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ +#define REG_TC1_IMR0 (*(__I uint32_t*)0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ +#define REG_TC1_CCR1 (*(__O uint32_t*)0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ +#define REG_TC1_CMR1 (*(__IO uint32_t*)0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ +#define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC1_CV1 (*(__I uint32_t*)0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ +#define REG_TC1_RA1 (*(__IO uint32_t*)0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ +#define REG_TC1_RB1 (*(__IO uint32_t*)0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ +#define REG_TC1_RC1 (*(__IO uint32_t*)0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ +#define REG_TC1_SR1 (*(__I uint32_t*)0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ +#define REG_TC1_IER1 (*(__O uint32_t*)0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ +#define REG_TC1_IDR1 (*(__O uint32_t*)0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ +#define REG_TC1_IMR1 (*(__I uint32_t*)0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ +#define REG_TC1_CCR2 (*(__O uint32_t*)0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ +#define REG_TC1_CMR2 (*(__IO uint32_t*)0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ +#define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC1_CV2 (*(__I uint32_t*)0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ +#define REG_TC1_RA2 (*(__IO uint32_t*)0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ +#define REG_TC1_RB2 (*(__IO uint32_t*)0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ +#define REG_TC1_RC2 (*(__IO uint32_t*)0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ +#define REG_TC1_SR2 (*(__I uint32_t*)0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ +#define REG_TC1_IER2 (*(__O uint32_t*)0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ +#define REG_TC1_IDR2 (*(__O uint32_t*)0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ +#define REG_TC1_IMR2 (*(__I uint32_t*)0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ +#define REG_TC1_BCR (*(__O uint32_t*)0x400140C0U) /**< \brief (TC1) Block Control Register */ +#define REG_TC1_BMR (*(__IO uint32_t*)0x400140C4U) /**< \brief (TC1) Block Mode Register */ +#define REG_TC1_WPMR (*(__IO uint32_t*)0x400140E4U) /**< \brief (TC1) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_TC1_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi0.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,107 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_TWI0_INSTANCE_ +#define _SAMG55_TWI0_INSTANCE_ + +/* ========== Register definition for TWI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI0_CR (0x4000C600U) /**< \brief (TWI0) TWI Control Register */ +#define REG_TWI0_MMR (0x4000C604U) /**< \brief (TWI0) TWI Master Mode Register */ +#define REG_TWI0_SMR (0x4000C608U) /**< \brief (TWI0) TWI Slave Mode Register */ +#define REG_TWI0_IADR (0x4000C60CU) /**< \brief (TWI0) TWI Internal Address Register */ +#define REG_TWI0_CWGR (0x4000C610U) /**< \brief (TWI0) TWI Clock Waveform Generator Register */ +#define REG_TWI0_SR (0x4000C620U) /**< \brief (TWI0) TWI Status Register */ +#define REG_TWI0_IER (0x4000C624U) /**< \brief (TWI0) TWI Interrupt Enable Register */ +#define REG_TWI0_IDR (0x4000C628U) /**< \brief (TWI0) TWI Interrupt Disable Register */ +#define REG_TWI0_IMR (0x4000C62CU) /**< \brief (TWI0) TWI Interrupt Mask Register */ +#define REG_TWI0_RHR (0x4000C630U) /**< \brief (TWI0) TWI Receive Holding Register */ +#define REG_TWI0_THR (0x4000C634U) /**< \brief (TWI0) TWI Transmit Holding Register */ +#define REG_TWI0_SMBTR (0x4000C638U) /**< \brief (TWI0) TWI SMBus Timing Register */ +#define REG_TWI0_ACR (0x4000C640U) /**< \brief (TWI0) TWI Alternative Command Register */ +#define REG_TWI0_FILTR (0x4000C644U) /**< \brief (TWI0) TWI Filter Register */ +#define REG_TWI0_SWMR (0x4000C64CU) /**< \brief (TWI0) TWI SleepWalking Matching Register */ +#define REG_TWI0_WPMR (0x4000C6E4U) /**< \brief (TWI0) TWI Write Protection Mode Register */ +#define REG_TWI0_WPSR (0x4000C6E8U) /**< \brief (TWI0) TWI Write Protection Status Register */ +#define REG_TWI0_RPR (0x4000C700U) /**< \brief (TWI0) Receive Pointer Register */ +#define REG_TWI0_RCR (0x4000C704U) /**< \brief (TWI0) Receive Counter Register */ +#define REG_TWI0_TPR (0x4000C708U) /**< \brief (TWI0) Transmit Pointer Register */ +#define REG_TWI0_TCR (0x4000C70CU) /**< \brief (TWI0) Transmit Counter Register */ +#define REG_TWI0_RNPR (0x4000C710U) /**< \brief (TWI0) Receive Next Pointer Register */ +#define REG_TWI0_RNCR (0x4000C714U) /**< \brief (TWI0) Receive Next Counter Register */ +#define REG_TWI0_TNPR (0x4000C718U) /**< \brief (TWI0) Transmit Next Pointer Register */ +#define REG_TWI0_TNCR (0x4000C71CU) /**< \brief (TWI0) Transmit Next Counter Register */ +#define REG_TWI0_PTCR (0x4000C720U) /**< \brief (TWI0) Transfer Control Register */ +#define REG_TWI0_PTSR (0x4000C724U) /**< \brief (TWI0) Transfer Status Register */ +#else +#define REG_TWI0_CR (*(__O uint32_t*)0x4000C600U) /**< \brief (TWI0) TWI Control Register */ +#define REG_TWI0_MMR (*(__IO uint32_t*)0x4000C604U) /**< \brief (TWI0) TWI Master Mode Register */ +#define REG_TWI0_SMR (*(__IO uint32_t*)0x4000C608U) /**< \brief (TWI0) TWI Slave Mode Register */ +#define REG_TWI0_IADR (*(__IO uint32_t*)0x4000C60CU) /**< \brief (TWI0) TWI Internal Address Register */ +#define REG_TWI0_CWGR (*(__IO uint32_t*)0x4000C610U) /**< \brief (TWI0) TWI Clock Waveform Generator Register */ +#define REG_TWI0_SR (*(__I uint32_t*)0x4000C620U) /**< \brief (TWI0) TWI Status Register */ +#define REG_TWI0_IER (*(__O uint32_t*)0x4000C624U) /**< \brief (TWI0) TWI Interrupt Enable Register */ +#define REG_TWI0_IDR (*(__O uint32_t*)0x4000C628U) /**< \brief (TWI0) TWI Interrupt Disable Register */ +#define REG_TWI0_IMR (*(__I uint32_t*)0x4000C62CU) /**< \brief (TWI0) TWI Interrupt Mask Register */ +#define REG_TWI0_RHR (*(__I uint32_t*)0x4000C630U) /**< \brief (TWI0) TWI Receive Holding Register */ +#define REG_TWI0_THR (*(__O uint32_t*)0x4000C634U) /**< \brief (TWI0) TWI Transmit Holding Register */ +#define REG_TWI0_SMBTR (*(__IO uint32_t*)0x4000C638U) /**< \brief (TWI0) TWI SMBus Timing Register */ +#define REG_TWI0_ACR (*(__IO uint32_t*)0x4000C640U) /**< \brief (TWI0) TWI Alternative Command Register */ +#define REG_TWI0_FILTR (*(__IO uint32_t*)0x4000C644U) /**< \brief (TWI0) TWI Filter Register */ +#define REG_TWI0_SWMR (*(__IO uint32_t*)0x4000C64CU) /**< \brief (TWI0) TWI SleepWalking Matching Register */ +#define REG_TWI0_WPMR (*(__IO uint32_t*)0x4000C6E4U) /**< \brief (TWI0) TWI Write Protection Mode Register */ +#define REG_TWI0_WPSR (*(__I uint32_t*)0x4000C6E8U) /**< \brief (TWI0) TWI Write Protection Status Register */ +#define REG_TWI0_RPR (*(__IO uint32_t*)0x4000C700U) /**< \brief (TWI0) Receive Pointer Register */ +#define REG_TWI0_RCR (*(__IO uint32_t*)0x4000C704U) /**< \brief (TWI0) Receive Counter Register */ +#define REG_TWI0_TPR (*(__IO uint32_t*)0x4000C708U) /**< \brief (TWI0) Transmit Pointer Register */ +#define REG_TWI0_TCR (*(__IO uint32_t*)0x4000C70CU) /**< \brief (TWI0) Transmit Counter Register */ +#define REG_TWI0_RNPR (*(__IO uint32_t*)0x4000C710U) /**< \brief (TWI0) Receive Next Pointer Register */ +#define REG_TWI0_RNCR (*(__IO uint32_t*)0x4000C714U) /**< \brief (TWI0) Receive Next Counter Register */ +#define REG_TWI0_TNPR (*(__IO uint32_t*)0x4000C718U) /**< \brief (TWI0) Transmit Next Pointer Register */ +#define REG_TWI0_TNCR (*(__IO uint32_t*)0x4000C71CU) /**< \brief (TWI0) Transmit Next Counter Register */ +#define REG_TWI0_PTCR (*(__O uint32_t*)0x4000C720U) /**< \brief (TWI0) Transfer Control Register */ +#define REG_TWI0_PTSR (*(__I uint32_t*)0x4000C724U) /**< \brief (TWI0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_TWI0_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi1.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,107 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_TWI1_INSTANCE_ +#define _SAMG55_TWI1_INSTANCE_ + +/* ========== Register definition for TWI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI1_CR (0x40020600U) /**< \brief (TWI1) TWI Control Register */ +#define REG_TWI1_MMR (0x40020604U) /**< \brief (TWI1) TWI Master Mode Register */ +#define REG_TWI1_SMR (0x40020608U) /**< \brief (TWI1) TWI Slave Mode Register */ +#define REG_TWI1_IADR (0x4002060CU) /**< \brief (TWI1) TWI Internal Address Register */ +#define REG_TWI1_CWGR (0x40020610U) /**< \brief (TWI1) TWI Clock Waveform Generator Register */ +#define REG_TWI1_SR (0x40020620U) /**< \brief (TWI1) TWI Status Register */ +#define REG_TWI1_IER (0x40020624U) /**< \brief (TWI1) TWI Interrupt Enable Register */ +#define REG_TWI1_IDR (0x40020628U) /**< \brief (TWI1) TWI Interrupt Disable Register */ +#define REG_TWI1_IMR (0x4002062CU) /**< \brief (TWI1) TWI Interrupt Mask Register */ +#define REG_TWI1_RHR (0x40020630U) /**< \brief (TWI1) TWI Receive Holding Register */ +#define REG_TWI1_THR (0x40020634U) /**< \brief (TWI1) TWI Transmit Holding Register */ +#define REG_TWI1_SMBTR (0x40020638U) /**< \brief (TWI1) TWI SMBus Timing Register */ +#define REG_TWI1_ACR (0x40020640U) /**< \brief (TWI1) TWI Alternative Command Register */ +#define REG_TWI1_FILTR (0x40020644U) /**< \brief (TWI1) TWI Filter Register */ +#define REG_TWI1_SWMR (0x4002064CU) /**< \brief (TWI1) TWI SleepWalking Matching Register */ +#define REG_TWI1_WPMR (0x400206E4U) /**< \brief (TWI1) TWI Write Protection Mode Register */ +#define REG_TWI1_WPSR (0x400206E8U) /**< \brief (TWI1) TWI Write Protection Status Register */ +#define REG_TWI1_RPR (0x40020700U) /**< \brief (TWI1) Receive Pointer Register */ +#define REG_TWI1_RCR (0x40020704U) /**< \brief (TWI1) Receive Counter Register */ +#define REG_TWI1_TPR (0x40020708U) /**< \brief (TWI1) Transmit Pointer Register */ +#define REG_TWI1_TCR (0x4002070CU) /**< \brief (TWI1) Transmit Counter Register */ +#define REG_TWI1_RNPR (0x40020710U) /**< \brief (TWI1) Receive Next Pointer Register */ +#define REG_TWI1_RNCR (0x40020714U) /**< \brief (TWI1) Receive Next Counter Register */ +#define REG_TWI1_TNPR (0x40020718U) /**< \brief (TWI1) Transmit Next Pointer Register */ +#define REG_TWI1_TNCR (0x4002071CU) /**< \brief (TWI1) Transmit Next Counter Register */ +#define REG_TWI1_PTCR (0x40020720U) /**< \brief (TWI1) Transfer Control Register */ +#define REG_TWI1_PTSR (0x40020724U) /**< \brief (TWI1) Transfer Status Register */ +#else +#define REG_TWI1_CR (*(__O uint32_t*)0x40020600U) /**< \brief (TWI1) TWI Control Register */ +#define REG_TWI1_MMR (*(__IO uint32_t*)0x40020604U) /**< \brief (TWI1) TWI Master Mode Register */ +#define REG_TWI1_SMR (*(__IO uint32_t*)0x40020608U) /**< \brief (TWI1) TWI Slave Mode Register */ +#define REG_TWI1_IADR (*(__IO uint32_t*)0x4002060CU) /**< \brief (TWI1) TWI Internal Address Register */ +#define REG_TWI1_CWGR (*(__IO uint32_t*)0x40020610U) /**< \brief (TWI1) TWI Clock Waveform Generator Register */ +#define REG_TWI1_SR (*(__I uint32_t*)0x40020620U) /**< \brief (TWI1) TWI Status Register */ +#define REG_TWI1_IER (*(__O uint32_t*)0x40020624U) /**< \brief (TWI1) TWI Interrupt Enable Register */ +#define REG_TWI1_IDR (*(__O uint32_t*)0x40020628U) /**< \brief (TWI1) TWI Interrupt Disable Register */ +#define REG_TWI1_IMR (*(__I uint32_t*)0x4002062CU) /**< \brief (TWI1) TWI Interrupt Mask Register */ +#define REG_TWI1_RHR (*(__I uint32_t*)0x40020630U) /**< \brief (TWI1) TWI Receive Holding Register */ +#define REG_TWI1_THR (*(__O uint32_t*)0x40020634U) /**< \brief (TWI1) TWI Transmit Holding Register */ +#define REG_TWI1_SMBTR (*(__IO uint32_t*)0x40020638U) /**< \brief (TWI1) TWI SMBus Timing Register */ +#define REG_TWI1_ACR (*(__IO uint32_t*)0x40020640U) /**< \brief (TWI1) TWI Alternative Command Register */ +#define REG_TWI1_FILTR (*(__IO uint32_t*)0x40020644U) /**< \brief (TWI1) TWI Filter Register */ +#define REG_TWI1_SWMR (*(__IO uint32_t*)0x4002064CU) /**< \brief (TWI1) TWI SleepWalking Matching Register */ +#define REG_TWI1_WPMR (*(__IO uint32_t*)0x400206E4U) /**< \brief (TWI1) TWI Write Protection Mode Register */ +#define REG_TWI1_WPSR (*(__I uint32_t*)0x400206E8U) /**< \brief (TWI1) TWI Write Protection Status Register */ +#define REG_TWI1_RPR (*(__IO uint32_t*)0x40020700U) /**< \brief (TWI1) Receive Pointer Register */ +#define REG_TWI1_RCR (*(__IO uint32_t*)0x40020704U) /**< \brief (TWI1) Receive Counter Register */ +#define REG_TWI1_TPR (*(__IO uint32_t*)0x40020708U) /**< \brief (TWI1) Transmit Pointer Register */ +#define REG_TWI1_TCR (*(__IO uint32_t*)0x4002070CU) /**< \brief (TWI1) Transmit Counter Register */ +#define REG_TWI1_RNPR (*(__IO uint32_t*)0x40020710U) /**< \brief (TWI1) Receive Next Pointer Register */ +#define REG_TWI1_RNCR (*(__IO uint32_t*)0x40020714U) /**< \brief (TWI1) Receive Next Counter Register */ +#define REG_TWI1_TNPR (*(__IO uint32_t*)0x40020718U) /**< \brief (TWI1) Transmit Next Pointer Register */ +#define REG_TWI1_TNCR (*(__IO uint32_t*)0x4002071CU) /**< \brief (TWI1) Transmit Next Counter Register */ +#define REG_TWI1_PTCR (*(__O uint32_t*)0x40020720U) /**< \brief (TWI1) Transfer Control Register */ +#define REG_TWI1_PTSR (*(__I uint32_t*)0x40020724U) /**< \brief (TWI1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_TWI1_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi2.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,107 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_TWI2_INSTANCE_ +#define _SAMG55_TWI2_INSTANCE_ + +/* ========== Register definition for TWI2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI2_CR (0x40024600U) /**< \brief (TWI2) TWI Control Register */ +#define REG_TWI2_MMR (0x40024604U) /**< \brief (TWI2) TWI Master Mode Register */ +#define REG_TWI2_SMR (0x40024608U) /**< \brief (TWI2) TWI Slave Mode Register */ +#define REG_TWI2_IADR (0x4002460CU) /**< \brief (TWI2) TWI Internal Address Register */ +#define REG_TWI2_CWGR (0x40024610U) /**< \brief (TWI2) TWI Clock Waveform Generator Register */ +#define REG_TWI2_SR (0x40024620U) /**< \brief (TWI2) TWI Status Register */ +#define REG_TWI2_IER (0x40024624U) /**< \brief (TWI2) TWI Interrupt Enable Register */ +#define REG_TWI2_IDR (0x40024628U) /**< \brief (TWI2) TWI Interrupt Disable Register */ +#define REG_TWI2_IMR (0x4002462CU) /**< \brief (TWI2) TWI Interrupt Mask Register */ +#define REG_TWI2_RHR (0x40024630U) /**< \brief (TWI2) TWI Receive Holding Register */ +#define REG_TWI2_THR (0x40024634U) /**< \brief (TWI2) TWI Transmit Holding Register */ +#define REG_TWI2_SMBTR (0x40024638U) /**< \brief (TWI2) TWI SMBus Timing Register */ +#define REG_TWI2_ACR (0x40024640U) /**< \brief (TWI2) TWI Alternative Command Register */ +#define REG_TWI2_FILTR (0x40024644U) /**< \brief (TWI2) TWI Filter Register */ +#define REG_TWI2_SWMR (0x4002464CU) /**< \brief (TWI2) TWI SleepWalking Matching Register */ +#define REG_TWI2_WPMR (0x400246E4U) /**< \brief (TWI2) TWI Write Protection Mode Register */ +#define REG_TWI2_WPSR (0x400246E8U) /**< \brief (TWI2) TWI Write Protection Status Register */ +#define REG_TWI2_RPR (0x40024700U) /**< \brief (TWI2) Receive Pointer Register */ +#define REG_TWI2_RCR (0x40024704U) /**< \brief (TWI2) Receive Counter Register */ +#define REG_TWI2_TPR (0x40024708U) /**< \brief (TWI2) Transmit Pointer Register */ +#define REG_TWI2_TCR (0x4002470CU) /**< \brief (TWI2) Transmit Counter Register */ +#define REG_TWI2_RNPR (0x40024710U) /**< \brief (TWI2) Receive Next Pointer Register */ +#define REG_TWI2_RNCR (0x40024714U) /**< \brief (TWI2) Receive Next Counter Register */ +#define REG_TWI2_TNPR (0x40024718U) /**< \brief (TWI2) Transmit Next Pointer Register */ +#define REG_TWI2_TNCR (0x4002471CU) /**< \brief (TWI2) Transmit Next Counter Register */ +#define REG_TWI2_PTCR (0x40024720U) /**< \brief (TWI2) Transfer Control Register */ +#define REG_TWI2_PTSR (0x40024724U) /**< \brief (TWI2) Transfer Status Register */ +#else +#define REG_TWI2_CR (*(__O uint32_t*)0x40024600U) /**< \brief (TWI2) TWI Control Register */ +#define REG_TWI2_MMR (*(__IO uint32_t*)0x40024604U) /**< \brief (TWI2) TWI Master Mode Register */ +#define REG_TWI2_SMR (*(__IO uint32_t*)0x40024608U) /**< \brief (TWI2) TWI Slave Mode Register */ +#define REG_TWI2_IADR (*(__IO uint32_t*)0x4002460CU) /**< \brief (TWI2) TWI Internal Address Register */ +#define REG_TWI2_CWGR (*(__IO uint32_t*)0x40024610U) /**< \brief (TWI2) TWI Clock Waveform Generator Register */ +#define REG_TWI2_SR (*(__I uint32_t*)0x40024620U) /**< \brief (TWI2) TWI Status Register */ +#define REG_TWI2_IER (*(__O uint32_t*)0x40024624U) /**< \brief (TWI2) TWI Interrupt Enable Register */ +#define REG_TWI2_IDR (*(__O uint32_t*)0x40024628U) /**< \brief (TWI2) TWI Interrupt Disable Register */ +#define REG_TWI2_IMR (*(__I uint32_t*)0x4002462CU) /**< \brief (TWI2) TWI Interrupt Mask Register */ +#define REG_TWI2_RHR (*(__I uint32_t*)0x40024630U) /**< \brief (TWI2) TWI Receive Holding Register */ +#define REG_TWI2_THR (*(__O uint32_t*)0x40024634U) /**< \brief (TWI2) TWI Transmit Holding Register */ +#define REG_TWI2_SMBTR (*(__IO uint32_t*)0x40024638U) /**< \brief (TWI2) TWI SMBus Timing Register */ +#define REG_TWI2_ACR (*(__IO uint32_t*)0x40024640U) /**< \brief (TWI2) TWI Alternative Command Register */ +#define REG_TWI2_FILTR (*(__IO uint32_t*)0x40024644U) /**< \brief (TWI2) TWI Filter Register */ +#define REG_TWI2_SWMR (*(__IO uint32_t*)0x4002464CU) /**< \brief (TWI2) TWI SleepWalking Matching Register */ +#define REG_TWI2_WPMR (*(__IO uint32_t*)0x400246E4U) /**< \brief (TWI2) TWI Write Protection Mode Register */ +#define REG_TWI2_WPSR (*(__I uint32_t*)0x400246E8U) /**< \brief (TWI2) TWI Write Protection Status Register */ +#define REG_TWI2_RPR (*(__IO uint32_t*)0x40024700U) /**< \brief (TWI2) Receive Pointer Register */ +#define REG_TWI2_RCR (*(__IO uint32_t*)0x40024704U) /**< \brief (TWI2) Receive Counter Register */ +#define REG_TWI2_TPR (*(__IO uint32_t*)0x40024708U) /**< \brief (TWI2) Transmit Pointer Register */ +#define REG_TWI2_TCR (*(__IO uint32_t*)0x4002470CU) /**< \brief (TWI2) Transmit Counter Register */ +#define REG_TWI2_RNPR (*(__IO uint32_t*)0x40024710U) /**< \brief (TWI2) Receive Next Pointer Register */ +#define REG_TWI2_RNCR (*(__IO uint32_t*)0x40024714U) /**< \brief (TWI2) Receive Next Counter Register */ +#define REG_TWI2_TNPR (*(__IO uint32_t*)0x40024718U) /**< \brief (TWI2) Transmit Next Pointer Register */ +#define REG_TWI2_TNCR (*(__IO uint32_t*)0x4002471CU) /**< \brief (TWI2) Transmit Next Counter Register */ +#define REG_TWI2_PTCR (*(__O uint32_t*)0x40024720U) /**< \brief (TWI2) Transfer Control Register */ +#define REG_TWI2_PTSR (*(__I uint32_t*)0x40024724U) /**< \brief (TWI2) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_TWI2_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi3.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,107 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_TWI3_INSTANCE_ +#define _SAMG55_TWI3_INSTANCE_ + +/* ========== Register definition for TWI3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI3_CR (0x40018600U) /**< \brief (TWI3) TWI Control Register */ +#define REG_TWI3_MMR (0x40018604U) /**< \brief (TWI3) TWI Master Mode Register */ +#define REG_TWI3_SMR (0x40018608U) /**< \brief (TWI3) TWI Slave Mode Register */ +#define REG_TWI3_IADR (0x4001860CU) /**< \brief (TWI3) TWI Internal Address Register */ +#define REG_TWI3_CWGR (0x40018610U) /**< \brief (TWI3) TWI Clock Waveform Generator Register */ +#define REG_TWI3_SR (0x40018620U) /**< \brief (TWI3) TWI Status Register */ +#define REG_TWI3_IER (0x40018624U) /**< \brief (TWI3) TWI Interrupt Enable Register */ +#define REG_TWI3_IDR (0x40018628U) /**< \brief (TWI3) TWI Interrupt Disable Register */ +#define REG_TWI3_IMR (0x4001862CU) /**< \brief (TWI3) TWI Interrupt Mask Register */ +#define REG_TWI3_RHR (0x40018630U) /**< \brief (TWI3) TWI Receive Holding Register */ +#define REG_TWI3_THR (0x40018634U) /**< \brief (TWI3) TWI Transmit Holding Register */ +#define REG_TWI3_SMBTR (0x40018638U) /**< \brief (TWI3) TWI SMBus Timing Register */ +#define REG_TWI3_ACR (0x40018640U) /**< \brief (TWI3) TWI Alternative Command Register */ +#define REG_TWI3_FILTR (0x40018644U) /**< \brief (TWI3) TWI Filter Register */ +#define REG_TWI3_SWMR (0x4001864CU) /**< \brief (TWI3) TWI SleepWalking Matching Register */ +#define REG_TWI3_WPMR (0x400186E4U) /**< \brief (TWI3) TWI Write Protection Mode Register */ +#define REG_TWI3_WPSR (0x400186E8U) /**< \brief (TWI3) TWI Write Protection Status Register */ +#define REG_TWI3_RPR (0x40018700U) /**< \brief (TWI3) Receive Pointer Register */ +#define REG_TWI3_RCR (0x40018704U) /**< \brief (TWI3) Receive Counter Register */ +#define REG_TWI3_TPR (0x40018708U) /**< \brief (TWI3) Transmit Pointer Register */ +#define REG_TWI3_TCR (0x4001870CU) /**< \brief (TWI3) Transmit Counter Register */ +#define REG_TWI3_RNPR (0x40018710U) /**< \brief (TWI3) Receive Next Pointer Register */ +#define REG_TWI3_RNCR (0x40018714U) /**< \brief (TWI3) Receive Next Counter Register */ +#define REG_TWI3_TNPR (0x40018718U) /**< \brief (TWI3) Transmit Next Pointer Register */ +#define REG_TWI3_TNCR (0x4001871CU) /**< \brief (TWI3) Transmit Next Counter Register */ +#define REG_TWI3_PTCR (0x40018720U) /**< \brief (TWI3) Transfer Control Register */ +#define REG_TWI3_PTSR (0x40018724U) /**< \brief (TWI3) Transfer Status Register */ +#else +#define REG_TWI3_CR (*(__O uint32_t*)0x40018600U) /**< \brief (TWI3) TWI Control Register */ +#define REG_TWI3_MMR (*(__IO uint32_t*)0x40018604U) /**< \brief (TWI3) TWI Master Mode Register */ +#define REG_TWI3_SMR (*(__IO uint32_t*)0x40018608U) /**< \brief (TWI3) TWI Slave Mode Register */ +#define REG_TWI3_IADR (*(__IO uint32_t*)0x4001860CU) /**< \brief (TWI3) TWI Internal Address Register */ +#define REG_TWI3_CWGR (*(__IO uint32_t*)0x40018610U) /**< \brief (TWI3) TWI Clock Waveform Generator Register */ +#define REG_TWI3_SR (*(__I uint32_t*)0x40018620U) /**< \brief (TWI3) TWI Status Register */ +#define REG_TWI3_IER (*(__O uint32_t*)0x40018624U) /**< \brief (TWI3) TWI Interrupt Enable Register */ +#define REG_TWI3_IDR (*(__O uint32_t*)0x40018628U) /**< \brief (TWI3) TWI Interrupt Disable Register */ +#define REG_TWI3_IMR (*(__I uint32_t*)0x4001862CU) /**< \brief (TWI3) TWI Interrupt Mask Register */ +#define REG_TWI3_RHR (*(__I uint32_t*)0x40018630U) /**< \brief (TWI3) TWI Receive Holding Register */ +#define REG_TWI3_THR (*(__O uint32_t*)0x40018634U) /**< \brief (TWI3) TWI Transmit Holding Register */ +#define REG_TWI3_SMBTR (*(__IO uint32_t*)0x40018638U) /**< \brief (TWI3) TWI SMBus Timing Register */ +#define REG_TWI3_ACR (*(__IO uint32_t*)0x40018640U) /**< \brief (TWI3) TWI Alternative Command Register */ +#define REG_TWI3_FILTR (*(__IO uint32_t*)0x40018644U) /**< \brief (TWI3) TWI Filter Register */ +#define REG_TWI3_SWMR (*(__IO uint32_t*)0x4001864CU) /**< \brief (TWI3) TWI SleepWalking Matching Register */ +#define REG_TWI3_WPMR (*(__IO uint32_t*)0x400186E4U) /**< \brief (TWI3) TWI Write Protection Mode Register */ +#define REG_TWI3_WPSR (*(__I uint32_t*)0x400186E8U) /**< \brief (TWI3) TWI Write Protection Status Register */ +#define REG_TWI3_RPR (*(__IO uint32_t*)0x40018700U) /**< \brief (TWI3) Receive Pointer Register */ +#define REG_TWI3_RCR (*(__IO uint32_t*)0x40018704U) /**< \brief (TWI3) Receive Counter Register */ +#define REG_TWI3_TPR (*(__IO uint32_t*)0x40018708U) /**< \brief (TWI3) Transmit Pointer Register */ +#define REG_TWI3_TCR (*(__IO uint32_t*)0x4001870CU) /**< \brief (TWI3) Transmit Counter Register */ +#define REG_TWI3_RNPR (*(__IO uint32_t*)0x40018710U) /**< \brief (TWI3) Receive Next Pointer Register */ +#define REG_TWI3_RNCR (*(__IO uint32_t*)0x40018714U) /**< \brief (TWI3) Receive Next Counter Register */ +#define REG_TWI3_TNPR (*(__IO uint32_t*)0x40018718U) /**< \brief (TWI3) Transmit Next Pointer Register */ +#define REG_TWI3_TNCR (*(__IO uint32_t*)0x4001871CU) /**< \brief (TWI3) Transmit Next Counter Register */ +#define REG_TWI3_PTCR (*(__O uint32_t*)0x40018720U) /**< \brief (TWI3) Transfer Control Register */ +#define REG_TWI3_PTSR (*(__I uint32_t*)0x40018724U) /**< \brief (TWI3) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_TWI3_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi4.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,107 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_TWI4_INSTANCE_ +#define _SAMG55_TWI4_INSTANCE_ + +/* ========== Register definition for TWI4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI4_CR (0x4001C600U) /**< \brief (TWI4) TWI Control Register */ +#define REG_TWI4_MMR (0x4001C604U) /**< \brief (TWI4) TWI Master Mode Register */ +#define REG_TWI4_SMR (0x4001C608U) /**< \brief (TWI4) TWI Slave Mode Register */ +#define REG_TWI4_IADR (0x4001C60CU) /**< \brief (TWI4) TWI Internal Address Register */ +#define REG_TWI4_CWGR (0x4001C610U) /**< \brief (TWI4) TWI Clock Waveform Generator Register */ +#define REG_TWI4_SR (0x4001C620U) /**< \brief (TWI4) TWI Status Register */ +#define REG_TWI4_IER (0x4001C624U) /**< \brief (TWI4) TWI Interrupt Enable Register */ +#define REG_TWI4_IDR (0x4001C628U) /**< \brief (TWI4) TWI Interrupt Disable Register */ +#define REG_TWI4_IMR (0x4001C62CU) /**< \brief (TWI4) TWI Interrupt Mask Register */ +#define REG_TWI4_RHR (0x4001C630U) /**< \brief (TWI4) TWI Receive Holding Register */ +#define REG_TWI4_THR (0x4001C634U) /**< \brief (TWI4) TWI Transmit Holding Register */ +#define REG_TWI4_SMBTR (0x4001C638U) /**< \brief (TWI4) TWI SMBus Timing Register */ +#define REG_TWI4_ACR (0x4001C640U) /**< \brief (TWI4) TWI Alternative Command Register */ +#define REG_TWI4_FILTR (0x4001C644U) /**< \brief (TWI4) TWI Filter Register */ +#define REG_TWI4_SWMR (0x4001C64CU) /**< \brief (TWI4) TWI SleepWalking Matching Register */ +#define REG_TWI4_WPMR (0x4001C6E4U) /**< \brief (TWI4) TWI Write Protection Mode Register */ +#define REG_TWI4_WPSR (0x4001C6E8U) /**< \brief (TWI4) TWI Write Protection Status Register */ +#define REG_TWI4_RPR (0x4001C700U) /**< \brief (TWI4) Receive Pointer Register */ +#define REG_TWI4_RCR (0x4001C704U) /**< \brief (TWI4) Receive Counter Register */ +#define REG_TWI4_TPR (0x4001C708U) /**< \brief (TWI4) Transmit Pointer Register */ +#define REG_TWI4_TCR (0x4001C70CU) /**< \brief (TWI4) Transmit Counter Register */ +#define REG_TWI4_RNPR (0x4001C710U) /**< \brief (TWI4) Receive Next Pointer Register */ +#define REG_TWI4_RNCR (0x4001C714U) /**< \brief (TWI4) Receive Next Counter Register */ +#define REG_TWI4_TNPR (0x4001C718U) /**< \brief (TWI4) Transmit Next Pointer Register */ +#define REG_TWI4_TNCR (0x4001C71CU) /**< \brief (TWI4) Transmit Next Counter Register */ +#define REG_TWI4_PTCR (0x4001C720U) /**< \brief (TWI4) Transfer Control Register */ +#define REG_TWI4_PTSR (0x4001C724U) /**< \brief (TWI4) Transfer Status Register */ +#else +#define REG_TWI4_CR (*(__O uint32_t*)0x4001C600U) /**< \brief (TWI4) TWI Control Register */ +#define REG_TWI4_MMR (*(__IO uint32_t*)0x4001C604U) /**< \brief (TWI4) TWI Master Mode Register */ +#define REG_TWI4_SMR (*(__IO uint32_t*)0x4001C608U) /**< \brief (TWI4) TWI Slave Mode Register */ +#define REG_TWI4_IADR (*(__IO uint32_t*)0x4001C60CU) /**< \brief (TWI4) TWI Internal Address Register */ +#define REG_TWI4_CWGR (*(__IO uint32_t*)0x4001C610U) /**< \brief (TWI4) TWI Clock Waveform Generator Register */ +#define REG_TWI4_SR (*(__I uint32_t*)0x4001C620U) /**< \brief (TWI4) TWI Status Register */ +#define REG_TWI4_IER (*(__O uint32_t*)0x4001C624U) /**< \brief (TWI4) TWI Interrupt Enable Register */ +#define REG_TWI4_IDR (*(__O uint32_t*)0x4001C628U) /**< \brief (TWI4) TWI Interrupt Disable Register */ +#define REG_TWI4_IMR (*(__I uint32_t*)0x4001C62CU) /**< \brief (TWI4) TWI Interrupt Mask Register */ +#define REG_TWI4_RHR (*(__I uint32_t*)0x4001C630U) /**< \brief (TWI4) TWI Receive Holding Register */ +#define REG_TWI4_THR (*(__O uint32_t*)0x4001C634U) /**< \brief (TWI4) TWI Transmit Holding Register */ +#define REG_TWI4_SMBTR (*(__IO uint32_t*)0x4001C638U) /**< \brief (TWI4) TWI SMBus Timing Register */ +#define REG_TWI4_ACR (*(__IO uint32_t*)0x4001C640U) /**< \brief (TWI4) TWI Alternative Command Register */ +#define REG_TWI4_FILTR (*(__IO uint32_t*)0x4001C644U) /**< \brief (TWI4) TWI Filter Register */ +#define REG_TWI4_SWMR (*(__IO uint32_t*)0x4001C64CU) /**< \brief (TWI4) TWI SleepWalking Matching Register */ +#define REG_TWI4_WPMR (*(__IO uint32_t*)0x4001C6E4U) /**< \brief (TWI4) TWI Write Protection Mode Register */ +#define REG_TWI4_WPSR (*(__I uint32_t*)0x4001C6E8U) /**< \brief (TWI4) TWI Write Protection Status Register */ +#define REG_TWI4_RPR (*(__IO uint32_t*)0x4001C700U) /**< \brief (TWI4) Receive Pointer Register */ +#define REG_TWI4_RCR (*(__IO uint32_t*)0x4001C704U) /**< \brief (TWI4) Receive Counter Register */ +#define REG_TWI4_TPR (*(__IO uint32_t*)0x4001C708U) /**< \brief (TWI4) Transmit Pointer Register */ +#define REG_TWI4_TCR (*(__IO uint32_t*)0x4001C70CU) /**< \brief (TWI4) Transmit Counter Register */ +#define REG_TWI4_RNPR (*(__IO uint32_t*)0x4001C710U) /**< \brief (TWI4) Receive Next Pointer Register */ +#define REG_TWI4_RNCR (*(__IO uint32_t*)0x4001C714U) /**< \brief (TWI4) Receive Next Counter Register */ +#define REG_TWI4_TNPR (*(__IO uint32_t*)0x4001C718U) /**< \brief (TWI4) Transmit Next Pointer Register */ +#define REG_TWI4_TNCR (*(__IO uint32_t*)0x4001C71CU) /**< \brief (TWI4) Transmit Next Counter Register */ +#define REG_TWI4_PTCR (*(__O uint32_t*)0x4001C720U) /**< \brief (TWI4) Transfer Control Register */ +#define REG_TWI4_PTSR (*(__I uint32_t*)0x4001C724U) /**< \brief (TWI4) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_TWI4_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi5.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,107 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_TWI5_INSTANCE_ +#define _SAMG55_TWI5_INSTANCE_ + +/* ========== Register definition for TWI5 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI5_CR (0x40008600U) /**< \brief (TWI5) TWI Control Register */ +#define REG_TWI5_MMR (0x40008604U) /**< \brief (TWI5) TWI Master Mode Register */ +#define REG_TWI5_SMR (0x40008608U) /**< \brief (TWI5) TWI Slave Mode Register */ +#define REG_TWI5_IADR (0x4000860CU) /**< \brief (TWI5) TWI Internal Address Register */ +#define REG_TWI5_CWGR (0x40008610U) /**< \brief (TWI5) TWI Clock Waveform Generator Register */ +#define REG_TWI5_SR (0x40008620U) /**< \brief (TWI5) TWI Status Register */ +#define REG_TWI5_IER (0x40008624U) /**< \brief (TWI5) TWI Interrupt Enable Register */ +#define REG_TWI5_IDR (0x40008628U) /**< \brief (TWI5) TWI Interrupt Disable Register */ +#define REG_TWI5_IMR (0x4000862CU) /**< \brief (TWI5) TWI Interrupt Mask Register */ +#define REG_TWI5_RHR (0x40008630U) /**< \brief (TWI5) TWI Receive Holding Register */ +#define REG_TWI5_THR (0x40008634U) /**< \brief (TWI5) TWI Transmit Holding Register */ +#define REG_TWI5_SMBTR (0x40008638U) /**< \brief (TWI5) TWI SMBus Timing Register */ +#define REG_TWI5_ACR (0x40008640U) /**< \brief (TWI5) TWI Alternative Command Register */ +#define REG_TWI5_FILTR (0x40008644U) /**< \brief (TWI5) TWI Filter Register */ +#define REG_TWI5_SWMR (0x4000864CU) /**< \brief (TWI5) TWI SleepWalking Matching Register */ +#define REG_TWI5_WPMR (0x400086E4U) /**< \brief (TWI5) TWI Write Protection Mode Register */ +#define REG_TWI5_WPSR (0x400086E8U) /**< \brief (TWI5) TWI Write Protection Status Register */ +#define REG_TWI5_RPR (0x40008700U) /**< \brief (TWI5) Receive Pointer Register */ +#define REG_TWI5_RCR (0x40008704U) /**< \brief (TWI5) Receive Counter Register */ +#define REG_TWI5_TPR (0x40008708U) /**< \brief (TWI5) Transmit Pointer Register */ +#define REG_TWI5_TCR (0x4000870CU) /**< \brief (TWI5) Transmit Counter Register */ +#define REG_TWI5_RNPR (0x40008710U) /**< \brief (TWI5) Receive Next Pointer Register */ +#define REG_TWI5_RNCR (0x40008714U) /**< \brief (TWI5) Receive Next Counter Register */ +#define REG_TWI5_TNPR (0x40008718U) /**< \brief (TWI5) Transmit Next Pointer Register */ +#define REG_TWI5_TNCR (0x4000871CU) /**< \brief (TWI5) Transmit Next Counter Register */ +#define REG_TWI5_PTCR (0x40008720U) /**< \brief (TWI5) Transfer Control Register */ +#define REG_TWI5_PTSR (0x40008724U) /**< \brief (TWI5) Transfer Status Register */ +#else +#define REG_TWI5_CR (*(__O uint32_t*)0x40008600U) /**< \brief (TWI5) TWI Control Register */ +#define REG_TWI5_MMR (*(__IO uint32_t*)0x40008604U) /**< \brief (TWI5) TWI Master Mode Register */ +#define REG_TWI5_SMR (*(__IO uint32_t*)0x40008608U) /**< \brief (TWI5) TWI Slave Mode Register */ +#define REG_TWI5_IADR (*(__IO uint32_t*)0x4000860CU) /**< \brief (TWI5) TWI Internal Address Register */ +#define REG_TWI5_CWGR (*(__IO uint32_t*)0x40008610U) /**< \brief (TWI5) TWI Clock Waveform Generator Register */ +#define REG_TWI5_SR (*(__I uint32_t*)0x40008620U) /**< \brief (TWI5) TWI Status Register */ +#define REG_TWI5_IER (*(__O uint32_t*)0x40008624U) /**< \brief (TWI5) TWI Interrupt Enable Register */ +#define REG_TWI5_IDR (*(__O uint32_t*)0x40008628U) /**< \brief (TWI5) TWI Interrupt Disable Register */ +#define REG_TWI5_IMR (*(__I uint32_t*)0x4000862CU) /**< \brief (TWI5) TWI Interrupt Mask Register */ +#define REG_TWI5_RHR (*(__I uint32_t*)0x40008630U) /**< \brief (TWI5) TWI Receive Holding Register */ +#define REG_TWI5_THR (*(__O uint32_t*)0x40008634U) /**< \brief (TWI5) TWI Transmit Holding Register */ +#define REG_TWI5_SMBTR (*(__IO uint32_t*)0x40008638U) /**< \brief (TWI5) TWI SMBus Timing Register */ +#define REG_TWI5_ACR (*(__IO uint32_t*)0x40008640U) /**< \brief (TWI5) TWI Alternative Command Register */ +#define REG_TWI5_FILTR (*(__IO uint32_t*)0x40008644U) /**< \brief (TWI5) TWI Filter Register */ +#define REG_TWI5_SWMR (*(__IO uint32_t*)0x4000864CU) /**< \brief (TWI5) TWI SleepWalking Matching Register */ +#define REG_TWI5_WPMR (*(__IO uint32_t*)0x400086E4U) /**< \brief (TWI5) TWI Write Protection Mode Register */ +#define REG_TWI5_WPSR (*(__I uint32_t*)0x400086E8U) /**< \brief (TWI5) TWI Write Protection Status Register */ +#define REG_TWI5_RPR (*(__IO uint32_t*)0x40008700U) /**< \brief (TWI5) Receive Pointer Register */ +#define REG_TWI5_RCR (*(__IO uint32_t*)0x40008704U) /**< \brief (TWI5) Receive Counter Register */ +#define REG_TWI5_TPR (*(__IO uint32_t*)0x40008708U) /**< \brief (TWI5) Transmit Pointer Register */ +#define REG_TWI5_TCR (*(__IO uint32_t*)0x4000870CU) /**< \brief (TWI5) Transmit Counter Register */ +#define REG_TWI5_RNPR (*(__IO uint32_t*)0x40008710U) /**< \brief (TWI5) Receive Next Pointer Register */ +#define REG_TWI5_RNCR (*(__IO uint32_t*)0x40008714U) /**< \brief (TWI5) Receive Next Counter Register */ +#define REG_TWI5_TNPR (*(__IO uint32_t*)0x40008718U) /**< \brief (TWI5) Transmit Next Pointer Register */ +#define REG_TWI5_TNCR (*(__IO uint32_t*)0x4000871CU) /**< \brief (TWI5) Transmit Next Counter Register */ +#define REG_TWI5_PTCR (*(__O uint32_t*)0x40008720U) /**< \brief (TWI5) Transfer Control Register */ +#define REG_TWI5_PTSR (*(__I uint32_t*)0x40008724U) /**< \brief (TWI5) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_TWI5_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi6.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,107 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_TWI6_INSTANCE_ +#define _SAMG55_TWI6_INSTANCE_ + +/* ========== Register definition for TWI6 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI6_CR (0x40040600U) /**< \brief (TWI6) TWI Control Register */ +#define REG_TWI6_MMR (0x40040604U) /**< \brief (TWI6) TWI Master Mode Register */ +#define REG_TWI6_SMR (0x40040608U) /**< \brief (TWI6) TWI Slave Mode Register */ +#define REG_TWI6_IADR (0x4004060CU) /**< \brief (TWI6) TWI Internal Address Register */ +#define REG_TWI6_CWGR (0x40040610U) /**< \brief (TWI6) TWI Clock Waveform Generator Register */ +#define REG_TWI6_SR (0x40040620U) /**< \brief (TWI6) TWI Status Register */ +#define REG_TWI6_IER (0x40040624U) /**< \brief (TWI6) TWI Interrupt Enable Register */ +#define REG_TWI6_IDR (0x40040628U) /**< \brief (TWI6) TWI Interrupt Disable Register */ +#define REG_TWI6_IMR (0x4004062CU) /**< \brief (TWI6) TWI Interrupt Mask Register */ +#define REG_TWI6_RHR (0x40040630U) /**< \brief (TWI6) TWI Receive Holding Register */ +#define REG_TWI6_THR (0x40040634U) /**< \brief (TWI6) TWI Transmit Holding Register */ +#define REG_TWI6_SMBTR (0x40040638U) /**< \brief (TWI6) TWI SMBus Timing Register */ +#define REG_TWI6_ACR (0x40040640U) /**< \brief (TWI6) TWI Alternative Command Register */ +#define REG_TWI6_FILTR (0x40040644U) /**< \brief (TWI6) TWI Filter Register */ +#define REG_TWI6_SWMR (0x4004064CU) /**< \brief (TWI6) TWI SleepWalking Matching Register */ +#define REG_TWI6_WPMR (0x400406E4U) /**< \brief (TWI6) TWI Write Protection Mode Register */ +#define REG_TWI6_WPSR (0x400406E8U) /**< \brief (TWI6) TWI Write Protection Status Register */ +#define REG_TWI6_RPR (0x40040700U) /**< \brief (TWI6) Receive Pointer Register */ +#define REG_TWI6_RCR (0x40040704U) /**< \brief (TWI6) Receive Counter Register */ +#define REG_TWI6_TPR (0x40040708U) /**< \brief (TWI6) Transmit Pointer Register */ +#define REG_TWI6_TCR (0x4004070CU) /**< \brief (TWI6) Transmit Counter Register */ +#define REG_TWI6_RNPR (0x40040710U) /**< \brief (TWI6) Receive Next Pointer Register */ +#define REG_TWI6_RNCR (0x40040714U) /**< \brief (TWI6) Receive Next Counter Register */ +#define REG_TWI6_TNPR (0x40040718U) /**< \brief (TWI6) Transmit Next Pointer Register */ +#define REG_TWI6_TNCR (0x4004071CU) /**< \brief (TWI6) Transmit Next Counter Register */ +#define REG_TWI6_PTCR (0x40040720U) /**< \brief (TWI6) Transfer Control Register */ +#define REG_TWI6_PTSR (0x40040724U) /**< \brief (TWI6) Transfer Status Register */ +#else +#define REG_TWI6_CR (*(__O uint32_t*)0x40040600U) /**< \brief (TWI6) TWI Control Register */ +#define REG_TWI6_MMR (*(__IO uint32_t*)0x40040604U) /**< \brief (TWI6) TWI Master Mode Register */ +#define REG_TWI6_SMR (*(__IO uint32_t*)0x40040608U) /**< \brief (TWI6) TWI Slave Mode Register */ +#define REG_TWI6_IADR (*(__IO uint32_t*)0x4004060CU) /**< \brief (TWI6) TWI Internal Address Register */ +#define REG_TWI6_CWGR (*(__IO uint32_t*)0x40040610U) /**< \brief (TWI6) TWI Clock Waveform Generator Register */ +#define REG_TWI6_SR (*(__I uint32_t*)0x40040620U) /**< \brief (TWI6) TWI Status Register */ +#define REG_TWI6_IER (*(__O uint32_t*)0x40040624U) /**< \brief (TWI6) TWI Interrupt Enable Register */ +#define REG_TWI6_IDR (*(__O uint32_t*)0x40040628U) /**< \brief (TWI6) TWI Interrupt Disable Register */ +#define REG_TWI6_IMR (*(__I uint32_t*)0x4004062CU) /**< \brief (TWI6) TWI Interrupt Mask Register */ +#define REG_TWI6_RHR (*(__I uint32_t*)0x40040630U) /**< \brief (TWI6) TWI Receive Holding Register */ +#define REG_TWI6_THR (*(__O uint32_t*)0x40040634U) /**< \brief (TWI6) TWI Transmit Holding Register */ +#define REG_TWI6_SMBTR (*(__IO uint32_t*)0x40040638U) /**< \brief (TWI6) TWI SMBus Timing Register */ +#define REG_TWI6_ACR (*(__IO uint32_t*)0x40040640U) /**< \brief (TWI6) TWI Alternative Command Register */ +#define REG_TWI6_FILTR (*(__IO uint32_t*)0x40040644U) /**< \brief (TWI6) TWI Filter Register */ +#define REG_TWI6_SWMR (*(__IO uint32_t*)0x4004064CU) /**< \brief (TWI6) TWI SleepWalking Matching Register */ +#define REG_TWI6_WPMR (*(__IO uint32_t*)0x400406E4U) /**< \brief (TWI6) TWI Write Protection Mode Register */ +#define REG_TWI6_WPSR (*(__I uint32_t*)0x400406E8U) /**< \brief (TWI6) TWI Write Protection Status Register */ +#define REG_TWI6_RPR (*(__IO uint32_t*)0x40040700U) /**< \brief (TWI6) Receive Pointer Register */ +#define REG_TWI6_RCR (*(__IO uint32_t*)0x40040704U) /**< \brief (TWI6) Receive Counter Register */ +#define REG_TWI6_TPR (*(__IO uint32_t*)0x40040708U) /**< \brief (TWI6) Transmit Pointer Register */ +#define REG_TWI6_TCR (*(__IO uint32_t*)0x4004070CU) /**< \brief (TWI6) Transmit Counter Register */ +#define REG_TWI6_RNPR (*(__IO uint32_t*)0x40040710U) /**< \brief (TWI6) Receive Next Pointer Register */ +#define REG_TWI6_RNCR (*(__IO uint32_t*)0x40040714U) /**< \brief (TWI6) Receive Next Counter Register */ +#define REG_TWI6_TNPR (*(__IO uint32_t*)0x40040718U) /**< \brief (TWI6) Transmit Next Pointer Register */ +#define REG_TWI6_TNCR (*(__IO uint32_t*)0x4004071CU) /**< \brief (TWI6) Transmit Next Counter Register */ +#define REG_TWI6_PTCR (*(__O uint32_t*)0x40040720U) /**< \brief (TWI6) Transfer Control Register */ +#define REG_TWI6_PTSR (*(__I uint32_t*)0x40040724U) /**< \brief (TWI6) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_TWI6_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_twi7.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,107 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_TWI7_INSTANCE_ +#define _SAMG55_TWI7_INSTANCE_ + +/* ========== Register definition for TWI7 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI7_CR (0x40034600U) /**< \brief (TWI7) TWI Control Register */ +#define REG_TWI7_MMR (0x40034604U) /**< \brief (TWI7) TWI Master Mode Register */ +#define REG_TWI7_SMR (0x40034608U) /**< \brief (TWI7) TWI Slave Mode Register */ +#define REG_TWI7_IADR (0x4003460CU) /**< \brief (TWI7) TWI Internal Address Register */ +#define REG_TWI7_CWGR (0x40034610U) /**< \brief (TWI7) TWI Clock Waveform Generator Register */ +#define REG_TWI7_SR (0x40034620U) /**< \brief (TWI7) TWI Status Register */ +#define REG_TWI7_IER (0x40034624U) /**< \brief (TWI7) TWI Interrupt Enable Register */ +#define REG_TWI7_IDR (0x40034628U) /**< \brief (TWI7) TWI Interrupt Disable Register */ +#define REG_TWI7_IMR (0x4003462CU) /**< \brief (TWI7) TWI Interrupt Mask Register */ +#define REG_TWI7_RHR (0x40034630U) /**< \brief (TWI7) TWI Receive Holding Register */ +#define REG_TWI7_THR (0x40034634U) /**< \brief (TWI7) TWI Transmit Holding Register */ +#define REG_TWI7_SMBTR (0x40034638U) /**< \brief (TWI7) TWI SMBus Timing Register */ +#define REG_TWI7_ACR (0x40034640U) /**< \brief (TWI7) TWI Alternative Command Register */ +#define REG_TWI7_FILTR (0x40034644U) /**< \brief (TWI7) TWI Filter Register */ +#define REG_TWI7_SWMR (0x4003464CU) /**< \brief (TWI7) TWI SleepWalking Matching Register */ +#define REG_TWI7_WPMR (0x400346E4U) /**< \brief (TWI7) TWI Write Protection Mode Register */ +#define REG_TWI7_WPSR (0x400346E8U) /**< \brief (TWI7) TWI Write Protection Status Register */ +#define REG_TWI7_RPR (0x40034700U) /**< \brief (TWI7) Receive Pointer Register */ +#define REG_TWI7_RCR (0x40034704U) /**< \brief (TWI7) Receive Counter Register */ +#define REG_TWI7_TPR (0x40034708U) /**< \brief (TWI7) Transmit Pointer Register */ +#define REG_TWI7_TCR (0x4003470CU) /**< \brief (TWI7) Transmit Counter Register */ +#define REG_TWI7_RNPR (0x40034710U) /**< \brief (TWI7) Receive Next Pointer Register */ +#define REG_TWI7_RNCR (0x40034714U) /**< \brief (TWI7) Receive Next Counter Register */ +#define REG_TWI7_TNPR (0x40034718U) /**< \brief (TWI7) Transmit Next Pointer Register */ +#define REG_TWI7_TNCR (0x4003471CU) /**< \brief (TWI7) Transmit Next Counter Register */ +#define REG_TWI7_PTCR (0x40034720U) /**< \brief (TWI7) Transfer Control Register */ +#define REG_TWI7_PTSR (0x40034724U) /**< \brief (TWI7) Transfer Status Register */ +#else +#define REG_TWI7_CR (*(__O uint32_t*)0x40034600U) /**< \brief (TWI7) TWI Control Register */ +#define REG_TWI7_MMR (*(__IO uint32_t*)0x40034604U) /**< \brief (TWI7) TWI Master Mode Register */ +#define REG_TWI7_SMR (*(__IO uint32_t*)0x40034608U) /**< \brief (TWI7) TWI Slave Mode Register */ +#define REG_TWI7_IADR (*(__IO uint32_t*)0x4003460CU) /**< \brief (TWI7) TWI Internal Address Register */ +#define REG_TWI7_CWGR (*(__IO uint32_t*)0x40034610U) /**< \brief (TWI7) TWI Clock Waveform Generator Register */ +#define REG_TWI7_SR (*(__I uint32_t*)0x40034620U) /**< \brief (TWI7) TWI Status Register */ +#define REG_TWI7_IER (*(__O uint32_t*)0x40034624U) /**< \brief (TWI7) TWI Interrupt Enable Register */ +#define REG_TWI7_IDR (*(__O uint32_t*)0x40034628U) /**< \brief (TWI7) TWI Interrupt Disable Register */ +#define REG_TWI7_IMR (*(__I uint32_t*)0x4003462CU) /**< \brief (TWI7) TWI Interrupt Mask Register */ +#define REG_TWI7_RHR (*(__I uint32_t*)0x40034630U) /**< \brief (TWI7) TWI Receive Holding Register */ +#define REG_TWI7_THR (*(__O uint32_t*)0x40034634U) /**< \brief (TWI7) TWI Transmit Holding Register */ +#define REG_TWI7_SMBTR (*(__IO uint32_t*)0x40034638U) /**< \brief (TWI7) TWI SMBus Timing Register */ +#define REG_TWI7_ACR (*(__IO uint32_t*)0x40034640U) /**< \brief (TWI7) TWI Alternative Command Register */ +#define REG_TWI7_FILTR (*(__IO uint32_t*)0x40034644U) /**< \brief (TWI7) TWI Filter Register */ +#define REG_TWI7_SWMR (*(__IO uint32_t*)0x4003464CU) /**< \brief (TWI7) TWI SleepWalking Matching Register */ +#define REG_TWI7_WPMR (*(__IO uint32_t*)0x400346E4U) /**< \brief (TWI7) TWI Write Protection Mode Register */ +#define REG_TWI7_WPSR (*(__I uint32_t*)0x400346E8U) /**< \brief (TWI7) TWI Write Protection Status Register */ +#define REG_TWI7_RPR (*(__IO uint32_t*)0x40034700U) /**< \brief (TWI7) Receive Pointer Register */ +#define REG_TWI7_RCR (*(__IO uint32_t*)0x40034704U) /**< \brief (TWI7) Receive Counter Register */ +#define REG_TWI7_TPR (*(__IO uint32_t*)0x40034708U) /**< \brief (TWI7) Transmit Pointer Register */ +#define REG_TWI7_TCR (*(__IO uint32_t*)0x4003470CU) /**< \brief (TWI7) Transmit Counter Register */ +#define REG_TWI7_RNPR (*(__IO uint32_t*)0x40034710U) /**< \brief (TWI7) Receive Next Pointer Register */ +#define REG_TWI7_RNCR (*(__IO uint32_t*)0x40034714U) /**< \brief (TWI7) Receive Next Counter Register */ +#define REG_TWI7_TNPR (*(__IO uint32_t*)0x40034718U) /**< \brief (TWI7) Transmit Next Pointer Register */ +#define REG_TWI7_TNCR (*(__IO uint32_t*)0x4003471CU) /**< \brief (TWI7) Transmit Next Counter Register */ +#define REG_TWI7_PTCR (*(__O uint32_t*)0x40034720U) /**< \brief (TWI7) Transfer Control Register */ +#define REG_TWI7_PTSR (*(__I uint32_t*)0x40034724U) /**< \brief (TWI7) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_TWI7_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_udp.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,77 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_UDP_INSTANCE_ +#define _SAMG55_UDP_INSTANCE_ + +/* ========== Register definition for UDP peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_UDP_FRM_NUM (0x40044000U) /**< \brief (UDP) Frame Number Register */ +#define REG_UDP_GLB_STAT (0x40044004U) /**< \brief (UDP) Global State Register */ +#define REG_UDP_FADDR (0x40044008U) /**< \brief (UDP) Function Address Register */ +#define REG_UDP_IER (0x40044010U) /**< \brief (UDP) Interrupt Enable Register */ +#define REG_UDP_IDR (0x40044014U) /**< \brief (UDP) Interrupt Disable Register */ +#define REG_UDP_IMR (0x40044018U) /**< \brief (UDP) Interrupt Mask Register */ +#define REG_UDP_ISR (0x4004401CU) /**< \brief (UDP) Interrupt Status Register */ +#define REG_UDP_ICR (0x40044020U) /**< \brief (UDP) Interrupt Clear Register */ +#define REG_UDP_RST_EP (0x40044028U) /**< \brief (UDP) Reset Endpoint Register */ +#define REG_UDP_CSR (0x40044030U) /**< \brief (UDP) Endpoint Control and Status Register */ +#define REG_UDP_FDR (0x40044050U) /**< \brief (UDP) Endpoint FIFO Data Register */ +#define REG_UDP_TXVC (0x40044074U) /**< \brief (UDP) Transceiver Control Register */ +#else +#define REG_UDP_FRM_NUM (*(__I uint32_t*)0x40044000U) /**< \brief (UDP) Frame Number Register */ +#define REG_UDP_GLB_STAT (*(__IO uint32_t*)0x40044004U) /**< \brief (UDP) Global State Register */ +#define REG_UDP_FADDR (*(__IO uint32_t*)0x40044008U) /**< \brief (UDP) Function Address Register */ +#define REG_UDP_IER (*(__O uint32_t*)0x40044010U) /**< \brief (UDP) Interrupt Enable Register */ +#define REG_UDP_IDR (*(__O uint32_t*)0x40044014U) /**< \brief (UDP) Interrupt Disable Register */ +#define REG_UDP_IMR (*(__I uint32_t*)0x40044018U) /**< \brief (UDP) Interrupt Mask Register */ +#define REG_UDP_ISR (*(__I uint32_t*)0x4004401CU) /**< \brief (UDP) Interrupt Status Register */ +#define REG_UDP_ICR (*(__O uint32_t*)0x40044020U) /**< \brief (UDP) Interrupt Clear Register */ +#define REG_UDP_RST_EP (*(__IO uint32_t*)0x40044028U) /**< \brief (UDP) Reset Endpoint Register */ +#define REG_UDP_CSR (*(__IO uint32_t*)0x40044030U) /**< \brief (UDP) Endpoint Control and Status Register */ +#define REG_UDP_FDR (*(__IO uint32_t*)0x40044050U) /**< \brief (UDP) Endpoint FIFO Data Register */ +#define REG_UDP_TXVC (*(__IO uint32_t*)0x40044074U) /**< \brief (UDP) Transceiver Control Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_UDP_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_uhp.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,97 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_UHP_INSTANCE_ +#define _SAMG55_UHP_INSTANCE_ + +/* ========== Register definition for UHP peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_UHP_HCREVISION (0x4004C000U) /**< \brief (UHP) OHCI Revision Number Register */ +#define REG_UHP_HCCONTROL (0x4004C004U) /**< \brief (UHP) HC Operating Mode Register */ +#define REG_UHP_HCCOMMANDSTATUS (0x4004C008U) /**< \brief (UHP) HC Command and Status Register */ +#define REG_UHP_HCINTERRUPTSTATUS (0x4004C00CU) /**< \brief (UHP) HC Interrupt and Status Register */ +#define REG_UHP_HCINTERRUPTENABLE (0x4004C010U) /**< \brief (UHP) HC Interrupt Enable Register */ +#define REG_UHP_HCINTERRUPTDISABLE (0x4004C014U) /**< \brief (UHP) HC Interrupt Disable Register */ +#define REG_UHP_HCHCCA (0x4004C018U) /**< \brief (UHP) HC HCCA Address Register */ +#define REG_UHP_HCPERIODCURRENTED (0x4004C01CU) /**< \brief (UHP) HC Current Periodic Register */ +#define REG_UHP_HCCONTROLHEADED (0x4004C020U) /**< \brief (UHP) HC Head Control Register */ +#define REG_UHP_HCCONTROLCURRENTED (0x4004C024U) /**< \brief (UHP) HC Current Control Register */ +#define REG_UHP_HCBULKHEADED (0x4004C028U) /**< \brief (UHP) HC Head Bulk Register */ +#define REG_UHP_HCBULKCURRENTED (0x4004C02CU) /**< \brief (UHP) HC Current Bulk Register */ +#define REG_UHP_HCDONEHEAD (0x4004C030U) /**< \brief (UHP) HC Head Done Register */ +#define REG_UHP_HCFMINTERVAL (0x4004C034U) /**< \brief (UHP) HC Frame Interval Register */ +#define REG_UHP_HCFMREMAINING (0x4004C038U) /**< \brief (UHP) HC Frame Remaining Register */ +#define REG_UHP_HCFMNUMBER (0x4004C03CU) /**< \brief (UHP) HC Frame Number Register */ +#define REG_UHP_HCPERIODICSTART (0x4004C040U) /**< \brief (UHP) HC Periodic Start Register */ +#define REG_UHP_HCLSTHRESHOLD (0x4004C044U) /**< \brief (UHP) HC Low-Speed Threshold Register */ +#define REG_UHP_HCRHDESCRIPTORA (0x4004C048U) /**< \brief (UHP) HC Root Hub A Register */ +#define REG_UHP_HCRHDESCRIPTORB (0x4004C04CU) /**< \brief (UHP) HC Root Hub B Register */ +#define REG_UHP_HCRHSTATUS (0x4004C050U) /**< \brief (UHP) HC Root Hub Status Register */ +#define REG_UHP_HCRHPORTSTATUS (0x4004C054U) /**< \brief (UHP) HC Port 1 Status and Control Register */ +#else +#define REG_UHP_HCREVISION (*(__I uint32_t*)0x4004C000U) /**< \brief (UHP) OHCI Revision Number Register */ +#define REG_UHP_HCCONTROL (*(__IO uint32_t*)0x4004C004U) /**< \brief (UHP) HC Operating Mode Register */ +#define REG_UHP_HCCOMMANDSTATUS (*(__IO uint32_t*)0x4004C008U) /**< \brief (UHP) HC Command and Status Register */ +#define REG_UHP_HCINTERRUPTSTATUS (*(__IO uint32_t*)0x4004C00CU) /**< \brief (UHP) HC Interrupt and Status Register */ +#define REG_UHP_HCINTERRUPTENABLE (*(__IO uint32_t*)0x4004C010U) /**< \brief (UHP) HC Interrupt Enable Register */ +#define REG_UHP_HCINTERRUPTDISABLE (*(__IO uint32_t*)0x4004C014U) /**< \brief (UHP) HC Interrupt Disable Register */ +#define REG_UHP_HCHCCA (*(__IO uint32_t*)0x4004C018U) /**< \brief (UHP) HC HCCA Address Register */ +#define REG_UHP_HCPERIODCURRENTED (*(__I uint32_t*)0x4004C01CU) /**< \brief (UHP) HC Current Periodic Register */ +#define REG_UHP_HCCONTROLHEADED (*(__IO uint32_t*)0x4004C020U) /**< \brief (UHP) HC Head Control Register */ +#define REG_UHP_HCCONTROLCURRENTED (*(__IO uint32_t*)0x4004C024U) /**< \brief (UHP) HC Current Control Register */ +#define REG_UHP_HCBULKHEADED (*(__IO uint32_t*)0x4004C028U) /**< \brief (UHP) HC Head Bulk Register */ +#define REG_UHP_HCBULKCURRENTED (*(__IO uint32_t*)0x4004C02CU) /**< \brief (UHP) HC Current Bulk Register */ +#define REG_UHP_HCDONEHEAD (*(__I uint32_t*)0x4004C030U) /**< \brief (UHP) HC Head Done Register */ +#define REG_UHP_HCFMINTERVAL (*(__IO uint32_t*)0x4004C034U) /**< \brief (UHP) HC Frame Interval Register */ +#define REG_UHP_HCFMREMAINING (*(__I uint32_t*)0x4004C038U) /**< \brief (UHP) HC Frame Remaining Register */ +#define REG_UHP_HCFMNUMBER (*(__I uint32_t*)0x4004C03CU) /**< \brief (UHP) HC Frame Number Register */ +#define REG_UHP_HCPERIODICSTART (*(__IO uint32_t*)0x4004C040U) /**< \brief (UHP) HC Periodic Start Register */ +#define REG_UHP_HCLSTHRESHOLD (*(__IO uint32_t*)0x4004C044U) /**< \brief (UHP) HC Low-Speed Threshold Register */ +#define REG_UHP_HCRHDESCRIPTORA (*(__IO uint32_t*)0x4004C048U) /**< \brief (UHP) HC Root Hub A Register */ +#define REG_UHP_HCRHDESCRIPTORB (*(__IO uint32_t*)0x4004C04CU) /**< \brief (UHP) HC Root Hub B Register */ +#define REG_UHP_HCRHSTATUS (*(__IO uint32_t*)0x4004C050U) /**< \brief (UHP) HC Root Hub Status Register */ +#define REG_UHP_HCRHPORTSTATUS (*(__IO uint32_t*)0x4004C054U) /**< \brief (UHP) HC Port 1 Status and Control Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_UHP_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart0.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,111 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_USART0_INSTANCE_ +#define _SAMG55_USART0_INSTANCE_ + +/* ========== Register definition for USART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART0_CR (0x4000C200U) /**< \brief (USART0) USART Control Register */ +#define REG_USART0_MR (0x4000C204U) /**< \brief (USART0) USART Mode Register */ +#define REG_USART0_IER (0x4000C208U) /**< \brief (USART0) USART Interrupt Enable Register */ +#define REG_USART0_IDR (0x4000C20CU) /**< \brief (USART0) USART Interrupt Disable Register */ +#define REG_USART0_IMR (0x4000C210U) /**< \brief (USART0) USART Interrupt Mask Register */ +#define REG_USART0_CSR (0x4000C214U) /**< \brief (USART0) USART Channel Status Register */ +#define REG_USART0_RHR (0x4000C218U) /**< \brief (USART0) USART Receive Holding Register */ +#define REG_USART0_THR (0x4000C21CU) /**< \brief (USART0) USART Transmit Holding Register */ +#define REG_USART0_BRGR (0x4000C220U) /**< \brief (USART0) USART Baud Rate Generator Register */ +#define REG_USART0_RTOR (0x4000C224U) /**< \brief (USART0) USART Receiver Time-out Register */ +#define REG_USART0_TTGR (0x4000C228U) /**< \brief (USART0) USART Transmitter Timeguard Register */ +#define REG_USART0_FIDI (0x4000C240U) /**< \brief (USART0) USART FI DI Ratio Register */ +#define REG_USART0_NER (0x4000C244U) /**< \brief (USART0) USART Number of Errors Register */ +#define REG_USART0_LINMR (0x4000C254U) /**< \brief (USART0) USART LIN Mode Register */ +#define REG_USART0_LINIR (0x4000C258U) /**< \brief (USART0) USART LIN Identifier Register */ +#define REG_USART0_LINBRR (0x4000C25CU) /**< \brief (USART0) USART LIN Baud Rate Register */ +#define REG_USART0_CMPR (0x4000C290U) /**< \brief (USART0) USART Comparison Register */ +#define REG_USART0_WPMR (0x4000C2E4U) /**< \brief (USART0) USART Write Protection Mode Register */ +#define REG_USART0_WPSR (0x4000C2E8U) /**< \brief (USART0) USART Write Protection Status Register */ +#define REG_USART0_RPR (0x4000C300U) /**< \brief (USART0) Receive Pointer Register */ +#define REG_USART0_RCR (0x4000C304U) /**< \brief (USART0) Receive Counter Register */ +#define REG_USART0_TPR (0x4000C308U) /**< \brief (USART0) Transmit Pointer Register */ +#define REG_USART0_TCR (0x4000C30CU) /**< \brief (USART0) Transmit Counter Register */ +#define REG_USART0_RNPR (0x4000C310U) /**< \brief (USART0) Receive Next Pointer Register */ +#define REG_USART0_RNCR (0x4000C314U) /**< \brief (USART0) Receive Next Counter Register */ +#define REG_USART0_TNPR (0x4000C318U) /**< \brief (USART0) Transmit Next Pointer Register */ +#define REG_USART0_TNCR (0x4000C31CU) /**< \brief (USART0) Transmit Next Counter Register */ +#define REG_USART0_PTCR (0x4000C320U) /**< \brief (USART0) Transfer Control Register */ +#define REG_USART0_PTSR (0x4000C324U) /**< \brief (USART0) Transfer Status Register */ +#else +#define REG_USART0_CR (*(__O uint32_t*)0x4000C200U) /**< \brief (USART0) USART Control Register */ +#define REG_USART0_MR (*(__IO uint32_t*)0x4000C204U) /**< \brief (USART0) USART Mode Register */ +#define REG_USART0_IER (*(__O uint32_t*)0x4000C208U) /**< \brief (USART0) USART Interrupt Enable Register */ +#define REG_USART0_IDR (*(__O uint32_t*)0x4000C20CU) /**< \brief (USART0) USART Interrupt Disable Register */ +#define REG_USART0_IMR (*(__I uint32_t*)0x4000C210U) /**< \brief (USART0) USART Interrupt Mask Register */ +#define REG_USART0_CSR (*(__I uint32_t*)0x4000C214U) /**< \brief (USART0) USART Channel Status Register */ +#define REG_USART0_RHR (*(__I uint32_t*)0x4000C218U) /**< \brief (USART0) USART Receive Holding Register */ +#define REG_USART0_THR (*(__O uint32_t*)0x4000C21CU) /**< \brief (USART0) USART Transmit Holding Register */ +#define REG_USART0_BRGR (*(__IO uint32_t*)0x4000C220U) /**< \brief (USART0) USART Baud Rate Generator Register */ +#define REG_USART0_RTOR (*(__IO uint32_t*)0x4000C224U) /**< \brief (USART0) USART Receiver Time-out Register */ +#define REG_USART0_TTGR (*(__IO uint32_t*)0x4000C228U) /**< \brief (USART0) USART Transmitter Timeguard Register */ +#define REG_USART0_FIDI (*(__IO uint32_t*)0x4000C240U) /**< \brief (USART0) USART FI DI Ratio Register */ +#define REG_USART0_NER (*(__I uint32_t*)0x4000C244U) /**< \brief (USART0) USART Number of Errors Register */ +#define REG_USART0_LINMR (*(__IO uint32_t*)0x4000C254U) /**< \brief (USART0) USART LIN Mode Register */ +#define REG_USART0_LINIR (*(__IO uint32_t*)0x4000C258U) /**< \brief (USART0) USART LIN Identifier Register */ +#define REG_USART0_LINBRR (*(__I uint32_t*)0x4000C25CU) /**< \brief (USART0) USART LIN Baud Rate Register */ +#define REG_USART0_CMPR (*(__IO uint32_t*)0x4000C290U) /**< \brief (USART0) USART Comparison Register */ +#define REG_USART0_WPMR (*(__IO uint32_t*)0x4000C2E4U) /**< \brief (USART0) USART Write Protection Mode Register */ +#define REG_USART0_WPSR (*(__I uint32_t*)0x4000C2E8U) /**< \brief (USART0) USART Write Protection Status Register */ +#define REG_USART0_RPR (*(__IO uint32_t*)0x4000C300U) /**< \brief (USART0) Receive Pointer Register */ +#define REG_USART0_RCR (*(__IO uint32_t*)0x4000C304U) /**< \brief (USART0) Receive Counter Register */ +#define REG_USART0_TPR (*(__IO uint32_t*)0x4000C308U) /**< \brief (USART0) Transmit Pointer Register */ +#define REG_USART0_TCR (*(__IO uint32_t*)0x4000C30CU) /**< \brief (USART0) Transmit Counter Register */ +#define REG_USART0_RNPR (*(__IO uint32_t*)0x4000C310U) /**< \brief (USART0) Receive Next Pointer Register */ +#define REG_USART0_RNCR (*(__IO uint32_t*)0x4000C314U) /**< \brief (USART0) Receive Next Counter Register */ +#define REG_USART0_TNPR (*(__IO uint32_t*)0x4000C318U) /**< \brief (USART0) Transmit Next Pointer Register */ +#define REG_USART0_TNCR (*(__IO uint32_t*)0x4000C31CU) /**< \brief (USART0) Transmit Next Counter Register */ +#define REG_USART0_PTCR (*(__O uint32_t*)0x4000C320U) /**< \brief (USART0) Transfer Control Register */ +#define REG_USART0_PTSR (*(__I uint32_t*)0x4000C324U) /**< \brief (USART0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_USART0_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart1.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,111 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_USART1_INSTANCE_ +#define _SAMG55_USART1_INSTANCE_ + +/* ========== Register definition for USART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART1_CR (0x40020200U) /**< \brief (USART1) USART Control Register */ +#define REG_USART1_MR (0x40020204U) /**< \brief (USART1) USART Mode Register */ +#define REG_USART1_IER (0x40020208U) /**< \brief (USART1) USART Interrupt Enable Register */ +#define REG_USART1_IDR (0x4002020CU) /**< \brief (USART1) USART Interrupt Disable Register */ +#define REG_USART1_IMR (0x40020210U) /**< \brief (USART1) USART Interrupt Mask Register */ +#define REG_USART1_CSR (0x40020214U) /**< \brief (USART1) USART Channel Status Register */ +#define REG_USART1_RHR (0x40020218U) /**< \brief (USART1) USART Receive Holding Register */ +#define REG_USART1_THR (0x4002021CU) /**< \brief (USART1) USART Transmit Holding Register */ +#define REG_USART1_BRGR (0x40020220U) /**< \brief (USART1) USART Baud Rate Generator Register */ +#define REG_USART1_RTOR (0x40020224U) /**< \brief (USART1) USART Receiver Time-out Register */ +#define REG_USART1_TTGR (0x40020228U) /**< \brief (USART1) USART Transmitter Timeguard Register */ +#define REG_USART1_FIDI (0x40020240U) /**< \brief (USART1) USART FI DI Ratio Register */ +#define REG_USART1_NER (0x40020244U) /**< \brief (USART1) USART Number of Errors Register */ +#define REG_USART1_LINMR (0x40020254U) /**< \brief (USART1) USART LIN Mode Register */ +#define REG_USART1_LINIR (0x40020258U) /**< \brief (USART1) USART LIN Identifier Register */ +#define REG_USART1_LINBRR (0x4002025CU) /**< \brief (USART1) USART LIN Baud Rate Register */ +#define REG_USART1_CMPR (0x40020290U) /**< \brief (USART1) USART Comparison Register */ +#define REG_USART1_WPMR (0x400202E4U) /**< \brief (USART1) USART Write Protection Mode Register */ +#define REG_USART1_WPSR (0x400202E8U) /**< \brief (USART1) USART Write Protection Status Register */ +#define REG_USART1_RPR (0x40020300U) /**< \brief (USART1) Receive Pointer Register */ +#define REG_USART1_RCR (0x40020304U) /**< \brief (USART1) Receive Counter Register */ +#define REG_USART1_TPR (0x40020308U) /**< \brief (USART1) Transmit Pointer Register */ +#define REG_USART1_TCR (0x4002030CU) /**< \brief (USART1) Transmit Counter Register */ +#define REG_USART1_RNPR (0x40020310U) /**< \brief (USART1) Receive Next Pointer Register */ +#define REG_USART1_RNCR (0x40020314U) /**< \brief (USART1) Receive Next Counter Register */ +#define REG_USART1_TNPR (0x40020318U) /**< \brief (USART1) Transmit Next Pointer Register */ +#define REG_USART1_TNCR (0x4002031CU) /**< \brief (USART1) Transmit Next Counter Register */ +#define REG_USART1_PTCR (0x40020320U) /**< \brief (USART1) Transfer Control Register */ +#define REG_USART1_PTSR (0x40020324U) /**< \brief (USART1) Transfer Status Register */ +#else +#define REG_USART1_CR (*(__O uint32_t*)0x40020200U) /**< \brief (USART1) USART Control Register */ +#define REG_USART1_MR (*(__IO uint32_t*)0x40020204U) /**< \brief (USART1) USART Mode Register */ +#define REG_USART1_IER (*(__O uint32_t*)0x40020208U) /**< \brief (USART1) USART Interrupt Enable Register */ +#define REG_USART1_IDR (*(__O uint32_t*)0x4002020CU) /**< \brief (USART1) USART Interrupt Disable Register */ +#define REG_USART1_IMR (*(__I uint32_t*)0x40020210U) /**< \brief (USART1) USART Interrupt Mask Register */ +#define REG_USART1_CSR (*(__I uint32_t*)0x40020214U) /**< \brief (USART1) USART Channel Status Register */ +#define REG_USART1_RHR (*(__I uint32_t*)0x40020218U) /**< \brief (USART1) USART Receive Holding Register */ +#define REG_USART1_THR (*(__O uint32_t*)0x4002021CU) /**< \brief (USART1) USART Transmit Holding Register */ +#define REG_USART1_BRGR (*(__IO uint32_t*)0x40020220U) /**< \brief (USART1) USART Baud Rate Generator Register */ +#define REG_USART1_RTOR (*(__IO uint32_t*)0x40020224U) /**< \brief (USART1) USART Receiver Time-out Register */ +#define REG_USART1_TTGR (*(__IO uint32_t*)0x40020228U) /**< \brief (USART1) USART Transmitter Timeguard Register */ +#define REG_USART1_FIDI (*(__IO uint32_t*)0x40020240U) /**< \brief (USART1) USART FI DI Ratio Register */ +#define REG_USART1_NER (*(__I uint32_t*)0x40020244U) /**< \brief (USART1) USART Number of Errors Register */ +#define REG_USART1_LINMR (*(__IO uint32_t*)0x40020254U) /**< \brief (USART1) USART LIN Mode Register */ +#define REG_USART1_LINIR (*(__IO uint32_t*)0x40020258U) /**< \brief (USART1) USART LIN Identifier Register */ +#define REG_USART1_LINBRR (*(__I uint32_t*)0x4002025CU) /**< \brief (USART1) USART LIN Baud Rate Register */ +#define REG_USART1_CMPR (*(__IO uint32_t*)0x40020290U) /**< \brief (USART1) USART Comparison Register */ +#define REG_USART1_WPMR (*(__IO uint32_t*)0x400202E4U) /**< \brief (USART1) USART Write Protection Mode Register */ +#define REG_USART1_WPSR (*(__I uint32_t*)0x400202E8U) /**< \brief (USART1) USART Write Protection Status Register */ +#define REG_USART1_RPR (*(__IO uint32_t*)0x40020300U) /**< \brief (USART1) Receive Pointer Register */ +#define REG_USART1_RCR (*(__IO uint32_t*)0x40020304U) /**< \brief (USART1) Receive Counter Register */ +#define REG_USART1_TPR (*(__IO uint32_t*)0x40020308U) /**< \brief (USART1) Transmit Pointer Register */ +#define REG_USART1_TCR (*(__IO uint32_t*)0x4002030CU) /**< \brief (USART1) Transmit Counter Register */ +#define REG_USART1_RNPR (*(__IO uint32_t*)0x40020310U) /**< \brief (USART1) Receive Next Pointer Register */ +#define REG_USART1_RNCR (*(__IO uint32_t*)0x40020314U) /**< \brief (USART1) Receive Next Counter Register */ +#define REG_USART1_TNPR (*(__IO uint32_t*)0x40020318U) /**< \brief (USART1) Transmit Next Pointer Register */ +#define REG_USART1_TNCR (*(__IO uint32_t*)0x4002031CU) /**< \brief (USART1) Transmit Next Counter Register */ +#define REG_USART1_PTCR (*(__O uint32_t*)0x40020320U) /**< \brief (USART1) Transfer Control Register */ +#define REG_USART1_PTSR (*(__I uint32_t*)0x40020324U) /**< \brief (USART1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_USART1_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart2.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,111 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_USART2_INSTANCE_ +#define _SAMG55_USART2_INSTANCE_ + +/* ========== Register definition for USART2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART2_CR (0x40024200U) /**< \brief (USART2) USART Control Register */ +#define REG_USART2_MR (0x40024204U) /**< \brief (USART2) USART Mode Register */ +#define REG_USART2_IER (0x40024208U) /**< \brief (USART2) USART Interrupt Enable Register */ +#define REG_USART2_IDR (0x4002420CU) /**< \brief (USART2) USART Interrupt Disable Register */ +#define REG_USART2_IMR (0x40024210U) /**< \brief (USART2) USART Interrupt Mask Register */ +#define REG_USART2_CSR (0x40024214U) /**< \brief (USART2) USART Channel Status Register */ +#define REG_USART2_RHR (0x40024218U) /**< \brief (USART2) USART Receive Holding Register */ +#define REG_USART2_THR (0x4002421CU) /**< \brief (USART2) USART Transmit Holding Register */ +#define REG_USART2_BRGR (0x40024220U) /**< \brief (USART2) USART Baud Rate Generator Register */ +#define REG_USART2_RTOR (0x40024224U) /**< \brief (USART2) USART Receiver Time-out Register */ +#define REG_USART2_TTGR (0x40024228U) /**< \brief (USART2) USART Transmitter Timeguard Register */ +#define REG_USART2_FIDI (0x40024240U) /**< \brief (USART2) USART FI DI Ratio Register */ +#define REG_USART2_NER (0x40024244U) /**< \brief (USART2) USART Number of Errors Register */ +#define REG_USART2_LINMR (0x40024254U) /**< \brief (USART2) USART LIN Mode Register */ +#define REG_USART2_LINIR (0x40024258U) /**< \brief (USART2) USART LIN Identifier Register */ +#define REG_USART2_LINBRR (0x4002425CU) /**< \brief (USART2) USART LIN Baud Rate Register */ +#define REG_USART2_CMPR (0x40024290U) /**< \brief (USART2) USART Comparison Register */ +#define REG_USART2_WPMR (0x400242E4U) /**< \brief (USART2) USART Write Protection Mode Register */ +#define REG_USART2_WPSR (0x400242E8U) /**< \brief (USART2) USART Write Protection Status Register */ +#define REG_USART2_RPR (0x40024300U) /**< \brief (USART2) Receive Pointer Register */ +#define REG_USART2_RCR (0x40024304U) /**< \brief (USART2) Receive Counter Register */ +#define REG_USART2_TPR (0x40024308U) /**< \brief (USART2) Transmit Pointer Register */ +#define REG_USART2_TCR (0x4002430CU) /**< \brief (USART2) Transmit Counter Register */ +#define REG_USART2_RNPR (0x40024310U) /**< \brief (USART2) Receive Next Pointer Register */ +#define REG_USART2_RNCR (0x40024314U) /**< \brief (USART2) Receive Next Counter Register */ +#define REG_USART2_TNPR (0x40024318U) /**< \brief (USART2) Transmit Next Pointer Register */ +#define REG_USART2_TNCR (0x4002431CU) /**< \brief (USART2) Transmit Next Counter Register */ +#define REG_USART2_PTCR (0x40024320U) /**< \brief (USART2) Transfer Control Register */ +#define REG_USART2_PTSR (0x40024324U) /**< \brief (USART2) Transfer Status Register */ +#else +#define REG_USART2_CR (*(__O uint32_t*)0x40024200U) /**< \brief (USART2) USART Control Register */ +#define REG_USART2_MR (*(__IO uint32_t*)0x40024204U) /**< \brief (USART2) USART Mode Register */ +#define REG_USART2_IER (*(__O uint32_t*)0x40024208U) /**< \brief (USART2) USART Interrupt Enable Register */ +#define REG_USART2_IDR (*(__O uint32_t*)0x4002420CU) /**< \brief (USART2) USART Interrupt Disable Register */ +#define REG_USART2_IMR (*(__I uint32_t*)0x40024210U) /**< \brief (USART2) USART Interrupt Mask Register */ +#define REG_USART2_CSR (*(__I uint32_t*)0x40024214U) /**< \brief (USART2) USART Channel Status Register */ +#define REG_USART2_RHR (*(__I uint32_t*)0x40024218U) /**< \brief (USART2) USART Receive Holding Register */ +#define REG_USART2_THR (*(__O uint32_t*)0x4002421CU) /**< \brief (USART2) USART Transmit Holding Register */ +#define REG_USART2_BRGR (*(__IO uint32_t*)0x40024220U) /**< \brief (USART2) USART Baud Rate Generator Register */ +#define REG_USART2_RTOR (*(__IO uint32_t*)0x40024224U) /**< \brief (USART2) USART Receiver Time-out Register */ +#define REG_USART2_TTGR (*(__IO uint32_t*)0x40024228U) /**< \brief (USART2) USART Transmitter Timeguard Register */ +#define REG_USART2_FIDI (*(__IO uint32_t*)0x40024240U) /**< \brief (USART2) USART FI DI Ratio Register */ +#define REG_USART2_NER (*(__I uint32_t*)0x40024244U) /**< \brief (USART2) USART Number of Errors Register */ +#define REG_USART2_LINMR (*(__IO uint32_t*)0x40024254U) /**< \brief (USART2) USART LIN Mode Register */ +#define REG_USART2_LINIR (*(__IO uint32_t*)0x40024258U) /**< \brief (USART2) USART LIN Identifier Register */ +#define REG_USART2_LINBRR (*(__I uint32_t*)0x4002425CU) /**< \brief (USART2) USART LIN Baud Rate Register */ +#define REG_USART2_CMPR (*(__IO uint32_t*)0x40024290U) /**< \brief (USART2) USART Comparison Register */ +#define REG_USART2_WPMR (*(__IO uint32_t*)0x400242E4U) /**< \brief (USART2) USART Write Protection Mode Register */ +#define REG_USART2_WPSR (*(__I uint32_t*)0x400242E8U) /**< \brief (USART2) USART Write Protection Status Register */ +#define REG_USART2_RPR (*(__IO uint32_t*)0x40024300U) /**< \brief (USART2) Receive Pointer Register */ +#define REG_USART2_RCR (*(__IO uint32_t*)0x40024304U) /**< \brief (USART2) Receive Counter Register */ +#define REG_USART2_TPR (*(__IO uint32_t*)0x40024308U) /**< \brief (USART2) Transmit Pointer Register */ +#define REG_USART2_TCR (*(__IO uint32_t*)0x4002430CU) /**< \brief (USART2) Transmit Counter Register */ +#define REG_USART2_RNPR (*(__IO uint32_t*)0x40024310U) /**< \brief (USART2) Receive Next Pointer Register */ +#define REG_USART2_RNCR (*(__IO uint32_t*)0x40024314U) /**< \brief (USART2) Receive Next Counter Register */ +#define REG_USART2_TNPR (*(__IO uint32_t*)0x40024318U) /**< \brief (USART2) Transmit Next Pointer Register */ +#define REG_USART2_TNCR (*(__IO uint32_t*)0x4002431CU) /**< \brief (USART2) Transmit Next Counter Register */ +#define REG_USART2_PTCR (*(__O uint32_t*)0x40024320U) /**< \brief (USART2) Transfer Control Register */ +#define REG_USART2_PTSR (*(__I uint32_t*)0x40024324U) /**< \brief (USART2) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_USART2_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart3.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,111 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_USART3_INSTANCE_ +#define _SAMG55_USART3_INSTANCE_ + +/* ========== Register definition for USART3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART3_CR (0x40018200U) /**< \brief (USART3) USART Control Register */ +#define REG_USART3_MR (0x40018204U) /**< \brief (USART3) USART Mode Register */ +#define REG_USART3_IER (0x40018208U) /**< \brief (USART3) USART Interrupt Enable Register */ +#define REG_USART3_IDR (0x4001820CU) /**< \brief (USART3) USART Interrupt Disable Register */ +#define REG_USART3_IMR (0x40018210U) /**< \brief (USART3) USART Interrupt Mask Register */ +#define REG_USART3_CSR (0x40018214U) /**< \brief (USART3) USART Channel Status Register */ +#define REG_USART3_RHR (0x40018218U) /**< \brief (USART3) USART Receive Holding Register */ +#define REG_USART3_THR (0x4001821CU) /**< \brief (USART3) USART Transmit Holding Register */ +#define REG_USART3_BRGR (0x40018220U) /**< \brief (USART3) USART Baud Rate Generator Register */ +#define REG_USART3_RTOR (0x40018224U) /**< \brief (USART3) USART Receiver Time-out Register */ +#define REG_USART3_TTGR (0x40018228U) /**< \brief (USART3) USART Transmitter Timeguard Register */ +#define REG_USART3_FIDI (0x40018240U) /**< \brief (USART3) USART FI DI Ratio Register */ +#define REG_USART3_NER (0x40018244U) /**< \brief (USART3) USART Number of Errors Register */ +#define REG_USART3_LINMR (0x40018254U) /**< \brief (USART3) USART LIN Mode Register */ +#define REG_USART3_LINIR (0x40018258U) /**< \brief (USART3) USART LIN Identifier Register */ +#define REG_USART3_LINBRR (0x4001825CU) /**< \brief (USART3) USART LIN Baud Rate Register */ +#define REG_USART3_CMPR (0x40018290U) /**< \brief (USART3) USART Comparison Register */ +#define REG_USART3_WPMR (0x400182E4U) /**< \brief (USART3) USART Write Protection Mode Register */ +#define REG_USART3_WPSR (0x400182E8U) /**< \brief (USART3) USART Write Protection Status Register */ +#define REG_USART3_RPR (0x40018300U) /**< \brief (USART3) Receive Pointer Register */ +#define REG_USART3_RCR (0x40018304U) /**< \brief (USART3) Receive Counter Register */ +#define REG_USART3_TPR (0x40018308U) /**< \brief (USART3) Transmit Pointer Register */ +#define REG_USART3_TCR (0x4001830CU) /**< \brief (USART3) Transmit Counter Register */ +#define REG_USART3_RNPR (0x40018310U) /**< \brief (USART3) Receive Next Pointer Register */ +#define REG_USART3_RNCR (0x40018314U) /**< \brief (USART3) Receive Next Counter Register */ +#define REG_USART3_TNPR (0x40018318U) /**< \brief (USART3) Transmit Next Pointer Register */ +#define REG_USART3_TNCR (0x4001831CU) /**< \brief (USART3) Transmit Next Counter Register */ +#define REG_USART3_PTCR (0x40018320U) /**< \brief (USART3) Transfer Control Register */ +#define REG_USART3_PTSR (0x40018324U) /**< \brief (USART3) Transfer Status Register */ +#else +#define REG_USART3_CR (*(__O uint32_t*)0x40018200U) /**< \brief (USART3) USART Control Register */ +#define REG_USART3_MR (*(__IO uint32_t*)0x40018204U) /**< \brief (USART3) USART Mode Register */ +#define REG_USART3_IER (*(__O uint32_t*)0x40018208U) /**< \brief (USART3) USART Interrupt Enable Register */ +#define REG_USART3_IDR (*(__O uint32_t*)0x4001820CU) /**< \brief (USART3) USART Interrupt Disable Register */ +#define REG_USART3_IMR (*(__I uint32_t*)0x40018210U) /**< \brief (USART3) USART Interrupt Mask Register */ +#define REG_USART3_CSR (*(__I uint32_t*)0x40018214U) /**< \brief (USART3) USART Channel Status Register */ +#define REG_USART3_RHR (*(__I uint32_t*)0x40018218U) /**< \brief (USART3) USART Receive Holding Register */ +#define REG_USART3_THR (*(__O uint32_t*)0x4001821CU) /**< \brief (USART3) USART Transmit Holding Register */ +#define REG_USART3_BRGR (*(__IO uint32_t*)0x40018220U) /**< \brief (USART3) USART Baud Rate Generator Register */ +#define REG_USART3_RTOR (*(__IO uint32_t*)0x40018224U) /**< \brief (USART3) USART Receiver Time-out Register */ +#define REG_USART3_TTGR (*(__IO uint32_t*)0x40018228U) /**< \brief (USART3) USART Transmitter Timeguard Register */ +#define REG_USART3_FIDI (*(__IO uint32_t*)0x40018240U) /**< \brief (USART3) USART FI DI Ratio Register */ +#define REG_USART3_NER (*(__I uint32_t*)0x40018244U) /**< \brief (USART3) USART Number of Errors Register */ +#define REG_USART3_LINMR (*(__IO uint32_t*)0x40018254U) /**< \brief (USART3) USART LIN Mode Register */ +#define REG_USART3_LINIR (*(__IO uint32_t*)0x40018258U) /**< \brief (USART3) USART LIN Identifier Register */ +#define REG_USART3_LINBRR (*(__I uint32_t*)0x4001825CU) /**< \brief (USART3) USART LIN Baud Rate Register */ +#define REG_USART3_CMPR (*(__IO uint32_t*)0x40018290U) /**< \brief (USART3) USART Comparison Register */ +#define REG_USART3_WPMR (*(__IO uint32_t*)0x400182E4U) /**< \brief (USART3) USART Write Protection Mode Register */ +#define REG_USART3_WPSR (*(__I uint32_t*)0x400182E8U) /**< \brief (USART3) USART Write Protection Status Register */ +#define REG_USART3_RPR (*(__IO uint32_t*)0x40018300U) /**< \brief (USART3) Receive Pointer Register */ +#define REG_USART3_RCR (*(__IO uint32_t*)0x40018304U) /**< \brief (USART3) Receive Counter Register */ +#define REG_USART3_TPR (*(__IO uint32_t*)0x40018308U) /**< \brief (USART3) Transmit Pointer Register */ +#define REG_USART3_TCR (*(__IO uint32_t*)0x4001830CU) /**< \brief (USART3) Transmit Counter Register */ +#define REG_USART3_RNPR (*(__IO uint32_t*)0x40018310U) /**< \brief (USART3) Receive Next Pointer Register */ +#define REG_USART3_RNCR (*(__IO uint32_t*)0x40018314U) /**< \brief (USART3) Receive Next Counter Register */ +#define REG_USART3_TNPR (*(__IO uint32_t*)0x40018318U) /**< \brief (USART3) Transmit Next Pointer Register */ +#define REG_USART3_TNCR (*(__IO uint32_t*)0x4001831CU) /**< \brief (USART3) Transmit Next Counter Register */ +#define REG_USART3_PTCR (*(__O uint32_t*)0x40018320U) /**< \brief (USART3) Transfer Control Register */ +#define REG_USART3_PTSR (*(__I uint32_t*)0x40018324U) /**< \brief (USART3) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_USART3_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart4.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,111 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_USART4_INSTANCE_ +#define _SAMG55_USART4_INSTANCE_ + +/* ========== Register definition for USART4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART4_CR (0x4001C200U) /**< \brief (USART4) USART Control Register */ +#define REG_USART4_MR (0x4001C204U) /**< \brief (USART4) USART Mode Register */ +#define REG_USART4_IER (0x4001C208U) /**< \brief (USART4) USART Interrupt Enable Register */ +#define REG_USART4_IDR (0x4001C20CU) /**< \brief (USART4) USART Interrupt Disable Register */ +#define REG_USART4_IMR (0x4001C210U) /**< \brief (USART4) USART Interrupt Mask Register */ +#define REG_USART4_CSR (0x4001C214U) /**< \brief (USART4) USART Channel Status Register */ +#define REG_USART4_RHR (0x4001C218U) /**< \brief (USART4) USART Receive Holding Register */ +#define REG_USART4_THR (0x4001C21CU) /**< \brief (USART4) USART Transmit Holding Register */ +#define REG_USART4_BRGR (0x4001C220U) /**< \brief (USART4) USART Baud Rate Generator Register */ +#define REG_USART4_RTOR (0x4001C224U) /**< \brief (USART4) USART Receiver Time-out Register */ +#define REG_USART4_TTGR (0x4001C228U) /**< \brief (USART4) USART Transmitter Timeguard Register */ +#define REG_USART4_FIDI (0x4001C240U) /**< \brief (USART4) USART FI DI Ratio Register */ +#define REG_USART4_NER (0x4001C244U) /**< \brief (USART4) USART Number of Errors Register */ +#define REG_USART4_LINMR (0x4001C254U) /**< \brief (USART4) USART LIN Mode Register */ +#define REG_USART4_LINIR (0x4001C258U) /**< \brief (USART4) USART LIN Identifier Register */ +#define REG_USART4_LINBRR (0x4001C25CU) /**< \brief (USART4) USART LIN Baud Rate Register */ +#define REG_USART4_CMPR (0x4001C290U) /**< \brief (USART4) USART Comparison Register */ +#define REG_USART4_WPMR (0x4001C2E4U) /**< \brief (USART4) USART Write Protection Mode Register */ +#define REG_USART4_WPSR (0x4001C2E8U) /**< \brief (USART4) USART Write Protection Status Register */ +#define REG_USART4_RPR (0x4001C300U) /**< \brief (USART4) Receive Pointer Register */ +#define REG_USART4_RCR (0x4001C304U) /**< \brief (USART4) Receive Counter Register */ +#define REG_USART4_TPR (0x4001C308U) /**< \brief (USART4) Transmit Pointer Register */ +#define REG_USART4_TCR (0x4001C30CU) /**< \brief (USART4) Transmit Counter Register */ +#define REG_USART4_RNPR (0x4001C310U) /**< \brief (USART4) Receive Next Pointer Register */ +#define REG_USART4_RNCR (0x4001C314U) /**< \brief (USART4) Receive Next Counter Register */ +#define REG_USART4_TNPR (0x4001C318U) /**< \brief (USART4) Transmit Next Pointer Register */ +#define REG_USART4_TNCR (0x4001C31CU) /**< \brief (USART4) Transmit Next Counter Register */ +#define REG_USART4_PTCR (0x4001C320U) /**< \brief (USART4) Transfer Control Register */ +#define REG_USART4_PTSR (0x4001C324U) /**< \brief (USART4) Transfer Status Register */ +#else +#define REG_USART4_CR (*(__O uint32_t*)0x4001C200U) /**< \brief (USART4) USART Control Register */ +#define REG_USART4_MR (*(__IO uint32_t*)0x4001C204U) /**< \brief (USART4) USART Mode Register */ +#define REG_USART4_IER (*(__O uint32_t*)0x4001C208U) /**< \brief (USART4) USART Interrupt Enable Register */ +#define REG_USART4_IDR (*(__O uint32_t*)0x4001C20CU) /**< \brief (USART4) USART Interrupt Disable Register */ +#define REG_USART4_IMR (*(__I uint32_t*)0x4001C210U) /**< \brief (USART4) USART Interrupt Mask Register */ +#define REG_USART4_CSR (*(__I uint32_t*)0x4001C214U) /**< \brief (USART4) USART Channel Status Register */ +#define REG_USART4_RHR (*(__I uint32_t*)0x4001C218U) /**< \brief (USART4) USART Receive Holding Register */ +#define REG_USART4_THR (*(__O uint32_t*)0x4001C21CU) /**< \brief (USART4) USART Transmit Holding Register */ +#define REG_USART4_BRGR (*(__IO uint32_t*)0x4001C220U) /**< \brief (USART4) USART Baud Rate Generator Register */ +#define REG_USART4_RTOR (*(__IO uint32_t*)0x4001C224U) /**< \brief (USART4) USART Receiver Time-out Register */ +#define REG_USART4_TTGR (*(__IO uint32_t*)0x4001C228U) /**< \brief (USART4) USART Transmitter Timeguard Register */ +#define REG_USART4_FIDI (*(__IO uint32_t*)0x4001C240U) /**< \brief (USART4) USART FI DI Ratio Register */ +#define REG_USART4_NER (*(__I uint32_t*)0x4001C244U) /**< \brief (USART4) USART Number of Errors Register */ +#define REG_USART4_LINMR (*(__IO uint32_t*)0x4001C254U) /**< \brief (USART4) USART LIN Mode Register */ +#define REG_USART4_LINIR (*(__IO uint32_t*)0x4001C258U) /**< \brief (USART4) USART LIN Identifier Register */ +#define REG_USART4_LINBRR (*(__I uint32_t*)0x4001C25CU) /**< \brief (USART4) USART LIN Baud Rate Register */ +#define REG_USART4_CMPR (*(__IO uint32_t*)0x4001C290U) /**< \brief (USART4) USART Comparison Register */ +#define REG_USART4_WPMR (*(__IO uint32_t*)0x4001C2E4U) /**< \brief (USART4) USART Write Protection Mode Register */ +#define REG_USART4_WPSR (*(__I uint32_t*)0x4001C2E8U) /**< \brief (USART4) USART Write Protection Status Register */ +#define REG_USART4_RPR (*(__IO uint32_t*)0x4001C300U) /**< \brief (USART4) Receive Pointer Register */ +#define REG_USART4_RCR (*(__IO uint32_t*)0x4001C304U) /**< \brief (USART4) Receive Counter Register */ +#define REG_USART4_TPR (*(__IO uint32_t*)0x4001C308U) /**< \brief (USART4) Transmit Pointer Register */ +#define REG_USART4_TCR (*(__IO uint32_t*)0x4001C30CU) /**< \brief (USART4) Transmit Counter Register */ +#define REG_USART4_RNPR (*(__IO uint32_t*)0x4001C310U) /**< \brief (USART4) Receive Next Pointer Register */ +#define REG_USART4_RNCR (*(__IO uint32_t*)0x4001C314U) /**< \brief (USART4) Receive Next Counter Register */ +#define REG_USART4_TNPR (*(__IO uint32_t*)0x4001C318U) /**< \brief (USART4) Transmit Next Pointer Register */ +#define REG_USART4_TNCR (*(__IO uint32_t*)0x4001C31CU) /**< \brief (USART4) Transmit Next Counter Register */ +#define REG_USART4_PTCR (*(__O uint32_t*)0x4001C320U) /**< \brief (USART4) Transfer Control Register */ +#define REG_USART4_PTSR (*(__I uint32_t*)0x4001C324U) /**< \brief (USART4) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_USART4_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart5.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,111 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_USART5_INSTANCE_ +#define _SAMG55_USART5_INSTANCE_ + +/* ========== Register definition for USART5 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART5_CR (0x40008200U) /**< \brief (USART5) USART Control Register */ +#define REG_USART5_MR (0x40008204U) /**< \brief (USART5) USART Mode Register */ +#define REG_USART5_IER (0x40008208U) /**< \brief (USART5) USART Interrupt Enable Register */ +#define REG_USART5_IDR (0x4000820CU) /**< \brief (USART5) USART Interrupt Disable Register */ +#define REG_USART5_IMR (0x40008210U) /**< \brief (USART5) USART Interrupt Mask Register */ +#define REG_USART5_CSR (0x40008214U) /**< \brief (USART5) USART Channel Status Register */ +#define REG_USART5_RHR (0x40008218U) /**< \brief (USART5) USART Receive Holding Register */ +#define REG_USART5_THR (0x4000821CU) /**< \brief (USART5) USART Transmit Holding Register */ +#define REG_USART5_BRGR (0x40008220U) /**< \brief (USART5) USART Baud Rate Generator Register */ +#define REG_USART5_RTOR (0x40008224U) /**< \brief (USART5) USART Receiver Time-out Register */ +#define REG_USART5_TTGR (0x40008228U) /**< \brief (USART5) USART Transmitter Timeguard Register */ +#define REG_USART5_FIDI (0x40008240U) /**< \brief (USART5) USART FI DI Ratio Register */ +#define REG_USART5_NER (0x40008244U) /**< \brief (USART5) USART Number of Errors Register */ +#define REG_USART5_LINMR (0x40008254U) /**< \brief (USART5) USART LIN Mode Register */ +#define REG_USART5_LINIR (0x40008258U) /**< \brief (USART5) USART LIN Identifier Register */ +#define REG_USART5_LINBRR (0x4000825CU) /**< \brief (USART5) USART LIN Baud Rate Register */ +#define REG_USART5_CMPR (0x40008290U) /**< \brief (USART5) USART Comparison Register */ +#define REG_USART5_WPMR (0x400082E4U) /**< \brief (USART5) USART Write Protection Mode Register */ +#define REG_USART5_WPSR (0x400082E8U) /**< \brief (USART5) USART Write Protection Status Register */ +#define REG_USART5_RPR (0x40008300U) /**< \brief (USART5) Receive Pointer Register */ +#define REG_USART5_RCR (0x40008304U) /**< \brief (USART5) Receive Counter Register */ +#define REG_USART5_TPR (0x40008308U) /**< \brief (USART5) Transmit Pointer Register */ +#define REG_USART5_TCR (0x4000830CU) /**< \brief (USART5) Transmit Counter Register */ +#define REG_USART5_RNPR (0x40008310U) /**< \brief (USART5) Receive Next Pointer Register */ +#define REG_USART5_RNCR (0x40008314U) /**< \brief (USART5) Receive Next Counter Register */ +#define REG_USART5_TNPR (0x40008318U) /**< \brief (USART5) Transmit Next Pointer Register */ +#define REG_USART5_TNCR (0x4000831CU) /**< \brief (USART5) Transmit Next Counter Register */ +#define REG_USART5_PTCR (0x40008320U) /**< \brief (USART5) Transfer Control Register */ +#define REG_USART5_PTSR (0x40008324U) /**< \brief (USART5) Transfer Status Register */ +#else +#define REG_USART5_CR (*(__O uint32_t*)0x40008200U) /**< \brief (USART5) USART Control Register */ +#define REG_USART5_MR (*(__IO uint32_t*)0x40008204U) /**< \brief (USART5) USART Mode Register */ +#define REG_USART5_IER (*(__O uint32_t*)0x40008208U) /**< \brief (USART5) USART Interrupt Enable Register */ +#define REG_USART5_IDR (*(__O uint32_t*)0x4000820CU) /**< \brief (USART5) USART Interrupt Disable Register */ +#define REG_USART5_IMR (*(__I uint32_t*)0x40008210U) /**< \brief (USART5) USART Interrupt Mask Register */ +#define REG_USART5_CSR (*(__I uint32_t*)0x40008214U) /**< \brief (USART5) USART Channel Status Register */ +#define REG_USART5_RHR (*(__I uint32_t*)0x40008218U) /**< \brief (USART5) USART Receive Holding Register */ +#define REG_USART5_THR (*(__O uint32_t*)0x4000821CU) /**< \brief (USART5) USART Transmit Holding Register */ +#define REG_USART5_BRGR (*(__IO uint32_t*)0x40008220U) /**< \brief (USART5) USART Baud Rate Generator Register */ +#define REG_USART5_RTOR (*(__IO uint32_t*)0x40008224U) /**< \brief (USART5) USART Receiver Time-out Register */ +#define REG_USART5_TTGR (*(__IO uint32_t*)0x40008228U) /**< \brief (USART5) USART Transmitter Timeguard Register */ +#define REG_USART5_FIDI (*(__IO uint32_t*)0x40008240U) /**< \brief (USART5) USART FI DI Ratio Register */ +#define REG_USART5_NER (*(__I uint32_t*)0x40008244U) /**< \brief (USART5) USART Number of Errors Register */ +#define REG_USART5_LINMR (*(__IO uint32_t*)0x40008254U) /**< \brief (USART5) USART LIN Mode Register */ +#define REG_USART5_LINIR (*(__IO uint32_t*)0x40008258U) /**< \brief (USART5) USART LIN Identifier Register */ +#define REG_USART5_LINBRR (*(__I uint32_t*)0x4000825CU) /**< \brief (USART5) USART LIN Baud Rate Register */ +#define REG_USART5_CMPR (*(__IO uint32_t*)0x40008290U) /**< \brief (USART5) USART Comparison Register */ +#define REG_USART5_WPMR (*(__IO uint32_t*)0x400082E4U) /**< \brief (USART5) USART Write Protection Mode Register */ +#define REG_USART5_WPSR (*(__I uint32_t*)0x400082E8U) /**< \brief (USART5) USART Write Protection Status Register */ +#define REG_USART5_RPR (*(__IO uint32_t*)0x40008300U) /**< \brief (USART5) Receive Pointer Register */ +#define REG_USART5_RCR (*(__IO uint32_t*)0x40008304U) /**< \brief (USART5) Receive Counter Register */ +#define REG_USART5_TPR (*(__IO uint32_t*)0x40008308U) /**< \brief (USART5) Transmit Pointer Register */ +#define REG_USART5_TCR (*(__IO uint32_t*)0x4000830CU) /**< \brief (USART5) Transmit Counter Register */ +#define REG_USART5_RNPR (*(__IO uint32_t*)0x40008310U) /**< \brief (USART5) Receive Next Pointer Register */ +#define REG_USART5_RNCR (*(__IO uint32_t*)0x40008314U) /**< \brief (USART5) Receive Next Counter Register */ +#define REG_USART5_TNPR (*(__IO uint32_t*)0x40008318U) /**< \brief (USART5) Transmit Next Pointer Register */ +#define REG_USART5_TNCR (*(__IO uint32_t*)0x4000831CU) /**< \brief (USART5) Transmit Next Counter Register */ +#define REG_USART5_PTCR (*(__O uint32_t*)0x40008320U) /**< \brief (USART5) Transfer Control Register */ +#define REG_USART5_PTSR (*(__I uint32_t*)0x40008324U) /**< \brief (USART5) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_USART5_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart6.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,111 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_USART6_INSTANCE_ +#define _SAMG55_USART6_INSTANCE_ + +/* ========== Register definition for USART6 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART6_CR (0x40040200U) /**< \brief (USART6) USART Control Register */ +#define REG_USART6_MR (0x40040204U) /**< \brief (USART6) USART Mode Register */ +#define REG_USART6_IER (0x40040208U) /**< \brief (USART6) USART Interrupt Enable Register */ +#define REG_USART6_IDR (0x4004020CU) /**< \brief (USART6) USART Interrupt Disable Register */ +#define REG_USART6_IMR (0x40040210U) /**< \brief (USART6) USART Interrupt Mask Register */ +#define REG_USART6_CSR (0x40040214U) /**< \brief (USART6) USART Channel Status Register */ +#define REG_USART6_RHR (0x40040218U) /**< \brief (USART6) USART Receive Holding Register */ +#define REG_USART6_THR (0x4004021CU) /**< \brief (USART6) USART Transmit Holding Register */ +#define REG_USART6_BRGR (0x40040220U) /**< \brief (USART6) USART Baud Rate Generator Register */ +#define REG_USART6_RTOR (0x40040224U) /**< \brief (USART6) USART Receiver Time-out Register */ +#define REG_USART6_TTGR (0x40040228U) /**< \brief (USART6) USART Transmitter Timeguard Register */ +#define REG_USART6_FIDI (0x40040240U) /**< \brief (USART6) USART FI DI Ratio Register */ +#define REG_USART6_NER (0x40040244U) /**< \brief (USART6) USART Number of Errors Register */ +#define REG_USART6_LINMR (0x40040254U) /**< \brief (USART6) USART LIN Mode Register */ +#define REG_USART6_LINIR (0x40040258U) /**< \brief (USART6) USART LIN Identifier Register */ +#define REG_USART6_LINBRR (0x4004025CU) /**< \brief (USART6) USART LIN Baud Rate Register */ +#define REG_USART6_CMPR (0x40040290U) /**< \brief (USART6) USART Comparison Register */ +#define REG_USART6_WPMR (0x400402E4U) /**< \brief (USART6) USART Write Protection Mode Register */ +#define REG_USART6_WPSR (0x400402E8U) /**< \brief (USART6) USART Write Protection Status Register */ +#define REG_USART6_RPR (0x40040300U) /**< \brief (USART6) Receive Pointer Register */ +#define REG_USART6_RCR (0x40040304U) /**< \brief (USART6) Receive Counter Register */ +#define REG_USART6_TPR (0x40040308U) /**< \brief (USART6) Transmit Pointer Register */ +#define REG_USART6_TCR (0x4004030CU) /**< \brief (USART6) Transmit Counter Register */ +#define REG_USART6_RNPR (0x40040310U) /**< \brief (USART6) Receive Next Pointer Register */ +#define REG_USART6_RNCR (0x40040314U) /**< \brief (USART6) Receive Next Counter Register */ +#define REG_USART6_TNPR (0x40040318U) /**< \brief (USART6) Transmit Next Pointer Register */ +#define REG_USART6_TNCR (0x4004031CU) /**< \brief (USART6) Transmit Next Counter Register */ +#define REG_USART6_PTCR (0x40040320U) /**< \brief (USART6) Transfer Control Register */ +#define REG_USART6_PTSR (0x40040324U) /**< \brief (USART6) Transfer Status Register */ +#else +#define REG_USART6_CR (*(__O uint32_t*)0x40040200U) /**< \brief (USART6) USART Control Register */ +#define REG_USART6_MR (*(__IO uint32_t*)0x40040204U) /**< \brief (USART6) USART Mode Register */ +#define REG_USART6_IER (*(__O uint32_t*)0x40040208U) /**< \brief (USART6) USART Interrupt Enable Register */ +#define REG_USART6_IDR (*(__O uint32_t*)0x4004020CU) /**< \brief (USART6) USART Interrupt Disable Register */ +#define REG_USART6_IMR (*(__I uint32_t*)0x40040210U) /**< \brief (USART6) USART Interrupt Mask Register */ +#define REG_USART6_CSR (*(__I uint32_t*)0x40040214U) /**< \brief (USART6) USART Channel Status Register */ +#define REG_USART6_RHR (*(__I uint32_t*)0x40040218U) /**< \brief (USART6) USART Receive Holding Register */ +#define REG_USART6_THR (*(__O uint32_t*)0x4004021CU) /**< \brief (USART6) USART Transmit Holding Register */ +#define REG_USART6_BRGR (*(__IO uint32_t*)0x40040220U) /**< \brief (USART6) USART Baud Rate Generator Register */ +#define REG_USART6_RTOR (*(__IO uint32_t*)0x40040224U) /**< \brief (USART6) USART Receiver Time-out Register */ +#define REG_USART6_TTGR (*(__IO uint32_t*)0x40040228U) /**< \brief (USART6) USART Transmitter Timeguard Register */ +#define REG_USART6_FIDI (*(__IO uint32_t*)0x40040240U) /**< \brief (USART6) USART FI DI Ratio Register */ +#define REG_USART6_NER (*(__I uint32_t*)0x40040244U) /**< \brief (USART6) USART Number of Errors Register */ +#define REG_USART6_LINMR (*(__IO uint32_t*)0x40040254U) /**< \brief (USART6) USART LIN Mode Register */ +#define REG_USART6_LINIR (*(__IO uint32_t*)0x40040258U) /**< \brief (USART6) USART LIN Identifier Register */ +#define REG_USART6_LINBRR (*(__I uint32_t*)0x4004025CU) /**< \brief (USART6) USART LIN Baud Rate Register */ +#define REG_USART6_CMPR (*(__IO uint32_t*)0x40040290U) /**< \brief (USART6) USART Comparison Register */ +#define REG_USART6_WPMR (*(__IO uint32_t*)0x400402E4U) /**< \brief (USART6) USART Write Protection Mode Register */ +#define REG_USART6_WPSR (*(__I uint32_t*)0x400402E8U) /**< \brief (USART6) USART Write Protection Status Register */ +#define REG_USART6_RPR (*(__IO uint32_t*)0x40040300U) /**< \brief (USART6) Receive Pointer Register */ +#define REG_USART6_RCR (*(__IO uint32_t*)0x40040304U) /**< \brief (USART6) Receive Counter Register */ +#define REG_USART6_TPR (*(__IO uint32_t*)0x40040308U) /**< \brief (USART6) Transmit Pointer Register */ +#define REG_USART6_TCR (*(__IO uint32_t*)0x4004030CU) /**< \brief (USART6) Transmit Counter Register */ +#define REG_USART6_RNPR (*(__IO uint32_t*)0x40040310U) /**< \brief (USART6) Receive Next Pointer Register */ +#define REG_USART6_RNCR (*(__IO uint32_t*)0x40040314U) /**< \brief (USART6) Receive Next Counter Register */ +#define REG_USART6_TNPR (*(__IO uint32_t*)0x40040318U) /**< \brief (USART6) Transmit Next Pointer Register */ +#define REG_USART6_TNCR (*(__IO uint32_t*)0x4004031CU) /**< \brief (USART6) Transmit Next Counter Register */ +#define REG_USART6_PTCR (*(__O uint32_t*)0x40040320U) /**< \brief (USART6) Transfer Control Register */ +#define REG_USART6_PTSR (*(__I uint32_t*)0x40040324U) /**< \brief (USART6) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_USART6_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_usart7.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,111 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_USART7_INSTANCE_ +#define _SAMG55_USART7_INSTANCE_ + +/* ========== Register definition for USART7 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART7_CR (0x40034200U) /**< \brief (USART7) USART Control Register */ +#define REG_USART7_MR (0x40034204U) /**< \brief (USART7) USART Mode Register */ +#define REG_USART7_IER (0x40034208U) /**< \brief (USART7) USART Interrupt Enable Register */ +#define REG_USART7_IDR (0x4003420CU) /**< \brief (USART7) USART Interrupt Disable Register */ +#define REG_USART7_IMR (0x40034210U) /**< \brief (USART7) USART Interrupt Mask Register */ +#define REG_USART7_CSR (0x40034214U) /**< \brief (USART7) USART Channel Status Register */ +#define REG_USART7_RHR (0x40034218U) /**< \brief (USART7) USART Receive Holding Register */ +#define REG_USART7_THR (0x4003421CU) /**< \brief (USART7) USART Transmit Holding Register */ +#define REG_USART7_BRGR (0x40034220U) /**< \brief (USART7) USART Baud Rate Generator Register */ +#define REG_USART7_RTOR (0x40034224U) /**< \brief (USART7) USART Receiver Time-out Register */ +#define REG_USART7_TTGR (0x40034228U) /**< \brief (USART7) USART Transmitter Timeguard Register */ +#define REG_USART7_FIDI (0x40034240U) /**< \brief (USART7) USART FI DI Ratio Register */ +#define REG_USART7_NER (0x40034244U) /**< \brief (USART7) USART Number of Errors Register */ +#define REG_USART7_LINMR (0x40034254U) /**< \brief (USART7) USART LIN Mode Register */ +#define REG_USART7_LINIR (0x40034258U) /**< \brief (USART7) USART LIN Identifier Register */ +#define REG_USART7_LINBRR (0x4003425CU) /**< \brief (USART7) USART LIN Baud Rate Register */ +#define REG_USART7_CMPR (0x40034290U) /**< \brief (USART7) USART Comparison Register */ +#define REG_USART7_WPMR (0x400342E4U) /**< \brief (USART7) USART Write Protection Mode Register */ +#define REG_USART7_WPSR (0x400342E8U) /**< \brief (USART7) USART Write Protection Status Register */ +#define REG_USART7_RPR (0x40034300U) /**< \brief (USART7) Receive Pointer Register */ +#define REG_USART7_RCR (0x40034304U) /**< \brief (USART7) Receive Counter Register */ +#define REG_USART7_TPR (0x40034308U) /**< \brief (USART7) Transmit Pointer Register */ +#define REG_USART7_TCR (0x4003430CU) /**< \brief (USART7) Transmit Counter Register */ +#define REG_USART7_RNPR (0x40034310U) /**< \brief (USART7) Receive Next Pointer Register */ +#define REG_USART7_RNCR (0x40034314U) /**< \brief (USART7) Receive Next Counter Register */ +#define REG_USART7_TNPR (0x40034318U) /**< \brief (USART7) Transmit Next Pointer Register */ +#define REG_USART7_TNCR (0x4003431CU) /**< \brief (USART7) Transmit Next Counter Register */ +#define REG_USART7_PTCR (0x40034320U) /**< \brief (USART7) Transfer Control Register */ +#define REG_USART7_PTSR (0x40034324U) /**< \brief (USART7) Transfer Status Register */ +#else +#define REG_USART7_CR (*(__O uint32_t*)0x40034200U) /**< \brief (USART7) USART Control Register */ +#define REG_USART7_MR (*(__IO uint32_t*)0x40034204U) /**< \brief (USART7) USART Mode Register */ +#define REG_USART7_IER (*(__O uint32_t*)0x40034208U) /**< \brief (USART7) USART Interrupt Enable Register */ +#define REG_USART7_IDR (*(__O uint32_t*)0x4003420CU) /**< \brief (USART7) USART Interrupt Disable Register */ +#define REG_USART7_IMR (*(__I uint32_t*)0x40034210U) /**< \brief (USART7) USART Interrupt Mask Register */ +#define REG_USART7_CSR (*(__I uint32_t*)0x40034214U) /**< \brief (USART7) USART Channel Status Register */ +#define REG_USART7_RHR (*(__I uint32_t*)0x40034218U) /**< \brief (USART7) USART Receive Holding Register */ +#define REG_USART7_THR (*(__O uint32_t*)0x4003421CU) /**< \brief (USART7) USART Transmit Holding Register */ +#define REG_USART7_BRGR (*(__IO uint32_t*)0x40034220U) /**< \brief (USART7) USART Baud Rate Generator Register */ +#define REG_USART7_RTOR (*(__IO uint32_t*)0x40034224U) /**< \brief (USART7) USART Receiver Time-out Register */ +#define REG_USART7_TTGR (*(__IO uint32_t*)0x40034228U) /**< \brief (USART7) USART Transmitter Timeguard Register */ +#define REG_USART7_FIDI (*(__IO uint32_t*)0x40034240U) /**< \brief (USART7) USART FI DI Ratio Register */ +#define REG_USART7_NER (*(__I uint32_t*)0x40034244U) /**< \brief (USART7) USART Number of Errors Register */ +#define REG_USART7_LINMR (*(__IO uint32_t*)0x40034254U) /**< \brief (USART7) USART LIN Mode Register */ +#define REG_USART7_LINIR (*(__IO uint32_t*)0x40034258U) /**< \brief (USART7) USART LIN Identifier Register */ +#define REG_USART7_LINBRR (*(__I uint32_t*)0x4003425CU) /**< \brief (USART7) USART LIN Baud Rate Register */ +#define REG_USART7_CMPR (*(__IO uint32_t*)0x40034290U) /**< \brief (USART7) USART Comparison Register */ +#define REG_USART7_WPMR (*(__IO uint32_t*)0x400342E4U) /**< \brief (USART7) USART Write Protection Mode Register */ +#define REG_USART7_WPSR (*(__I uint32_t*)0x400342E8U) /**< \brief (USART7) USART Write Protection Status Register */ +#define REG_USART7_RPR (*(__IO uint32_t*)0x40034300U) /**< \brief (USART7) Receive Pointer Register */ +#define REG_USART7_RCR (*(__IO uint32_t*)0x40034304U) /**< \brief (USART7) Receive Counter Register */ +#define REG_USART7_TPR (*(__IO uint32_t*)0x40034308U) /**< \brief (USART7) Transmit Pointer Register */ +#define REG_USART7_TCR (*(__IO uint32_t*)0x4003430CU) /**< \brief (USART7) Transmit Counter Register */ +#define REG_USART7_RNPR (*(__IO uint32_t*)0x40034310U) /**< \brief (USART7) Receive Next Pointer Register */ +#define REG_USART7_RNCR (*(__IO uint32_t*)0x40034314U) /**< \brief (USART7) Receive Next Counter Register */ +#define REG_USART7_TNPR (*(__IO uint32_t*)0x40034318U) /**< \brief (USART7) Transmit Next Pointer Register */ +#define REG_USART7_TNCR (*(__IO uint32_t*)0x4003431CU) /**< \brief (USART7) Transmit Next Counter Register */ +#define REG_USART7_PTCR (*(__O uint32_t*)0x40034320U) /**< \brief (USART7) Transfer Control Register */ +#define REG_USART7_PTSR (*(__I uint32_t*)0x40034324U) /**< \brief (USART7) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_USART7_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/instance/ins_wdt.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,59 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55_WDT_INSTANCE_ +#define _SAMG55_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CR (0x400E1450U) /**< \brief (WDT) Control Register */ +#define REG_WDT_MR (0x400E1454U) /**< \brief (WDT) Mode Register */ +#define REG_WDT_SR (0x400E1458U) /**< \brief (WDT) Status Register */ +#else +#define REG_WDT_CR (*(__O uint32_t*)0x400E1450U) /**< \brief (WDT) Control Register */ +#define REG_WDT_MR (*(__IO uint32_t*)0x400E1454U) /**< \brief (WDT) Mode Register */ +#define REG_WDT_SR (*(__I uint32_t*)0x400E1458U) /**< \brief (WDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMG55_WDT_INSTANCE_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55g18.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,449 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55G18_PIO_ +#define _SAMG55G18_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ +#define PIO_PB3X1_WKUP13 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA0A_I2SCK0 (1u << 0) /**< \brief I2sc0 signal: I2SCK0 */ +#define PIO_PA2B_I2SDI0 (1u << 2) /**< \brief I2sc0 signal: I2SDI0 */ +#define PIO_PA3B_I2SDO0 (1u << 3) /**< \brief I2sc0 signal: I2SDO0 */ +#define PIO_PA17A_I2SDO0 (1u << 17) /**< \brief I2sc0 signal: I2SDO0 */ +#define PIO_PA4B_I2SMCK0 (1u << 4) /**< \brief I2sc0 signal: I2SMCK0 */ +#define PIO_PA18A_I2SMCK0 (1u << 18) /**< \brief I2sc0 signal: I2SMCK0 */ +#define PIO_PA1A_I2SWS0 (1u << 1) /**< \brief I2sc0 signal: I2SWS0 */ +#define PIO_PA10B_PDMCLK0 (1u << 10) /**< \brief I2sc0 signal: PDMCLK0 */ +#define PIO_PA9B_PDMDAT0 (1u << 9) /**< \brief I2sc0 signal: PDMDAT0 */ +/* ========== Pio definition for I2SC1 peripheral ========== */ +#define PIO_PA19B_I2SCK1 (1u << 19) /**< \brief I2sc1 signal: I2SCK1 */ +#define PIO_PA22B_I2SDI1 (1u << 22) /**< \brief I2sc1 signal: I2SDI1 */ +#define PIO_PA23A_I2SDO1 (1u << 23) /**< \brief I2sc1 signal: I2SDO1 */ +#define PIO_PA25B_I2SDO1 (1u << 25) /**< \brief I2sc1 signal: I2SDO1 */ +#define PIO_PA24A_I2SMCK1 (1u << 24) /**< \brief I2sc1 signal: I2SMCK1 */ +#define PIO_PA26B_I2SMCK1 (1u << 26) /**< \brief I2sc1 signal: I2SMCK1 */ +#define PIO_PA20B_I2SWS1 (1u << 20) /**< \brief I2sc1 signal: I2SWS1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA30A_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31A_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ +#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ +#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ +/* ========== Pio definition for SPI2 peripheral ========== */ +#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ +/* ========== Pio definition for SPI3 peripheral ========== */ +#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ +/* ========== Pio definition for SPI4 peripheral ========== */ +#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +/* ========== Pio definition for SPI5 peripheral ========== */ +#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ +/* ========== Pio definition for SPI6 peripheral ========== */ +#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA19A_TCLK1 (1u << 19) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA20A_TCLK2 (1u << 20) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA23B_TIOA1 (1u << 23) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA21A_TIOA2 (1u << 21) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA22A_TIOB2 (1u << 22) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ +/* ========== Pio definition for TWI2 peripheral ========== */ +#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ +/* ========== Pio definition for TWI3 peripheral ========== */ +#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ +/* ========== Pio definition for TWI4 peripheral ========== */ +#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +/* ========== Pio definition for TWI5 peripheral ========== */ +#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ +/* ========== Pio definition for TWI6 peripheral ========== */ +#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ +#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ +#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ +/* ========== Pio definition for USART3 peripheral ========== */ +#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ +/* ========== Pio definition for USART4 peripheral ========== */ +#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +/* ========== Pio definition for USART5 peripheral ========== */ +#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ +/* ========== Pio definition for USART6 peripheral ========== */ +#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 + +#endif /* _SAMG55G18_PIO_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55g19.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,449 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55G19_PIO_ +#define _SAMG55G19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ +#define PIO_PB3X1_WKUP13 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA0A_I2SCK0 (1u << 0) /**< \brief I2sc0 signal: I2SCK0 */ +#define PIO_PA2B_I2SDI0 (1u << 2) /**< \brief I2sc0 signal: I2SDI0 */ +#define PIO_PA3B_I2SDO0 (1u << 3) /**< \brief I2sc0 signal: I2SDO0 */ +#define PIO_PA17A_I2SDO0 (1u << 17) /**< \brief I2sc0 signal: I2SDO0 */ +#define PIO_PA4B_I2SMCK0 (1u << 4) /**< \brief I2sc0 signal: I2SMCK0 */ +#define PIO_PA18A_I2SMCK0 (1u << 18) /**< \brief I2sc0 signal: I2SMCK0 */ +#define PIO_PA1A_I2SWS0 (1u << 1) /**< \brief I2sc0 signal: I2SWS0 */ +#define PIO_PA10B_PDMCLK0 (1u << 10) /**< \brief I2sc0 signal: PDMCLK0 */ +#define PIO_PA9B_PDMDAT0 (1u << 9) /**< \brief I2sc0 signal: PDMDAT0 */ +/* ========== Pio definition for I2SC1 peripheral ========== */ +#define PIO_PA19B_I2SCK1 (1u << 19) /**< \brief I2sc1 signal: I2SCK1 */ +#define PIO_PA22B_I2SDI1 (1u << 22) /**< \brief I2sc1 signal: I2SDI1 */ +#define PIO_PA23A_I2SDO1 (1u << 23) /**< \brief I2sc1 signal: I2SDO1 */ +#define PIO_PA25B_I2SDO1 (1u << 25) /**< \brief I2sc1 signal: I2SDO1 */ +#define PIO_PA24A_I2SMCK1 (1u << 24) /**< \brief I2sc1 signal: I2SMCK1 */ +#define PIO_PA26B_I2SMCK1 (1u << 26) /**< \brief I2sc1 signal: I2SMCK1 */ +#define PIO_PA20B_I2SWS1 (1u << 20) /**< \brief I2sc1 signal: I2SWS1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA30A_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31A_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ +#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ +#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ +/* ========== Pio definition for SPI2 peripheral ========== */ +#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ +/* ========== Pio definition for SPI3 peripheral ========== */ +#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ +/* ========== Pio definition for SPI4 peripheral ========== */ +#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +/* ========== Pio definition for SPI5 peripheral ========== */ +#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ +/* ========== Pio definition for SPI6 peripheral ========== */ +#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA19A_TCLK1 (1u << 19) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA20A_TCLK2 (1u << 20) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA23B_TIOA1 (1u << 23) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA21A_TIOA2 (1u << 21) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA22A_TIOB2 (1u << 22) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ +/* ========== Pio definition for TWI2 peripheral ========== */ +#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ +/* ========== Pio definition for TWI3 peripheral ========== */ +#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ +/* ========== Pio definition for TWI4 peripheral ========== */ +#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +/* ========== Pio definition for TWI5 peripheral ========== */ +#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ +/* ========== Pio definition for TWI6 peripheral ========== */ +#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ +#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ +#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ +/* ========== Pio definition for USART3 peripheral ========== */ +#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ +/* ========== Pio definition for USART4 peripheral ========== */ +#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +/* ========== Pio definition for USART5 peripheral ========== */ +#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ +/* ========== Pio definition for USART6 peripheral ========== */ +#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 + +#endif /* _SAMG55G19_PIO_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55j18.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,502 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55J18_PIO_ +#define _SAMG55J18_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ +#define PIO_PB3X1_WKUP13 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA0A_I2SCK0 (1u << 0) /**< \brief I2sc0 signal: I2SCK0 */ +#define PIO_PA2B_I2SDI0 (1u << 2) /**< \brief I2sc0 signal: I2SDI0 */ +#define PIO_PA3B_I2SDO0 (1u << 3) /**< \brief I2sc0 signal: I2SDO0 */ +#define PIO_PA17A_I2SDO0 (1u << 17) /**< \brief I2sc0 signal: I2SDO0 */ +#define PIO_PA4B_I2SMCK0 (1u << 4) /**< \brief I2sc0 signal: I2SMCK0 */ +#define PIO_PA18A_I2SMCK0 (1u << 18) /**< \brief I2sc0 signal: I2SMCK0 */ +#define PIO_PA1A_I2SWS0 (1u << 1) /**< \brief I2sc0 signal: I2SWS0 */ +#define PIO_PA10B_PDMCLK0 (1u << 10) /**< \brief I2sc0 signal: PDMCLK0 */ +#define PIO_PA9B_PDMDAT0 (1u << 9) /**< \brief I2sc0 signal: PDMDAT0 */ +/* ========== Pio definition for I2SC1 peripheral ========== */ +#define PIO_PA19B_I2SCK1 (1u << 19) /**< \brief I2sc1 signal: I2SCK1 */ +#define PIO_PA22B_I2SDI1 (1u << 22) /**< \brief I2sc1 signal: I2SDI1 */ +#define PIO_PA23A_I2SDO1 (1u << 23) /**< \brief I2sc1 signal: I2SDO1 */ +#define PIO_PA25B_I2SDO1 (1u << 25) /**< \brief I2sc1 signal: I2SDO1 */ +#define PIO_PA24A_I2SMCK1 (1u << 24) /**< \brief I2sc1 signal: I2SMCK1 */ +#define PIO_PA26B_I2SMCK1 (1u << 26) /**< \brief I2sc1 signal: I2SMCK1 */ +#define PIO_PA20B_I2SWS1 (1u << 20) /**< \brief I2sc1 signal: I2SWS1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA30A_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31A_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ +#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ +#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ +/* ========== Pio definition for SPI2 peripheral ========== */ +#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ +/* ========== Pio definition for SPI3 peripheral ========== */ +#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ +/* ========== Pio definition for SPI4 peripheral ========== */ +#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +/* ========== Pio definition for SPI5 peripheral ========== */ +#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ +/* ========== Pio definition for SPI6 peripheral ========== */ +#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +/* ========== Pio definition for SPI7 peripheral ========== */ +#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA29B_SCK7 (1u << 29) /**< \brief Spi7 signal: SCK7/SPI7_SPCK */ +#define PIO_PA29B_SPI7_SPCK (1u << 29) /**< \brief Spi7 signal: SCK7/SPI7_SPCK */ +#define PIO_PA30B_SPI7_NPCS0 (1u << 30) /**< \brief Spi7 signal: SPI7_NPCS0/CTS7 */ +#define PIO_PA30B_CTS7 (1u << 30) /**< \brief Spi7 signal: SPI7_NPCS0/CTS7 */ +#define PIO_PA31B_SPI7_NPCS1 (1u << 31) /**< \brief Spi7 signal: SPI7_NPCS1/RTS7 */ +#define PIO_PA31B_RTS7 (1u << 31) /**< \brief Spi7 signal: SPI7_NPCS1/RTS7 */ +#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA19A_TCLK1 (1u << 19) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA20A_TCLK2 (1u << 20) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA23B_TIOA1 (1u << 23) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA21A_TIOA2 (1u << 21) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA22A_TIOB2 (1u << 22) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ +/* ========== Pio definition for TWI2 peripheral ========== */ +#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ +/* ========== Pio definition for TWI3 peripheral ========== */ +#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ +/* ========== Pio definition for TWI4 peripheral ========== */ +#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +/* ========== Pio definition for TWI5 peripheral ========== */ +#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ +/* ========== Pio definition for TWI6 peripheral ========== */ +#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +/* ========== Pio definition for TWI7 peripheral ========== */ +#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ +#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ +#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ +/* ========== Pio definition for USART3 peripheral ========== */ +#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ +/* ========== Pio definition for USART4 peripheral ========== */ +#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +/* ========== Pio definition for USART5 peripheral ========== */ +#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ +/* ========== Pio definition for USART6 peripheral ========== */ +#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +/* ========== Pio definition for USART7 peripheral ========== */ +#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA29B_SCK7 (1u << 29) /**< \brief Usart7 signal: SCK7/SPI7_SPCK */ +#define PIO_PA29B_SPI7_SPCK (1u << 29) /**< \brief Usart7 signal: SCK7/SPI7_SPCK */ +#define PIO_PA30B_SPI7_NPCS0 (1u << 30) /**< \brief Usart7 signal: SPI7_NPCS0/CTS7 */ +#define PIO_PA30B_CTS7 (1u << 30) /**< \brief Usart7 signal: SPI7_NPCS0/CTS7 */ +#define PIO_PA31B_SPI7_NPCS1 (1u << 31) /**< \brief Usart7 signal: SPI7_NPCS1/RTS7 */ +#define PIO_PA31B_RTS7 (1u << 31) /**< \brief Usart7 signal: SPI7_NPCS1/RTS7 */ +#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PB15_IDX 47 + +#endif /* _SAMG55J18_PIO_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55j19.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,502 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55J19_PIO_ +#define _SAMG55J19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ +#define PIO_PB3X1_WKUP13 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA0A_I2SCK0 (1u << 0) /**< \brief I2sc0 signal: I2SCK0 */ +#define PIO_PA2B_I2SDI0 (1u << 2) /**< \brief I2sc0 signal: I2SDI0 */ +#define PIO_PA3B_I2SDO0 (1u << 3) /**< \brief I2sc0 signal: I2SDO0 */ +#define PIO_PA17A_I2SDO0 (1u << 17) /**< \brief I2sc0 signal: I2SDO0 */ +#define PIO_PA4B_I2SMCK0 (1u << 4) /**< \brief I2sc0 signal: I2SMCK0 */ +#define PIO_PA18A_I2SMCK0 (1u << 18) /**< \brief I2sc0 signal: I2SMCK0 */ +#define PIO_PA1A_I2SWS0 (1u << 1) /**< \brief I2sc0 signal: I2SWS0 */ +#define PIO_PA10B_PDMCLK0 (1u << 10) /**< \brief I2sc0 signal: PDMCLK0 */ +#define PIO_PA9B_PDMDAT0 (1u << 9) /**< \brief I2sc0 signal: PDMDAT0 */ +/* ========== Pio definition for I2SC1 peripheral ========== */ +#define PIO_PA19B_I2SCK1 (1u << 19) /**< \brief I2sc1 signal: I2SCK1 */ +#define PIO_PA22B_I2SDI1 (1u << 22) /**< \brief I2sc1 signal: I2SDI1 */ +#define PIO_PA23A_I2SDO1 (1u << 23) /**< \brief I2sc1 signal: I2SDO1 */ +#define PIO_PA25B_I2SDO1 (1u << 25) /**< \brief I2sc1 signal: I2SDO1 */ +#define PIO_PA24A_I2SMCK1 (1u << 24) /**< \brief I2sc1 signal: I2SMCK1 */ +#define PIO_PA26B_I2SMCK1 (1u << 26) /**< \brief I2sc1 signal: I2SMCK1 */ +#define PIO_PA20B_I2SWS1 (1u << 20) /**< \brief I2sc1 signal: I2SWS1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA30A_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31A_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ +#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ +#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ +/* ========== Pio definition for SPI2 peripheral ========== */ +#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ +/* ========== Pio definition for SPI3 peripheral ========== */ +#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ +/* ========== Pio definition for SPI4 peripheral ========== */ +#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +/* ========== Pio definition for SPI5 peripheral ========== */ +#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ +/* ========== Pio definition for SPI6 peripheral ========== */ +#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +/* ========== Pio definition for SPI7 peripheral ========== */ +#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA29B_SCK7 (1u << 29) /**< \brief Spi7 signal: SCK7/SPI7_SPCK */ +#define PIO_PA29B_SPI7_SPCK (1u << 29) /**< \brief Spi7 signal: SCK7/SPI7_SPCK */ +#define PIO_PA30B_SPI7_NPCS0 (1u << 30) /**< \brief Spi7 signal: SPI7_NPCS0/CTS7 */ +#define PIO_PA30B_CTS7 (1u << 30) /**< \brief Spi7 signal: SPI7_NPCS0/CTS7 */ +#define PIO_PA31B_SPI7_NPCS1 (1u << 31) /**< \brief Spi7 signal: SPI7_NPCS1/RTS7 */ +#define PIO_PA31B_RTS7 (1u << 31) /**< \brief Spi7 signal: SPI7_NPCS1/RTS7 */ +#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA19A_TCLK1 (1u << 19) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA20A_TCLK2 (1u << 20) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA23B_TIOA1 (1u << 23) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA21A_TIOA2 (1u << 21) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA22A_TIOB2 (1u << 22) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ +/* ========== Pio definition for TWI2 peripheral ========== */ +#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ +/* ========== Pio definition for TWI3 peripheral ========== */ +#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ +/* ========== Pio definition for TWI4 peripheral ========== */ +#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +/* ========== Pio definition for TWI5 peripheral ========== */ +#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ +/* ========== Pio definition for TWI6 peripheral ========== */ +#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +/* ========== Pio definition for TWI7 peripheral ========== */ +#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ +#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ +#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ +/* ========== Pio definition for USART3 peripheral ========== */ +#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ +/* ========== Pio definition for USART4 peripheral ========== */ +#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +/* ========== Pio definition for USART5 peripheral ========== */ +#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ +/* ========== Pio definition for USART6 peripheral ========== */ +#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +/* ========== Pio definition for USART7 peripheral ========== */ +#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA29B_SCK7 (1u << 29) /**< \brief Usart7 signal: SCK7/SPI7_SPCK */ +#define PIO_PA29B_SPI7_SPCK (1u << 29) /**< \brief Usart7 signal: SCK7/SPI7_SPCK */ +#define PIO_PA30B_SPI7_NPCS0 (1u << 30) /**< \brief Usart7 signal: SPI7_NPCS0/CTS7 */ +#define PIO_PA30B_CTS7 (1u << 30) /**< \brief Usart7 signal: SPI7_NPCS0/CTS7 */ +#define PIO_PA31B_SPI7_NPCS1 (1u << 31) /**< \brief Usart7 signal: SPI7_NPCS1/RTS7 */ +#define PIO_PA31B_RTS7 (1u << 31) /**< \brief Usart7 signal: SPI7_NPCS1/RTS7 */ +#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PB15_IDX 47 + +#endif /* _SAMG55J19_PIO_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/pio/pio_samg55n19.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,502 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAMG55N19_PIO_ +#define _SAMG55N19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ +#define PIO_PB3X1_WKUP13 (1u << 3) /**< \brief Adc signal: AD7/WKUP13 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for I2SC0 peripheral ========== */ +#define PIO_PA0A_I2SCK0 (1u << 0) /**< \brief I2sc0 signal: I2SCK0 */ +#define PIO_PA2B_I2SDI0 (1u << 2) /**< \brief I2sc0 signal: I2SDI0 */ +#define PIO_PA3B_I2SDO0 (1u << 3) /**< \brief I2sc0 signal: I2SDO0 */ +#define PIO_PA17A_I2SDO0 (1u << 17) /**< \brief I2sc0 signal: I2SDO0 */ +#define PIO_PA4B_I2SMCK0 (1u << 4) /**< \brief I2sc0 signal: I2SMCK0 */ +#define PIO_PA18A_I2SMCK0 (1u << 18) /**< \brief I2sc0 signal: I2SMCK0 */ +#define PIO_PA1A_I2SWS0 (1u << 1) /**< \brief I2sc0 signal: I2SWS0 */ +#define PIO_PA10B_PDMCLK0 (1u << 10) /**< \brief I2sc0 signal: PDMCLK0 */ +#define PIO_PA9B_PDMDAT0 (1u << 9) /**< \brief I2sc0 signal: PDMDAT0 */ +/* ========== Pio definition for I2SC1 peripheral ========== */ +#define PIO_PA19B_I2SCK1 (1u << 19) /**< \brief I2sc1 signal: I2SCK1 */ +#define PIO_PA22B_I2SDI1 (1u << 22) /**< \brief I2sc1 signal: I2SDI1 */ +#define PIO_PA23A_I2SDO1 (1u << 23) /**< \brief I2sc1 signal: I2SDO1 */ +#define PIO_PA25B_I2SDO1 (1u << 25) /**< \brief I2sc1 signal: I2SDO1 */ +#define PIO_PA24A_I2SMCK1 (1u << 24) /**< \brief I2sc1 signal: I2SMCK1 */ +#define PIO_PA26B_I2SMCK1 (1u << 26) /**< \brief I2sc1 signal: I2SMCK1 */ +#define PIO_PA20B_I2SWS1 (1u << 20) /**< \brief I2sc1 signal: I2SWS1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA30A_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31A_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Spi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ +#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Spi0 signal: SCK0/SPI0_SPCK */ +#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Spi0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Spi0 signal: TXD0/SPI0_MOSI/TWD0 */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Spi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Spi1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Spi1 signal: TXD1/SPI1_MOSI/TWD1 */ +/* ========== Pio definition for SPI2 peripheral ========== */ +#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Spi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Spi2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Spi2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Spi2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Spi2 signal: TXD2/SPI2_MOSI/TWD2 */ +/* ========== Pio definition for SPI3 peripheral ========== */ +#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Spi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Spi3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Spi3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Spi3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Spi3 signal: TXD3/SPI3_MOSI/TWD3 */ +/* ========== Pio definition for SPI4 peripheral ========== */ +#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Spi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Spi4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Spi4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Spi4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Spi4 signal: TXD4/SPI4_MOSI/TWD4 */ +/* ========== Pio definition for SPI5 peripheral ========== */ +#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Spi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Spi5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Spi5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Spi5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Spi5 signal: TXD5/SPI5_MOSI/TWD5 */ +/* ========== Pio definition for SPI6 peripheral ========== */ +#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Spi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Spi6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Spi6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Spi6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Spi6 signal: TXD6/SPI6_MOSI/TWD6 */ +/* ========== Pio definition for SPI7 peripheral ========== */ +#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Spi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA29B_SCK7 (1u << 29) /**< \brief Spi7 signal: SCK7/SPI7_SPCK */ +#define PIO_PA29B_SPI7_SPCK (1u << 29) /**< \brief Spi7 signal: SCK7/SPI7_SPCK */ +#define PIO_PA30B_SPI7_NPCS0 (1u << 30) /**< \brief Spi7 signal: SPI7_NPCS0/CTS7 */ +#define PIO_PA30B_CTS7 (1u << 30) /**< \brief Spi7 signal: SPI7_NPCS0/CTS7 */ +#define PIO_PA31B_SPI7_NPCS1 (1u << 31) /**< \brief Spi7 signal: SPI7_NPCS1/RTS7 */ +#define PIO_PA31B_RTS7 (1u << 31) /**< \brief Spi7 signal: SPI7_NPCS1/RTS7 */ +#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Spi7 signal: TXD7/SPI7_MOSI/TWD7 */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA19A_TCLK1 (1u << 19) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA20A_TCLK2 (1u << 20) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA23B_TIOA1 (1u << 23) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA21A_TIOA2 (1u << 21) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA22A_TIOB2 (1u << 22) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Twi0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Twi0 signal: TXD0/SPI0_MOSI/TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Twi1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Twi1 signal: TXD1/SPI1_MOSI/TWD1 */ +/* ========== Pio definition for TWI2 peripheral ========== */ +#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Twi2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Twi2 signal: TXD2/SPI2_MOSI/TWD2 */ +/* ========== Pio definition for TWI3 peripheral ========== */ +#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Twi3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Twi3 signal: TXD3/SPI3_MOSI/TWD3 */ +/* ========== Pio definition for TWI4 peripheral ========== */ +#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Twi4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Twi4 signal: TXD4/SPI4_MOSI/TWD4 */ +/* ========== Pio definition for TWI5 peripheral ========== */ +#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Twi5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Twi5 signal: TXD5/SPI5_MOSI/TWD5 */ +/* ========== Pio definition for TWI6 peripheral ========== */ +#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Twi6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Twi6 signal: TXD6/SPI6_MOSI/TWD6 */ +/* ========== Pio definition for TWI7 peripheral ========== */ +#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Twi7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Twi7 signal: TXD7/SPI7_MOSI/TWD7 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA9A_RXD0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_SPI0_MISO (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PA9A_TWCK0 (1u << 9) /**< \brief Usart0 signal: RXD0/SPI0_MISO/TWCK0 */ +#define PIO_PB0A_SCK0 (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ +#define PIO_PB0A_SPI0_SPCK (1u << 0) /**< \brief Usart0 signal: SCK0/SPI0_SPCK */ +#define PIO_PA25A_SPI0_NPCS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA25A_CTS0 (1u << 25) /**< \brief Usart0 signal: SPI0_NPCS0/CTS0 */ +#define PIO_PA26A_SPI0_NPCS1 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA26A_RTS0 (1u << 26) /**< \brief Usart0 signal: SPI0_NPCS1/RTS0 */ +#define PIO_PA10A_TXD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_SPI0_MOSI (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ +#define PIO_PA10A_TWD0 (1u << 10) /**< \brief Usart0 signal: TXD0/SPI0_MOSI/TWD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PB2A_RXD1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_SPI1_MISO (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PB2A_TWCK1 (1u << 2) /**< \brief Usart1 signal: RXD1/SPI1_MISO/TWCK1 */ +#define PIO_PA27A_SCK1 (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA27A_SPI1_SPCK (1u << 27) /**< \brief Usart1 signal: SCK1/SPI1_SPCK */ +#define PIO_PA28A_SPI1_NPCS0 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA28A_CTS1 (1u << 28) /**< \brief Usart1 signal: SPI1_NPCS0/CTS1 */ +#define PIO_PA29A_SPI1_NPCS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PA29A_RTS1 (1u << 29) /**< \brief Usart1 signal: SPI1_NPCS1/RTS1 */ +#define PIO_PB3A_TXD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_SPI1_MOSI (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ +#define PIO_PB3A_TWD1 (1u << 3) /**< \brief Usart1 signal: TXD1/SPI1_MOSI/TWD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PA5A_RXD2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_SPI2_MISO (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA5A_TWCK2 (1u << 5) /**< \brief Usart2 signal: RXD2/SPI2_MISO/TWCK2 */ +#define PIO_PA15B_SCK2 (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA15B_SPI2_SPCK (1u << 15) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA24B_SPI2_SPCK (1u << 24) /**< \brief Usart2 signal: SCK2/SPI2_SPCK */ +#define PIO_PA16A_SPI2_NPCS0 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA16A_CTS2 (1u << 16) /**< \brief Usart2 signal: SPI2_NPCS0/CTS2 */ +#define PIO_PA15A_SPI2_NPCS1 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA15A_RTS2 (1u << 15) /**< \brief Usart2 signal: SPI2_NPCS1/RTS2 */ +#define PIO_PA6A_TXD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_SPI2_MOSI (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ +#define PIO_PA6A_TWD2 (1u << 6) /**< \brief Usart2 signal: TXD2/SPI2_MOSI/TWD2 */ +/* ========== Pio definition for USART3 peripheral ========== */ +#define PIO_PA4A_RXD3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_SPI3_MISO (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PA4A_TWCK3 (1u << 4) /**< \brief Usart3 signal: RXD3/SPI3_MISO/TWCK3 */ +#define PIO_PB13A_SCK3 (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB13A_SPI3_SPCK (1u << 13) /**< \brief Usart3 signal: SCK3/SPI3_SPCK */ +#define PIO_PB14A_SPI3_NPCS0 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB14A_CTS3 (1u << 14) /**< \brief Usart3 signal: SPI3_NPCS0/CTS3 */ +#define PIO_PB15A_SPI3_NPCS1 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PB15A_RTS3 (1u << 15) /**< \brief Usart3 signal: SPI3_NPCS1/RTS3 */ +#define PIO_PA3A_TXD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_SPI3_MOSI (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ +#define PIO_PA3A_TWD3 (1u << 3) /**< \brief Usart3 signal: TXD3/SPI3_MOSI/TWD3 */ +/* ========== Pio definition for USART4 peripheral ========== */ +#define PIO_PB9A_RXD4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_SPI4_MISO (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB9A_TWCK4 (1u << 9) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_RXD4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_SPI4_MISO (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB11A_TWCK4 (1u << 11) /**< \brief Usart4 signal: RXD4/SPI4_MISO/TWCK4 */ +#define PIO_PB1A_SCK4 (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB1A_SPI4_SPCK (1u << 1) /**< \brief Usart4 signal: SCK4/SPI4_SPCK */ +#define PIO_PB8B_SPI4_NPCS0 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB8B_CTS4 (1u << 8) /**< \brief Usart4 signal: SPI4_NPCS0/CTS4 */ +#define PIO_PB9B_SPI4_NPCS1 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB9B_RTS4 (1u << 9) /**< \brief Usart4 signal: SPI4_NPCS1/RTS4 */ +#define PIO_PB8A_TXD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_SPI4_MOSI (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB8A_TWD4 (1u << 8) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TXD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_SPI4_MOSI (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +#define PIO_PB10A_TWD4 (1u << 10) /**< \brief Usart4 signal: TXD4/SPI4_MOSI/TWD4 */ +/* ========== Pio definition for USART5 peripheral ========== */ +#define PIO_PA12A_RXD5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_SPI5_MISO (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA12A_TWCK5 (1u << 12) /**< \brief Usart5 signal: RXD5/SPI5_MISO/TWCK5 */ +#define PIO_PA14A_SCK5 (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA14A_SPI5_SPCK (1u << 14) /**< \brief Usart5 signal: SCK5/SPI5_SPCK */ +#define PIO_PA11A_SPI5_NPCS0 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA11A_CTS5 (1u << 11) /**< \brief Usart5 signal: SPI5_NPCS0/CTS5 */ +#define PIO_PA5B_SPI5_NPCS1 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA5B_RTS5 (1u << 5) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_SPI5_NPCS1 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PB2B_RTS5 (1u << 2) /**< \brief Usart5 signal: SPI5_NPCS1/RTS5 */ +#define PIO_PA13A_TXD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_SPI5_MOSI (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ +#define PIO_PA13A_TWD5 (1u << 13) /**< \brief Usart5 signal: TXD5/SPI5_MOSI/TWD5 */ +/* ========== Pio definition for USART6 peripheral ========== */ +#define PIO_PB1B_RXD6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_SPI6_MISO (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB1B_TWCK6 (1u << 1) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_RXD6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_SPI6_MISO (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB11B_TWCK6 (1u << 11) /**< \brief Usart6 signal: RXD6/SPI6_MISO/TWCK6 */ +#define PIO_PB13B_SCK6 (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB13B_SPI6_SPCK (1u << 13) /**< \brief Usart6 signal: SCK6/SPI6_SPCK */ +#define PIO_PB14B_SPI6_NPCS0 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB14B_CTS6 (1u << 14) /**< \brief Usart6 signal: SPI6_NPCS0/CTS6 */ +#define PIO_PB15B_SPI6_NPCS1 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB15B_RTS6 (1u << 15) /**< \brief Usart6 signal: SPI6_NPCS1/RTS6 */ +#define PIO_PB0B_TXD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_SPI6_MOSI (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB0B_TWD6 (1u << 0) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TXD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_SPI6_MOSI (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +#define PIO_PB10B_TWD6 (1u << 10) /**< \brief Usart6 signal: TXD6/SPI6_MOSI/TWD6 */ +/* ========== Pio definition for USART7 peripheral ========== */ +#define PIO_PA27B_RXD7 (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_SPI7_MISO (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA27B_TWCK7 (1u << 27) /**< \brief Usart7 signal: RXD7/SPI7_MISO/TWCK7 */ +#define PIO_PA29B_SCK7 (1u << 29) /**< \brief Usart7 signal: SCK7/SPI7_SPCK */ +#define PIO_PA29B_SPI7_SPCK (1u << 29) /**< \brief Usart7 signal: SCK7/SPI7_SPCK */ +#define PIO_PA30B_SPI7_NPCS0 (1u << 30) /**< \brief Usart7 signal: SPI7_NPCS0/CTS7 */ +#define PIO_PA30B_CTS7 (1u << 30) /**< \brief Usart7 signal: SPI7_NPCS0/CTS7 */ +#define PIO_PA31B_SPI7_NPCS1 (1u << 31) /**< \brief Usart7 signal: SPI7_NPCS1/RTS7 */ +#define PIO_PA31B_RTS7 (1u << 31) /**< \brief Usart7 signal: SPI7_NPCS1/RTS7 */ +#define PIO_PA28B_TXD7 (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_SPI7_MOSI (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ +#define PIO_PA28B_TWD7 (1u << 28) /**< \brief Usart7 signal: TXD7/SPI7_MOSI/TWD7 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PB15_IDX 47 + +#endif /* _SAMG55N19_PIO_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,61 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ +#ifndef _SAMG55_ +#define _SAMG55_ + +#if defined (__SAMG55G18__) +#include "samg55g18.h" +#elif defined (__SAMG55G19__) +#include "samg55g19.h" +#elif defined (__SAMG55J18__) +#include "samg55j18.h" +#elif defined (__SAMG55J19__) +#include "samg55j19.h" +#elif defined (__SAMG55N19__) +#include "samg55n19.h" +#else +#error Library does not support the specified device. +#endif + +#endif /* _SAMG55_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55g18.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,721 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55G18_
+#define _SAMG55G18_
+
+/** \addtogroup SAMG55G18_definitions SAMG55G18 definitions
+ This file defines all structures and symbols for SAMG55G18:
+ - registers and bitfields
+ - peripheral base address
+ - peripheral ID
+ - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#endif
+
+/* ************************************************************************** */
+/* CMSIS DEFINITIONS FOR SAMG55G18 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55G18_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn {
+ /****** Cortex-M4 Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
+ /****** SAMG55G18 specific Interrupt Numbers *********************************/
+
+ SUPC_IRQn = 0, /**< 0 SAMG55G18 Supply Controller (SUPC) */
+ RSTC_IRQn = 1, /**< 1 SAMG55G18 Reset Controller (RSTC) */
+ RTC_IRQn = 2, /**< 2 SAMG55G18 Real Time Clock (RTC) */
+ RTT_IRQn = 3, /**< 3 SAMG55G18 Real Time Timer (RTT) */
+ WDT_IRQn = 4, /**< 4 SAMG55G18 Watchdog Timer (WDT) */
+ PMC_IRQn = 5, /**< 5 SAMG55G18 Power Management Controller (PMC) */
+ EFC_IRQn = 6, /**< 6 SAMG55G18 Enhanced Flash Controller (EFC) */
+ USART0_IRQn = 8, /**< 8 SAMG55G18 FLEXCOM0 (USART0) */
+ SPI0_IRQn = 8, /**< 8 SAMG55G18 FLEXCOM0 (SPI0) */
+ TWI0_IRQn = 8, /**< 8 SAMG55G18 FLEXCOM0 (TWI0) */
+ USART1_IRQn = 9, /**< 9 SAMG55G18 FLEXCOM1 (USART1) */
+ SPI1_IRQn = 9, /**< 9 SAMG55G18 FLEXCOM1 (SPI1) */
+ TWI1_IRQn = 9, /**< 9 SAMG55G18 FLEXCOM1 (TWI1) */
+ PIOA_IRQn = 11, /**< 11 SAMG55G18 Parallel I/O Controller A (PIOA) */
+ PIOB_IRQn = 12, /**< 12 SAMG55G18 Parallel I/O Controller B (PIOB) */
+ PDMIC0_IRQn = 13, /**< 13 SAMG55G18 PDM 0 (PDMIC0) */
+ USART2_IRQn = 14, /**< 14 SAMG55G18 FLEXCOM2 (USART2) */
+ SPI2_IRQn = 14, /**< 14 SAMG55G18 FLEXCOM2 (SPI2) */
+ TWI2_IRQn = 14, /**< 14 SAMG55G18 FLEXCOM2 (TWI2) */
+ MEM2MEM_IRQn = 15, /**< 15 SAMG55G18 MEM2MEM (MEM2MEM) */
+ I2SC0_IRQn = 16, /**< 16 SAMG55G18 I2SC0 (I2SC0) */
+ I2SC1_IRQn = 17, /**< 17 SAMG55G18 I2SC1 (I2SC1) */
+ PDMIC1_IRQn = 18, /**< 18 SAMG55G18 PDM 1 (PDMIC1) */
+ USART3_IRQn = 19, /**< 19 SAMG55G18 FLEXCOM3 (USART3) */
+ SPI3_IRQn = 19, /**< 19 SAMG55G18 FLEXCOM3 (SPI3) */
+ TWI3_IRQn = 19, /**< 19 SAMG55G18 FLEXCOM3 (TWI3) */
+ USART4_IRQn = 20, /**< 20 SAMG55G18 FLEXCOM3 (USART4) */
+ SPI4_IRQn = 20, /**< 20 SAMG55G18 FLEXCOM3 (SPI4) */
+ TWI4_IRQn = 20, /**< 20 SAMG55G18 FLEXCOM3 (TWI4) */
+ USART5_IRQn = 21, /**< 21 SAMG55G18 FLEXCOM3 (USART5) */
+ SPI5_IRQn = 21, /**< 21 SAMG55G18 FLEXCOM3 (SPI5) */
+ TWI5_IRQn = 21, /**< 21 SAMG55G18 FLEXCOM3 (TWI5) */
+ USART6_IRQn = 22, /**< 22 SAMG55G18 FLEXCOM3 (USART6) */
+ SPI6_IRQn = 22, /**< 22 SAMG55G18 FLEXCOM3 (SPI6) */
+ TWI6_IRQn = 22, /**< 22 SAMG55G18 FLEXCOM3 (TWI6) */
+ TC0_IRQn = 23, /**< 23 SAMG55G18 Timer/Counter 0 (TC0) */
+ TC1_IRQn = 24, /**< 24 SAMG55G18 Timer/Counter 1 (TC1) */
+ TC2_IRQn = 25, /**< 25 SAMG55G18 Timer/Counter 2 (TC2) */
+ TC3_IRQn = 26, /**< 26 SAMG55G18 Timer/Counter 3 (TC3) */
+ TC4_IRQn = 27, /**< 27 SAMG55G18 Timer/Counter 4 (TC4) */
+ TC5_IRQn = 28, /**< 28 SAMG55G18 Timer/Counter 5 (TC5) */
+ ADC_IRQn = 29, /**< 29 SAMG55G18 Analog To Digital Converter (ADC) */
+ ARM_IRQn = 30, /**< 30 SAMG55G18 FPU (ARM) */
+ WKUP0_IRQn = 31, /**< 31 SAMG55J18 External interrupt 0 (WKUP0) */
+ WKUP1_IRQn = 32, /**< 32 SAMG55J18 External interrupt 1 (WKUP1) */
+ WKUP2_IRQn = 33, /**< 33 SAMG55J18 External interrupt 2 (WKUP2) */
+ WKUP3_IRQn = 34, /**< 34 SAMG55J18 External interrupt 3 (WKUP3) */
+ WKUP4_IRQn = 35, /**< 35 SAMG55J18 External interrupt 4 (WKUP4) */
+ WKUP5_IRQn = 36, /**< 36 SAMG55J18 External interrupt 5 (WKUP5) */
+ WKUP6_IRQn = 37, /**< 37 SAMG55J18 External interrupt 6 (WKUP6) */
+ WKUP7_IRQn = 38, /**< 38 SAMG55J18 External interrupt 7 (WKUP7) */
+ WKUP8_IRQn = 39, /**< 39 SAMG55J18 External interrupt 8 (WKUP8) */
+ WKUP9_IRQn = 40, /**< 40 SAMG55J18 External interrupt 9 (WKUP9) */
+ WKUP10_IRQn = 41, /**< 41 SAMG55J18 External interrupt 10 (WKUP10) */
+ WKUP11_IRQn = 42, /**< 42 SAMG55J18 External interrupt 11 (WKUP11) */
+ WKUP12_IRQn = 43, /**< 43 SAMG55J18 External interrupt 12 (WKUP12) */
+ WKUP13_IRQn = 44, /**< 44 SAMG55J18 External interrupt 13 (WKUP13) */
+ WKUP14_IRQn = 45, /**< 45 SAMG55J18 External interrupt 14 (WKUP14) */
+ WKUP15_IRQn = 46, /**< 46 SAMG55J18 External interrupt 15 (WKUP15) */
+ UHP_IRQn = 47, /**< 47 SAMG55G18 USB OHCI (UHP) */
+ UDP_IRQn = 48, /**< 48 SAMG55G18 USB Device FS (UDP) */
+
+ PERIPH_COUNT_IRQn = 49 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnMemManage_Handler;
+ void* pfnBusFault_Handler;
+ void* pfnUsageFault_Handler;
+ void* pfnReserved1_Handler;
+ void* pfnReserved2_Handler;
+ void* pfnReserved3_Handler;
+ void* pfnReserved4_Handler;
+ void* pfnSVC_Handler;
+ void* pfnDebugMon_Handler;
+ void* pfnReserved5_Handler;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnSUPC_Handler; /* 0 Supply Controller */
+ void* pfnRSTC_Handler; /* 1 Reset Controller */
+ void* pfnRTC_Handler; /* 2 Real Time Clock */
+ void* pfnRTT_Handler; /* 3 Real Time Timer */
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */
+ void* pfnPMC_Handler; /* 5 Power Management Controller */
+ void* pfnEFC_Handler; /* 6 Enhanced Flash Controller */
+ void* pvReserved7;
+ void* pfnUSART0_Handler; /* 8 FLEXCOM 0 */
+ void* pfnSPI0_Handler; /* 8 FLEXCOM 0 */
+ void* pfnTWI0_Handler; /* 8 FLEXCOM 0 */
+ void* pfnUSART1_Handler; /* 9 FLEXCOM 1 */
+ void* pfnSPI1_Handler; /* 9 FLEXCOM 1 */
+ void* pfnTWI1_Handler; /* 9 FLEXCOM 1 */
+ void* pvReserved10;
+ void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */
+ void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */
+ void* pfnPDMIC0_Handler; /* 13 PDM 0 */
+ void* pfnUSART2_Handler; /* 14 FLEXCOM 2 */
+ void* pfnSPI2_Handler; /* 14 FLEXCOM 2 */
+ void* pfnTWI2_Handler; /* 14 FLEXCOM 2 */
+ void* pfnMEM2MEM_Handler; /* 15 MEM2MEM */
+ void* pfnI2SC0_Handler; /* 16 I2SC0 */
+ void* pfnI2SC1_Handler; /* 17 I2SC1 */
+ void* pfnPDMIC1_Handler; /* 18 PDM 1 */
+ void* pfnUSART3_Handler; /* 19 FLEXCOM 3 */
+ void* pfnSPI3_Handler; /* 19 FLEXCOM 3 */
+ void* pfnTWI3_Handler; /* 19 FLEXCOM 3 */
+ void* pfnUSART4_Handler; /* 20 FLEXCOM 4 */
+ void* pfnSPI4_Handler; /* 20 FLEXCOM 4 */
+ void* pfnTWI4_Handler; /* 20 FLEXCOM 4 */
+ void* pfnUSART5_Handler; /* 21 FLEXCOM 5 */
+ void* pfnSPI5_Handler; /* 21 FLEXCOM 5 */
+ void* pfnTWI5_Handler; /* 21 FLEXCOM 5 */
+ void* pfnUSART6_Handler; /* 22 FLEXCOM 6 */
+ void* pfnSPI6_Handler; /* 22 FLEXCOM 6 */
+ void* pfnTWI6_Handler; /* 22 FLEXCOM 6 */
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
+ void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
+ void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
+ void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
+ void* pfnADC_Handler; /* 29 Analog To Digital Converter */
+ void* pfnARM_Handler; /* 30 FPU */
+ void* pvReserved31;
+ void* pvReserved32;
+ void* pvReserved33;
+ void* pvReserved34;
+ void* pvReserved35;
+ void* pvReserved36;
+ void* pvReserved37;
+ void* pvReserved38;
+ void* pvReserved39;
+ void* pvReserved40;
+ void* pvReserved41;
+ void* pvReserved42;
+ void* pvReserved43;
+ void* pvReserved44;
+ void* pvReserved45;
+ void* pvReserved46;
+ void* pfnUHP_Handler; /* 47 USB OHCI */
+ void* pfnUDP_Handler; /* 48 USB Device FS */
+ void* pvReserved49; /* */
+ void* pvReserved50; /* */
+ void* pvReserved51; /* */
+ void* pvReserved52; /* */
+ void* pvReserved53; /* */
+ void* pvReserved54; /* */
+ void* pvReserved55; /* */
+ void* pvReserved56; /* */
+ void* pvReserved57; /* */
+ void* pvReserved58; /* */
+ void* pvReserved59; /* */
+ void* pvReserved60; /* */
+ void* pvReserved61; /* */
+ void* pvReserved62; /* */
+ void* pvReserved63; /* UHP */
+ void* pvReserved64; /* UDP */
+ void* pvReserved65; /* CRCCU */
+} DeviceVectors;
+
+/* Cortex-M4 core handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void MemManage_Handler ( void );
+void BusFault_Handler ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler ( void );
+void DebugMon_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void ADC_Handler ( void );
+void ARM_Handler ( void );
+void EFC_Handler ( void );
+void I2SC0_Handler ( void );
+void I2SC1_Handler ( void );
+void MEM2MEM_Handler ( void );
+void PDMIC0_Handler ( void );
+void PDMIC1_Handler ( void );
+void PIOA_Handler ( void );
+void PIOB_Handler ( void );
+void PMC_Handler ( void );
+void RSTC_Handler ( void );
+void RTC_Handler ( void );
+void RTT_Handler ( void );
+void SPI0_Handler ( void );
+void SPI1_Handler ( void );
+void SPI2_Handler ( void );
+void SPI3_Handler ( void );
+void SPI4_Handler ( void );
+void SPI5_Handler ( void );
+void SPI6_Handler ( void );
+void SUPC_Handler ( void );
+void TC0_Handler ( void );
+void TC1_Handler ( void );
+void TC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TWI0_Handler ( void );
+void TWI1_Handler ( void );
+void TWI2_Handler ( void );
+void TWI3_Handler ( void );
+void TWI4_Handler ( void );
+void TWI5_Handler ( void );
+void TWI6_Handler ( void );
+void UDP_Handler ( void );
+void UHP_Handler ( void );
+void USART0_Handler ( void );
+void USART1_Handler ( void );
+void USART2_Handler ( void );
+void USART3_Handler ( void );
+void USART4_Handler ( void );
+void USART5_Handler ( void );
+void USART6_Handler ( void );
+void WDT_Handler ( void );
+
+/**
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define __CM4_REV 0x0001 /**< SAMG55G18 core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT 1 /**< SAMG55G18 does provide a MPU */
+#define __FPU_PRESENT 1 /**< SAMG55G18 does provide a FPU */
+#define __NVIC_PRIO_BITS 4 /**< SAMG55G18 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include <core_cm4.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samg55.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMG55G18 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55G18_api Peripheral Software API */
+/*@{*/
+
+#include "comp_adc.h"
+#include "comp_chipid.h"
+#include "comp_cmcc.h"
+#include "comp_crccu.h"
+#include "comp_efc.h"
+#include "comp_flexcom.h"
+#include "comp_gpbr.h"
+#include "comp_i2sc.h"
+#include "comp_matrix.h"
+#include "comp_mem2mem.h"
+#include "comp_pdc.h"
+#include "comp_pdmic.h"
+#include "comp_pio.h"
+#include "comp_pmc.h"
+#include "comp_rstc.h"
+#include "comp_rtc.h"
+#include "comp_rtt.h"
+#include "comp_spi.h"
+#include "comp_supc.h"
+#include "comp_tc.h"
+#include "comp_twi.h"
+#include "comp_twihs.h"
+#include "comp_udp.h"
+#include "comp_usart.h"
+#include "comp_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* REGISTER ACCESS DEFINITIONS FOR SAMG55G18 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55G18_reg Registers Access Definitions */
+/*@{*/
+
+#include "ins_i2sc0.h"
+#include "ins_i2sc1.h"
+#include "ins_flexcom5.h"
+#include "ins_usart5.h"
+#include "ins_spi5.h"
+#include "ins_twi5.h"
+#include "ins_flexcom0.h"
+#include "ins_usart0.h"
+#include "ins_spi0.h"
+#include "ins_twi0.h"
+#include "ins_tc0.h"
+#include "ins_tc1.h"
+#include "ins_flexcom3.h"
+#include "ins_usart3.h"
+#include "ins_spi3.h"
+#include "ins_twi3.h"
+#include "ins_flexcom4.h"
+#include "ins_usart4.h"
+#include "ins_spi4.h"
+#include "ins_twi4.h"
+#include "ins_flexcom1.h"
+#include "ins_usart1.h"
+#include "ins_spi1.h"
+#include "ins_twi1.h"
+#include "ins_flexcom2.h"
+#include "ins_usart2.h"
+#include "ins_spi2.h"
+#include "ins_twi2.h"
+#include "ins_mem2mem.h"
+#include "ins_pdmic0.h"
+#include "ins_pdmic1.h"
+#include "ins_flexcom7.h"
+#include "ins_adc.h"
+#include "ins_cmcc.h"
+#include "ins_flexcom6.h"
+#include "ins_usart6.h"
+#include "ins_spi6.h"
+#include "ins_twi6.h"
+#include "ins_udp.h"
+#include "ins_crccu.h"
+#include "ins_uhp.h"
+#include "ins_matrix.h"
+#include "ins_pmc.h"
+#include "ins_chipid.h"
+#include "ins_efc.h"
+#include "ins_pioa.h"
+#include "ins_piob.h"
+#include "ins_rstc.h"
+#include "ins_supc.h"
+#include "ins_rtt.h"
+#include "ins_wdt.h"
+#include "ins_rtc.h"
+#include "ins_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* PERIPHERAL ID DEFINITIONS FOR SAMG55G18 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55G18_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_USART0 ( 8) /**< \brief FLEXCOM 0 (USART0) */
+#define ID_SPI0 ( 8) /**< \brief FLEXCOM 0 (SPI0) */
+#define ID_TWI0 ( 8) /**< \brief FLEXCOM 0 (TWI0) */
+#define ID_USART1 ( 9) /**< \brief FLEXCOM 1 (USART1) */
+#define ID_SPI1 ( 9) /**< \brief FLEXCOM 1 (SPI1) */
+#define ID_TWI1 ( 9) /**< \brief FLEXCOM 1 (TWI1) */
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PDMIC0 (13) /**< \brief PDM 0 (PDMIC0) */
+#define ID_USART2 (14) /**< \brief FLEXCOM2 (USART2) */
+#define ID_SPI2 (14) /**< \brief FLEXCOM2 (SPI2) */
+#define ID_TWI2 (14) /**< \brief FLEXCOM2 (TWI2) */
+#define ID_MEM2MEM (15) /**< \brief MEM2MEM (MEM2MEM) */
+#define ID_I2SC0 (16) /**< \brief I2SC0 (I2SC0) */
+#define ID_I2SC1 (17) /**< \brief I2SC1 (I2SC1) */
+#define ID_PDMIC1 (18) /**< \brief PDM 1 (PDMIC1) */
+#define ID_USART3 (19) /**< \brief FLEXCOM3 (USART3) */
+#define ID_SPI3 (19) /**< \brief FLEXCOM3 (SPI3) */
+#define ID_TWI3 (19) /**< \brief FLEXCOM3 (TWI3) */
+#define ID_USART4 (20) /**< \brief FLEXCOM4 (USART4) */
+#define ID_SPI4 (20) /**< \brief FLEXCOM4 (SPI4) */
+#define ID_TWI4 (20) /**< \brief FLEXCOM4 (TWI4) */
+#define ID_USART5 (21) /**< \brief FLEXCOM5 (USART5) */
+#define ID_SPI5 (21) /**< \brief FLEXCOM5 (SPI5) */
+#define ID_TWI5 (21) /**< \brief FLEXCOM5 (TWI5) */
+#define ID_USART6 (22) /**< \brief FLEXCOM6 (USART6) */
+#define ID_SPI6 (22) /**< \brief FLEXCOM6 (SPI6) */
+#define ID_TWI6 (22) /**< \brief FLEXCOM6 (TWI6) */
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_ARM (30) /**< \brief FPU (ARM) */
+#define ID_UHP (47) /**< \brief USB OHCI (UHP) */
+#define ID_UDP (48) /**< \brief USB Device FS (UDP) */
+#define ID_CRCCU (49) /**< \brief CRCCU (CRCCU) */
+
+#define ID_PERIPH_COUNT (50) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/* BASE ADDRESS DEFINITIONS FOR SAMG55G18 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55G18_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define I2SC0 (0x40000000U) /**< \brief (I2SC0 ) Base Address */
+#define PDC_I2SC0 (0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */
+#define I2SC1 (0x40004000U) /**< \brief (I2SC1 ) Base Address */
+#define PDC_I2SC1 (0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */
+#define FLEXCOM5 (0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */
+#define USART5 (0x40008200U) /**< \brief (USART5 ) Base Address */
+#define PDC_USART5 (0x40008300U) /**< \brief (PDC_USART5 ) Base Address */
+#define SPI5 (0x40008400U) /**< \brief (SPI5 ) Base Address */
+#define PDC_SPI5 (0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */
+#define TWI5 (0x40008600U) /**< \brief (TWI5 ) Base Address */
+#define PDC_TWI5 (0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */
+#define FLEXCOM0 (0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */
+#define USART0 (0x4000C200U) /**< \brief (USART0 ) Base Address */
+#define PDC_USART0 (0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */
+#define SPI0 (0x4000C400U) /**< \brief (SPI0 ) Base Address */
+#define PDC_SPI0 (0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */
+#define TWI0 (0x4000C600U) /**< \brief (TWI0 ) Base Address */
+#define PDC_TWI0 (0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */
+#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */
+#define PDC_TC0 (0x40010100U) /**< \brief (PDC_TC0 ) Base Address */
+#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */
+#define FLEXCOM3 (0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */
+#define USART3 (0x40018200U) /**< \brief (USART3 ) Base Address */
+#define PDC_USART3 (0x40018300U) /**< \brief (PDC_USART3 ) Base Address */
+#define SPI3 (0x40018400U) /**< \brief (SPI3 ) Base Address */
+#define PDC_SPI3 (0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */
+#define TWI3 (0x40018600U) /**< \brief (TWI3 ) Base Address */
+#define PDC_TWI3 (0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */
+#define FLEXCOM4 (0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */
+#define USART4 (0x4001C200U) /**< \brief (USART4 ) Base Address */
+#define PDC_USART4 (0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */
+#define SPI4 (0x4001C400U) /**< \brief (SPI4 ) Base Address */
+#define PDC_SPI4 (0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */
+#define TWI4 (0x4001C600U) /**< \brief (TWI4 ) Base Address */
+#define PDC_TWI4 (0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */
+#define FLEXCOM1 (0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */
+#define USART1 (0x40020200U) /**< \brief (USART1 ) Base Address */
+#define PDC_USART1 (0x40020300U) /**< \brief (PDC_USART1 ) Base Address */
+#define SPI1 (0x40020400U) /**< \brief (SPI1 ) Base Address */
+#define PDC_SPI1 (0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */
+#define TWI1 (0x40020600U) /**< \brief (TWI1 ) Base Address */
+#define PDC_TWI1 (0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */
+#define FLEXCOM2 (0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */
+#define USART2 (0x40024200U) /**< \brief (USART2 ) Base Address */
+#define PDC_USART2 (0x40024300U) /**< \brief (PDC_USART2 ) Base Address */
+#define SPI2 (0x40024400U) /**< \brief (SPI2 ) Base Address */
+#define PDC_SPI2 (0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */
+#define TWI2 (0x40024600U) /**< \brief (TWI2 ) Base Address */
+#define PDC_TWI2 (0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */
+#define MEM2MEM (0x40028000U) /**< \brief (MEM2MEM ) Base Address */
+#define PDC_MEM2MEM (0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */
+#define PDMIC0 (0x4002C000U) /**< \brief (PDMIC0 ) Base Address */
+#define PDC_PDMIC0 (0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */
+#define PDMIC1 (0x40030000U) /**< \brief (PDMIC1 ) Base Address */
+#define PDC_PDMIC1 (0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */
+#define FLEXCOM7 (0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */
+#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */
+#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */
+#define CMCC (0x4003C000U) /**< \brief (CMCC ) Base Address */
+#define FLEXCOM6 (0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */
+#define USART6 (0x40040200U) /**< \brief (USART6 ) Base Address */
+#define PDC_USART6 (0x40040300U) /**< \brief (PDC_USART6 ) Base Address */
+#define SPI6 (0x40040400U) /**< \brief (SPI6 ) Base Address */
+#define PDC_SPI6 (0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */
+#define TWI6 (0x40040600U) /**< \brief (TWI6 ) Base Address */
+#define PDC_TWI6 (0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */
+#define UDP (0x40044000U) /**< \brief (UDP ) Base Address */
+#define CRCCU (0x40048000U) /**< \brief (CRCCU ) Base Address */
+#define UHP (0x4004C000U) /**< \brief (UHP ) Base Address */
+#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */
+#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */
+#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */
+#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
+#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */
+#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */
+#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */
+#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */
+#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */
+#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */
+#else
+#define I2SC0 ((I2sc *)0x40000000U) /**< \brief (I2SC0 ) Base Address */
+#define PDC_I2SC0 ((Pdc *)0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */
+#define I2SC1 ((I2sc *)0x40004000U) /**< \brief (I2SC1 ) Base Address */
+#define PDC_I2SC1 ((Pdc *)0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */
+#define FLEXCOM5 ((Flexcom *)0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */
+#define USART5 ((Usart *)0x40008200U) /**< \brief (USART5 ) Base Address */
+#define PDC_USART5 ((Pdc *)0x40008300U) /**< \brief (PDC_USART5 ) Base Address */
+#define SPI5 ((Spi *)0x40008400U) /**< \brief (SPI5 ) Base Address */
+#define PDC_SPI5 ((Pdc *)0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */
+#define TWI5 ((Twi *)0x40008600U) /**< \brief (TWI5 ) Base Address */
+#define PDC_TWI5 ((Pdc *)0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */
+#define FLEXCOM0 ((Flexcom *)0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */
+#define USART0 ((Usart *)0x4000C200U) /**< \brief (USART0 ) Base Address */
+#define PDC_USART0 ((Pdc *)0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */
+#define SPI0 ((Spi *)0x4000C400U) /**< \brief (SPI0 ) Base Address */
+#define PDC_SPI0 ((Pdc *)0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */
+#define TWI0 ((Twi *)0x4000C600U) /**< \brief (TWI0 ) Base Address */
+#define PDC_TWI0 ((Pdc *)0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */
+#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */
+#define PDC_TC0 ((Pdc *)0x40010100U) /**< \brief (PDC_TC0 ) Base Address */
+#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */
+#define FLEXCOM3 ((Flexcom *)0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */
+#define USART3 ((Usart *)0x40018200U) /**< \brief (USART3 ) Base Address */
+#define PDC_USART3 ((Pdc *)0x40018300U) /**< \brief (PDC_USART3 ) Base Address */
+#define SPI3 ((Spi *)0x40018400U) /**< \brief (SPI3 ) Base Address */
+#define PDC_SPI3 ((Pdc *)0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */
+#define TWI3 ((Twihs *)0x40018600U) /**< \brief (TWI3 ) Base Address */
+#define PDC_TWI3 ((Pdc *)0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */
+#define FLEXCOM4 ((Flexcom *)0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */
+#define USART4 ((Usart *)0x4001C200U) /**< \brief (USART4 ) Base Address */
+#define PDC_USART4 ((Pdc *)0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */
+#define SPI4 ((Spi *)0x4001C400U) /**< \brief (SPI4 ) Base Address */
+#define PDC_SPI4 ((Pdc *)0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */
+#define TWI4 ((Twi *)0x4001C600U) /**< \brief (TWI4 ) Base Address */
+#define PDC_TWI4 ((Pdc *)0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */
+#define FLEXCOM1 ((Flexcom *)0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */
+#define USART1 ((Usart *)0x40020200U) /**< \brief (USART1 ) Base Address */
+#define PDC_USART1 ((Pdc *)0x40020300U) /**< \brief (PDC_USART1 ) Base Address */
+#define SPI1 ((Spi *)0x40020400U) /**< \brief (SPI1 ) Base Address */
+#define PDC_SPI1 ((Pdc *)0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */
+#define TWI1 ((Twi *)0x40020600U) /**< \brief (TWI1 ) Base Address */
+#define PDC_TWI1 ((Pdc *)0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */
+#define FLEXCOM2 ((Flexcom *)0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */
+#define USART2 ((Usart *)0x40024200U) /**< \brief (USART2 ) Base Address */
+#define PDC_USART2 ((Pdc *)0x40024300U) /**< \brief (PDC_USART2 ) Base Address */
+#define SPI2 ((Spi *)0x40024400U) /**< \brief (SPI2 ) Base Address */
+#define PDC_SPI2 ((Pdc *)0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */
+#define TWI2 ((Twi *)0x40024600U) /**< \brief (TWI2 ) Base Address */
+#define PDC_TWI2 ((Pdc *)0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */
+#define MEM2MEM ((Mem2mem *)0x40028000U) /**< \brief (MEM2MEM ) Base Address */
+#define PDC_MEM2MEM ((Pdc *)0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */
+#define PDMIC0 ((Pdmic *)0x4002C000U) /**< \brief (PDMIC0 ) Base Address */
+#define PDC_PDMIC0 ((Pdc *)0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */
+#define PDMIC1 ((Pdmic *)0x40030000U) /**< \brief (PDMIC1 ) Base Address */
+#define PDC_PDMIC1 ((Pdc *)0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */
+#define FLEXCOM7 ((Flexcom *)0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */
+#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */
+#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */
+#define CMCC ((Cmcc *)0x4003C000U) /**< \brief (CMCC ) Base Address */
+#define FLEXCOM6 ((Flexcom *)0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */
+#define USART6 ((Usart *)0x40040200U) /**< \brief (USART6 ) Base Address */
+#define PDC_USART6 ((Pdc *)0x40040300U) /**< \brief (PDC_USART6 ) Base Address */
+#define SPI6 ((Spi *)0x40040400U) /**< \brief (SPI6 ) Base Address */
+#define PDC_SPI6 ((Pdc *)0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */
+#define TWI6 ((Twi *)0x40040600U) /**< \brief (TWI6 ) Base Address */
+#define PDC_TWI6 ((Pdc *)0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */
+#define UDP ((Udp *)0x40044000U) /**< \brief (UDP ) Base Address */
+#define CRCCU ((Crccu *)0x40048000U) /**< \brief (CRCCU ) Base Address */
+#define UHP ((Uhp *)0x4004C000U) /**< \brief (UHP ) Base Address */
+#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */
+#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */
+#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */
+#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
+#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */
+#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */
+#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */
+#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */
+#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */
+#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/* PIO DEFINITIONS FOR SAMG55G18 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55G18_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio_samg55g18.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* MEMORY MAPPING DEFINITIONS FOR SAMG55G18 */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE (0x40000u)
+#define IFLASH_PAGE_SIZE (512u)
+#define IFLASH_LOCK_REGION_SIZE (8192u)
+#define IFLASH_NB_OF_PAGES (512u)
+#define IFLASH_NB_OF_LOCK_BITS (32u)
+#define IRAM_SIZE (0x28000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/* MISCELLANEOUS DEFINITIONS FOR SAMG55G18 */
+/* ************************************************************************** */
+
+#define CHIP_JTAGID (0x05B3E03FUL)
+#define CHIP_CIDR (0x244709E0UL)
+#define CHIP_EXID (0x0UL)
+#define NB_CH_ADC (8UL)
+
+/* ************************************************************************** */
+/* ELECTRICAL DEFINITIONS FOR SAMG55G18 */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
+#define CHIP_FREQ_SLCK_RC (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_16MHZ (16000000UL)
+#define CHIP_FREQ_MAINCK_RC_24MHZ (24000000UL)
+#define CHIP_FREQ_CPU_MAX (120000000UL)
+#define CHIP_FREQ_XTAL_32K (32768UL)
+
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE (5U)
+
+/* Embedded Flash Read Wait State (VDDIO set at 1.62V, Max value) */
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
+#define CHIP_FREQ_FWS_5 (120000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAMG55G18_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55g19.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,662 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55G19_
+#define _SAMG55G19_
+
+/** \addtogroup SAMG55G19_definitions SAMG55G19 definitions
+ This file defines all structures and symbols for SAMG55G19:
+ - registers and bitfields
+ - peripheral base address
+ - peripheral ID
+ - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#endif
+
+/* ************************************************************************** */
+/* CMSIS DEFINITIONS FOR SAMG55G19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55G19_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn {
+ /****** Cortex-M4 Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
+ /****** SAMG55G19 specific Interrupt Numbers *********************************/
+
+ SUPC_IRQn = 0, /**< 0 SAMG55G19 Supply Controller (SUPC) */
+ RSTC_IRQn = 1, /**< 1 SAMG55G19 Reset Controller (RSTC) */
+ RTC_IRQn = 2, /**< 2 SAMG55G19 Real Time Clock (RTC) */
+ RTT_IRQn = 3, /**< 3 SAMG55G19 Real Time Timer (RTT) */
+ WDT_IRQn = 4, /**< 4 SAMG55G19 Watchdog Timer (WDT) */
+ PMC_IRQn = 5, /**< 5 SAMG55G19 Power Management Controller (PMC) */
+ EFC_IRQn = 6, /**< 6 SAMG55G19 Enhanced Flash Controller (EFC) */
+ FLEXCOM0_IRQn = 8, /**< 8 SAMG55G19 FLEXCOM 0 (FLEXCOM0) */
+ FLEXCOM1_IRQn = 9, /**< 9 SAMG55G19 FLEXCOM 1 (FLEXCOM1) */
+ PIOA_IRQn = 11, /**< 11 SAMG55G19 Parallel I/O Controller A (PIOA) */
+ PIOB_IRQn = 12, /**< 12 SAMG55G19 Parallel I/O Controller B (PIOB) */
+ PDMIC0_IRQn = 13, /**< 13 SAMG55G19 PDM 0 (PDMIC0) */
+ FLEXCOM2_IRQn = 14, /**< 14 SAMG55G19 FLEXCOM2 (FLEXCOM2) */
+ MEM2MEM_IRQn = 15, /**< 15 SAMG55G19 MEM2MEM (MEM2MEM) */
+ I2SC0_IRQn = 16, /**< 16 SAMG55G19 I2SC0 (I2SC0) */
+ I2SC1_IRQn = 17, /**< 17 SAMG55G19 I2SC1 (I2SC1) */
+ PDMIC1_IRQn = 18, /**< 18 SAMG55G19 PDM 1 (PDMIC1) */
+ FLEXCOM3_IRQn = 19, /**< 19 SAMG55G19 FLEXCOM3 (FLEXCOM3) */
+ FLEXCOM4_IRQn = 20, /**< 20 SAMG55G19 FLEXCOM4 (FLEXCOM4) */
+ FLEXCOM5_IRQn = 21, /**< 21 SAMG55G19 FLEXCOM5 (FLEXCOM5) */
+ FLEXCOM6_IRQn = 22, /**< 22 SAMG55G19 FLEXCOM6 (FLEXCOM6) */
+ TC0_IRQn = 23, /**< 23 SAMG55G19 Timer/Counter 0 (TC0) */
+ TC1_IRQn = 24, /**< 24 SAMG55G19 Timer/Counter 1 (TC1) */
+ TC2_IRQn = 25, /**< 25 SAMG55G19 Timer/Counter 2 (TC2) */
+ TC3_IRQn = 26, /**< 26 SAMG55G19 Timer/Counter 3 (TC3) */
+ TC4_IRQn = 27, /**< 27 SAMG55G19 Timer/Counter 4 (TC4) */
+ TC5_IRQn = 28, /**< 28 SAMG55G19 Timer/Counter 5 (TC5) */
+ ADC_IRQn = 29, /**< 29 SAMG55G19 Analog To Digital Converter (ADC) */
+ ARM_IRQn = 30, /**< 30 SAMG55G19 FPU (ARM) */
+ WKUP0_IRQn = 31, /**< 31 SAMG55G19 External interrupt 0 (WKUP0) */
+ WKUP1_IRQn = 32, /**< 32 SAMG55G19 External interrupt 1 (WKUP1) */
+ WKUP2_IRQn = 33, /**< 33 SAMG55G19 External interrupt 2 (WKUP2) */
+ WKUP3_IRQn = 34, /**< 34 SAMG55G19 External interrupt 3 (WKUP3) */
+ WKUP4_IRQn = 35, /**< 35 SAMG55G19 External interrupt 4 (WKUP4) */
+ WKUP5_IRQn = 36, /**< 36 SAMG55G19 External interrupt 5 (WKUP5) */
+ WKUP6_IRQn = 37, /**< 37 SAMG55G19 External interrupt 6 (WKUP6) */
+ WKUP7_IRQn = 38, /**< 38 SAMG55G19 External interrupt 7 (WKUP7) */
+ WKUP8_IRQn = 39, /**< 39 SAMG55G19 External interrupt 8 (WKUP8) */
+ WKUP9_IRQn = 40, /**< 40 SAMG55G19 External interrupt 9 (WKUP9) */
+ WKUP10_IRQn = 41, /**< 41 SAMG55G19 External interrupt 10 (WKUP10) */
+ WKUP11_IRQn = 42, /**< 42 SAMG55G19 External interrupt 11 (WKUP11) */
+ WKUP12_IRQn = 43, /**< 43 SAMG55G19 External interrupt 12 (WKUP12) */
+ WKUP13_IRQn = 44, /**< 44 SAMG55G19 External interrupt 13 (WKUP13) */
+ WKUP14_IRQn = 45, /**< 45 SAMG55G19 External interrupt 14 (WKUP14) */
+ WKUP15_IRQn = 46, /**< 46 SAMG55G19 External interrupt 15 (WKUP15) */
+ UHP_IRQn = 47, /**< 47 SAMG55G19 USB OHCI (UHP) */
+ UDP_IRQn = 48, /**< 48 SAMG55G19 USB Device FS (UDP) */
+ CRCCU_IRQn = 49, /**< 49 SAMG55G19 CRCCU */
+ PERIPH_COUNT_IRQn = 50 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnMemManage_Handler;
+ void* pfnBusFault_Handler;
+ void* pfnUsageFault_Handler;
+ void* pfnReserved1_Handler;
+ void* pfnReserved2_Handler;
+ void* pfnReserved3_Handler;
+ void* pfnReserved4_Handler;
+ void* pfnSVC_Handler;
+ void* pfnDebugMon_Handler;
+ void* pfnReserved5_Handler;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnSUPC_Handler; /* 0 Supply Controller */
+ void* pfnRSTC_Handler; /* 1 Reset Controller */
+ void* pfnRTC_Handler; /* 2 Real Time Clock */
+ void* pfnRTT_Handler; /* 3 Real Time Timer */
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */
+ void* pfnPMC_Handler; /* 5 Power Management Controller */
+ void* pfnEFC_Handler; /* 6 Enhanced Flash Controller */
+ void* pvReserved7;
+ void* pfnFLEXCOM0_Handler; /* 8 FLEXCOM 0 */
+ void* pfnFLEXCOM1_Handler; /* 9 FLEXCOM 1 */
+ void* pvReserved10;
+ void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */
+ void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */
+ void* pfnPDMIC0_Handler; /* 13 PDM 0 */
+ void* pfnFLEXCOM2_Handler; /* 14 FLEXCOM 2 */
+ void* pfnMEM2MEM_Handler; /* 15 MEM2MEM */
+ void* pfnI2SC0_Handler; /* 16 I2SC0 */
+ void* pfnI2SC1_Handler; /* 17 I2SC1 */
+ void* pfnPDMIC1_Handler; /* 18 PDM 1 */
+ void* pfnFLEXCOM3_Handler; /* 19 FLEXCOM 3 */
+ void* pfnFLEXCOM4_Handler; /* 20 FLEXCOM 4 */
+ void* pfnFLEXCOM5_Handler; /* 21 FLEXCOM 5 */
+ void* pfnFLEXCOM6_Handler; /* 22 FLEXCOM 6 */
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
+ void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
+ void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
+ void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
+ void* pfnADC_Handler; /* 29 Analog To Digital Converter */
+ void* pfnARM_Handler; /* 30 FPU */
+ void* pvReserved31;
+ void* pvReserved32;
+ void* pvReserved33;
+ void* pvReserved34;
+ void* pvReserved35;
+ void* pvReserved36;
+ void* pvReserved37;
+ void* pvReserved38;
+ void* pvReserved39;
+ void* pvReserved40;
+ void* pvReserved41;
+ void* pvReserved42;
+ void* pvReserved43;
+ void* pvReserved44;
+ void* pvReserved45;
+ void* pvReserved46;
+ void* pfnUHP_Handler; /* 47 USB OHCI */
+ void* pfnUDP_Handler; /* 48 USB Device FS */
+ void* pfnCRCCU_Handler; /*49 CRCCU Device */
+ void* pvReserved50; /* */
+ void* pvReserved51; /* */
+ void* pvReserved52; /* */
+ void* pvReserved53; /* */
+ void* pvReserved54; /* */
+ void* pvReserved55; /* */
+ void* pvReserved56; /* */
+ void* pvReserved57; /* */
+ void* pvReserved58; /* */
+ void* pvReserved59; /* */
+ void* pvReserved60; /* */
+ void* pvReserved61; /* */
+ void* pvReserved62; /* */
+ void* pvReserved63; /* UHP */
+ void* pvReserved64; /* UDP */
+ void* pvReserved65; /* CRCCU */
+} DeviceVectors;
+
+/* Cortex-M4 core handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void MemManage_Handler ( void );
+void BusFault_Handler ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler ( void );
+void DebugMon_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void ADC_Handler ( void );
+void ARM_Handler ( void );
+void CRCCU_Handler ( void );
+void EFC_Handler ( void );
+void I2SC0_Handler ( void );
+void I2SC1_Handler ( void );
+void MEM2MEM_Handler ( void );
+void PDMIC0_Handler ( void );
+void PDMIC1_Handler ( void );
+void PIOA_Handler ( void );
+void PIOB_Handler ( void );
+void PMC_Handler ( void );
+void RSTC_Handler ( void );
+void RTC_Handler ( void );
+void RTT_Handler ( void );
+void SUPC_Handler ( void );
+void TC0_Handler ( void );
+void TC1_Handler ( void );
+void TC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void UDP_Handler ( void );
+void UHP_Handler ( void );
+void FLEXCOM0_Handler ( void );
+void FLEXCOM1_Handler ( void );
+void FLEXCOM2_Handler ( void );
+void FLEXCOM3_Handler ( void );
+void FLEXCOM4_Handler ( void );
+void FLEXCOM5_Handler ( void );
+void FLEXCOM6_Handler ( void );
+void WDT_Handler ( void );
+/**
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define __CM4_REV 0x0001 /**< SAMG55G19 core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT 1 /**< SAMG55G19 does provide a MPU */
+#define __FPU_PRESENT 1 /**< SAMG55G19 does provide a FPU */
+#define __NVIC_PRIO_BITS 4 /**< SAMG55G19 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include <core_cm4.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samg55.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMG55G19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55G19_api Peripheral Software API */
+/*@{*/
+
+#include "comp_adc.h"
+#include "comp_chipid.h"
+#include "comp_cmcc.h"
+#include "comp_crccu.h"
+#include "comp_efc.h"
+#include "comp_flexcom.h"
+#include "comp_gpbr.h"
+#include "comp_i2sc.h"
+#include "comp_matrix.h"
+#include "comp_mem2mem.h"
+#include "comp_pdc.h"
+#include "comp_pdmic.h"
+#include "comp_pio.h"
+#include "comp_pmc.h"
+#include "comp_rstc.h"
+#include "comp_rtc.h"
+#include "comp_rtt.h"
+#include "comp_spi.h"
+#include "comp_supc.h"
+#include "comp_tc.h"
+#include "comp_twi.h"
+#include "comp_udp.h"
+#include "comp_uhp.h"
+#include "comp_usart.h"
+#include "comp_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* REGISTER ACCESS DEFINITIONS FOR SAMG55G19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55G19_reg Registers Access Definitions */
+/*@{*/
+
+#include "ins_i2sc0.h"
+#include "ins_i2sc1.h"
+#include "ins_flexcom5.h"
+#include "ins_usart5.h"
+#include "ins_spi5.h"
+#include "ins_twi5.h"
+#include "ins_flexcom0.h"
+#include "ins_usart0.h"
+#include "ins_spi0.h"
+#include "ins_twi0.h"
+#include "ins_tc0.h"
+#include "ins_tc1.h"
+#include "ins_flexcom3.h"
+#include "ins_usart3.h"
+#include "ins_spi3.h"
+#include "ins_twi3.h"
+#include "ins_flexcom4.h"
+#include "ins_usart4.h"
+#include "ins_spi4.h"
+#include "ins_twi4.h"
+#include "ins_flexcom1.h"
+#include "ins_usart1.h"
+#include "ins_spi1.h"
+#include "ins_twi1.h"
+#include "ins_flexcom2.h"
+#include "ins_usart2.h"
+#include "ins_spi2.h"
+#include "ins_twi2.h"
+#include "ins_mem2mem.h"
+#include "ins_pdmic0.h"
+#include "ins_pdmic1.h"
+#include "ins_adc.h"
+#include "ins_cmcc.h"
+#include "ins_flexcom6.h"
+#include "ins_usart6.h"
+#include "ins_spi6.h"
+#include "ins_twi6.h"
+#include "ins_udp.h"
+#include "ins_crccu.h"
+#include "ins_uhp.h"
+#include "ins_matrix.h"
+#include "ins_pmc.h"
+#include "ins_chipid.h"
+#include "ins_efc.h"
+#include "ins_pioa.h"
+#include "ins_piob.h"
+#include "ins_rstc.h"
+#include "ins_supc.h"
+#include "ins_rtt.h"
+#include "ins_wdt.h"
+#include "ins_rtc.h"
+#include "ins_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* PERIPHERAL ID DEFINITIONS FOR SAMG55G19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55G19_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_FLEXCOM0 ( 8) /**< \brief FLEXCOM0 */
+#define ID_FLEXCOM1 ( 9) /**< \brief FLEXCOM1 */
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PDMIC0 (13) /**< \brief PDM 0 (PDMIC0) */
+#define ID_FLEXCOM2 (14) /**< \brief FLEXCOM2 */
+#define ID_MEM2MEM (15) /**< \brief MEM2MEM (MEM2MEM) */
+#define ID_I2SC0 (16) /**< \brief I2SC0 (I2SC0) */
+#define ID_I2SC1 (17) /**< \brief I2SC1 (I2SC1) */
+#define ID_PDMIC1 (18) /**< \brief PDM 1 (PDMIC1) */
+#define ID_FLEXCOM3 (19) /**< \brief FLEXCOM3 */
+#define ID_FLEXCOM4 (20) /**< \brief FLEXCOM4 */
+#define ID_FLEXCOM5 (21) /**< \brief FLEXCOM5 */
+#define ID_FLEXCOM6 (22) /**< \brief FLEXCOM6 */
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_ARM (30) /**< \brief FPU (ARM) */
+#define ID_UHP (47) /**< \brief USB OHCI (UHP) */
+#define ID_UDP (48) /**< \brief USB Device FS (UDP) */
+#define ID_CRCCU (49) /**< \brief CRCCU (CRCCU) */
+
+#define ID_PERIPH_COUNT (50) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/* BASE ADDRESS DEFINITIONS FOR SAMG55G19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55G19_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define I2SC0 (0x40000000U) /**< \brief (I2SC0 ) Base Address */
+#define PDC_I2SC0 (0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */
+#define I2SC1 (0x40004000U) /**< \brief (I2SC1 ) Base Address */
+#define PDC_I2SC1 (0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */
+#define FLEXCOM5 (0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */
+#define USART5 (0x40008200U) /**< \brief (USART5 ) Base Address */
+#define PDC_USART5 (0x40008300U) /**< \brief (PDC_USART5 ) Base Address */
+#define SPI5 (0x40008400U) /**< \brief (SPI5 ) Base Address */
+#define PDC_SPI5 (0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */
+#define TWI5 (0x40008600U) /**< \brief (TWI5 ) Base Address */
+#define PDC_TWI5 (0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */
+#define FLEXCOM0 (0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */
+#define USART0 (0x4000C200U) /**< \brief (USART0 ) Base Address */
+#define PDC_USART0 (0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */
+#define SPI0 (0x4000C400U) /**< \brief (SPI0 ) Base Address */
+#define PDC_SPI0 (0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */
+#define TWI0 (0x4000C600U) /**< \brief (TWI0 ) Base Address */
+#define PDC_TWI0 (0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */
+#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */
+#define PDC_TC0 (0x40010100U) /**< \brief (PDC_TC0 ) Base Address */
+#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */
+#define FLEXCOM3 (0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */
+#define USART3 (0x40018200U) /**< \brief (USART3 ) Base Address */
+#define PDC_USART3 (0x40018300U) /**< \brief (PDC_USART3 ) Base Address */
+#define SPI3 (0x40018400U) /**< \brief (SPI3 ) Base Address */
+#define PDC_SPI3 (0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */
+#define TWI3 (0x40018600U) /**< \brief (TWI3 ) Base Address */
+#define PDC_TWI3 (0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */
+#define FLEXCOM4 (0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */
+#define USART4 (0x4001C200U) /**< \brief (USART4 ) Base Address */
+#define PDC_USART4 (0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */
+#define SPI4 (0x4001C400U) /**< \brief (SPI4 ) Base Address */
+#define PDC_SPI4 (0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */
+#define TWI4 (0x4001C600U) /**< \brief (TWI4 ) Base Address */
+#define PDC_TWI4 (0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */
+#define FLEXCOM1 (0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */
+#define USART1 (0x40020200U) /**< \brief (USART1 ) Base Address */
+#define PDC_USART1 (0x40020300U) /**< \brief (PDC_USART1 ) Base Address */
+#define SPI1 (0x40020400U) /**< \brief (SPI1 ) Base Address */
+#define PDC_SPI1 (0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */
+#define TWI1 (0x40020600U) /**< \brief (TWI1 ) Base Address */
+#define PDC_TWI1 (0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */
+#define FLEXCOM2 (0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */
+#define USART2 (0x40024200U) /**< \brief (USART2 ) Base Address */
+#define PDC_USART2 (0x40024300U) /**< \brief (PDC_USART2 ) Base Address */
+#define SPI2 (0x40024400U) /**< \brief (SPI2 ) Base Address */
+#define PDC_SPI2 (0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */
+#define TWI2 (0x40024600U) /**< \brief (TWI2 ) Base Address */
+#define PDC_TWI2 (0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */
+#define MEM2MEM (0x40028000U) /**< \brief (MEM2MEM ) Base Address */
+#define PDC_MEM2MEM (0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */
+#define PDMIC0 (0x4002C000U) /**< \brief (PDMIC0 ) Base Address */
+#define PDC_PDMIC0 (0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */
+#define PDMIC1 (0x40030000U) /**< \brief (PDMIC1 ) Base Address */
+#define PDC_PDMIC1 (0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */
+#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */
+#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */
+#define CMCC (0x4003C000U) /**< \brief (CMCC ) Base Address */
+#define FLEXCOM6 (0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */
+#define USART6 (0x40040200U) /**< \brief (USART6 ) Base Address */
+#define PDC_USART6 (0x40040300U) /**< \brief (PDC_USART6 ) Base Address */
+#define SPI6 (0x40040400U) /**< \brief (SPI6 ) Base Address */
+#define PDC_SPI6 (0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */
+#define TWI6 (0x40040600U) /**< \brief (TWI6 ) Base Address */
+#define PDC_TWI6 (0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */
+#define UDP (0x40044000U) /**< \brief (UDP ) Base Address */
+#define CRCCU (0x40048000U) /**< \brief (CRCCU ) Base Address */
+#define UHP (0x20400000U) /**< \brief (UHP ) Base Address */
+#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */
+#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */
+#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */
+#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
+#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */
+#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */
+#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */
+#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */
+#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */
+#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */
+#else
+#define I2SC0 ((I2sc *)0x40000000U) /**< \brief (I2SC0 ) Base Address */
+#define PDC_I2SC0 ((Pdc *)0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */
+#define I2SC1 ((I2sc *)0x40004000U) /**< \brief (I2SC1 ) Base Address */
+#define PDC_I2SC1 ((Pdc *)0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */
+#define FLEXCOM5 ((Flexcom *)0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */
+#define USART5 ((Usart *)0x40008200U) /**< \brief (USART5 ) Base Address */
+#define PDC_USART5 ((Pdc *)0x40008300U) /**< \brief (PDC_USART5 ) Base Address */
+#define SPI5 ((Spi *)0x40008400U) /**< \brief (SPI5 ) Base Address */
+#define PDC_SPI5 ((Pdc *)0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */
+#define TWI5 ((Twi *)0x40008600U) /**< \brief (TWI5 ) Base Address */
+#define PDC_TWI5 ((Pdc *)0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */
+#define FLEXCOM0 ((Flexcom *)0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */
+#define USART0 ((Usart *)0x4000C200U) /**< \brief (USART0 ) Base Address */
+#define PDC_USART0 ((Pdc *)0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */
+#define SPI0 ((Spi *)0x4000C400U) /**< \brief (SPI0 ) Base Address */
+#define PDC_SPI0 ((Pdc *)0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */
+#define TWI0 ((Twi *)0x4000C600U) /**< \brief (TWI0 ) Base Address */
+#define PDC_TWI0 ((Pdc *)0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */
+#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */
+#define PDC_TC0 ((Pdc *)0x40010100U) /**< \brief (PDC_TC0 ) Base Address */
+#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */
+#define FLEXCOM3 ((Flexcom *)0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */
+#define USART3 ((Usart *)0x40018200U) /**< \brief (USART3 ) Base Address */
+#define PDC_USART3 ((Pdc *)0x40018300U) /**< \brief (PDC_USART3 ) Base Address */
+#define SPI3 ((Spi *)0x40018400U) /**< \brief (SPI3 ) Base Address */
+#define PDC_SPI3 ((Pdc *)0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */
+#define TWI3 ((Twi *)0x40018600U) /**< \brief (TWI3 ) Base Address */
+#define PDC_TWI3 ((Pdc *)0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */
+#define FLEXCOM4 ((Flexcom *)0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */
+#define USART4 ((Usart *)0x4001C200U) /**< \brief (USART4 ) Base Address */
+#define PDC_USART4 ((Pdc *)0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */
+#define SPI4 ((Spi *)0x4001C400U) /**< \brief (SPI4 ) Base Address */
+#define PDC_SPI4 ((Pdc *)0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */
+#define TWI4 ((Twi *)0x4001C600U) /**< \brief (TWI4 ) Base Address */
+#define PDC_TWI4 ((Pdc *)0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */
+#define FLEXCOM1 ((Flexcom *)0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */
+#define USART1 ((Usart *)0x40020200U) /**< \brief (USART1 ) Base Address */
+#define PDC_USART1 ((Pdc *)0x40020300U) /**< \brief (PDC_USART1 ) Base Address */
+#define SPI1 ((Spi *)0x40020400U) /**< \brief (SPI1 ) Base Address */
+#define PDC_SPI1 ((Pdc *)0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */
+#define TWI1 ((Twi *)0x40020600U) /**< \brief (TWI1 ) Base Address */
+#define PDC_TWI1 ((Pdc *)0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */
+#define FLEXCOM2 ((Flexcom *)0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */
+#define USART2 ((Usart *)0x40024200U) /**< \brief (USART2 ) Base Address */
+#define PDC_USART2 ((Pdc *)0x40024300U) /**< \brief (PDC_USART2 ) Base Address */
+#define SPI2 ((Spi *)0x40024400U) /**< \brief (SPI2 ) Base Address */
+#define PDC_SPI2 ((Pdc *)0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */
+#define TWI2 ((Twi *)0x40024600U) /**< \brief (TWI2 ) Base Address */
+#define PDC_TWI2 ((Pdc *)0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */
+#define MEM2MEM ((Mem2mem *)0x40028000U) /**< \brief (MEM2MEM ) Base Address */
+#define PDC_MEM2MEM ((Pdc *)0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */
+#define PDMIC0 ((Pdmic *)0x4002C000U) /**< \brief (PDMIC0 ) Base Address */
+#define PDC_PDMIC0 ((Pdc *)0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */
+#define PDMIC1 ((Pdmic *)0x40030000U) /**< \brief (PDMIC1 ) Base Address */
+#define PDC_PDMIC1 ((Pdc *)0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */
+#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */
+#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */
+#define CMCC ((Cmcc *)0x4003C000U) /**< \brief (CMCC ) Base Address */
+#define FLEXCOM6 ((Flexcom *)0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */
+#define USART6 ((Usart *)0x40040200U) /**< \brief (USART6 ) Base Address */
+#define PDC_USART6 ((Pdc *)0x40040300U) /**< \brief (PDC_USART6 ) Base Address */
+#define SPI6 ((Spi *)0x40040400U) /**< \brief (SPI6 ) Base Address */
+#define PDC_SPI6 ((Pdc *)0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */
+#define TWI6 ((Twi *)0x40040600U) /**< \brief (TWI6 ) Base Address */
+#define PDC_TWI6 ((Pdc *)0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */
+#define UDP ((Udp *)0x40044000U) /**< \brief (UDP ) Base Address */
+#define CRCCU ((Crccu *)0x40048000U) /**< \brief (CRCCU ) Base Address */
+#define UHP ((Uhp *)0x20400000U) /**< \brief (UHP ) Base Address */
+#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */
+#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */
+#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */
+#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
+#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */
+#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */
+#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */
+#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */
+#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */
+#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/* PIO DEFINITIONS FOR SAMG55G19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55G19_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio_samg55g19.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* MEMORY MAPPING DEFINITIONS FOR SAMG55G19 */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE (0x80000u)
+#define IFLASH_PAGE_SIZE (512u)
+#define IFLASH_LOCK_REGION_SIZE (8192u)
+#define IFLASH_NB_OF_PAGES (1024u)
+#define IFLASH_NB_OF_LOCK_BITS (64u)
+#define IRAM_SIZE (0x28000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/* MISCELLANEOUS DEFINITIONS FOR SAMG55G19 */
+/* ************************************************************************** */
+
+#define CHIP_JTAGID (0x05B3E03FUL)
+#define CHIP_CIDR (0x24470AE0UL)
+#define CHIP_EXID (0x0UL)
+#define NB_CH_ADC (8UL)
+
+/* ************************************************************************** */
+/* ELECTRICAL DEFINITIONS FOR SAMG55G19 */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
+#define CHIP_FREQ_SLCK_RC (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_16MHZ (16000000UL)
+#define CHIP_FREQ_MAINCK_RC_24MHZ (24000000UL)
+#define CHIP_FREQ_CPU_MAX (120000000UL)
+#define CHIP_FREQ_XTAL_32K (32768UL)
+
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE (5U)
+
+/* Embedded Flash Read Wait State (VDDIO set at 1.62V, Max value) */
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
+#define CHIP_FREQ_FWS_5 (120000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAMG55G19_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55j18.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,747 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55J18_
+#define _SAMG55J18_
+
+/** \addtogroup SAMG55J18_definitions SAMG55J18 definitions
+ This file defines all structures and symbols for SAMG55J18:
+ - registers and bitfields
+ - peripheral base address
+ - peripheral ID
+ - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#endif
+
+/* ************************************************************************** */
+/* CMSIS DEFINITIONS FOR SAMG55J18 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55J18_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn {
+ /****** Cortex-M4 Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
+ /****** SAMG55J18 specific Interrupt Numbers *********************************/
+
+ SUPC_IRQn = 0, /**< 0 SAMG55J18 Supply Controller (SUPC) */
+ RSTC_IRQn = 1, /**< 1 SAMG55J18 Reset Controller (RSTC) */
+ RTC_IRQn = 2, /**< 2 SAMG55J18 Real Time Clock (RTC) */
+ RTT_IRQn = 3, /**< 3 SAMG55J18 Real Time Timer (RTT) */
+ WDT_IRQn = 4, /**< 4 SAMG55J18 Watchdog Timer (WDT) */
+ PMC_IRQn = 5, /**< 5 SAMG55J18 Power Management Controller (PMC) */
+ EFC_IRQn = 6, /**< 6 SAMG55J18 Enhanced Flash Controller (EFC) */
+ USART7_IRQn = 7, /**< 7 SAMG55J18 FLEXCOM 7 (USART7) */
+ SPI7_IRQn = 7, /**< 7 SAMG55J18 FLEXCOM 7 (SPI7) */
+ TWI7_IRQn = 7, /**< 7 SAMG55J18 FLEXCOM 7 (TWI7) */
+ USART0_IRQn = 8, /**< 8 SAMG55J18 FLEXCOM 0 (USART0) */
+ SPI0_IRQn = 8, /**< 8 SAMG55J18 FLEXCOM 0 (SPI0) */
+ TWI0_IRQn = 8, /**< 8 SAMG55J18 FLEXCOM 0 (TWI0) */
+ USART1_IRQn = 9, /**< 9 SAMG55J18 FLEXCOM 1 (USART1) */
+ SPI1_IRQn = 9, /**< 8 SAMG55J18 FLEXCOM 1 (SPI1) */
+ TWI1_IRQn = 9, /**< 8 SAMG55J18 FLEXCOM 1 (TWI1) */
+ PIOA_IRQn = 11, /**< 11 SAMG55J18 Parallel I/O Controller A (PIOA) */
+ PIOB_IRQn = 12, /**< 12 SAMG55J18 Parallel I/O Controller B (PIOB) */
+ PDMIC0_IRQn = 13, /**< 13 SAMG55J18 PDM 0 (PDMIC0) */
+ USART2_IRQn = 14, /**< 14 SAMG55J18 FLEXCOM2 (USART2) */
+ SPI2_IRQn = 14, /**< 14 SAMG55J18 FLEXCOM 2 (SPI2) */
+ TWI2_IRQn = 14, /**< 14 SAMG55J18 FLEXCOM 2 (TWI2) */
+ MEM2MEM_IRQn = 15, /**< 15 SAMG55J18 MEM2MEM (MEM2MEM) */
+ I2SC0_IRQn = 16, /**< 16 SAMG55J18 I2SC0 (I2SC0) */
+ I2SC1_IRQn = 17, /**< 17 SAMG55J18 I2SC1 (I2SC1) */
+ PDMIC1_IRQn = 18, /**< 18 SAMG55J18 PDM 1 (PDMIC1) */
+ USART3__IRQn = 19, /**< 19 SAMG55J18 FLEXCOM3 (USART3) */
+ SPI3_IRQn = 19, /**< 19 SAMG55J18 FLEXCOM 3 (SPI3) */
+ TWI3_IRQn = 19, /**< 19 SAMG55J18 FLEXCOM 3 (TWI3) */
+ USART4_IRQn = 20, /**< 20 SAMG55J18 FLEXCOM4 (USART4) */
+ SPI4_IRQn = 20, /**< 8 SAMG55J18 FLEXCOM 4 (SPI4) */
+ TWI4_IRQn = 20, /**< 8 SAMG55J18 FLEXCOM 4 (TWI4) */
+ USART5_IRQn = 21, /**< 21 SAMG55J18 FLEXCOM5 (USART5) */
+ SPI5_IRQn = 21, /**< 8 SAMG55J18 FLEXCOM 5 (SPI5) */
+ TWI5_IRQn = 21, /**< 8 SAMG55J18 FLEXCOM 5 (TWI5) */
+ USART6_IRQn = 22, /**< 22 SAMG55J18 FLEXCOM6 (USART6) */
+ SPI6_IRQn = 22, /**< 22 SAMG55J18 FLEXCOM 6 (SPI6) */
+ TWI6_IRQn = 22, /**< 22 SAMG55J18 FLEXCOM 6 (TWI6) */
+ TC0_IRQn = 23, /**< 23 SAMG55J18 Timer/Counter 0 (TC0) */
+ TC1_IRQn = 24, /**< 24 SAMG55J18 Timer/Counter 1 (TC1) */
+ TC2_IRQn = 25, /**< 25 SAMG55J18 Timer/Counter 2 (TC2) */
+ TC3_IRQn = 26, /**< 26 SAMG55J18 Timer/Counter 3 (TC3) */
+ TC4_IRQn = 27, /**< 27 SAMG55J18 Timer/Counter 4 (TC4) */
+ TC5_IRQn = 28, /**< 28 SAMG55J18 Timer/Counter 5 (TC5) */
+ ADC_IRQn = 29, /**< 29 SAMG55J18 Analog To Digital Converter (ADC) */
+ ARM_IRQn = 30, /**< 30 SAMG55J18 FPU (ARM) */
+ WKUP0_IRQn = 31, /**< 31 SAMG55J18 External interrupt 0 (WKUP0) */
+ WKUP1_IRQn = 32, /**< 32 SAMG55J18 External interrupt 1 (WKUP1) */
+ WKUP2_IRQn = 33, /**< 33 SAMG55J18 External interrupt 2 (WKUP2) */
+ WKUP3_IRQn = 34, /**< 34 SAMG55J18 External interrupt 3 (WKUP3) */
+ WKUP4_IRQn = 35, /**< 35 SAMG55J18 External interrupt 4 (WKUP4) */
+ WKUP5_IRQn = 36, /**< 36 SAMG55J18 External interrupt 5 (WKUP5) */
+ WKUP6_IRQn = 37, /**< 37 SAMG55J18 External interrupt 6 (WKUP6) */
+ WKUP7_IRQn = 38, /**< 38 SAMG55J18 External interrupt 7 (WKUP7) */
+ WKUP8_IRQn = 39, /**< 39 SAMG55J18 External interrupt 8 (WKUP8) */
+ WKUP9_IRQn = 40, /**< 40 SAMG55J18 External interrupt 9 (WKUP9) */
+ WKUP10_IRQn = 41, /**< 41 SAMG55J18 External interrupt 10 (WKUP10) */
+ WKUP11_IRQn = 42, /**< 42 SAMG55J18 External interrupt 11 (WKUP11) */
+ WKUP12_IRQn = 43, /**< 43 SAMG55J18 External interrupt 12 (WKUP12) */
+ WKUP13_IRQn = 44, /**< 44 SAMG55J18 External interrupt 13 (WKUP13) */
+ WKUP14_IRQn = 45, /**< 45 SAMG55J18 External interrupt 14 (WKUP14) */
+ WKUP15_IRQn = 46, /**< 46 SAMG55J18 External interrupt 15 (WKUP15) */
+ UHP_IRQn = 47, /**< 47 SAMG55J18 USB OHCI (UHP) */
+ UDP_IRQn = 48, /**< 48 SAMG55J18 USB Device FS (UDP) */
+
+ PERIPH_COUNT_IRQn = 49 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnMemManage_Handler;
+ void* pfnBusFault_Handler;
+ void* pfnUsageFault_Handler;
+ void* pfnReserved1_Handler;
+ void* pfnReserved2_Handler;
+ void* pfnReserved3_Handler;
+ void* pfnReserved4_Handler;
+ void* pfnSVC_Handler;
+ void* pfnDebugMon_Handler;
+ void* pfnReserved5_Handler;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnSUPC_Handler; /* 0 Supply Controller */
+ void* pfnRSTC_Handler; /* 1 Reset Controller */
+ void* pfnRTC_Handler; /* 2 Real Time Clock */
+ void* pfnRTT_Handler; /* 3 Real Time Timer */
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */
+ void* pfnPMC_Handler; /* 5 Power Management Controller */
+ void* pfnEFC_Handler; /* 6 Enhanced Flash Controller */
+ void* pfnUSART7_Handler; /* USART7 */
+ void* pfnSPI7_Handler; /* SPI7 */
+ void* pfnTWI7_Handler; /* TWI7 */
+ void* pfnUSART0_Handler; /* 8 FLEXCOM 0 */
+ void* pfnSPI0_Handler; /* 8 FLEXCOM 0 */
+ void* pfnTWI0_Handler; /* 8 FLEXCOM 0 */
+ void* pfnUSART1_Handler; /* 9 FLEXCOM 1 */
+ void* pfnSPI1_Handler; /* 9 FLEXCOM 1 */
+ void* pfnTWI1_Handler; /* 9 FLEXCOM 1 */
+ void* pvReserved10;
+ void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */
+ void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */
+ void* pfnPDMIC0_Handler; /* 13 PDM 0 */
+ void* pfnUSART2_Handler; /* 14 FLEXCOM 2 */
+ void* pfnSPI2_Handler; /* 14 FLEXCOM 2 */
+ void* pfnTWI2_Handler; /* 14 FLEXCOM 2 */
+ void* pfnMEM2MEM_Handler; /* 15 MEM2MEM */
+ void* pfnI2SC0_Handler; /* 16 I2SC0 */
+ void* pfnI2SC1_Handler; /* 17 I2SC1 */
+ void* pfnPDMIC1_Handler; /* 18 PDM 1 */
+ void* pfnUSART3_Handler; /* 19 FLEXCOM 3 */
+ void* pfnSPI3_Handler; /* 19 FLEXCOM 3 */
+ void* pfnTWI3_Handler; /* 19 FLEXCOM 3 */
+ void* pfnUSART4_Handler; /* 20 FLEXCOM 4 */
+ void* pfnSPI4_Handler; /* 20 FLEXCOM 4 */
+ void* pfnTWI4_Handler; /* 20 FLEXCOM 4 */
+ void* pfnUSART5_Handler; /* 21 FLEXCOM 5 */
+ void* pfnSPI5_Handler; /* 21 FLEXCOM 5 */
+ void* pfnTWI5_Handler; /* 21 FLEXCOM 5 */
+ void* pfnUSART6_Handler; /* 22 FLEXCOM 6 */
+ void* pfnSPI6_Handler; /* 22 FLEXCOM 6 */
+ void* pfnTWI6_Handler; /* 22 FLEXCOM 6 */
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
+ void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
+ void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
+ void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
+ void* pfnADC_Handler; /* 29 Analog To Digital Converter */
+ void* pfnARM_Handler; /* 30 FPU */
+ void* pvReserved31;
+ void* pvReserved32;
+ void* pvReserved33;
+ void* pvReserved34;
+ void* pvReserved35;
+ void* pvReserved36;
+ void* pvReserved37;
+ void* pvReserved38;
+ void* pvReserved39;
+ void* pvReserved40;
+ void* pvReserved41;
+ void* pvReserved42;
+ void* pvReserved43;
+ void* pvReserved44;
+ void* pvReserved45;
+ void* pvReserved46;
+ void* pfnUHP_Handler; /* 47 USB OHCI */
+ void* pfnUDP_Handler; /* 48 USB Device FS */
+ void* pvReserved49; /* */
+ void* pvReserved50; /* */
+ void* pvReserved51; /* */
+ void* pvReserved52; /* */
+ void* pvReserved53; /* */
+ void* pvReserved54; /* */
+ void* pvReserved55; /* */
+ void* pvReserved56; /* */
+ void* pvReserved57; /* */
+ void* pvReserved58; /* */
+ void* pvReserved59; /* */
+ void* pvReserved60; /* */
+ void* pvReserved61; /* */
+ void* pvReserved62; /* */
+ void* pvReserved63; /* UHP */
+ void* pvReserved64; /* UDP */
+ void* pvReserved65; /* CRCCU */
+} DeviceVectors;
+
+/* Cortex-M4 core handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void MemManage_Handler ( void );
+void BusFault_Handler ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler ( void );
+void DebugMon_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void ADC_Handler ( void );
+void ARM_Handler ( void );
+void EFC_Handler ( void );
+void I2SC0_Handler ( void );
+void I2SC1_Handler ( void );
+void MEM2MEM_Handler ( void );
+void PDMIC0_Handler ( void );
+void PDMIC1_Handler ( void );
+void PIOA_Handler ( void );
+void PIOB_Handler ( void );
+void PMC_Handler ( void );
+void RSTC_Handler ( void );
+void RTC_Handler ( void );
+void RTT_Handler ( void );
+void SPI0_Handler ( void );
+void SPI1_Handler ( void );
+void SPI2_Handler ( void );
+void SPI3_Handler ( void );
+void SPI4_Handler ( void );
+void SPI5_Handler ( void );
+void SPI6_Handler ( void );
+void SPI7_Handler ( void );
+void SUPC_Handler ( void );
+void TC0_Handler ( void );
+void TC1_Handler ( void );
+void TC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TWI0_Handler ( void );
+void TWI1_Handler ( void );
+void TWI2_Handler ( void );
+void TWI3_Handler ( void );
+void TWI4_Handler ( void );
+void TWI5_Handler ( void );
+void TWI6_Handler ( void );
+void TWI7_Handler ( void );
+void UDP_Handler ( void );
+void UHP_Handler ( void );
+void USART0_Handler ( void );
+void USART1_Handler ( void );
+void USART2_Handler ( void );
+void USART3_Handler ( void );
+void USART4_Handler ( void );
+void USART5_Handler ( void );
+void USART6_Handler ( void );
+void USART7_Handler ( void );
+void WDT_Handler ( void );
+
+/**
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define __CM4_REV 0x0001 /**< SAMG55J18 core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT 1 /**< SAMG55J18 does provide a MPU */
+#define __FPU_PRESENT 1 /**< SAMG55J18 does provide a FPU */
+#define __NVIC_PRIO_BITS 4 /**< SAMG55J18 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include <core_cm4.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samg55.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMG55J18 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55J18_api Peripheral Software API */
+/*@{*/
+
+#include "comp_adc.h"
+#include "comp_chipid.h"
+#include "comp_cmcc.h"
+#include "comp_crccu.h"
+#include "comp_efc.h"
+#include "comp_flexcom.h"
+#include "comp_gpbr.h"
+#include "comp_i2sc.h"
+#include "comp_matrix.h"
+#include "comp_mem2mem.h"
+#include "comp_pdc.h"
+#include "comp_pdmic.h"
+#include "comp_pio.h"
+#include "comp_pmc.h"
+#include "comp_rstc.h"
+#include "comp_rtc.h"
+#include "comp_rtt.h"
+#include "comp_spi.h"
+#include "comp_supc.h"
+#include "comp_tc.h"
+#include "comp_twi.h"
+#include "comp_twihs.h"
+#include "comp_udp.h"
+#include "comp_usart.h"
+#include "comp_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* REGISTER ACCESS DEFINITIONS FOR SAMG55J18 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55J18_reg Registers Access Definitions */
+/*@{*/
+
+#include "ins_i2sc0.h"
+#include "ins_i2sc1.h"
+#include "ins_flexcom5.h"
+#include "ins_usart5.h"
+#include "ins_spi5.h"
+#include "ins_twi5.h"
+#include "ins_flexcom0.h"
+#include "ins_usart0.h"
+#include "ins_spi0.h"
+#include "ins_twi0.h"
+#include "ins_tc0.h"
+#include "ins_tc1.h"
+#include "ins_flexcom3.h"
+#include "ins_usart3.h"
+#include "ins_spi3.h"
+#include "ins_twi3.h"
+#include "ins_flexcom4.h"
+#include "ins_usart4.h"
+#include "ins_spi4.h"
+#include "ins_twi4.h"
+#include "ins_flexcom1.h"
+#include "ins_usart1.h"
+#include "ins_spi1.h"
+#include "ins_twi1.h"
+#include "ins_flexcom2.h"
+#include "ins_usart2.h"
+#include "ins_spi2.h"
+#include "ins_twi2.h"
+#include "ins_mem2mem.h"
+#include "ins_pdmic0.h"
+#include "ins_pdmic1.h"
+#include "ins_flexcom7.h"
+#include "ins_usart7.h"
+#include "ins_spi7.h"
+#include "ins_twi7.h"
+#include "ins_adc.h"
+#include "ins_cmcc.h"
+#include "ins_flexcom6.h"
+#include "ins_usart6.h"
+#include "ins_spi6.h"
+#include "ins_twi6.h"
+#include "ins_udp.h"
+#include "ins_crccu.h"
+#include "ins_uhp.h"
+#include "ins_matrix.h"
+#include "ins_pmc.h"
+#include "ins_chipid.h"
+#include "ins_efc.h"
+#include "ins_pioa.h"
+#include "ins_piob.h"
+#include "ins_rstc.h"
+#include "ins_supc.h"
+#include "ins_rtt.h"
+#include "ins_wdt.h"
+#include "ins_rtc.h"
+#include "ins_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* PERIPHERAL ID DEFINITIONS FOR SAMG55J18 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55J18_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_USART7 ( 7) /**< \brief FLEXCOM 7 (USART7) */
+#define ID_SPI7 ( 7) /**< \brief FLEXCOM 7 (SPI7) */
+#define ID_TWI7 ( 7) /**< \brief FLEXCOM 7 (TWI7) */
+#define ID_USART0 ( 8) /**< \brief FLEXCOM 0 (USART0) */
+#define ID_SPI0 ( 8) /**< \brief FLEXCOM 0 (SPI0) */
+#define ID_TWI0 ( 8) /**< \brief FLEXCOM 0 (TWI0) */
+#define ID_USART1 ( 9) /**< \brief FLEXCOM 1 (USART1) */
+#define ID_SPI1 ( 9) /**< \brief FLEXCOM 1 (SPI1) */
+#define ID_TWI1 ( 9) /**< \brief FLEXCOM 1 (TWI1) */
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PDMIC0 (13) /**< \brief PDM 0 (PDMIC0) */
+#define ID_USART2 (14) /**< \brief FLEXCOM2 (USART2) */
+#define ID_SPI2 (14) /**< \brief FLEXCOM2 (SPI2) */
+#define ID_TWI2 (14) /**< \brief FLEXCOM2 (TWI2) */
+#define ID_MEM2MEM (15) /**< \brief MEM2MEM (MEM2MEM) */
+#define ID_I2SC0 (16) /**< \brief I2SC0 (I2SC0) */
+#define ID_I2SC1 (17) /**< \brief I2SC1 (I2SC1) */
+#define ID_PDMIC1 (18) /**< \brief PDM 1 (PDMIC1) */
+#define ID_USART3 (19) /**< \brief FLEXCOM3 (USART3) */
+#define ID_SPI3 (19) /**< \brief FLEXCOM3 (SPI3) */
+#define ID_TWI3 (19) /**< \brief FLEXCOM3 (TWI3) */
+#define ID_USART4 (20) /**< \brief FLEXCOM4 (USART4) */
+#define ID_SPI4 (20) /**< \brief FLEXCOM4 (SPI4) */
+#define ID_TWI4 (20) /**< \brief FLEXCOM4 (TWI4) */
+#define ID_USART5 (21) /**< \brief FLEXCOM5 (USART5) */
+#define ID_SPI5 (21) /**< \brief FLEXCOM5 (SPI5) */
+#define ID_TWI5 (21) /**< \brief FLEXCOM5 (TWI5) */
+#define ID_USART6 (22) /**< \brief FLEXCOM6 (USART6) */
+#define ID_SPI6 (22) /**< \brief FLEXCOM6 (SPI6) */
+#define ID_TWI6 (22) /**< \brief FLEXCOM6 (TWI6) */
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_ARM (30) /**< \brief FPU (ARM) */
+#define ID_UHP (47) /**< \brief USB OHCI (UHP) */
+#define ID_UDP (48) /**< \brief USB Device FS (UDP) */
+#define ID_CRCCU (49) /**< \brief CRCCU (CRCCU) */
+
+#define ID_PERIPH_COUNT (50) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/* BASE ADDRESS DEFINITIONS FOR SAMG55J18 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55J18_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define I2SC0 (0x40000000U) /**< \brief (I2SC0 ) Base Address */
+#define PDC_I2SC0 (0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */
+#define I2SC1 (0x40004000U) /**< \brief (I2SC1 ) Base Address */
+#define PDC_I2SC1 (0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */
+#define FLEXCOM5 (0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */
+#define USART5 (0x40008200U) /**< \brief (USART5 ) Base Address */
+#define PDC_USART5 (0x40008300U) /**< \brief (PDC_USART5 ) Base Address */
+#define SPI5 (0x40008400U) /**< \brief (SPI5 ) Base Address */
+#define PDC_SPI5 (0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */
+#define TWI5 (0x40008600U) /**< \brief (TWI5 ) Base Address */
+#define PDC_TWI5 (0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */
+#define FLEXCOM0 (0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */
+#define USART0 (0x4000C200U) /**< \brief (USART0 ) Base Address */
+#define PDC_USART0 (0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */
+#define SPI0 (0x4000C400U) /**< \brief (SPI0 ) Base Address */
+#define PDC_SPI0 (0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */
+#define TWI0 (0x4000C600U) /**< \brief (TWI0 ) Base Address */
+#define PDC_TWI0 (0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */
+#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */
+#define PDC_TC0 (0x40010100U) /**< \brief (PDC_TC0 ) Base Address */
+#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */
+#define FLEXCOM3 (0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */
+#define USART3 (0x40018200U) /**< \brief (USART3 ) Base Address */
+#define PDC_USART3 (0x40018300U) /**< \brief (PDC_USART3 ) Base Address */
+#define SPI3 (0x40018400U) /**< \brief (SPI3 ) Base Address */
+#define PDC_SPI3 (0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */
+#define TWI3 (0x40018600U) /**< \brief (TWI3 ) Base Address */
+#define PDC_TWI3 (0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */
+#define FLEXCOM4 (0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */
+#define USART4 (0x4001C200U) /**< \brief (USART4 ) Base Address */
+#define PDC_USART4 (0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */
+#define SPI4 (0x4001C400U) /**< \brief (SPI4 ) Base Address */
+#define PDC_SPI4 (0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */
+#define TWI4 (0x4001C600U) /**< \brief (TWI4 ) Base Address */
+#define PDC_TWI4 (0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */
+#define FLEXCOM1 (0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */
+#define USART1 (0x40020200U) /**< \brief (USART1 ) Base Address */
+#define PDC_USART1 (0x40020300U) /**< \brief (PDC_USART1 ) Base Address */
+#define SPI1 (0x40020400U) /**< \brief (SPI1 ) Base Address */
+#define PDC_SPI1 (0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */
+#define TWI1 (0x40020600U) /**< \brief (TWI1 ) Base Address */
+#define PDC_TWI1 (0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */
+#define FLEXCOM2 (0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */
+#define USART2 (0x40024200U) /**< \brief (USART2 ) Base Address */
+#define PDC_USART2 (0x40024300U) /**< \brief (PDC_USART2 ) Base Address */
+#define SPI2 (0x40024400U) /**< \brief (SPI2 ) Base Address */
+#define PDC_SPI2 (0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */
+#define TWI2 (0x40024600U) /**< \brief (TWI2 ) Base Address */
+#define PDC_TWI2 (0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */
+#define MEM2MEM (0x40028000U) /**< \brief (MEM2MEM ) Base Address */
+#define PDC_MEM2MEM (0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */
+#define PDMIC0 (0x4002C000U) /**< \brief (PDMIC0 ) Base Address */
+#define PDC_PDMIC0 (0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */
+#define PDMIC1 (0x40030000U) /**< \brief (PDMIC1 ) Base Address */
+#define PDC_PDMIC1 (0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */
+#define FLEXCOM7 (0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */
+#define USART7 (0x40034200U) /**< \brief (USART7 ) Base Address */
+#define PDC_USART7 (0x40034300U) /**< \brief (PDC_USART7 ) Base Address */
+#define SPI7 (0x40034400U) /**< \brief (SPI7 ) Base Address */
+#define PDC_SPI7 (0x40034500U) /**< \brief (PDC_SPI7 ) Base Address */
+#define TWI7 (0x40034600U) /**< \brief (TWI7 ) Base Address */
+#define PDC_TWI7 (0x40034700U) /**< \brief (PDC_TWI7 ) Base Address */
+#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */
+#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */
+#define CMCC (0x4003C000U) /**< \brief (CMCC ) Base Address */
+#define FLEXCOM6 (0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */
+#define USART6 (0x40040200U) /**< \brief (USART6 ) Base Address */
+#define PDC_USART6 (0x40040300U) /**< \brief (PDC_USART6 ) Base Address */
+#define SPI6 (0x40040400U) /**< \brief (SPI6 ) Base Address */
+#define PDC_SPI6 (0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */
+#define TWI6 (0x40040600U) /**< \brief (TWI6 ) Base Address */
+#define PDC_TWI6 (0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */
+#define UDP (0x40044000U) /**< \brief (UDP ) Base Address */
+#define CRCCU (0x40048000U) /**< \brief (CRCCU ) Base Address */
+#define UHP (0x4004C000U) /**< \brief (UHP ) Base Address */
+#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */
+#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */
+#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */
+#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
+#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */
+#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */
+#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */
+#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */
+#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */
+#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */
+#else
+#define I2SC0 ((I2sc *)0x40000000U) /**< \brief (I2SC0 ) Base Address */
+#define PDC_I2SC0 ((Pdc *)0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */
+#define I2SC1 ((I2sc *)0x40004000U) /**< \brief (I2SC1 ) Base Address */
+#define PDC_I2SC1 ((Pdc *)0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */
+#define FLEXCOM5 ((Flexcom *)0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */
+#define USART5 ((Usart *)0x40008200U) /**< \brief (USART5 ) Base Address */
+#define PDC_USART5 ((Pdc *)0x40008300U) /**< \brief (PDC_USART5 ) Base Address */
+#define SPI5 ((Spi *)0x40008400U) /**< \brief (SPI5 ) Base Address */
+#define PDC_SPI5 ((Pdc *)0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */
+#define TWI5 ((Twi *)0x40008600U) /**< \brief (TWI5 ) Base Address */
+#define PDC_TWI5 ((Pdc *)0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */
+#define FLEXCOM0 ((Flexcom *)0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */
+#define USART0 ((Usart *)0x4000C200U) /**< \brief (USART0 ) Base Address */
+#define PDC_USART0 ((Pdc *)0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */
+#define SPI0 ((Spi *)0x4000C400U) /**< \brief (SPI0 ) Base Address */
+#define PDC_SPI0 ((Pdc *)0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */
+#define TWI0 ((Twi *)0x4000C600U) /**< \brief (TWI0 ) Base Address */
+#define PDC_TWI0 ((Pdc *)0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */
+#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */
+#define PDC_TC0 ((Pdc *)0x40010100U) /**< \brief (PDC_TC0 ) Base Address */
+#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */
+#define FLEXCOM3 ((Flexcom *)0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */
+#define USART3 ((Usart *)0x40018200U) /**< \brief (USART3 ) Base Address */
+#define PDC_USART3 ((Pdc *)0x40018300U) /**< \brief (PDC_USART3 ) Base Address */
+#define SPI3 ((Spi *)0x40018400U) /**< \brief (SPI3 ) Base Address */
+#define PDC_SPI3 ((Pdc *)0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */
+#define TWI3 ((Twihs *)0x40018600U) /**< \brief (TWI3 ) Base Address */
+#define PDC_TWI3 ((Pdc *)0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */
+#define FLEXCOM4 ((Flexcom *)0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */
+#define USART4 ((Usart *)0x4001C200U) /**< \brief (USART4 ) Base Address */
+#define PDC_USART4 ((Pdc *)0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */
+#define SPI4 ((Spi *)0x4001C400U) /**< \brief (SPI4 ) Base Address */
+#define PDC_SPI4 ((Pdc *)0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */
+#define TWI4 ((Twi *)0x4001C600U) /**< \brief (TWI4 ) Base Address */
+#define PDC_TWI4 ((Pdc *)0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */
+#define FLEXCOM1 ((Flexcom *)0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */
+#define USART1 ((Usart *)0x40020200U) /**< \brief (USART1 ) Base Address */
+#define PDC_USART1 ((Pdc *)0x40020300U) /**< \brief (PDC_USART1 ) Base Address */
+#define SPI1 ((Spi *)0x40020400U) /**< \brief (SPI1 ) Base Address */
+#define PDC_SPI1 ((Pdc *)0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */
+#define TWI1 ((Twi *)0x40020600U) /**< \brief (TWI1 ) Base Address */
+#define PDC_TWI1 ((Pdc *)0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */
+#define FLEXCOM2 ((Flexcom *)0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */
+#define USART2 ((Usart *)0x40024200U) /**< \brief (USART2 ) Base Address */
+#define PDC_USART2 ((Pdc *)0x40024300U) /**< \brief (PDC_USART2 ) Base Address */
+#define SPI2 ((Spi *)0x40024400U) /**< \brief (SPI2 ) Base Address */
+#define PDC_SPI2 ((Pdc *)0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */
+#define TWI2 ((Twi *)0x40024600U) /**< \brief (TWI2 ) Base Address */
+#define PDC_TWI2 ((Pdc *)0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */
+#define MEM2MEM ((Mem2mem *)0x40028000U) /**< \brief (MEM2MEM ) Base Address */
+#define PDC_MEM2MEM ((Pdc *)0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */
+#define PDMIC0 ((Pdmic *)0x4002C000U) /**< \brief (PDMIC0 ) Base Address */
+#define PDC_PDMIC0 ((Pdc *)0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */
+#define PDMIC1 ((Pdmic *)0x40030000U) /**< \brief (PDMIC1 ) Base Address */
+#define PDC_PDMIC1 ((Pdc *)0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */
+#define FLEXCOM7 ((Flexcom *)0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */
+#define USART7 ((Usart *)0x40034200U) /**< \brief (USART7 ) Base Address */
+#define PDC_USART7 ((Pdc *)0x40034300U) /**< \brief (PDC_USART7 ) Base Address */
+#define SPI7 ((Spi *)0x40034400U) /**< \brief (SPI7 ) Base Address */
+#define PDC_SPI7 ((Pdc *)0x40034500U) /**< \brief (PDC_SPI7 ) Base Address */
+#define TWI7 ((Twi *)0x40034600U) /**< \brief (TWI7 ) Base Address */
+#define PDC_TWI7 ((Pdc *)0x40034700U) /**< \brief (PDC_TWI7 ) Base Address */
+#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */
+#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */
+#define CMCC ((Cmcc *)0x4003C000U) /**< \brief (CMCC ) Base Address */
+#define FLEXCOM6 ((Flexcom *)0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */
+#define USART6 ((Usart *)0x40040200U) /**< \brief (USART6 ) Base Address */
+#define PDC_USART6 ((Pdc *)0x40040300U) /**< \brief (PDC_USART6 ) Base Address */
+#define SPI6 ((Spi *)0x40040400U) /**< \brief (SPI6 ) Base Address */
+#define PDC_SPI6 ((Pdc *)0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */
+#define TWI6 ((Twi *)0x40040600U) /**< \brief (TWI6 ) Base Address */
+#define PDC_TWI6 ((Pdc *)0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */
+#define UDP ((Udp *)0x40044000U) /**< \brief (UDP ) Base Address */
+#define CRCCU ((Crccu *)0x40048000U) /**< \brief (CRCCU ) Base Address */
+#define UHP ((Uhp *)0x4004C000U) /**< \brief (UHP ) Base Address */
+#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */
+#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */
+#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */
+#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
+#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */
+#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */
+#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */
+#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */
+#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */
+#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/* PIO DEFINITIONS FOR SAMG55J18 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55J18_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio_samg55j18.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* MEMORY MAPPING DEFINITIONS FOR SAMG55J18 */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE (0x40000u)
+#define IFLASH_PAGE_SIZE (512u)
+#define IFLASH_LOCK_REGION_SIZE (8192u)
+#define IFLASH_NB_OF_PAGES (512u)
+#define IFLASH_NB_OF_LOCK_BITS (32u)
+#define IRAM_SIZE (0x28000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/* MISCELLANEOUS DEFINITIONS FOR SAMG55J18 */
+/* ************************************************************************** */
+
+#define CHIP_JTAGID (0x05B3E03FUL)
+#define CHIP_CIDR (0x245709E0UL)
+#define CHIP_EXID (0x0UL)
+#define NB_CH_ADC (8UL)
+
+/* ************************************************************************** */
+/* ELECTRICAL DEFINITIONS FOR SAMG55J18 */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
+#define CHIP_FREQ_SLCK_RC (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_16MHZ (16000000UL)
+#define CHIP_FREQ_MAINCK_RC_24MHZ (24000000UL)
+#define CHIP_FREQ_CPU_MAX (120000000UL)
+#define CHIP_FREQ_XTAL_32K (32768UL)
+
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE (5U)
+
+/* Embedded Flash Read Wait State (VDDIO set at 1.62V, Max value) */
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
+#define CHIP_FREQ_FWS_5 (120000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAMG55J18_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55j19.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,683 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55J19_
+#define _SAMG55J19_
+
+/** \addtogroup SAMG55J19_definitions SAMG55J19 definitions
+ This file defines all structures and symbols for SAMG55J19:
+ - registers and bitfields
+ - peripheral base address
+ - peripheral ID
+ - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#endif
+
+/* ************************************************************************** */
+/* CMSIS DEFINITIONS FOR SAMG55J19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55J19_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn {
+ /****** Cortex-M4 Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
+ /****** SAMG55J19 specific Interrupt Numbers *********************************/
+
+ SUPC_IRQn = 0, /**< 0 SAMG55J19 Supply Controller (SUPC) */
+ RSTC_IRQn = 1, /**< 1 SAMG55J19 Reset Controller (RSTC) */
+ RTC_IRQn = 2, /**< 2 SAMG55J19 Real Time Clock (RTC) */
+ RTT_IRQn = 3, /**< 3 SAMG55J19 Real Time Timer (RTT) */
+ WDT_IRQn = 4, /**< 4 SAMG55J19 Watchdog Timer (WDT) */
+ PMC_IRQn = 5, /**< 5 SAMG55J19 Power Management Controller (PMC) */
+ EFC_IRQn = 6, /**< 6 SAMG55J19 Enhanced Flash Controller (EFC) */
+ FLEXCOM7_IRQn = 7, /**< 7 SAMG55J19 FLEXCOM 7 (FLEXCOM7) */
+ FLEXCOM0_IRQn = 8, /**< 8 SAMG55J19 FLEXCOM 0 (FLEXCOM0) */
+ FLEXCOM1_IRQn = 9, /**< 9 SAMG55J19 FLEXCOM 1 (FLEXCOM1) */
+ PIOA_IRQn = 11, /**< 11 SAMG55J19 Parallel I/O Controller A (PIOA) */
+ PIOB_IRQn = 12, /**< 12 SAMG55J19 Parallel I/O Controller B (PIOB) */
+ PDMIC0_IRQn = 13, /**< 13 SAMG55J19 PDM 0 (PDMIC0) */
+ FLEXCOM2_IRQn = 14, /**< 14 SAMG55J19 FLEXCOM2 (FLEXCOM2) */
+ MEM2MEM_IRQn = 15, /**< 15 SAMG55J19 MEM2MEM (MEM2MEM) */
+ I2SC0_IRQn = 16, /**< 16 SAMG55J19 I2SC0 (I2SC0) */
+ I2SC1_IRQn = 17, /**< 17 SAMG55J19 I2SC1 (I2SC1) */
+ PDMIC1_IRQn = 18, /**< 18 SAMG55J19 PDM 1 (PDMIC1) */
+ FLEXCOM3_IRQn = 19, /**< 19 SAMG55J19 FLEXCOM3 (FLEXCOM3) */
+ FLEXCOM4_IRQn = 20, /**< 20 SAMG55J19 FLEXCOM4 (FLEXCOM4) */
+ FLEXCOM5_IRQn = 21, /**< 21 SAMG55J19 FLEXCOM5 (FLEXCOM5) */
+ FLEXCOM6_IRQn = 22, /**< 22 SAMG55J19 FLEXCOM6 (FLEXCOM6) */
+ TC0_IRQn = 23, /**< 23 SAMG55J19 Timer/Counter 0 (TC0) */
+ TC1_IRQn = 24, /**< 24 SAMG55J19 Timer/Counter 1 (TC1) */
+ TC2_IRQn = 25, /**< 25 SAMG55J19 Timer/Counter 2 (TC2) */
+ TC3_IRQn = 26, /**< 26 SAMG55J19 Timer/Counter 3 (TC3) */
+ TC4_IRQn = 27, /**< 27 SAMG55J19 Timer/Counter 4 (TC4) */
+ TC5_IRQn = 28, /**< 28 SAMG55J19 Timer/Counter 5 (TC5) */
+ ADC_IRQn = 29, /**< 29 SAMG55J19 Analog To Digital Converter (ADC) */
+ ARM_IRQn = 30, /**< 30 SAMG55J19 FPU (ARM) */
+ WKUP0_IRQn = 31, /**< 31 SAMG55J19 External interrupt 0 (WKUP0) */
+ WKUP1_IRQn = 32, /**< 32 SAMG55J19 External interrupt 1 (WKUP1) */
+ WKUP2_IRQn = 33, /**< 33 SAMG55J19 External interrupt 2 (WKUP2) */
+ WKUP3_IRQn = 34, /**< 34 SAMG55J19 External interrupt 3 (WKUP3) */
+ WKUP4_IRQn = 35, /**< 35 SAMG55J19 External interrupt 4 (WKUP4) */
+ WKUP5_IRQn = 36, /**< 36 SAMG55J19 External interrupt 5 (WKUP5) */
+ WKUP6_IRQn = 37, /**< 37 SAMG55J19 External interrupt 6 (WKUP6) */
+ WKUP7_IRQn = 38, /**< 38 SAMG55J19 External interrupt 7 (WKUP7) */
+ WKUP8_IRQn = 39, /**< 39 SAMG55J19 External interrupt 8 (WKUP8) */
+ WKUP9_IRQn = 40, /**< 40 SAMG55J19 External interrupt 9 (WKUP9) */
+ WKUP10_IRQn = 41, /**< 41 SAMG55J19 External interrupt 10 (WKUP10) */
+ WKUP11_IRQn = 42, /**< 42 SAMG55J19 External interrupt 11 (WKUP11) */
+ WKUP12_IRQn = 43, /**< 43 SAMG55J19 External interrupt 12 (WKUP12) */
+ WKUP13_IRQn = 44, /**< 44 SAMG55J19 External interrupt 13 (WKUP13) */
+ WKUP14_IRQn = 45, /**< 45 SAMG55J19 External interrupt 14 (WKUP14) */
+ WKUP15_IRQn = 46, /**< 46 SAMG55J19 External interrupt 15 (WKUP15) */
+ UHP_IRQn = 47, /**< 47 SAMG55J19 USB OHCI (UHP) */
+ UDP_IRQn = 48, /**< 48 SAMG55J19 USB Device FS (UDP) */
+ CRCCU_IRQn = 49, /**< 49 SAMG55G19 CRCCU */
+ PERIPH_COUNT_IRQn = 50 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnMemManage_Handler;
+ void* pfnBusFault_Handler;
+ void* pfnUsageFault_Handler;
+ void* pfnReserved1_Handler;
+ void* pfnReserved2_Handler;
+ void* pfnReserved3_Handler;
+ void* pfnReserved4_Handler;
+ void* pfnSVC_Handler;
+ void* pfnDebugMon_Handler;
+ void* pfnReserved5_Handler;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnSUPC_Handler; /* 0 Supply Controller */
+ void* pfnRSTC_Handler; /* 1 Reset Controller */
+ void* pfnRTC_Handler; /* 2 Real Time Clock */
+ void* pfnRTT_Handler; /* 3 Real Time Timer */
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */
+ void* pfnPMC_Handler; /* 5 Power Management Controller */
+ void* pfnEFC_Handler; /* 6 Enhanced Flash Controller */
+ void* pfnFLEXCOM7_Handler; /* FLEXCOM7 */
+ void* pfnFLEXCOM0_Handler; /* 8 FLEXCOM 0 */
+ void* pfnFLEXCOM1_Handler; /* 9 FLEXCOM 1 */
+ void* pvReserved10;
+ void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */
+ void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */
+ void* pfnPDMIC0_Handler; /* 13 PDM 0 */
+ void* pfnFLEXCOM2_Handler; /* 14 FLEXCOM 2 */
+ void* pfnMEM2MEM_Handler; /* 15 MEM2MEM */
+ void* pfnI2SC0_Handler; /* 16 I2SC0 */
+ void* pfnI2SC1_Handler; /* 17 I2SC1 */
+ void* pfnPDMIC1_Handler; /* 18 PDM 1 */
+ void* pfnFLEXCOM3_Handler; /* 19 FLEXCOM 3 */
+ void* pfnFLEXCOM4_Handler; /* 20 FLEXCOM 4 */
+ void* pfnFLEXCOM5_Handler; /* 21 FLEXCOM 5 */
+ void* pfnFLEXCOM6_Handler; /* 22 FLEXCOM 6 */
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
+ void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
+ void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
+ void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
+ void* pfnADC_Handler; /* 29 Analog To Digital Converter */
+ void* pfnARM_Handler; /* 30 FPU */
+ void* pvReserved31;
+ void* pvReserved32;
+ void* pvReserved33;
+ void* pvReserved34;
+ void* pvReserved35;
+ void* pvReserved36;
+ void* pvReserved37;
+ void* pvReserved38;
+ void* pvReserved39;
+ void* pvReserved40;
+ void* pvReserved41;
+ void* pvReserved42;
+ void* pvReserved43;
+ void* pvReserved44;
+ void* pvReserved45;
+ void* pvReserved46;
+ void* pfnUHP_Handler; /* 47 USB OHCI */
+ void* pfnUDP_Handler; /* 48 USB Device FS */
+ void* pfnCRCCU_Handler; /*49 CRCCU Device */
+ void* pvReserved50; /* */
+ void* pvReserved51; /* */
+ void* pvReserved52; /* */
+ void* pvReserved53; /* */
+ void* pvReserved54; /* */
+ void* pvReserved55; /* */
+ void* pvReserved56; /* */
+ void* pvReserved57; /* */
+ void* pvReserved58; /* */
+ void* pvReserved59; /* */
+ void* pvReserved60; /* */
+ void* pvReserved61; /* */
+ void* pvReserved62; /* */
+ void* pvReserved63; /* UHP */
+ void* pvReserved64; /* UDP */
+ void* pvReserved65; /* CRCCU */
+} DeviceVectors;
+
+/* Cortex-M4 core handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void MemManage_Handler ( void );
+void BusFault_Handler ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler ( void );
+void DebugMon_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void ADC_Handler ( void );
+void ARM_Handler ( void );
+void CRCCU_Handler ( void );
+void EFC_Handler ( void );
+void I2SC0_Handler ( void );
+void I2SC1_Handler ( void );
+void MEM2MEM_Handler ( void );
+void PDMIC0_Handler ( void );
+void PDMIC1_Handler ( void );
+void PIOA_Handler ( void );
+void PIOB_Handler ( void );
+void PMC_Handler ( void );
+void RSTC_Handler ( void );
+void RTC_Handler ( void );
+void RTT_Handler ( void );
+void SUPC_Handler ( void );
+void TC0_Handler ( void );
+void TC1_Handler ( void );
+void TC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void UDP_Handler ( void );
+void UHP_Handler ( void );
+void FLEXCOM0_Handler ( void );
+void FLEXCOM1_Handler ( void );
+void FLEXCOM2_Handler ( void );
+void FLEXCOM3_Handler ( void );
+void FLEXCOM4_Handler ( void );
+void FLEXCOM5_Handler ( void );
+void FLEXCOM6_Handler ( void );
+void FLEXCOM7_Handler ( void );
+void WDT_Handler ( void );
+/**
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define __CM4_REV 0x0001 /**< SAMG55J19 core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT 1 /**< SAMG55J19 does provide a MPU */
+#define __FPU_PRESENT 1 /**< SAMG55J19 does provide a FPU */
+#define __NVIC_PRIO_BITS 4 /**< SAMG55J19 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include <core_cm4.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samg55.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMG55J19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55J19_api Peripheral Software API */
+/*@{*/
+
+#include "comp_adc.h"
+#include "comp_chipid.h"
+#include "comp_cmcc.h"
+#include "comp_crccu.h"
+#include "comp_efc.h"
+#include "comp_flexcom.h"
+#include "comp_gpbr.h"
+#include "comp_i2sc.h"
+#include "comp_matrix.h"
+#include "comp_mem2mem.h"
+#include "comp_pdc.h"
+#include "comp_pdmic.h"
+#include "comp_pio.h"
+#include "comp_pmc.h"
+#include "comp_rstc.h"
+#include "comp_rtc.h"
+#include "comp_rtt.h"
+#include "comp_spi.h"
+#include "comp_supc.h"
+#include "comp_tc.h"
+#include "comp_twi.h"
+#include "comp_udp.h"
+#include "comp_uhp.h"
+#include "comp_usart.h"
+#include "comp_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* REGISTER ACCESS DEFINITIONS FOR SAMG55J19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55J19_reg Registers Access Definitions */
+/*@{*/
+
+#include "ins_i2sc0.h"
+#include "ins_i2sc1.h"
+#include "ins_flexcom5.h"
+#include "ins_usart5.h"
+#include "ins_spi5.h"
+#include "ins_twi5.h"
+#include "ins_flexcom0.h"
+#include "ins_usart0.h"
+#include "ins_spi0.h"
+#include "ins_twi0.h"
+#include "ins_tc0.h"
+#include "ins_tc1.h"
+#include "ins_flexcom3.h"
+#include "ins_usart3.h"
+#include "ins_spi3.h"
+#include "ins_twi3.h"
+#include "ins_flexcom4.h"
+#include "ins_usart4.h"
+#include "ins_spi4.h"
+#include "ins_twi4.h"
+#include "ins_flexcom1.h"
+#include "ins_usart1.h"
+#include "ins_spi1.h"
+#include "ins_twi1.h"
+#include "ins_flexcom2.h"
+#include "ins_usart2.h"
+#include "ins_spi2.h"
+#include "ins_twi2.h"
+#include "ins_mem2mem.h"
+#include "ins_pdmic0.h"
+#include "ins_pdmic1.h"
+#include "ins_flexcom7.h"
+#include "ins_usart7.h"
+#include "ins_spi7.h"
+#include "ins_twi7.h"
+#include "ins_adc.h"
+#include "ins_cmcc.h"
+#include "ins_flexcom6.h"
+#include "ins_usart6.h"
+#include "ins_spi6.h"
+#include "ins_twi6.h"
+#include "ins_udp.h"
+#include "ins_crccu.h"
+#include "ins_uhp.h"
+#include "ins_matrix.h"
+#include "ins_pmc.h"
+#include "ins_chipid.h"
+#include "ins_efc.h"
+#include "ins_pioa.h"
+#include "ins_piob.h"
+#include "ins_rstc.h"
+#include "ins_supc.h"
+#include "ins_rtt.h"
+#include "ins_wdt.h"
+#include "ins_rtc.h"
+#include "ins_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* PERIPHERAL ID DEFINITIONS FOR SAMG55J19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55J19_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_FLEXCOM7 ( 7) /**< \brief FLEXCOM7 */
+#define ID_FLEXCOM0 ( 8) /**< \brief FLEXCOM0 */
+#define ID_FLEXCOM1 ( 9) /**< \brief FLEXCOM1 */
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PDMIC0 (13) /**< \brief PDM 0 (PDMIC0) */
+#define ID_FLEXCOM2 (14) /**< \brief FLEXCOM2 */
+#define ID_MEM2MEM (15) /**< \brief MEM2MEM (MEM2MEM) */
+#define ID_I2SC0 (16) /**< \brief I2SC0 (I2SC0) */
+#define ID_I2SC1 (17) /**< \brief I2SC1 (I2SC1) */
+#define ID_PDMIC1 (18) /**< \brief PDM 1 (PDMIC1) */
+#define ID_FLEXCOM3 (19) /**< \brief FLEXCOM3 */
+#define ID_FLEXCOM4 (20) /**< \brief FLEXCOM4 */
+#define ID_FLEXCOM5 (21) /**< \brief FLEXCOM5 */
+#define ID_FLEXCOM6 (22) /**< \brief FLEXCOM6 */
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_ARM (30) /**< \brief FPU (ARM) */
+#define ID_UHP (47) /**< \brief USB OHCI (UHP) */
+#define ID_UDP (48) /**< \brief USB Device FS (UDP) */
+#define ID_CRCCU (49) /**< \brief CRCCU (CRCCU) */
+
+#define ID_PERIPH_COUNT (50) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/* BASE ADDRESS DEFINITIONS FOR SAMG55J19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55J19_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define I2SC0 (0x40000000U) /**< \brief (I2SC0 ) Base Address */
+#define PDC_I2SC0 (0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */
+#define I2SC1 (0x40004000U) /**< \brief (I2SC1 ) Base Address */
+#define PDC_I2SC1 (0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */
+#define FLEXCOM5 (0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */
+#define USART5 (0x40008200U) /**< \brief (USART5 ) Base Address */
+#define PDC_USART5 (0x40008300U) /**< \brief (PDC_USART5 ) Base Address */
+#define SPI5 (0x40008400U) /**< \brief (SPI5 ) Base Address */
+#define PDC_SPI5 (0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */
+#define TWI5 (0x40008600U) /**< \brief (TWI5 ) Base Address */
+#define PDC_TWI5 (0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */
+#define FLEXCOM0 (0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */
+#define USART0 (0x4000C200U) /**< \brief (USART0 ) Base Address */
+#define PDC_USART0 (0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */
+#define SPI0 (0x4000C400U) /**< \brief (SPI0 ) Base Address */
+#define PDC_SPI0 (0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */
+#define TWI0 (0x4000C600U) /**< \brief (TWI0 ) Base Address */
+#define PDC_TWI0 (0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */
+#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */
+#define PDC_TC0 (0x40010100U) /**< \brief (PDC_TC0 ) Base Address */
+#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */
+#define FLEXCOM3 (0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */
+#define USART3 (0x40018200U) /**< \brief (USART3 ) Base Address */
+#define PDC_USART3 (0x40018300U) /**< \brief (PDC_USART3 ) Base Address */
+#define SPI3 (0x40018400U) /**< \brief (SPI3 ) Base Address */
+#define PDC_SPI3 (0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */
+#define TWI3 (0x40018600U) /**< \brief (TWI3 ) Base Address */
+#define PDC_TWI3 (0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */
+#define FLEXCOM4 (0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */
+#define USART4 (0x4001C200U) /**< \brief (USART4 ) Base Address */
+#define PDC_USART4 (0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */
+#define SPI4 (0x4001C400U) /**< \brief (SPI4 ) Base Address */
+#define PDC_SPI4 (0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */
+#define TWI4 (0x4001C600U) /**< \brief (TWI4 ) Base Address */
+#define PDC_TWI4 (0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */
+#define FLEXCOM1 (0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */
+#define USART1 (0x40020200U) /**< \brief (USART1 ) Base Address */
+#define PDC_USART1 (0x40020300U) /**< \brief (PDC_USART1 ) Base Address */
+#define SPI1 (0x40020400U) /**< \brief (SPI1 ) Base Address */
+#define PDC_SPI1 (0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */
+#define TWI1 (0x40020600U) /**< \brief (TWI1 ) Base Address */
+#define PDC_TWI1 (0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */
+#define FLEXCOM2 (0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */
+#define USART2 (0x40024200U) /**< \brief (USART2 ) Base Address */
+#define PDC_USART2 (0x40024300U) /**< \brief (PDC_USART2 ) Base Address */
+#define SPI2 (0x40024400U) /**< \brief (SPI2 ) Base Address */
+#define PDC_SPI2 (0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */
+#define TWI2 (0x40024600U) /**< \brief (TWI2 ) Base Address */
+#define PDC_TWI2 (0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */
+#define MEM2MEM (0x40028000U) /**< \brief (MEM2MEM ) Base Address */
+#define PDC_MEM2MEM (0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */
+#define PDMIC0 (0x4002C000U) /**< \brief (PDMIC0 ) Base Address */
+#define PDC_PDMIC0 (0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */
+#define PDMIC1 (0x40030000U) /**< \brief (PDMIC1 ) Base Address */
+#define PDC_PDMIC1 (0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */
+#define FLEXCOM7 (0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */
+#define USART7 (0x40034200U) /**< \brief (USART7 ) Base Address */
+#define PDC_USART7 (0x40034300U) /**< \brief (PDC_USART7 ) Base Address */
+#define SPI7 (0x40034400U) /**< \brief (SPI7 ) Base Address */
+#define PDC_SPI7 (0x40034500U) /**< \brief (PDC_SPI7 ) Base Address */
+#define TWI7 (0x40034600U) /**< \brief (TWI7 ) Base Address */
+#define PDC_TWI7 (0x40034700U) /**< \brief (PDC_TWI7 ) Base Address */
+#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */
+#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */
+#define CMCC (0x4003C000U) /**< \brief (CMCC ) Base Address */
+#define FLEXCOM6 (0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */
+#define USART6 (0x40040200U) /**< \brief (USART6 ) Base Address */
+#define PDC_USART6 (0x40040300U) /**< \brief (PDC_USART6 ) Base Address */
+#define SPI6 (0x40040400U) /**< \brief (SPI6 ) Base Address */
+#define PDC_SPI6 (0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */
+#define TWI6 (0x40040600U) /**< \brief (TWI6 ) Base Address */
+#define PDC_TWI6 (0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */
+#define UDP (0x40044000U) /**< \brief (UDP ) Base Address */
+#define CRCCU (0x40048000U) /**< \brief (CRCCU ) Base Address */
+#define UHP (0x20400000U) /**< \brief (UHP ) Base Address */
+#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */
+#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */
+#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */
+#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
+#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */
+#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */
+#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */
+#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */
+#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */
+#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */
+#else
+#define I2SC0 ((I2sc *)0x40000000U) /**< \brief (I2SC0 ) Base Address */
+#define PDC_I2SC0 ((Pdc *)0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */
+#define I2SC1 ((I2sc *)0x40004000U) /**< \brief (I2SC1 ) Base Address */
+#define PDC_I2SC1 ((Pdc *)0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */
+#define FLEXCOM5 ((Flexcom *)0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */
+#define USART5 ((Usart *)0x40008200U) /**< \brief (USART5 ) Base Address */
+#define PDC_USART5 ((Pdc *)0x40008300U) /**< \brief (PDC_USART5 ) Base Address */
+#define SPI5 ((Spi *)0x40008400U) /**< \brief (SPI5 ) Base Address */
+#define PDC_SPI5 ((Pdc *)0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */
+#define TWI5 ((Twi *)0x40008600U) /**< \brief (TWI5 ) Base Address */
+#define PDC_TWI5 ((Pdc *)0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */
+#define FLEXCOM0 ((Flexcom *)0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */
+#define USART0 ((Usart *)0x4000C200U) /**< \brief (USART0 ) Base Address */
+#define PDC_USART0 ((Pdc *)0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */
+#define SPI0 ((Spi *)0x4000C400U) /**< \brief (SPI0 ) Base Address */
+#define PDC_SPI0 ((Pdc *)0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */
+#define TWI0 ((Twi *)0x4000C600U) /**< \brief (TWI0 ) Base Address */
+#define PDC_TWI0 ((Pdc *)0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */
+#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */
+#define PDC_TC0 ((Pdc *)0x40010100U) /**< \brief (PDC_TC0 ) Base Address */
+#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */
+#define FLEXCOM3 ((Flexcom *)0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */
+#define USART3 ((Usart *)0x40018200U) /**< \brief (USART3 ) Base Address */
+#define PDC_USART3 ((Pdc *)0x40018300U) /**< \brief (PDC_USART3 ) Base Address */
+#define SPI3 ((Spi *)0x40018400U) /**< \brief (SPI3 ) Base Address */
+#define PDC_SPI3 ((Pdc *)0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */
+#define TWI3 ((Twi *)0x40018600U) /**< \brief (TWI3 ) Base Address */
+#define PDC_TWI3 ((Pdc *)0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */
+#define FLEXCOM4 ((Flexcom *)0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */
+#define USART4 ((Usart *)0x4001C200U) /**< \brief (USART4 ) Base Address */
+#define PDC_USART4 ((Pdc *)0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */
+#define SPI4 ((Spi *)0x4001C400U) /**< \brief (SPI4 ) Base Address */
+#define PDC_SPI4 ((Pdc *)0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */
+#define TWI4 ((Twi *)0x4001C600U) /**< \brief (TWI4 ) Base Address */
+#define PDC_TWI4 ((Pdc *)0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */
+#define FLEXCOM1 ((Flexcom *)0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */
+#define USART1 ((Usart *)0x40020200U) /**< \brief (USART1 ) Base Address */
+#define PDC_USART1 ((Pdc *)0x40020300U) /**< \brief (PDC_USART1 ) Base Address */
+#define SPI1 ((Spi *)0x40020400U) /**< \brief (SPI1 ) Base Address */
+#define PDC_SPI1 ((Pdc *)0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */
+#define TWI1 ((Twi *)0x40020600U) /**< \brief (TWI1 ) Base Address */
+#define PDC_TWI1 ((Pdc *)0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */
+#define FLEXCOM2 ((Flexcom *)0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */
+#define USART2 ((Usart *)0x40024200U) /**< \brief (USART2 ) Base Address */
+#define PDC_USART2 ((Pdc *)0x40024300U) /**< \brief (PDC_USART2 ) Base Address */
+#define SPI2 ((Spi *)0x40024400U) /**< \brief (SPI2 ) Base Address */
+#define PDC_SPI2 ((Pdc *)0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */
+#define TWI2 ((Twi *)0x40024600U) /**< \brief (TWI2 ) Base Address */
+#define PDC_TWI2 ((Pdc *)0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */
+#define MEM2MEM ((Mem2mem *)0x40028000U) /**< \brief (MEM2MEM ) Base Address */
+#define PDC_MEM2MEM ((Pdc *)0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */
+#define PDMIC0 ((Pdmic *)0x4002C000U) /**< \brief (PDMIC0 ) Base Address */
+#define PDC_PDMIC0 ((Pdc *)0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */
+#define PDMIC1 ((Pdmic *)0x40030000U) /**< \brief (PDMIC1 ) Base Address */
+#define PDC_PDMIC1 ((Pdc *)0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */
+#define FLEXCOM7 ((Flexcom *)0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */
+#define USART7 ((Usart *)0x40034200U) /**< \brief (USART7 ) Base Address */
+#define PDC_USART7 ((Pdc *)0x40034300U) /**< \brief (PDC_USART7 ) Base Address */
+#define SPI7 ((Spi *)0x40034400U) /**< \brief (SPI7 ) Base Address */
+#define PDC_SPI7 ((Pdc *)0x40034500U) /**< \brief (PDC_SPI7 ) Base Address */
+#define TWI7 ((Twi *)0x40034600U) /**< \brief (TWI7 ) Base Address */
+#define PDC_TWI7 ((Pdc *)0x40034700U) /**< \brief (PDC_TWI7 ) Base Address */
+#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */
+#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */
+#define CMCC ((Cmcc *)0x4003C000U) /**< \brief (CMCC ) Base Address */
+#define FLEXCOM6 ((Flexcom *)0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */
+#define USART6 ((Usart *)0x40040200U) /**< \brief (USART6 ) Base Address */
+#define PDC_USART6 ((Pdc *)0x40040300U) /**< \brief (PDC_USART6 ) Base Address */
+#define SPI6 ((Spi *)0x40040400U) /**< \brief (SPI6 ) Base Address */
+#define PDC_SPI6 ((Pdc *)0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */
+#define TWI6 ((Twi *)0x40040600U) /**< \brief (TWI6 ) Base Address */
+#define PDC_TWI6 ((Pdc *)0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */
+#define UDP ((Udp *)0x40044000U) /**< \brief (UDP ) Base Address */
+#define CRCCU ((Crccu *)0x40048000U) /**< \brief (CRCCU ) Base Address */
+#define UHP ((Uhp *)0x20400000U) /**< \brief (UHP ) Base Address */
+#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */
+#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */
+#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */
+#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
+#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */
+#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */
+#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */
+#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */
+#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */
+#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/* PIO DEFINITIONS FOR SAMG55J19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55J19_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio_samg55j19.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* MEMORY MAPPING DEFINITIONS FOR SAMG55J19 */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE (0x80000u)
+#define IFLASH_PAGE_SIZE (512u)
+#define IFLASH_LOCK_REGION_SIZE (8192u)
+#define IFLASH_NB_OF_PAGES (1024u)
+#define IFLASH_NB_OF_LOCK_BITS (64u)
+#define IRAM_SIZE (0x28000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/* MISCELLANEOUS DEFINITIONS FOR SAMG55J19 */
+/* ************************************************************************** */
+
+#define CHIP_JTAGID (0x05B3E03FUL)
+#define CHIP_CIDR (0x24570AE0UL)
+#define CHIP_EXID (0x0UL)
+#define NB_CH_ADC (8UL)
+
+/* ************************************************************************** */
+/* ELECTRICAL DEFINITIONS FOR SAMG55J19 */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
+#define CHIP_FREQ_SLCK_RC (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_16MHZ (16000000UL)
+#define CHIP_FREQ_MAINCK_RC_24MHZ (24000000UL)
+#define CHIP_FREQ_CPU_MAX (120000000UL)
+#define CHIP_FREQ_XTAL_32K (32768UL)
+
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE (5U)
+
+/* Embedded Flash Read Wait State (VDDIO set at 1.62V, Max value) */
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
+#define CHIP_FREQ_FWS_5 (120000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAMG55J19_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/samg55n19.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,747 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _SAMG55N19_
+#define _SAMG55N19_
+
+/** \addtogroup SAMG55N19_definitions SAMG55N19 definitions
+ This file defines all structures and symbols for SAMG55N19:
+ - registers and bitfields
+ - peripheral base address
+ - peripheral ID
+ - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#endif
+
+/* ************************************************************************** */
+/* CMSIS DEFINITIONS FOR SAMG55N19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55N19_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn {
+ /****** Cortex-M4 Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
+ /****** SAMG55N19 specific Interrupt Numbers *********************************/
+
+ SUPC_IRQn = 0, /**< 0 SAMG55N19 Supply Controller (SUPC) */
+ RSTC_IRQn = 1, /**< 1 SAMG55N19 Reset Controller (RSTC) */
+ RTC_IRQn = 2, /**< 2 SAMG55N19 Real Time Clock (RTC) */
+ RTT_IRQn = 3, /**< 3 SAMG55N19 Real Time Timer (RTT) */
+ WDT_IRQn = 4, /**< 4 SAMG55N19 Watchdog Timer (WDT) */
+ PMC_IRQn = 5, /**< 5 SAMG55N19 Power Management Controller (PMC) */
+ EFC_IRQn = 6, /**< 6 SAMG55N19 Enhanced Flash Controller (EFC) */
+ USART7_IRQn = 48, /**< 48 SAMG55N19 FLEXCOM 7 (USART7) */
+ SPI7_IRQn = 48, /**< 48 SAMG55N19 FLEXCOM 7 (SPI7) */
+ TWI7_IRQn = 48, /**< 48 SAMG55N19 FLEXCOM 7 (TWI7) */
+ USART0_IRQn = 8, /**< 8 SAMG55 FLEXCOM 0 (USART0) */
+ SPI0_IRQn = 8, /**< 8 SAMG55 FLEXCOM 0 (SPI0) */
+ TWI0_IRQn = 8, /**< 8 SAMG55 FLEXCOM 0 (TWI0) */
+ USART1_IRQn = 9, /**< 9 SAMG55 FLEXCOM 1 (USART1) */
+ SPI1_IRQn = 9, /**< 8 SAMG55 FLEXCOM 1 (SPI1) */
+ TWI1_IRQn = 9, /**< 8 SAMG55 FLEXCOM 1 (TWI1) */
+ PIOA_IRQn = 11, /**< 11 SAMG55N19 Parallel I/O Controller A (PIOA) */
+ PIOB_IRQn = 12, /**< 12 SAMG55N19 Parallel I/O Controller B (PIOB) */
+ PDMIC0_IRQn = 13, /**< 13 SAMG55N19 PDM 0 (PDMIC0) */
+ USART2_IRQn = 14, /**< 14 SAMG55 FLEXCOM2 (USART2) */
+ SPI2_IRQn = 14, /**< 14 SAMG55 FLEXCOM 2 (SPI2) */
+ TWI2_IRQn = 14, /**< 14 SAMG55 FLEXCOM 2 (TWI2) */
+ MEM2MEM_IRQn = 15, /**< 15 SAMG55N19 MEM2MEM (MEM2MEM) */
+ I2SC0_IRQn = 16, /**< 16 SAMG55N19 I2SC0 (I2SC0) */
+ I2SC1_IRQn = 17, /**< 17 SAMG55N19 I2SC1 (I2SC1) */
+ PDMIC1_IRQn = 18, /**< 18 SAMG55N19 PDM 1 (PDMIC1) */
+ USART3__IRQn = 19, /**< 19 SAMG55 FLEXCOM3 (USART3) */
+ SPI3_IRQn = 19, /**< 19 SAMG55 FLEXCOM 3 (SPI3) */
+ TWI3_IRQn = 19, /**< 19 SAMG55 FLEXCOM 3 (TWI3) */
+ USART4_IRQn = 20, /**< 20 SAMG55 FLEXCOM4 (USART4) */
+ SPI4_IRQn = 20, /**< 8 SAMG55 FLEXCOM 4 (SPI4) */
+ TWI4_IRQn = 20, /**< 8 SAMG55 FLEXCOM 4 (TWI4) */
+ USART5_IRQn = 21, /**< 21 SAMG55 FLEXCOM5 (USART5) */
+ SPI5_IRQn = 21, /**< 8 SAMG55 FLEXCOM 5 (SPI5) */
+ TWI5_IRQn = 21, /**< 8 SAMG55 FLEXCOM 5 (TWI5) */
+ USART6_IRQn = 22, /**< 22 SAMG55 FLEXCOM6 (USART6) */
+ SPI6_IRQn = 22, /**< 22 SAMG55 FLEXCOM 6 (SPI6) */
+ TWI6_IRQn = 22, /**< 22 SAMG55 FLEXCOM 6 (TWI6) */
+ TC0_IRQn = 23, /**< 23 SAMG55N19 Timer/Counter 0 (TC0) */
+ TC1_IRQn = 24, /**< 24 SAMG55N19 Timer/Counter 1 (TC1) */
+ TC2_IRQn = 25, /**< 25 SAMG55N19 Timer/Counter 2 (TC2) */
+ TC3_IRQn = 26, /**< 26 SAMG55N19 Timer/Counter 3 (TC3) */
+ TC4_IRQn = 27, /**< 27 SAMG55N19 Timer/Counter 4 (TC4) */
+ TC5_IRQn = 28, /**< 28 SAMG55N19 Timer/Counter 5 (TC5) */
+ ADC_IRQn = 29, /**< 29 SAMG55N19 Analog To Digital Converter (ADC) */
+ ARM_IRQn = 30, /**< 30 SAMG55N19 FPU (ARM) */
+ WKUP0_IRQn = 31, /**< 31 SAMG55 External interrupt 0 (WKUP0) */
+ WKUP1_IRQn = 32, /**< 32 SAMG55 External interrupt 1 (WKUP1) */
+ WKUP2_IRQn = 33, /**< 33 SAMG55 External interrupt 2 (WKUP2) */
+ WKUP3_IRQn = 34, /**< 34 SAMG55 External interrupt 3 (WKUP3) */
+ WKUP4_IRQn = 35, /**< 35 SAMG55 External interrupt 4 (WKUP4) */
+ WKUP5_IRQn = 36, /**< 36 SAMG55 External interrupt 5 (WKUP5) */
+ WKUP6_IRQn = 37, /**< 37 SAMG55 External interrupt 6 (WKUP6) */
+ WKUP7_IRQn = 38, /**< 38 SAMG55 External interrupt 7 (WKUP7) */
+ WKUP8_IRQn = 39, /**< 39 SAMG55 External interrupt 8 (WKUP8) */
+ WKUP9_IRQn = 40, /**< 40 SAMG55 External interrupt 9 (WKUP9) */
+ WKUP10_IRQn = 41, /**< 41 SAMG55 External interrupt 10 (WKUP10) */
+ WKUP11_IRQn = 42, /**< 42 SAMG55 External interrupt 11 (WKUP11) */
+ WKUP12_IRQn = 43, /**< 43 SAMG55 External interrupt 12 (WKUP12) */
+ WKUP13_IRQn = 44, /**< 44 SAMG55 External interrupt 13 (WKUP13) */
+ WKUP14_IRQn = 45, /**< 45 SAMG55 External interrupt 14 (WKUP14) */
+ WKUP15_IRQn = 46, /**< 46 SAMG55 External interrupt 15 (WKUP15) */
+ UHP_IRQn = 47, /**< 47 SAMG55N19 USB OHCI (UHP) */
+ UDP_IRQn = 48, /**< 48 SAMG55N19 USB Device FS (UDP) */
+
+ PERIPH_COUNT_IRQn = 49 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnMemManage_Handler;
+ void* pfnBusFault_Handler;
+ void* pfnUsageFault_Handler;
+ void* pfnReserved1_Handler;
+ void* pfnReserved2_Handler;
+ void* pfnReserved3_Handler;
+ void* pfnReserved4_Handler;
+ void* pfnSVC_Handler;
+ void* pfnDebugMon_Handler;
+ void* pfnReserved5_Handler;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnSUPC_Handler; /* 0 Supply Controller */
+ void* pfnRSTC_Handler; /* 1 Reset Controller */
+ void* pfnRTC_Handler; /* 2 Real Time Clock */
+ void* pfnRTT_Handler; /* 3 Real Time Timer */
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */
+ void* pfnPMC_Handler; /* 5 Power Management Controller */
+ void* pfnEFC_Handler; /* 6 Enhanced Flash Controller */
+ void* pfnUSART7_Handler; /* USART7 */
+ void* pfnSPI7_Handler; /* SPI7 */
+ void* pfnTWI7_Handler; /* TWI7 */
+ void* pfnUSART0_Handler; /* 8 FLEXCOM 0 */
+ void* pfnSPI0_Handler; /* 8 FLEXCOM 0 */
+ void* pfnTWI0_Handler; /* 8 FLEXCOM 0 */
+ void* pfnUSART1_Handler; /* 9 FLEXCOM 1 */
+ void* pfnSPI1_Handler; /* 9 FLEXCOM 1 */
+ void* pfnTWI1_Handler; /* 9 FLEXCOM 1 */
+ void* pvReserved10;
+ void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */
+ void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */
+ void* pfnPDMIC0_Handler; /* 13 PDM 0 */
+ void* pfnUSART2_Handler; /* 14 FLEXCOM 2 */
+ void* pfnSPI2_Handler; /* 14 FLEXCOM 2 */
+ void* pfnTWI2_Handler; /* 14 FLEXCOM 2 */
+ void* pfnMEM2MEM_Handler; /* 15 MEM2MEM */
+ void* pfnI2SC0_Handler; /* 16 I2SC0 */
+ void* pfnI2SC1_Handler; /* 17 I2SC1 */
+ void* pfnPDMIC1_Handler; /* 18 PDM 1 */
+ void* pfnUSART3_Handler; /* 19 FLEXCOM 3 */
+ void* pfnSPI3_Handler; /* 19 FLEXCOM 3 */
+ void* pfnTWI3_Handler; /* 19 FLEXCOM 3 */
+ void* pfnUSART4_Handler; /* 20 FLEXCOM 4 */
+ void* pfnSPI4_Handler; /* 20 FLEXCOM 4 */
+ void* pfnTWI4_Handler; /* 20 FLEXCOM 4 */
+ void* pfnUSART5_Handler; /* 21 FLEXCOM 5 */
+ void* pfnSPI5_Handler; /* 21 FLEXCOM 5 */
+ void* pfnTWI5_Handler; /* 21 FLEXCOM 5 */
+ void* pfnUSART6_Handler; /* 22 FLEXCOM 6 */
+ void* pfnSPI6_Handler; /* 22 FLEXCOM 6 */
+ void* pfnTWI6_Handler; /* 22 FLEXCOM 6 */
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
+ void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
+ void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
+ void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
+ void* pfnADC_Handler; /* 29 Analog To Digital Converter */
+ void* pfnARM_Handler; /* 30 FPU */
+ void* pvReserved31;
+ void* pvReserved32;
+ void* pvReserved33;
+ void* pvReserved34;
+ void* pvReserved35;
+ void* pvReserved36;
+ void* pvReserved37;
+ void* pvReserved38;
+ void* pvReserved39;
+ void* pvReserved40;
+ void* pvReserved41;
+ void* pvReserved42;
+ void* pvReserved43;
+ void* pvReserved44;
+ void* pvReserved45;
+ void* pvReserved46;
+ void* pfnUHP_Handler; /* 47 USB OHCI */
+ void* pfnUDP_Handler; /* 48 USB Device FS */
+ void* pvReserved49; /* */
+ void* pvReserved50; /* */
+ void* pvReserved51; /* */
+ void* pvReserved52; /* */
+ void* pvReserved53; /* */
+ void* pvReserved54; /* */
+ void* pvReserved55; /* */
+ void* pvReserved56; /* */
+ void* pvReserved57; /* */
+ void* pvReserved58; /* */
+ void* pvReserved59; /* */
+ void* pvReserved60; /* */
+ void* pvReserved61; /* */
+ void* pvReserved62; /* */
+ void* pvReserved63; /* UHP */
+ void* pvReserved64; /* UDP */
+ void* pvReserved65; /* CRCCU */
+} DeviceVectors;
+
+/* Cortex-M4 core handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void MemManage_Handler ( void );
+void BusFault_Handler ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler ( void );
+void DebugMon_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void ADC_Handler ( void );
+void ARM_Handler ( void );
+void EFC_Handler ( void );
+void I2SC0_Handler ( void );
+void I2SC1_Handler ( void );
+void MEM2MEM_Handler ( void );
+void PDMIC0_Handler ( void );
+void PDMIC1_Handler ( void );
+void PIOA_Handler ( void );
+void PIOB_Handler ( void );
+void PMC_Handler ( void );
+void RSTC_Handler ( void );
+void RTC_Handler ( void );
+void RTT_Handler ( void );
+void SPI0_Handler ( void );
+void SPI1_Handler ( void );
+void SPI2_Handler ( void );
+void SPI3_Handler ( void );
+void SPI4_Handler ( void );
+void SPI5_Handler ( void );
+void SPI6_Handler ( void );
+void SPI7_Handler ( void );
+void SUPC_Handler ( void );
+void TC0_Handler ( void );
+void TC1_Handler ( void );
+void TC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TWI0_Handler ( void );
+void TWI1_Handler ( void );
+void TWI2_Handler ( void );
+void TWI3_Handler ( void );
+void TWI4_Handler ( void );
+void TWI5_Handler ( void );
+void TWI6_Handler ( void );
+void TWI7_Handler ( void );
+void UDP_Handler ( void );
+void UHP_Handler ( void );
+void USART0_Handler ( void );
+void USART1_Handler ( void );
+void USART2_Handler ( void );
+void USART3_Handler ( void );
+void USART4_Handler ( void );
+void USART5_Handler ( void );
+void USART6_Handler ( void );
+void USART7_Handler ( void );
+void WDT_Handler ( void );
+
+/**
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define __CM4_REV 0x0001 /**< SAMG55N19 core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT 1 /**< SAMG55N19 does provide a MPU */
+#define __FPU_PRESENT 1 /**< SAMG55N19 does provide a FPU */
+#define __NVIC_PRIO_BITS 4 /**< SAMG55N19 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include <core_cm4.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samg55.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMG55N19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55N19_api Peripheral Software API */
+/*@{*/
+
+#include "comp_adc.h"
+#include "comp_chipid.h"
+#include "comp_cmcc.h"
+#include "comp_crccu.h"
+#include "comp_efc.h"
+#include "comp_flexcom.h"
+#include "comp_gpbr.h"
+#include "comp_i2sc.h"
+#include "comp_matrix.h"
+#include "comp_mem2mem.h"
+#include "comp_pdc.h"
+#include "comp_pdmic.h"
+#include "comp_pio.h"
+#include "comp_pmc.h"
+#include "comp_rstc.h"
+#include "comp_rtc.h"
+#include "comp_rtt.h"
+#include "comp_spi.h"
+#include "comp_supc.h"
+#include "comp_tc.h"
+#include "comp_twi.h"
+#include "comp_twihs.h"
+#include "comp_udp.h"
+#include "comp_usart.h"
+#include "comp_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* REGISTER ACCESS DEFINITIONS FOR SAMG55N19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55N19_reg Registers Access Definitions */
+/*@{*/
+
+#include "ins_i2sc0.h"
+#include "ins_i2sc1.h"
+#include "ins_flexcom5.h"
+#include "ins_usart5.h"
+#include "ins_spi5.h"
+#include "ins_twi5.h"
+#include "ins_flexcom0.h"
+#include "ins_usart0.h"
+#include "ins_spi0.h"
+#include "ins_twi0.h"
+#include "ins_tc0.h"
+#include "ins_tc1.h"
+#include "ins_flexcom3.h"
+#include "ins_usart3.h"
+#include "ins_spi3.h"
+#include "ins_twi3.h"
+#include "ins_flexcom4.h"
+#include "ins_usart4.h"
+#include "ins_spi4.h"
+#include "ins_twi4.h"
+#include "ins_flexcom1.h"
+#include "ins_usart1.h"
+#include "ins_spi1.h"
+#include "ins_twi1.h"
+#include "ins_flexcom2.h"
+#include "ins_usart2.h"
+#include "ins_spi2.h"
+#include "ins_twi2.h"
+#include "ins_mem2mem.h"
+#include "ins_pdmic0.h"
+#include "ins_pdmic1.h"
+#include "ins_flexcom7.h"
+#include "ins_usart7.h"
+#include "ins_spi7.h"
+#include "ins_twi7.h"
+#include "ins_adc.h"
+#include "ins_cmcc.h"
+#include "ins_flexcom6.h"
+#include "ins_usart6.h"
+#include "ins_spi6.h"
+#include "ins_twi6.h"
+#include "ins_udp.h"
+#include "ins_crccu.h"
+#include "ins_uhp.h"
+#include "ins_matrix.h"
+#include "ins_pmc.h"
+#include "ins_chipid.h"
+#include "ins_efc.h"
+#include "ins_pioa.h"
+#include "ins_piob.h"
+#include "ins_rstc.h"
+#include "ins_supc.h"
+#include "ins_rtt.h"
+#include "ins_wdt.h"
+#include "ins_rtc.h"
+#include "ins_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* PERIPHERAL ID DEFINITIONS FOR SAMG55N19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55N19_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_USART7 ( 7) /**< \brief FLEXCOM 7 (USART7) */
+#define ID_SPI7 ( 7) /**< \brief FLEXCOM 7 (SPI7) */
+#define ID_TWI7 ( 7) /**< \brief FLEXCOM 7 (TWI7) */
+#define ID_USART0 ( 8) /**< \brief FLEXCOM 0 (USART0) */
+#define ID_SPI0 ( 8) /**< \brief FLEXCOM 0 (SPI0) */
+#define ID_TWI0 ( 8) /**< \brief FLEXCOM 0 (TWI0) */
+#define ID_USART1 ( 9) /**< \brief FLEXCOM 1 (USART1) */
+#define ID_SPI1 ( 9) /**< \brief FLEXCOM 1 (SPI1) */
+#define ID_TWI1 ( 9) /**< \brief FLEXCOM 1 (TWI1) */
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PDMIC0 (13) /**< \brief PDM 0 (PDMIC0) */
+#define ID_USART2 (14) /**< \brief FLEXCOM2 (USART2) */
+#define ID_SPI2 (14) /**< \brief FLEXCOM2 (SPI2) */
+#define ID_TWI2 (14) /**< \brief FLEXCOM2 (TWI2) */
+#define ID_MEM2MEM (15) /**< \brief MEM2MEM (MEM2MEM) */
+#define ID_I2SC0 (16) /**< \brief I2SC0 (I2SC0) */
+#define ID_I2SC1 (17) /**< \brief I2SC1 (I2SC1) */
+#define ID_PDMIC1 (18) /**< \brief PDM 1 (PDMIC1) */
+#define ID_USART3 (19) /**< \brief FLEXCOM3 (USART3) */
+#define ID_SPI3 (19) /**< \brief FLEXCOM3 (SPI3) */
+#define ID_TWI3 (19) /**< \brief FLEXCOM3 (TWI3) */
+#define ID_USART4 (20) /**< \brief FLEXCOM4 (USART4) */
+#define ID_SPI4 (20) /**< \brief FLEXCOM4 (SPI4) */
+#define ID_TWI4 (20) /**< \brief FLEXCOM4 (TWI4) */
+#define ID_USART5 (21) /**< \brief FLEXCOM5 (USART5) */
+#define ID_SPI5 (21) /**< \brief FLEXCOM5 (SPI5) */
+#define ID_TWI5 (21) /**< \brief FLEXCOM5 (TWI5) */
+#define ID_USART6 (22) /**< \brief FLEXCOM6 (USART6) */
+#define ID_SPI6 (22) /**< \brief FLEXCOM6 (SPI6) */
+#define ID_TWI6 (22) /**< \brief FLEXCOM6 (TWI6) */
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_ARM (30) /**< \brief FPU (ARM) */
+#define ID_UHP (47) /**< \brief USB OHCI (UHP) */
+#define ID_UDP (48) /**< \brief USB Device FS (UDP) */
+#define ID_CRCCU (49) /**< \brief CRCCU (CRCCU) */
+
+#define ID_PERIPH_COUNT (50) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/* BASE ADDRESS DEFINITIONS FOR SAMG55N19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55N19_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define I2SC0 (0x40000000U) /**< \brief (I2SC0 ) Base Address */
+#define PDC_I2SC0 (0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */
+#define I2SC1 (0x40004000U) /**< \brief (I2SC1 ) Base Address */
+#define PDC_I2SC1 (0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */
+#define FLEXCOM5 (0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */
+#define USART5 (0x40008200U) /**< \brief (USART5 ) Base Address */
+#define PDC_USART5 (0x40008300U) /**< \brief (PDC_USART5 ) Base Address */
+#define SPI5 (0x40008400U) /**< \brief (SPI5 ) Base Address */
+#define PDC_SPI5 (0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */
+#define TWI5 (0x40008600U) /**< \brief (TWI5 ) Base Address */
+#define PDC_TWI5 (0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */
+#define FLEXCOM0 (0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */
+#define USART0 (0x4000C200U) /**< \brief (USART0 ) Base Address */
+#define PDC_USART0 (0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */
+#define SPI0 (0x4000C400U) /**< \brief (SPI0 ) Base Address */
+#define PDC_SPI0 (0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */
+#define TWI0 (0x4000C600U) /**< \brief (TWI0 ) Base Address */
+#define PDC_TWI0 (0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */
+#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */
+#define PDC_TC0 (0x40010100U) /**< \brief (PDC_TC0 ) Base Address */
+#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */
+#define FLEXCOM3 (0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */
+#define USART3 (0x40018200U) /**< \brief (USART3 ) Base Address */
+#define PDC_USART3 (0x40018300U) /**< \brief (PDC_USART3 ) Base Address */
+#define SPI3 (0x40018400U) /**< \brief (SPI3 ) Base Address */
+#define PDC_SPI3 (0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */
+#define TWI3 (0x40018600U) /**< \brief (TWI3 ) Base Address */
+#define PDC_TWI3 (0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */
+#define FLEXCOM4 (0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */
+#define USART4 (0x4001C200U) /**< \brief (USART4 ) Base Address */
+#define PDC_USART4 (0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */
+#define SPI4 (0x4001C400U) /**< \brief (SPI4 ) Base Address */
+#define PDC_SPI4 (0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */
+#define TWI4 (0x4001C600U) /**< \brief (TWI4 ) Base Address */
+#define PDC_TWI4 (0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */
+#define FLEXCOM1 (0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */
+#define USART1 (0x40020200U) /**< \brief (USART1 ) Base Address */
+#define PDC_USART1 (0x40020300U) /**< \brief (PDC_USART1 ) Base Address */
+#define SPI1 (0x40020400U) /**< \brief (SPI1 ) Base Address */
+#define PDC_SPI1 (0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */
+#define TWI1 (0x40020600U) /**< \brief (TWI1 ) Base Address */
+#define PDC_TWI1 (0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */
+#define FLEXCOM2 (0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */
+#define USART2 (0x40024200U) /**< \brief (USART2 ) Base Address */
+#define PDC_USART2 (0x40024300U) /**< \brief (PDC_USART2 ) Base Address */
+#define SPI2 (0x40024400U) /**< \brief (SPI2 ) Base Address */
+#define PDC_SPI2 (0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */
+#define TWI2 (0x40024600U) /**< \brief (TWI2 ) Base Address */
+#define PDC_TWI2 (0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */
+#define MEM2MEM (0x40028000U) /**< \brief (MEM2MEM ) Base Address */
+#define PDC_MEM2MEM (0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */
+#define PDMIC0 (0x4002C000U) /**< \brief (PDMIC0 ) Base Address */
+#define PDC_PDMIC0 (0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */
+#define PDMIC1 (0x40030000U) /**< \brief (PDMIC1 ) Base Address */
+#define PDC_PDMIC1 (0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */
+#define FLEXCOM7 (0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */
+#define USART7 (0x40034200U) /**< \brief (USART7 ) Base Address */
+#define PDC_USART7 (0x40034300U) /**< \brief (PDC_USART7 ) Base Address */
+#define SPI7 (0x40034400U) /**< \brief (SPI7 ) Base Address */
+#define PDC_SPI7 (0x40034500U) /**< \brief (PDC_SPI7 ) Base Address */
+#define TWI7 (0x40034600U) /**< \brief (TWI7 ) Base Address */
+#define PDC_TWI7 (0x40034700U) /**< \brief (PDC_TWI7 ) Base Address */
+#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */
+#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */
+#define CMCC (0x4003C000U) /**< \brief (CMCC ) Base Address */
+#define FLEXCOM6 (0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */
+#define USART6 (0x40040200U) /**< \brief (USART6 ) Base Address */
+#define PDC_USART6 (0x40040300U) /**< \brief (PDC_USART6 ) Base Address */
+#define SPI6 (0x40040400U) /**< \brief (SPI6 ) Base Address */
+#define PDC_SPI6 (0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */
+#define TWI6 (0x40040600U) /**< \brief (TWI6 ) Base Address */
+#define PDC_TWI6 (0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */
+#define UDP (0x40044000U) /**< \brief (UDP ) Base Address */
+#define CRCCU (0x40048000U) /**< \brief (CRCCU ) Base Address */
+#define UHP (0x4004C000U) /**< \brief (UHP ) Base Address */
+#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */
+#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */
+#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */
+#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
+#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */
+#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */
+#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */
+#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */
+#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */
+#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */
+#else
+#define I2SC0 ((I2sc *)0x40000000U) /**< \brief (I2SC0 ) Base Address */
+#define PDC_I2SC0 ((Pdc *)0x40000100U) /**< \brief (PDC_I2SC0 ) Base Address */
+#define I2SC1 ((I2sc *)0x40004000U) /**< \brief (I2SC1 ) Base Address */
+#define PDC_I2SC1 ((Pdc *)0x40004100U) /**< \brief (PDC_I2SC1 ) Base Address */
+#define FLEXCOM5 ((Flexcom *)0x40008000U) /**< \brief (FLEXCOM5 ) Base Address */
+#define USART5 ((Usart *)0x40008200U) /**< \brief (USART5 ) Base Address */
+#define PDC_USART5 ((Pdc *)0x40008300U) /**< \brief (PDC_USART5 ) Base Address */
+#define SPI5 ((Spi *)0x40008400U) /**< \brief (SPI5 ) Base Address */
+#define PDC_SPI5 ((Pdc *)0x40008500U) /**< \brief (PDC_SPI5 ) Base Address */
+#define TWI5 ((Twi *)0x40008600U) /**< \brief (TWI5 ) Base Address */
+#define PDC_TWI5 ((Pdc *)0x40008700U) /**< \brief (PDC_TWI5 ) Base Address */
+#define FLEXCOM0 ((Flexcom *)0x4000C000U) /**< \brief (FLEXCOM0 ) Base Address */
+#define USART0 ((Usart *)0x4000C200U) /**< \brief (USART0 ) Base Address */
+#define PDC_USART0 ((Pdc *)0x4000C300U) /**< \brief (PDC_USART0 ) Base Address */
+#define SPI0 ((Spi *)0x4000C400U) /**< \brief (SPI0 ) Base Address */
+#define PDC_SPI0 ((Pdc *)0x4000C500U) /**< \brief (PDC_SPI0 ) Base Address */
+#define TWI0 ((Twi *)0x4000C600U) /**< \brief (TWI0 ) Base Address */
+#define PDC_TWI0 ((Pdc *)0x4000C700U) /**< \brief (PDC_TWI0 ) Base Address */
+#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */
+#define PDC_TC0 ((Pdc *)0x40010100U) /**< \brief (PDC_TC0 ) Base Address */
+#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */
+#define FLEXCOM3 ((Flexcom *)0x40018000U) /**< \brief (FLEXCOM3 ) Base Address */
+#define USART3 ((Usart *)0x40018200U) /**< \brief (USART3 ) Base Address */
+#define PDC_USART3 ((Pdc *)0x40018300U) /**< \brief (PDC_USART3 ) Base Address */
+#define SPI3 ((Spi *)0x40018400U) /**< \brief (SPI3 ) Base Address */
+#define PDC_SPI3 ((Pdc *)0x40018500U) /**< \brief (PDC_SPI3 ) Base Address */
+#define TWI3 ((Twihs *)0x40018600U) /**< \brief (TWI3 ) Base Address */
+#define PDC_TWI3 ((Pdc *)0x40018700U) /**< \brief (PDC_TWI3 ) Base Address */
+#define FLEXCOM4 ((Flexcom *)0x4001C000U) /**< \brief (FLEXCOM4 ) Base Address */
+#define USART4 ((Usart *)0x4001C200U) /**< \brief (USART4 ) Base Address */
+#define PDC_USART4 ((Pdc *)0x4001C300U) /**< \brief (PDC_USART4 ) Base Address */
+#define SPI4 ((Spi *)0x4001C400U) /**< \brief (SPI4 ) Base Address */
+#define PDC_SPI4 ((Pdc *)0x4001C500U) /**< \brief (PDC_SPI4 ) Base Address */
+#define TWI4 ((Twi *)0x4001C600U) /**< \brief (TWI4 ) Base Address */
+#define PDC_TWI4 ((Pdc *)0x4001C700U) /**< \brief (PDC_TWI4 ) Base Address */
+#define FLEXCOM1 ((Flexcom *)0x40020000U) /**< \brief (FLEXCOM1 ) Base Address */
+#define USART1 ((Usart *)0x40020200U) /**< \brief (USART1 ) Base Address */
+#define PDC_USART1 ((Pdc *)0x40020300U) /**< \brief (PDC_USART1 ) Base Address */
+#define SPI1 ((Spi *)0x40020400U) /**< \brief (SPI1 ) Base Address */
+#define PDC_SPI1 ((Pdc *)0x40020500U) /**< \brief (PDC_SPI1 ) Base Address */
+#define TWI1 ((Twi *)0x40020600U) /**< \brief (TWI1 ) Base Address */
+#define PDC_TWI1 ((Pdc *)0x40020700U) /**< \brief (PDC_TWI1 ) Base Address */
+#define FLEXCOM2 ((Flexcom *)0x40024000U) /**< \brief (FLEXCOM2 ) Base Address */
+#define USART2 ((Usart *)0x40024200U) /**< \brief (USART2 ) Base Address */
+#define PDC_USART2 ((Pdc *)0x40024300U) /**< \brief (PDC_USART2 ) Base Address */
+#define SPI2 ((Spi *)0x40024400U) /**< \brief (SPI2 ) Base Address */
+#define PDC_SPI2 ((Pdc *)0x40024500U) /**< \brief (PDC_SPI2 ) Base Address */
+#define TWI2 ((Twi *)0x40024600U) /**< \brief (TWI2 ) Base Address */
+#define PDC_TWI2 ((Pdc *)0x40024700U) /**< \brief (PDC_TWI2 ) Base Address */
+#define MEM2MEM ((Mem2mem *)0x40028000U) /**< \brief (MEM2MEM ) Base Address */
+#define PDC_MEM2MEM ((Pdc *)0x40028100U) /**< \brief (PDC_MEM2MEM) Base Address */
+#define PDMIC0 ((Pdmic *)0x4002C000U) /**< \brief (PDMIC0 ) Base Address */
+#define PDC_PDMIC0 ((Pdc *)0x4002C100U) /**< \brief (PDC_PDMIC0 ) Base Address */
+#define PDMIC1 ((Pdmic *)0x40030000U) /**< \brief (PDMIC1 ) Base Address */
+#define PDC_PDMIC1 ((Pdc *)0x40030100U) /**< \brief (PDC_PDMIC1 ) Base Address */
+#define FLEXCOM7 ((Flexcom *)0x40034000U) /**< \brief (FLEXCOM7 ) Base Address */
+#define USART7 ((Usart *)0x40034200U) /**< \brief (USART7 ) Base Address */
+#define PDC_USART7 ((Pdc *)0x40034300U) /**< \brief (PDC_USART7 ) Base Address */
+#define SPI7 ((Spi *)0x40034400U) /**< \brief (SPI7 ) Base Address */
+#define PDC_SPI7 ((Pdc *)0x40034500U) /**< \brief (PDC_SPI7 ) Base Address */
+#define TWI7 ((Twi *)0x40034600U) /**< \brief (TWI7 ) Base Address */
+#define PDC_TWI7 ((Pdc *)0x40034700U) /**< \brief (PDC_TWI7 ) Base Address */
+#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */
+#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */
+#define CMCC ((Cmcc *)0x4003C000U) /**< \brief (CMCC ) Base Address */
+#define FLEXCOM6 ((Flexcom *)0x40040000U) /**< \brief (FLEXCOM6 ) Base Address */
+#define USART6 ((Usart *)0x40040200U) /**< \brief (USART6 ) Base Address */
+#define PDC_USART6 ((Pdc *)0x40040300U) /**< \brief (PDC_USART6 ) Base Address */
+#define SPI6 ((Spi *)0x40040400U) /**< \brief (SPI6 ) Base Address */
+#define PDC_SPI6 ((Pdc *)0x40040500U) /**< \brief (PDC_SPI6 ) Base Address */
+#define TWI6 ((Twi *)0x40040600U) /**< \brief (TWI6 ) Base Address */
+#define PDC_TWI6 ((Pdc *)0x40040700U) /**< \brief (PDC_TWI6 ) Base Address */
+#define UDP ((Udp *)0x40044000U) /**< \brief (UDP ) Base Address */
+#define CRCCU ((Crccu *)0x40048000U) /**< \brief (CRCCU ) Base Address */
+#define UHP ((Uhp *)0x4004C000U) /**< \brief (UHP ) Base Address */
+#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */
+#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */
+#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */
+#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
+#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */
+#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */
+#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */
+#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */
+#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */
+#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/* PIO DEFINITIONS FOR SAMG55N19 */
+/* ************************************************************************** */
+/** \addtogroup SAMG55N19_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio_samg55n19.h"
+/*@}*/
+
+/* ************************************************************************** */
+/* MEMORY MAPPING DEFINITIONS FOR SAMG55N19 */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE (0x80000u)
+#define IFLASH_PAGE_SIZE (512u)
+#define IFLASH_LOCK_REGION_SIZE (8192u)
+#define IFLASH_NB_OF_PAGES (1024u)
+#define IFLASH_NB_OF_LOCK_BITS (64u)
+#define IRAM_SIZE (0x28000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/* MISCELLANEOUS DEFINITIONS FOR SAMG55N19 */
+/* ************************************************************************** */
+
+#define CHIP_JTAGID (0x05B3E03FUL)
+#define CHIP_CIDR (0x24670AE0UL)
+#define CHIP_EXID (0x0UL)
+#define NB_CH_ADC (8UL)
+
+/* ************************************************************************** */
+/* ELECTRICAL DEFINITIONS FOR SAMG55N19 */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
+#define CHIP_FREQ_SLCK_RC (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_16MHZ (16000000UL)
+#define CHIP_FREQ_MAINCK_RC_24MHZ (24000000UL)
+#define CHIP_FREQ_CPU_MAX (120000000UL)
+#define CHIP_FREQ_XTAL_32K (32768UL)
+
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE (5U)
+
+/* Embedded Flash Read Wait State (VDDIO set at 1.62V, Max value) */
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
+#define CHIP_FREQ_FWS_5 (120000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAMG55N19_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/source/system_samg55.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,179 @@
+/**
+ * \file
+ *
+ * \brief Provides the low-level initialization functions that called
+ * on chip startup.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "system_samg55.h"
+#include "samg55.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+ /* @endcond */
+
+ /* Clock Settings (120MHz) */
+#define SYS_BOARD_PLLAR (CKGR_PLLAR_MULA(0xe4eU) \
+ | CKGR_PLLAR_PLLACOUNT(0x3fU) \
+ | CKGR_PLLAR_PLLAEN(0x1U))
+#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK)
+
+ /* Key to unlock MOR register */
+#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37)
+
+ /* External oscillator definition, to be overriden by application */
+#define CHIP_FREQ_XTAL_12M (12000000UL)
+
+#if (!defined CHIP_FREQ_XTAL)
+# define CHIP_FREQ_XTAL CHIP_FREQ_XTAL_12M
+#endif
+
+ uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_8MHZ;
+
+ /**
+ * \brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+ void SystemInit(void)
+{
+ /* Set FWS according to SYS_BOARD_MCKR configuration */
+ EFC->EEFC_FMR = EEFC_FMR_FWS(8)|EEFC_FMR_CLOE;
+
+ /* Initialize PLLA */
+ PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
+ while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
+ }
+
+ /* Switch to PLLA */
+ PMC->PMC_MCKR = SYS_BOARD_MCKR;
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+ }
+
+ SystemCoreClock = CHIP_FREQ_CPU_MAX;
+}
+
+void SystemCoreClockUpdate(void)
+{
+ /* Determine clock frequency according to clock register values */
+ switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) {
+ case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
+ if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
+ SystemCoreClock = CHIP_FREQ_XTAL_32K;
+ } else {
+ SystemCoreClock = CHIP_FREQ_SLCK_RC;
+ }
+ break;
+ case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+ SystemCoreClock = CHIP_FREQ_XTAL;
+ } else {
+ SystemCoreClock = CHIP_FREQ_MAINCK_RC_8MHZ;
+
+ switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+ case CKGR_MOR_MOSCRCF_8_MHz:
+ break;
+ case CKGR_MOR_MOSCRCF_16_MHz:
+ SystemCoreClock *= 2U;
+ break;
+ case CKGR_MOR_MOSCRCF_24_MHz:
+ SystemCoreClock *= 3U;
+ break;
+ default:
+ break;
+ }
+ }
+ break;
+ case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
+ if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
+ SystemCoreClock = CHIP_FREQ_XTAL_32K;
+ } else {
+ SystemCoreClock = CHIP_FREQ_SLCK_RC;
+ }
+ if ((uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
+ SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>
+ CKGR_PLLAR_MULA_Pos) + 1U);
+ }
+ break;
+ default:
+ break;
+ }
+
+ if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
+ SystemCoreClock /= 3U;
+ } else {
+ SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
+ }
+}
+
+/**
+ * Initialize flash.
+ */
+void system_init_flash(uint32_t ul_clk)
+{
+ /* Set FWS for embedded Flash access according to operating frequency */
+ if (ul_clk < CHIP_FREQ_FWS_0) {
+ EFC->EEFC_FMR = EEFC_FMR_FWS(0)|EEFC_FMR_CLOE;
+ } else if (ul_clk < CHIP_FREQ_FWS_1) {
+ EFC->EEFC_FMR = EEFC_FMR_FWS(1)|EEFC_FMR_CLOE;
+ } else if (ul_clk < CHIP_FREQ_FWS_2) {
+ EFC->EEFC_FMR = EEFC_FMR_FWS(2)|EEFC_FMR_CLOE;
+ } else if (ul_clk < CHIP_FREQ_FWS_3) {
+ EFC->EEFC_FMR = EEFC_FMR_FWS(3)|EEFC_FMR_CLOE;
+ } else if (ul_clk < CHIP_FREQ_FWS_4) {
+ EFC->EEFC_FMR = EEFC_FMR_FWS(4)|EEFC_FMR_CLOE;
+ } else {
+ EFC->EEFC_FMR = EEFC_FMR_FWS(5)|EEFC_FMR_CLOE;
+ }
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/source/system_samg55.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,85 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SYSTEM_SAMG55_H_INCLUDED
+#define SYSTEM_SAMG55_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+ /* @endcond */
+
+#include <stdint.h>
+
+ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
+
+ /**
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+ void SystemInit(void);
+
+ /**
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+ void SystemCoreClockUpdate(void);
+
+ /**
+ * Initialize flash.
+ */
+ void system_init_flash(uint32_t dw_clk);
+
+ /* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* SYSTEM_SAMG55_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/compiler.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,1180 @@
+/**
+ * \file
+ *
+ * \brief Commonly used includes, types and macros.
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef UTILS_COMPILER_H
+#define UTILS_COMPILER_H
+
+/**
+ * \defgroup group_sam_utils Compiler abstraction layer and code utilities
+ *
+ * Compiler abstraction layer and code utilities for AT91SAM.
+ * This module provides various abstraction layers and utilities to make code compatible between different compilers.
+ *
+ * \{
+ */
+#include <stddef.h>
+
+#if (defined __ICCARM__)
+# include <intrinsics.h>
+#endif
+
+#include <parts.h>
+#include "preprocessor.h"
+
+#include <io.h>
+
+//_____ D E C L A R A T I O N S ____________________________________________
+
+#ifndef __ASSEMBLY__ // Not defined for assembling.
+
+#include <stdio.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#ifdef __ICCARM__
+/*! \name Compiler Keywords
+ *
+ * Port of some keywords from GCC to IAR Embedded Workbench.
+ */
+//! @{
+#define __asm__ asm
+#define __inline__ inline
+#define __volatile__
+//! @}
+
+#endif
+
+#define FUNC_PTR void *
+/**
+ * \def UNUSED
+ * \brief Marking \a v as a unused parameter or value.
+ */
+#define UNUSED(v) (void)(v)
+
+/**
+ * \def unused
+ * \brief Marking \a v as a unused parameter or value.
+ */
+#define unused(v) do { (void)(v); } while(0)
+
+/**
+ * \def barrier
+ * \brief Memory barrier
+ */
+#define barrier() __DMB()
+
+/**
+ * \brief Emit the compiler pragma \a arg.
+ *
+ * \param arg The pragma directive as it would appear after \e \#pragma
+ * (i.e. not stringified).
+ */
+#define COMPILER_PRAGMA(arg) _Pragma(#arg)
+
+/**
+ * \def COMPILER_PACK_SET(alignment)
+ * \brief Set maximum alignment for subsequent struct and union
+ * definitions to \a alignment.
+ */
+#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))
+
+/**
+ * \def COMPILER_PACK_RESET()
+ * \brief Set default alignment for subsequent struct and union
+ * definitions.
+ */
+#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())
+
+
+/**
+ * \brief Set aligned boundary.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
+#elif (defined __ICCARM__)
+# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)
+#endif
+
+/**
+ * \brief Set word-aligned boundary.
+ */
+#if (defined __GNUC__) || defined(__CC_ARM)
+#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))
+#elif (defined __ICCARM__)
+#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4)
+#endif
+
+/**
+ * \def __always_inline
+ * \brief The function should always be inlined.
+ *
+ * This annotation instructs the compiler to ignore its inlining
+ * heuristics and inline the function no matter how big it thinks it
+ * becomes.
+ */
+#if defined(__CC_ARM)
+# define __always_inline __forceinline
+#elif (defined __GNUC__)
+# define __always_inline inline __attribute__((__always_inline__))
+#elif (defined __ICCARM__)
+# define __always_inline _Pragma("inline=forced")
+#endif
+
+/**
+ * \def __no_inline
+ * \brief The function should not be inlined.
+ *
+ * This annotation instructs the compiler to ignore its inlining
+ * heuristics and not inline the function.
+ */
+#if defined(__CC_ARM)
+# define __no_inline __attribute__((noinline))
+#elif (defined __GNUC__)
+# define __no_inline __attribute__((__noinline__))
+#elif (defined __ICCARM__)
+# define __no_inline _Pragma("inline=never")
+#endif
+
+/*! \brief This macro is used to test fatal errors.
+ *
+ * The macro tests if the expression is false. If it is, a fatal error is
+ * detected and the application hangs up. If TEST_SUITE_DEFINE_ASSERT_MACRO
+ * is defined, a unit test version of the macro is used, to allow execution
+ * of further tests after a false expression.
+ *
+ * \param expr Expression to evaluate and supposed to be nonzero.
+ */
+#if defined(_ASSERT_ENABLE_)
+# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO)
+// Assert() is defined in unit_test/suite.h
+# include "unit_test/suite.h"
+# else
+#undef TEST_SUITE_DEFINE_ASSERT_MACRO
+# define Assert(expr) \
+ {\
+ if (!(expr)) while (true);\
+ }
+# endif
+#else
+# define Assert(expr) ((void) 0)
+#endif
+
+/* Define WEAK attribute */
+#if defined ( __CC_ARM ) /* Keil µVision 4 */
+# define WEAK __attribute__ ((weak))
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
+# define WEAK __weak
+#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */
+# define WEAK __attribute__ ((weak))
+#endif
+
+/* Define NO_INIT attribute */
+#if defined ( __CC_ARM )
+# define NO_INIT __attribute__((zero_init))
+#elif defined ( __ICCARM__ )
+# define NO_INIT __no_init
+#elif defined ( __GNUC__ )
+# define NO_INIT __attribute__((section(".no_init")))
+#endif
+
+/* Define RAMFUNC attribute */
+#if defined ( __CC_ARM ) /* Keil µVision 4 */
+# define RAMFUNC __attribute__ ((section(".ramfunc")))
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
+# define RAMFUNC __ramfunc
+#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */
+# define RAMFUNC __attribute__ ((section(".ramfunc")))
+#endif
+
+/* Define OPTIMIZE_HIGH attribute */
+#if defined ( __CC_ARM ) /* Keil µVision 4 */
+# define OPTIMIZE_HIGH _Pragma("O3")
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
+# define OPTIMIZE_HIGH _Pragma("optimize=high")
+#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */
+# define OPTIMIZE_HIGH __attribute__((optimize(s)))
+#endif
+
+#include "interrupt.h"
+
+/*! \name Usual Types
+ */
+//! @{
+typedef unsigned char Bool; //!< Boolean.
+#ifndef __cplusplus
+#if !defined(__bool_true_false_are_defined)
+typedef unsigned char bool; //!< Boolean.
+#endif
+#endif
+typedef int8_t S8 ; //!< 8-bit signed integer.
+typedef uint8_t U8 ; //!< 8-bit unsigned integer.
+typedef int16_t S16; //!< 16-bit signed integer.
+typedef uint16_t U16; //!< 16-bit unsigned integer.
+typedef uint16_t le16_t;
+typedef uint16_t be16_t;
+typedef int32_t S32; //!< 32-bit signed integer.
+typedef uint32_t U32; //!< 32-bit unsigned integer.
+typedef uint32_t le32_t;
+typedef uint32_t be32_t;
+typedef int64_t S64; //!< 64-bit signed integer.
+typedef uint64_t U64; //!< 64-bit unsigned integer.
+typedef float F32; //!< 32-bit floating-point number.
+typedef double F64; //!< 64-bit floating-point number.
+typedef uint32_t iram_size_t;
+//! @}
+
+
+/*! \name Status Types
+ */
+//! @{
+typedef bool Status_bool_t; //!< Boolean status.
+typedef U8 Status_t; //!< 8-bit-coded status.
+//! @}
+
+
+/*! \name Aliasing Aggregate Types
+ */
+//! @{
+
+//! 16-bit union.
+typedef union {
+ S16 s16 ;
+ U16 u16 ;
+ S8 s8 [2];
+ U8 u8 [2];
+} Union16;
+
+//! 32-bit union.
+typedef union {
+ S32 s32 ;
+ U32 u32 ;
+ S16 s16[2];
+ U16 u16[2];
+ S8 s8 [4];
+ U8 u8 [4];
+} Union32;
+
+//! 64-bit union.
+typedef union {
+ S64 s64 ;
+ U64 u64 ;
+ S32 s32[2];
+ U32 u32[2];
+ S16 s16[4];
+ U16 u16[4];
+ S8 s8 [8];
+ U8 u8 [8];
+} Union64;
+
+//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers.
+typedef union {
+ S64 *s64ptr;
+ U64 *u64ptr;
+ S32 *s32ptr;
+ U32 *u32ptr;
+ S16 *s16ptr;
+ U16 *u16ptr;
+ S8 *s8ptr ;
+ U8 *u8ptr ;
+} UnionPtr;
+
+//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef union {
+ volatile S64 *s64ptr;
+ volatile U64 *u64ptr;
+ volatile S32 *s32ptr;
+ volatile U32 *u32ptr;
+ volatile S16 *s16ptr;
+ volatile U16 *u16ptr;
+ volatile S8 *s8ptr ;
+ volatile U8 *u8ptr ;
+} UnionVPtr;
+
+//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
+typedef union {
+ const S64 *s64ptr;
+ const U64 *u64ptr;
+ const S32 *s32ptr;
+ const U32 *u32ptr;
+ const S16 *s16ptr;
+ const U16 *u16ptr;
+ const S8 *s8ptr ;
+ const U8 *u8ptr ;
+} UnionCPtr;
+
+//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef union {
+ const volatile S64 *s64ptr;
+ const volatile U64 *u64ptr;
+ const volatile S32 *s32ptr;
+ const volatile U32 *u32ptr;
+ const volatile S16 *s16ptr;
+ const volatile U16 *u16ptr;
+ const volatile S8 *s8ptr ;
+ const volatile U8 *u8ptr ;
+} UnionCVPtr;
+
+//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct {
+ S64 *s64ptr;
+ U64 *u64ptr;
+ S32 *s32ptr;
+ U32 *u32ptr;
+ S16 *s16ptr;
+ U16 *u16ptr;
+ S8 *s8ptr ;
+ U8 *u8ptr ;
+} StructPtr;
+
+//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct {
+ volatile S64 *s64ptr;
+ volatile U64 *u64ptr;
+ volatile S32 *s32ptr;
+ volatile U32 *u32ptr;
+ volatile S16 *s16ptr;
+ volatile U16 *u16ptr;
+ volatile S8 *s8ptr ;
+ volatile U8 *u8ptr ;
+} StructVPtr;
+
+//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct {
+ const S64 *s64ptr;
+ const U64 *u64ptr;
+ const S32 *s32ptr;
+ const U32 *u32ptr;
+ const S16 *s16ptr;
+ const U16 *u16ptr;
+ const S8 *s8ptr ;
+ const U8 *u8ptr ;
+} StructCPtr;
+
+//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct {
+ const volatile S64 *s64ptr;
+ const volatile U64 *u64ptr;
+ const volatile S32 *s32ptr;
+ const volatile U32 *u32ptr;
+ const volatile S16 *s16ptr;
+ const volatile U16 *u16ptr;
+ const volatile S8 *s8ptr ;
+ const volatile U8 *u8ptr ;
+} StructCVPtr;
+
+//! @}
+
+#endif // #ifndef __ASSEMBLY__
+
+/*! \name Usual Constants
+ */
+//! @{
+#define DISABLE 0
+#define ENABLE 1
+#ifndef __cplusplus
+#if !defined(__bool_true_false_are_defined)
+#define false 0
+#define true 1
+#endif
+#endif
+#define PASS 0
+#define FAIL 1
+#define LOW 0
+#define HIGH 1
+//! @}
+
+
+#ifndef __ASSEMBLY__ // not for assembling.
+
+//! \name Optimization Control
+//@{
+
+/**
+ * \def likely(exp)
+ * \brief The expression \a exp is likely to be true
+ */
+#ifndef likely
+# define likely(exp) (exp)
+#endif
+
+/**
+ * \def unlikely(exp)
+ * \brief The expression \a exp is unlikely to be true
+ */
+#ifndef unlikely
+# define unlikely(exp) (exp)
+#endif
+
+/**
+ * \def is_constant(exp)
+ * \brief Determine if an expression evaluates to a constant value.
+ *
+ * \param exp Any expression
+ *
+ * \return true if \a exp is constant, false otherwise.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+# define is_constant(exp) __builtin_constant_p(exp)
+#else
+# define is_constant(exp) (0)
+#endif
+
+//! @}
+
+/*! \name Bit-Field Handling
+ */
+//! @{
+
+/*! \brief Reads the bits of a value specified by a given bit-mask.
+ *
+ * \param value Value to read bits from.
+ * \param mask Bit-mask indicating bits to read.
+ *
+ * \return Read bits.
+ */
+#define Rd_bits( value, mask) ((value) & (mask))
+
+/*! \brief Writes the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue C lvalue to write bits to.
+ * \param mask Bit-mask indicating bits to write.
+ * \param bits Bits to write.
+ *
+ * \return Resulting value with written bits.
+ */
+#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\
+ ((bits ) & (mask)))
+
+/*! \brief Tests the bits of a value specified by a given bit-mask.
+ *
+ * \param value Value of which to test bits.
+ * \param mask Bit-mask indicating bits to test.
+ *
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.
+ */
+#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0)
+
+/*! \brief Clears the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue C lvalue of which to clear bits.
+ * \param mask Bit-mask indicating bits to clear.
+ *
+ * \return Resulting value with cleared bits.
+ */
+#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask))
+
+/*! \brief Sets the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue C lvalue of which to set bits.
+ * \param mask Bit-mask indicating bits to set.
+ *
+ * \return Resulting value with set bits.
+ */
+#define Set_bits(lvalue, mask) ((lvalue) |= (mask))
+
+/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue C lvalue of which to toggle bits.
+ * \param mask Bit-mask indicating bits to toggle.
+ *
+ * \return Resulting value with toggled bits.
+ */
+#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask))
+
+/*! \brief Reads the bit-field of a value specified by a given bit-mask.
+ *
+ * \param value Value to read a bit-field from.
+ * \param mask Bit-mask indicating the bit-field to read.
+ *
+ * \return Read bit-field.
+ */
+#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask))
+
+/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue C lvalue to write a bit-field to.
+ * \param mask Bit-mask indicating the bit-field to write.
+ * \param bitfield Bit-field to write.
+ *
+ * \return Resulting value with written bit-field.
+ */
+#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask)))
+
+//! @}
+
+
+/*! \name Zero-Bit Counting
+ *
+ * Under GCC, __builtin_clz and __builtin_ctz behave like macros when
+ * applied to constant expressions (values known at compile time), so they are
+ * more optimized than the use of the corresponding assembly instructions and
+ * they can be used as constant expressions e.g. to initialize objects having
+ * static storage duration, and like the corresponding assembly instructions
+ * when applied to non-constant expressions (values unknown at compile time), so
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz
+ * ensure a possible and optimized behavior for both constant and non-constant
+ * expressions.
+ */
+//! @{
+
+/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param u Value of which to count the leading zero bits.
+ *
+ * \return The count of leading zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+# define clz(u) __builtin_clz(u)
+#elif (defined __ICCARM__)
+# define clz(u) __CLZ(u)
+#else
+# define clz(u) (((u) == 0) ? 32 : \
+ ((u) & (1ul << 31)) ? 0 : \
+ ((u) & (1ul << 30)) ? 1 : \
+ ((u) & (1ul << 29)) ? 2 : \
+ ((u) & (1ul << 28)) ? 3 : \
+ ((u) & (1ul << 27)) ? 4 : \
+ ((u) & (1ul << 26)) ? 5 : \
+ ((u) & (1ul << 25)) ? 6 : \
+ ((u) & (1ul << 24)) ? 7 : \
+ ((u) & (1ul << 23)) ? 8 : \
+ ((u) & (1ul << 22)) ? 9 : \
+ ((u) & (1ul << 21)) ? 10 : \
+ ((u) & (1ul << 20)) ? 11 : \
+ ((u) & (1ul << 19)) ? 12 : \
+ ((u) & (1ul << 18)) ? 13 : \
+ ((u) & (1ul << 17)) ? 14 : \
+ ((u) & (1ul << 16)) ? 15 : \
+ ((u) & (1ul << 15)) ? 16 : \
+ ((u) & (1ul << 14)) ? 17 : \
+ ((u) & (1ul << 13)) ? 18 : \
+ ((u) & (1ul << 12)) ? 19 : \
+ ((u) & (1ul << 11)) ? 20 : \
+ ((u) & (1ul << 10)) ? 21 : \
+ ((u) & (1ul << 9)) ? 22 : \
+ ((u) & (1ul << 8)) ? 23 : \
+ ((u) & (1ul << 7)) ? 24 : \
+ ((u) & (1ul << 6)) ? 25 : \
+ ((u) & (1ul << 5)) ? 26 : \
+ ((u) & (1ul << 4)) ? 27 : \
+ ((u) & (1ul << 3)) ? 28 : \
+ ((u) & (1ul << 2)) ? 29 : \
+ ((u) & (1ul << 1)) ? 30 : \
+ 31)
+#endif
+
+/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param u Value of which to count the trailing zero bits.
+ *
+ * \return The count of trailing zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+# define ctz(u) __builtin_ctz(u)
+#else
+# define ctz(u) ((u) & (1ul << 0) ? 0 : \
+ (u) & (1ul << 1) ? 1 : \
+ (u) & (1ul << 2) ? 2 : \
+ (u) & (1ul << 3) ? 3 : \
+ (u) & (1ul << 4) ? 4 : \
+ (u) & (1ul << 5) ? 5 : \
+ (u) & (1ul << 6) ? 6 : \
+ (u) & (1ul << 7) ? 7 : \
+ (u) & (1ul << 8) ? 8 : \
+ (u) & (1ul << 9) ? 9 : \
+ (u) & (1ul << 10) ? 10 : \
+ (u) & (1ul << 11) ? 11 : \
+ (u) & (1ul << 12) ? 12 : \
+ (u) & (1ul << 13) ? 13 : \
+ (u) & (1ul << 14) ? 14 : \
+ (u) & (1ul << 15) ? 15 : \
+ (u) & (1ul << 16) ? 16 : \
+ (u) & (1ul << 17) ? 17 : \
+ (u) & (1ul << 18) ? 18 : \
+ (u) & (1ul << 19) ? 19 : \
+ (u) & (1ul << 20) ? 20 : \
+ (u) & (1ul << 21) ? 21 : \
+ (u) & (1ul << 22) ? 22 : \
+ (u) & (1ul << 23) ? 23 : \
+ (u) & (1ul << 24) ? 24 : \
+ (u) & (1ul << 25) ? 25 : \
+ (u) & (1ul << 26) ? 26 : \
+ (u) & (1ul << 27) ? 27 : \
+ (u) & (1ul << 28) ? 28 : \
+ (u) & (1ul << 29) ? 29 : \
+ (u) & (1ul << 30) ? 30 : \
+ (u) & (1ul << 31) ? 31 : \
+ 32)
+#endif
+
+//! @}
+
+
+/*! \name Bit Reversing
+ */
+//! @{
+
+/*! \brief Reverses the bits of \a u8.
+ *
+ * \param u8 U8 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u8 with reversed bits.
+ */
+#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24))
+
+/*! \brief Reverses the bits of \a u16.
+ *
+ * \param u16 U16 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u16 with reversed bits.
+ */
+#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16))
+
+/*! \brief Reverses the bits of \a u32.
+ *
+ * \param u32 U32 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u32 with reversed bits.
+ */
+#define bit_reverse32(u32) __RBIT(u32)
+
+/*! \brief Reverses the bits of \a u64.
+ *
+ * \param u64 U64 of which to reverse the bits.
+ *
+ * \return Value resulting from \a u64 with reversed bits.
+ */
+#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\
+ ((U64)bit_reverse32((U64)(u64)) << 32)))
+
+//! @}
+
+
+/*! \name Alignment
+ */
+//! @{
+
+/*! \brief Tests alignment of the number \a val with the \a n boundary.
+ *
+ * \param val Input value.
+ * \param n Boundary.
+ *
+ * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.
+ */
+#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) )
+
+/*! \brief Gets alignment of the number \a val with respect to the \a n boundary.
+ *
+ * \param val Input value.
+ * \param n Boundary.
+ *
+ * \return Alignment of the number \a val with respect to the \a n boundary.
+ */
+#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) )
+
+/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.
+ *
+ * \param lval Input/output lvalue.
+ * \param n Boundary.
+ * \param alg Alignment.
+ *
+ * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.
+ */
+#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) )
+
+/*! \brief Aligns the number \a val with the upper \a n boundary.
+ *
+ * \param val Input value.
+ * \param n Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the upper \a n boundary.
+ */
+#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1))
+
+/*! \brief Aligns the number \a val with the lower \a n boundary.
+ *
+ * \param val Input value.
+ * \param n Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the lower \a n boundary.
+ */
+#define Align_down(val, n ) ( (val) & ~((n) - 1))
+
+//! @}
+
+
+/*! \name Mathematics
+ *
+ * The same considerations as for clz and ctz apply here but GCC does not
+ * provide built-in functions to access the assembly instructions abs, min and
+ * max and it does not produce them by itself in most cases, so two sets of
+ * macros are defined here:
+ * - Abs, Min and Max to apply to constant expressions (values known at
+ * compile time);
+ * - abs, min and max to apply to non-constant expressions (values unknown at
+ * compile time), abs is found in stdlib.h.
+ */
+//! @{
+
+/*! \brief Takes the absolute value of \a a.
+ *
+ * \param a Input value.
+ *
+ * \return Absolute value of \a a.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Abs(a) (((a) < 0 ) ? -(a) : (a))
+
+/*! \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Min(a, b) (((a) < (b)) ? (a) : (b))
+
+/*! \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Max(a, b) (((a) > (b)) ? (a) : (b))
+
+// abs() is already defined by stdlib.h
+
+/*! \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define min(a, b) Min(a, b)
+
+/*! \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define max(a, b) Max(a, b)
+
+//! @}
+
+
+/*! \brief Calls the routine at address \a addr.
+ *
+ * It generates a long call opcode.
+ *
+ * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if
+ * it is invoked from the CPU supervisor mode.
+ *
+ * \param addr Address of the routine to call.
+ *
+ * \note It may be used as a long jump opcode in some special cases.
+ */
+#define Long_call(addr) ((*(void (*)(void))(addr))())
+
+
+/*! \name MCU Endianism Handling
+ * ARM is MCU little endianism.
+ */
+//! @{
+#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.
+#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.
+
+#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.
+#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.
+#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.
+#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.
+#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.
+#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.
+#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.
+#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.
+#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.
+#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.
+
+#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.
+#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.
+#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64.
+#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64.
+#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64.
+#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64.
+#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.
+#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.
+#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.
+#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.
+#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64.
+#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64.
+#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64.
+#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64.
+#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64.
+#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64.
+#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64.
+#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64.
+#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.
+#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.
+#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.
+#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.
+#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.
+#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.
+#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.
+#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.
+
+#define BE16(x) Swap16(x)
+#define LE16(x) (x)
+
+#define le16_to_cpu(x) (x)
+#define cpu_to_le16(x) (x)
+#define LE16_TO_CPU(x) (x)
+#define CPU_TO_LE16(x) (x)
+
+#define be16_to_cpu(x) Swap16(x)
+#define cpu_to_be16(x) Swap16(x)
+#define BE16_TO_CPU(x) Swap16(x)
+#define CPU_TO_BE16(x) Swap16(x)
+
+#define le32_to_cpu(x) (x)
+#define cpu_to_le32(x) (x)
+#define LE32_TO_CPU(x) (x)
+#define CPU_TO_LE32(x) (x)
+
+#define be32_to_cpu(x) swap32(x)
+#define cpu_to_be32(x) swap32(x)
+#define BE32_TO_CPU(x) swap32(x)
+#define CPU_TO_BE32(x) swap32(x)
+//! @}
+
+
+/*! \name Endianism Conversion
+ *
+ * The same considerations as for clz and ctz apply here but GCC's
+ * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when
+ * applied to constant expressions, so two sets of macros are defined here:
+ * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known
+ * at compile time);
+ * - swap16, swap32 and swap64 to apply to non-constant expressions (values
+ * unknown at compile time).
+ */
+//! @{
+
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\
+ ((U16)(u16) << 8)))
+
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\
+ ((U32)Swap16((U32)(u32)) << 16)))
+
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\
+ ((U64)Swap32((U64)(u64)) << 32)))
+
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define swap16(u16) Swap16(u16)
+
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if (defined __GNUC__)
+# define swap32(u32) ((U32)__builtin_bswap32((U32)(u32)))
+#else
+# define swap32(u32) Swap32(u32)
+#endif
+
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if (defined __GNUC__)
+# define swap64(u64) ((U64)__builtin_bswap64((U64)(u64)))
+#else
+# define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\
+ ((U64)swap32((U64)(u64)) << 32)))
+#endif
+
+//! @}
+
+
+/*! \name Target Abstraction
+ */
+//! @{
+
+#define _GLOBEXT_ extern //!< extern storage-class specifier.
+#define _CONST_TYPE_ const //!< const type qualifier.
+#define _MEM_TYPE_SLOW_ //!< Slow memory type.
+#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type.
+#define _MEM_TYPE_FAST_ //!< Fast memory type.
+
+typedef U8 Byte; //!< 8-bit unsigned integer.
+
+#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM.
+#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM.
+#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM.
+#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM.
+
+#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.
+#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.
+#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.
+#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.
+#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.
+#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.
+#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.
+#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.
+
+//! @}
+
+/**
+ * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using
+ * integer arithmetic.
+ *
+ * \param a An integer
+ * \param b Another integer
+ *
+ * \return (\a a / \a b) rounded up to the nearest integer.
+ */
+#define div_ceil(a, b) (((a) + (b) - 1) / (b))
+
+#endif // #ifndef __ASSEMBLY__
+
+
+#if defined(__ICCARM__)
+#define SHORTENUM __packed
+#elif defined(__GNUC__)
+#define SHORTENUM __attribute__((packed))
+#endif
+
+/* No operation */
+#if defined(__ICCARM__)
+#define nop() __no_operation()
+#elif defined(__GNUC__)
+#define nop() (__NOP())
+#endif
+
+#define FLASH_DECLARE(x) const x
+#define FLASH_EXTERN(x) extern const x
+#define PGM_READ_BYTE(x) *(x)
+#define PGM_READ_WORD(x) *(x)
+#define PGM_READ_DWORD(x) *(x)
+#define MEMCPY_ENDIAN memcpy
+#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len))
+
+/*Defines the Flash Storage for the request and response of MAC*/
+#define CMD_ID_OCTET (0)
+
+/* Converting of values from CPU endian to little endian. */
+#define CPU_ENDIAN_TO_LE16(x) (x)
+#define CPU_ENDIAN_TO_LE32(x) (x)
+#define CPU_ENDIAN_TO_LE64(x) (x)
+
+/* Converting of values from little endian to CPU endian. */
+#define LE16_TO_CPU_ENDIAN(x) (x)
+#define LE32_TO_CPU_ENDIAN(x) (x)
+#define LE64_TO_CPU_ENDIAN(x) (x)
+
+/* Converting of constants from little endian to CPU endian. */
+#define CLE16_TO_CPU_ENDIAN(x) (x)
+#define CLE32_TO_CPU_ENDIAN(x) (x)
+#define CLE64_TO_CPU_ENDIAN(x) (x)
+
+/* Converting of constants from CPU endian to little endian. */
+#define CCPU_ENDIAN_TO_LE16(x) (x)
+#define CCPU_ENDIAN_TO_LE32(x) (x)
+#define CCPU_ENDIAN_TO_LE64(x) (x)
+
+#define ADDR_COPY_DST_SRC_16(dst, src) ((dst) = (src))
+#define ADDR_COPY_DST_SRC_64(dst, src) ((dst) = (src))
+
+/**
+ * @brief Converts a 64-Bit value into a 8 Byte array
+ *
+ * @param[in] value 64-Bit value
+ * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value
+ * @ingroup apiPalApi
+ */
+static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data)
+{
+ uint8_t val_index = 0;
+
+ while (val_index < 8) {
+ data[val_index++] = value & 0xFF;
+ value = value >> 8;
+ }
+}
+
+/**
+ * @brief Converts a 16-Bit value into a 2 Byte array
+ *
+ * @param[in] value 16-Bit value
+ * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value
+ * @ingroup apiPalApi
+ */
+static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data)
+{
+ data[0] = value & 0xFF;
+ data[1] = (value >> 8) & 0xFF;
+}
+
+/* Converts a 16-Bit value into a 2 Byte array */
+static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data)
+{
+ data[0] = value & 0xFF;
+ data[1] = (value >> 8) & 0xFF;
+}
+
+/* Converts a 16-Bit value into a 2 Byte array */
+static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data)
+{
+ data[0] = value & 0xFF;
+ data[1] = (value >> 8) & 0xFF;
+}
+
+/*
+ * @brief Converts a 2 Byte array into a 16-Bit value
+ *
+ * @param data Specifies the pointer to the 2 Byte array
+ *
+ * @return 16-Bit value
+ * @ingroup apiPalApi
+ */
+static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data)
+{
+ return (data[0] | ((uint16_t)data[1] << 8));
+}
+
+/* Converts a 8 Byte array into a 32-Bit value */
+static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data)
+{
+ union {
+ uint32_t u32;
+ uint8_t u8[8];
+ } long_addr;
+ uint8_t index;
+ for (index = 0; index < 4; index++) {
+ long_addr.u8[index] = *data++;
+ }
+ return long_addr.u32;
+}
+
+/**
+ * @brief Converts a 8 Byte array into a 64-Bit value
+ *
+ * @param data Specifies the pointer to the 8 Byte array
+ *
+ * @return 64-Bit value
+ * @ingroup apiPalApi
+ */
+static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data)
+{
+ union {
+ uint64_t u64;
+ uint8_t u8[8];
+ } long_addr;
+
+ uint8_t val_index;
+
+ for (val_index = 0; val_index < 8; val_index++) {
+ long_addr.u8[val_index] = *data++;
+ }
+
+ return long_addr.u64;
+}
+/**
+ * \}
+ */
+
+#endif /* UTILS_COMPILER_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/header_files/io.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,157 @@ +/** + * \file + * + * \brief Arch file for SAM. + * + * This file defines common SAM series. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _SAM_IO_ +#define _SAM_IO_ + +/* SAM3 family */ + +/* SAM3S series */ +#if (SAM3S) +# if (SAM3S8 || SAM3SD8) +# include "sam3s8.h" +# else +# include "sam3s.h" +# endif +#endif + +/* SAM3U series */ +#if (SAM3U) +# include "sam3u.h" +#endif + +/* SAM3N series */ +#if (SAM3N) +# include "sam3n.h" +#endif + +/* SAM3XA series */ +#if (SAM3XA) +# include "sam3xa.h" +#endif + +/* SAM4S series */ +#if (SAM4S) +# include "sam4s.h" +#endif + +/* SAM4L series */ +#if (SAM4L) +# include "sam4l.h" +#endif + +/* SAM4E series */ +#if (SAM4E) +# include "sam4e.h" +#endif + +/* SAM4N series */ +#if (SAM4N) +# include "sam4n.h" +#endif + +/* SAM4C series */ +#if (SAM4C) +# include "sam4c.h" +#endif + +/* SAM4CM series */ +#if (SAM4CM) +# if (SAM4CMP32 || SAM4CMS32) +# include "sam4cm32.h" +# else +# include "sam4cm.h" +# endif +#endif + +/* SAM4CP series */ +#if (SAM4CP) +# include "sam4cp.h" +#endif + +/* SAMG51 series */ +#if (SAMG51) +# include "samg51.h" +#endif + +/* SAMG53 series */ +#if (SAMG53) +# include "samg53.h" +#endif + +/* SAMG54 series */ +#if (SAMG54) +# include "samg54.h" +#endif + +/* SAMG55 series */ +#if (SAMG55) +# include "samg55.h" +#endif + +/* SAMV71 series */ +#if (SAMV71) +# include "samv71.h" +#endif + +/* SAMV70 series */ +#if (SAMV70) +# include "samv70.h" +#endif + +/* SAME70 series */ +#if (SAME70) +# include "same70.h" +#endif + +/* SAMS70 series */ +#if (SAMS70) +# include "sams70.h" +#endif + +#endif /* _SAM_IO_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/mrepeat.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,339 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor macro repeating utils.
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _MREPEAT_H_
+#define _MREPEAT_H_
+
+/**
+ * \defgroup group_sam_utils_mrepeat Preprocessor - Macro Repeat
+ *
+ * \ingroup group_sam_utils
+ *
+ * \{
+ */
+
+#include "preprocessor.h"
+
+
+//! Maximal number of repetitions supported by MREPEAT.
+#define MREPEAT_LIMIT 256
+
+/*! \brief Macro repeat.
+ *
+ * This macro represents a horizontal repetition construct.
+ *
+ * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT.
+ * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with
+ * the current repetition number and the auxiliary data argument.
+ * \param data Auxiliary data passed to macro.
+ *
+ * \return <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>
+ */
+#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data)
+
+#define MREPEAT0( macro, data)
+#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data)
+#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data)
+#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data)
+#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data)
+#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data)
+#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data)
+#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data)
+#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data)
+#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data)
+#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data)
+#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data)
+#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data)
+#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data)
+#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data)
+#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data)
+#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data)
+#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data)
+#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data)
+#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data)
+#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data)
+#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data)
+#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data)
+#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data)
+#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data)
+#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data)
+#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data)
+#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data)
+#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data)
+#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data)
+#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data)
+#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data)
+#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data)
+#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data)
+#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data)
+#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data)
+#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data)
+#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data)
+#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data)
+#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data)
+#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data)
+#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data)
+#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data)
+#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data)
+#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data)
+#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data)
+#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data)
+#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data)
+#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data)
+#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data)
+#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data)
+#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data)
+#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data)
+#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data)
+#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data)
+#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data)
+#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data)
+#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data)
+#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data)
+#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data)
+#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data)
+#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data)
+#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data)
+#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data)
+#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data)
+#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data)
+#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data)
+#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data)
+#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data)
+#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data)
+#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data)
+#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data)
+#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data)
+#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data)
+#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data)
+#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data)
+#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data)
+#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data)
+#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data)
+#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data)
+#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data)
+#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data)
+#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data)
+#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data)
+#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data)
+#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data)
+#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data)
+#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data)
+#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data)
+#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data)
+#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data)
+#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data)
+#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data)
+#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data)
+#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data)
+#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data)
+#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data)
+#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data)
+#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data)
+#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data)
+#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data)
+#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data)
+#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data)
+#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data)
+#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data)
+#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data)
+#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data)
+#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data)
+#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data)
+#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data)
+#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data)
+#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data)
+#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data)
+#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data)
+#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data)
+#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data)
+#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data)
+#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data)
+#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data)
+#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data)
+#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data)
+#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data)
+#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data)
+#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data)
+#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data)
+#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data)
+#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data)
+#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data)
+#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data)
+#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data)
+#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data)
+#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data)
+#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data)
+#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data)
+#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data)
+#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data)
+#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data)
+#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data)
+#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data)
+#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data)
+#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data)
+#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data)
+#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data)
+#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data)
+#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data)
+#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data)
+#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data)
+#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data)
+#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data)
+#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data)
+#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data)
+#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data)
+#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data)
+#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data)
+#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data)
+#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data)
+#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data)
+#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data)
+#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data)
+#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data)
+#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data)
+#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data)
+#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data)
+#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data)
+#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data)
+#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data)
+#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data)
+#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data)
+#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data)
+#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data)
+#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data)
+#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data)
+#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data)
+#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data)
+#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data)
+#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data)
+#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data)
+#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data)
+#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data)
+#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data)
+#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data)
+#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data)
+#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data)
+#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data)
+#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data)
+#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data)
+#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data)
+#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data)
+#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data)
+#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data)
+#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data)
+#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data)
+#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data)
+#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data)
+#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data)
+#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data)
+#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data)
+#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data)
+#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data)
+#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data)
+#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data)
+#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data)
+#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data)
+#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data)
+#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data)
+#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data)
+#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data)
+#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data)
+#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data)
+#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data)
+#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data)
+#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data)
+#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data)
+#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data)
+#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data)
+#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data)
+#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data)
+#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data)
+#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data)
+#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data)
+#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data)
+#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data)
+#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data)
+#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data)
+#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data)
+#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data)
+#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data)
+#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data)
+#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data)
+#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data)
+#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data)
+#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data)
+#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data)
+#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data)
+#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data)
+#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data)
+#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data)
+#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data)
+#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data)
+#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data)
+#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data)
+#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data)
+#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data)
+#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data)
+#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data)
+#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data)
+#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data)
+#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data)
+#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data)
+#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data)
+#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data)
+#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data)
+#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data)
+#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data)
+#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data)
+#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data)
+#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data)
+
+/**
+ * \}
+ */
+
+#endif // _MREPEAT_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/preprocessor.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,55 @@ +/** + * \file + * + * \brief Preprocessor utils. + * + * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef _PREPROCESSOR_H_ +#define _PREPROCESSOR_H_ + +#include "tpaste.h" +#include "stringz.h" +#include "mrepeat.h" + + +#endif // _PREPROCESSOR_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/stringz.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,85 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor stringizing utils.
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _STRINGZ_H_
+#define _STRINGZ_H_
+
+/**
+ * \defgroup group_sam_utils_stringz Preprocessor - Stringize
+ *
+ * \ingroup group_sam_utils
+ *
+ * \{
+ */
+
+/*! \brief Stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be \#defined.
+ *
+ * May be used only within macros with the token passed as an argument if the token is \#defined.
+ *
+ * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)
+ * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to
+ * writing "A0".
+ */
+#define STRINGZ(x) #x
+
+/*! \brief Absolute stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be \#defined.
+ *
+ * No restriction of use if the token is \#defined.
+ *
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is
+ * equivalent to writing "A0".
+ */
+#define ASTRINGZ(x) STRINGZ(x)
+
+/**
+ * \}
+ */
+
+#endif // _STRINGZ_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/preprocessor/tpaste.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,105 @@
+/**
+ * \file
+ *
+ * \brief Preprocessor token pasting utils.
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _TPASTE_H_
+#define _TPASTE_H_
+
+/**
+ * \defgroup group_sam_utils_tpaste Preprocessor - Token Paste
+ *
+ * \ingroup group_sam_utils
+ *
+ * \{
+ */
+
+/*! \name Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.
+ *
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is
+ * equivalent to writing U32.
+ */
+//! @{
+#define TPASTE2( a, b) a##b
+#define TPASTE3( a, b, c) a##b##c
+#define TPASTE4( a, b, c, d) a##b##c##d
+#define TPASTE5( a, b, c, d, e) a##b##c##d##e
+#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f
+#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g
+#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h
+#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j
+//! @}
+
+/*! \name Absolute Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * No restriction of use if the tokens are \#defined.
+ *
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined
+ * as 32 is equivalent to writing U32.
+ */
+//! @{
+#define ATPASTE2( a, b) TPASTE2( a, b)
+#define ATPASTE3( a, b, c) TPASTE3( a, b, c)
+#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d)
+#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e)
+#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f)
+#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g)
+#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h)
+#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i)
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j)
+//! @}
+
+/**
+ * \}
+ */
+
+#endif // _TPASTE_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM4/utils/status_codes.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,113 @@
+/**
+ * \file
+ *
+ * \brief Status code definitions.
+ *
+ * This file defines various status codes returned by functions,
+ * indicating success or failure as well as what kind of failure.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef STATUS_CODES_H_INCLUDED
+#define STATUS_CODES_H_INCLUDED
+
+/* Note: this is a local workaround to avoid a pre-processor clash due to the
+ * lwIP macro ERR_TIMEOUT. */
+#if defined(__LWIP_ERR_H__) && defined(ERR_TIMEOUT)
+#if (ERR_TIMEOUT != -3)
+
+/* Internal check to make sure that the later restore of lwIP's ERR_TIMEOUT
+ * macro is set to the correct value. Note that it is highly improbable that
+ * this value ever changes in lwIP. */
+#error ASF developers: check lwip err.h new value for ERR_TIMEOUT
+#endif
+#undef ERR_TIMEOUT
+#endif
+
+/**
+ * Status code that may be returned by shell commands and protocol
+ * implementations.
+ *
+ * \note Any change to these status codes and the corresponding
+ * message strings is strictly forbidden. New codes can be added,
+ * however, but make sure that any message string tables are updated
+ * at the same time.
+ */
+enum status_code {
+ STATUS_OK = 0, //!< Success
+ STATUS_ERR_BUSY = 0x19,
+ STATUS_ERR_DENIED = 0x1C,
+ STATUS_ERR_TIMEOUT = 0x12,
+ ERR_IO_ERROR = -1, //!< I/O error
+ ERR_FLUSHED = -2, //!< Request flushed from queue
+ ERR_TIMEOUT = -3, //!< Operation timed out
+ ERR_BAD_DATA = -4, //!< Data integrity check failed
+ ERR_PROTOCOL = -5, //!< Protocol error
+ ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device
+ ERR_NO_MEMORY = -7, //!< Insufficient memory
+ ERR_INVALID_ARG = -8, //!< Invalid argument
+ ERR_BAD_ADDRESS = -9, //!< Bad address
+ ERR_BUSY = -10, //!< Resource is busy
+ ERR_BAD_FORMAT = -11, //!< Data format not recognized
+ ERR_NO_TIMER = -12, //!< No timer available
+ ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running
+ ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running
+ ERR_ABORTED = -15, //!< Operation aborted by user
+ /**
+ * \brief Operation in progress
+ *
+ * This status code is for driver-internal use when an operation
+ * is currently being performed.
+ *
+ * \note Drivers should never return this status code to any
+ * callers. It is strictly for internal use.
+ */
+ OPERATION_IN_PROGRESS = -128,
+};
+
+typedef enum status_code status_code_t;
+
+#if defined(__LWIP_ERR_H__)
+#define ERR_TIMEOUT -3
+#endif
+
+#endif /* STATUS_CODES_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/PortNames.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,32 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB,
+ PortMax
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PeripheralNames.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,58 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)0x4000C200U,
+ UART_1 = (int)0x40020200U,
+ UART_2 = (int)0x40024200U,
+ UART_3 = (int)0x40018200U,
+ UART_4 = (int)0x4001C200U,
+ UART_5 = (int)0x40008200U,
+ UART_6 = (int)0x40040200U,
+ UART_7 = (int)0x40034200U,
+} UARTName;
+
+typedef enum {
+ ADC_0 = 0,
+ ADC_1,
+ ADC_2,
+ ADC_3,
+ ADC_4,
+ ADC_5,
+ ADC_6,
+ ADC_7,
+} ADCName;
+
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_7
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PeripheralPins.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,195 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+ /* Not connected */
+ {PA17, ADC_0, NC}, /*NC in mux posiotn since it is a extra function and doesnt have a name*/
+ {PA18, ADC_1, NC}, /*Pin is multiplexed to the extra function once the corresponding ADC channel is enabled*/
+ {PA19, ADC_2, NC},
+ {PA20, ADC_3, NC},
+ {PB00, ADC_4, NC},
+ {PB01, ADC_5, NC},
+ {PB02, ADC_6, NC},
+ {PB03, ADC_7, NC},
+ /* Not connected */
+ {NC , NC , NC}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+ {PA03, UART_3, 0},
+ {PA06, UART_2, 0},
+ {PA10, UART_0, 0},
+ {PA13, UART_5, 0},
+ {PA28, UART_7, 1},
+ {PB00, UART_6, 1},
+ {PB03, UART_1, 0},
+ {PB08, UART_4, 0},
+ {PB10, UART_4, 0},
+ {PB10, UART_6, 1},
+ /* Not connected */
+ {NC , NC , NC}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA04, UART_3, 0},
+ {PA05, UART_2, 0},
+ {PA09, UART_0, 0},
+ {PA12, UART_5, 0},
+ {PA27, UART_7, 1},
+ {PB01, UART_6, 1},
+ {PB02, UART_1, 0},
+ {PB09, UART_4, 0},
+ {PB11, UART_4, 0},
+ {PB11, UART_6, 1},
+ /* Not connected */
+ {NC , NC , NC}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+ {PA11, UART_5, 0},
+ {PA16, UART_2, 0},
+ {PA25, UART_0, 0},
+ {PA28, UART_1, 0},
+ {PA30, UART_7, 1},
+ {PB08, UART_4, 1},
+ {PB14, UART_3, 0},
+ {PB14, UART_6, 1},
+ /* Not connected */
+ {NC , NC , NC}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+ {PA15, UART_2, 0},
+ {PA26, UART_0, 0},
+ {PA29, UART_1, 0},
+ {PA31, UART_7, 1},
+ {PB02, UART_5, 1},
+ {PB09, UART_4, 1},
+ {PB15, UART_3, 0},
+ {PB15, UART_6, 1},
+ /* Not connected */
+ {NC , NC , NC}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+ {PB00, (int)SPI0, 0},
+ {PA27, (int)SPI1, 0},
+ {PA15, (int)SPI2, 1},
+ {PA24, (int)SPI2, 1},
+ {PB13, (int)SPI3, 0},
+ {PB01, (int)SPI4, 0},
+ {PA14, (int)SPI5, 0},
+ {PB13, (int)SPI6, 1},
+ {PA29, (int)SPI7, 1},
+ /* Not connected */
+ {NC , (int)NC , NC}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA10, (int)SPI0, 0},
+ {PB03, (int)SPI1, 0},
+ {PA06, (int)SPI2, 0},
+ {PA03, (int)SPI3, 0},
+ {PB08, (int)SPI4, 0},
+ {PB10, (int)SPI4, 0},
+ {PA13, (int)SPI5, 0},
+ {PB00, (int)SPI6, 1},
+ {PB10, (int)SPI6, 1},
+ {PA28, (int)SPI7, 1},
+ /* Not connected */
+ {NC , (int)NC , NC}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA09, (int)SPI0, 0},
+ {PB02, (int)SPI1, 0},
+ {PA05, (int)SPI2, 0},
+ {PA04, (int)SPI3, 0},
+ {PB09, (int)SPI4, 0},
+ {PB11, (int)SPI4, 0},
+ {PA12, (int)SPI5, 0},
+ {PB01, (int)SPI6, 1},
+ {PB11, (int)SPI6, 1},
+ {PA27, (int)SPI7, 1},
+ /* Not connected */
+ {NC , (int)NC , NC}
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+ {PA10, (int)TWI0, 0},
+ {PB03, (int)TWI1, 0},
+ {PA06, (int)TWI2, 0},
+ {PA03, (int)TWI3, 0},
+ {PB08, (int)TWI4, 0},
+ {PB10, (int)TWI4, 0},
+ {PB10, (int)TWI6, 1},
+ {PA13, (int)TWI5, 0},
+ {PB00, (int)TWI6, 1},
+ {PB10, (int)TWI6, 1},
+ {PA28, (int)TWI7, 1},
+ /* Not connected */
+ {NC , NC , NC}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA09, (int)TWI0, 0},
+ {PB02, (int)TWI1, 0},
+ {PA05, (int)TWI2, 0},
+ {PA04, (int)TWI3, 0},
+ {PB09, (int)TWI4, 0},
+ {PB11, (int)TWI4, 0},
+ {PA12, (int)TWI5, 0},
+ {PB01, (int)TWI6, 1},
+ {PB11, (int)TWI6, 1},
+ {PA27, (int)TWI7, 1},
+ /* Not connected */
+ {NC , NC , NC}
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+ {PA00, (int)TC0, 1},
+ {PA23, (int)TC0, 1},
+ {PA21, (int)TC0, 0},
+ {PA01, (int)TC0, 1},
+ {PA16, (int)TC0, 1},
+ {PA22, (int)TC0, 0},
+ /* Not connected */
+ {NC , NC , NC}
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM_IO_Line[] = {
+ {PA00, 0, 0},
+ {PA23, 1, 0},
+ {PA21, 2, 0},
+ {PA01, 0, 1},
+ {PA16, 1, 1},
+ {PA22, 2, 1},
+ /* Not connected */
+ {NC , NC , NC}
+};
+
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PeripheralPins.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,47 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_CTS[]; +extern const PinMap PinMap_UART_RTS[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; +extern const PinMap PinMap_PWM_IO_Line[]; + + + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/PinNames.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,105 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT,
+ PIN_INPUT_OUTPUT //pin state can be set and read back
+} PinDirection;
+
+typedef enum {
+ PA00 = 0,
+ PA01 = 1,
+ PA02 = 2,
+ PA03 = 3,
+ PA04 = 4,
+ PA05 = 5,
+ PA06 = 6,
+ PA07 = 7,
+ PA08 = 8,
+ PA09 = 9,
+ PA10 = 10,
+ PA11 = 11,
+ PA12 = 12,
+ PA13 = 13,
+ PA14 = 14,
+ PA15 = 15,
+ PA16 = 16,
+ PA17 = 17,
+ PA18 = 18,
+ PA19 = 19,
+ PA20 = 20,
+ PA21 = 21,
+ PA22 = 22,
+ PA23 = 23,
+ PA24 = 24,
+ PA25 = 25,
+ PA26 = 26,
+ PA27 = 27,
+ PA28 = 28,
+ PA29 = 29,
+ PA30 = 30,
+ PA31 = 31,
+
+ PB00 = 32,
+ PB01 = 33,
+ PB02 = 34,
+ PB03 = 35,
+ PB04 = 36,
+ PB05 = 37,
+ PB06 = 38,
+ PB07 = 39,
+ PB08 = 40,
+ PB09 = 41,
+ PB10 = 42,
+ PB11 = 43,
+ PB12 = 44,
+ PB13 = 45,
+ PB14 = 46,
+ PB15 = 47,
+
+ USBTX = PA28,
+ USBRX = PA27,
+
+ LED1 = PA06,
+ LED2 = PA06,
+ LED3 = PA06,
+ LED4 = PA06,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullUp = 1,
+ PullDown = 2,
+ PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/SAMG55_XPLAINED_PRO/board_init.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,228 @@
+/**
+ * \file
+ *
+ * \brief SAMG55 Xplained Pro board initialization
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <compiler.h>
+#include <board.h>
+#include <conf_board.h>
+#include <ioport.h>
+
+/**
+ * \addtogroup samg55_xplained_pro_group
+ * @{
+ */
+
+/**
+ * \brief Set peripheral mode for IOPORT pins.
+ * It will configure port mode and disable pin mode (but enable peripheral).
+ * \param port IOPORT port to configure
+ * \param masks IOPORT pin masks to configure
+ * \param mode Mode masks to configure for the specified pin (\ref ioport_modes)
+ */
+#define ioport_set_port_peripheral_mode(port, masks, mode) \
+ do {\
+ ioport_set_port_mode(port, masks, mode);\
+ ioport_disable_port(port, masks);\
+ } while (0)
+
+/**
+ * \brief Set peripheral mode for one single IOPORT pin.
+ * It will configure port mode and disable pin mode (but enable peripheral).
+ * \param pin IOPORT pin to configure
+ * \param mode Mode masks to configure for the specified pin (\ref ioport_modes)
+ */
+#define ioport_set_pin_peripheral_mode(pin, mode) \
+ do {\
+ ioport_set_pin_mode(pin, mode);\
+ ioport_disable_pin(pin);\
+ } while (0)
+
+#if defined(__GNUC__)
+void board_init(void) WEAK __attribute__((alias("system_board_init")));
+#elif defined(__ICCARM__)
+void board_init(void);
+# pragma weak board_init=system_board_init
+#endif
+
+void system_board_init(void)
+{
+
+#ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT
+ WDT->WDT_MR = WDT_MR_WDDIS;
+#endif
+ ioport_init();
+
+ /* Initialize LED0, turned off */
+ ioport_set_pin_dir(LED_0_PIN, IOPORT_DIR_OUTPUT);
+ ioport_set_pin_level(LED_0_PIN, IOPORT_PIN_LEVEL_HIGH);
+
+ /* Initialize SW0 */
+ ioport_set_pin_dir(BUTTON_0_PIN, IOPORT_DIR_INPUT);
+ ioport_set_pin_mode(BUTTON_0_PIN, IOPORT_MODE_PULLUP);
+
+ /* Initialize EXT3 LED0, LED1 & LED2, turned off */
+ ioport_set_pin_level(OLED1_LED1_PIN, !OLED1_LED1_ACTIVE);
+ ioport_set_pin_dir(OLED1_LED1_PIN, IOPORT_DIR_OUTPUT);
+ ioport_set_pin_level(OLED1_LED2_PIN, !OLED1_LED2_ACTIVE);
+ ioport_set_pin_dir(OLED1_LED2_PIN, IOPORT_DIR_OUTPUT);
+ ioport_set_pin_level(OLED1_LED3_PIN, !OLED1_LED3_ACTIVE);
+ ioport_set_pin_dir(OLED1_LED3_PIN, IOPORT_DIR_OUTPUT);
+
+#if defined (CONF_BOARD_UART_CONSOLE)
+ /* Configure UART pins */
+ ioport_set_port_peripheral_mode(PINS_USART7_PORT, PINS_USART7,
+ PINS_USART7_FLAGS);
+#endif
+
+#ifdef CONF_BOARD_USART_RXD
+ /* Configure USART RXD pin */
+ ioport_set_pin_peripheral_mode(EXT3_PIN_UART_RX,
+ IOPORT_MODE_MUX_B);
+#endif
+
+#ifdef CONF_BOARD_USART_TXD
+ /* Configure USART TXD pin */
+ ioport_set_pin_peripheral_mode(EXT3_PIN_UART_TX,
+ IOPORT_MODE_MUX_B);
+#endif
+
+#ifdef CONF_BOARD_USART_SCK
+ /* Configure USART synchronous communication SCK pin */
+ ioport_set_pin_peripheral_mode(EXT3_PIN_8,
+ IOPORT_MODE_MUX_B);
+#endif
+
+#if defined(CONF_BOARD_SPI) || defined(CONF_BOARD_SD_MMC_SPI)
+ ioport_set_pin_peripheral_mode(SPI_MISO_GPIO, SPI_MISO_FLAGS);
+ ioport_set_pin_peripheral_mode(SPI_MOSI_GPIO, SPI_MOSI_FLAGS);
+ ioport_set_pin_peripheral_mode(SPI_SPCK_GPIO, SPI_SPCK_FLAGS);
+
+#ifdef CONF_BOARD_SD_MMC_SPI
+ /* Setting SD detection pin */
+ ioport_set_pin_dir(SD_MMC_0_CD_GPIO, IOPORT_DIR_INPUT);
+ ioport_set_pin_mode(SD_MMC_0_CD_GPIO, IOPORT_MODE_PULLUP);
+#endif
+
+#ifdef CONF_BOARD_SPI_NPCS0
+ ioport_set_pin_peripheral_mode(SPI_NPCS0_GPIO, SPI_NPCS0_FLAGS);
+#endif
+
+#ifdef CONF_BOARD_SPI_NPCS1
+ ioport_set_pin_peripheral_mode(SPI_NPCS1_GPIO, SPI_NPCS1_FLAGS);
+#endif
+#endif
+
+#ifdef CONF_BOARD_OLED_UG_2832HSWEG04
+ ioport_set_pin_dir(UG_2832HSWEG04_DATA_CMD_GPIO, IOPORT_DIR_OUTPUT);
+ ioport_set_pin_mode(UG_2832HSWEG04_DATA_CMD_GPIO, IOPORT_MODE_PULLUP);
+ ioport_set_pin_dir(UG_2832HSWEG04_RESET_GPIO, IOPORT_DIR_OUTPUT);
+ ioport_set_pin_mode(UG_2832HSWEG04_RESET_GPIO, IOPORT_MODE_PULLUP);
+#endif
+
+#ifdef CONF_BOARD_TWI0
+ ioport_set_pin_peripheral_mode(TWI0_DATA_GPIO, TWI0_DATA_FLAGS);
+ ioport_set_pin_peripheral_mode(TWI0_CLK_GPIO, TWI0_CLK_FLAGS);
+#endif
+
+#ifdef CONF_BOARD_TWI1
+ ioport_set_pin_peripheral_mode(TWI1_DATA_GPIO, TWI1_DATA_FLAGS);
+ ioport_set_pin_peripheral_mode(TWI1_CLK_GPIO, TWI1_CLK_FLAGS);
+#endif
+
+#ifdef CONF_BOARD_TWI2
+ ioport_set_pin_peripheral_mode(TWI2_DATA_GPIO, TWI2_DATA_FLAGS);
+ ioport_set_pin_peripheral_mode(TWI2_CLK_GPIO, TWI2_CLK_FLAGS);
+#endif
+
+#if defined(CONF_BOARD_TWI4) ||defined(CONF_BOARD_AT30TSE)
+ ioport_set_pin_peripheral_mode(TWI4_DATA_GPIO, TWI4_DATA_FLAGS);
+ ioport_set_pin_peripheral_mode(TWI4_CLK_GPIO, TWI4_CLK_FLAGS);
+#endif
+
+#ifdef CONF_BOARD_I2S0
+ ioport_set_pin_peripheral_mode(I2S0_SCK_GPIO, I2S0_SCK_FLAGS);
+ ioport_set_pin_peripheral_mode(I2S0_MCK_GPIO, I2S0_MCK_FLAGS);
+ ioport_set_pin_peripheral_mode(I2S0_SDI_GPIO, I2S0_SDI_FLAGS);
+ ioport_set_pin_peripheral_mode(I2S0_SDO_GPIO, I2S0_SDO_FLAGS);
+ ioport_set_pin_peripheral_mode(I2S0_WS_GPIO, I2S0_WS_FLAGS);
+#endif
+
+#ifdef CONF_BOARD_I2S1
+ ioport_set_pin_peripheral_mode(I2S1_SCK_GPIO, I2S1_SCK_FLAGS);
+ ioport_set_pin_peripheral_mode(I2S1_MCK_GPIO, I2S1_MCK_FLAGS);
+ ioport_set_pin_peripheral_mode(I2S1_SDI_GPIO, I2S1_SDI_FLAGS);
+ ioport_set_pin_peripheral_mode(I2S1_SDO_GPIO, I2S1_SDO_FLAGS);
+ ioport_set_pin_peripheral_mode(I2S1_WS_GPIO, I2S1_WS_FLAGS);
+#endif
+
+#ifdef CONF_BOARD_PDM
+ ioport_set_pin_peripheral_mode(PDM_CLK_GPIO, PDM_CLK_FLAGS);
+ ioport_set_pin_peripheral_mode(PDM_DAT_GPIO, PDM_DAT_FLAGS);
+#endif
+
+#ifdef CONF_BOARD_USART0
+ ioport_set_pin_peripheral_mode(USART0_RXD_GPIO, USART0_RXD_FLAGS);
+ ioport_set_pin_peripheral_mode(USART0_TXD_GPIO, USART0_TXD_FLAGS);
+ ioport_set_pin_peripheral_mode(USART0_SCK_GPIO, USART0_SCK_FLAGS);
+ ioport_set_pin_peripheral_mode(USART0_CTS_GPIO, USART0_CTS_FLAGS);
+ ioport_set_pin_peripheral_mode(USART0_RTS_GPIO, USART0_RTS_FLAGS);
+#endif
+
+#ifdef CONF_BOARD_USART6
+ ioport_set_pin_peripheral_mode(USART6_RXD_GPIO, USART6_RXD_FLAGS);
+ ioport_set_pin_peripheral_mode(USART6_TXD_GPIO, USART6_TXD_FLAGS);
+ ioport_set_pin_peripheral_mode(USART6_SCK_GPIO, USART6_SCK_FLAGS);
+ ioport_set_pin_peripheral_mode(USART6_CTS_GPIO, USART6_CTS_FLAGS);
+ ioport_set_pin_peripheral_mode(USART6_RTS_GPIO, USART6_RTS_FLAGS);
+#endif
+
+#if defined(CONF_BOARD_USB_PORT)
+# if defined(CONF_BOARD_USB_VBUS_DETECT)
+ gpio_configure_pin(USB_VBUS_PIN, USB_VBUS_FLAGS);
+# endif
+#endif
+}
+
+/** @} */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/SAMG55_XPLAINED_PRO/mbed_overrides.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "compiler.h"
+#include "sysclk.h"
+
+uint8_t g_sys_init = 0;
+
+//called before main - implement here if board needs it ortherwise, let
+// the application override this if necessary
+//TODO: To be implemented by adding system init and board init
+void mbed_sdk_init()
+{
+ if(g_sys_init == 0) {
+ sysclk_init();
+ system_board_init();
+ g_sys_init = 1;
+ }
+}
+/***************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/SAMG55_XPLAINED_PRO/samg55_xplained_pro.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,731 @@
+/**
+ * \file
+ *
+ * \brief SAMG55 Xplained Pro board definition
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SAMG55_XPLAINED_PRO_H_INCLUDED
+#define SAMG55_XPLAINED_PRO_H_INCLUDED
+
+#include <conf_board.h>
+#include <compiler.h>
+
+/**
+ * \ingroup group_common_boards
+ * \defgroup samg55_xplained_pro_group SAMG55 Xplained Pro board
+ *
+ * @{
+ */
+
+void system_board_init(void);
+
+/**
+ * \defgroup samg55_config_group Configuration
+ *
+ * Symbols to use for configuring the board and its initialization.
+ *
+ * @{
+ */
+#ifdef __DOXYGEN__
+
+/* ! \name Initialization */
+/* @{ */
+
+/**
+ * \def CONF_BOARD_KEEP_WATCHDOG_AT_INIT
+ * \brief If defined, the watchdog will remain enabled
+ *
+ * If this symbol is defined, the watchdog is left running with its current
+ * configuration. Otherwise, it is disabled during board initialization.
+ */
+# ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT
+# define CONF_BOARD_KEEP_WATCHDOG_AT_INIT
+# endif
+
+/* @} */
+
+#endif /* __DOXYGEN__ */
+/**@} */
+
+/**
+ * \defgroup samg55_xplained_pro_features_group Features
+ *
+ * Symbols that describe features and capabilities of the board.
+ *
+ * @{
+ */
+
+/** Name string macro */
+#define BOARD_NAME "SAMG55_XPLAINED_PRO"
+
+/** \name Resonator definitions
+ * @{ */
+#define BOARD_FREQ_SLCK_XTAL (32768U)
+#define BOARD_FREQ_SLCK_BYPASS (32768U)
+#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */
+#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */
+#define BOARD_MCK CHIP_FREQ_CPU_MAX
+/*TBD startup time needs to be adjusted according to measurements */
+#define BOARD_OSC_STARTUP_US 15625
+
+/** @} */
+
+/** \name LED0 definitions
+ * @{ */
+#define LED0_GPIO (PIO_PA6_IDX)
+#define LED0_FLAGS (PIO_OUTPUT_1 | PIO_DEFAULT)
+
+#define LED0_PIN IOPORT_CREATE_PIN(PIOA, 6)
+#define LED0_ACTIVE_LEVEL false
+#define LED0_INACTIVE_LEVEL !LED0_ACTIVE_LEVEL
+/** @} */
+
+/** \name SW0 definitions
+ * @{ */
+#define SW0_PIN IOPORT_CREATE_PIN(PIOA, 2)
+#define SW0_ACTIVE false
+#define SW0_INACTIVE !SW0_ACTIVE
+#define SW0_SUPC_INPUT 2
+/** @} */
+
+/**
+ * Wrapper macros for SW0, to ensure common naming across all Xplained Pro
+ * boards.
+ */
+#define PIN_SW0 {PIO_PA2, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE}
+#define PIN_SW0_MASK PIO_PA2
+#define PIN_SW0_PIO PIOA
+#define PIN_SW0_ID ID_PIOA
+#define PIN_SW0_TYPE PIO_INPUT
+#define PIN_SW0_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE)
+//@}
+
+/**
+ * \name LED #0 definitions
+ *
+ * Wrapper macros for LED0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ * @{ */
+#define LED_0_NAME "LED0 (yellow)"
+#define LED_0_PIN LED0_PIN
+#define LED_0_ACTIVE LED0_ACTIVE_LEVEL
+#define LED_0_INACTIVE LED0_INACTIVE_LEVEL
+
+#define PIN_LED_0 {PIO_PA16, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}
+#define PIN_LED_0_MASK PIO_PA16
+#define PIN_LED_0_PIO PIOA
+#define PIN_LED_0_ID ID_PIOA
+#define PIN_LED_0_TYPE PIO_OUTPUT_1
+#define PIN_LED_0_ATTR PIO_DEFAULT
+/** @} */
+
+/** Number of on-board LEDs */
+#define LED_COUNT 1
+
+/**
+ * \name Button #0 definitions
+ *
+ * Wrapper macros for SW0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ * @{ */
+#define BUTTON_0_NAME "SW0"
+#define BUTTON_0_PIN SW0_PIN
+#define BUTTON_0_ACTIVE SW0_ACTIVE
+#define BUTTON_0_INACTIVE SW0_INACTIVE
+#define BUTTON_0_SUPC_INPUT SW0_SUPC_INPUT
+
+#define PUSHBUTTON_1_NAME "SW0"
+#define PIN_PUSHBUTTON_1 {PIO_PA2, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE}
+#define PIN_PUSHBUTTON_1_MASK PIO_PA2
+#define PIN_PUSHBUTTON_1_PIO PIOA
+#define PIN_PUSHBUTTON_1_ID ID_PIOA
+#define PIN_PUSHBUTTON_1_TYPE PIO_INPUT
+#define PIN_PUSHBUTTON_1_ATTR PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE
+/** @} */
+
+/** Number of on-board buttons */
+#define BUTTON_COUNT 1
+
+#define CONSOLE_UART USART7
+#define CONSOLE_UART_ID ID_FLEXCOM7
+/** USART7 pins (TXD7 and RXD7) definitions, PA27,28. */
+#define PINS_USART7 (PIO_PA27B_RXD7| PIO_PA28B_TXD7)
+#define PINS_USART7_FLAGS (IOPORT_MODE_MUX_B)
+
+#define PINS_USART7_PORT IOPORT_PIOA
+#define PINS_USART7_MASK (PIO_PA27B_RXD7 | PIO_PA28B_TXD7)
+#define PINS_USART7_PIO PIOA
+#define PINS_USART7_ID ID_PIOA
+#define PINS_USART7_TYPE PIO_PERIPH_B
+#define PINS_USART7_ATTR PIO_DEFAULT
+
+/** PCK1 pin definition (PA17) */
+#define PIN_PCK1 (PIO_PA17_IDX)
+#define PIN_PCK1_MUX (IOPORT_MODE_MUX_B)
+#define PIN_PCK1_FLAGS (IOPORT_MODE_MUX_B)
+#define PIN_PCK1_PORT IOPORT_PIOA
+#define PIN_PCK1_MASK PIO_PA17B_PCK1
+#define PIN_PCK1_PIO PIOA
+#define PIN_PCK1_ID ID_PIOA
+#define PIN_PCK1_TYPE PIO_PERIPH_B
+#define PIN_PCK1_ATTR PIO_DEFAULT
+
+#define PIN_TC0_TIOA0 (PIO_PA0_IDX)
+#define PIN_TC0_TIOA0_MUX (IOPORT_MODE_MUX_B)
+#define PIN_TC0_TIOA0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)
+
+#define PIN_TC0_TIOA1 (PIO_PA23_IDX)
+#define PIN_TC0_TIOA1_MUX (IOPORT_MODE_MUX_B)
+#define PIN_TC0_TIOA1_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)
+//! \name SPI
+//@{
+/** SPI MISO pin definition. */
+#define SPI_MISO_GPIO (PIO_PA12_IDX)
+#define SPI_MISO_FLAGS (IOPORT_MODE_MUX_A)
+/** SPI MOSI pin definition. */
+#define SPI_MOSI_GPIO (PIO_PA13_IDX)
+#define SPI_MOSI_FLAGS (IOPORT_MODE_MUX_A)
+/** SPI SPCK pin definition. */
+#define SPI_SPCK_GPIO (PIO_PA14_IDX)
+#define SPI_SPCK_FLAGS (IOPORT_MODE_MUX_A)
+
+/** SPI chip select 0 pin definition. */
+#define SPI_NPCS0_GPIO (PIO_PA11_IDX)
+#define SPI_NPCS0_FLAGS (IOPORT_MODE_MUX_A)
+/** SPI chip select 1 pin definition. */
+#define SPI_NPCS1_GPIO (PIO_PA5_IDX)
+#define SPI_NPCS1_FLAGS (IOPORT_MODE_MUX_B)
+//@}
+
+/** \name Extension header #1 pin definitions
+ * @{
+ */
+#define EXT1_PIN_3 IOPORT_CREATE_PIN(PIOA, 17)
+#define EXT1_PIN_4 IOPORT_CREATE_PIN(PIOA, 18)
+#define EXT1_PIN_5 IOPORT_CREATE_PIN(PIOA, 26)
+#define EXT1_PIN_6 IOPORT_CREATE_PIN(PIOA, 25)
+#define EXT1_PIN_7 IOPORT_CREATE_PIN(PIOA, 0)
+#define EXT1_PIN_8 IOPORT_CREATE_PIN(PIOA, 23)
+#define EXT1_PIN_9 IOPORT_CREATE_PIN(PIOA, 24)
+#define EXT1_PIN_10 IOPORT_CREATE_PIN(PIOA, 29)
+#define EXT1_PIN_11 IOPORT_CREATE_PIN(PIOB, 10)
+#define EXT1_PIN_12 IOPORT_CREATE_PIN(PIOB, 11)
+#define EXT1_PIN_13 IOPORT_CREATE_PIN(PIOA, 9)
+#define EXT1_PIN_14 IOPORT_CREATE_PIN(PIOA, 10)
+#define EXT1_PIN_15 IOPORT_CREATE_PIN(PIOA, 11)
+#define EXT1_PIN_16 IOPORT_CREATE_PIN(PIOA, 13)
+#define EXT1_PIN_17 IOPORT_CREATE_PIN(PIOA, 12)
+#define EXT1_PIN_18 IOPORT_CREATE_PIN(PIOA, 14)
+/** @} */
+
+/** \name Extension header #1 pin definitions by function
+ * @{
+ */
+#define EXT1_PIN_ADC_0 EXT1_PIN_3
+#define EXT1_PIN_ADC_1 EXT1_PIN_4
+#define EXT1_PIN_GPIO_0 EXT1_PIN_5
+#define EXT1_PIN_GPIO_1 EXT1_PIN_6
+#define EXT1_PIN_PWM_0 EXT1_PIN_7
+#define EXT1_PIN_PWM_1 EXT1_PIN_8
+#define EXT1_PIN_IRQ EXT1_PIN_9
+#define EXT1_PIN_I2C_SDA EXT1_PIN_11
+#define EXT1_PIN_I2C_SCL EXT1_PIN_12
+#define EXT1_PIN_UART_RX EXT1_PIN_13
+#define EXT1_PIN_UART_TX EXT1_PIN_14
+#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10
+#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15
+#define EXT1_PIN_SPI_MOSI EXT1_PIN_16
+#define EXT1_PIN_SPI_MISO EXT1_PIN_17
+#define EXT1_PIN_SPI_SCK EXT1_PIN_18
+/** @} */
+
+/** \name Extension header #1 ADC definitions
+ * @{
+ */
+#define EXT1_ADC_MODULE ADC
+#define EXT1_ADC_0_CHANNEL 0
+#define EXT1_ADC_1_CHANNEL 1
+/** @} */
+
+/** \name Extension header #1 PWM definitions
+ * @{
+ */
+#define EXT1_PWM_MODULE TC0
+#define EXT1_PWM_0_CHANNEL 0
+#define EXT1_PWM_0_MUX IOPORT_MODE_MUX_B
+#define EXT1_PWM_1_CHANNEL 1
+#define EXT1_PWM_1_MUX IOPORT_MODE_MUX_B
+/** @} */
+
+/** \name Extension header #1 IRQ/External interrupt definitions
+ * @{
+ */
+#define EXT1_IRQ_MODULE SUPC
+#define EXT1_IRQ_INPUT 11
+/** @} */
+
+/** \name Extension header #1 I2C definitions
+ * @{
+ */
+#define EXT1_TWI_MODULE TWI4
+#define EXT1_TWI_TWD_MUX IOPORT_MODE_MUX_B
+#define EXT1_TWI_TWCK_MUX IOPORT_MODE_MUX_B
+/** @} */
+
+/** \name Extension header #1 UART definitions
+ * @{
+ */
+#define EXT1_UART_MODULE USART0
+#define EXT1_UART_RXD_MUX IOPORT_MODE_MUX_A
+#define EXT1_UART_TXD_MUX IOPORT_MODE_MUX_A
+/** @} */
+
+/** \name Extension header #1 SPI definitions
+ * @{
+ */
+#define EXT1_SPI_MODULE SPI5
+#define EXT1_SPI_MISO_MUX IOPORT_MODE_MUX_A
+#define EXT1_SPI_MOSI_MUX IOPORT_MODE_MUX_A
+#define EXT1_SPI_SPCK_MUX IOPORT_MODE_MUX_A
+#define EXT1_SPI_NPCS0_MUX IOPORT_MODE_MUX_A
+/** @} */
+
+/** \name Extension header #3 pin definitions
+ * @{
+ */
+#define EXT3_PIN_3 IOPORT_CREATE_PIN(PIOA, 19)
+#define EXT3_PIN_4 IOPORT_CREATE_PIN(PIOA, 20)
+#define EXT3_PIN_5 IOPORT_CREATE_PIN(PIOA, 30)
+#define EXT3_PIN_6 IOPORT_CREATE_PIN(PIOB, 15)
+#define EXT3_PIN_7 IOPORT_CREATE_PIN(PIOA, 1)
+#define EXT3_PIN_8 IOPORT_CREATE_PIN(PIOB, 13)
+#define EXT3_PIN_9 IOPORT_CREATE_PIN(PIOB, 3)
+#define EXT3_PIN_10 IOPORT_CREATE_PIN(PIOA, 15)
+#define EXT3_PIN_11 IOPORT_CREATE_PIN(PIOB, 8)
+#define EXT3_PIN_12 IOPORT_CREATE_PIN(PIOB, 9)
+#define EXT3_PIN_13 IOPORT_CREATE_PIN(PIOB, 1)
+#define EXT3_PIN_14 IOPORT_CREATE_PIN(PIOB, 0)
+#define EXT3_PIN_15 IOPORT_CREATE_PIN(PIOA, 5)
+#define EXT3_PIN_16 IOPORT_CREATE_PIN(PIOA, 13)
+#define EXT3_PIN_17 IOPORT_CREATE_PIN(PIOA, 12)
+#define EXT3_PIN_18 IOPORT_CREATE_PIN(PIOA, 14)
+/** @} */
+
+/** \name Extension header #3 pin definitions by function
+ * @{
+ */
+#define EXT3_PIN_ADC_0 EXT3_PIN_3
+#define EXT3_PIN_ADC_1 EXT3_PIN_4
+#define EXT3_PIN_GPIO_0 EXT3_PIN_5
+#define EXT3_PIN_PWM_0 EXT3_PIN_7
+#define EXT3_PIN_IRQ EXT3_PIN_9
+#define EXT3_PIN_I2C_SDA EXT3_PIN_11
+#define EXT3_PIN_I2C_SCL EXT3_PIN_12
+#define EXT3_PIN_UART_RX EXT3_PIN_13
+#define EXT3_PIN_UART_TX EXT3_PIN_14
+#define EXT3_PIN_SPI_SS_1 EXT3_PIN_10
+#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15
+#define EXT3_PIN_SPI_MOSI EXT3_PIN_16
+#define EXT3_PIN_SPI_MISO EXT3_PIN_17
+#define EXT3_PIN_SPI_SCK EXT3_PIN_18
+/** @} */
+
+/** \name Extension header #3 ADC definitions
+ * @{
+ */
+#define EXT3_ADC_MODULE ADC
+#define EXT3_ADC_0_CHANNEL 2
+#define EXT3_ADC_1_CHANNEL 3
+/** @} */
+
+/** \name Extension header #3 PWM definitions
+ * @{
+ */
+#define EXT3_PWM_MODULE TC2
+#define EXT3_PWM_0_CHANNEL 0
+#define EXT3_PWM_0_MUX IOPORT_MODE_MUX_A
+/** @} */
+
+/** \name Extension header #3 IRQ/External interrupt definitions
+ * @{
+ */
+#define EXT3_IRQ_MODULE SUPC
+#define EXT3_IRQ_INPUT 10
+/** @} */
+
+/** \name Extension header #3 I2C definitions
+ * @{
+ */
+#define EXT3_TWI_MODULE TWI1
+#define EXT3_TWI_TWD_MUX IOPORT_MODE_MUX_A
+#define EXT3_TWI_TWCK_MUX IOPORT_MODE_MUX_A
+/** @} */
+
+/** \name Extension header #3 UART definitions
+ * @{
+ */
+#define EXT3_UART_MODULE UART0
+#define EXT3_UART_RXD_MUX IOPORT_MODE_MUX_A
+#define EXT3_UART_TXD_MUX IOPORT_MODE_MUX_A
+/** @} */
+
+/** \name Extension header #3 SPI definitions
+ * @{
+ */
+#define EXT3_SPI_MODULE SPI5
+#define EXT3_SPI_MISO_MUX IOPORT_MODE_MUX_A
+#define EXT3_SPI_MOSI_MUX IOPORT_MODE_MUX_A
+#define EXT3_SPI_SPCK_MUX IOPORT_MODE_MUX_A
+#define EXT3_SPI_NPCS1_MUX IOPORT_MODE_MUX_B
+/** @} */
+
+/** \name Extension header #4 pin definitions
+ * @{
+ */
+#define EXT4_PIN_5 IOPORT_CREATE_PIN(PIOA, 31)
+#define EXT4_PIN_9 IOPORT_CREATE_PIN(PIOB, 14)
+#define EXT4_PIN_11 IOPORT_CREATE_PIN(PIOB, 10)
+#define EXT4_PIN_12 IOPORT_CREATE_PIN(PIOB, 11)
+/** @} */
+
+/** \name Extension header #4 pin definitions by function
+ * @{
+ */
+#define EXT4_PIN_GPIO_0 EXT3_PIN_5
+#define EXT4_PIN_IRQ EXT3_PIN_9
+#define EXT4_PIN_I2C_SDA EXT3_PIN_11
+#define EXT4_PIN_I2C_SCL EXT3_PIN_12
+/** @} */
+
+/** \name Extension header #4 IRQ/External interrupt definitions
+ * @{
+ */
+#define EXT4_IRQ_MODULE SUPC
+#define EXT4_IRQ_INPUT 14
+/** @} */
+
+/** \name Extension header #4 TWI definitions
+ * @{
+ */
+#define EXT4_TWI_MODULE TWI1
+#define EXT4_TWI_TWD_MUX IOPORT_MODE_MUX_A
+#define EXT4_TWI_TWCK_MUX IOPORT_MODE_MUX_A
+/** @} */
+
+/** \name Embedded debugger GPIO interface definitions
+ * @{
+ */
+#define EDBG_GPIO0_PIN IOPORT_CREATE_PIN(PIOA, 15)
+#define EDBG_GPIO1_PIN IOPORT_CREATE_PIN(PIOB, 3)
+#define EDBG_GPIO2_PIN IOPORT_CREATE_PIN(PIOB, 4)
+#define EDBG_GPIO3_PIN IOPROT_CREATE_PIN(PIOB, 9)
+/** @} */
+
+/** \name Embedded debugger USART interface definitions
+ * @{
+ */
+#define EDBG_UART_MODULE USART
+#define EDBG_UART_RX_PIN IOPORT_CREATE_PIN(PIOA, 5)
+#define EDBG_UART_RX_MUX IOPORT_MODE_MUX_A
+#define EDBG_UART_TX_PIN IOPORT_CREATE_PIN(PIOA, 6)
+#define EDBG_UART_TX_MUX IOPORT_MODE_MUX_A
+/** @} */
+
+/** \name Embedded debugger I2C interface definitions
+ * @{
+ */
+#define EDBG_TWI_MODULE TWI1
+#define EDBG_TWI_TWD_MUX IOPORT_MODE_MUX_A
+#define EDBG_TWI_TWCK_MUX IOPORT_MODE_MUX_A
+/** @} */
+
+/** \name Embedded debugger CDC Gateway USART interface definitions
+ * @{
+ */
+#define EDBG_CDC_UART_MODULE UART0
+#define EDBG_CDC_UART_RX_PIN IOPORT_CREATE_PIN(PIOA, 9)
+#define EDBG_CDC_UART_RX_MUX IOPORT_MODE_MUX_A
+#define EDBG_CDC_UART_TX_PIN IOPORT_CREATE_PIN(PIOA, 10)
+#define EDBG_CDC_UART_TX_MUX IOPORT_MODE_MUX_A
+/** @} */
+
+//! \name OLED
+//@{
+/** OLED command/data select pin */
+#define UG_2832HSWEG04_DATA_CMD_GPIO (PIO_PA30_IDX)
+/** OLED reset pin */
+#define UG_2832HSWEG04_RESET_GPIO (PIO_PA15_IDX)
+/** OLED SPI configuration */
+#define UG_2832HSWEG04_SS 1
+#define UG_2832HSWEG04_BAUDRATE 5000000
+//! \name OLED dimensions
+//@{
+#define LCD_WIDTH_PIXELS (128)
+#define LCD_HEIGHT_PIXELS (32)
+//@}
+//@}
+
+/** \name TWI
+* @{
+*/
+/** TWI0 pin definitions */
+#define TWI0_DATA_GPIO PIO_PA9_IDX
+#define TWI0_DATA_FLAGS IOPORT_MODE_MUX_A
+#define TWI0_CLK_GPIO PIO_PA10_IDX
+#define TWI0_CLK_FLAGS IOPORT_MODE_MUX_A
+/** TWI1 pin definitions */
+#define TWI1_DATA_GPIO PIO_PB2_IDX
+#define TWI1_DATA_FLAGS IOPORT_MODE_MUX_A
+#define TWI1_CLK_GPIO PIO_PB3_IDX
+#define TWI1_CLK_FLAGS IOPORT_MODE_MUX_A
+/** TWI4 pin definitions */
+#define TWI4_DATA_GPIO EXT1_PIN_11
+#define TWI4_DATA_FLAGS IOPORT_MODE_MUX_A
+#define TWI4_CLK_GPIO EXT1_PIN_12
+#define TWI4_CLK_FLAGS IOPORT_MODE_MUX_A
+/** TWI6 pin definitions */
+#define TWI6_DATA_GPIO EXT3_PIN_11
+#define TWI6_DATA_FLAGS IOPORT_MODE_MUX_B
+#define TWI6_CLK_GPIO EXT3_PIN_12
+#define TWI6_CLK_FLAGS IOPORT_MODE_MUX_B
+/** @} */
+
+/** \name USART
+* @{
+*/
+/** USART0 pin definitions */
+#define USART0_RXD_GPIO EXT1_PIN_13
+#define USART0_RXD_FLAGS IOPORT_MODE_MUX_A
+#define USART0_TXD_GPIO EXT1_PIN_14
+#define USART0_TXD_FLAGS IOPORT_MODE_MUX_A
+#define USART0_SCK_GPIO EXT3_PIN_14
+#define USART0_SCK_FLAGS IOPORT_MODE_MUX_A
+#define USART0_CTS_GPIO EXT1_PIN_6
+#define USART0_CTS_FLAGS IOPORT_MODE_MUX_A
+#define USART0_RTS_GPIO EXT1_PIN_5
+#define USART0_RTS_FLAGS IOPORT_MODE_MUX_A
+
+/** USART6 pin definitions */
+#define USART6_RXD_GPIO EXT4_PIN_12
+#define USART6_RXD_FLAGS IOPORT_MODE_MUX_B
+#define USART6_TXD_GPIO EXT4_PIN_11
+#define USART6_TXD_FLAGS IOPORT_MODE_MUX_B
+#define USART6_SCK_GPIO EXT3_PIN_8
+#define USART6_SCK_FLAGS IOPORT_MODE_MUX_B
+#define USART6_CTS_GPIO EXT4_PIN_9
+#define USART6_CTS_FLAGS IOPORT_MODE_MUX_B
+#define USART6_RTS_GPIO EXT3_PIN_6
+#define USART6_RTS_FLAGS IOPORT_MODE_MUX_B
+/** @} */
+
+//! \name I2S0
+//@{
+/** I2S0 SCK pin definition. */
+#define I2S0_SCK_GPIO (PIO_PA0_IDX)
+#define I2S0_SCK_FLAGS (IOPORT_MODE_MUX_A)
+/** I2S0 MCK pin definition. */
+#define I2S0_MCK_GPIO (PIO_PA4_IDX)
+#define I2S0_MCK_FLAGS (IOPORT_MODE_MUX_B)
+/** I2S0 SDI pin definition. */
+#define I2S0_SDI_GPIO (PIO_PA2_IDX)
+#define I2S0_SDI_FLAGS (IOPORT_MODE_MUX_B)
+/** I2S0 SDO pin definition. */
+#define I2S0_SDO_GPIO (PIO_PA3_IDX)
+#define I2S0_SDO_FLAGS (IOPORT_MODE_MUX_B)
+/** I2S0 WS pin definition. */
+#define I2S0_WS_GPIO (PIO_PA1_IDX)
+#define I2S0_WS_FLAGS (IOPORT_MODE_MUX_A)
+//@}
+
+//! \name I2S1
+//@{
+/** I2S1 SCK pin definition. */
+#define I2S1_SCK_GPIO (PIO_PA19_IDX)
+#define I2S1_SCK_FLAGS (IOPORT_MODE_MUX_B)
+/** I2S1 MCK pin definition. */
+#define I2S1_MCK_GPIO (PIO_PA24_IDX)
+#define I2S1_MCK_FLAGS (IOPORT_MODE_MUX_A)
+/** I2S1 SDI pin definition. */
+#define I2S1_SDI_GPIO (PIO_PA22_IDX)
+#define I2S1_SDI_FLAGS (IOPORT_MODE_MUX_B)
+/** I2S1 SDO pin definition. */
+#define I2S1_SDO_GPIO (PIO_PA23_IDX)
+#define I2S1_SDO_FLAGS (IOPORT_MODE_MUX_A)
+/** I2S1 WS pin definition. */
+#define I2S1_WS_GPIO (PIO_PA20_IDX)
+#define I2S1_WS_FLAGS (IOPORT_MODE_MUX_B)
+//@}
+
+//! \name IO1 button definitions */
+//@{
+/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on rising edge. */
+#define PUSHBUTTON_1_NAME "SW0"
+#define GPIO_PUSH_BUTTON_1 (PIO_PA2_IDX)
+#define GPIO_PUSH_BUTTON_1_FLAGS (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE)
+//@}
+
+//! \name Light Sensor
+//@{
+#define LIGHT_SENSOR_GPIO PIO_PA17_IDX
+#define LIGHT_SENSOR_FLAGS PIO_INPUT
+//@}
+
+/** \name USB definitions
+ * @{
+ */
+#define PIN_USB_VBUS {PIO_PB4, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP}
+#define USB_VBUS_FLAGS (PIO_INPUT | PIO_DEBOUNCE | PIO_IT_EDGE)
+#define USB_VBUS_PIN_IRQn (PIOB_IRQn)
+#define USB_VBUS_PIN (PIO_PB4_IDX)
+#define USB_VBUS_PIO_ID (ID_PIOB)
+#define USB_VBUS_PIO_MASK (PIO_PB4)
+
+/** USB D- pin (System function) */
+#define PIN_USB_DM {PIO_PA21}
+/** USB D+ pin (System function) */
+#define PIN_USB_DP {PIO_PA22}
+/** @} */
+
+//! \name IO1 SD card definitions */
+//@{
+#define SD_MMC_SPI_MEM_CNT 1
+#define SD_MMC_0_CD_GPIO (PIO_PA29_IDX)
+#define SD_MMC_0_CD_DIR (IOPORT_DIR_INPUT)
+#define SD_MMC_0_CD_MODE (IOPORT_MODE_PULLUP)
+#define SD_MMC_0_CD_DETECT_VALUE 0
+#define SD_MMC_SPI SPI5
+#define SD_MMC_SPI_0_CS 0
+#define SD_MMC_0_CD_PIO_ID ID_PIOA
+/**
+ * Wrapper macros for IO1 SD, to ensure common naming across all Xplained Pro
+ * boards.
+ */
+#define SD_MMC_0_CD_FLAGS (PIO_INPUT | PIO_PULLUP)
+#define SD_MMC_0_CD {PIO_PA29, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE}
+#define SD_MMC_0_CD_MASK PIO_PA29
+#define SD_MMC_0_CD_PIO PIOA
+#define SD_MMC_0_CD_ID ID_PIOA
+#define SD_MMC_0_CD_TYPE PIO_INPUT
+#define SD_MMC_0_CD_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_EDGE)
+//@}
+
+//! \name IO1 temperature sensor definitions */
+//@{
+#define BOARD_AT30TSE_TWI TWI4
+#define BOARD_AT30TSE_TWI_ID ID_TWI4
+#define BOARD_TWI_SPEED (400000u)
+#define BOARD_USING_AT30TSE AT30TSE758
+#define BOARD_AT30TSE_DEVICE_ADDR 0x07
+//@}
+
+//! \name OLED1 led definitions */
+//@{
+#define OLED1_LED1_PIN EXT3_PIN_7
+#define OLED1_LED1_ACTIVE false
+#define OLED1_LED1_INACTIVE !OLED1_LED1_ACTIVE
+
+#define OLED1_LED2_PIN EXT3_PIN_8
+#define OLED1_LED2_ACTIVE false
+#define OLED1_LED2_INACTIVE !OLED1_LED2_ACTIVE
+
+#define OLED1_LED3_PIN EXT3_PIN_6
+#define OLED1_LED3_ACTIVE false
+#define OLED1_LED3_INACTIVE !OLED1_LED3_ACTIVE
+//@}
+
+//! \name OLED1 button definitions */
+//@{
+/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on rising edge. */
+#define OLED1_PUSHBUTTON_1_NAME "BUTTON 1"
+#define OLED1_GPIO_PUSH_BUTTON_1 (PIO_PB3_IDX)
+#define OLED1_GPIO_PUSH_BUTTON_1_FLAGS (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE)
+
+#define OLED1_PIN_PUSHBUTTON_1 {PIO_PB3, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE}
+#define OLED1_PIN_PUSHBUTTON_1_MASK PIO_PB3
+#define OLED1_PIN_PUSHBUTTON_1_PIO PIOB
+#define OLED1_PIN_PUSHBUTTON_1_ID ID_PIOB
+#define OLED1_PIN_PUSHBUTTON_1_TYPE PIO_INPUT
+#define OLED1_PIN_PUSHBUTTON_1_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE)
+
+/** Push button #2 definition. Attributes = pull-up + debounce + interrupt on rising edge. */
+#define OLED1_PUSHBUTTON_2_NAME "BUTTON 2"
+#define OLED1_GPIO_PUSH_BUTTON_2 (PIO_PA19_IDX)
+#define OLED1_GPIO_PUSH_BUTTON_2_FLAGS (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE)
+
+#define OLED1_PIN_PUSHBUTTON_2 {PIO_PA19, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE}
+#define OLED1_PIN_PUSHBUTTON_2_MASK PIO_PA19
+#define OLED1_PIN_PUSHBUTTON_2_PIO PIOA
+#define OLED1_PIN_PUSHBUTTON_2_ID ID_PIOA
+#define OLED1_PIN_PUSHBUTTON_2_TYPE PIO_INPUT
+#define OLED1_PIN_PUSHBUTTON_2_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE)
+
+/** Push button #3 definition. Attributes = pull-up + debounce + interrupt on rising edge. */
+#define OLED1_PUSHBUTTON_3_NAME "BUTTON 3"
+#define OLED1_GPIO_PUSH_BUTTON_3 (PIO_PA20_IDX)
+#define OLED1_GPIO_PUSH_BUTTON_3_FLAGS (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE)
+
+#define OLED1_PIN_PUSHBUTTON_3 {PIO_PA20, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE}
+#define OLED1_PIN_PUSHBUTTON_3_MASK PIO_PA20
+#define OLED1_PIN_PUSHBUTTON_3_PIO PIOA
+#define OLED1_PIN_PUSHBUTTON_3_ID ID_PIOA
+#define OLED1_PIN_PUSHBUTTON_3_TYPE PIO_INPUT
+#define OLED1_PIN_PUSHBUTTON_3_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE)
+//@}
+
+//! \name PDM
+//@{
+/** PDM CLK pin definition. */
+#define PDM_CLK_GPIO (PIO_PA10_IDX)
+#define PDM_CLK_FLAGS (IOPORT_MODE_MUX_B)
+/** PDM DAT pin definition. */
+#define PDM_DAT_GPIO (PIO_PA9_IDX)
+#define PDM_DAT_FLAGS (IOPORT_MODE_MUX_B)
+//@}
+
+/** @} */
+
+/** @} */
+
+#endif /* SAMG55_XPLAINED_PRO_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/TARGET_SAMG55J19/device.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,64 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 +#define DEVICE_SERIAL_FC 1 +#define DEVICE_SERIAL_ASYNCH 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 +#define DEVICE_I2C_ASYNCH 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 +#define DEVICE_SPI_ASYNCH 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 0 +#define DEVICE_MAC_OFFSET 0 + +#define DEVICE_LOWPOWERTIMER 1 +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 0 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/analogin_api.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+#include "cmsis.h"
+#include "adc2.h"
+#include "PeripheralPins.h"
+
+extern uint8_t g_sys_init;
+static uint8_t adc_inited = 0;
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+ MBED_ASSERT(obj);
+ if (g_sys_init == 0) {
+ sysclk_init();
+ system_board_init();
+ g_sys_init = 1;
+ }
+ obj->channel = (enum adc_channel_num)pinmap_peripheral(pin, PinMap_ADC);
+ MBED_ASSERT(obj->channel != NC);
+ if(!adc_inited) { /*ADC hardare to be initialised only once*/
+ adc_enable();
+#if SAMG55
+ adc_select_clock_source_mck(ADC);
+#endif
+ struct adc_config adc_cfg;
+ adc_get_config_defaults(&adc_cfg);
+ adc_cfg.resolution = ADC_16_BITS;
+ adc_init(ADC, &adc_cfg);
+ adc_average_on_single_trigger(ADC);
+ adc_set_trigger(ADC, ADC_TRIG_SW);
+ adc_start_calibration(ADC);
+ adc_inited = 1;
+ }
+ adc_channel_enable(ADC, obj->channel);
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+ MBED_ASSERT(obj);
+ adc_channel_get_value(ADC, obj->channel); /*Dummy read of current value*/
+ adc_start_software_conversion(ADC);
+ while (adc_get_interrupt_status(ADC) & (1 << obj->channel));
+ return (uint16_t)adc_channel_get_value(ADC, obj->channel);
+}
+
+float analogin_read(analogin_t *obj)
+{
+ MBED_ASSERT(obj);
+ uint16_t value = analogin_read_u16(obj);
+ return (float)value * (1.0f / (float)0xFFFF);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/board.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,415 @@
+/**
+ * \file
+ *
+ * \brief Standard board header file.
+ *
+ * This file includes the appropriate board header file according to the
+ * defined board (parameter BOARD).
+ *
+ * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/**
+ * \defgroup group_common_boards Generic board support
+ *
+ * The generic board support module includes board-specific definitions
+ * and function prototypes, such as the board initialization function.
+ *
+ * \{
+ */
+
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*! \name Base Boards
+ */
+//! @{
+#define EVK1100 1 //!< AT32UC3A EVK1100 board.
+#define EVK1101 2 //!< AT32UC3B EVK1101 board.
+#define UC3C_EK 3 //!< AT32UC3C UC3C-EK board.
+#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.
+#define EVK1105 5 //!< AT32UC3A EVK1105 board.
+#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board.
+#define UC3L_EK 7 //!< AT32UC3L-EK board.
+#define XPLAIN 8 //!< ATxmega128A1 Xplain board.
+#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board.
+#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board.
+#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board.
+#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board.
+#define STK600_RCUC3D 16 //!< STK600 RCUC3D board.
+#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board.
+#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board.
+#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board.
+#define XMEGA_A1U_XPLAINED_PRO 20 //!< ATxmega128A1U XMEGA-A1U Xplained Pro board.
+#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board.
+#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board.
+#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board.
+#define STK600_RC044X 24 //!< STK600 with RC044X routing card board.
+#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board.
+#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board.
+#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board.
+#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board.
+#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board.
+#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards.
+#define RZ600 31 //!< AT32UC3A RZ600 MCU board.
+#define SAM3S_EK 32 //!< SAM3S-EK board.
+#define SAM3U_EK 33 //!< SAM3U-EK board.
+#define SAM3X_EK 34 //!< SAM3X-EK board.
+#define SAM3N_EK 35 //!< SAM3N-EK board.
+#define SAM3S_EK2 36 //!< SAM3S-EK2 board.
+#define SAM4S_EK 37 //!< SAM4S-EK board.
+#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board.
+#define STK600_MEGA 39 //!< STK600 MEGA board.
+#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board.
+#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board.
+#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board.
+#define ARDUINO_DUE_X 43 //!< Arduino Due/X board.
+#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board.
+#define SAM4L_EK 45 //!< SAM4L-EK board.
+#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board.
+#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board.
+#define STK600_RC032X 48 //!< STK600 with RC032X routing card board.
+#define SAM4S_EK2 49 //!< SAM4S-EK2 board.
+#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board.
+#define SAM4E_EK 51 //!< SAM4E-EK board.
+#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board.
+#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board.
+#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board.
+#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit.
+#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 Zigbit.
+#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B Zigbit.
+#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board.
+#define SAMD20_XPLAINED_PRO 59 //!< SAM D20 Xplained Pro board.
+#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board.
+#define SAM4N_XPLAINED_PRO 61 //!< SAM4N Xplained Pro board.
+#define XMEGA_A3_REB_CBB 62 //!< XMEGA REB Controller Base board.
+#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB.
+#define SAM4C_EK 64 //!< SAM4C-EK board.
+#define RCB256RFR2_XPRO 65 //!< RFR2 RCB Xplained Pro board.
+#define SAMG53_XPLAINED_PRO 66 //!< SAMG53 Xplained Pro board.
+#define SAM4CP16BMB 67 //!< SAM4CP16BMB board.
+#define SAM4E_XPLAINED_PRO 68 //!< SAM4E Xplained Pro board.
+#define SAMD21_XPLAINED_PRO 69 //!< SAM D21 Xplained Pro board.
+#define SAMR21_XPLAINED_PRO 70 //!< SAM R21 Xplained Pro board.
+#define SAM4CMP_DB 71 //!< SAM4CMP demo board.
+#define SAM4CMS_DB 72 //!< SAM4CMS demo board.
+#define ATPL230AMB 73 //!< ATPL230AMB board.
+#define SAMD11_XPLAINED_PRO 74 //!< SAM D11 Xplained Pro board.
+#define SAMG55_XPLAINED_PRO 75 //!< SAMG55 Xplained Pro board.
+#define SAML21_XPLAINED_PRO 76 //!< SAM L21 Xplained Pro board.
+#define SAMD10_XPLAINED_MINI 77 //!< SAM D10 Xplained Mini board.
+#define SAMDA1_XPLAINED_PRO 78 //!< SAM DA1 Xplained Pro board.
+#define SAMW25_XPLAINED_PRO 79 //!< SAMW25 Xplained Pro board.
+#define SAMC21_XPLAINED_PRO 80 //!< SAM C21 Xplained Pro board.
+#define SAMV71_XPLAINED_ULTRA 81 //!< SAMV71 Xplained Ultra board.
+#define SAML22_XPLAINED_PRO 86 //!< SAM L22 Xplained Pro board.
+#define ATMEGA328P_XPLAINED_MINI 82 //!< ATMEGA328P Xplained MINI board.
+#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices.
+#define AVR_SIMULATOR_UC3 98 //!< Simulator for the AVR UC3 device family.
+#define USER_BOARD 99 //!< User-reserved board (if any).
+#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader).
+//! @}
+
+/*! \name Extension Boards
+ */
+//! @{
+#define EXT1102 1 //!< AT32UC3B EXT1102 board
+#define MC300 2 //!< AT32UC3 MC300 board
+#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1
+#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2
+#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board
+#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board
+#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A"
+#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600
+#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600
+#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600
+#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard
+#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board
+#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).
+//! @}
+
+#if BOARD == EVK1100
+# include "evk1100/evk1100.h"
+#elif BOARD == EVK1101
+# include "evk1101/evk1101.h"
+#elif BOARD == UC3C_EK
+# include "uc3c_ek/uc3c_ek.h"
+#elif BOARD == EVK1104
+# include "evk1104/evk1104.h"
+#elif BOARD == EVK1105
+# include "evk1105/evk1105.h"
+#elif BOARD == STK600_RCUC3L0
+# include "stk600/rcuc3l0/stk600_rcuc3l0.h"
+#elif BOARD == UC3L_EK
+# include "uc3l_ek/uc3l_ek.h"
+#elif BOARD == STK600_RCUC3L4
+# include "stk600/rcuc3l4/stk600_rcuc3l4.h"
+#elif BOARD == XPLAIN
+# include "xplain/xplain.h"
+#elif BOARD == STK600_MEGA
+/*No header-file to include*/
+#elif BOARD == STK600_MEGA_RF
+# include "stk600.h"
+#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO
+# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"
+#elif BOARD == ATMEGA256RFR2_ZIGBIT
+# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"
+#elif BOARD == STK600_RC032X
+# include "stk600/rc032x/stk600_rc032x.h"
+#elif BOARD == STK600_RC044X
+# include "stk600/rc044x/stk600_rc044x.h"
+#elif BOARD == STK600_RC064X
+# include "stk600/rc064x/stk600_rc064x.h"
+#elif BOARD == STK600_RC100X
+# include "stk600/rc100x/stk600_rc100x.h"
+#elif BOARD == UC3_A3_XPLAINED
+# include "uc3_a3_xplained/uc3_a3_xplained.h"
+#elif BOARD == UC3_L0_XPLAINED
+# include "uc3_l0_xplained/uc3_l0_xplained.h"
+#elif BOARD == STK600_RCUC3B0
+# include "stk600/rcuc3b0/stk600_rcuc3b0.h"
+#elif BOARD == STK600_RCUC3D
+# include "stk600/rcuc3d/stk600_rcuc3d.h"
+#elif BOARD == STK600_RCUC3C0
+# include "stk600/rcuc3c0/stk600_rcuc3c0.h"
+#elif BOARD == SAMG53_XPLAINED_PRO
+# include "samg53_xplained_pro/samg53_xplained_pro.h"
+#elif BOARD == SAMG55_XPLAINED_PRO
+# include "samg55_xplained_pro/samg55_xplained_pro.h"
+#elif BOARD == XMEGA_B1_XPLAINED
+# include "xmega_b1_xplained/xmega_b1_xplained.h"
+#elif BOARD == STK600_RC064X_LCDX
+# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"
+#elif BOARD == STK600_RC100X_LCDX
+# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"
+#elif BOARD == XMEGA_A1_XPLAINED
+# include "xmega_a1_xplained/xmega_a1_xplained.h"
+#elif BOARD == XMEGA_A1U_XPLAINED_PRO
+# include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h"
+#elif BOARD == UC3_L0_XPLAINED_BC
+# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"
+#elif BOARD == SAM3S_EK
+# include "sam3s_ek/sam3s_ek.h"
+# include "system_sam3s.h"
+#elif BOARD == SAM3S_EK2
+# include "sam3s_ek2/sam3s_ek2.h"
+# include "system_sam3sd8.h"
+#elif BOARD == SAM3U_EK
+# include "sam3u_ek/sam3u_ek.h"
+# include "system_sam3u.h"
+#elif BOARD == SAM3X_EK
+# include "sam3x_ek/sam3x_ek.h"
+# include "system_sam3x.h"
+#elif BOARD == SAM3N_EK
+# include "sam3n_ek/sam3n_ek.h"
+# include "system_sam3n.h"
+#elif BOARD == SAM4S_EK
+# include "sam4s_ek/sam4s_ek.h"
+# include "system_sam4s.h"
+#elif BOARD == SAM4S_WPIR_RD
+# include "sam4s_wpir_rd/sam4s_wpir_rd.h"
+# include "system_sam4s.h"
+#elif BOARD == SAM4S_XPLAINED
+# include "sam4s_xplained/sam4s_xplained.h"
+# include "system_sam4s.h"
+#elif BOARD == SAM4S_EK2
+# include "sam4s_ek2/sam4s_ek2.h"
+# include "system_sam4s.h"
+#elif BOARD == MEGA_1284P_XPLAINED
+/*No header-file to include*/
+#elif BOARD == ARDUINO_DUE_X
+# include "arduino_due_x/arduino_due_x.h"
+# include "system_sam3x.h"
+#elif BOARD == SAM4L_EK
+# include "sam4l_ek/sam4l_ek.h"
+#elif BOARD == SAM4E_EK
+# include "sam4e_ek/sam4e_ek.h"
+#elif BOARD == SAMD20_XPLAINED_PRO
+# include "samd20_xplained_pro/samd20_xplained_pro.h"
+#elif BOARD == SAMD21_XPLAINED_PRO
+# include "samd21_xplained_pro/samd21_xplained_pro.h"
+#elif BOARD == SAMR21_XPLAINED_PRO
+# include "samr21_xplained_pro/samr21_xplained_pro.h"
+#elif BOARD == SAMD11_XPLAINED_PRO
+# include "samd11_xplained_pro/samd11_xplained_pro.h"
+#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18A__)
+# include "saml21_xplained_pro/saml21_xplained_pro.h"
+#elif BOARD == SAML22_XPLAINED_PRO
+# include "saml22_xplained_pro/saml22_xplained_pro.h"
+#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18B__)
+# include "saml21_xplained_pro_b/saml21_xplained_pro.h"
+#elif BOARD == SAMD10_XPLAINED_MINI
+# include "samd10_xplained_mini/samd10_xplained_mini.h"
+#elif BOARD == SAMDA1_XPLAINED_PRO
+# include "samda1_xplained_pro/samda1_xplained_pro.h"
+#elif BOARD == SAMC21_XPLAINED_PRO
+# include "samc21_xplained_pro/samc21_xplained_pro.h"
+#elif BOARD == SAM4N_XPLAINED_PRO
+# include "sam4n_xplained_pro/sam4n_xplained_pro.h"
+#elif BOARD == SAMW25_XPLAINED_PRO
+# include "samw25_xplained_pro/samw25_xplained_pro.h"
+#elif BOARD == SAMV71_XPLAINED_ULTRA
+# include "samv71_xplained_ultra/samv71_xplained_ultra.h"
+#elif BOARD == MEGA1284P_XPLAINED_BC
+# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"
+#elif BOARD == UC3_L0_QT600
+# include "uc3_l0_qt600/uc3_l0_qt600.h"
+#elif BOARD == XMEGA_A3BU_XPLAINED
+# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"
+#elif BOARD == XMEGA_E5_XPLAINED
+# include "xmega_e5_xplained/xmega_e5_xplained.h"
+#elif BOARD == UC3B_BOARD_CONTROLLER
+# include "uc3b_board_controller/uc3b_board_controller.h"
+#elif BOARD == RZ600
+# include "rz600/rz600.h"
+#elif BOARD == STK600_RCUC3A0
+# include "stk600/rcuc3a0/stk600_rcuc3a0.h"
+#elif BOARD == ATXMEGA128A1_QT600
+# include "atxmega128a1_qt600/atxmega128a1_qt600.h"
+#elif BOARD == STK600_RCUC3L3
+# include "stk600/rcuc3l3/stk600_rcuc3l3.h"
+#elif BOARD == SAM4S_XPLAINED_PRO
+# include "sam4s_xplained_pro/sam4s_xplained_pro.h"
+#elif BOARD == SAM4L_XPLAINED_PRO
+# include "sam4l_xplained_pro/sam4l_xplained_pro.h"
+#elif BOARD == SAM4L8_XPLAINED_PRO
+# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"
+#elif BOARD == SAM4C_EK
+# include "sam4c_ek/sam4c_ek.h"
+#elif BOARD == SAM4CMP_DB
+# include "sam4cmp_db/sam4cmp_db.h"
+#elif BOARD == SAM4CMS_DB
+# include "sam4cms_db/sam4cms_db.h"
+#elif BOARD == SAM4CP16BMB
+# include "sam4cp16bmb/sam4cp16bmb.h"
+#elif BOARD == ATPL230AMB
+# include "atpl230amb/atpl230amb.h"
+#elif BOARD == SIMULATOR_XMEGA_A1
+# include "simulator/xmega_a1/simulator_xmega_a1.h"
+#elif BOARD == XMEGA_C3_XPLAINED
+# include "xmega_c3_xplained/xmega_c3_xplained.h"
+#elif BOARD == XMEGA_RF233_ZIGBIT
+# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"
+#elif BOARD == XMEGA_A3_REB_CBB
+# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"
+#elif BOARD == ATMEGARFX_RCB
+# include "atmegarfx_rcb/atmegarfx_rcb.h"
+#elif BOARD == RCB256RFR2_XPRO
+# include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h"
+#elif BOARD == XMEGA_RF212B_ZIGBIT
+# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"
+#elif BOARD == SAM4E_XPLAINED_PRO
+# include "sam4e_xplained_pro/sam4e_xplained_pro.h"
+#elif BOARD == AVR_SIMULATOR_UC3
+# include "avr_simulator_uc3/avr_simulator_uc3.h"
+#elif BOARD == USER_BOARD
+// User-reserved area: #include the header file of your board here (if any).
+# include "user_board.h"
+#elif BOARD == ATMEGA328P_XPLAINED_MINI
+# include "atmega328p_xplained_mini/atmega328p_xplained_mini.h"
+#elif BOARD == DUMMY_BOARD
+# include "dummy/dummy_board.h"
+#else
+# error No known Atmel board defined
+#endif
+
+#if (defined EXT_BOARD)
+# if EXT_BOARD == MC300
+# include "mc300/mc300.h"
+# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \
+ (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \
+ (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \
+ (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
+# include "sensors_xplained/sensors_xplained.h"
+# elif EXT_BOARD == RZ600_AT86RF231
+# include "at86rf231/at86rf231.h"
+# elif EXT_BOARD == RZ600_AT86RF230B
+# include "at86rf230b/at86rf230b.h"
+# elif EXT_BOARD == RZ600_AT86RF212
+# include "at86rf212/at86rf212.h"
+# elif EXT_BOARD == SECURITY_XPLAINED
+# include "security_xplained.h"
+# elif EXT_BOARD == USER_EXT_BOARD
+// User-reserved area: #include the header file of your extension board here
+// (if any).
+# endif
+#endif
+
+
+#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+
+/*! \brief This function initializes the board target resources
+ *
+ * This function should be called to ensure proper initialization of the target
+ * board hardware connected to the part.
+ */
+extern void board_init(void);
+
+#endif // #ifdef __AVR32_ABI_COMPILER__
+#else
+/*! \brief This function initializes the board target resources
+ *
+ * This function should be called to ensure proper initialization of the target
+ * board hardware connected to the part.
+ */
+extern void board_init(void);
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \}
+ */
+
+#endif // _BOARD_H_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_board.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,52 @@ +/** + * \file + * + * \brief Board configuration. + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef CONF_BOARD_H_INCLUDED +#define CONF_BOARD_H_INCLUDED + +#define BAORD SAMG55_XPLAINED_PRO + +#endif /* CONF_BOARD_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_clock.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,95 @@ +/** + * \file + * + * \brief SAMG55 clock configuration. + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef CONF_CLOCK_H_INCLUDED +#define CONF_CLOCK_H_INCLUDED + +/* + * ===== System Clock (MCK) Source Options + * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC + * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL + * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS + * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC + * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_16M_RC + * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_24M_RC + * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL + * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS + */ +#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK + +/* + * ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES)) + */ +#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 +/* + * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_2 + * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_4 + * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_8 + * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_16 + * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_32 + * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_64 + * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_3 + */ + +/* + * ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div) + * Use mul and div effective values here. + */ +#define CONFIG_PLL0_SOURCE PLL_SRC_SLCK_XTAL +#define CONFIG_PLL0_MUL 3662 +#define CONFIG_PLL0_DIV 1 + +/* + * ===== Target frequency (System clock) + * - External XTAL frequency: 32768Hz + * - System clock source: SLCK XTAL + * - System clock prescaler: 1 (divided by 1) + * - PLLA source: SLCK_XTAL + * - PLLA output: SLCK_XTAL * 3662 / 1 + * - System clock: SLCK_XTAL * 3662 / 1 / 1 = 120MHz + */ + +#endif /* CONF_CLOCK_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_extint.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,100 @@
+/**
+ * \file
+ *
+ * \brief SAM G55 External Interrupt Driver Configuration Header
+ *
+ * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef CONF_EXTINT_H_INCLUDED
+#define CONF_EXTINT_H_INCLUDED
+
+#include <asf.h>
+
+/**
+ * Push button definitions for sleep mode and active mode
+ * @{
+ */
+#define PIN_PUSHBUTTON_WAKEUP_PIO PIOA
+#define PIN_PUSHBUTTON_WAKEUP_MASK PIO_PA2
+#define PIN_PUSHBUTTON_WAKEUP_ID ID_PIOA
+#define PIN_PUSHBUTTON_WAKEUP_ATTR PIO_DEFAULT
+/** @} */
+
+/** Wakeup pin for wait mode: SW0 */
+#define WAKEUP_WAIT_INPUT_ID (1u << 2)
+/** Wakeup pin for backup mode: Touchscreen controller IRQ pin */
+#define WAKEUP_BACKUP_INPUT_ID (1u << 2)
+
+void button_cb(void);
+static inline void button_handler(uint32_t ul_id, uint32_t ul_mask);
+
+/* Button Initialize */
+static inline void button_init(void)
+{
+ /* Adjust PIO debounce filter parameters, using 10 Hz filter. */
+ pio_set_debounce_filter(PIN_PUSHBUTTON_WAKEUP_PIO,
+ PIN_PUSHBUTTON_WAKEUP_MASK, 10);
+
+ /* Initialize PIO interrupt handlers, see PIO definition in board.h. */
+ pio_handler_set(PIN_PUSHBUTTON_WAKEUP_PIO, PIN_PUSHBUTTON_WAKEUP_ID,
+ PIN_PUSHBUTTON_WAKEUP_MASK, PIN_PUSHBUTTON_WAKEUP_ATTR,
+ button_handler);
+
+ /* Enable PIO controller IRQs. */
+ NVIC_EnableIRQ((IRQn_Type)PIN_PUSHBUTTON_WAKEUP_ID);
+
+ /* Enable PIO line interrupts. */
+ pio_enable_interrupt(PIN_PUSHBUTTON_WAKEUP_PIO,
+ PIN_PUSHBUTTON_WAKEUP_MASK);
+}
+
+/**
+ * \brief Handler for button interrupt.
+ *
+ * \note This interrupt is for waking up from sleep mode or exiting from active
+ * mode.
+ */
+static inline void button_handler(uint32_t ul_id, uint32_t ul_mask)
+{
+ if (PIN_PUSHBUTTON_WAKEUP_ID == ul_id &&
+ PIN_PUSHBUTTON_WAKEUP_MASK == ul_mask) {
+ button_cb();
+ }
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_serialdrv.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,166 @@
+/**
+ * \file
+ *
+ * \brief SAM G55 serial driver configuration.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef CONF_SERIALDRV_H_INCLUDED
+#define CONF_SERIALDRV_H_INCLUDED
+
+/* BTLC1000 Wakeup Pin */
+#define BTLC1000_WAKEUP_PIN (EXT1_PIN_6)
+
+/* BTLC1000 Chip Enable Pin */
+#define BTLC1000_CHIP_ENABLE_PIN (EXT1_PIN_10)
+
+/* BTLC1000 50ms Reset Duration */
+#define BTLC1000_RESET_MS (50)
+
+/* set port pin high */
+#define IOPORT_PIN_LEVEL_HIGH (true)
+/* Set port pin low */
+#define IOPORT_PIN_LEVEL_LOW (false)
+
+/** UART Interface */
+#define BLE_UART EXT1_UART_MODULE
+#define BLE_UART_ID ID_FLEXCOM0
+#define BLE_USART_FLEXCOM FLEXCOM0
+#define BLE_UART_IRQn FLEXCOM0_IRQn
+/* Configuration for console uart IRQ handler */
+#define BLE_UART_Handler FLEXCOM0_Handler
+
+/** Baudrate setting */
+#define CONF_UART_BAUDRATE (115200UL)
+/** Character length setting */
+#define CONF_UART_CHAR_LENGTH US_MR_CHRL_8_BIT
+/** Parity setting */
+#define CONF_UART_PARITY US_MR_PAR_NO
+/** Stop bits setting */
+#define CONF_UART_STOP_BITS US_MR_NBSTOP_1_BIT
+
+void serial_rx_callback(void);
+void serial_tx_callback(void);
+
+#define SERIAL_DRV_RX_CB serial_rx_callback
+#define SERIAL_DRV_TX_CB serial_tx_callback
+#define SERIAL_DRV_TX_CB_ENABLE true
+#define SERIAL_DRV_RX_CB_ENABLE true
+
+#define BLE_MAX_TX_PAYLOAD_SIZE 512
+#define BLE_MAX_RX_PAYLOAD_SIZE 512
+
+/* Set BLE Wakeup pin to be low */
+static inline bool ble_wakeup_pin_level(void)
+{
+ return (ioport_get_pin_level(BTLC1000_WAKEUP_PIN));
+}
+
+/* Set BLE Wakeup pin to be low */
+static inline void ble_wakeup_pin_set_low(void)
+{
+ ioport_set_pin_level(BTLC1000_WAKEUP_PIN,
+ IOPORT_PIN_LEVEL_LOW);
+}
+
+/* Set wakeup pin to high */
+static inline void ble_wakeup_pin_set_high(void)
+{
+ ioport_set_pin_level(BTLC1000_WAKEUP_PIN,
+ IOPORT_PIN_LEVEL_HIGH);
+}
+
+/* Set enable pin to Low */
+static inline void ble_enable_pin_set_low(void)
+{
+ ioport_set_pin_level(BTLC1000_CHIP_ENABLE_PIN,
+ IOPORT_PIN_LEVEL_LOW);
+}
+
+/* Set enable pin to high */
+static inline void ble_enable_pin_set_high(void)
+{
+ ioport_set_pin_level(BTLC1000_CHIP_ENABLE_PIN,
+ IOPORT_PIN_LEVEL_HIGH);
+}
+
+/* Configure the BTLC1000 control(chip_enable, wakeup) pins */
+static inline void ble_configure_control_pin(void)
+{
+ /* initialize the delay before use */
+ delay_init();
+
+ /* Configure control pins as output */
+ ioport_init();
+
+ ioport_set_pin_dir(BTLC1000_WAKEUP_PIN, IOPORT_DIR_OUTPUT);
+
+ /* set wakeup pin to low */
+ ble_wakeup_pin_set_high();
+
+ ioport_set_pin_dir(BTLC1000_CHIP_ENABLE_PIN, IOPORT_DIR_OUTPUT);
+
+ /* set chip enable to low */
+ ble_enable_pin_set_low();
+
+ /* Delay for 50ms */
+ delay_ms(BTLC1000_RESET_MS);
+
+ /* set chip enable to high */
+ ble_enable_pin_set_high();
+}
+
+static inline void ble_reset(void)
+{
+ /* BTLC1000 Reset Sequence @Todo */
+ ble_enable_pin_set_high();
+ ble_wakeup_pin_set_high();
+ delay_ms(BTLC1000_RESET_MS);
+
+ ble_enable_pin_set_low();
+ ble_wakeup_pin_set_low();
+ delay_ms(BTLC1000_RESET_MS);
+
+ ble_enable_pin_set_high();
+ ble_wakeup_pin_set_high();
+ delay_ms(BTLC1000_RESET_MS);
+}
+
+
+#endif /* CONF_SERIALDRV_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_sleepmgr.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,51 @@ +/** + * \file + * + * \brief Sleep manager configuration + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ +#ifndef CONF_SLEEPMGR_H +#define CONF_SLEEPMGR_H + +#define CONFIG_SLEEPMGR_ENABLE + +#endif /* CONF_SLEEPMGR_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_timer.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief Timer Driver Configuration Header + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef CONF_TIMER_H_INCLUDED +#define CONF_TIMER_H_INCLUDED + +#define TIMER (TC0) +#define TIMER_CHANNEL_ID 0 +#define ID_TC (ID_TC0) + +#define DEF_1MHZ (1000000) +#define DEF_120MHz (120000000) +#define TIMER_OVF_COUNT_1SEC (DEF_120MHz/(128*65535)) + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/config/TARGET_SAMG55/conf_uart_serial.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,61 @@ +/** + * \file + * + * \brief USART Serial Configuration + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef CONF_USART_SERIAL_H_INCLUDED +#define CONF_USART_SERIAL_H_INCLUDED + +/** UART Interface */ +#define CONF_UART CONSOLE_UART +/** Baudrate setting */ +#define CONF_UART_BAUDRATE (115200UL) +/** Character length setting */ +#define CONF_UART_CHAR_LENGTH US_MR_CHRL_8_BIT +/** Parity setting */ +#define CONF_UART_PARITY US_MR_PAR_NO +/** Stop bits setting */ +#define CONF_UART_STOP_BITS US_MR_NBSTOP_1_BIT + +#endif/* CONF_USART_SERIAL_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/adc/adc2.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,518 @@
+/**
+ * \file
+ *
+ * \brief ADC Controller driver.
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "adc2.h"
+#include "sleepmgr.h"
+#include "status_codes.h"
+#include "sysclk.h"
+#include "pmc.h"
+
+/**
+ * \defgroup sam_drivers_adc2_group Analog-to-Digital Controller
+ *
+ * See \ref sam_adc2_quickstart.
+ *
+ * Driver for the Analog-to-Digital Controller. This driver provides access to
+ * the main features of the ADC controller.
+ *
+ * @{
+ */
+
+/* The number of channel in channel sequence1 register */
+#define ADC_SEQ1_CHANNEL_NUM (8UL)
+
+/* The number of ADC interrupt source */
+#define ADC_NUM_OF_INTERRUPT_SOURCE (24UL)
+
+
+const uint32_t adc_interrupt_mask[ADC_NUM_OF_INTERRUPT_SOURCE] = {
+ ADC_ISR_EOC0, ADC_ISR_EOC1, ADC_ISR_EOC2, ADC_ISR_EOC3,
+ ADC_ISR_EOC4, ADC_ISR_EOC5, ADC_ISR_EOC6, ADC_ISR_EOC7,
+#if (SAM4N)
+ ADC_ISR_EOC8, ADC_ISR_EOC9, ADC_ISR_EOC10, ADC_ISR_EOC11,
+ ADC_ISR_EOC12, ADC_ISR_EOC13, ADC_ISR_EOC14, ADC_ISR_EOC15,
+ ADC_ISR_EOC16,
+#endif
+#ifdef TEMP_SENSOR
+ ADC_ISR_TEMPCHG,
+#endif
+ ADC_ISR_EOCAL, ADC_ISR_DRDY,
+ ADC_ISR_GOVRE, ADC_ISR_COMPE, ADC_ISR_ENDRX, ADC_ISR_RXBUFF,
+};
+
+adc_callback_t adc_callback_pointer[ADC_NUM_OF_INTERRUPT_SOURCE];
+
+/**
+ * \brief Get the ADC default configurations.
+ *
+ * Use to initialize the configuration structure to known default values. This
+ * function should be called at the start of any ADC initiation.
+ *
+ * The default configuration is as follows:
+ * - 10-bit resolution
+ * - ADC clock frequency is 6MHz
+ * - Start Up Time is 64 periods ADC clock
+ * - Tracking Time is 3 periods of ADC clock
+ * - Transfer Period field shall be programmed with 2 as datasheet said
+ * - The controller converts channels in a simple numeric order
+ * - Appends the channel number to the conversion result in ADC_LCDR register
+ * - Only a Single Trigger is required to get an averaged value
+ *
+ * \param cfg Pointer to configuration structure to be initiated.
+ */
+void adc_get_config_defaults(struct adc_config *const cfg)
+{
+ /* Sanity check argument. */
+ Assert(cfg);
+
+#if SAMG55
+ cfg->resolution = ADC_12_BITS;
+#else
+ cfg->resolution = ADC_10_BITS;
+#endif
+ cfg->mck = sysclk_get_cpu_hz();
+ cfg->adc_clock = 6000000UL;
+ cfg->startup_time = ADC_STARTUP_TIME_4;
+ cfg->tracktim = 2;
+ cfg->transfer = 2;
+ cfg->useq = false;
+ cfg->tag = false;
+ cfg->aste = false;
+}
+
+/**
+ * \internal
+ * \brief Configure the ADC Module.
+ *
+ * \param adc Base address of the ADC
+ * \param config Configuration for the ADC
+ */
+static void adc_set_config(Adc *const adc, struct adc_config *config)
+{
+ uint32_t reg = 0;
+
+ reg = (config->useq ? ADC_MR_USEQ_REG_ORDER : 0) |
+ ADC_MR_PRESCAL(config->mck /
+ (2 * config->adc_clock) - 1) |
+ ADC_MR_TRACKTIM(config->tracktim) |
+ ADC_MR_TRANSFER(config->transfer) |
+ (config->startup_time);
+
+ adc->ADC_MR = reg;
+
+ adc->ADC_EMR = (config->tag ? ADC_EMR_TAG : 0) |
+ (config->aste ? ADC_EMR_ASTE_SINGLE_TRIG_AVERAGE : 0);
+
+ adc_set_resolution(adc, config->resolution);
+}
+
+#ifdef TEMP_SENSOR
+/**
+ * \brief Get the ADC Temperature Sensor default configurations.
+ *
+ * Use to initialize the configuration structure to known default values.
+ *
+ * The default configuration is as follows:
+ * - Generates an event when the converted data is in the comparison window
+ * - The window range is 0xFF ~ 0xFFF
+ *
+ * \param cfg Pointer to temperature sensor configuration structure
+ * to be initiated.
+ */
+void adc_temp_sensor_get_config_defaults(
+ struct adc_temp_sensor_config *const cfg)
+{
+ /*Sanity check argument. */
+ Assert(cfg);
+
+ cfg->tempon = true;
+ cfg->mode = ADC_TEMP_CMP_MODE_2;
+ cfg->low_threshold = 0xFF;
+ cfg->high_threshold = 0xFFF;
+}
+
+/**
+ * \brief Configure the ADC temperature sensor.
+ *
+ * \param adc Base address of the ADC
+ * \param config Configuration for the ADC temperature sensor
+ */
+void adc_temp_sensor_set_config(Adc *const adc,
+ struct adc_temp_sensor_config *config)
+{
+ uint32_t reg = 0;
+
+ reg = ((config->tempon) ? ADC_TEMPMR_TEMPON : 0) | (config->mode);
+ adc->ADC_TEMPMR = reg;
+
+ adc->ADC_TEMPCWR = ADC_TEMPCWR_TLOWTHRES(config->low_threshold) |
+ ADC_TEMPCWR_THIGHTHRES(config->high_threshold);
+}
+#endif
+
+#if (SAMG)
+/**
+ * \brief Get the Last Channel Specific Measurement default configurations.
+ *
+ * Use to initialize the configuration structure to known default values.
+ *
+ * The default configuration is as follows:
+ * - Generates an event when the converted data is in the comparison window
+ * - The window range is 0xFF ~ 0xFFF
+ *
+ * \param cfg Pointer to last channel configuration structure
+ * to be initiated.
+ */
+void adc_last_channel_get_config_defaults(
+ struct adc_last_channel_config *const cfg)
+{
+ /*Sanity check argument. */
+ Assert(cfg);
+
+ cfg->dual_trig_on = true;
+ cfg->mode = ADC_LAST_CHANNEL_CMP_MODE_2;
+ cfg->low_threshold = 0xFF;
+ cfg->high_threshold = 0xFFF;
+}
+
+/**
+ * \brief Configure the ADC Last Channel Specific Measurement.
+ *
+ * \param adc Base address of the ADC
+ * \param config Configuration for the last channel
+ */
+void adc_last_channel_set_config(Adc *const adc,
+ struct adc_last_channel_config *config)
+{
+ uint32_t reg = 0;
+
+ reg = ((config->dual_trig_on) ? ADC_LCTMR_DUALTRIG : 0) | (config->mode);
+ adc->ADC_LCTMR = reg;
+
+ adc->ADC_LCCWR = ADC_LCCWR_LOWTHRES(config->low_threshold) |
+ ADC_LCCWR_HIGHTHRES(config->high_threshold);
+}
+#endif
+
+/**
+ * \brief Initialize the ADC Module.
+ *
+ * \param adc Base address of the ADC
+ * \param config Configuration for the ADC
+ *
+ * \retval STATUS_OK Initialization is finished.
+ * \retval STATUS_ERR_BUSY Initialization failed.
+ */
+enum status_code adc_init(Adc *const adc, struct adc_config *config)
+{
+ Assert(adc);
+ Assert(config);
+
+ if ((adc_get_interrupt_status(adc) & ADC_ISR_DRDY) == ADC_ISR_DRDY) {
+ return STATUS_ERR_BUSY;
+ }
+
+ /* Reset and configure the ADC module */
+ adc->ADC_CR = ADC_CR_SWRST;
+ adc_set_config(adc, config);
+
+ uint32_t i;
+ for (i = 0; i < ADC_NUM_OF_INTERRUPT_SOURCE; i++) {
+ adc_callback_pointer[i] = 0;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * \brief Configure conversion resolution.
+ *
+ * \param adc Base address of the ADC.
+ * \param res Conversion resolution.
+ *
+ */
+void adc_set_resolution(Adc *const adc,
+ const enum adc_resolution res)
+{
+#if SAMG55
+ adc->ADC_EMR |= res;
+#else
+ if (res == ADC_11_BITS || res == ADC_12_BITS) {
+ adc->ADC_MR &= ~ADC_MR_LOWRES;
+ adc->ADC_EMR |= res;
+ } else {
+ adc->ADC_MR |= res;
+ adc->ADC_EMR &= ~ADC_EMR_OSR_Msk;
+ }
+#endif
+}
+
+/**
+ * \brief Configure comparison mode.
+ *
+ * \param adc Base address of the ADC.
+ * \param mode Comparison mode.
+ * \param channel Comparison Selected Channel.
+ * \param cmp_filter Compare Event Filtering.
+ */
+void adc_set_comparison_mode(Adc *const adc,
+ const enum adc_cmp_mode mode,
+ const enum adc_channel_num channel, uint8_t cmp_filter)
+{
+ if (channel != ADC_CHANNEL_ALL) {
+ adc_ch_sanity_check(adc, channel);
+ }
+
+ uint32_t reg;
+
+ reg = adc->ADC_EMR;
+
+ reg &= ~(ADC_EMR_CMPSEL_Msk |
+ ADC_EMR_CMPMODE_Msk |
+ ADC_EMR_CMPFILTER_Msk);
+ reg |= mode |
+ ((channel == ADC_CHANNEL_ALL) ? ADC_EMR_CMPALL
+ : ADC_EMR_CMPSEL(channel)) |
+ ADC_EMR_CMPFILTER(cmp_filter);
+
+ adc->ADC_EMR = reg;
+}
+
+/**
+ * \brief Configure ADC power mode.
+ *
+ * \param adc Base address of the ADC.
+ * \param mode ADC power mode value.
+ */
+void adc_set_power_mode(Adc *const adc,
+ const enum adc_power_mode mode)
+{
+ uint32_t reg;
+
+ reg = adc->ADC_MR;
+
+ switch (mode) {
+ case ADC_POWER_MODE_0:
+ reg |= ADC_MR_SLEEP_NORMAL;
+ break;
+
+ case ADC_POWER_MODE_1:
+ reg |= ADC_MR_SLEEP_SLEEP;
+ break;
+ }
+
+ adc->ADC_MR = reg;
+}
+
+/**
+ * \brief Set callback for ADC
+ *
+ * \param adc Base address of the ADC
+ * \param source Interrupt source
+ * \param callback Callback function pointer
+ * \param irq_level Interrupt level
+ */
+void adc_set_callback(Adc *const adc, enum adc_interrupt_source source,
+ adc_callback_t callback, uint8_t irq_level)
+{
+ Assert(adc);
+ Assert(callback);
+
+ adc_callback_pointer[source] = callback;
+ irq_register_handler(ADC_IRQn, irq_level);
+
+ /* Enable the specified interrupt source */
+ adc_enable_interrupt(adc, source);
+}
+
+/**
+ * \brief Enable ADC interrupts.
+ *
+ * \param adc Base address of the ADC.
+ * \param interrupt_source Interrupts to be enabled.
+ */
+void adc_enable_interrupt(Adc *const adc,
+ enum adc_interrupt_source interrupt_source)
+{
+ if (interrupt_source == ADC_INTERRUPT_ALL) {
+ adc->ADC_IER = ADC_INTERRUPT_ALL;
+ return;
+ } else {
+ adc->ADC_IER = adc_interrupt_mask[interrupt_source];
+ }
+}
+
+/**
+ * \brief Disable ADC interrupts.
+ *
+ * \param adc Base address of the ADC.
+ * \param interrupt_source Interrupts to be disabled.
+ */
+void adc_disable_interrupt(Adc *const adc,
+ enum adc_interrupt_source interrupt_source)
+{
+ if (interrupt_source == ADC_INTERRUPT_ALL) {
+ adc->ADC_IDR = ADC_INTERRUPT_ALL;
+ return;
+ } else {
+ adc->ADC_IDR = adc_interrupt_mask[interrupt_source];
+ }
+}
+
+/**
+ * \internal
+ * \brief Common ADC interrupt handler
+ *
+ * The optional callback used by the interrupt handler is set by the
+ * adc_set_callback() function.
+ *
+ * \param inst_num ADC instance number to handle interrupt for
+ * \param source Interrupt source number
+ */
+static void adc_interrupt(enum adc_interrupt_source source)
+{
+ if (adc_callback_pointer[source]) {
+ adc_callback_pointer[source]();
+ }
+}
+
+/**
+ * \internal
+ * \brief Call the callback function if the corresponding interrupt is asserted
+ *
+ * \param adc Base address of the ADC.
+ */
+static void adc_process_callback(Adc *const adc)
+{
+ volatile uint32_t status;
+ uint32_t cnt;
+
+ status = adc_get_interrupt_status(adc);
+
+ for (cnt = 0; cnt < ADC_NUM_OF_INTERRUPT_SOURCE; cnt++) {
+ if (status & adc_interrupt_mask[cnt]) {
+ adc_interrupt((enum adc_interrupt_source)cnt);
+ }
+ }
+}
+
+/**
+ * \brief Interrupt handler for ADC.
+ */
+void ADC_Handler(void)
+{
+ adc_process_callback(ADC);
+}
+
+/**
+ * \brief Enable ADC Module.
+ *
+ */
+void adc_enable(void)
+{
+ /* Enable peripheral clock. */
+ pmc_enable_periph_clk(ID_ADC);
+ sleepmgr_lock_mode(SLEEP_MODE_ADC);
+}
+
+/**
+ * \brief Disable ADC Module.
+ *
+ */
+void adc_disable(void)
+{
+ /* Disable peripheral clock. */
+ pmc_disable_periph_clk(ID_ADC);
+ sleepmgr_unlock_mode(SLEEP_MODE_ADC);
+}
+
+/**
+ * \brief Configure conversion sequence.
+ *
+ * \param adc Base address of the ADC.
+ * \param ch_list Channel sequence list.
+ * \param uc_num Number of channels in the list.
+ */
+void adc_configure_sequence(Adc *const adc,
+ const enum adc_channel_num ch_list[], uint8_t uc_num)
+{
+ uint8_t uc_counter;
+
+ /* Set user sequence mode */
+ adc->ADC_MR |= ADC_MR_USEQ_REG_ORDER;
+#if (SAM4N)
+ adc->ADC_SEQR1 = 0;
+ adc->ADC_SEQR2 = 0;
+#endif
+#if (SAMG)
+ adc->ADC_SEQR1 = 0;
+#endif
+
+ if (uc_num <= ADC_SEQ1_CHANNEL_NUM) {
+ for (uc_counter = 0; uc_counter < uc_num; uc_counter++) {
+#if (SAM4N || SAMG)
+ adc->ADC_SEQR1
+#endif
+ |= ch_list[uc_counter] << (4 * uc_counter);
+ }
+ } else {
+ for (uc_counter = 0; uc_counter <= ADC_SEQ1_CHANNEL_NUM;
+ uc_counter++) {
+#if (SAM4N || SAMG)
+ adc->ADC_SEQR1
+#endif
+ |= ch_list[uc_counter] << (4 * uc_counter);
+ }
+ for (uc_counter = 0; uc_counter < uc_num - ADC_SEQ1_CHANNEL_NUM;
+ uc_counter++) {
+#if (SAM4N)
+ adc->ADC_SEQR2 |= ch_list[8 + uc_counter] << (4 * uc_counter);
+#endif
+ }
+ }
+}
+
+//@}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/adc/adc2.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,813 @@
+/**
+ * \file
+ *
+ * \brief ADC Controller driver.
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef ADC2_H_INCLUDED
+#define ADC2_H_INCLUDED
+
+#include "compiler.h"
+#include "status_codes.h"
+
+#if (SAM4N)
+#define TEMP_SENSOR
+#define SLEEP_MODE_ADC SLEEPMGR_SLEEP_WFI
+#endif
+
+#if (SAMG)
+#define NO_TEMP_SENSOR
+#define SLEEP_MODE_ADC SLEEPMGR_ACTIVE
+#endif
+
+/** Write Protect Key */
+#ifndef ADC_WPMR_WPKEY_PASSWD
+#define ADC_WPMR_WPKEY_PASSWD (0x414443u << 8)
+#endif
+
+/** Definitions for ADC resolution */
+enum adc_resolution {
+#if SAMG55
+ ADC_12_BITS = ADC_EMR_OSR_NO_AVERAGE, /* ADC 12-bit resolution */
+ ADC_13_BITS = ADC_EMR_OSR_OSR4, /* ADC 13-bit resolution */
+ ADC_14_BITS = ADC_EMR_OSR_OSR16, /* ADC 14-bit resolution */
+ ADC_15_BITS = ADC_EMR_OSR_OSR64, /* ADC 15-bit resolution */
+ ADC_16_BITS = ADC_EMR_OSR_OSR256, /* ADC 16-bit resolution */
+#else
+ ADC_8_BITS = ADC_MR_LOWRES_BITS_8, /* ADC 8-bit resolution */
+ ADC_10_BITS = ADC_MR_LOWRES_BITS_10, /* ADC 10-bit resolution */
+ ADC_11_BITS = ADC_EMR_OSR_OSR4, /* ADC 11-bit resolution */
+ ADC_12_BITS = ADC_EMR_OSR_OSR16 /* ADC 12-bit resolution */
+#endif
+};
+
+/** Definitions for ADC power mode */
+enum adc_power_mode {
+ /* ADC core on and reference voltage circuitry on */
+ ADC_POWER_MODE_0 = 0,
+ /* ADC core off and reference voltage circuitry off */
+ ADC_POWER_MODE_1
+};
+
+/** Definitions for ADC trigger */
+enum adc_trigger {
+ /* Starting a conversion is only possible by software. */
+ ADC_TRIG_SW = ADC_MR_TRGEN_DIS,
+ /* External trigger */
+ ADC_TRIG_EXT = ADC_MR_TRGSEL_ADC_TRIG0 | ADC_MR_TRGEN,
+ /* TIO Output of the Timer Counter Channel 0 */
+ ADC_TRIG_TIO_CH_0 = ADC_MR_TRGSEL_ADC_TRIG1 | ADC_MR_TRGEN,
+ /* TIO Output of the Timer Counter Channel 1 */
+ ADC_TRIG_TIO_CH_1 = ADC_MR_TRGSEL_ADC_TRIG2 | ADC_MR_TRGEN,
+ /* TIO Output of the Timer Counter Channel 2 */
+ ADC_TRIG_TIO_CH_2 = ADC_MR_TRGSEL_ADC_TRIG3 | ADC_MR_TRGEN,
+#if (SAMG)
+ /* RTCOUT0 */
+ ADC_TRIG_RTC_0 = ADC_MR_TRGSEL_ADC_TRIG4 | ADC_MR_TRGEN,
+ /* RTTINC */
+ ADC_TRIG_RTT = ADC_MR_TRGSEL_ADC_TRIG5 | ADC_MR_TRGEN,
+#endif
+ /* Freerun mode conversion. */
+ ADC_TRIG_FREERUN = 0xFF
+};
+
+/** Definitions for ADC channel number */
+enum adc_channel_num {
+ ADC_CHANNEL_0 = 0,
+ ADC_CHANNEL_1,
+ ADC_CHANNEL_2,
+ ADC_CHANNEL_3,
+ ADC_CHANNEL_4,
+ ADC_CHANNEL_5,
+ ADC_CHANNEL_6,
+ ADC_CHANNEL_7,
+#if (SAM4N)
+ ADC_CHANNEL_8,
+ ADC_CHANNEL_9,
+ ADC_CHANNEL_10,
+ ADC_CHANNEL_11,
+ ADC_CHANNEL_12,
+ ADC_CHANNEL_13,
+ ADC_CHANNEL_14,
+ ADC_CHANNEL_15,
+#endif
+#ifdef TEMP_SENSOR
+ ADC_TEMPERATURE_SENSOR,
+#endif
+ ADC_CHANNEL_ALL = 0xFFFF
+};
+
+/** Definitions for ADC Start Up Time */
+enum adc_startup_time {
+ ADC_STARTUP_TIME_0 = ADC_MR_STARTUP_SUT0,
+ ADC_STARTUP_TIME_1 = ADC_MR_STARTUP_SUT8,
+ ADC_STARTUP_TIME_2 = ADC_MR_STARTUP_SUT16,
+ ADC_STARTUP_TIME_3 = ADC_MR_STARTUP_SUT24,
+ ADC_STARTUP_TIME_4 = ADC_MR_STARTUP_SUT64,
+ ADC_STARTUP_TIME_5 = ADC_MR_STARTUP_SUT80,
+ ADC_STARTUP_TIME_6 = ADC_MR_STARTUP_SUT96,
+ ADC_STARTUP_TIME_7 = ADC_MR_STARTUP_SUT112,
+ ADC_STARTUP_TIME_8 = ADC_MR_STARTUP_SUT512,
+ ADC_STARTUP_TIME_9 = ADC_MR_STARTUP_SUT576,
+ ADC_STARTUP_TIME_10 = ADC_MR_STARTUP_SUT640,
+ ADC_STARTUP_TIME_11 = ADC_MR_STARTUP_SUT704,
+ ADC_STARTUP_TIME_12 = ADC_MR_STARTUP_SUT768,
+ ADC_STARTUP_TIME_13 = ADC_MR_STARTUP_SUT832,
+ ADC_STARTUP_TIME_14 = ADC_MR_STARTUP_SUT896,
+ ADC_STARTUP_TIME_15 = ADC_MR_STARTUP_SUT960
+};
+
+/** Definitions for Comparison Mode */
+enum adc_cmp_mode {
+ ADC_CMP_MODE_0 = ADC_EMR_CMPMODE_LOW,
+ ADC_CMP_MODE_1 = ADC_EMR_CMPMODE_HIGH,
+ ADC_CMP_MODE_2 = ADC_EMR_CMPMODE_IN,
+ ADC_CMP_MODE_3 = ADC_EMR_CMPMODE_OUT
+};
+
+#ifdef TEMP_SENSOR
+/** Definitions for Temperature Comparison Mode */
+enum adc_temp_cmp_mode {
+ ADC_TEMP_CMP_MODE_0 = ADC_TEMPMR_TEMPCMPMOD_LOW,
+ ADC_TEMP_CMP_MODE_1 = ADC_TEMPMR_TEMPCMPMOD_HIGH,
+ ADC_TEMP_CMP_MODE_2 = ADC_TEMPMR_TEMPCMPMOD_IN,
+ ADC_TEMP_CMP_MODE_3 = ADC_TEMPMR_TEMPCMPMOD_OUT
+};
+#endif
+#if (SAMG)
+/** Definitions for Last Channel Specific Measurement Comparison Mode */
+enum adc_last_channel_cmp_mode {
+ ADC_LAST_CHANNEL_CMP_MODE_0 = ADC_LCTMR_CMPMOD_LOW,
+ ADC_LAST_CHANNEL_CMP_MODE_1 = ADC_LCTMR_CMPMOD_HIGH,
+ ADC_LAST_CHANNEL_CMP_MODE_2 = ADC_LCTMR_CMPMOD_IN,
+ ADC_LAST_CHANNEL_CMP_MODE_3 = ADC_LCTMR_CMPMOD_OUT
+};
+#endif
+
+/** Definitions for Reference Voltage Selection */
+enum adc_refer_voltage_source {
+ ADC_REFER_VOL_EXTERNAL = 0,
+ ADC_REFER_VOL_STUCK_AT_MIN,
+ ADC_REFER_VOL_VDDANA,
+ ADC_REFER_VOL_IRVS
+};
+
+/**
+ * \brief ADC Enhanced configuration structure.
+ *
+ * Configuration structure for a ADC Enhanced instance.
+ * This structure could be initialized by the \ref ADC_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct adc_config {
+ /** Resolution */
+ enum adc_resolution resolution;
+ /** Master Clock */
+ uint32_t mck;
+ /** ADC Clock */
+ uint32_t adc_clock;
+ /** Start Up Time */
+ enum adc_startup_time startup_time;
+ /** Tracking Time = (tracktim+1) / ADC clock */
+ uint8_t tracktim;
+ /** Transfer Period */
+ uint8_t transfer;
+ /** Use Sequence Enable */
+ bool useq;
+ /** TAG of ADC_LDCR register */
+ bool tag;
+ /** Averaging on Single Trigger Event */
+ bool aste;
+};
+
+#ifdef TEMP_SENSOR
+/** ADC Temperature Sensor configuration structure.*/
+struct adc_temp_sensor_config {
+ /** Temperature Sensor On */
+ bool tempon;
+ /** Temperature Comparison Mode */
+ enum adc_temp_cmp_mode mode;
+ /** Temperature Low Threshold */
+ uint16_t low_threshold;
+ /** Temperature High Threshold */
+ uint16_t high_threshold;
+};
+#endif
+
+#if (SAMG)
+/** ADC Last Channel Specific Measurement configuration structure.*/
+struct adc_last_channel_config {
+ /** Specific Measurement On */
+ bool dual_trig_on;
+ /** Specific Measurement Comparison Mode */
+ enum adc_last_channel_cmp_mode mode;
+ /** Specific Measurement Low Threshold */
+ uint16_t low_threshold;
+ /** Specific Measurement High Threshold */
+ uint16_t high_threshold;
+};
+#endif
+
+/** ADC interrupt source type */
+enum adc_interrupt_source {
+ ADC_INTERRUPT_EOC_0 = 0,
+ ADC_INTERRUPT_EOC_1,
+ ADC_INTERRUPT_EOC_2,
+ ADC_INTERRUPT_EOC_3,
+ ADC_INTERRUPT_EOC_4,
+ ADC_INTERRUPT_EOC_5,
+ ADC_INTERRUPT_EOC_6,
+ ADC_INTERRUPT_EOC_7,
+#if (SAM4N)
+ ADC_INTERRUPT_EOC_8,
+ ADC_INTERRUPT_EOC_9,
+ ADC_INTERRUPT_EOC_10,
+ ADC_INTERRUPT_EOC_11,
+ ADC_INTERRUPT_EOC_12,
+ ADC_INTERRUPT_EOC_13,
+ ADC_INTERRUPT_EOC_14,
+ ADC_INTERRUPT_EOC_15,
+ ADC_INTERRUPT_EOC_16,
+#endif
+#ifdef TEMP_SENSOR
+ ADC_INTERRUPT_TEMP_CHANGE,
+#endif
+ ADC_INTERRUPT_END_CAL,
+ ADC_INTERRUPT_DATA_READY,
+ ADC_INTERRUPT_OVERRUN_ERROR,
+ ADC_INTERRUPT_COMP_ERROR,
+ ADC_INTERRUPT_END_RXBUF,
+ ADC_INTERRUPT_RXBUF_FULL,
+ ADC_INTERRUPT_ALL = 0xFFFFFFFF
+};
+
+typedef void (*adc_callback_t)(void);
+
+void adc_get_config_defaults(struct adc_config *const cfg);
+enum status_code adc_init(Adc *const adc, struct adc_config *const config);
+
+#ifdef TEMP_SENSOR
+void adc_temp_sensor_get_config_defaults(
+ struct adc_temp_sensor_config *const cfg);
+void adc_temp_sensor_set_config(Adc *const adc,
+ struct adc_temp_sensor_config *config);
+#endif
+#if (SAMG)
+void adc_last_channel_get_config_defaults(
+ struct adc_last_channel_config *const cfg);
+void adc_last_channel_set_config(Adc *const adc,
+ struct adc_last_channel_config *config);
+#endif
+
+void adc_configure_sequence(Adc *const adc,
+ const enum adc_channel_num ch_list[], const uint8_t uc_num);
+void adc_enable(void);
+void adc_disable(void);
+void adc_set_callback(Adc *const adc, enum adc_interrupt_source source,
+ adc_callback_t callback, uint8_t irq_level);
+
+/**
+ * \internal
+ * \brief ADC channel sanity check
+ *
+ * \param adc Base address of the ADC.
+ * \param channel Adc channel number.
+ *
+ */
+static inline void adc_ch_sanity_check(Adc *const adc,
+ const enum adc_channel_num channel)
+{
+ if (adc == ADC) {
+ Assert((channel < NB_CH_ADC)
+#ifdef TEMP_SENSOR
+ ||(channel == ADC_TEMPERATURE_SENSOR)
+#endif
+ );
+ }
+
+ UNUSED(channel);
+}
+
+#if (SAMG)
+#if SAMG55
+/**
+ * \brief Configure ADC clock to mck.
+ *
+ * \param adc Base address of the ADC.
+ *
+ */
+static inline void adc_select_clock_source_mck(Adc *const adc)
+{
+ uint32_t reg;
+
+ reg = adc->ADC_EMR;
+
+ reg &= ~ADC_EMR_SRCCLK_PMC_PCK;
+
+ adc->ADC_EMR = reg;
+}
+
+/**
+ * \brief Configure ADC clock to pck.
+ *
+ * \param adc Base address of the ADC.
+ *
+ */
+static inline void adc_select_clock_source_pck(Adc *const adc)
+{
+ uint32_t reg;
+
+ reg = adc->ADC_EMR;
+
+ reg |= ADC_EMR_SRCCLK_PMC_PCK;
+
+ adc->ADC_EMR = reg;
+}
+
+#else
+/**
+ * \brief Configure ADC clock to MCK.
+ *
+ * \param adc Base address of the ADC.
+ *
+ */
+static inline void adc_set_clock_mck(Adc *const adc)
+{
+ uint32_t reg;
+
+ reg = adc->ADC_EMR;
+
+ reg |= ADC_MR_DIV1;
+
+ adc->ADC_MR = reg;
+}
+
+/**
+ * \brief Configure ADC clock to MCK/3.
+ *
+ * \param adc Base address of the ADC.
+ *
+ */
+static inline void adc_set_clock_mck_div3(Adc *const adc)
+{
+ uint32_t reg;
+
+ reg = adc->ADC_MR;
+
+ reg &= ~ADC_MR_DIV1;
+ reg |= ADC_MR_DIV3;
+
+ adc->ADC_MR = reg;
+}
+#endif
+#endif
+
+/**
+ * \brief Configure conversion trigger and free run mode.
+ *
+ * \param adc Base address of the ADC.
+ * \param trigger Conversion trigger.
+ *
+ */
+static inline void adc_set_trigger(Adc *const adc,
+ const enum adc_trigger trigger)
+{
+ uint32_t reg;
+
+ reg = adc->ADC_MR;
+
+ if (trigger == ADC_TRIG_FREERUN) {
+ reg |= ADC_MR_FREERUN_ON;
+ } else {
+ reg &= ~(ADC_MR_TRGSEL_Msk | ADC_MR_TRGEN | ADC_MR_FREERUN_ON);
+ reg |= trigger;
+ }
+
+ adc->ADC_MR = reg;
+}
+
+void adc_set_resolution(Adc *const adc,
+ const enum adc_resolution res);
+
+void adc_set_comparison_mode(Adc *const adc,
+ const enum adc_cmp_mode mode,
+ const enum adc_channel_num channel,
+ uint8_t cmp_filter);
+
+/**
+ * \brief Get comparison mode.
+ *
+ * \param adc Base address of the ADC.
+ *
+ * \retval Compare mode value.
+ */
+static inline enum adc_cmp_mode adc_get_comparison_mode(Adc *const adc)
+{
+ return (enum adc_cmp_mode)(adc->ADC_EMR & ADC_EMR_CMPMODE_Msk);
+}
+
+/**
+ * \brief Configure ADC compare window.
+ *
+ * \param adc Base address of the ADC.
+ * \param us_low_threshold Low threshold of compare window.
+ * \param us_high_threshold High threshold of compare window.
+ */
+static inline void adc_set_comparison_window(Adc *const adc,
+ const uint16_t us_low_threshold,
+ const uint16_t us_high_threshold)
+{
+ adc->ADC_CWR = ADC_CWR_LOWTHRES(us_low_threshold) |
+ ADC_CWR_HIGHTHRES(us_high_threshold);
+}
+
+/**
+ * \brief Enable or disable write protection of ADC registers.
+ *
+ * \param adc Base address of the ADC.
+ * \param is_enable 1 to enable, 0 to disable.
+ */
+static inline void adc_set_writeprotect(Adc *const adc,
+ const bool is_enable)
+{
+ if (is_enable) {
+ adc->ADC_WPMR = ADC_WPMR_WPEN | ADC_WPMR_WPKEY_PASSWD;
+ } else {
+ adc->ADC_WPMR = ADC_WPMR_WPKEY_PASSWD;
+ }
+}
+
+/**
+ * \brief Indicate write protect status.
+ *
+ * \param adc Base address of the ADC.
+ *
+ * \return 0 if no write protect violation occurred, or 16-bit write protect
+ * violation source.
+ */
+static inline uint32_t adc_get_writeprotect_status(Adc *const adc)
+{
+ uint32_t reg_value;
+
+ reg_value = adc->ADC_WPSR;
+ if (reg_value & ADC_WPSR_WPVS) {
+ return (reg_value & ADC_WPSR_WPVSRC_Msk) >> ADC_WPSR_WPVSRC_Pos;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Get ADC overrun error status.
+ *
+ * \param adc Base address of the ADC.
+ *
+ * \return ADC overrun error status.
+ */
+static inline uint32_t adc_get_overrun_status(Adc *const adc)
+{
+ return adc->ADC_OVER;
+}
+
+/**
+ * \brief Set ADC averaging on single trigger event
+ *
+ * \param adc Base address of the ADC.
+ */
+static inline void adc_average_on_single_trigger(Adc *const adc)
+{
+ adc->ADC_EMR |= ADC_EMR_ASTE_SINGLE_TRIG_AVERAGE;
+}
+
+/**
+ * \brief Set ADC averaging on serval trigger events
+ *
+ * \param adc Base address of the ADC.
+ */
+static inline void adc_average_on_multi_trigger(Adc *const adc)
+{
+ adc->ADC_EMR &= ~ADC_EMR_ASTE_SINGLE_TRIG_AVERAGE;
+}
+
+/**
+ * \brief Start analog-to-digital conversion.
+ *
+ * \note If one of the hardware event is selected as ADC trigger,
+ * this function can NOT start analog to digital conversion.
+ *
+ * \param adc Base address of the ADC.
+ */
+static inline void adc_start_software_conversion(Adc *const adc)
+{
+ adc->ADC_CR = ADC_CR_START;
+}
+
+void adc_set_power_mode(Adc *const adc,
+ const enum adc_power_mode mode);
+
+/**
+ * \brief Enable the specified ADC channel.
+ *
+ * \param adc Base address of the ADC.
+ * \param adc_ch Adc channel number.
+ */
+static inline void adc_channel_enable(Adc *const adc,
+ const enum adc_channel_num adc_ch)
+{
+ if (adc_ch != ADC_CHANNEL_ALL) {
+ adc_ch_sanity_check(adc, adc_ch);
+ }
+
+ adc->ADC_CHER = (adc_ch == ADC_CHANNEL_ALL) ?
+ ADC_CHANNEL_ALL : 1 << adc_ch;
+}
+
+/**
+ * \brief Disable the specified ADC channel.
+ *
+ * \param adc Base address of the ADC.
+ * \param adc_ch Adc channel number.
+ */
+static inline void adc_channel_disable(Adc *const adc,
+ const enum adc_channel_num adc_ch)
+{
+ if (adc_ch != ADC_CHANNEL_ALL) {
+ adc_ch_sanity_check(adc, adc_ch);
+ }
+
+ adc->ADC_CHDR = (adc_ch == ADC_CHANNEL_ALL) ?
+ ADC_CHANNEL_ALL : 1 << adc_ch;
+}
+
+/**
+ * \brief Get the ADC channel status.
+ *
+ * \param adc Base address of the ADC.
+ * \param adc_ch Adc channel number.
+ *
+ * \retval 1 if channel is enabled.
+ * \retval 0 if channel is disabled.
+ */
+static inline uint32_t adc_channel_get_status(Adc *const adc,
+ const enum adc_channel_num adc_ch)
+{
+ adc_ch_sanity_check(adc, adc_ch);
+
+ return adc->ADC_CHSR & (1 << adc_ch);
+}
+
+/**
+ * \brief Read the Converted Data of the selected channel.
+ *
+ * \param adc Base address of the ADC.
+ * \param adc_ch Adc channel number.
+ *
+ * \return ADC converted value of the selected channel.
+ */
+static inline uint32_t adc_channel_get_value(Adc *const adc,
+ enum adc_channel_num adc_ch)
+{
+ adc_ch_sanity_check(adc, adc_ch);
+
+ return adc->ADC_CDR[adc_ch];
+}
+
+/**
+ * \brief Get the Last Data Converted.
+ *
+ * \param adc Base address of the ADC.
+ *
+ * \return ADC latest converted value.
+ */
+static inline uint32_t adc_get_latest_value(Adc *const adc)
+{
+ return adc->ADC_LCDR & ADC_LCDR_LDATA_Msk;
+}
+
+/**
+ * \brief Get the Last Converted Channel Number.
+ *
+ * \param adc Base address of the ADC.
+ *
+ * \return ADC Last Converted Channel Number.
+ */
+static inline uint32_t adc_get_latest_chan_num(Adc *const adc)
+{
+#if SAMG55
+ return (adc->ADC_LCDR & ADC_LCDR_CHNBOSR_Msk) >> ADC_LCDR_CHNBOSR_Pos;
+#else
+ return (adc->ADC_LCDR & ADC_LCDR_CHNB_Msk) >> ADC_LCDR_CHNB_Pos;
+#endif
+}
+
+void adc_enable_interrupt(Adc *const adc,
+ enum adc_interrupt_source interrupt_source);
+
+void adc_disable_interrupt(Adc *const adc,
+ enum adc_interrupt_source interrupt_source);
+
+/**
+ * \brief Get ADC interrupt status.
+ *
+ * \param adc Base address of the ADC.
+ *
+ * \return The interrupt status value.
+ */
+static inline uint32_t adc_get_interrupt_status(Adc *const adc)
+{
+ return adc->ADC_ISR;
+}
+
+/**
+ * \brief Get ADC interrupt mask.
+ *
+ * \param adc Base address of the ADC.
+ *
+ * \return The interrupt mask value.
+ */
+static inline uint32_t adc_get_interrupt_mask(Adc *const adc)
+{
+ return adc->ADC_IMR;
+}
+
+/**
+ * \brief Get PDC registers base address.
+ *
+ * \param adc Base address of the ADC.
+ *
+ * \return Adc Pdc register base address.
+ */
+static inline Pdc *adc_get_pdc_base(Adc *const adc)
+{
+ Pdc *p_pdc_base = NULL;
+
+ if (adc == ADC) {
+ p_pdc_base = PDC_ADC;
+ }
+
+ return p_pdc_base;
+}
+
+/**
+ * \brief Launch an automatic calibration of the ADC on next sequence.
+ *
+ * \param adc Base address of the ADC.
+ *
+ * \retval STATUS_OK An automatic calibration is launched.
+ * \retval STATUS_ERR_BUSY Automatic calibration can not be launched because
+ * the ADC is in freerun mode.
+ */
+static inline enum status_code adc_start_calibration(Adc *const adc)
+{
+ if ((adc->ADC_MR & ADC_MR_FREERUN) == ADC_MR_FREERUN_ON) {
+ return STATUS_ERR_BUSY;
+ }
+
+ adc->ADC_CR = ADC_CR_AUTOCAL;
+ return STATUS_OK;
+}
+
+#if (SAM4N)
+/**
+ * \brief ADC Reference Voltage Selection
+ *
+ * \param adc Base address of the ADC.
+ * \param adc_ref_src The source selection for ADC reference voltage,
+ * ADC_REFER_VOL_EXTERNAL - the external pin ADVREF defines the voltage reference.
+ * ADC_REFER_VOL_STUCK_AT_MIN - the internal reference voltage is stuck at the minimum value
+ * ADC_REFER_VOL_VDDANA - the internal voltage reference is forced to VDDANA. Effective only if ONREF is 1.
+ * ADC_REFER_VOL_IRVS - the internal reference voltage is defined by field IRVS
+ * See the product electrical characteristics for further details.
+ * \param irvs Internal reference volatage selection, only be effective when
+ * adc_ref_src equals to ADC_REFER_VOL_IRVS
+ */
+static inline void adc_ref_vol_sel(Adc *const adc,
+ enum adc_refer_voltage_source adc_ref_src,
+ uint8_t irvs)
+{
+ if (ADC_REFER_VOL_EXTERNAL == adc_ref_src) {
+ adc->ADC_ACR &= ~ADC_ACR_ONREF_EN;
+ } else if (ADC_REFER_VOL_STUCK_AT_MIN == adc_ref_src) {
+ adc->ADC_ACR |= ADC_ACR_ONREF_EN;
+ adc->ADC_ACR &= ~(ADC_ACR_IRVCE_EN | ADC_ACR_FORCEREF_EN);
+ } else if (ADC_REFER_VOL_VDDANA == adc_ref_src) {
+ adc->ADC_ACR |= ADC_ACR_ONREF_EN | ADC_ACR_FORCEREF_EN;
+ } else if (ADC_REFER_VOL_IRVS == adc_ref_src) {
+ adc->ADC_ACR &= ~ADC_ACR_FORCEREF_EN;
+ adc->ADC_ACR |= ADC_ACR_ONREF_EN | ADC_ACR_IRVCE_EN |
+ (irvs << ADC_ACR_IRVS_Pos);
+ }
+}
+#endif
+
+/**
+ * \page sam_adc2_quickstart Quickstart guide for ADC driver
+ *
+ * This is the quickstart guide for the \ref sam_drivers_adc2_group
+ * "ADC2 driver" with step-by-step instructions on how to configure and use
+ * the driver in a selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section adc_basic_use_case Basic use case
+ * In this basic use case, the ADC module and single channel are configured for:
+ * - 10 -bit resolution
+ * - ADC clock frequency is 6MHz
+ * - Start Up Time is 64 periods ADC clock
+ * - Tracking Time is 3 periods of ADC clock
+ * - Transfer Period field shall be programmed with 2 as datasheet said
+ * - The controller converts channels in a simple numeric order
+ * - Appends the channel number to the conversion result in AFE_LDCR register
+ * - Single Trigger is optional to get an averaged value
+ * - Software triggering of conversions
+ * - Single channel measurement
+ * - ADC_CHANNEL_1 of ADC as input
+ *
+ * \subsection sam_adc2_quickstart_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (Sysclock)"
+ *
+ * \section adc_basic_use_case_setup Setup steps
+ * \subsection adc_basic_use_case_setup_code Example code
+ * Add to application C-file:
+ * \code
+ adc_enable();
+ adc_get_config_defaults(&adc_cfg);
+ adc_init(ADC, &adc_cfg);
+ adc_set_trigger(ADC, ADC_TRIG_SW);
+ adc_channel_enable(ADC, ADC_CHANNEL_1);
+\endcode
+ *
+ * \subsection adc_basic_use_case_setup_flow Workflow
+ * -# Enable ADC Module:
+ * - \code adc_enable(); \endcode
+ * -# Get the ADC default configurations:
+ * - \code adc_get_config_defaults(&adc_cfg); \endcode
+ * -# Initialize the ADC Module:
+ * - \code adc_init(ADC, &adc_cfg); \endcode
+ * -# Configure conversion trigger and free run mode:
+ * - \code adc_set_trigger(ADC, ADC_TRIG_SW); \endcode
+ * -# Enable Channel:
+ * - \code adc_channel_enable(ADC, ADC_CHANNEL_1); \endcode
+ *
+ * \section adc_basic_use_case_usage Usage steps
+ * \subsection adc_basic_use_case_usage_code Example code
+ * Add to, e.g., main loop in application C-file:
+ * \code
+ adc_start_software_conversion(ADC);
+ while (adc_get_interrupt_status(ADC) & (1 << ADC_CHANNEL_1));
+ uint32_t result = adc_channel_get_value(ADC, ADC_CHANNEL_1);
+\endcode
+ *
+ * \subsection adc_basic_use_case_usage_flow Workflow
+ * -# Start ADC conversion on channel:
+ * - \code adc_start_software_conversion(ADC); \endcode
+ * -# Wait for the conversion over:
+ * - \code while (adc_get_interrupt_status(ADC) & (1 << ADC_CHANNEL_1));
+\endcode
+ * -# Get the conversion result:
+ * - \code uint32_t result = adc_channel_get_value(ADC, ADC_CHANNEL_1);
+\endcode
+ */
+#endif /* ADC2_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/efc/efc.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,438 @@
+/**
+ * \file
+ *
+ * \brief Enhanced Embedded Flash Controller (EEFC) driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "efc.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /**
+ * \defgroup sam_drivers_efc_group Enhanced Embedded Flash Controller (EEFC)
+ *
+ * The Enhanced Embedded Flash Controller ensures the interface of the Flash
+ * block with the 32-bit internal bus.
+ *
+ * @{
+ */
+
+ /* Address definition for read operation */
+#if (SAM3XA || SAM3U4 || SAM4SD16 || SAM4SD32)
+# define READ_BUFF_ADDR0 IFLASH0_ADDR
+# define READ_BUFF_ADDR1 IFLASH1_ADDR
+#elif (SAM3S || SAM3N || SAM4E || SAM4N || SAMG || SAMV71 || SAMV70 || SAMS70 || SAME70)
+# define READ_BUFF_ADDR IFLASH_ADDR
+#elif (SAM4C || SAM4CP || SAM4CM)
+#if SAM4C32
+# define READ_BUFF_ADDR0 IFLASH0_CNC_ADDR
+# define READ_BUFF_ADDR1 IFLASH1_CNC_ADDR
+#else
+# define READ_BUFF_ADDR IFLASH_CNC_ADDR
+#endif
+#elif (SAM3U || SAM4S)
+# define READ_BUFF_ADDR IFLASH0_ADDR
+#else
+# warning Only reading unique ID for sam3/4 is implemented.
+#endif
+
+ /* Flash Writing Protection Key */
+#define FWP_KEY 0x5Au
+
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM)
+#define EEFC_FCR_FCMD(value) \
+ ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
+#define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR)
+#elif (SAMV71 || SAMV70 || SAMS70 || SAME70)
+#define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR \
+ | EEFC_FSR_UECCELSB | EEFC_FSR_MECCELSB | EEFC_FSR_UECCEMSB | EEFC_FSR_MECCEMSB)
+#else
+#define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE)
+#endif
+
+#ifndef EEFC_FCR_FKEY_PASSWD
+#define EEFC_FCR_FKEY_PASSWD EEFC_FCR_FKEY(FWP_KEY)
+#endif
+
+
+ /*
+ * Local function declaration.
+ * Because they are RAM functions, they need 'extern' declaration.
+ */
+ extern void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr);
+ extern uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr);
+
+ /**
+ * \brief Initialize the EFC controller.
+ *
+ * \param ul_access_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit.
+ * \param ul_fws The number of wait states in cycle (no shift).
+ *
+ * \return 0 if successful.
+ */
+ uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws)
+{
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \
+ SAMV71 || SAMV70 || SAMS70 || SAME70)
+ efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws) | EEFC_FMR_CLOE);
+#else
+ efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws));
+#endif
+ return EFC_RC_OK;
+}
+
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \
+ SAMV71 || SAMV70 || SAMS70 || SAME70)
+/**
+ * \brief Enable code loop optimization.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ */
+void efc_enable_cloe(Efc *p_efc)
+{
+ uint32_t ul_fmr = p_efc->EEFC_FMR;
+ efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_CLOE);
+}
+
+/**
+ * \brief Disable code loop optimization.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ */
+void efc_disable_cloe(Efc *p_efc)
+{
+ uint32_t ul_fmr = p_efc->EEFC_FMR;
+ efc_write_fmr(p_efc, ul_fmr & (~EEFC_FMR_CLOE));
+}
+#endif
+
+
+
+/**
+ * \brief Enable the flash ready interrupt.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ */
+void efc_enable_frdy_interrupt(Efc *p_efc)
+{
+ uint32_t ul_fmr = p_efc->EEFC_FMR;
+
+ efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FRDY);
+}
+
+/**
+ * \brief Disable the flash ready interrupt.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ */
+void efc_disable_frdy_interrupt(Efc *p_efc)
+{
+ uint32_t ul_fmr = p_efc->EEFC_FMR;
+
+ efc_write_fmr(p_efc, ul_fmr & (~EEFC_FMR_FRDY));
+}
+
+#if (SAMV71 || SAMV70 || SAMS70 || SAME70)
+/**
+ * \brief Enable the write protection.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ */
+void efc_enable_write_protection(Efc *p_efc)
+{
+ p_efc->EEFC_WPMR = EEFC_WPMR_WPKEY_PASSWD | EEFC_WPMR_WPEN;
+}
+
+/**
+ * \brief Disable the write protection.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ */
+void efc_disable_write_protection(Efc *p_efc)
+{
+ p_efc->EEFC_WPMR = EEFC_WPMR_WPKEY_PASSWD;
+}
+#else
+/**
+ * \brief Set flash access mode.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ * \param ul_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit.
+ */
+void efc_set_flash_access_mode(Efc *p_efc, uint32_t ul_mode)
+{
+ uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FAM);
+
+ efc_write_fmr(p_efc, ul_fmr | ul_mode);
+}
+
+/**
+ * \brief Get flash access mode.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ *
+ * \return 0 for 128-bit or EEFC_FMR_FAM for 64-bit.
+ */
+uint32_t efc_get_flash_access_mode(Efc *p_efc)
+{
+ return (p_efc->EEFC_FMR & EEFC_FMR_FAM);
+}
+#endif
+
+/**
+ * \brief Set flash wait state.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ * \param ul_fws The number of wait states in cycle (no shift).
+ */
+void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws)
+{
+ uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FWS_Msk);
+
+ efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FWS(ul_fws));
+}
+
+/**
+ * \brief Get flash wait state.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ *
+ * \return The number of wait states in cycle (no shift).
+ */
+uint32_t efc_get_wait_state(Efc *p_efc)
+{
+ return ((p_efc->EEFC_FMR & EEFC_FMR_FWS_Msk) >> EEFC_FMR_FWS_Pos);
+}
+
+/**
+ * \brief Perform the given command and wait until its completion (or an error).
+ *
+ * \note Unique ID commands are not supported, use efc_perform_read_sequence.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ * \param ul_command Command to perform.
+ * \param ul_argument Optional command argument.
+ *
+ * \note This function will automatically choose to use IAP function.
+ *
+ * \return 0 if successful, otherwise returns an error code.
+ */
+uint32_t efc_perform_command(Efc *p_efc, uint32_t ul_command,
+ uint32_t ul_argument)
+{
+ uint32_t result;
+ irqflags_t flags;
+
+ /* Unique ID commands are not supported. */
+ if (ul_command == EFC_FCMD_STUI || ul_command == EFC_FCMD_SPUI) {
+ return EFC_RC_NOT_SUPPORT;
+ }
+
+ flags = cpu_irq_save();
+ /* Use RAM Function. */
+ result = efc_perform_fcr(p_efc,
+ EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(ul_argument) |
+ EEFC_FCR_FCMD(ul_command));
+ cpu_irq_restore(flags);
+ return result;
+}
+
+/**
+ * \brief Get the current status of the EEFC.
+ *
+ * \note This function clears the value of some status bits (FLOCKE, FCMDE).
+ *
+ * \param p_efc Pointer to an EFC instance.
+ *
+ * \return The current status.
+ */
+uint32_t efc_get_status(Efc *p_efc)
+{
+ return p_efc->EEFC_FSR;
+}
+
+/**
+ * \brief Get the result of the last executed command.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ *
+ * \return The result of the last executed command.
+ */
+uint32_t efc_get_result(Efc *p_efc)
+{
+ return p_efc->EEFC_FRR;
+}
+
+/**
+ * \brief Perform read sequence. Supported sequences are read Unique ID and
+ * read User Signature
+ *
+ * \param p_efc Pointer to an EFC instance.
+ * \param ul_cmd_st Start command to perform.
+ * \param ul_cmd_sp Stop command to perform.
+ * \param p_ul_buf Pointer to an data buffer.
+ * \param ul_size Buffer size.
+ *
+ * \return 0 if successful, otherwise returns an error code.
+ */
+__no_inline
+RAMFUNC
+uint32_t efc_perform_read_sequence(Efc *p_efc,
+ uint32_t ul_cmd_st, uint32_t ul_cmd_sp,
+ uint32_t *p_ul_buf, uint32_t ul_size)
+{
+ volatile uint32_t ul_status;
+ uint32_t ul_cnt;
+
+#if (SAM3U4 || SAM3XA || SAM4SD16 || SAM4SD32 || SAM4C32)
+ uint32_t *p_ul_data =
+ (uint32_t *) ((p_efc == EFC0) ?
+ READ_BUFF_ADDR0 : READ_BUFF_ADDR1);
+#elif (SAM3S || SAM4S || SAM3N || SAM3U || SAM4E || SAM4N || SAM4C || SAMG || \
+ SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAMS70 || SAME70)
+ uint32_t *p_ul_data = (uint32_t *) READ_BUFF_ADDR;
+#else
+ return EFC_RC_NOT_SUPPORT;
+#endif
+
+ if (p_ul_buf == NULL) {
+ return EFC_RC_INVALID;
+ }
+
+ p_efc->EEFC_FMR |= (0x1u << 16);
+
+ /* Send the Start Read command */
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \
+ SAMV71 || SAMV70 || SAMS70 || SAME70)
+ p_efc->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0)
+ | EEFC_FCR_FCMD(ul_cmd_st);
+#else
+ p_efc->EEFC_FCR = EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0)
+ | EEFC_FCR_FCMD(ul_cmd_st);
+#endif
+ /* Wait for the FRDY bit in the Flash Programming Status Register
+ * (EEFC_FSR) falls.
+ */
+ do {
+ ul_status = p_efc->EEFC_FSR;
+ } while ((ul_status & EEFC_FSR_FRDY) == EEFC_FSR_FRDY);
+
+ /* The data is located in the first address of the Flash
+ * memory mapping.
+ */
+ for (ul_cnt = 0; ul_cnt < ul_size; ul_cnt++) {
+ p_ul_buf[ul_cnt] = p_ul_data[ul_cnt];
+ }
+
+ /* To stop the read mode */
+ p_efc->EEFC_FCR =
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \
+ SAMV71 || SAMV70 || SAMS70 || SAME70)
+ EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0) |
+ EEFC_FCR_FCMD(ul_cmd_sp);
+#else
+ EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0) |
+ EEFC_FCR_FCMD(ul_cmd_sp);
+#endif
+ /* Wait for the FRDY bit in the Flash Programming Status Register (EEFC_FSR)
+ * rises.
+ */
+ do {
+ ul_status = p_efc->EEFC_FSR;
+ } while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY);
+
+ p_efc->EEFC_FMR &= ~(0x1u << 16);
+
+ return EFC_RC_OK;
+}
+
+/**
+ * \brief Set mode register.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ * \param ul_fmr Value of mode register
+ */
+__no_inline
+RAMFUNC
+void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr)
+{
+ p_efc->EEFC_FMR = ul_fmr;
+}
+
+/**
+ * \brief Perform command.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ * \param ul_fcr Flash command.
+ *
+ * \return The current status.
+ */
+__no_inline
+RAMFUNC
+uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr)
+{
+ volatile uint32_t ul_status;
+
+ p_efc->EEFC_FCR = ul_fcr;
+ do {
+ ul_status = p_efc->EEFC_FSR;
+ } while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY);
+
+ return (ul_status & EEFC_ERROR_FLAGS);
+}
+
+//@}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/efc/efc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,150 @@
+/**
+ * \file
+ *
+ * \brief Embedded Flash Controller (EFC) driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef EFC_H_INCLUDED
+#define EFC_H_INCLUDED
+
+#include "compiler.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /*! \name EFC return codes */
+//! @{
+typedef enum efc_rc {
+ EFC_RC_OK = 0, //!< Operation OK
+ EFC_RC_YES = 0, //!< Yes
+ EFC_RC_NO = 1, //!< No
+ EFC_RC_ERROR = 1, //!< General error
+ EFC_RC_INVALID, //!< Invalid argument input
+ EFC_RC_NOT_SUPPORT = 0xFFFFFFFF //!< Operation is not supported
+} efc_rc_t;
+//! @}
+
+/*! \name EFC command */
+//! @{
+#define EFC_FCMD_GETD 0x00 //!< Get Flash Descriptor
+#define EFC_FCMD_WP 0x01 //!< Write page
+#define EFC_FCMD_WPL 0x02 //!< Write page and lock
+#define EFC_FCMD_EWP 0x03 //!< Erase page and write page
+#define EFC_FCMD_EWPL 0x04 //!< Erase page and write page then lock
+#define EFC_FCMD_EA 0x05 //!< Erase all
+#if (SAM3SD8)
+#define EFC_FCMD_EPL 0x06 //!< Erase plane
+#endif
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \
+ SAMV71 || SAMV70 || SAMS70 || SAME70)
+#define EFC_FCMD_EPA 0x07 //!< Erase pages
+#endif
+#define EFC_FCMD_SLB 0x08 //!< Set Lock Bit
+#define EFC_FCMD_CLB 0x09 //!< Clear Lock Bit
+#define EFC_FCMD_GLB 0x0A //!< Get Lock Bit
+#define EFC_FCMD_SGPB 0x0B //!< Set GPNVM Bit
+#define EFC_FCMD_CGPB 0x0C //!< Clear GPNVM Bit
+#define EFC_FCMD_GGPB 0x0D //!< Get GPNVM Bit
+#define EFC_FCMD_STUI 0x0E //!< Start unique ID
+#define EFC_FCMD_SPUI 0x0F //!< Stop unique ID
+#if (!SAM3U && !SAM3SD8 && !SAM3S8)
+#define EFC_FCMD_GCALB 0x10 //!< Get CALIB Bit
+#endif
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \
+ SAMV71 || SAMV70 || SAMS70 || SAME70)
+#define EFC_FCMD_ES 0x11 //!< Erase sector
+#define EFC_FCMD_WUS 0x12 //!< Write user signature
+#define EFC_FCMD_EUS 0x13 //!< Erase user signature
+#define EFC_FCMD_STUS 0x14 //!< Start read user signature
+#define EFC_FCMD_SPUS 0x15 //!< Stop read user signature
+#endif
+//! @}
+
+/*! The IAP function entry address */
+#define CHIP_FLASH_IAP_ADDRESS (IROM_ADDR + 8)
+
+/*! \name EFC access mode */
+//! @{
+#define EFC_ACCESS_MODE_128 0
+#define EFC_ACCESS_MODE_64 EEFC_FMR_FAM
+//! @}
+
+uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws);
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || \
+ SAMV71 || SAMV70 || SAMS70 || SAME70)
+void efc_enable_cloe(Efc *p_efc);
+void efc_disable_cloe(Efc *p_efc);
+#endif
+void efc_enable_frdy_interrupt(Efc *p_efc);
+void efc_disable_frdy_interrupt(Efc *p_efc);
+#if (SAMV71 || SAMV70 || SAMS70 || SAME70)
+void efc_enable_write_protection(Efc *p_efc);
+void efc_disable_write_protection(Efc *p_efc);
+#else
+void efc_set_flash_access_mode(Efc *p_efc, uint32_t ul_mode);
+uint32_t efc_get_flash_access_mode(Efc *p_efc);
+#endif
+void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws);
+uint32_t efc_get_wait_state(Efc *p_efc);
+uint32_t efc_perform_command(Efc *p_efc, uint32_t ul_command,
+ uint32_t ul_argument);
+uint32_t efc_get_status(Efc *p_efc);
+uint32_t efc_get_result(Efc *p_efc);
+uint32_t efc_perform_read_sequence(Efc *p_efc,
+ uint32_t ul_cmd_st, uint32_t ul_cmd_sp,
+ uint32_t *p_ul_buf, uint32_t ul_size);
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* EFC_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/flexcom/flexcom.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,273 @@
+/**
+ * \file
+ *
+ * \brief FLEXCOM driver for SAM.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "flexcom.h"
+#include "sysclk.h"
+#include "sleepmgr.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+
+ /**
+ * \brief Enable the FLEXCOM module.
+ *
+ * \param p_flexcom Pointer to a FLEXCOM instance.
+ *
+ */
+ void flexcom_enable(Flexcom *p_flexcom)
+{
+ sleepmgr_lock_mode(SLEEPMGR_ACTIVE);
+ /* Enable PMC clock for FLEXCOM */
+#ifdef ID_FLEXCOM7
+ if (p_flexcom == FLEXCOM7) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM7);
+ /* Enable PCK output */
+ pmc_disable_pck(PMC_PCK_7);
+ pmc_switch_pck_to_mck(PMC_PCK_7, PMC_PCK_PRES_CLK_1);
+ pmc_enable_pck(PMC_PCK_7);
+ } else
+#endif
+#ifdef ID_FLEXCOM6
+ if (p_flexcom == FLEXCOM6) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM6);
+ /* Enable PCK output */
+ pmc_disable_pck(PMC_PCK_7);
+ pmc_switch_pck_to_mck(PMC_PCK_7, PMC_PCK_PRES_CLK_1);
+ pmc_enable_pck(PMC_PCK_7);
+ } else
+#endif
+#ifdef ID_FLEXCOM5
+ if (p_flexcom == FLEXCOM5) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM5);
+ /* Enable PCK output */
+ pmc_disable_pck(PMC_PCK_7);
+ pmc_switch_pck_to_mck(PMC_PCK_7, PMC_PCK_PRES_CLK_1);
+ pmc_enable_pck(PMC_PCK_7);
+ } else
+#endif
+#ifdef ID_FLEXCOM4
+ if (p_flexcom == FLEXCOM4) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM4);
+ /* Enable PCK output */
+ pmc_disable_pck(PMC_PCK_7);
+ pmc_switch_pck_to_mck(PMC_PCK_7, PMC_PCK_PRES_CLK_1);
+ pmc_enable_pck(PMC_PCK_7);
+ } else
+#endif
+#ifdef ID_FLEXCOM3
+ if (p_flexcom == FLEXCOM3) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM3);
+ /* Enable PCK output */
+ pmc_disable_pck(PMC_PCK_6);
+ pmc_switch_pck_to_mck(PMC_PCK_6, PMC_PCK_PRES_CLK_1);
+ pmc_enable_pck(PMC_PCK_6);
+ } else
+#endif
+#ifdef ID_FLEXCOM2
+ if (p_flexcom == FLEXCOM2) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM2);
+ /* Enable PCK output */
+ pmc_disable_pck(PMC_PCK_6);
+ pmc_switch_pck_to_mck(PMC_PCK_6, PMC_PCK_PRES_CLK_1);
+ pmc_enable_pck(PMC_PCK_6);
+ } else
+#endif
+#ifdef ID_FLEXCOM1
+ if (p_flexcom == FLEXCOM1) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM1);
+ /* Enable PCK output */
+ pmc_disable_pck(PMC_PCK_6);
+ pmc_switch_pck_to_mck(PMC_PCK_6, PMC_PCK_PRES_CLK_1);
+ pmc_enable_pck(PMC_PCK_6);
+ } else
+#endif
+#ifdef ID_FLEXCOM0
+ if (p_flexcom == FLEXCOM0) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM0);
+ /* Enable PCK output */
+ pmc_disable_pck(PMC_PCK_6);
+ pmc_switch_pck_to_mck(PMC_PCK_6, PMC_PCK_PRES_CLK_1);
+ pmc_enable_pck(PMC_PCK_6);
+ } else
+#endif
+ {
+ Assert(false);
+ }
+}
+
+/**
+ * \brief Disable the FLEXCOM module.
+ *
+ * \param p_flexcom Pointer to a FLEXCOM instance.
+ *
+ */
+void flexcom_disable(Flexcom *p_flexcom)
+{
+ sleepmgr_unlock_mode(SLEEPMGR_ACTIVE);
+ /* Enable PMC clock for FLEXCOM */
+#ifdef ID_FLEXCOM7
+ if (p_flexcom == FLEXCOM7) {
+ sysclk_disable_peripheral_clock(ID_FLEXCOM7);
+ /* Disable PCK output */
+ pmc_disable_pck(PMC_PCK_7);
+ } else
+#endif
+#ifdef ID_FLEXCOM6
+ if (p_flexcom == FLEXCOM6) {
+ sysclk_disable_peripheral_clock(ID_FLEXCOM6);
+ /* Disable PCK output */
+ pmc_disable_pck(PMC_PCK_7);
+ } else
+#endif
+#ifdef ID_FLEXCOM5
+ if (p_flexcom == FLEXCOM5) {
+ sysclk_disable_peripheral_clock(ID_FLEXCOM5);
+ /* Disable PCK output */
+ pmc_disable_pck(PMC_PCK_7);
+ } else
+#endif
+#ifdef ID_FLEXCOM4
+ if (p_flexcom == FLEXCOM4) {
+ sysclk_disable_peripheral_clock(ID_FLEXCOM4);
+ /* Disable PCK output */
+ pmc_disable_pck(PMC_PCK_7);
+ } else
+#endif
+#ifdef ID_FLEXCOM3
+ if (p_flexcom == FLEXCOM3) {
+ sysclk_disable_peripheral_clock(ID_FLEXCOM3);
+ /* Disable PCK output */
+ pmc_disable_pck(PMC_PCK_6);
+ } else
+#endif
+#ifdef ID_FLEXCOM2
+ if (p_flexcom == FLEXCOM2) {
+ sysclk_disable_peripheral_clock(ID_FLEXCOM2);
+ /* Disable PCK output */
+ pmc_disable_pck(PMC_PCK_6);
+ } else
+#endif
+#ifdef ID_FLEXCOM1
+ if (p_flexcom == FLEXCOM1) {
+ sysclk_disable_peripheral_clock(ID_FLEXCOM1);
+ /* Disable PCK output */
+ pmc_disable_pck(PMC_PCK_6);
+ } else
+#endif
+#ifdef ID_FLEXCOM0
+ if (p_flexcom == FLEXCOM0) {
+ /* Disable PCK output */
+ pmc_disable_pck(PMC_PCK_6);
+ sysclk_disable_peripheral_clock(ID_FLEXCOM0);
+ } else
+#endif
+ {
+ Assert(false);
+ }
+}
+
+/**
+ * \brief Set the FLEXCOM opration mode.
+ *
+ * \param p_flexcom Pointer to a FLEXCOM instance.
+ * \param opmode Opration mode.
+ *
+ */
+void flexcom_set_opmode(Flexcom *p_flexcom, enum flexcom_opmode opmode)
+{
+ p_flexcom->FLEXCOM_MR = opmode;
+}
+
+/**
+ * \brief Set the FLEXCOM opration mode.
+ *
+ * \param p_flexcom Pointer to a FLEXCOM instance.
+ * \param opmode Opration mode.
+ *
+ */
+void flexcom_get_opmode(Flexcom *p_flexcom, enum flexcom_opmode *opmode)
+{
+ *opmode = (enum flexcom_opmode)(p_flexcom->FLEXCOM_MR & FLEXCOM_MR_OPMODE_Msk);
+}
+
+/**
+ * \brief Write to the FLEXCOM.
+ *
+ * \param p_flexcom Pointer to a FLEXCOM instance.
+ * \param data Data to be tansfer.
+ *
+ */
+void flexcom_write(Flexcom *p_flexcom, uint32_t data)
+{
+ p_flexcom->FLEXCOM_THR = data;
+}
+
+/**
+ * \brief Read the FLEXCOM data.
+ *
+ * \param p_flexcom Pointer to a FLEXCOM instance.
+ * \param data Data received.
+ *
+ */
+void flexcom_read(Flexcom *p_flexcom, uint32_t *data)
+{
+ *data = p_flexcom->FLEXCOM_RHR;
+}
+
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/flexcom/flexcom.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,137 @@
+/**
+ * \file
+ *
+ * \brief FLEXCOM driver for SAM.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef FLEXCOM_H_INCLUDED
+#define FLEXCOM_H_INCLUDED
+
+#include "compiler.h"
+#include "status_codes.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /**
+ * \defgroup sam_drivers_flexcom_group Flexible Serial Communication Controller
+ * (FLEXCOM) Driver.
+ *
+ * \par Purpose
+ *
+ * The Flexible Serial Communication Controller (FLEXCOM) offers several
+ * serial communication protocols that are managed by the three submodules
+ * USART, SPI, and TWI.
+ * @{
+ */
+
+ /**
+ * FLEXCOM opration Mode
+ */
+enum flexcom_opmode {
+ FLEXCOM_NONE = FLEXCOM_MR_OPMODE_NO_COM,
+ FLEXCOM_USART = FLEXCOM_MR_OPMODE_USART,
+ FLEXCOM_SPI = FLEXCOM_MR_OPMODE_SPI,
+ FLEXCOM_TWI = FLEXCOM_MR_OPMODE_TWI,
+};
+
+void flexcom_enable(Flexcom *p_flexcom);
+void flexcom_disable(Flexcom *p_flexcom);
+void flexcom_set_opmode(Flexcom *p_flexcom, enum flexcom_opmode opmode);
+void flexcom_get_opmode(Flexcom *p_flexcom, enum flexcom_opmode *opmode);
+void flexcom_write(Flexcom *p_flexcom, uint32_t data);
+void flexcom_read(Flexcom *p_flexcom, uint32_t *data);
+
+/** @} */
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/**
+ * \page sam_flexcom_quickstart Quickstart guide for SAM FLEXCOM module
+ *
+ * This is the quickstart guide for the "SAM FLEXCOM module", with
+ * instructions on how to configure and use the module in a selection of use
+ * cases. All details related to these submodules(USART/SPI/TWI)
+ * are provided in independent sections.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g.the main application function.
+ *
+ * \section flexcom_use_cases FLEXCOM use cases
+ * - \ref flexcom_basic_use_case
+ *
+ * \section flexcom_basic_use_case Basic use case
+ *
+ * \subsection sam_flexcom_quickstart_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (Sysclock)"
+ *
+ *
+ * \section flexcom_basic_use_case_setup Setup steps
+ * \subsection flexcom_basic_use_case_setup_code Example code
+ * -# Enable flexcom module access:
+ * - \code flexcom_enable(FLEXCOM0); \endcode
+ * -# Set flexcom operation module:
+ * - \code flexcom_set_opmode(FLEXCOM0, FLEXCOM_USART); \endcode
+ *
+ * \section flexcom_basic_use_case_usage Usage steps
+ * \subsection flexcom_basic_use_case_usage_flow Workflow
+ * -# Use write/read function to access the data
+ * \code
+ flexcom_write(FLEXCOM0, data);
+ flexcom_read(FLEXCOM0, &data);
+ \endcode
+ */
+
+#endif /* FLEXCOM_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pdc/pdc.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,334 @@
+/**
+ * \file
+ *
+ * \brief SAM4 Peripheral DMA Controller (PDC) driver.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "pdc.h"
+
+/// @cond
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /**
+ * \brief Configure PDC for data transmit.
+ *
+ * \param[out] p_pdc Device structure pointer
+ * \param[in] p_packet Pointer to packet information for current buffer register
+ * set. Use NULL to leave unaltered.
+ * \param[in] p_next_packet Pointer to packet information for next buffer register
+ * set. Use NULL to leave unaltered.
+ */
+ void pdc_tx_init(
+ Pdc *p_pdc,
+ pdc_packet_t *p_packet,
+ pdc_packet_t *p_next_packet)
+{
+ /* Validate inputs. */
+ Assert(p_pdc);
+
+ if (p_packet) {
+ p_pdc->PERIPH_TPR = p_packet->ul_addr;
+ p_pdc->PERIPH_TCR = p_packet->ul_size;
+ }
+ if (p_next_packet) {
+ p_pdc->PERIPH_TNPR = p_next_packet->ul_addr;
+ p_pdc->PERIPH_TNCR = p_next_packet->ul_size;
+ }
+}
+
+/**
+ * \brief Configure PDC for data receive.
+ *
+ * \param[out] p_pdc Device structure pointer
+ * \param[in] p_packet Pointer to packet information for current buffer register
+ * set. Use NULL to leave unaltered.
+ * \param[in] p_next_packet Pointer to packet information for next buffer register
+ * set. Use NULL to leave unaltered.
+ */
+void pdc_rx_init(
+ Pdc *p_pdc,
+ pdc_packet_t *p_packet,
+ pdc_packet_t *p_next_packet)
+{
+ /* Validate inputs. */
+ Assert(p_pdc);
+
+ if (p_packet) {
+ p_pdc->PERIPH_RPR = p_packet->ul_addr;
+ p_pdc->PERIPH_RCR = p_packet->ul_size;
+ }
+ if (p_next_packet) {
+ p_pdc->PERIPH_RNPR = p_next_packet->ul_addr;
+ p_pdc->PERIPH_RNCR = p_next_packet->ul_size;
+ }
+}
+
+/**
+ * \brief Clear PDC buffer receive counter.
+ *
+ * \param[out] p_pdc Device structure pointer
+ */
+void pdc_rx_clear_cnt(
+ Pdc *p_pdc)
+{
+ /* Validate inputs. */
+ Assert(p_pdc);
+
+ p_pdc->PERIPH_RNCR = 0;
+ p_pdc->PERIPH_RCR = 0;
+}
+
+/**
+ * \brief Enable PDC transfers (TX and/or RX).
+ *
+ * \note It is forbidden to set both TXTEN and RXTEN for a half duplex
+ * peripheral.
+ *
+ * \param[out] p_pdc Device structure pointer
+ * \param[in] ul_controls Transfer directions
+ * (bit PERIPH_PTCR_RXTEN and bit PERIPH_PTCR_TXTEN)
+ */
+void pdc_enable_transfer(
+ Pdc *p_pdc,
+ uint32_t ul_controls)
+{
+ /* Validate inputs. */
+ Assert(p_pdc);
+
+ p_pdc->PERIPH_PTCR =
+ ul_controls & (PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);
+}
+
+/**
+ * \brief Disable PDC transfers (TX and/or RX).
+ *
+ * \param[out] p_pdc Device structure pointer
+ * \param[in] ul_controls Transfer directions
+ * (bit PERIPH_PTCR_TXTDIS, bit PERIPH_PTCR_TXTDIS)
+ */
+void pdc_disable_transfer(
+ Pdc *p_pdc,
+ uint32_t ul_controls)
+{
+ /* Validate inputs. */
+ Assert(p_pdc);
+
+ p_pdc->PERIPH_PTCR =
+ ul_controls & (PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);
+}
+
+/**
+ * \brief Read PDC status.
+ *
+ * \param[in] p_pdc Device structure pointer
+ *
+ * \return PDC status register bit map.
+ *
+ * <table>
+ * <tr>
+ * <th>Name</th>
+ * <th>Description</th>
+ * <th>Bit</th>
+ * </tr>
+ * <tr>
+ * <td>RXTEN</td>
+ * <td>Receiver Transfer Enabled</td>
+ * <td>8</td>
+ * </tr>
+ * <tr>
+ * <td>TXTEN</td>
+ * <td>Transmitter Transfer Enabled</td>
+ * <td>1</td>
+ * </tr>
+ * </table>
+ *
+ */
+uint32_t pdc_read_status(
+ Pdc *p_pdc)
+{
+ /* Validate inputs. */
+ Assert(p_pdc);
+
+ return p_pdc->PERIPH_PTSR;
+}
+
+/**
+ * \brief Return Receive Pointer Register (RPR) value.
+ *
+ * \param[in] p_pdc Device structure pointer
+ *
+ * \return Receive Pointer Register value.
+ */
+uint32_t pdc_read_rx_ptr(
+ Pdc *p_pdc)
+{
+ /* Validate inputs. */
+ Assert(p_pdc);
+
+ return p_pdc->PERIPH_RPR;
+}
+
+/**
+ * \brief Return Receive Counter Register (RCR) value.
+ *
+ * \param[in] p_pdc Device structure pointer
+ *
+ * \return Receive Counter Register value.
+ */
+uint32_t pdc_read_rx_counter(
+ Pdc *p_pdc)
+{
+ /* Validate inputs. */
+ Assert(p_pdc);
+
+ return p_pdc->PERIPH_RCR;
+}
+
+/**
+ * \brief Return Transmit Pointer Register (TPR) value.
+ *
+ * \param[in] p_pdc Device structure pointer
+ *
+ * \return Transmit Pointer Register value.
+ */
+uint32_t pdc_read_tx_ptr(
+ Pdc *p_pdc)
+{
+ /* Validate inputs. */
+ Assert(p_pdc);
+
+ return p_pdc->PERIPH_TPR;
+}
+
+/**
+ * \brief Return Transmit Counter Register (TCR) value.
+ *
+ * \param[in] p_pdc Device structure pointer
+ *
+ * \return Transmit Counter Register value.
+ */
+uint32_t pdc_read_tx_counter(
+ Pdc *p_pdc)
+{
+ /* Validate inputs. */
+ Assert(p_pdc);
+
+ return p_pdc->PERIPH_TCR;
+}
+
+/**
+ * \brief Return Receive Next Pointer Register (RNPR) value.
+ *
+ * \param[in] p_pdc Device structure pointer
+ *
+ * \return Receive Next Pointer Register value.
+ */
+uint32_t pdc_read_rx_next_ptr(
+ Pdc *p_pdc)
+{
+ /* Validate inputs. */
+ Assert(p_pdc);
+
+ return p_pdc->PERIPH_RNPR;
+}
+
+/**
+ * \brief Return Receive Next Counter Register (RNCR) value.
+ *
+ * \param[in] p_pdc Device structure pointer
+ *
+ * \return Receive Next Counter Register value.
+ */
+uint32_t pdc_read_rx_next_counter(
+ Pdc *p_pdc)
+{
+ /* Validate inputs. */
+ Assert(p_pdc);
+
+ return p_pdc->PERIPH_RNCR;
+}
+
+/**
+ * \brief Return Transmit Next Pointer Register (TNPR) value.
+ *
+ * \param[in] p_pdc Device structure pointer
+ *
+ * \return Transmit Next Pointer Register value.
+ */
+uint32_t pdc_read_tx_next_ptr(
+ Pdc *p_pdc)
+{
+ /* Validate inputs. */
+ Assert(p_pdc);
+
+ return p_pdc->PERIPH_TNPR;
+}
+
+/**
+ * \brief Return Transmit Next Counter Register (TNCR) value.
+ *
+ * \param[in] p_pdc Device structure pointer
+ *
+ * \return Transmit Next Counter Register value.
+ */
+uint32_t pdc_read_tx_next_counter(
+ Pdc *p_pdc)
+{
+ /* Validate inputs. */
+ Assert(p_pdc);
+
+ return p_pdc->PERIPH_TNCR;
+}
+
+/// @cond
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pdc/pdc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,323 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral DMA Controller (PDC) driver.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef PDC_H_INCLUDED
+#define PDC_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam_drivers_pdc_group SAM3A/3N/3S/3U/3X/4E/4N/4S/G Peripheral DMA Controller (PDC) Driver
+ * This driver for Atmel® | SMART ARM®-based microcontrollers provides
+ * an interface for the configuration and management of the the Peripheral
+ * Direct Memory Access (DMA) Controller (PDC) module.
+ *
+ * The PDC transfers data between on-chip serial peripherals and the on and/or
+ * off-chip memories. The link between the PDC and a serial peripheral is
+ * operated by the AHB to ABP bridge.
+ *
+ * This module:
+ * - Performs transfers to/from APB communication serial peripherals
+ * - Supports half-duplex and full-duplex peripherals
+ *
+ * Devices from the following series can use this module:
+ * - Atmel | SMART SAM3A
+ * - Atmel | SMART SAM3N
+ * - Atmel | SMART SAM3S
+ * - Atmel | SMART SAM3U
+ * - Atmel | SMART SAM3X
+ * - Atmel | SMART SAM4E
+ * - Atmel | SMART SAM4N
+ * - Atmel | SMART SAM4S
+ * - Atmel | SMART SAM G
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam_drivers_pdc_prerequisites
+ * - \ref asfdoc_sam_drivers_pdc_module_overview
+ * - \ref asfdoc_sam_drivers_pdc_special_considerations
+ * - \ref asfdoc_sam_drivers_pdc_extra_info
+ * - \ref asfdoc_sam_drivers_pdc_examples
+ * - \ref asfdoc_sam_drivers_pdc_api_overview
+ *
+ *
+ * \section asfdoc_sam_drivers_pdc_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam_drivers_pdc_module_overview Module Overview
+ * The user interface of each PDC channel is integrated into the user interface
+ * of the peripheral it serves. The user interface of unidirectional channels
+ * (receive only or transmit only), contains two 32-bit memory pointers and
+ * two 16-bit counters, one set (pointer, counter) for current transfer and
+ * one set (pointer, counter) for next transfer. The bidirectional channel
+ * user interface contains four 32-bit memory pointers and four 16-bit counters.
+ * Each set (pointer, counter) is used by current transmit, next transmit,
+ * current receive and next receive. Using the PDC removes processor overhead
+ * by reducing its intervention during the transfer. This significantly reduces
+ * the number of clock cycles required for a data transfer, which improves
+ * microcontroller performance. To launch a transfer, the peripheral triggers
+ * its associated PDC channels by using transmit and receive signals.
+ * When the programmed data is transferred, an end of transfer interrupt is
+ * generated by the peripheral itself.
+ *
+ * \section asfdoc_sam_drivers_pdc_special_considerations Special Considerations
+ * There are no special considerations for this module.
+ *
+ *
+ * \section asfdoc_sam_drivers_pdc_extra_info Extra Information
+
+ * For extra information, see \ref asfdoc_sam_drivers_pdc_extra. This includes:
+ * - \ref asfdoc_sam_drivers_pdc_extra_acronyms
+ * - \ref asfdoc_sam_drivers_pdc_extra_dependencies
+ * - \ref asfdoc_sam_drivers_pdc_extra_errata
+ * - \ref asfdoc_sam_drivers_pdc_extra_history
+ *
+ * \section asfdoc_sam_drivers_pdc_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam_drivers_pdc_exqsg.
+ *
+ *
+ * \section asfdoc_sam_drivers_pdc_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+
+/// @cond
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /**
+ * \brief PDC data packet for transfer.
+ */
+ typedef struct pdc_packet {
+ /** Start address of the transfer packet data. */
+ uint32_t ul_addr;
+ /** Transfer packet size (in units of the peripheral data width). */
+ uint32_t ul_size;
+ } pdc_packet_t;
+
+ void pdc_tx_init(Pdc *p_pdc, pdc_packet_t *p_packet,
+ pdc_packet_t *p_next_packet);
+ void pdc_rx_init(Pdc *p_pdc, pdc_packet_t *p_packet,
+ pdc_packet_t *p_next_packet);
+ void pdc_rx_clear_cnt(Pdc *p_pdc);
+ void pdc_enable_transfer(Pdc *p_pdc, uint32_t ul_controls);
+ void pdc_disable_transfer(Pdc *p_pdc, uint32_t ul_controls);
+ uint32_t pdc_read_status(Pdc *p_pdc);
+ uint32_t pdc_read_rx_ptr(Pdc *p_pdc);
+ uint32_t pdc_read_rx_counter(Pdc *p_pdc);
+ uint32_t pdc_read_tx_ptr(Pdc *p_pdc);
+ uint32_t pdc_read_tx_counter(Pdc *p_pdc);
+ uint32_t pdc_read_rx_next_ptr(Pdc *p_pdc);
+ uint32_t pdc_read_rx_next_counter(Pdc *p_pdc);
+ uint32_t pdc_read_tx_next_ptr(Pdc *p_pdc);
+ uint32_t pdc_read_tx_next_counter(Pdc *p_pdc);
+
+/// @cond
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/** @} */
+
+/**
+ * \page asfdoc_sam_drivers_pdc_extra Extra Information for Peripheral DMA Controller
+ *
+ * \section asfdoc_sam_drivers_pdc_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Definition</th>
+ * </tr>
+ * </tr>
+ * <tr>
+ * <td>AHB</td>
+ * <td>Advanced High-performance Bus</td>
+ * </tr>
+ * <tr>
+ * <td>AMBA</td>
+ * <td> Advanced Microcontroller Bus Architecture</td>
+ * </tr>
+ * <tr>
+ * <td>QSG</td>
+ * <td>Quick Start Guide</td>
+ *
+ * </tr>
+ * <tr>
+ * <td>RCR</td>
+ * <td>Receive Counter Register</td>
+ * </tr>
+ * <tr>
+ * <td>RNCR</td>
+ * <td>Return Receive Next Counter Register</td>
+ * </tr>
+ * <tr>
+ * <td>RNPR</td>
+ * <td>Receive Next Pointer Register</td>
+ * </tr>
+ * <tr>
+ * <td>RPR</td>
+ * <td>Receive Pointer Register</td>
+ * </tr>
+ * <tr>
+ * <td>TCR</td>
+ * <td>Transmit Counter Register</td>
+ * </tr>
+ * <tr>
+ * <td>TNCR</td>
+ * <td>Transmit Next Counter Register</td>
+ * </tr>
+ * <tr>
+ * <td>TNPR</td>
+ * <td>Transmit Next Pointer Register</td>
+ * </tr>
+ * <tr>
+ * <td>TPR</td>
+ * <td>Transmit Pointer Register</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam_drivers_pdc_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - None
+ *
+ *
+ * \section asfdoc_sam_drivers_pdc_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam_drivers_pdc_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>Initial document release</td>
+ * </tr>
+ * </table>
+ *
+ *
+ *
+ * \page asfdoc_sam_pdc_quickstart_basic Quick Start Guide for PDC - Basic
+ * This is the quickstart guide for \ref asfdoc_sam_drivers_pdc_group
+ * with step-by-step instructions on how to configure and use the driver.
+ *
+ *
+ * A handler is required for the interrupt, below is a simple example:
+ * \snippet pdc_uart_example.c int_handler
+ *
+ * First initialise the board:
+ *
+ * \snippet pdc_uart_example.c board_setup
+ *
+ * Now setup the PDC registers:
+ * \snippet pdc_uart_example.c pdc_config
+ *
+ * Enable UART IRQ:
+ * \snippet pdc_uart_example.c uart_irq
+ *
+ * Enable UART interrupt
+ * \snippet pdc_uart_example.c uart_nvic_irq
+ *
+ * Once the required number of bytes have been transferred, an interrupt is
+ * triggered and the handler will run. The main program may execute other code
+ * or be busy-waiting:
+ *
+ * \snippet pdc_uart_example.c busy_waiting
+ *
+ * \page asfdoc_sam_drivers_pdc_exqsg Examples for Peripheral DMA Controller
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam_drivers_pdc_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam_pdc_quickstart_basic
+ * - \subpage asfdoc_sam_drivers_pdc_example
+ *
+ *
+ * \page asfdoc_sam_drivers_pdc_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>42316B</td>
+ * <td>07/2015</td>
+ * <td>Updated title of application note and added list of supported devices</td>
+ * </tr>
+ * <tr>
+ * <td>42316A</td>
+ * <td>05/2014</td>
+ * <td>Initial document release</td>
+ * </tr>
+ * </table>
+ *
+ */
+
+#endif /* PDC_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,1460 @@
+/**
+ * \file
+ *
+ * \brief Parallel Input/Output (PIO) Controller driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "pio.h"
+
+#ifndef PIO_WPMR_WPKEY_PASSWD
+# define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494Fu)
+#endif
+
+/**
+ * \defgroup sam_drivers_pio_group Peripheral Parallel Input/Output (PIO) Controller
+ *
+ * \par Purpose
+ *
+ * The Parallel Input/Output Controller (PIO) manages up to 32 fully
+ * programmable input/output lines. Each I/O line may be dedicated as a
+ * general-purpose I/O or be assigned to a function of an embedded peripheral.
+ * This assures effective optimization of the pins of a product.
+ *
+ * @{
+ */
+
+#ifndef FREQ_SLOW_CLOCK_EXT
+/* External slow clock frequency (hz) */
+#define FREQ_SLOW_CLOCK_EXT 32768
+#endif
+
+/**
+ * \brief Configure PIO internal pull-up.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Bitmask of one or more pin(s) to configure.
+ * \param ul_pull_up_enable Indicates if the pin(s) internal pull-up shall be
+ * configured.
+ */
+void pio_pull_up(Pio *p_pio, const uint32_t ul_mask,
+ const uint32_t ul_pull_up_enable)
+{
+ /* Enable the pull-up(s) if necessary */
+ if (ul_pull_up_enable) {
+ p_pio->PIO_PUER = ul_mask;
+ } else {
+ p_pio->PIO_PUDR = ul_mask;
+ }
+}
+
+/**
+ * \brief Configure Glitch or Debouncing filter for the specified input(s).
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Bitmask of one or more pin(s) to configure.
+ * \param ul_cut_off Cuts off frequency for debouncing filter.
+ */
+void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask,
+ const uint32_t ul_cut_off)
+{
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ /* Set Debouncing, 0 bit field no effect */
+ p_pio->PIO_IFSCER = ul_mask;
+#elif (SAM3XA || SAM3U)
+ /* Set Debouncing, 0 bit field no effect */
+ p_pio->PIO_DIFSR = ul_mask;
+#else
+#error "Unsupported device"
+#endif
+
+ /*
+ * The debouncing filter can filter a pulse of less than 1/2 Period of a
+ * programmable Divided Slow Clock:
+ * Tdiv_slclk = ((DIV+1)*2).Tslow_clock
+ */
+ p_pio->PIO_SCDR = PIO_SCDR_DIV((FREQ_SLOW_CLOCK_EXT /
+ (2 * (ul_cut_off))) - 1);
+}
+
+/**
+ * \brief Set a high output level on all the PIOs defined in ul_mask.
+ * This has no immediate effects on PIOs that are not output, but the PIO
+ * controller will save the value if they are changed to outputs.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Bitmask of one or more pin(s) to configure.
+ */
+void pio_set(Pio *p_pio, const uint32_t ul_mask)
+{
+ p_pio->PIO_SODR = ul_mask;
+}
+
+/**
+ * \brief Set a low output level on all the PIOs defined in ul_mask.
+ * This has no immediate effects on PIOs that are not output, but the PIO
+ * controller will save the value if they are changed to outputs.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Bitmask of one or more pin(s) to configure.
+ */
+void pio_clear(Pio *p_pio, const uint32_t ul_mask)
+{
+ p_pio->PIO_CODR = ul_mask;
+}
+
+/**
+ * \brief Return 1 if one or more PIOs of the given Pin instance currently have
+ * a high level; otherwise returns 0. This method returns the actual value that
+ * is being read on the pin. To return the supposed output value of a pin, use
+ * pio_get_output_data_status() instead.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_type PIO type.
+ * \param ul_mask Bitmask of one or more pin(s) to configure.
+ *
+ * \retval 1 at least one PIO currently has a high level.
+ * \retval 0 all PIOs have a low level.
+ */
+uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type,
+ const uint32_t ul_mask)
+{
+ uint32_t ul_reg;
+
+ if ((ul_type == PIO_OUTPUT_0) || (ul_type == PIO_OUTPUT_1)) {
+ ul_reg = p_pio->PIO_ODSR;
+ } else {
+ ul_reg = p_pio->PIO_PDSR;
+ }
+
+ if ((ul_reg & ul_mask) == 0) {
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
+/**
+ * \brief Configure IO of a PIO controller as being controlled by a specific
+ * peripheral.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_type PIO type.
+ * \param ul_mask Bitmask of one or more pin(s) to configure.
+ */
+void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type,
+ const uint32_t ul_mask)
+{
+ uint32_t ul_sr;
+
+ /* Disable interrupts on the pin(s) */
+ p_pio->PIO_IDR = ul_mask;
+
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ switch (ul_type) {
+ case PIO_PERIPH_A:
+ ul_sr = p_pio->PIO_ABCDSR[0];
+ p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr);
+
+ ul_sr = p_pio->PIO_ABCDSR[1];
+ p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr);
+ break;
+ case PIO_PERIPH_B:
+ ul_sr = p_pio->PIO_ABCDSR[0];
+ p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr);
+
+ ul_sr = p_pio->PIO_ABCDSR[1];
+ p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr);
+ break;
+#if (!SAMG)
+ case PIO_PERIPH_C:
+ ul_sr = p_pio->PIO_ABCDSR[0];
+ p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr);
+
+ ul_sr = p_pio->PIO_ABCDSR[1];
+ p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr);
+ break;
+ case PIO_PERIPH_D:
+ ul_sr = p_pio->PIO_ABCDSR[0];
+ p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr);
+
+ ul_sr = p_pio->PIO_ABCDSR[1];
+ p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr);
+ break;
+#endif
+ /* Other types are invalid in this function */
+ case PIO_INPUT:
+ case PIO_OUTPUT_0:
+ case PIO_OUTPUT_1:
+ case PIO_NOT_A_PIN:
+ return;
+ }
+#elif (SAM3XA|| SAM3U)
+ switch (ul_type) {
+ case PIO_PERIPH_A:
+ ul_sr = p_pio->PIO_ABSR;
+ p_pio->PIO_ABSR &= (~ul_mask & ul_sr);
+ break;
+
+ case PIO_PERIPH_B:
+ ul_sr = p_pio->PIO_ABSR;
+ p_pio->PIO_ABSR = (ul_mask | ul_sr);
+ break;
+
+ // other types are invalid in this function
+ case PIO_INPUT:
+ case PIO_OUTPUT_0:
+ case PIO_OUTPUT_1:
+ case PIO_NOT_A_PIN:
+ return;
+ }
+#else
+#error "Unsupported device"
+#endif
+
+ /* Remove the pins from under the control of PIO */
+ p_pio->PIO_PDR = ul_mask;
+}
+
+/**
+ * \brief Configure one or more pin(s) or a PIO controller as inputs.
+ * Optionally, the corresponding internal pull-up(s) and glitch filter(s) can
+ * be enabled.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Bitmask indicating which pin(s) to configure as input(s).
+ * \param ul_attribute PIO attribute(s).
+ */
+void pio_set_input(Pio *p_pio, const uint32_t ul_mask,
+ const uint32_t ul_attribute)
+{
+ pio_disable_interrupt(p_pio, ul_mask);
+ pio_pull_up(p_pio, ul_mask, ul_attribute & PIO_PULLUP);
+
+ /* Enable Input Filter if necessary */
+ if (ul_attribute & (PIO_DEGLITCH | PIO_DEBOUNCE)) {
+ p_pio->PIO_IFER = ul_mask;
+ } else {
+ p_pio->PIO_IFDR = ul_mask;
+ }
+
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ /* Enable de-glitch or de-bounce if necessary */
+ if (ul_attribute & PIO_DEGLITCH) {
+ p_pio->PIO_IFSCDR = ul_mask;
+ } else {
+ if (ul_attribute & PIO_DEBOUNCE) {
+ p_pio->PIO_IFSCER = ul_mask;
+ }
+ }
+#elif (SAM3XA|| SAM3U)
+ /* Enable de-glitch or de-bounce if necessary */
+ if (ul_attribute & PIO_DEGLITCH) {
+ p_pio->PIO_SCIFSR = ul_mask;
+ } else {
+ if (ul_attribute & PIO_DEBOUNCE) {
+ p_pio->PIO_DIFSR = ul_mask;
+ }
+ }
+#else
+#error "Unsupported device"
+#endif
+
+ /* Configure pin as input */
+ p_pio->PIO_ODR = ul_mask;
+ p_pio->PIO_PER = ul_mask;
+}
+
+/**
+ * \brief Configure one or more pin(s) of a PIO controller as outputs, with
+ * the given default value. Optionally, the multi-drive feature can be enabled
+ * on the pin(s).
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Bitmask indicating which pin(s) to configure.
+ * \param ul_default_level Default level on the pin(s).
+ * \param ul_multidrive_enable Indicates if the pin(s) shall be configured as
+ * open-drain.
+ * \param ul_pull_up_enable Indicates if the pin shall have its pull-up
+ * activated.
+ */
+void pio_set_output(Pio *p_pio, const uint32_t ul_mask,
+ const uint32_t ul_default_level,
+ const uint32_t ul_multidrive_enable,
+ const uint32_t ul_pull_up_enable)
+{
+ pio_disable_interrupt(p_pio, ul_mask);
+ pio_pull_up(p_pio, ul_mask, ul_pull_up_enable);
+
+ /* Enable multi-drive if necessary */
+ if (ul_multidrive_enable) {
+ p_pio->PIO_MDER = ul_mask;
+ } else {
+ p_pio->PIO_MDDR = ul_mask;
+ }
+
+ /* Set default value */
+ if (ul_default_level) {
+ p_pio->PIO_SODR = ul_mask;
+ } else {
+ p_pio->PIO_CODR = ul_mask;
+ }
+
+ /* Configure pin(s) as output(s) */
+ p_pio->PIO_OER = ul_mask;
+ p_pio->PIO_PER = ul_mask;
+}
+
+/**
+ * \brief Perform complete pin(s) configuration; general attributes and PIO init
+ * if necessary.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_type PIO type.
+ * \param ul_mask Bitmask of one or more pin(s) to configure.
+ * \param ul_attribute Pins attributes.
+ *
+ * \return Whether the pin(s) have been configured properly.
+ */
+uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type,
+ const uint32_t ul_mask, const uint32_t ul_attribute)
+{
+ /* Configure pins */
+ switch (ul_type) {
+ case PIO_PERIPH_A:
+ case PIO_PERIPH_B:
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ case PIO_PERIPH_C:
+ case PIO_PERIPH_D:
+#endif
+ pio_set_peripheral(p_pio, ul_type, ul_mask);
+ pio_pull_up(p_pio, ul_mask, (ul_attribute & PIO_PULLUP));
+ break;
+
+ case PIO_INPUT:
+ pio_set_input(p_pio, ul_mask, ul_attribute);
+ break;
+
+ case PIO_OUTPUT_0:
+ case PIO_OUTPUT_1:
+ pio_set_output(p_pio, ul_mask, (ul_type == PIO_OUTPUT_1),
+ (ul_attribute & PIO_OPENDRAIN) ? 1 : 0,
+ (ul_attribute & PIO_PULLUP) ? 1 : 0);
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 1;
+}
+
+/**
+ * \brief Return 1 if one or more PIOs of the given Pin are configured to
+ * output a high level (even if they are not output).
+ * To get the actual value of the pin, use PIO_Get() instead.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Bitmask of one or more pin(s).
+ *
+ * \retval 1 At least one PIO is configured to output a high level.
+ * \retval 0 All PIOs are configured to output a low level.
+ */
+uint32_t pio_get_output_data_status(const Pio *p_pio,
+ const uint32_t ul_mask)
+{
+ if ((p_pio->PIO_ODSR & ul_mask) == 0) {
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
+/**
+ * \brief Configure PIO pin multi-driver.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Bitmask of one or more pin(s) to configure.
+ * \param ul_multi_driver_enable Indicates if the pin(s) multi-driver shall be
+ * configured.
+ */
+void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask,
+ const uint32_t ul_multi_driver_enable)
+{
+ /* Enable the multi-driver if necessary */
+ if (ul_multi_driver_enable) {
+ p_pio->PIO_MDER = ul_mask;
+ } else {
+ p_pio->PIO_MDDR = ul_mask;
+ }
+}
+
+/**
+ * \brief Get multi-driver status.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return The multi-driver mask value.
+ */
+uint32_t pio_get_multi_driver_status(const Pio *p_pio)
+{
+ return p_pio->PIO_MDSR;
+}
+
+
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Configure PIO pin internal pull-down.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Bitmask of one or more pin(s) to configure.
+ * \param ul_pull_down_enable Indicates if the pin(s) internal pull-down shall
+ * be configured.
+ */
+void pio_pull_down(Pio *p_pio, const uint32_t ul_mask,
+ const uint32_t ul_pull_down_enable)
+{
+ /* Enable the pull-down if necessary */
+ if (ul_pull_down_enable) {
+ p_pio->PIO_PPDER = ul_mask;
+ } else {
+ p_pio->PIO_PPDDR = ul_mask;
+ }
+}
+#endif
+
+/**
+ * \brief Enable PIO output write for synchronous data output.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Bitmask of one or more pin(s) to configure.
+ */
+void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask)
+{
+ p_pio->PIO_OWER = ul_mask;
+}
+
+/**
+ * \brief Disable PIO output write.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Bitmask of one or more pin(s) to configure.
+ */
+void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask)
+{
+ p_pio->PIO_OWDR = ul_mask;
+}
+
+/**
+ * \brief Read PIO output write status.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return The output write mask value.
+ */
+uint32_t pio_get_output_write_status(const Pio *p_pio)
+{
+ return p_pio->PIO_OWSR;
+}
+
+/**
+ * \brief Synchronously write on output pins.
+ * \note Only bits unmasked by PIO_OWSR (Output Write Status Register) are
+ * written.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Bitmask of one or more pin(s) to configure.
+ */
+void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask)
+{
+ p_pio->PIO_ODSR = ul_mask;
+}
+
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Configure PIO pin schmitt trigger. By default the Schmitt trigger is
+ * active.
+ * Disabling the Schmitt Trigger is requested when using the QTouch Library.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Bitmask of one or more pin(s) to configure.
+ */
+void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask)
+{
+ p_pio->PIO_SCHMITT = ul_mask;
+}
+
+/**
+ * \brief Get PIO pin schmitt trigger status.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return The schmitt trigger mask value.
+ */
+uint32_t pio_get_schmitt_trigger(const Pio *p_pio)
+{
+ return p_pio->PIO_SCHMITT;
+}
+#endif
+
+/**
+ * \brief Configure the given interrupt source.
+ * Interrupt can be configured to trigger on rising edge, falling edge,
+ * high level, low level or simply on level change.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Interrupt source bit map.
+ * \param ul_attr Interrupt source attributes.
+ */
+void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask,
+ const uint32_t ul_attr)
+{
+ /* Configure additional interrupt mode registers. */
+ if (ul_attr & PIO_IT_AIME) {
+ /* Enable additional interrupt mode. */
+ p_pio->PIO_AIMER = ul_mask;
+
+ /* If bit field of the selected pin is 1, set as
+ Rising Edge/High level detection event. */
+ if (ul_attr & PIO_IT_RE_OR_HL) {
+ /* Rising Edge or High Level */
+ p_pio->PIO_REHLSR = ul_mask;
+ } else {
+ /* Falling Edge or Low Level */
+ p_pio->PIO_FELLSR = ul_mask;
+ }
+
+ /* If bit field of the selected pin is 1, set as
+ edge detection source. */
+ if (ul_attr & PIO_IT_EDGE) {
+ /* Edge select */
+ p_pio->PIO_ESR = ul_mask;
+ } else {
+ /* Level select */
+ p_pio->PIO_LSR = ul_mask;
+ }
+ } else {
+ /* Disable additional interrupt mode. */
+ p_pio->PIO_AIMDR = ul_mask;
+ }
+}
+
+/**
+ * \brief Enable the given interrupt source.
+ * The PIO must be configured as an NVIC interrupt source as well.
+ * The status register of the corresponding PIO controller is cleared
+ * prior to enabling the interrupt.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Interrupt sources bit map.
+ */
+void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask)
+{
+ p_pio->PIO_ISR;
+ p_pio->PIO_IER = ul_mask;
+}
+
+/**
+ * \brief Disable a given interrupt source, with no added side effects.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Interrupt sources bit map.
+ */
+void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask)
+{
+ p_pio->PIO_IDR = ul_mask;
+}
+
+/**
+ * \brief Read PIO interrupt status.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return The interrupt status mask value.
+ */
+uint32_t pio_get_interrupt_status(const Pio *p_pio)
+{
+ return p_pio->PIO_ISR;
+}
+
+/**
+ * \brief Read PIO interrupt mask.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return The interrupt mask value.
+ */
+uint32_t pio_get_interrupt_mask(const Pio *p_pio)
+{
+ return p_pio->PIO_IMR;
+}
+
+/**
+ * \brief Set additional interrupt mode.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Interrupt sources bit map.
+ * \param ul_attribute Pin(s) attributes.
+ */
+void pio_set_additional_interrupt_mode(Pio *p_pio,
+ const uint32_t ul_mask, const uint32_t ul_attribute)
+{
+ /* Enables additional interrupt mode if needed */
+ if (ul_attribute & PIO_IT_AIME) {
+ /* Enables additional interrupt mode */
+ p_pio->PIO_AIMER = ul_mask;
+
+ /* Configures the Polarity of the event detection */
+ /* (Rising/Falling Edge or High/Low Level) */
+ if (ul_attribute & PIO_IT_RE_OR_HL) {
+ /* Rising Edge or High Level */
+ p_pio->PIO_REHLSR = ul_mask;
+ } else {
+ /* Falling Edge or Low Level */
+ p_pio->PIO_FELLSR = ul_mask;
+ }
+
+ /* Configures the type of event detection (Edge or Level) */
+ if (ul_attribute & PIO_IT_EDGE) {
+ /* Edge select */
+ p_pio->PIO_ESR = ul_mask;
+ } else {
+ /* Level select */
+ p_pio->PIO_LSR = ul_mask;
+ }
+ } else {
+ /* Disable additional interrupt mode */
+ p_pio->PIO_AIMDR = ul_mask;
+ }
+}
+
+#ifndef PIO_WPMR_WPKEY_PASSWD
+#define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494FU)
+#endif
+
+/**
+ * \brief Enable or disable write protect of PIO registers.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_enable 1 to enable, 0 to disable.
+ */
+void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable)
+{
+ p_pio->PIO_WPMR = PIO_WPMR_WPKEY_PASSWD | (ul_enable & PIO_WPMR_WPEN);
+}
+
+/**
+ * \brief Read write protect status.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return Return write protect status.
+ */
+uint32_t pio_get_writeprotect_status(const Pio *p_pio)
+{
+ return p_pio->PIO_WPSR;
+}
+
+/**
+ * \brief Return the value of a pin.
+ *
+ * \param ul_pin The pin number.
+ *
+ * \return The pin value.
+ *
+ * \note If pin is output: a pull-up or pull-down could hide the actual value.
+ * The function \ref pio_get can be called to get the actual pin output
+ * level.
+ * \note If pin is input: PIOx must be clocked to sample the signal.
+ * See PMC driver.
+ */
+uint32_t pio_get_pin_value(uint32_t ul_pin)
+{
+ Pio *p_pio = pio_get_pin_group(ul_pin);
+
+ return (p_pio->PIO_PDSR >> (ul_pin & 0x1F)) & 1;
+}
+
+/**
+ * \brief Drive a GPIO pin to 1.
+ *
+ * \param ul_pin The pin index.
+ *
+ * \note The function \ref pio_configure_pin must be called beforehand.
+ */
+void pio_set_pin_high(uint32_t ul_pin)
+{
+ Pio *p_pio = pio_get_pin_group(ul_pin);
+
+ /* Value to be driven on the I/O line: 1. */
+ p_pio->PIO_SODR = 1 << (ul_pin & 0x1F);
+}
+
+/**
+ * \brief Drive a GPIO pin to 0.
+ *
+ * \param ul_pin The pin index.
+ *
+ * \note The function \ref pio_configure_pin must be called before.
+ */
+void pio_set_pin_low(uint32_t ul_pin)
+{
+ Pio *p_pio = pio_get_pin_group(ul_pin);
+
+ /* Value to be driven on the I/O line: 0. */
+ p_pio->PIO_CODR = 1 << (ul_pin & 0x1F);
+}
+
+/**
+ * \brief Toggle a GPIO pin.
+ *
+ * \param ul_pin The pin index.
+ *
+ * \note The function \ref pio_configure_pin must be called before.
+ */
+void pio_toggle_pin(uint32_t ul_pin)
+{
+ Pio *p_pio = pio_get_pin_group(ul_pin);
+
+ if (p_pio->PIO_ODSR & (1 << (ul_pin & 0x1F))) {
+ /* Value to be driven on the I/O line: 0. */
+ p_pio->PIO_CODR = 1 << (ul_pin & 0x1F);
+ } else {
+ /* Value to be driven on the I/O line: 1. */
+ p_pio->PIO_SODR = 1 << (ul_pin & 0x1F);
+ }
+}
+
+/**
+ * \brief Perform complete pin(s) configuration; general attributes and PIO init
+ * if necessary.
+ *
+ * \param ul_pin Bitmask of one or more pin(s) to configure.
+ * \param ul_flags Pins attributes.
+ *
+ * \return Whether the pin(s) have been configured properly.
+ */
+uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags)
+{
+ Pio *p_pio = pio_get_pin_group(ul_pin);
+
+ /* Configure pins */
+ switch (ul_flags & PIO_TYPE_Msk) {
+ case PIO_TYPE_PIO_PERIPH_A:
+ pio_set_peripheral(p_pio, PIO_PERIPH_A, (1 << (ul_pin & 0x1F)));
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),
+ (ul_flags & PIO_PULLUP));
+ break;
+ case PIO_TYPE_PIO_PERIPH_B:
+ pio_set_peripheral(p_pio, PIO_PERIPH_B, (1 << (ul_pin & 0x1F)));
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),
+ (ul_flags & PIO_PULLUP));
+ break;
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ case PIO_TYPE_PIO_PERIPH_C:
+ pio_set_peripheral(p_pio, PIO_PERIPH_C, (1 << (ul_pin & 0x1F)));
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),
+ (ul_flags & PIO_PULLUP));
+ break;
+ case PIO_TYPE_PIO_PERIPH_D:
+ pio_set_peripheral(p_pio, PIO_PERIPH_D, (1 << (ul_pin & 0x1F)));
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),
+ (ul_flags & PIO_PULLUP));
+ break;
+#endif
+
+ case PIO_TYPE_PIO_INPUT:
+ pio_set_input(p_pio, (1 << (ul_pin & 0x1F)), ul_flags);
+ break;
+
+ case PIO_TYPE_PIO_OUTPUT_0:
+ case PIO_TYPE_PIO_OUTPUT_1:
+ pio_set_output(p_pio, (1 << (ul_pin & 0x1F)),
+ ((ul_flags & PIO_TYPE_PIO_OUTPUT_1)
+ == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0,
+ (ul_flags & PIO_OPENDRAIN) ? 1 : 0,
+ (ul_flags & PIO_PULLUP) ? 1 : 0);
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 1;
+}
+
+/**
+ * \brief Drive a GPIO port to 1.
+ *
+ * \param p_pio Base address of the PIO port.
+ * \param ul_mask Bitmask of one or more pin(s) to toggle.
+ */
+void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask)
+{
+ /* Value to be driven on the I/O line: 1. */
+ p_pio->PIO_SODR = ul_mask;
+}
+
+/**
+ * \brief Drive a GPIO port to 0.
+ *
+ * \param p_pio Base address of the PIO port.
+ * \param ul_mask Bitmask of one or more pin(s) to toggle.
+ */
+void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask)
+{
+ /* Value to be driven on the I/O line: 0. */
+ p_pio->PIO_CODR = ul_mask;
+}
+
+/**
+ * \brief Toggle a GPIO group.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Bitmask of one or more pin(s) to configure.
+ */
+void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask)
+{
+ if (p_pio->PIO_ODSR & ul_mask) {
+ /* Value to be driven on the I/O line: 0. */
+ p_pio->PIO_CODR = ul_mask;
+ } else {
+ /* Value to be driven on the I/O line: 1. */
+ p_pio->PIO_SODR = ul_mask;
+ }
+}
+
+/**
+ * \brief Perform complete pin(s) configuration; general attributes and PIO init
+ * if necessary.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Bitmask of one or more pin(s) to configure.
+ * \param ul_flags Pin(s) attributes.
+ *
+ * \return Whether the pin(s) have been configured properly.
+ */
+uint32_t pio_configure_pin_group(Pio *p_pio,
+ uint32_t ul_mask, const uint32_t ul_flags)
+{
+ /* Configure pins */
+ switch (ul_flags & PIO_TYPE_Msk) {
+ case PIO_TYPE_PIO_PERIPH_A:
+ pio_set_peripheral(p_pio, PIO_PERIPH_A, ul_mask);
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));
+ break;
+ case PIO_TYPE_PIO_PERIPH_B:
+ pio_set_peripheral(p_pio, PIO_PERIPH_B, ul_mask);
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));
+ break;
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ case PIO_TYPE_PIO_PERIPH_C:
+ pio_set_peripheral(p_pio, PIO_PERIPH_C, ul_mask);
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));
+ break;
+ case PIO_TYPE_PIO_PERIPH_D:
+ pio_set_peripheral(p_pio, PIO_PERIPH_D, ul_mask);
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));
+ break;
+#endif
+
+ case PIO_TYPE_PIO_INPUT:
+ pio_set_input(p_pio, ul_mask, ul_flags);
+ break;
+
+ case PIO_TYPE_PIO_OUTPUT_0:
+ case PIO_TYPE_PIO_OUTPUT_1:
+ pio_set_output(p_pio, ul_mask,
+ ((ul_flags & PIO_TYPE_PIO_OUTPUT_1)
+ == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0,
+ (ul_flags & PIO_OPENDRAIN) ? 1 : 0,
+ (ul_flags & PIO_PULLUP) ? 1 : 0);
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 1;
+}
+
+/**
+ * \brief Enable interrupt for a GPIO pin.
+ *
+ * \param ul_pin The pin index.
+ *
+ * \note The function \ref gpio_configure_pin must be called before.
+ */
+void pio_enable_pin_interrupt(uint32_t ul_pin)
+{
+ Pio *p_pio = pio_get_pin_group(ul_pin);
+
+ p_pio->PIO_IER = 1 << (ul_pin & 0x1F);
+}
+
+
+/**
+ * \brief Disable interrupt for a GPIO pin.
+ *
+ * \param ul_pin The pin index.
+ *
+ * \note The function \ref gpio_configure_pin must be called before.
+ */
+void pio_disable_pin_interrupt(uint32_t ul_pin)
+{
+ Pio *p_pio = pio_get_pin_group(ul_pin);
+
+ p_pio->PIO_IDR = 1 << (ul_pin & 0x1F);
+}
+
+
+/**
+ * \brief Return GPIO port for a GPIO pin.
+ *
+ * \param ul_pin The pin index.
+ *
+ * \return Pointer to \ref Pio struct for GPIO port.
+ */
+Pio *pio_get_pin_group(uint32_t ul_pin)
+{
+ Pio *p_pio;
+
+#if (SAM4C || SAM4CP)
+# ifdef ID_PIOD
+ if (ul_pin > PIO_PC9_IDX) {
+ p_pio = PIOD;
+ } else if (ul_pin > PIO_PB31_IDX) {
+# else
+ if (ul_pin > PIO_PB31_IDX) {
+# endif
+ p_pio = PIOC;
+ } else {
+ p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));
+ }
+#elif (SAM4CM)
+ if (ul_pin > PIO_PB21_IDX) {
+ p_pio = PIOC;
+ } else {
+ p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));
+ }
+#else
+ p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));
+#endif
+ return p_pio;
+}
+
+/**
+ * \brief Return GPIO port peripheral ID for a GPIO pin.
+ *
+ * \param ul_pin The pin index.
+ *
+ * \return GPIO port peripheral ID.
+ */
+uint32_t pio_get_pin_group_id(uint32_t ul_pin)
+{
+ uint32_t ul_id;
+
+#if (SAM4C || SAM4CP)
+# ifdef ID_PIOD
+ if (ul_pin > PIO_PC9_IDX) {
+ ul_id = ID_PIOD;
+ } else if (ul_pin > PIO_PB31_IDX) {
+# else
+ if (ul_pin > PIO_PB31_IDX) {
+# endif
+ ul_id = ID_PIOC;
+ } else {
+ ul_id = ID_PIOA + (ul_pin >> 5);
+ }
+#elif (SAM4CM)
+ if (ul_pin > PIO_PB21_IDX) {
+ ul_id = ID_PIOC;
+ } else {
+ ul_id = ID_PIOA + (ul_pin >> 5);
+ }
+#else
+ ul_id = ID_PIOA + (ul_pin >> 5);
+#endif
+ return ul_id;
+}
+
+
+/**
+ * \brief Return GPIO port pin mask for a GPIO pin.
+ *
+ * \param ul_pin The pin index.
+ *
+ * \return GPIO port pin mask.
+ */
+uint32_t pio_get_pin_group_mask(uint32_t ul_pin)
+{
+ uint32_t ul_mask = 1 << (ul_pin & 0x1F);
+ return ul_mask;
+}
+
+#if (SAM3S || SAM4S || SAM4E || SAMV71 || SAMV70 || SAME70 || SAMS70)
+/* Capture mode enable flag */
+uint32_t pio_capture_enable_flag;
+
+/**
+ * \brief Configure PIO capture mode.
+ * \note PIO capture mode will be disabled automatically.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mode Bitmask of one or more modes.
+ */
+void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode)
+{
+ ul_mode &= (~PIO_PCMR_PCEN); /* Disable PIO capture mode */
+ p_pio->PIO_PCMR = ul_mode;
+}
+
+/**
+ * \brief Enable PIO capture mode.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ */
+void pio_capture_enable(Pio *p_pio)
+{
+ p_pio->PIO_PCMR |= PIO_PCMR_PCEN;
+ pio_capture_enable_flag = true;
+}
+
+/**
+ * \brief Disable PIO capture mode.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ */
+void pio_capture_disable(Pio *p_pio)
+{
+ p_pio->PIO_PCMR &= (~PIO_PCMR_PCEN);
+ pio_capture_enable_flag = false;
+}
+
+/**
+ * \brief Read from Capture Reception Holding Register.
+ * \note Data presence should be tested before any read attempt.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param pul_data Pointer to store the data.
+ *
+ * \retval 0 Success.
+ * \retval 1 I/O Failure, Capture data is not ready.
+ */
+uint32_t pio_capture_read(const Pio *p_pio, uint32_t *pul_data)
+{
+ /* Check if the data is ready */
+ if ((p_pio->PIO_PCISR & PIO_PCISR_DRDY) == 0) {
+ return 1;
+ }
+
+ /* Read data */
+ *pul_data = p_pio->PIO_PCRHR;
+ return 0;
+}
+
+/**
+ * \brief Enable the given interrupt source of PIO capture. The status
+ * register of the corresponding PIO capture controller is cleared prior
+ * to enabling the interrupt.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Interrupt sources bit map.
+ */
+void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask)
+{
+ p_pio->PIO_PCISR;
+ p_pio->PIO_PCIER = ul_mask;
+}
+
+/**
+ * \brief Disable a given interrupt source of PIO capture.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Interrupt sources bit map.
+ */
+void pio_capture_disable_interrupt(Pio *p_pio, const uint32_t ul_mask)
+{
+ p_pio->PIO_PCIDR = ul_mask;
+}
+
+/**
+ * \brief Read PIO interrupt status of PIO capture.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return The interrupt status mask value.
+ */
+uint32_t pio_capture_get_interrupt_status(const Pio *p_pio)
+{
+ return p_pio->PIO_PCISR;
+}
+
+/**
+ * \brief Read PIO interrupt mask of PIO capture.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return The interrupt mask value.
+ */
+uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio)
+{
+ return p_pio->PIO_PCIMR;
+}
+#if !(SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Get PDC registers base address.
+ *
+ * \param p_pio Pointer to an PIO peripheral.
+ *
+ * \return PIOA PDC register base address.
+ */
+Pdc *pio_capture_get_pdc_base(const Pio *p_pio)
+{
+ UNUSED(p_pio); /* Stop warning */
+ return PDC_PIOA;
+}
+#endif
+#endif
+
+#if (SAM4C || SAM4CP || SAM4CM || SAMG55)
+/**
+ * \brief Set PIO IO drive.
+ *
+ * \param p_pio Pointer to an PIO peripheral.
+ * \param ul_line Line index (0..31).
+ * \param mode IO drive mode.
+ */
+void pio_set_io_drive(Pio *p_pio, uint32_t ul_line,
+ enum pio_io_drive_mode mode)
+{
+ p_pio->PIO_DRIVER &= ~(1 << ul_line);
+ p_pio->PIO_DRIVER |= mode << ul_line;
+}
+#endif
+
+#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Enable PIO keypad controller.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ */
+void pio_keypad_enable(Pio *p_pio)
+{
+ p_pio->PIO_KER |= PIO_KER_KCE;
+}
+
+/**
+ * \brief Disable PIO keypad controller.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ */
+void pio_keypad_disable(Pio *p_pio)
+{
+ p_pio->PIO_KER &= (~PIO_KER_KCE);
+}
+
+/**
+ * \brief Set PIO keypad controller row number.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param num Number of row of the keypad matrix.
+ */
+void pio_keypad_set_row_num(Pio *p_pio, uint8_t num)
+{
+ p_pio->PIO_KRCR &= (~PIO_KRCR_NBR_Msk);
+ p_pio->PIO_KRCR |= PIO_KRCR_NBR(num);
+}
+
+/**
+ * \brief Get PIO keypad controller row number.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return Number of row of the keypad matrix.
+ */
+uint8_t pio_keypad_get_row_num(const Pio *p_pio)
+{
+ return ((p_pio->PIO_KRCR & PIO_KRCR_NBR_Msk) >> PIO_KRCR_NBR_Pos);
+}
+
+/**
+ * \brief Set PIO keypad controller column number.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param num Number of column of the keypad matrix.
+ */
+void pio_keypad_set_column_num(Pio *p_pio, uint8_t num)
+{
+ p_pio->PIO_KRCR &= (~PIO_KRCR_NBC_Msk);
+ p_pio->PIO_KRCR |= PIO_KRCR_NBC(num);
+}
+
+/**
+ * \brief Get PIO keypad controller column number.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return Number of column of the keypad matrix.
+ */
+uint8_t pio_keypad_get_column_num(const Pio *p_pio)
+{
+ return ((p_pio->PIO_KRCR & PIO_KRCR_NBC_Msk) >> PIO_KRCR_NBC_Pos);
+}
+
+/**
+ * \brief Set PIO keypad matrix debouncing value.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param num Number of debouncing value.
+ */
+void pio_keypad_set_debouncing_value(Pio *p_pio, uint16_t value)
+{
+ p_pio->PIO_KDR = PIO_KDR_DBC(value);
+}
+
+/**
+ * \brief Get PIO keypad matrix debouncing value.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return The keypad debouncing value.
+ */
+uint16_t pio_keypad_get_debouncing_value(const Pio *p_pio)
+{
+ return ((p_pio->PIO_KDR & PIO_KDR_DBC_Msk) >> PIO_KDR_DBC_Pos);
+}
+
+/**
+ * \brief Enable the interrupt source of PIO keypad.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Interrupt sources bit map.
+ */
+void pio_keypad_enable_interrupt(Pio *p_pio, uint32_t ul_mask)
+{
+ p_pio->PIO_KIER = ul_mask;
+}
+
+/**
+ * \brief Disable the interrupt source of PIO keypad.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param ul_mask Interrupt sources bit map.
+ */
+void pio_keypad_disable_interrupt(Pio *p_pio, uint32_t ul_mask)
+{
+ p_pio->PIO_KIDR = ul_mask;
+}
+
+/**
+ * \brief Get interrupt mask of PIO keypad.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return The interrupt mask value.
+ */
+uint32_t pio_keypad_get_interrupt_mask(const Pio *p_pio)
+{
+ return p_pio->PIO_KIMR;
+}
+
+/**
+ * \brief Get key press status of PIO keypad.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return The status of key press.
+ * 0: No key press has been detected.
+ * 1: At least one key press has been detected.
+ */
+uint32_t pio_keypad_get_press_status(const Pio *p_pio)
+{
+ if (p_pio->PIO_KSR & PIO_KSR_KPR) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Get key release status of PIO keypad.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return The status of key release.
+ * 0 No key release has been detected.
+ * 1 At least one key release has been detected.
+ */
+uint32_t pio_keypad_get_release_status(const Pio *p_pio)
+{
+ if (p_pio->PIO_KSR & PIO_KSR_KRL) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Get simultaneous key press number of PIO keypad.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return The number of simultaneous key press.
+ */
+uint8_t pio_keypad_get_simult_press_num(const Pio *p_pio)
+{
+ return ((p_pio->PIO_KSR & PIO_KSR_NBKPR_Msk) >> PIO_KSR_NBKPR_Pos);
+}
+
+/**
+ * \brief Get simultaneous key release number of PIO keypad.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ *
+ * \return The number of simultaneous key release.
+ */
+uint8_t pio_keypad_get_simult_release_num(const Pio *p_pio)
+{
+ return ((p_pio->PIO_KSR & PIO_KSR_NBKRL_Msk) >> PIO_KSR_NBKRL_Pos);
+}
+
+/**
+ * \brief Get detected key press row index of PIO keypad.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param queue The queue of key press row
+ *
+ * \return The index of detected key press row.
+ */
+uint8_t pio_keypad_get_press_row_index(const Pio *p_pio, uint8_t queue)
+{
+ switch (queue) {
+ case 0:
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY0ROW_Msk) >> PIO_KKPR_KEY0ROW_Pos);
+ case 1:
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY1ROW_Msk) >> PIO_KKPR_KEY1ROW_Pos);
+ case 2:
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY2ROW_Msk) >> PIO_KKPR_KEY2ROW_Pos);
+ case 3:
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY3ROW_Msk) >> PIO_KKPR_KEY3ROW_Pos);
+ default:
+ return 0;
+ }
+}
+
+/**
+ * \brief Get detected key press column index of PIO keypad.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param queue The queue of key press column
+ *
+ * \return The index of detected key press column.
+ */
+uint8_t pio_keypad_get_press_column_index(const Pio *p_pio, uint8_t queue)
+{
+ switch (queue) {
+ case 0:
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY0COL_Msk) >> PIO_KKPR_KEY0COL_Pos);
+ case 1:
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY1COL_Msk) >> PIO_KKPR_KEY1COL_Pos);
+ case 2:
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY2COL_Msk) >> PIO_KKPR_KEY2COL_Pos);
+ case 3:
+ return ((p_pio->PIO_KKPR & PIO_KKPR_KEY3COL_Msk) >> PIO_KKPR_KEY3COL_Pos);
+ default:
+ return 0;
+ }
+}
+
+/**
+ * \brief Get detected key release row index of PIO keypad.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param queue The queue of key release row
+ *
+ * \return The index of detected key release row.
+ */
+uint8_t pio_keypad_get_release_row_index(const Pio *p_pio, uint8_t queue)
+{
+ switch (queue) {
+ case 0:
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY0ROW_Msk) >> PIO_KKRR_KEY0ROW_Pos);
+ case 1:
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY1ROW_Msk) >> PIO_KKRR_KEY1ROW_Pos);
+ case 2:
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY2ROW_Msk) >> PIO_KKRR_KEY2ROW_Pos);
+ case 3:
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY3ROW_Msk) >> PIO_KKRR_KEY3ROW_Pos);
+ default:
+ return 0;
+ }
+}
+
+/**
+ * \brief Get detected key release column index of PIO keypad.
+ *
+ * \param p_pio Pointer to a PIO instance.
+ * \param queue The queue of key release column
+ *
+ * \return The index of detected key release column.
+ */
+uint8_t pio_keypad_get_release_column_index(const Pio *p_pio, uint8_t queue)
+{
+ switch (queue) {
+ case 0:
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY0COL_Msk) >> PIO_KKRR_KEY0COL_Pos);
+ case 1:
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY1COL_Msk) >> PIO_KKRR_KEY1COL_Pos);
+ case 2:
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY2COL_Msk) >> PIO_KKRR_KEY2COL_Pos);
+ case 3:
+ return ((p_pio->PIO_KKRR & PIO_KKRR_KEY3COL_Msk) >> PIO_KKRR_KEY3COL_Pos);
+ default:
+ return 0;
+ }
+}
+
+#endif
+
+//@}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,377 @@
+/**
+ * \file
+ *
+ * \brief Parallel Input/Output (PIO) Controller driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef PIO_H_INCLUDED
+#define PIO_H_INCLUDED
+
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Compute PIO register length */
+#define PIO_DELTA ((uint32_t) PIOB - (uint32_t) PIOA)
+
+/* GPIO Support */
+#define PIO_TYPE_Pos 27
+/* PIO Type Mask */
+#define PIO_TYPE_Msk (0xFu << PIO_TYPE_Pos)
+/* The pin is not a function pin. */
+#define PIO_TYPE_NOT_A_PIN (0x0u << PIO_TYPE_Pos)
+/* The pin is controlled by the peripheral A. */
+#define PIO_TYPE_PIO_PERIPH_A (0x1u << PIO_TYPE_Pos)
+/* The pin is controlled by the peripheral B. */
+#define PIO_TYPE_PIO_PERIPH_B (0x2u << PIO_TYPE_Pos)
+/* The pin is controlled by the peripheral C. */
+#define PIO_TYPE_PIO_PERIPH_C (0x3u << PIO_TYPE_Pos)
+/* The pin is controlled by the peripheral D. */
+#define PIO_TYPE_PIO_PERIPH_D (0x4u << PIO_TYPE_Pos)
+/* The pin is an input. */
+#define PIO_TYPE_PIO_INPUT (0x5u << PIO_TYPE_Pos)
+/* The pin is an output and has a default level of 0. */
+#define PIO_TYPE_PIO_OUTPUT_0 (0x6u << PIO_TYPE_Pos)
+/* The pin is an output and has a default level of 1. */
+#define PIO_TYPE_PIO_OUTPUT_1 (0x7u << PIO_TYPE_Pos)
+
+typedef enum _pio_type {
+ PIO_NOT_A_PIN = PIO_TYPE_NOT_A_PIN,
+ PIO_PERIPH_A = PIO_TYPE_PIO_PERIPH_A,
+ PIO_PERIPH_B = PIO_TYPE_PIO_PERIPH_B,
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ PIO_PERIPH_C = PIO_TYPE_PIO_PERIPH_C,
+ PIO_PERIPH_D = PIO_TYPE_PIO_PERIPH_D,
+#endif
+ PIO_INPUT = PIO_TYPE_PIO_INPUT,
+ PIO_OUTPUT_0 = PIO_TYPE_PIO_OUTPUT_0,
+ PIO_OUTPUT_1 = PIO_TYPE_PIO_OUTPUT_1
+} pio_type_t;
+
+/* Default pin configuration (no attribute). */
+#define PIO_DEFAULT (0u << 0)
+/* The internal pin pull-up is active. */
+#define PIO_PULLUP (1u << 0)
+/* The internal glitch filter is active. */
+#define PIO_DEGLITCH (1u << 1)
+/* The pin is open-drain. */
+#define PIO_OPENDRAIN (1u << 2)
+
+/* The internal debouncing filter is active. */
+#define PIO_DEBOUNCE (1u << 3)
+
+/* Enable additional interrupt modes. */
+#define PIO_IT_AIME (1u << 4)
+
+/* Interrupt High Level/Rising Edge detection is active. */
+#define PIO_IT_RE_OR_HL (1u << 5)
+/* Interrupt Edge detection is active. */
+#define PIO_IT_EDGE (1u << 6)
+
+/* Low level interrupt is active */
+#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME)
+/* High level interrupt is active */
+#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME)
+/* Falling edge interrupt is active */
+#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME)
+/* Rising edge interrupt is active */
+#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME)
+
+/*
+ * The #attribute# field is a bitmask that can either be set to PIO_DEFAULT,
+ * or combine (using bitwise OR '|') any number of the following constants:
+ * - PIO_PULLUP
+ * - PIO_DEGLITCH
+ * - PIO_DEBOUNCE
+ * - PIO_OPENDRAIN
+ * - PIO_IT_LOW_LEVEL
+ * - PIO_IT_HIGH_LEVEL
+ * - PIO_IT_FALL_EDGE
+ * - PIO_IT_RISE_EDGE
+ */
+void pio_pull_up(Pio *p_pio, const uint32_t ul_mask,
+ const uint32_t ul_pull_up_enable);
+void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask,
+ const uint32_t ul_cut_off);
+void pio_set(Pio *p_pio, const uint32_t ul_mask);
+void pio_clear(Pio *p_pio, const uint32_t ul_mask);
+uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type,
+ const uint32_t ul_mask);
+void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type,
+ const uint32_t ul_mask);
+void pio_set_input(Pio *p_pio, const uint32_t ul_mask,
+ const uint32_t ul_attribute);
+void pio_set_output(Pio *p_pio, const uint32_t ul_mask,
+ const uint32_t ul_default_level,
+ const uint32_t ul_multidrive_enable,
+ const uint32_t ul_pull_up_enable);
+uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type,
+ const uint32_t ul_mask, const uint32_t ul_attribute);
+uint32_t pio_get_output_data_status(const Pio *p_pio,
+ const uint32_t ul_mask);
+void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask,
+ const uint32_t ul_multi_driver_enable);
+uint32_t pio_get_multi_driver_status(const Pio *p_pio);
+
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+void pio_pull_down(Pio *p_pio, const uint32_t ul_mask,
+ const uint32_t ul_pull_down_enable);
+#endif
+
+void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask);
+void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask);
+uint32_t pio_get_output_write_status(const Pio *p_pio);
+void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask);
+
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask);
+uint32_t pio_get_schmitt_trigger(const Pio *p_pio);
+#endif
+
+void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask,
+ const uint32_t ul_attr);
+void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask);
+void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask);
+uint32_t pio_get_interrupt_status(const Pio *p_pio);
+uint32_t pio_get_interrupt_mask(const Pio *p_pio);
+void pio_set_additional_interrupt_mode(Pio *p_pio,
+ const uint32_t ul_mask, const uint32_t ul_attribute);
+void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable);
+uint32_t pio_get_writeprotect_status(const Pio *p_pio);
+
+#if (SAM3S || SAM4S || SAM4E || SAMV71 || SAMV70 || SAME70 || SAMS70)
+void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode);
+void pio_capture_enable(Pio *p_pio);
+void pio_capture_disable(Pio *p_pio);
+uint32_t pio_capture_read(const Pio *p_pio, uint32_t * pul_data);
+void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask);
+void pio_capture_disable_interrupt(Pio * p_pio, const uint32_t ul_mask);
+uint32_t pio_capture_get_interrupt_status(const Pio *p_pio);
+uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio);
+#if !(SAMV71 || SAMV70 || SAME70 || SAMS70)
+Pdc *pio_capture_get_pdc_base(const Pio *p_pio);
+#endif
+#endif
+
+/* GPIO Support */
+uint32_t pio_get_pin_value(uint32_t pin);
+void pio_set_pin_high(uint32_t pin);
+void pio_set_pin_low(uint32_t pin);
+void pio_toggle_pin(uint32_t pin);
+void pio_enable_pin_interrupt(uint32_t pin);
+void pio_disable_pin_interrupt(uint32_t pin);
+Pio *pio_get_pin_group(uint32_t pin);
+uint32_t pio_get_pin_group_id(uint32_t pin);
+uint32_t pio_get_pin_group_mask(uint32_t pin);
+uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags);
+void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask);
+void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask);
+void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask);
+uint32_t pio_configure_pin_group(Pio *p_pio, uint32_t ul_mask,
+ const uint32_t ul_flags);
+
+#if (SAM4C || SAM4CP || SAM4CM || SAMG55)
+enum pio_io_drive_mode {
+ PIO_IO_DRIVE_LOW = 0,
+ PIO_IO_DRIVE_HIGH,
+};
+void pio_set_io_drive(Pio *p_pio, uint32_t ul_line,
+ enum pio_io_drive_mode mode);
+#endif
+
+#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
+void pio_keypad_enable(Pio *p_pio);
+void pio_keypad_disable(Pio *p_pio);
+void pio_keypad_set_row_num(Pio *p_pio, uint8_t num);
+uint8_t pio_keypad_get_row_num(const Pio *p_pio);
+void pio_keypad_set_column_num(Pio *p_pio, uint8_t num);
+uint8_t pio_keypad_get_column_num(const Pio *p_pio);
+void pio_keypad_set_debouncing_value(Pio *p_pio, uint16_t value);
+uint16_t pio_keypad_get_debouncing_value(const Pio *p_pio);
+void pio_keypad_enable_interrupt(Pio *p_pio, uint32_t ul_mask);
+void pio_keypad_disable_interrupt(Pio *p_pio, uint32_t ul_mask);
+uint32_t pio_keypad_get_interrupt_mask(const Pio *p_pio);
+uint32_t pio_keypad_get_press_status(const Pio *p_pio);
+uint32_t pio_keypad_get_release_status(const Pio *p_pio);
+uint8_t pio_keypad_get_simult_press_num(const Pio *p_pio);
+uint8_t pio_keypad_get_simult_release_num(const Pio *p_pio);
+uint8_t pio_keypad_get_press_row_index(const Pio *p_pio, uint8_t queue);
+uint8_t pio_keypad_get_press_column_index(const Pio *p_pio, uint8_t queue);
+uint8_t pio_keypad_get_release_row_index(const Pio *p_pio, uint8_t queue);
+uint8_t pio_keypad_get_release_column_index(const Pio *p_pio, uint8_t queue);
+#endif
+/**
+ * \page sam_pio_quickstart Quick Start Guide for the SAM PIO driver
+ *
+ * This is the quick start guide for the \ref sam_drivers_pio_group "PIO Driver",
+ * with step-by-step instructions on how to configure and use the driver for
+ * specific use cases.
+ *
+ * The section described below can be compiled into e.g. the main application
+ * loop or any other function that will need to interface with the IO port.
+ *
+ * \section sam_pio_usecases PIO use cases
+ * - \ref sam_pio_quickstart_basic
+ * - \ref sam_pio_quickstart_use_case_2
+ *
+ * \section sam_pio_quickstart_basic Basic usage of the PIO driver
+ * This section will present a basic use case for the PIO driver. This use case
+ * will configure pin 23 on port A as output and pin 16 as an input with pullup,
+ * and then toggle the output pin's value to match that of the input pin.
+ *
+ * \subsection sam_pio_quickstart_use_case_1_prereq Prerequisites
+ * - \ref group_pmc "Power Management Controller driver"
+ *
+ * \subsection sam_pio_quickstart_use_case_1_setup_steps Initialization code
+ * Add to the application initialization code:
+ * \code
+ pmc_enable_periph_clk(ID_PIOA);
+
+ pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE);
+ pio_set_input(PIOA, PIO_PA16, PIO_PULLUP);
+\endcode
+ *
+ * \subsection sam_pio_quickstart_use_case_1_setup_steps_workflow Workflow
+ * -# Enable the module clock to the PIOA peripheral:
+ * \code pmc_enable_periph_clk(ID_PIOA); \endcode
+ * -# Set pin 23 direction on PIOA as output, default low level:
+ * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode
+ * -# Set pin 16 direction on PIOA as input, with pullup:
+ * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode
+ *
+ * \subsection sam_pio_quickstart_use_case_1_example_code Example code
+ * Set the state of output pin 23 to match input pin 16:
+ * \code
+ if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))
+ pio_clear(PIOA, PIO_PA23);
+ else
+ pio_set(PIOA, PIO_PA23);
+\endcode
+ *
+ * \subsection sam_pio_quickstart_use_case_1_example_workflow Workflow
+ * -# We check the value of the pin:
+ * \code
+ if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))
+\endcode
+ * -# Then we set the new output value based on the read pin value:
+ * \code
+ pio_clear(PIOA, PIO_PA23);
+ else
+ pio_set(PIOA, PIO_PA23);
+\endcode
+ */
+
+/**
+ * \page sam_pio_quickstart_use_case_2 Advanced use case - Interrupt driven edge detection
+ *
+ * \section sam_pio_quickstart_use_case_2 Advanced Use Case 1
+ * This section will present a more advanced use case for the PIO driver. This use case
+ * will configure pin 23 on port A as output and pin 16 as an input with pullup,
+ * and then toggle the output pin's value to match that of the input pin using the interrupt
+ * controller within the device.
+ *
+ * \subsection sam_pio_quickstart_use_case_2_prereq Prerequisites
+ * - \ref group_pmc "Power Management Controller driver"
+ *
+ * \subsection sam_pio_quickstart_use_case_2_setup_steps Initialization code
+ * Add to the application initialization code:
+ * \code
+ pmc_enable_periph_clk(ID_PIOA);
+
+ pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE);
+ pio_set_input(PIOA, PIO_PA16, PIO_PULLUP);
+
+ pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler);
+ pio_enable_interrupt(PIOA, PIO_PA16);
+
+ NVIC_EnableIRQ(PIOA_IRQn);
+\endcode
+ *
+ * \subsection sam_pio_quickstart_use_case_2_setup_steps_workflow Workflow
+ * -# Enable the module clock to the PIOA peripheral:
+ * \code pmc_enable_periph_clk(ID_PIOA); \endcode
+ * -# Set pin 23 direction on PIOA as output, default low level:
+ * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode
+ * -# Set pin 16 direction on PIOA as input, with pullup:
+ * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode
+ * -# Configure the input pin 16 interrupt mode and handler:
+ * \code pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler); \endcode
+ * -# Enable the interrupt for the configured input pin:
+ * \code pio_enable_interrupt(PIOA, PIO_PA16); \endcode
+ * -# Enable interrupt handling from the PIOA module:
+ * \code NVIC_EnableIRQ(PIOA_IRQn); \endcode
+ *
+ * \subsection sam_pio_quickstart_use_case_2_example_code Example code
+ * Add the following function to your application:
+ * \code
+ void pin_edge_handler(const uint32_t id, const uint32_t index)
+ {
+ if ((id == ID_PIOA) && (index == PIO_PA16)){
+ if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))
+ pio_clear(PIOA, PIO_PA23);
+ else
+ pio_set(PIOA, PIO_PA23);
+ }
+ }
+\endcode
+ *
+ * \subsection sam_pio_quickstart_use_case_2_example_workflow Workflow
+ * -# We check the value of the pin:
+ * \code
+ if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))
+\endcode
+ * -# Then we set the new output value based on the read pin value:
+ * \code
+ pio_clear(PIOA, PIO_PA23);
+ else
+ pio_set(PIOA, PIO_PA23);
+\endcode
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PIO_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio_handler.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,286 @@
+/**
+ * \file
+ *
+ * \brief Parallel Input/Output (PIO) interrupt handler for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "pio.h"
+#include "pio_handler.h"
+
+/**
+ * Maximum number of interrupt sources that can be defined. This
+ * constant can be increased, but the current value is the smallest possible one
+ * that will be compatible with all existing projects.
+ */
+#define MAX_INTERRUPT_SOURCES 7
+
+/**
+ * Describes a PIO interrupt source, including the PIO instance triggering the
+ * interrupt and the associated interrupt handler.
+ */
+struct s_interrupt_source {
+ uint32_t id;
+ uint32_t mask;
+ uint32_t attr;
+
+ /* Interrupt handler. */
+ void (*handler) (const uint32_t, const uint32_t);
+};
+
+
+/* List of interrupt sources. */
+static struct s_interrupt_source gs_interrupt_sources[MAX_INTERRUPT_SOURCES];
+
+/* Number of currently defined interrupt sources. */
+static uint32_t gs_ul_nb_sources = 0;
+
+#if (SAM3S || SAM4S || SAM4E)
+/* PIO Capture handler */
+static void (*pio_capture_handler)(Pio *) = NULL;
+extern uint32_t pio_capture_enable_flag;
+#endif
+
+/**
+ * \brief Process an interrupt request on the given PIO controller.
+ *
+ * \param p_pio PIO controller base address.
+ * \param ul_id PIO controller ID.
+ */
+void pio_handler_process(Pio *p_pio, uint32_t ul_id)
+{
+ uint32_t status;
+ uint32_t i;
+
+ /* Read PIO controller status */
+ status = pio_get_interrupt_status(p_pio);
+ status &= pio_get_interrupt_mask(p_pio);
+
+ /* Check pending events */
+ if (status != 0) {
+ /* Find triggering source */
+ i = 0;
+ while (status != 0) {
+ /* Source is configured on the same controller */
+ if (gs_interrupt_sources[i].id == ul_id) {
+ /* Source has PIOs whose statuses have changed */
+ if ((status & gs_interrupt_sources[i].mask) != 0) {
+ gs_interrupt_sources[i].handler(gs_interrupt_sources[i].id,
+ gs_interrupt_sources[i].mask);
+ status &= ~(gs_interrupt_sources[i].mask);
+ }
+ }
+ i++;
+ if (i >= MAX_INTERRUPT_SOURCES) {
+ break;
+ }
+ }
+ }
+
+ /* Check capture events */
+#if (SAM3S || SAM4S || SAM4E)
+ if (pio_capture_enable_flag) {
+ if (pio_capture_handler) {
+ pio_capture_handler(p_pio);
+ }
+ }
+#endif
+}
+
+/**
+ * \brief Set an interrupt handler for the provided pins.
+ * The provided handler will be called with the triggering pin as its parameter
+ * as soon as an interrupt is detected.
+ *
+ * \param p_pio PIO controller base address.
+ * \param ul_id PIO ID.
+ * \param ul_mask Pins (bit mask) to configure.
+ * \param ul_attr Pins attribute to configure.
+ * \param p_handler Interrupt handler function pointer.
+ *
+ * \return 0 if successful, 1 if the maximum number of sources has been defined.
+ */
+uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask,
+ uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t))
+{
+ struct s_interrupt_source *pSource;
+
+ if (gs_ul_nb_sources >= MAX_INTERRUPT_SOURCES)
+ return 1;
+
+ /* Define new source */
+ pSource = &(gs_interrupt_sources[gs_ul_nb_sources]);
+ pSource->id = ul_id;
+ pSource->mask = ul_mask;
+ pSource->attr = ul_attr;
+ pSource->handler = p_handler;
+ gs_ul_nb_sources++;
+
+ /* Configure interrupt mode */
+ pio_configure_interrupt(p_pio, ul_mask, ul_attr);
+
+ return 0;
+}
+
+#if (SAM3S || SAM4S || SAM4E)
+/**
+ * \brief Set a capture interrupt handler for all PIO.
+ *
+ * The handler will be called with the triggering PIO as its parameter
+ * as soon as an interrupt is detected.
+ *
+ * \param p_handler Interrupt handler function pointer.
+ *
+ */
+void pio_capture_handler_set(void (*p_handler)(Pio *))
+{
+ pio_capture_handler = p_handler;
+}
+#endif
+
+#ifdef ID_PIOA
+/**
+ * \brief Set an interrupt handler for the specified pin.
+ * The provided handler will be called with the triggering pin as its parameter
+ * as soon as an interrupt is detected.
+ *
+ * \param ul_pin Pin index to configure.
+ * \param ul_flag Pin flag.
+ * \param p_handler Interrupt handler function pointer.
+ *
+ * \return 0 if successful, 1 if the maximum number of sources has been defined.
+ */
+uint32_t pio_handler_set_pin(uint32_t ul_pin, uint32_t ul_flag,
+ void (*p_handler) (uint32_t, uint32_t))
+{
+ Pio *p_pio = pio_get_pin_group(ul_pin);
+ uint32_t group_id = pio_get_pin_group_id(ul_pin);
+ uint32_t group_mask = pio_get_pin_group_mask(ul_pin);
+
+ return pio_handler_set(p_pio, group_id, group_mask, ul_flag, p_handler);
+}
+
+/**
+ * \brief Parallel IO Controller A interrupt handler.
+ * Redefined PIOA interrupt handler for NVIC interrupt table.
+ */
+void PIOA_Handler(void)
+{
+ pio_handler_process(PIOA, ID_PIOA);
+}
+#endif
+
+#ifdef ID_PIOB
+/**
+ * \brief Parallel IO Controller B interrupt handler
+ * Redefined PIOB interrupt handler for NVIC interrupt table.
+ */
+void PIOB_Handler(void)
+{
+ pio_handler_process(PIOB, ID_PIOB);
+}
+#endif
+
+#ifdef ID_PIOC
+/**
+ * \brief Parallel IO Controller C interrupt handler.
+ * Redefined PIOC interrupt handler for NVIC interrupt table.
+ */
+void PIOC_Handler(void)
+{
+ pio_handler_process(PIOC, ID_PIOC);
+}
+#endif
+
+#ifdef ID_PIOD
+/**
+ * \brief Parallel IO Controller D interrupt handler.
+ * Redefined PIOD interrupt handler for NVIC interrupt table.
+ */
+void PIOD_Handler(void)
+{
+ pio_handler_process(PIOD, ID_PIOD);
+}
+#endif
+
+#ifdef ID_PIOE
+/**
+ * \brief Parallel IO Controller E interrupt handler.
+ * Redefined PIOE interrupt handler for NVIC interrupt table.
+ */
+void PIOE_Handler(void)
+{
+ pio_handler_process(PIOE, ID_PIOE);
+}
+#endif
+
+#ifdef ID_PIOF
+/**
+ * \brief Parallel IO Controller F interrupt handler.
+ * Redefined PIOF interrupt handler for NVIC interrupt table.
+ */
+void PIOF_Handler(void)
+{
+ pio_handler_process(PIOF, ID_PIOF);
+}
+#endif
+
+/**
+ * \brief Initialize PIO interrupt management logic.
+ *
+ * \param p_pio PIO controller base address.
+ * \param ul_irqn NVIC line number.
+ * \param ul_priority PIO controller interrupts priority.
+ */
+void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority)
+{
+ uint32_t bitmask = 0;
+
+ bitmask = pio_get_interrupt_mask(p_pio);
+ pio_disable_interrupt(p_pio, 0xFFFFFFFF);
+ pio_get_interrupt_status(p_pio);
+ NVIC_DisableIRQ(ul_irqn);
+ NVIC_ClearPendingIRQ(ul_irqn);
+ NVIC_SetPriority(ul_irqn, ul_priority);
+ NVIC_EnableIRQ(ul_irqn);
+ pio_enable_interrupt(p_pio, bitmask);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio_handler.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,69 @@
+/**
+ * \file
+ *
+ * \brief Parallel Input/Output (PIO) interrupt handler for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef PIO_HANDLER_H_INCLUDED
+#define PIO_HANDLER_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void pio_handler_process(Pio *p_pio, uint32_t ul_id);
+void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority);
+uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask,
+ uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t));
+uint32_t pio_handler_set_pin(uint32_t ul_pin, uint32_t ul_flag,
+ void (*p_handler) (uint32_t, uint32_t));
+
+#if (SAM3S || SAM4S || SAM4E)
+void pio_capture_handler_set(void (*p_handler)(Pio *));
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PIO_HANDLER_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/pmc.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,1647 @@
+/**
+ * \file
+ *
+ * \brief Power Management Controller (PMC) driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "pmc.h"
+
+#if (SAM3N)
+# define MAX_PERIPH_ID 31
+#elif (SAM3XA)
+# define MAX_PERIPH_ID 44
+#elif (SAM3U)
+# define MAX_PERIPH_ID 29
+#elif (SAM3S || SAM4S)
+# define MAX_PERIPH_ID 34
+#elif (SAM4E)
+# define MAX_PERIPH_ID 47
+#elif (SAMV71)
+# define MAX_PERIPH_ID 63
+#elif (SAMV70)
+# define MAX_PERIPH_ID 63
+#elif (SAME70)
+# define MAX_PERIPH_ID 63
+#elif (SAMS70)
+# define MAX_PERIPH_ID 63
+#elif (SAM4N)
+# define MAX_PERIPH_ID 31
+#elif (SAM4C || SAM4CM || SAM4CP)
+# define MAX_PERIPH_ID 43
+#elif (SAMG51)
+# define MAX_PERIPH_ID 47
+#elif (SAMG53)
+# define MAX_PERIPH_ID 47
+#elif (SAMG54)
+# define MAX_PERIPH_ID 47
+#elif (SAMG55)
+# define MAX_PERIPH_ID 50
+#endif
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /**
+ * \defgroup sam_drivers_pmc_group Power Management Controller (PMC)
+ *
+ * \par Purpose
+ *
+ * The Power Management Controller (PMC) optimizes power consumption by
+ * controlling all system and user peripheral clocks. The PMC enables/disables
+ * the clock inputs to many of the peripherals and the Cortex-M Processor.
+ *
+ * @{
+ */
+
+ /**
+ * \brief Set the prescaler of the MCK.
+ *
+ * \param ul_pres Prescaler value.
+ */
+ void pmc_mck_set_prescaler(uint32_t ul_pres)
+{
+ PMC->PMC_MCKR =
+ (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
+}
+
+#if SAMV71 || SAMV70 || SAME70 || SAMS70
+/**
+ * \brief Set the division of the MCK.
+ *
+ * \param ul_div Division value.
+ */
+void pmc_mck_set_division(uint32_t ul_div)
+{
+ switch (ul_div) {
+ case 1:
+ ul_div = PMC_MCKR_MDIV_EQ_PCK;
+ break;
+ case 2:
+ ul_div = PMC_MCKR_MDIV_PCK_DIV2;
+ break;
+ case 3:
+ ul_div = PMC_MCKR_MDIV_PCK_DIV3;
+ break;
+ case 4:
+ ul_div = PMC_MCKR_MDIV_PCK_DIV4;
+ break;
+ default:
+ ul_div = PMC_MCKR_MDIV_EQ_PCK;
+ break;
+ }
+ PMC->PMC_MCKR =
+ (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | ul_div;
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
+}
+#endif
+
+/**
+ * \brief Set the source of the MCK.
+ *
+ * \param ul_source Source selection value.
+ */
+void pmc_mck_set_source(uint32_t ul_source)
+{
+ PMC->PMC_MCKR =
+ (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source;
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
+}
+
+/**
+ * \brief Switch master clock source selection to slow clock.
+ *
+ * \param ul_pres Processor clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres)
+{
+ uint32_t ul_timeout;
+
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
+ PMC_MCKR_CSS_SLOW_CLK;
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+ --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+ --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * \brief Switch master clock source selection to main clock.
+ *
+ * \param ul_pres Processor clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres)
+{
+ uint32_t ul_timeout;
+
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
+ PMC_MCKR_CSS_MAIN_CLK;
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+ --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+ --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * \brief Switch master clock source selection to PLLA clock.
+ *
+ * \param ul_pres Processor clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres)
+{
+ uint32_t ul_timeout;
+
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+ --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
+ PMC_MCKR_CSS_PLLA_CLK;
+
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+ --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
+/**
+ * \brief Switch master clock source selection to PLLB clock.
+ *
+ * \param ul_pres Processor clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres)
+{
+ uint32_t ul_timeout;
+
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+ --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
+ PMC_MCKR_CSS_PLLB_CLK;
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+ --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+#endif
+
+#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Switch master clock source selection to UPLL clock.
+ *
+ * \param ul_pres Processor clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres)
+{
+ uint32_t ul_timeout;
+
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+ --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
+ PMC_MCKR_CSS_UPLL_CLK;
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+ --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+#endif
+
+/**
+ * \brief Switch slow clock source selection to external 32k (Xtal or Bypass).
+ *
+ * \note Switching SCLK back to 32krc is only possible by shutting down the
+ * VDDIO power supply.
+ *
+ * \param ul_bypass 0 for Xtal, 1 for bypass.
+ */
+void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass)
+{
+ /* Set Bypass mode if required */
+ if (ul_bypass == 1) {
+ SUPC->SUPC_MR |= SUPC_MR_KEY_PASSWD |
+ SUPC_MR_OSCBYPASS;
+ }
+
+ SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL;
+}
+
+/**
+ * \brief Check if the external 32k Xtal is ready.
+ *
+ * \retval 1 External 32k Xtal is ready.
+ * \retval 0 External 32k Xtal is not ready.
+ */
+uint32_t pmc_osc_is_ready_32kxtal(void)
+{
+ return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL)
+ && (PMC->PMC_SR & PMC_SR_OSCSELS));
+}
+
+/**
+ * \brief Switch main clock source selection to internal fast RC.
+ *
+ * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz).
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ * \retval 2 Invalid frequency.
+ */
+void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf)
+{
+ /* Enable Fast RC oscillator but DO NOT switch to RC now */
+ PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);
+
+ /* Wait the Fast RC to stabilize */
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
+
+ /* Change Fast RC oscillator frequency */
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
+ CKGR_MOR_KEY_PASSWD | ul_moscrcf;
+
+ /* Wait the Fast RC to stabilize */
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
+
+ /* Switch to Fast RC */
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) |
+ CKGR_MOR_KEY_PASSWD;
+}
+
+/**
+ * \brief Enable fast RC oscillator.
+ *
+ * \param ul_rc Fast RC oscillator(4/8/12Mhz).
+ */
+void pmc_osc_enable_fastrc(uint32_t ul_rc)
+{
+ /* Enable Fast RC oscillator but DO NOT switch to RC */
+ PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);
+ /* Wait the Fast RC to stabilize */
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
+
+ /* Change Fast RC oscillator frequency */
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
+ CKGR_MOR_KEY_PASSWD | ul_rc;
+ /* Wait the Fast RC to stabilize */
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
+}
+
+/**
+ * \brief Disable the internal fast RC.
+ */
+void pmc_osc_disable_fastrc(void)
+{
+ /* Disable Fast RC oscillator */
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN &
+ ~CKGR_MOR_MOSCRCF_Msk)
+ | CKGR_MOR_KEY_PASSWD;
+}
+
+/**
+ * \brief Check if the main fastrc is ready.
+ *
+ * \retval 0 Xtal is not ready, otherwise ready.
+ */
+uint32_t pmc_osc_is_ready_fastrc(void)
+{
+ return (PMC->PMC_SR & PMC_SR_MOSCRCS);
+}
+
+/**
+ * \brief Enable main XTAL oscillator.
+ *
+ * \param ul_xtal_startup_time Xtal start-up time, in number of slow clocks.
+ */
+void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time)
+{
+ uint32_t mor = PMC->CKGR_MOR;
+ mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
+ mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN |
+ CKGR_MOR_MOSCXTST(ul_xtal_startup_time);
+ PMC->CKGR_MOR = mor;
+ /* Wait the main Xtal to stabilize */
+ while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
+}
+
+/**
+ * \brief Bypass main XTAL.
+ */
+void pmc_osc_bypass_main_xtal(void)
+{
+ uint32_t mor = PMC->CKGR_MOR;
+ mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
+ mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY;
+ /* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */
+ PMC->CKGR_MOR = mor;
+ /* The MOSCXTS in PMC_SR is automatically set */
+}
+
+/**
+ * \brief Disable the main Xtal.
+ */
+void pmc_osc_disable_main_xtal(void)
+{
+ uint32_t mor = PMC->CKGR_MOR;
+ mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
+ PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
+}
+
+/**
+ * \brief Check if the main crystal is bypassed.
+ *
+ * \retval 0 Xtal is bypassed, otherwise not.
+ */
+uint32_t pmc_osc_is_bypassed_main_xtal(void)
+{
+ return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY);
+}
+
+/**
+ * \brief Check if the main crystal is ready.
+ *
+ * \note If main crystal is bypassed, it's always ready.
+ *
+ * \retval 0 main crystal is not ready, otherwise ready.
+ */
+uint32_t pmc_osc_is_ready_main_xtal(void)
+{
+ return (PMC->PMC_SR & PMC_SR_MOSCXTS);
+}
+
+/**
+ * \brief Switch main clock source selection to external Xtal/Bypass.
+ *
+ * \note The function may switch MCK to SCLK if MCK source is MAINCK to avoid
+ * any system crash.
+ *
+ * \note If used in Xtal mode, the Xtal is automatically enabled.
+ *
+ * \param ul_bypass 0 for Xtal, 1 for bypass.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+void pmc_switch_mainck_to_xtal(uint32_t ul_bypass,
+ uint32_t ul_xtal_startup_time)
+{
+ /* Enable Main Xtal oscillator */
+ if (ul_bypass) {
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
+ CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY |
+ CKGR_MOR_MOSCSEL;
+ } else {
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
+ CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN |
+ CKGR_MOR_MOSCXTST(ul_xtal_startup_time);
+ /* Wait the Xtal to stabilize */
+ while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
+
+ PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL;
+ }
+}
+
+/**
+ * \brief Disable the external Xtal.
+ *
+ * \param ul_bypass 0 for Xtal, 1 for bypass.
+ */
+void pmc_osc_disable_xtal(uint32_t ul_bypass)
+{
+ /* Disable xtal oscillator */
+ if (ul_bypass) {
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
+ CKGR_MOR_KEY_PASSWD;
+ } else {
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
+ CKGR_MOR_KEY_PASSWD;
+ }
+}
+
+/**
+ * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one
+ * of Xtal, bypass or internal RC.
+ *
+ * \retval 1 Xtal is ready.
+ * \retval 0 Xtal is not ready.
+ */
+uint32_t pmc_osc_is_ready_mainck(void)
+{
+ return PMC->PMC_SR & PMC_SR_MOSCSELS;
+}
+
+/**
+ * \brief Select Main Crystal or internal RC as main clock source.
+ *
+ * \note This function will not enable/disable RC or Main Crystal.
+ *
+ * \param ul_xtal_rc 0 internal RC is selected, otherwise Main Crystal.
+ */
+void pmc_mainck_osc_select(uint32_t ul_xtal_rc)
+{
+ uint32_t mor = PMC->CKGR_MOR;
+ if (ul_xtal_rc) {
+ mor |= CKGR_MOR_MOSCSEL;
+ } else {
+ mor &= ~CKGR_MOR_MOSCSEL;
+ }
+ PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
+}
+
+/**
+ * \brief Enable PLLA clock.
+ *
+ * \param mula PLLA multiplier.
+ * \param pllacount PLLA counter.
+ * \param diva Divider.
+ */
+void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva)
+{
+ /* first disable the PLL to unlock the lock */
+ pmc_disable_pllack();
+
+#if (SAM4C || SAM4CM || SAM4CP || SAMG)
+ PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(diva) |
+ CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);
+#else
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) |
+ CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);
+#endif
+ while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0);
+}
+
+/**
+ * \brief Disable PLLA clock.
+ */
+void pmc_disable_pllack(void)
+{
+#if (SAM4C || SAM4CM || SAM4CP || SAMG)
+ PMC->CKGR_PLLAR = CKGR_PLLAR_MULA(0);
+#else
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);
+#endif
+}
+
+/**
+ * \brief Is PLLA locked?
+ *
+ * \retval 0 Not locked.
+ * \retval 1 Locked.
+ */
+uint32_t pmc_is_locked_pllack(void)
+{
+ return (PMC->PMC_SR & PMC_SR_LOCKA);
+}
+
+#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
+/**
+ * \brief Enable PLLB clock.
+ *
+ * \param mulb PLLB multiplier.
+ * \param pllbcount PLLB counter.
+ * \param divb Divider.
+ */
+void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb)
+{
+ /* first disable the PLL to unlock the lock */
+ pmc_disable_pllbck();
+
+#if SAMG55
+ PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(divb) |
+ CKGR_PLLAR_PLLACOUNT(pllbcount) | CKGR_PLLAR_MULA(mulb);
+#else
+ PMC->CKGR_PLLBR =
+ CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount)
+ | CKGR_PLLBR_MULB(mulb);
+#endif
+ while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0);
+}
+
+/**
+ * \brief Disable PLLB clock.
+ */
+void pmc_disable_pllbck(void)
+{
+ PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0);
+}
+
+/**
+ * \brief Is PLLB locked?
+ *
+ * \retval 0 Not locked.
+ * \retval 1 Locked.
+ */
+uint32_t pmc_is_locked_pllbck(void)
+{
+ return (PMC->PMC_SR & PMC_SR_LOCKB);
+}
+#endif
+
+#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Enable UPLL clock.
+ */
+void pmc_enable_upll_clock(void)
+{
+ PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN;
+
+ /* Wait UTMI PLL Lock Status */
+ while (!(PMC->PMC_SR & PMC_SR_LOCKU));
+}
+
+/**
+ * \brief Disable UPLL clock.
+ */
+void pmc_disable_upll_clock(void)
+{
+ PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
+}
+
+/**
+ * \brief Is UPLL locked?
+ *
+ * \retval 0 Not locked.
+ * \retval 1 Locked.
+ */
+uint32_t pmc_is_locked_upll(void)
+{
+ return (PMC->PMC_SR & PMC_SR_LOCKU);
+}
+#endif
+
+/**
+ * \brief Enable the specified peripheral clock.
+ *
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
+ *
+ * \param ul_id Peripheral ID (ID_xxx).
+ *
+ * \retval 0 Success.
+ * \retval 1 Invalid parameter.
+ */
+uint32_t pmc_enable_periph_clk(uint32_t ul_id)
+{
+ if (ul_id > MAX_PERIPH_ID) {
+ return 1;
+ }
+
+ if (ul_id < 32) {
+ if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) {
+ PMC->PMC_PCER0 = 1 << ul_id;
+ }
+#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ } else {
+ ul_id -= 32;
+ if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) {
+ PMC->PMC_PCER1 = 1 << ul_id;
+ }
+#endif
+ }
+
+ return 0;
+}
+
+/**
+ * \brief Disable the specified peripheral clock.
+ *
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
+ *
+ * \param ul_id Peripheral ID (ID_xxx).
+ *
+ * \retval 0 Success.
+ * \retval 1 Invalid parameter.
+ */
+uint32_t pmc_disable_periph_clk(uint32_t ul_id)
+{
+ if (ul_id > MAX_PERIPH_ID) {
+ return 1;
+ }
+
+ if (ul_id < 32) {
+ if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) {
+ PMC->PMC_PCDR0 = 1 << ul_id;
+ }
+#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 \
+ || SAMV70 || SAME70 || SAMS70)
+ } else {
+ ul_id -= 32;
+ if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) {
+ PMC->PMC_PCDR1 = 1 << ul_id;
+ }
+#endif
+ }
+ return 0;
+}
+
+/**
+ * \brief Enable all peripheral clocks.
+ */
+void pmc_enable_all_periph_clk(void)
+{
+ PMC->PMC_PCER0 = PMC_MASK_STATUS0;
+ while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0);
+
+#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
+ || SAMV70 || SAME70 || SAMS70)
+ PMC->PMC_PCER1 = PMC_MASK_STATUS1;
+ while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1);
+#endif
+}
+
+/**
+ * \brief Disable all peripheral clocks.
+ */
+void pmc_disable_all_periph_clk(void)
+{
+ PMC->PMC_PCDR0 = PMC_MASK_STATUS0;
+ while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0);
+
+#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
+ || SAMV70 || SAME70 || SAMS70)
+ PMC->PMC_PCDR1 = PMC_MASK_STATUS1;
+ while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0);
+#endif
+}
+
+/**
+ * \brief Check if the specified peripheral clock is enabled.
+ *
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
+ *
+ * \param ul_id Peripheral ID (ID_xxx).
+ *
+ * \retval 0 Peripheral clock is disabled or unknown.
+ * \retval 1 Peripheral clock is enabled.
+ */
+uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id)
+{
+ if (ul_id > MAX_PERIPH_ID) {
+ return 0;
+ }
+
+#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
+ || SAMV70 || SAME70 || SAMS70)
+ if (ul_id < 32) {
+#endif
+ if ((PMC->PMC_PCSR0 & (1u << ul_id))) {
+ return 1;
+ } else {
+ return 0;
+ }
+#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
+ || SAMV70 || SAME70 || SAMS70)
+ } else {
+ ul_id -= 32;
+ if ((PMC->PMC_PCSR1 & (1u << ul_id))) {
+ return 1;
+ } else {
+ return 0;
+ }
+ }
+#endif
+}
+
+/**
+ * \brief Set the prescaler for the specified programmable clock.
+ *
+ * \param ul_id Peripheral ID.
+ * \param ul_pres Prescaler value.
+ */
+void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres)
+{
+ PMC->PMC_PCK[ul_id] =
+ (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres;
+ while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
+ && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
+}
+
+/**
+ * \brief Set the source oscillator for the specified programmable clock.
+ *
+ * \param ul_id Peripheral ID.
+ * \param ul_source Source selection value.
+ */
+void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source)
+{
+ PMC->PMC_PCK[ul_id] =
+ (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source;
+ while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
+ && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
+}
+
+/**
+ * \brief Switch programmable clock source selection to slow clock.
+ *
+ * \param ul_id Id of the programmable clock.
+ * \param ul_pres Programmable clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres)
+{
+ uint32_t ul_timeout;
+
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres;
+ for (ul_timeout = PMC_TIMEOUT;
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * \brief Switch programmable clock source selection to main clock.
+ *
+ * \param ul_id Id of the programmable clock.
+ * \param ul_pres Programmable clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres)
+{
+ uint32_t ul_timeout;
+
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres;
+ for (ul_timeout = PMC_TIMEOUT;
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * \brief Switch programmable clock source selection to PLLA clock.
+ *
+ * \param ul_id Id of the programmable clock.
+ * \param ul_pres Programmable clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres)
+{
+ uint32_t ul_timeout;
+
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres;
+ for (ul_timeout = PMC_TIMEOUT;
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
+/**
+ * \brief Switch programmable clock source selection to PLLB clock.
+ *
+ * \param ul_id Id of the programmable clock.
+ * \param ul_pres Programmable clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres)
+{
+ uint32_t ul_timeout;
+
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres;
+ for (ul_timeout = PMC_TIMEOUT;
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
+ --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+#endif
+
+#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Switch programmable clock source selection to UPLL clock.
+ *
+ * \param ul_id Id of the programmable clock.
+ * \param ul_pres Programmable clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres)
+{
+ uint32_t ul_timeout;
+
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres;
+ for (ul_timeout = PMC_TIMEOUT;
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
+ --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+#endif
+
+/**
+ * \brief Switch programmable clock source selection to mck.
+ *
+ * \param ul_id Id of the programmable clock.
+ * \param ul_pres Programmable clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres)
+{
+ uint32_t ul_timeout;
+
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MCK | ul_pres;
+ for (ul_timeout = PMC_TIMEOUT;
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
+ if (ul_timeout == 0) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * \brief Enable the specified programmable clock.
+ *
+ * \param ul_id Id of the programmable clock.
+ */
+void pmc_enable_pck(uint32_t ul_id)
+{
+ PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id;
+}
+
+/**
+ * \brief Disable the specified programmable clock.
+ *
+ * \param ul_id Id of the programmable clock.
+ */
+void pmc_disable_pck(uint32_t ul_id)
+{
+ PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id;
+}
+
+/**
+ * \brief Enable all programmable clocks.
+ */
+void pmc_enable_all_pck(void)
+{
+ PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2;
+}
+
+/**
+ * \brief Disable all programmable clocks.
+ */
+void pmc_disable_all_pck(void)
+{
+ PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2;
+}
+
+/**
+ * \brief Check if the specified programmable clock is enabled.
+ *
+ * \param ul_id Id of the programmable clock.
+ *
+ * \retval 0 Programmable clock is disabled or unknown.
+ * \retval 1 Programmable clock is enabled.
+ */
+uint32_t pmc_is_pck_enabled(uint32_t ul_id)
+{
+ if (ul_id > 2) {
+ return 0;
+ }
+
+ return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id));
+}
+
+#if (SAM4C || SAM4CM || SAM4CP)
+/**
+ * \brief Enable Coprocessor Clocks.
+ */
+void pmc_enable_cpck(void)
+{
+ PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD;
+}
+
+/**
+ * \brief Disable Coprocessor Clocks.
+ */
+void pmc_disable_cpck(void)
+{
+ PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD;
+}
+
+/**
+ * \brief Check if the Coprocessor Clocks is enabled.
+ *
+ * \retval 0 Coprocessor Clocks is disabled.
+ * \retval 1 Coprocessor Clocks is enabled.
+ */
+bool pmc_is_cpck_enabled(void)
+{
+ if(PMC->PMC_SCSR & PMC_SCSR_CPCK) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Enable Coprocessor Bus Master Clocks.
+ */
+void pmc_enable_cpbmck(void)
+{
+ PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD;
+}
+
+/**
+ * \brief Disable Coprocessor Bus Master Clocks.
+ */
+void pmc_disable_cpbmck(void)
+{
+ PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD;
+}
+
+/**
+ * \brief Check if the Coprocessor Bus Master Clocks is enabled.
+ *
+ * \retval 0 Coprocessor Bus Master Clocks is disabled.
+ * \retval 1 Coprocessor Bus Master Clocks is enabled.
+ */
+bool pmc_is_cpbmck_enabled(void)
+{
+ if(PMC->PMC_SCSR & PMC_SCSR_CPBMCK) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Set the prescaler for the Coprocessor Master Clock.
+ *
+ * \param ul_pres Prescaler value.
+ */
+void pmc_cpck_set_prescaler(uint32_t ul_pres)
+{
+ PMC->PMC_MCKR =
+ (PMC->PMC_MCKR & (~PMC_MCKR_CPPRES_Msk)) | PMC_MCKR_CPPRES(ul_pres);
+}
+
+/**
+ * \brief Set the source for the Coprocessor Master Clock.
+ *
+ * \param ul_source Source selection value.
+ */
+void pmc_cpck_set_source(uint32_t ul_source)
+{
+ PMC->PMC_MCKR =
+ (PMC->PMC_MCKR & (~PMC_MCKR_CPCSS_Msk)) | ul_source;
+}
+#endif
+
+#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Switch UDP (USB) clock source selection to PLLA clock.
+ *
+ * \param ul_usbdiv Clock divisor.
+ */
+void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv)
+{
+ PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);
+}
+#endif
+
+#if (SAM3S || SAM4S || SAMG55)
+/**
+ * \brief Switch UDP (USB) clock source selection to PLLB clock.
+ *
+ * \param ul_usbdiv Clock divisor.
+ */
+void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv)
+{
+ PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;
+}
+#endif
+
+#if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Switch UDP (USB) clock source selection to UPLL clock.
+ *
+ * \param ul_usbdiv Clock divisor.
+ */
+void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv)
+{
+ PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv);
+}
+#endif
+
+#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Enable UDP (USB) clock.
+ */
+void pmc_enable_udpck(void)
+{
+#if (SAM3S || SAM4S || SAM4E || SAMG55)
+ PMC->PMC_SCER = PMC_SCER_UDP;
+#elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
+ PMC->PMC_SCER = PMC_SCER_USBCLK;
+#else
+ PMC->PMC_SCER = PMC_SCER_UOTGCLK;
+# endif
+}
+
+/**
+ * \brief Disable UDP (USB) clock.
+ */
+void pmc_disable_udpck(void)
+{
+#if (SAM3S || SAM4S || SAM4E || SAMG55)
+ PMC->PMC_SCDR = PMC_SCDR_UDP;
+#elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
+ PMC->PMC_SCDR = PMC_SCDR_USBCLK;
+#else
+ PMC->PMC_SCDR = PMC_SCDR_UOTGCLK;
+# endif
+}
+#endif
+
+#if SAMG55
+/**
+ * \brief Switch UHP (USB) clock source selection to PLLA clock.
+ *
+ * \param ul_usbdiv Clock divisor.
+ */
+void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv)
+{
+ PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);
+}
+
+/**
+ * \brief Switch UHP (USB) clock source selection to PLLB clock.
+ *
+ * \param ul_usbdiv Clock divisor.
+ */
+void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv)
+{
+ PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;
+}
+
+/**
+ * \brief Enable UHP (USB) clock.
+ */
+void pmc_enable_uhpck(void)
+{
+ PMC->PMC_SCER = PMC_SCER_UHP;
+}
+#endif
+
+/**
+ * \brief Enable PMC interrupts.
+ *
+ * \param ul_sources Interrupt sources bit map.
+ */
+void pmc_enable_interrupt(uint32_t ul_sources)
+{
+ PMC->PMC_IER = ul_sources;
+}
+
+/**
+ * \brief Disable PMC interrupts.
+ *
+ * \param ul_sources Interrupt sources bit map.
+ */
+void pmc_disable_interrupt(uint32_t ul_sources)
+{
+ PMC->PMC_IDR = ul_sources;
+}
+
+/**
+ * \brief Get PMC interrupt mask.
+ *
+ * \return The interrupt mask value.
+ */
+uint32_t pmc_get_interrupt_mask(void)
+{
+ return PMC->PMC_IMR;
+}
+
+/**
+ * \brief Get current status.
+ *
+ * \return The current PMC status.
+ */
+uint32_t pmc_get_status(void)
+{
+ return PMC->PMC_SR;
+}
+
+/**
+ * \brief Set the wake-up inputs for fast startup mode registers
+ * (event generation).
+ *
+ * \param ul_inputs Wake up inputs to enable.
+ */
+void pmc_set_fast_startup_input(uint32_t ul_inputs)
+{
+ ul_inputs &= PMC_FAST_STARTUP_Msk;
+ PMC->PMC_FSMR |= ul_inputs;
+}
+
+/**
+ * \brief Clear the wake-up inputs for fast startup mode registers
+ * (remove event generation).
+ *
+ * \param ul_inputs Wake up inputs to disable.
+ */
+void pmc_clr_fast_startup_input(uint32_t ul_inputs)
+{
+ ul_inputs &= PMC_FAST_STARTUP_Msk;
+ PMC->PMC_FSMR &= ~ul_inputs;
+}
+
+#if (SAM4C || SAM4CM || SAM4CP)
+/**
+ * \brief Set the wake-up inputs of coprocessor for fast startup mode registers
+ * (event generation).
+ *
+ * \param ul_inputs Wake up inputs to enable.
+ */
+void pmc_cp_set_fast_startup_input(uint32_t ul_inputs)
+{
+ ul_inputs &= PMC_FAST_STARTUP_Msk;
+ PMC->PMC_CPFSMR |= ul_inputs;
+}
+
+/**
+ * \brief Clear the wake-up inputs of coprocessor for fast startup mode registers
+ * (remove event generation).
+ *
+ * \param ul_inputs Wake up inputs to disable.
+ */
+void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs)
+{
+ ul_inputs &= PMC_FAST_STARTUP_Msk;
+ PMC->PMC_CPFSMR &= ~ul_inputs;
+}
+#endif
+
+#if (!(SAMG51 || SAMG53 || SAMG54))
+/**
+ * \brief Enable Sleep Mode.
+ * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0)
+ *
+ * \param uc_type 0 for wait for interrupt, 1 for wait for event.
+ * \note For SAM4S, SAM4C, SAM4CM, SAM4CP, SAMV71 and SAM4E series,
+ * since only WFI is effective, uc_type = 1 will be treated as uc_type = 0.
+ */
+void pmc_enable_sleepmode(uint8_t uc_type)
+{
+#if !(SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode
+#endif
+ SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep
+
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ UNUSED(uc_type);
+ __WFI();
+#else
+ if (uc_type == 0) {
+ __WFI();
+ } else {
+ __WFE();
+ }
+#endif
+}
+#endif
+
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
+static uint32_t ul_flash_in_wait_mode = PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN;
+ /**
+ * \brief Set the embedded flash state in wait mode
+ *
+ * \param ul_flash_state PMC_WAIT_MODE_FLASH_STANDBY flash in standby mode,
+ * PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN flash in deep power down mode.
+ */
+ void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state)
+{
+ ul_flash_in_wait_mode = ul_flash_state;
+}
+
+/**
+ * \brief Enable Wait Mode. Enter condition: (WAITMODE bit = 1) + FLPM
+ *
+ * \note In this function, FLPM will retain, WAITMODE bit will be set,
+ * Generally, this function will be called by pmc_sleep() in order to
+ * complete all sequence entering wait mode.
+ * See \ref pmc_sleep() for entering different sleep modes.
+ */
+void pmc_enable_waitmode(void)
+{
+ uint32_t i;
+
+ /* Flash in wait mode */
+ i = PMC->PMC_FSMR;
+ i &= ~PMC_FSMR_FLPM_Msk;
+ i |= ul_flash_in_wait_mode;
+ PMC->PMC_FSMR = i;
+
+ /* Set the WAITMODE bit = 1 */
+ PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_WAITMODE;
+
+ /* Waiting for Master Clock Ready MCKRDY = 1 */
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
+
+ /* Waiting for MOSCRCEN bit cleared is strongly recommended
+ * to ensure that the core will not execute undesired instructions
+ */
+ for (i = 0; i < 500; i++) {
+ __NOP();
+ }
+ while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));
+
+#if (!SAMG)
+ /* Restore Flash in idle mode */
+ i = PMC->PMC_FSMR;
+ i &= ~PMC_FSMR_FLPM_Msk;
+ i |= PMC_WAIT_MODE_FLASH_IDLE;
+ PMC->PMC_FSMR = i;
+#endif
+}
+#else
+/**
+ * \brief Enable Wait Mode. Enter condition: WFE + (SLEEPDEEP bit = 0) +
+ * (LPM bit = 1)
+ */
+void pmc_enable_waitmode(void)
+{
+ uint32_t i;
+
+ PMC->PMC_FSMR |= PMC_FSMR_LPM; /* Enter Wait mode */
+ SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep */
+
+ __WFE();
+
+ /* Waiting for MOSCRCEN bit cleared is strongly recommended
+ * to ensure that the core will not execute undesired instructions
+ */
+ for (i = 0; i < 500; i++) {
+ __NOP();
+ }
+ while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));
+
+}
+#endif
+
+#if (!(SAMG51 || SAMG53 || SAMG54))
+/**
+ * \brief Enable Backup Mode. Enter condition: WFE/(VROFF bit = 1) +
+ * (SLEEPDEEP bit = 1)
+ */
+void pmc_enable_backupmode(void)
+{
+#if (SAM4C || SAM4CM || SAM4CP)
+ uint32_t tmp = SUPC->SUPC_MR & ~(SUPC_MR_BUPPOREN | SUPC_MR_KEY_Msk);
+ SUPC->SUPC_MR = tmp | SUPC_MR_KEY_PASSWD;
+ while (SUPC->SUPC_SR & SUPC_SR_BUPPORS);
+#endif
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG;
+ __WFE();
+ __WFI();
+#else
+ __WFE();
+#endif
+}
+#endif
+
+/**
+ * \brief Enable Clock Failure Detector.
+ */
+void pmc_enable_clock_failure_detector(void)
+{
+ uint32_t ul_reg = PMC->CKGR_MOR;
+
+ PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_CFDEN | ul_reg;
+}
+
+/**
+ * \brief Disable Clock Failure Detector.
+ */
+void pmc_disable_clock_failure_detector(void)
+{
+ uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN);
+
+ PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg;
+}
+
+#if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Enable Slow Crystal Oscillator Frequency Monitoring.
+ */
+void pmc_enable_sclk_osc_freq_monitor(void)
+{
+ uint32_t ul_reg = PMC->CKGR_MOR;
+
+ PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_XT32KFME | ul_reg;
+}
+
+/**
+ * \brief Disable Slow Crystal Oscillator Frequency Monitoring.
+ */
+void pmc_disable_sclk_osc_freq_monitor(void)
+{
+ uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_XT32KFME);
+
+ PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg;
+}
+#endif
+
+/**
+ * \brief Enable or disable write protect of PMC registers.
+ *
+ * \param ul_enable 1 to enable, 0 to disable.
+ */
+void pmc_set_writeprotect(uint32_t ul_enable)
+{
+ if (ul_enable) {
+ PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD | PMC_WPMR_WPEN;
+ } else {
+ PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD;
+ }
+}
+
+/**
+ * \brief Return write protect status.
+ *
+ * \return Return write protect status.
+ */
+uint32_t pmc_get_writeprotect_status(void)
+{
+ return PMC->PMC_WPSR;
+}
+
+#if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Enable the specified peripheral clock.
+ *
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
+ *
+ * \param ul_id Peripheral ID (ID_xxx).
+ *
+ * \retval 0 Success.
+ * \retval 1 Fail.
+ */
+uint32_t pmc_enable_sleepwalking(uint32_t ul_id)
+{
+ uint32_t temp;
+#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ if ((7 <= ul_id) && (ul_id<= 29)) {
+#else
+ if ((8 <= ul_id) && (ul_id<= 29)) {
+#endif
+ temp = pmc_get_active_status0();
+ if (temp & (1 << ul_id)) {
+ return 1;
+ }
+ PMC->PMC_SLPWK_ER0 = 1 << ul_id;
+ temp = pmc_get_active_status0();
+ if (temp & (1 << ul_id)) {
+ pmc_disable_sleepwalking(ul_id);
+ return 1;
+ }
+ return 0;
+ }
+#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
+ else if ((32 <= ul_id) && (ul_id<= 60)) {
+ ul_id -= 32;
+ temp = pmc_get_active_status1();
+ if (temp & (1 << ul_id)) {
+ return 1;
+ }
+ PMC->PMC_SLPWK_ER1 = 1 << ul_id;
+ temp = pmc_get_active_status1();
+ if (temp & (1 << ul_id)) {
+ pmc_disable_sleepwalking(ul_id);
+ return 1;
+ }
+ return 0;
+ }
+#endif
+ else {
+ return 1;
+ }
+}
+
+/**
+ * \brief Disable the sleepwalking of specified peripheral.
+ *
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
+ *
+ * \param ul_id Peripheral ID (ID_xxx).
+ *
+ * \retval 0 Success.
+ * \retval 1 Invalid parameter.
+ */
+uint32_t pmc_disable_sleepwalking(uint32_t ul_id)
+{
+#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ if ((7 <= ul_id) && (ul_id<= 29)) {
+#else
+ if ((8 <= ul_id) && (ul_id<= 29)) {
+#endif
+ PMC->PMC_SLPWK_DR0 = 1 << ul_id;
+ return 0;
+ }
+#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
+ else if ((32 <= ul_id) && (ul_id<= 60)) {
+ ul_id -= 32;
+ PMC->PMC_SLPWK_DR1 = 1 << ul_id;
+ return 0;
+ }
+#endif
+ else {
+ return 1;
+ }
+}
+
+/**
+ * \brief Return peripheral sleepwalking enable status.
+ *
+ * \return the status register value.
+ */
+uint32_t pmc_get_sleepwalking_status0(void)
+{
+ return PMC->PMC_SLPWK_SR0;
+}
+
+/**
+ * \brief Return peripheral active status.
+ *
+ * \return the status register value.
+ */
+uint32_t pmc_get_active_status0(void)
+{
+ return PMC->PMC_SLPWK_ASR0;
+}
+
+#endif
+
+#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Return peripheral sleepwalking enable status.
+ *
+ * \return the status register value.
+ */
+uint32_t pmc_get_sleepwalking_status1(void)
+{
+ return PMC->PMC_SLPWK_SR1;
+}
+
+/**
+ * \brief Return peripheral active status.
+ *
+ * \return the status register value.
+ */
+uint32_t pmc_get_active_status1(void)
+{
+ return PMC->PMC_SLPWK_ASR1;
+}
+#endif
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/pmc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,550 @@
+/**
+ * \file
+ *
+ * \brief Power Management Controller (PMC) driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef PMC_H_INCLUDED
+#define PMC_H_INCLUDED
+
+#include "compiler.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /** Bit mask for peripheral clocks (PCER0) */
+#define PMC_MASK_STATUS0 (0xFFFFFFFC)
+
+ /** Bit mask for peripheral clocks (PCER1) */
+#define PMC_MASK_STATUS1 (0xFFFFFFFF)
+
+ /** Loop counter timeout value */
+#if !(SAME70)
+#define PMC_TIMEOUT (2048)
+#else
+#define PMC_TIMEOUT (4096)
+#endif
+
+ /** Key to unlock CKGR_MOR register */
+#ifndef CKGR_MOR_KEY_PASSWD
+#define CKGR_MOR_KEY_PASSWD CKGR_MOR_KEY(0x37U)
+#endif
+
+ /** Key used to write SUPC registers */
+#ifndef SUPC_CR_KEY_PASSWD
+#define SUPC_CR_KEY_PASSWD SUPC_CR_KEY(0xA5U)
+#endif
+
+#ifndef SUPC_MR_KEY_PASSWD
+#define SUPC_MR_KEY_PASSWD SUPC_MR_KEY(0xA5U)
+#endif
+
+ /** Mask to access fast startup input */
+#define PMC_FAST_STARTUP_Msk (0x7FFFFu)
+
+ /** PMC_WPMR Write Protect KEY, unlock it */
+#ifndef PMC_WPMR_WPKEY_PASSWD
+#define PMC_WPMR_WPKEY_PASSWD PMC_WPMR_WPKEY((uint32_t) 0x504D43)
+#endif
+
+ /** Using external oscillator */
+#define PMC_OSC_XTAL 0
+
+ /** Oscillator in bypass mode */
+#define PMC_OSC_BYPASS 1
+
+#define PMC_PCK_0 0 /* PCK0 ID */
+#define PMC_PCK_1 1 /* PCK1 ID */
+#define PMC_PCK_2 2 /* PCK2 ID */
+#if SAMG55
+#define PMC_PCK_3 3 /* PCK3 ID */
+#define PMC_PCK_4 4 /* PCK4 ID */
+#define PMC_PCK_5 5 /* PCK5 ID */
+#define PMC_PCK_6 6 /* PCK6 ID */
+#define PMC_PCK_7 7 /* PCK7 ID */
+#endif
+
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ /** Flash state in Wait Mode */
+#define PMC_WAIT_MODE_FLASH_STANDBY PMC_FSMR_FLPM_FLASH_STANDBY
+#define PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN
+#define PMC_WAIT_MODE_FLASH_IDLE PMC_FSMR_FLPM_FLASH_IDLE
+#endif
+
+ /** Convert startup time from us to MOSCXTST */
+#define pmc_us_to_moscxtst(startup_us, slowck_freq) \
+ ((startup_us * slowck_freq / 8 / 1000000) < 0x100 ? \
+ (startup_us * slowck_freq / 8 / 1000000) : 0xFF)
+
+ /**
+ * \name Master clock (MCK) Source and Prescaler configuration
+ *
+ * \note The following functions may be used to select the clock source and
+ * prescaler for the master clock.
+ */
+//@{
+
+ void pmc_mck_set_prescaler(uint32_t ul_pres);
+#if SAMV71 || SAMV70 || SAME70 || SAMS70
+ void pmc_mck_set_division(uint32_t ul_div);
+#endif
+ void pmc_mck_set_source(uint32_t ul_source);
+ uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres);
+ uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres);
+ uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres);
+#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
+ uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres);
+#endif
+#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres);
+#endif
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state);
+#endif
+
+
+//@}
+
+ /**
+ * \name Slow clock (SLCK) oscillator and configuration
+ *
+ */
+//@{
+
+ void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass);
+ uint32_t pmc_osc_is_ready_32kxtal(void);
+
+//@}
+
+ /**
+ * \name Main Clock (MAINCK) oscillator and configuration
+ *
+ */
+//@{
+
+ void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf);
+ void pmc_osc_enable_fastrc(uint32_t ul_rc);
+ void pmc_osc_disable_fastrc(void);
+ uint32_t pmc_osc_is_ready_fastrc(void);
+ void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time);
+ void pmc_osc_bypass_main_xtal(void);
+ void pmc_osc_disable_main_xtal(void);
+ uint32_t pmc_osc_is_bypassed_main_xtal(void);
+ uint32_t pmc_osc_is_ready_main_xtal(void);
+ void pmc_switch_mainck_to_xtal(uint32_t ul_bypass,
+ uint32_t ul_xtal_startup_time);
+ void pmc_osc_disable_xtal(uint32_t ul_bypass);
+ uint32_t pmc_osc_is_ready_mainck(void);
+ void pmc_mainck_osc_select(uint32_t ul_xtal_rc);
+
+//@}
+
+ /**
+ * \name PLL oscillator and configuration
+ *
+ */
+//@{
+
+ void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva);
+ void pmc_disable_pllack(void);
+ uint32_t pmc_is_locked_pllack(void);
+
+#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
+ void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb);
+ void pmc_disable_pllbck(void);
+ uint32_t pmc_is_locked_pllbck(void);
+#endif
+
+#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ void pmc_enable_upll_clock(void);
+ void pmc_disable_upll_clock(void);
+ uint32_t pmc_is_locked_upll(void);
+#endif
+
+//@}
+
+ /**
+ * \name Peripherals clock configuration
+ *
+ */
+//@{
+
+ uint32_t pmc_enable_periph_clk(uint32_t ul_id);
+ uint32_t pmc_disable_periph_clk(uint32_t ul_id);
+ void pmc_enable_all_periph_clk(void);
+ void pmc_disable_all_periph_clk(void);
+ uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id);
+
+//@}
+
+ /**
+ * \name Programmable clock Source and Prescaler configuration
+ *
+ * The following functions may be used to select the clock source and
+ * prescaler for the specified programmable clock.
+ */
+//@{
+
+ void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres);
+ void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source);
+ uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres);
+ uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres);
+ uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres);
+#if (SAM4C || SAM4CM || SAM4CP)
+ void pmc_enable_cpck(void);
+ void pmc_disable_cpck(void);
+ bool pmc_is_cpck_enabled(void);
+ void pmc_enable_cpbmck(void);
+ void pmc_disable_cpbmck(void);
+ bool pmc_is_cpbmck_enabled(void);
+ void pmc_cpck_set_prescaler(uint32_t ul_pres);
+ void pmc_cpck_set_source(uint32_t ul_source);
+#endif
+#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
+ uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres);
+#endif
+#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres);
+#endif
+ uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres);
+ void pmc_enable_pck(uint32_t ul_id);
+ void pmc_disable_pck(uint32_t ul_id);
+ void pmc_enable_all_pck(void);
+ void pmc_disable_all_pck(void);
+ uint32_t pmc_is_pck_enabled(uint32_t ul_id);
+
+//@}
+
+ /**
+ * \name USB clock configuration
+ *
+ */
+//@{
+
+#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv);
+#endif
+#if (SAM3S || SAM4S || SAMG55)
+ void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv);
+#endif
+#if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv);
+#endif
+#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ void pmc_enable_udpck(void);
+ void pmc_disable_udpck(void);
+#endif
+#if SAMG55
+ void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv);
+ void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv);
+ void pmc_enable_uhpck(void);
+#endif
+
+//@}
+
+ /**
+ * \name Interrupt and status management
+ *
+ */
+//@{
+
+ void pmc_enable_interrupt(uint32_t ul_sources);
+ void pmc_disable_interrupt(uint32_t ul_sources);
+ uint32_t pmc_get_interrupt_mask(void);
+ uint32_t pmc_get_status(void);
+
+//@}
+
+ /**
+ * \name Power management
+ *
+ * The following functions are used to configure sleep mode and additional
+ * wake up inputs.
+ */
+//@{
+
+ void pmc_set_fast_startup_input(uint32_t ul_inputs);
+ void pmc_clr_fast_startup_input(uint32_t ul_inputs);
+#if (SAM4C || SAM4CM || SAM4CP)
+ void pmc_cp_set_fast_startup_input(uint32_t ul_inputs);
+ void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs);
+#endif
+#if (!(SAMG51 || SAMG53 || SAMG54))
+ void pmc_enable_sleepmode(uint8_t uc_type);
+#endif
+ void pmc_enable_waitmode(void);
+#if (!(SAMG51 || SAMG53 || SAMG54))
+ void pmc_enable_backupmode(void);
+#endif
+//@}
+
+ /**
+ * \name Failure detector
+ *
+ */
+//@{
+
+ void pmc_enable_clock_failure_detector(void);
+ void pmc_disable_clock_failure_detector(void);
+
+//@}
+
+#if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ /**
+ * \name Slow Crystal Oscillator Frequency Monitoring
+ *
+ */
+//@{
+
+ void pmc_enable_sclk_osc_freq_monitor(void);
+ void pmc_disable_sclk_osc_freq_monitor(void);
+
+//@}
+#endif
+
+ /**
+ * \name Write protection
+ *
+ */
+//@{
+
+ void pmc_set_writeprotect(uint32_t ul_enable);
+ uint32_t pmc_get_writeprotect_status(void);
+
+//@}
+
+#if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ /**
+ * \name Sleepwalking configuration
+ *
+ */
+//@{
+
+ uint32_t pmc_enable_sleepwalking(uint32_t ul_id);
+ uint32_t pmc_disable_sleepwalking(uint32_t ul_id);
+ uint32_t pmc_get_sleepwalking_status0(void);
+ uint32_t pmc_get_active_status0(void);
+#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
+ uint32_t pmc_get_sleepwalking_status1(void);
+ uint32_t pmc_get_active_status1(void);
+#endif
+//@}
+#endif
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+//! @}
+
+/**
+ * \page sam_pmc_quickstart Quick start guide for the SAM PMC module
+ *
+ * This is the quick start guide for the \ref sam_drivers_pmc_group "PMC module",
+ * with step-by-step instructions on how to configure and use the driver in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section pmc_use_cases PMC use cases
+ * - \ref pmc_basic_use_case Basic use case - Switch Main Clock sources
+ * - \ref pmc_use_case_2 Advanced use case - Configure Programmable Clocks
+ *
+ * \section pmc_basic_use_case Basic use case - Switch Main Clock sources
+ * In this use case, the PMC module is configured for a variety of system clock
+ * sources and speeds. A LED is used to visually indicate the current clock
+ * speed as the source is switched.
+ *
+ * \section pmc_basic_use_case_setup Setup
+ *
+ * \subsection pmc_basic_use_case_setup_prereq Prerequisites
+ * -# \ref gpio_group "General Purpose I/O Management (gpio)"
+ *
+ * \subsection pmc_basic_use_case_setup_code Code
+ * The following function needs to be added to the user application, to flash a
+ * board LED a variable number of times at a rate given in CPU ticks.
+ *
+ * \code
+ #define FLASH_TICK_COUNT 0x00012345
+
+ void flash_led(uint32_t tick_count, uint8_t flash_count)
+ {
+ SysTick->CTRL = SysTick_CTRL_ENABLE_Msk;
+ SysTick->LOAD = tick_count;
+
+ while (flash_count--)
+ {
+ gpio_toggle_pin(LED0_GPIO);
+ while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));
+ gpio_toggle_pin(LED0_GPIO);
+ while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));
+ }
+ }
+\endcode
+ *
+ * \section pmc_basic_use_case_usage Use case
+ *
+ * \subsection pmc_basic_use_case_usage_code Example code
+ * Add to application C-file:
+ * \code
+ for (;;)
+ {
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);
+ flash_led(FLASH_TICK_COUNT, 5);
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);
+ flash_led(FLASH_TICK_COUNT, 5);
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);
+ flash_led(FLASH_TICK_COUNT, 5);
+ pmc_switch_mainck_to_xtal(0);
+ flash_led(FLASH_TICK_COUNT, 5);
+ }
+\endcode
+ *
+ * \subsection pmc_basic_use_case_usage_flow Workflow
+ * -# Wrap the code in an infinite loop:
+ * \code
+ for (;;)
+\endcode
+ * -# Switch the Master CPU frequency to the internal 12MHz RC oscillator, flash
+ * a LED on the board several times:
+ * \code
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);
+ flash_led(FLASH_TICK_COUNT, 5);
+\endcode
+ * -# Switch the Master CPU frequency to the internal 8MHz RC oscillator, flash
+ * a LED on the board several times:
+ * \code
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);
+ flash_led(FLASH_TICK_COUNT, 5);
+\endcode
+ * -# Switch the Master CPU frequency to the internal 4MHz RC oscillator, flash
+ * a LED on the board several times:
+ * \code
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);
+ flash_led(FLASH_TICK_COUNT, 5);
+\endcode
+ * -# Switch the Master CPU frequency to the external crystal oscillator, flash
+ * a LED on the board several times:
+ * \code
+ pmc_switch_mainck_to_xtal(0, BOARD_OSC_STARTUP_US);
+ flash_led(FLASH_TICK_COUNT, 5);
+\endcode
+ *
+ * \section pmc_use_case_2 Use case #2 - Configure Programmable Clocks
+ * In this use case, the PMC module is configured to start the Slow Clock from
+ * an attached 32KHz crystal, and start one of the Programmable Clock modules
+ * sourced from the Slow Clock divided down with a prescale factor of 64.
+ *
+ * \section pmc_use_case_2_setup Setup
+ *
+ * \subsection pmc_use_case_2_setup_prereq Prerequisites
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"
+ *
+ * \subsection pmc_use_case_2_setup_code Code
+ * The following code must be added to the user application:
+ * \code
+ pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);
+\endcode
+ *
+ * \subsection pmc_use_case_2_setup_code_workflow Workflow
+ * -# Configure the PCK1 pin to output on a specific port pin (in this case,
+ * PIOA pin 17) of the microcontroller.
+ * \code
+ pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);
+\endcode
+ * \note The peripheral selection and pin will vary according to your selected
+ * SAM device model. Refer to the "Peripheral Signal Multiplexing on I/O
+ * Lines" of your device's datasheet.
+ *
+ * \section pmc_use_case_2_usage Use case
+ * The generated PCK1 clock output can be viewed on an oscilloscope attached to
+ * the correct pin of the microcontroller.
+ *
+ * \subsection pmc_use_case_2_usage_code Example code
+ * Add to application C-file:
+ * \code
+ pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);
+ pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);
+ pmc_enable_pck(PMC_PCK_1);
+
+ for (;;)
+ {
+ // Do Nothing
+ }
+\endcode
+ *
+ * \subsection pmc_use_case_2_usage_flow Workflow
+ * -# Switch the Slow Clock source input to an external 32KHz crystal:
+ * \code
+ pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);
+\endcode
+ * -# Switch the Programmable Clock module PCK1 source clock to the Slow Clock,
+ * with a prescaler of 64:
+ * \code
+ pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);
+\endcode
+ * -# Enable Programmable Clock module PCK1:
+ * \code
+ pmc_enable_pck(PMC_PCK_1);
+\endcode
+ * -# Enter an infinite loop:
+ * \code
+ for (;;)
+ {
+ // Do Nothing
+ }
+\endcode
+ */
+
+#endif /* PMC_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/sleep.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,389 @@
+/**
+ * \file
+ *
+ * \brief Sleep mode access
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <compiler.h>
+#include "sleep.h"
+
+/* SAM3 and SAM4 series */
+#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \
+ SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAMS70 || SAME70)
+# include "pmc.h"
+# include "board.h"
+
+/* Checking board configuration of main clock xtal statup time */
+#if !defined(BOARD_OSC_STARTUP_US)
+# warning The board main clock xtal statup time has not been defined. Using default settings.
+# define BOARD_OSC_STARTUP_US (15625UL)
+#endif
+
+#if !defined(EFC0)
+# define EFC0 EFC
+#endif
+
+/**
+ * Save clock settings and shutdown PLLs
+ */
+__always_inline static void pmc_save_clock_settings(
+ uint32_t *p_osc_setting,
+ uint32_t *p_pll0_setting,
+ uint32_t *p_pll1_setting,
+ uint32_t *p_mck_setting,
+ uint32_t *p_fmr_setting,
+#if defined(EFC1)
+ uint32_t *p_fmr_setting1,
+#endif
+ const bool disable_xtal)
+{
+ uint32_t mor = PMC->CKGR_MOR;
+ uint32_t mckr = PMC->PMC_MCKR;
+ uint32_t fmr = EFC0->EEFC_FMR;
+# if defined(EFC1)
+ uint32_t fmr1 = EFC1->EEFC_FMR;
+# endif
+
+ if (p_osc_setting) {
+ *p_osc_setting = mor;
+ }
+ if (p_pll0_setting) {
+ *p_pll0_setting = PMC->CKGR_PLLAR;
+ }
+ if (p_pll1_setting) {
+#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP)
+ *p_pll1_setting = PMC->CKGR_PLLBR;
+#elif (SAM3U || SAM3XA)
+ *p_pll1_setting = PMC->CKGR_UCKR;
+#else
+ *p_pll1_setting = 0;
+#endif
+ }
+ if (p_mck_setting) {
+ *p_mck_setting = mckr;
+ }
+ if (p_fmr_setting) {
+ *p_fmr_setting = fmr;
+ }
+#if defined(EFC1)
+ if (p_fmr_setting1) {
+ *p_fmr_setting1 = fmr1;
+ }
+#endif
+
+ /* Enable FAST RC */
+ PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor | CKGR_MOR_MOSCRCEN;
+ /* if MCK source is PLL, switch to mainck */
+ if ((mckr & PMC_MCKR_CSS_Msk) > PMC_MCKR_CSS_MAIN_CLK) {
+ /* MCK -> MAINCK */
+ mckr = (mckr & (~PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_MAIN_CLK;
+ PMC->PMC_MCKR = mckr;
+ while(!(PMC->PMC_SR & PMC_SR_MCKRDY));
+ }
+ /* MCK prescale -> 1 */
+ if (mckr & PMC_MCKR_PRES_Msk) {
+ mckr = (mckr & (~PMC_MCKR_PRES_Msk));
+ PMC->PMC_MCKR = mckr;
+ while(!(PMC->PMC_SR & PMC_SR_MCKRDY));
+ }
+ /* Disable PLLs */
+ pmc_disable_pllack();
+#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP)
+ pmc_disable_pllbck();
+#elif (SAM3U || SAM3XA)
+ pmc_disable_upll_clock();
+#endif
+
+ /* Prepare for entering WAIT mode */
+ /* Wait fast RC ready */
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
+
+ /* Switch mainck to FAST RC */
+#if SAMG
+ /**
+ * For the sleepwalking feature, we need an accurate RC clock. Only 24M and
+ * 16M are trimmed in production. Here we select the 24M.
+ * And so wait state need to be 1.
+ */
+ EFC0->EEFC_FMR = (fmr & (~EEFC_FMR_FWS_Msk)) | EEFC_FMR_FWS(1);
+
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | CKGR_MOR_MOSCRCF_24_MHz |
+ CKGR_MOR_KEY_PASSWD;
+#else
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) |
+ CKGR_MOR_KEY_PASSWD;
+#endif
+ while (!(PMC->PMC_SR & PMC_SR_MOSCSELS));
+
+#if (!SAMG)
+ /* FWS update */
+ EFC0->EEFC_FMR = fmr & (~EEFC_FMR_FWS_Msk);
+#if defined(EFC1)
+ EFC1->EEFC_FMR = fmr1 & (~EEFC_FMR_FWS_Msk);
+#endif
+#endif
+
+ /* Disable XTALs */
+ if (disable_xtal) {
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
+ CKGR_MOR_KEY_PASSWD;
+ }
+}
+
+/**
+ * Restore clock settings
+ */
+__always_inline static void pmc_restore_clock_setting(
+ const uint32_t osc_setting,
+ const uint32_t pll0_setting,
+ const uint32_t pll1_setting,
+ const uint32_t mck_setting,
+ const uint32_t fmr_setting
+#if defined(EFC1)
+ , const uint32_t fmr_setting1
+#endif
+)
+{
+ uint32_t mckr;
+ uint32_t pll_sr = 0;
+
+ /* Switch mainck to external xtal */
+ if (CKGR_MOR_MOSCXTBY == (osc_setting & CKGR_MOR_MOSCXTBY)) {
+ /* Bypass mode */
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
+ CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY |
+ CKGR_MOR_MOSCSEL;
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN &
+ ~CKGR_MOR_MOSCRCF_Msk)
+ | CKGR_MOR_KEY_PASSWD;
+ } else if (CKGR_MOR_MOSCXTEN == (osc_setting & CKGR_MOR_MOSCXTEN)) {
+ /* Enable External XTAL */
+ if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCXTEN)) {
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
+ CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN;
+ /* Wait the Xtal to stabilize */
+ while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
+ }
+ /* Select External XTAL */
+ if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
+ PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL;
+ while (!(PMC->PMC_SR & PMC_SR_MOSCSELS));
+ }
+ /* Disable Fast RC */
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN &
+ ~CKGR_MOR_MOSCRCF_Msk)
+ | CKGR_MOR_KEY_PASSWD;
+ }
+
+ if (pll0_setting & CKGR_PLLAR_MULA_Msk) {
+#if (SAM4C || SAM4CM || SAMG || SAM4CP)
+ PMC->CKGR_PLLAR = pll0_setting;
+#else
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | pll0_setting;
+#endif
+ pll_sr |= PMC_SR_LOCKA;
+ }
+#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP)
+ if (pll1_setting & CKGR_PLLBR_MULB_Msk) {
+ PMC->CKGR_PLLBR = pll1_setting;
+ pll_sr |= PMC_SR_LOCKB;
+ }
+#elif (SAM3U || SAM3XA)
+ if (pll1_setting & CKGR_UCKR_UPLLEN) {
+ PMC->CKGR_UCKR = pll1_setting;
+ pll_sr |= PMC_SR_LOCKU;
+ }
+#else
+ UNUSED(pll1_setting);
+#endif
+ /* Wait MCK source ready */
+ switch(mck_setting & PMC_MCKR_CSS_Msk) {
+ case PMC_MCKR_CSS_PLLA_CLK:
+ while (!(PMC->PMC_SR & PMC_SR_LOCKA));
+ break;
+#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP)
+ case PMC_MCKR_CSS_PLLB_CLK:
+ while (!(PMC->PMC_SR & PMC_SR_LOCKB));
+ break;
+#elif (SAM3U || SAM3XA)
+ case PMC_MCKR_CSS_UPLL_CLK:
+ while (!(PMC->PMC_SR & PMC_SR_LOCKU));
+ break;
+#endif
+ }
+
+ /* Switch to faster clock */
+ mckr = PMC->PMC_MCKR;
+
+ /* Set PRES */
+ PMC->PMC_MCKR = (mckr & ~PMC_MCKR_PRES_Msk)
+ | (mck_setting & PMC_MCKR_PRES_Msk);
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
+
+ /* Restore flash wait states */
+ EFC0->EEFC_FMR = fmr_setting;
+#if defined(EFC1)
+ EFC1->EEFC_FMR = fmr_setting1;
+#endif
+
+ /* Set CSS and others */
+ PMC->PMC_MCKR = mck_setting;
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
+
+ /* Waiting all restored PLLs ready */
+ while (!(PMC->PMC_SR & pll_sr));
+}
+
+/** If clocks are switched for some sleep mode */
+static volatile bool b_is_sleep_clock_used = false;
+/** Callback invoked once when clocks are restored */
+static pmc_callback_wakeup_clocks_restored_t callback_clocks_restored = NULL;
+
+void pmc_sleep(int sleep_mode)
+{
+ switch (sleep_mode) {
+#if (!(SAMG51 || SAMG53 || SAMG54))
+ case SAM_PM_SMODE_SLEEP_WFI:
+ case SAM_PM_SMODE_SLEEP_WFE:
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70)
+ SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP;
+ cpu_irq_enable();
+ __WFI();
+ break;
+#else
+ PMC->PMC_FSMR &= (uint32_t)~PMC_FSMR_LPM;
+ SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP;
+ cpu_irq_enable();
+ if (sleep_mode == SAM_PM_SMODE_SLEEP_WFI)
+ __WFI();
+ else
+ __WFE();
+ break;
+#endif
+#endif
+
+ case SAM_PM_SMODE_WAIT_FAST:
+ case SAM_PM_SMODE_WAIT: {
+ uint32_t mor, pllr0, pllr1, mckr;
+ uint32_t fmr;
+#if defined(EFC1)
+ uint32_t fmr1;
+#endif
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70)
+ (sleep_mode == SAM_PM_SMODE_WAIT_FAST) ?
+ pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_STANDBY) :
+ pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN);
+#endif
+ cpu_irq_disable();
+ b_is_sleep_clock_used = true;
+
+#if (SAM4C || SAM4CM || SAM4CP)
+ /* Backup the sub-system 1 status and stop sub-system 1 */
+ uint32_t cpclk_backup = PMC->PMC_SCSR &
+ (PMC_SCSR_CPCK | PMC_SCSR_CPBMCK);
+ PMC->PMC_SCDR = cpclk_backup | PMC_SCDR_CPKEY_PASSWD;
+#endif
+ pmc_save_clock_settings(&mor, &pllr0, &pllr1, &mckr, &fmr,
+#if defined(EFC1)
+ &fmr1,
+#endif
+ (sleep_mode == SAM_PM_SMODE_WAIT));
+
+ /* Enter wait mode */
+ cpu_irq_enable();
+
+ pmc_enable_waitmode();
+
+ cpu_irq_disable();
+ pmc_restore_clock_setting(mor, pllr0, pllr1, mckr, fmr
+#if defined(EFC1)
+ , fmr1
+#endif
+ );
+
+#if (SAM4C || SAM4CM || SAM4CP)
+ /* Restore the sub-system 1 */
+ PMC->PMC_SCER = cpclk_backup | PMC_SCER_CPKEY_PASSWD;
+#endif
+ b_is_sleep_clock_used = false;
+ if (callback_clocks_restored) {
+ callback_clocks_restored();
+ callback_clocks_restored = NULL;
+ }
+ cpu_irq_enable();
+
+ break;
+ }
+#if (!(SAMG51 || SAMG53 || SAMG54))
+ case SAM_PM_SMODE_BACKUP:
+ SCB->SCR |= SCR_SLEEPDEEP;
+#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70)
+ SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG;
+ cpu_irq_enable();
+ __WFI() ;
+#else
+ cpu_irq_enable();
+ __WFE() ;
+#endif
+ break;
+#endif
+ }
+}
+
+bool pmc_is_wakeup_clocks_restored(void)
+{
+ return !b_is_sleep_clock_used;
+}
+
+void pmc_wait_wakeup_clocks_restore(
+ pmc_callback_wakeup_clocks_restored_t callback)
+{
+ if (b_is_sleep_clock_used) {
+ cpu_irq_disable();
+ callback_clocks_restored = callback;
+ } else if (callback) {
+ callback();
+ }
+}
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/sleep.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,133 @@
+/**
+ * \file
+ *
+ * \brief Sleep mode access
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+
+/**
+ * \defgroup sleep_group Power Manager (PM)
+ *
+ * This is a stub on the SAM Power Manager Control (PMC) for the sleepmgr
+ * service.
+ *
+ * \note To minimize the code overhead, these functions do not feature
+ * interrupt-protected access since they are likely to be called inside
+ * interrupt handlers or in applications where such protection is not
+ * necessary. If such protection is needed, it must be ensured by the calling
+ * code.
+ *
+ * @{
+ */
+
+#if defined(__DOXYGEN__)
+/**
+ * \brief Sets the MCU in the specified sleep mode
+ * \param sleep_mode Sleep mode to set.
+ */
+#endif
+/* SAM3 and SAM4 series */
+#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \
+ SAM4CM || SAM4CP || SAMG || SAMV71 || SAME70)
+
+#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \
+ SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAME70)
+# define SAM_PM_SMODE_ACTIVE 0 /**< Active */
+# define SAM_PM_SMODE_SLEEP_WFE 1 /**< Wait for Events */
+# define SAM_PM_SMODE_SLEEP_WFI 2 /**< Wait for Interrupts */
+# define SAM_PM_SMODE_WAIT_FAST 3 /**< Wait Mode, startup fast (in 3ms) */
+# define SAM_PM_SMODE_WAIT 4 /**< Wait Mode */
+# define SAM_PM_SMODE_BACKUP 5 /**< Backup Mode */
+#else
+# define SAM_PM_SMODE_ACTIVE 0 /**< Active */
+# define SAM_PM_SMODE_WAIT_FAST 1 /**< Wait Mode, startup fast (in 3ms) */
+# define SAM_PM_SMODE_WAIT 2 /**< Wait Mode */
+#endif
+
+/** (SCR) Sleep deep bit */
+#define SCR_SLEEPDEEP (0x1 << 2)
+
+/**
+ * Clocks restored callback function type.
+ * Registered by routine pmc_wait_wakeup_clocks_restore()
+ * Callback called when all clocks are restored.
+ */
+typedef void (*pmc_callback_wakeup_clocks_restored_t) (void);
+
+/**
+ * Enter sleep mode
+ * \param sleep_mode Sleep mode to enter
+ */
+void pmc_sleep(int sleep_mode);
+
+/**
+ * Check if clocks are restored after wakeup
+ * (For WAIT mode. In WAIT mode, clocks are switched to FASTRC.
+ * After wakeup clocks should be restored, before that some of the
+ * ISR should not be served, otherwise there may be timing or clock issue.)
+ */
+bool pmc_is_wakeup_clocks_restored(void);
+
+/**
+ * \return true if start waiting
+ */
+void pmc_wait_wakeup_clocks_restore(
+ pmc_callback_wakeup_clocks_restored_t callback);
+
+#endif
+
+//! @}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SLEEP_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtc/rtc.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,904 @@
+/**
+ * \file
+ *
+ * \brief Real-Time Clock (RTC) driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "rtc.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /**
+ * \defgroup sam_drivers_rtc_group Real-Time Clock (RTC)
+ *
+ * See \ref sam_rtc_quickstart.
+ *
+ * The RTC provides a full binary-coded decimal (BCD) clock that includes
+ * century (19/20), year (with leap years), month, date, day, hour, minute
+ * and second.
+ *
+ * @{
+ */
+
+ /* RTC Write Protect Key "RTC" in ASCII */
+#define RTC_WP_KEY (0x525443)
+
+ /* The BCD code shift value */
+#define BCD_SHIFT 4
+
+ /* The BCD code mask value */
+#define BCD_MASK 0xfu
+
+ /* The BCD mul/div factor value */
+#define BCD_FACTOR 10
+
+ /**
+ * \brief Set the RTC hour mode.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param ul_mode 1 for 12-hour mode, 0 for 24-hour mode.
+ */
+ void rtc_set_hour_mode(Rtc *p_rtc, uint32_t ul_mode)
+{
+ if (ul_mode) {
+ p_rtc->RTC_MR |= RTC_MR_HRMOD;
+ } else {
+ p_rtc->RTC_MR &= (~RTC_MR_HRMOD);
+ }
+}
+
+/**
+ * \brief Get the RTC hour mode.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ *
+ * \return 1 for 12-hour mode, 0 for 24-hour mode.
+ */
+uint32_t rtc_get_hour_mode(Rtc *p_rtc)
+{
+ uint32_t ul_temp = p_rtc->RTC_MR;
+
+ if (ul_temp & RTC_MR_HRMOD) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Enable RTC interrupts.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param ul_sources Interrupts to be enabled.
+ */
+void rtc_enable_interrupt(Rtc *p_rtc, uint32_t ul_sources)
+{
+ p_rtc->RTC_IER = ul_sources;
+}
+
+/**
+ * \brief Disable RTC interrupts.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param ul_sources Interrupts to be disabled.
+ */
+void rtc_disable_interrupt(Rtc *p_rtc, uint32_t ul_sources)
+{
+ p_rtc->RTC_IDR = ul_sources;
+}
+
+/**
+ * \brief Read RTC interrupt mask.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ *
+ * \return The interrupt mask value.
+ */
+uint32_t rtc_get_interrupt_mask(Rtc *p_rtc)
+{
+ return p_rtc->RTC_IMR;
+}
+
+/**
+ * \brief Get the RTC time value.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param pul_hour Current hour, 24-hour mode.
+ * \param pul_minute Current minute.
+ * \param pul_second Current second.
+ */
+void rtc_get_time(Rtc *p_rtc, uint32_t *pul_hour, uint32_t *pul_minute,
+ uint32_t *pul_second)
+{
+ uint32_t ul_time;
+ uint32_t ul_temp;
+
+ /* Get the current RTC time (multiple reads are necessary to insure a stable value). */
+ ul_time = p_rtc->RTC_TIMR;
+ while (ul_time != p_rtc->RTC_TIMR) {
+ ul_time = p_rtc->RTC_TIMR;
+ }
+
+ /* Hour */
+ if (pul_hour) {
+ ul_temp = (ul_time & RTC_TIMR_HOUR_Msk) >> RTC_TIMR_HOUR_Pos;
+ *pul_hour = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK);
+
+ if ((ul_time & RTC_TIMR_AMPM) == RTC_TIMR_AMPM) {
+ *pul_hour += 12;
+ }
+ }
+
+ /* Minute */
+ if (pul_minute) {
+ ul_temp = (ul_time & RTC_TIMR_MIN_Msk) >> RTC_TIMR_MIN_Pos;
+ *pul_minute = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK);
+ }
+
+ /* Second */
+ if (pul_second) {
+ ul_temp = (ul_time & RTC_TIMR_SEC_Msk) >> RTC_TIMR_SEC_Pos;
+ *pul_second = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK);
+ }
+}
+
+/**
+ * \brief Set the RTC time value.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param ul_hour Current hour, 24-hour mode.
+ * \param ul_minute Current minute.
+ * \param ul_second Current second.
+ *
+ * \return 0 for OK, else invalid setting.
+ */
+uint32_t rtc_set_time(Rtc *p_rtc, uint32_t ul_hour, uint32_t ul_minute,
+ uint32_t ul_second)
+{
+ uint32_t ul_time = 0;
+
+ /* If 12-hour mode, set AMPM bit */
+ if ((p_rtc->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD) {
+ if (ul_hour > 12) {
+ ul_hour -= 12;
+ ul_time |= RTC_TIMR_AMPM;
+ }
+ }
+
+ /* Hour */
+ ul_time |= ((ul_hour / BCD_FACTOR) << (RTC_TIMR_HOUR_Pos + BCD_SHIFT)) |
+ ((ul_hour % BCD_FACTOR) << RTC_TIMR_HOUR_Pos);
+
+ /* Minute */
+ ul_time |= ((ul_minute / BCD_FACTOR) << (RTC_TIMR_MIN_Pos + BCD_SHIFT)) |
+ ((ul_minute % BCD_FACTOR) << RTC_TIMR_MIN_Pos);
+
+ /* Second */
+ ul_time |= ((ul_second / BCD_FACTOR) << (RTC_TIMR_SEC_Pos + BCD_SHIFT)) |
+ ((ul_second % BCD_FACTOR) << RTC_TIMR_SEC_Pos);
+
+ /* Update time register. Check the spec for the flow. */
+ p_rtc->RTC_CR |= RTC_CR_UPDTIM;
+ while ((p_rtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD);
+ p_rtc->RTC_SCCR = RTC_SCCR_ACKCLR;
+ p_rtc->RTC_TIMR = ul_time;
+ p_rtc->RTC_CR &= (~RTC_CR_UPDTIM);
+ p_rtc->RTC_SCCR |= RTC_SCCR_SECCLR;
+
+ return (p_rtc->RTC_VER & RTC_VER_NVTIM);
+}
+
+/**
+ * \brief Set the RTC alarm time value.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param ul_hour_flag 1 for setting, 0 for not setting.
+ * \param ul_hour Alarm hour value, 24-hour mode.
+ * \param ul_minute_flag 1 for setting, 0 for not setting.
+ * \param ul_minute Alarm minute value.
+ * \param ul_second_flag 1 for setting, 0 for not setting.
+ * \param ul_second Alarm second value.
+ *
+ * \return 0 for OK, else invalid setting.
+ */
+uint32_t rtc_set_time_alarm(Rtc *p_rtc,
+ uint32_t ul_hour_flag, uint32_t ul_hour,
+ uint32_t ul_minute_flag, uint32_t ul_minute,
+ uint32_t ul_second_flag, uint32_t ul_second)
+{
+ uint32_t ul_alarm = 0;
+
+ /* Hour alarm setting */
+ if (ul_hour_flag) {
+ /* If 12-hour mode, set AMPM bit */
+ if ((p_rtc->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD) {
+ if (ul_hour > 12) {
+ ul_hour -= 12;
+ ul_alarm |= RTC_TIMR_AMPM;
+ }
+ }
+
+ ul_alarm |= ((ul_hour / BCD_FACTOR) << (RTC_TIMR_HOUR_Pos + BCD_SHIFT)) |
+ ((ul_hour % BCD_FACTOR) << RTC_TIMR_HOUR_Pos);
+ }
+
+ /* Minute alarm setting */
+ if (ul_minute_flag) {
+ ul_alarm |= ((ul_minute / BCD_FACTOR) << (RTC_TIMR_MIN_Pos + BCD_SHIFT)) |
+ ((ul_minute % BCD_FACTOR) << RTC_TIMR_MIN_Pos);
+ }
+
+ /* Second alarm setting */
+ if (ul_second_flag) {
+ ul_alarm |= ((ul_second / BCD_FACTOR) << (RTC_TIMR_SEC_Pos + BCD_SHIFT)) |
+ ((ul_second % BCD_FACTOR) << RTC_TIMR_SEC_Pos);
+ }
+
+ p_rtc->RTC_TIMALR &= ~(RTC_TIMALR_SECEN | RTC_TIMALR_MINEN | RTC_TIMALR_HOUREN);
+ p_rtc->RTC_TIMALR = ul_alarm;
+ p_rtc->RTC_TIMALR |= (RTC_TIMALR_SECEN | RTC_TIMALR_MINEN | RTC_TIMALR_HOUREN);
+
+ return (p_rtc->RTC_VER & RTC_VER_NVTIMALR);
+}
+
+/**
+ * \brief Get the RTC date value.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param pul_year Current year.
+ * \param pul_month Current month.
+ * \param pul_day Current day.
+ * \param pul_week Current day in current week.
+ */
+void rtc_get_date(Rtc *p_rtc, uint32_t *pul_year, uint32_t *pul_month,
+ uint32_t *pul_day, uint32_t *pul_week)
+{
+ uint32_t ul_date;
+ uint32_t ul_cent;
+ uint32_t ul_temp;
+
+ /* Get the current date (multiple reads are necessary to insure a stable value). */
+ ul_date = p_rtc->RTC_CALR;
+ while (ul_date != p_rtc->RTC_CALR) {
+ ul_date = p_rtc->RTC_CALR;
+ }
+
+ /* Retrieve year */
+ if (pul_year) {
+ ul_temp = (ul_date & RTC_CALR_CENT_Msk) >> RTC_CALR_CENT_Pos;
+ ul_cent = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK);
+ ul_temp = (ul_date & RTC_CALR_YEAR_Msk) >> RTC_CALR_YEAR_Pos;
+ *pul_year = (ul_cent * BCD_FACTOR * BCD_FACTOR) +
+ (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK);
+ }
+
+ /* Retrieve month */
+ if (pul_month) {
+ ul_temp = (ul_date & RTC_CALR_MONTH_Msk) >> RTC_CALR_MONTH_Pos;
+ *pul_month = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK);
+ }
+
+ /* Retrieve day */
+ if (pul_day) {
+ ul_temp = (ul_date & RTC_CALR_DATE_Msk) >> RTC_CALR_DATE_Pos;
+ *pul_day = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK);
+ }
+
+ /* Retrieve week */
+ if (pul_week) {
+ *pul_week = ((ul_date & RTC_CALR_DAY_Msk) >> RTC_CALR_DAY_Pos);
+ }
+}
+
+/**
+ * \brief Set the RTC date.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param ul_year Current year.
+ * \param ul_month Current month.
+ * \param ul_day Current day.
+ * \param ul_week Current day in current week.
+ *
+ * \return 0 for OK, else invalid setting.
+ */
+uint32_t rtc_set_date(Rtc *p_rtc, uint32_t ul_year, uint32_t ul_month,
+ uint32_t ul_day, uint32_t ul_week)
+{
+ uint32_t ul_date = 0;
+
+ /* Cent */
+ ul_date |= ((ul_year / BCD_FACTOR / BCD_FACTOR / BCD_FACTOR) <<
+ (RTC_CALR_CENT_Pos + BCD_SHIFT) |
+ ((ul_year / BCD_FACTOR / BCD_FACTOR) % BCD_FACTOR) << RTC_CALR_CENT_Pos);
+
+ /* Year */
+ ul_date |= (((ul_year / BCD_FACTOR) % BCD_FACTOR) <<
+ (RTC_CALR_YEAR_Pos + BCD_SHIFT)) |
+ ((ul_year % BCD_FACTOR) << RTC_CALR_YEAR_Pos);
+
+ /* Month */
+ ul_date |= ((ul_month / BCD_FACTOR) << (RTC_CALR_MONTH_Pos + BCD_SHIFT)) |
+ ((ul_month % BCD_FACTOR) << RTC_CALR_MONTH_Pos);
+
+ /* Week */
+ ul_date |= (ul_week << RTC_CALR_DAY_Pos);
+
+ /* Day */
+ ul_date |= ((ul_day / BCD_FACTOR) << (RTC_CALR_DATE_Pos + BCD_SHIFT)) |
+ ((ul_day % BCD_FACTOR) << RTC_CALR_DATE_Pos);
+
+ /* Update calendar register. Check the spec for the flow. */
+ p_rtc->RTC_CR |= RTC_CR_UPDCAL;
+ while ((p_rtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD);
+
+ p_rtc->RTC_SCCR = RTC_SCCR_ACKCLR;
+ p_rtc->RTC_CALR = ul_date;
+ p_rtc->RTC_CR &= (~RTC_CR_UPDCAL);
+ /* Clear SECENV in SCCR */
+ p_rtc->RTC_SCCR |= RTC_SCCR_SECCLR;
+
+ return (p_rtc->RTC_VER & RTC_VER_NVCAL);
+}
+
+/**
+ * \brief Set the RTC alarm date value.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param ul_month_flag 1 for setting, 0 for not setting.
+ * \param ul_month Alarm month value.
+ * \param ul_day_flag 1 for setting, 0 for not setting.
+ * \param ul_day Alarm day value.
+ *
+ * \return 0 for OK, else invalid setting.
+ */
+uint32_t rtc_set_date_alarm(Rtc *p_rtc,
+ uint32_t ul_month_flag, uint32_t ul_month,
+ uint32_t ul_day_flag, uint32_t ul_day)
+{
+ uint32_t ul_alarm = 0;
+
+ /* Month alarm setting */
+ if (ul_month_flag) {
+ ul_alarm |= ((ul_month / BCD_FACTOR) << (RTC_CALR_MONTH_Pos + BCD_SHIFT)) |
+ ((ul_month % BCD_FACTOR) << RTC_CALR_MONTH_Pos);
+ }
+
+ /* Day alarm setting */
+ if (ul_day_flag) {
+ ul_alarm |= ((ul_day / BCD_FACTOR) << (RTC_CALR_DATE_Pos + BCD_SHIFT)) |
+ ((ul_day % BCD_FACTOR) << RTC_CALR_DATE_Pos);
+ }
+
+ /* Set alarm */
+ p_rtc->RTC_CALALR &= ~(RTC_CALALR_MTHEN | RTC_CALALR_DATEEN);
+ p_rtc->RTC_CALALR = ul_alarm;
+ p_rtc->RTC_CALALR |= (RTC_CALALR_MTHEN | RTC_CALALR_DATEEN);
+
+ return (p_rtc->RTC_VER & RTC_VER_NVCALALR);
+}
+
+/**
+ * \brief Clear the RTC time alarm setting.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ */
+void rtc_clear_time_alarm(Rtc *p_rtc)
+{
+ p_rtc->RTC_TIMALR = 0;
+}
+
+/**
+ * \brief Clear the RTC date alarm setting.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ */
+void rtc_clear_date_alarm(Rtc *p_rtc)
+{
+ /* Need a valid value without enabling */
+ p_rtc->RTC_CALALR = RTC_CALALR_MONTH(0x01) | RTC_CALALR_DATE(0x01);
+}
+
+/**
+ * \brief Get the RTC status.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ *
+ * \return Status of the RTC.
+ */
+uint32_t rtc_get_status(Rtc *p_rtc)
+{
+ return (p_rtc->RTC_SR);
+}
+
+/**
+ * \brief Set the RTC SCCR to clear status bits.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param ul_clear Some flag bits which will be cleared.
+ */
+void rtc_clear_status(Rtc *p_rtc, uint32_t ul_clear)
+{
+ p_rtc->RTC_SCCR = ul_clear;
+}
+
+/**
+ * \brief Get the RTC valid entry.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ *
+ * \return 0 for no invalid data, else has contained invalid data.
+ */
+uint32_t rtc_get_valid_entry(Rtc *p_rtc)
+{
+ return (p_rtc->RTC_VER);
+}
+
+/**
+ * \brief Set the RTC time event selection.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param ul_selection Time event selection to be enabled.
+ */
+void rtc_set_time_event(Rtc *p_rtc, uint32_t ul_selection)
+{
+ p_rtc->RTC_CR &= ~RTC_CR_TIMEVSEL_Msk;
+ p_rtc->RTC_CR |= (ul_selection << RTC_CR_TIMEVSEL_Pos) & RTC_CR_TIMEVSEL_Msk;
+}
+
+/**
+ * \brief Set the RTC calendar event selection.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param ul_selection Calendar event selection to be enabled..
+ */
+void rtc_set_calendar_event(Rtc *p_rtc, uint32_t ul_selection)
+{
+ p_rtc->RTC_CR &= ~RTC_CR_CALEVSEL_Msk;
+ p_rtc->RTC_CR |= (ul_selection << RTC_CR_CALEVSEL_Pos) & RTC_CR_CALEVSEL_Msk;
+}
+
+#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4N) || (SAM4C) || (SAMG) || (SAM4CP) || (SAM4CM))
+/**
+ * \brief Set the RTC calendar mode.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param ul_mode 1 for Persian mode,0 for Gregorian mode.
+ */
+void rtc_set_calendar_mode(Rtc *p_rtc, uint32_t ul_mode)
+{
+ if (ul_mode) {
+ p_rtc->RTC_MR |= RTC_MR_PERSIAN;
+ } else {
+ p_rtc->RTC_MR &= (~RTC_MR_PERSIAN);
+ }
+}
+
+/**
+ * \brief Get the RTC calendar mode.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ *
+ * \return 1 for Persian calendar, 0 for Gregorian calendar.
+ */
+uint32_t rtc_get_calendar_mode(Rtc *p_rtc)
+{
+ uint32_t ul_temp = p_rtc->RTC_MR;
+
+ if (ul_temp & RTC_MR_PERSIAN) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Set the RTC calibration.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param ul_direction_ppm Positive/negative correction.
+ * \param ul_correction Correction value.
+ * \param ul_range_ppm Low/high range correction.
+ */
+void rtc_set_calibration(Rtc *p_rtc, uint32_t ul_direction_ppm,
+ uint32_t ul_correction, uint32_t ul_range_ppm)
+{
+ uint32_t ul_temp;
+
+ ul_temp = p_rtc->RTC_MR;
+
+ if (ul_direction_ppm) {
+ ul_temp |= RTC_MR_NEGPPM;
+ } else {
+ ul_temp &= (~RTC_MR_NEGPPM);
+ }
+
+ ul_temp |= RTC_MR_CORRECTION(ul_correction);
+
+ if (ul_range_ppm) {
+ ul_temp |= RTC_MR_HIGHPPM;
+ } else {
+ ul_temp &= (~RTC_MR_HIGHPPM);
+ }
+
+ p_rtc->RTC_MR = ul_temp;
+}
+#endif
+
+#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4C) || (SAMG) || (SAM4CP) || (SAM4CM) || SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Set the RTC output waveform.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param ul_channel Output channel selection.
+ * \param ul_value Output source selection value.
+ */
+void rtc_set_waveform(Rtc *p_rtc, uint32_t ul_channel, uint32_t ul_value)
+{
+ if (ul_channel == 0) {
+ switch (ul_value) {
+ case 0:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT0_NO_WAVE;
+ break;
+
+ case 1:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT0_FREQ1HZ;
+ break;
+
+ case 2:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT0_FREQ32HZ;
+ break;
+
+ case 3:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT0_FREQ64HZ;
+ break;
+
+ case 4:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT0_FREQ512HZ;
+ break;
+
+#if (!SAMG)
+ case 5:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT0_ALARM_TOGGLE;
+ break;
+#endif
+
+ case 6:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT0_ALARM_FLAG;
+ break;
+
+#if (!SAMG)
+ case 7:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT0_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT0_PROG_PULSE;
+ break;
+#endif
+
+ default:
+ break;
+ }
+ } else {
+#if (!SAM4C && !SAM4CP && !SAM4CM)
+ switch (ul_value) {
+ case 0:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT1_NO_WAVE;
+ break;
+
+ case 1:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT1_FREQ1HZ;
+ break;
+
+ case 2:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT1_FREQ32HZ;
+ break;
+
+ case 3:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT1_FREQ64HZ;
+ break;
+
+ case 4:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT1_FREQ512HZ;
+ break;
+
+#if (!SAMG)
+ case 5:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT1_ALARM_TOGGLE;
+ break;
+#endif
+
+ case 6:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT1_ALARM_FLAG;
+ break;
+
+#if (!SAMG)
+ case 7:
+ p_rtc->RTC_MR &= ~RTC_MR_OUT1_Msk;
+ p_rtc->RTC_MR |= RTC_MR_OUT1_PROG_PULSE;
+ break;
+#endif
+
+ default:
+ break;
+ }
+#endif
+ }
+}
+
+#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4C) || SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Set the pulse output waveform parameters.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param ul_time_high High duration of the output pulse.
+ * \param ul_period Period of the output pulse.
+ */
+void rtc_set_pulse_parameter(Rtc *p_rtc, uint32_t ul_time_high,
+ uint32_t ul_period)
+{
+ uint32_t ul_temp;
+
+ ul_temp = p_rtc->RTC_MR;
+
+ ul_temp |= (RTC_MR_THIGH_Msk & ((ul_time_high) << RTC_MR_THIGH_Pos));
+ ul_temp |= (RTC_MR_TPERIOD_Msk & ((ul_period) << RTC_MR_TPERIOD_Pos));
+
+ p_rtc->RTC_MR = ul_temp;
+}
+#endif
+#endif
+
+
+#if ((SAM3N) || (SAM3U) || (SAM3XA))
+/**
+ * \brief Enable or disable write protection of RTC registers.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param ul_enable 1 to enable, 0 to disable.
+ */
+void rtc_set_writeprotect(Rtc *p_rtc, uint32_t ul_enable)
+{
+ if (ul_enable) {
+ p_rtc->RTC_WPMR = RTC_WPMR_WPKEY(RTC_WP_KEY) | RTC_WPMR_WPEN;
+ } else {
+ p_rtc->RTC_WPMR = RTC_WPMR_WPKEY(RTC_WP_KEY);
+ }
+}
+#endif /* ((SAM3N) || (SAM3U) || (SAM3XA)) */
+
+#if SAM4C || SAM4CP || SAM4CM
+/**
+ * \brief Get the RTC tamper time value.
+ *
+ * \note This function should be called before rtc_get_tamper_source()
+ * function call, Otherwise the tamper time will be cleared.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param pul_hour Current hour, 24-hour mode.
+ * \param pul_minute Current minute.
+ * \param pul_second Current second.
+ * \param reg_num Current tamper register set number.
+ */
+void rtc_get_tamper_time(Rtc *p_rtc, uint32_t *pul_hour, uint32_t *pul_minute,
+ uint32_t *pul_second, uint8_t reg_num)
+{
+ uint32_t ul_time;
+ uint32_t ul_temp;
+
+ /* Get the current RTC time (multiple reads are to insure a stable value). */
+ ul_time = p_rtc->RTC_TS[reg_num].RTC_TSTR;
+ while (ul_time != p_rtc->RTC_TS[reg_num].RTC_TSTR) {
+ ul_time = p_rtc->RTC_TS[reg_num].RTC_TSTR;
+ }
+
+ /* Hour */
+ if (pul_hour) {
+ ul_temp = (ul_time & RTC_TSTR_HOUR_Msk) >> RTC_TSTR_HOUR_Pos;
+ *pul_hour = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK);
+
+ if ((ul_time & RTC_TSTR_AMPM) == RTC_TSTR_AMPM) {
+ *pul_hour += 12;
+ }
+ }
+
+ /* Minute */
+ if (pul_minute) {
+ ul_temp = (ul_time & RTC_TSTR_MIN_Msk) >> RTC_TSTR_MIN_Pos;
+ *pul_minute = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK);
+ }
+
+ /* Second */
+ if (pul_second) {
+ ul_temp = (ul_time & RTC_TSTR_SEC_Msk) >> RTC_TSTR_SEC_Pos;
+ *pul_second = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK);
+ }
+}
+
+/**
+ * \brief Get the RTC tamper date.
+ *
+ * \note This function should be called before rtc_get_tamper_source()
+ * function call, Otherwise the tamper date will be cleared.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param pul_year Current year.
+ * \param pul_month Current month.
+ * \param pul_day Current day.
+ * \param pul_week Current day in current week.
+ * \param reg_num Current tamper register set number.
+ */
+void rtc_get_tamper_date(Rtc *p_rtc, uint32_t *pul_year, uint32_t *pul_month,
+ uint32_t *pul_day, uint32_t *pul_week, uint8_t reg_num)
+{
+ uint32_t ul_date;
+ uint32_t ul_cent;
+ uint32_t ul_temp;
+
+ /* Get the current date (multiple reads are to insure a stable value). */
+ ul_date = p_rtc->RTC_TS[reg_num].RTC_TSDR;
+ while (ul_date != p_rtc->RTC_TS[reg_num].RTC_TSDR) {
+ ul_date = p_rtc->RTC_TS[reg_num].RTC_TSDR;
+ }
+
+ /* Retrieve year */
+ if (pul_year) {
+ ul_temp = (ul_date & RTC_TSDR_CENT_Msk) >> RTC_TSDR_CENT_Pos;
+ ul_cent = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK);
+ ul_temp = (ul_date & RTC_TSDR_YEAR_Msk) >> RTC_TSDR_YEAR_Pos;
+ *pul_year = (ul_cent * BCD_FACTOR * BCD_FACTOR) +
+ (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK);
+ }
+
+ /* Retrieve month */
+ if (pul_month) {
+ ul_temp = (ul_date & RTC_TSDR_MONTH_Msk) >> RTC_TSDR_MONTH_Pos;
+ *pul_month = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK);
+ }
+
+ /* Retrieve day */
+ if (pul_day) {
+ ul_temp = (ul_date & RTC_TSDR_DATE_Msk) >> RTC_TSDR_DATE_Pos;
+ *pul_day = (ul_temp >> BCD_SHIFT) * BCD_FACTOR + (ul_temp & BCD_MASK);
+ }
+
+ /* Retrieve week */
+ if (pul_week) {
+ *pul_week = ((ul_date & RTC_TSDR_DAY_Msk) >> RTC_TSDR_DAY_Pos);
+ }
+}
+
+/**
+ * \brief Get the RTC tamper source.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param reg_num Current tamper register set number.
+ *
+ * \return Tamper source.
+ */
+uint32_t rtc_get_tamper_source(Rtc *p_rtc, uint8_t reg_num)
+{
+ return (p_rtc->RTC_TS[reg_num].RTC_TSSR & RTC_TSSR_TSRC_Msk) >>
+ RTC_TSSR_TSRC_Pos;
+}
+
+/**
+ * \brief Get the RTC tamper event counter.
+ *
+ * \note This function should be called before rtc_get_tamper_source()
+ * function call, Otherwise the tamper event counter will be cleared.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ *
+ * \return Tamper event counter
+ */
+uint32_t rtc_get_tamper_event_counter(Rtc *p_rtc)
+{
+ return (p_rtc->RTC_TS[0].RTC_TSTR & RTC_TSTR_TEVCNT_Msk) >>
+ RTC_TSTR_TEVCNT_Pos;
+}
+
+/**
+ * \brief Check the system is in backup mode when RTC tamper event happen.
+ *
+ * \note This function should be called before rtc_get_tamper_source()
+ * function call, Otherwise the flag indicates tamper occur in backup
+ * mode will be cleared.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ * \param reg_num Current tamper register set number.
+ *
+ * \return True - The system is in backup mode when the tamper event occurs.
+ * Flase - The system is different from backup mode.
+ */
+bool rtc_is_tamper_occur_in_backup_mode(Rtc *p_rtc, uint8_t reg_num)
+{
+ if(p_rtc->RTC_TS[reg_num].RTC_TSTR & RTC_TSTR_BACKUP) {
+ return true;
+ } else {
+ return false;
+ }
+}
+#endif
+
+#if (SAMG55)
+/**
+ * \brief Get the RTC milliseconds value.
+ *
+ * \param p_rtc Pointer to an RTC instance.
+ *
+ * \return Number of 1/1024 seconds elapsed within one second.
+ */
+uint32_t rtc_get_milliseconds(Rtc *p_rtc)
+{
+ return (p_rtc->RTC_MSR) & RTC_MSR_MS_Msk;
+}
+#endif
+
+
+//@}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtc/rtc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,192 @@
+/**
+ * \file
+ *
+ * \brief Real-Time Clock (RTC) driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef RTC_H_INCLUDED
+#define RTC_H_INCLUDED
+
+#include "compiler.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ void rtc_set_hour_mode(Rtc *p_rtc, uint32_t ul_mode);
+ uint32_t rtc_get_hour_mode(Rtc *p_rtc);
+ void rtc_enable_interrupt(Rtc *p_rtc, uint32_t ul_sources);
+ void rtc_disable_interrupt(Rtc *p_rtc, uint32_t ul_sources);
+ uint32_t rtc_get_interrupt_mask(Rtc *p_rtc);
+ void rtc_get_time(Rtc *p_rtc, uint32_t *pul_hour, uint32_t *pul_minute,
+ uint32_t *pul_second);
+ uint32_t rtc_set_time(Rtc *p_rtc, uint32_t ul_hour, uint32_t ul_minute,
+ uint32_t ul_second);
+ uint32_t rtc_set_time_alarm(Rtc *p_rtc,
+ uint32_t ul_hour_flag, uint32_t ul_hour,
+ uint32_t ul_minute_flag, uint32_t ul_minute,
+ uint32_t ul_second_flag, uint32_t ul_second);
+ void rtc_get_date(Rtc *p_rtc, uint32_t *pul_year, uint32_t *pul_month,
+ uint32_t *pul_day, uint32_t *pul_week);
+ uint32_t rtc_set_date(Rtc *p_rtc, uint32_t ul_year, uint32_t ul_month,
+ uint32_t ul_day, uint32_t ul_week);
+ uint32_t rtc_set_date_alarm(Rtc *p_rtc,
+ uint32_t ul_month_flag, uint32_t ul_month,
+ uint32_t ul_day_flag, uint32_t ul_day);
+ void rtc_clear_time_alarm(Rtc *p_rtc);
+ void rtc_clear_date_alarm(Rtc *p_rtc);
+ uint32_t rtc_get_status(Rtc *p_rtc);
+ void rtc_clear_status(Rtc *p_rtc, uint32_t ul_clear);
+ uint32_t rtc_get_valid_entry(Rtc *p_rtc);
+ void rtc_set_time_event(Rtc *p_rtc, uint32_t ul_selection);
+ void rtc_set_calendar_event(Rtc *p_rtc, uint32_t ul_selection);
+
+#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4N) || (SAM4C) || (SAMG) || (SAM4CP) || (SAM4CM))
+ void rtc_set_calendar_mode(Rtc *p_rtc, uint32_t ul_mode);
+ uint32_t rtc_get_calendar_mode(Rtc *p_rtc);
+ void rtc_set_calibration(Rtc *p_rtc, uint32_t ul_direction_ppm,
+ uint32_t ul_correction, uint32_t ul_range_ppm);
+#endif
+
+#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4C) || (SAMG) || (SAM4CP) || (SAM4CM) || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ void rtc_set_waveform(Rtc *p_rtc, uint32_t ul_channel, uint32_t ul_value);
+#if ((SAM3S8) || (SAM3SD8) || (SAM4S) || (SAM4C)|| (SAM4CP) || (SAM4CM) || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ void rtc_set_pulse_parameter(Rtc *p_rtc, uint32_t ul_time_high,
+ uint32_t ul_period);
+#endif
+#endif
+
+#if ((SAM3N) || (SAM3U) || (SAM3XA))
+ void rtc_set_writeprotect(Rtc *p_rtc, uint32_t ul_enable);
+#endif /* ((SAM3N) || (SAM3U) || (SAM3XA)) */
+
+#if ((SAM4C) || (SAM4CP) || (SAM4CM))
+ void rtc_get_tamper_time(Rtc *p_rtc, uint32_t *pul_hour, uint32_t *pul_minute,
+ uint32_t *pul_second, uint8_t reg_num);
+ void rtc_get_tamper_date(Rtc *p_rtc, uint32_t *pul_year, uint32_t *pul_month,
+ uint32_t *pul_day, uint32_t *pul_week, uint8_t reg_num);
+ uint32_t rtc_get_tamper_source(Rtc *p_rtc, uint8_t reg_num);
+ uint32_t rtc_get_tamper_event_counter(Rtc *p_rtc);
+ bool rtc_is_tamper_occur_in_backup_mode(Rtc *p_rtc, uint8_t reg_num);
+#endif
+
+#if (SAMG55)
+ uint32_t rtc_get_milliseconds(Rtc *p_rtc);
+#endif
+
+ /**
+ * \page sam_rtc_quickstart Quickstart guide for SAM RTC driver
+ *
+ * This is the quickstart guide for the \ref rtc_group "SAM RTC driver",
+ * with step-by-step instructions on how to configure and use the driver in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section rtc_basic_use_case Basic use case
+ * In this basic use case, the RTC module is using 32kHz external crystal and
+ * configured for 24-hour mode. It will read the current date and time.
+ *
+ * \subsection sam_rtc_quickstart_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (Sysclock)"
+ *
+ * \section rtc_basic_use_case_setup Setup steps
+ * \subsection rtc_basic_use_case_setup_code Example code
+ * Add to application C-file:
+ * \code
+ void rtc_setup(void)
+ {
+ pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);
+
+ while (!pmc_osc_is_ready_32kxtal());
+
+ rtc_set_hour_mode(RTC, 0);
+ }
+ \endcode
+ *
+ * \subsection rtc_basic_use_case_setup_flow Workflow
+ * - \note Please make sure the external 32kHz crystal is available.
+ * -# Enable the External 32K crystal :
+ * - \code pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); \endcode
+ * -# Wait for 32K crystal ready:
+ * - \code while (!pmc_osc_is_ready_32kxtal()); \endcode
+ * -# Set default RTC configuration, 24-hour mode .
+ * - \code rtc_set_hour_mode(RTC, 0); \endcode
+ *
+ * \section rtc_basic_use_case_usage Usage steps
+ * \subsection rtc_basic_use_case_usage_code Example code
+ * Add to, e.g., main loop in application C-file:
+ * \code
+ uint32_t hour, minute, second;
+ uint32_t year, month, day, week;
+
+ rtc_get_time(RTC, &hour, &minute, &second);
+ rtc_get_date(RTC, &year, &month, &day, &week);
+ \endcode
+ *
+ * \subsection rtc_basic_use_case_usage_flow Workflow
+ * -# Start Define the variables for the date and time:
+ * - \code uint32_t hour, minute, second; \endcode
+ * - \code uint32_t year, month, day, week; \endcode
+ * -# Read current time:
+ * - \code rtc_get_time(RTC, &hour, &minute, &second); \endcode
+ * -# Read current date:
+ * - \code rtc_get_date(RTC, &year, &month, &day, &week); \endcode
+ *
+ */
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* RTC_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtt/rtt.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,260 @@
+/**
+ * \file
+ *
+ * \brief Real-time Timer (RTT) driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "rtt.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /**
+ * \defgroup sam_drivers_rtt_group Real-time Timer (RTT)
+ *
+ * The Real-time Timer is built around a 32-bit counter used to count
+ * roll-over events of the programmable 16-bit prescaler, which enables
+ * counting elapsed seconds from a 32 kHz slow clock source.
+ * This is a driver for configuration and use of the RTT peripheral.
+ *
+ * @{
+ */
+
+ /*
+ * In follow series chip, the bit RTC1HZ and RTTDIS in RTT_MR are write only.
+ * So we use a variable to record status of these bits.
+ */
+#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG51 || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ static uint32_t g_wobits_in_rtt_mr = 0;
+#endif
+
+ /**
+ * \brief Initialize the given RTT.
+ *
+ * \note This function restarts the real-time timer. If w_prescaler is equal to zero,
+ * the prescaler period is equal to 2^16 * SCLK period. If not, the prescaler period
+ * is equal to us_prescaler * SCLK period.
+ *
+ * \param p_rtt Pointer to an RTT instance.
+ * \param us_prescaler Prescaler value for the RTT.
+ *
+ * \return 0 if successful.
+ */
+ uint32_t rtt_init(Rtt *p_rtt, uint16_t us_prescaler)
+{
+#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG51 || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ p_rtt->RTT_MR = (us_prescaler | RTT_MR_RTTRST | g_wobits_in_rtt_mr);
+#else
+ p_rtt->RTT_MR = (us_prescaler | RTT_MR_RTTRST);
+#endif
+ return 0;
+}
+
+#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG51 || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Select RTT counter source.
+ *
+ * \param p_rtt Pointer to an RTT instance.
+ * \param is_rtc_sel RTC 1Hz Clock Selection.
+ */
+void rtt_sel_source(Rtt *p_rtt, bool is_rtc_sel)
+{
+ if(is_rtc_sel) {
+ g_wobits_in_rtt_mr |= RTT_MR_RTC1HZ;
+ p_rtt->RTT_MR |= g_wobits_in_rtt_mr;
+ } else {
+ g_wobits_in_rtt_mr &= ~RTT_MR_RTC1HZ;
+ p_rtt->RTT_MR |= g_wobits_in_rtt_mr;
+ }
+}
+
+/**
+ * \brief Enable RTT.
+ *
+ * \param p_rtt Pointer to an RTT instance.
+ */
+void rtt_enable(Rtt *p_rtt)
+{
+ g_wobits_in_rtt_mr &= ~RTT_MR_RTTDIS;
+ p_rtt->RTT_MR |= g_wobits_in_rtt_mr;
+}
+/**
+ * \brief Disable RTT.
+ *
+ * \param p_rtt Pointer to an RTT instance.
+ */
+void rtt_disable(Rtt *p_rtt)
+{
+ g_wobits_in_rtt_mr |= RTT_MR_RTTDIS;
+ p_rtt->RTT_MR |= g_wobits_in_rtt_mr;
+}
+#elif (SAMG53 || SAMG54 || SAMG55)
+void rtt_sel_source(Rtt *p_rtt, bool is_rtc_sel)
+{
+ if(is_rtc_sel) {
+ p_rtt->RTT_MR |= RTT_MR_RTC1HZ;
+ } else {
+ p_rtt->RTT_MR &= ~RTT_MR_RTC1HZ;
+ }
+}
+
+void rtt_enable(Rtt *p_rtt)
+{
+ p_rtt->RTT_MR &= ~RTT_MR_RTTDIS;
+}
+/**
+ * \brief Disable RTT.
+ *
+ * \param p_rtt Pointer to an RTT instance.
+ */
+void rtt_disable(Rtt *p_rtt)
+{
+ p_rtt->RTT_MR |= RTT_MR_RTTDIS;
+}
+#endif
+
+/**
+ * \brief Enable RTT interrupts.
+ *
+ * \param p_rtt Pointer to an RTT instance.
+ * \param ul_sources Interrupts to be enabled.
+ */
+void rtt_enable_interrupt(Rtt *p_rtt, uint32_t ul_sources)
+{
+ uint32_t temp;
+
+ temp = p_rtt->RTT_MR;
+ temp |= ul_sources;
+#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG51 || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ temp |= g_wobits_in_rtt_mr;
+#endif
+ p_rtt->RTT_MR = temp;
+}
+
+/**
+ * \brief Disable RTT interrupts.
+ *
+ * \param p_rtt Pointer to an RTT instance.
+ * \param ul_sources Interrupts to be disabled.
+ */
+void rtt_disable_interrupt(Rtt *p_rtt, uint32_t ul_sources)
+{
+ uint32_t temp = 0;
+
+ temp = p_rtt->RTT_MR;
+ temp &= (~ul_sources);
+#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG51 || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ temp |= g_wobits_in_rtt_mr;
+#endif
+ p_rtt->RTT_MR = temp;
+}
+
+/**
+ * \brief Read the current value of the RTT timer value.
+ *
+ * \param p_rtt Pointer to an RTT instance.
+ *
+ * \return The current Real-time Timer value.
+ */
+uint32_t rtt_read_timer_value(Rtt *p_rtt)
+{
+ return p_rtt->RTT_VR;
+}
+
+/**
+ * \brief Get the status register value of the given RTT.
+ *
+ * \param p_rtt Pointer to an RTT instance.
+ *
+ * \return The Real-time Timer status.
+ */
+uint32_t rtt_get_status(Rtt *p_rtt)
+{
+ return p_rtt->RTT_SR;
+}
+
+/**
+ * \brief Configure the RTT to generate an alarm at the given time.
+ *
+ * \param p_rtt Pointer to an RTT instance.
+ * \param ul_alarm_time Alarm time.
+ *
+ * \retval 0 Configuration is done.
+ * \retval 1 Parameter error.
+ */
+uint32_t rtt_write_alarm_time(Rtt *p_rtt, uint32_t ul_alarm_time)
+{
+ uint32_t flag;
+
+ if (ul_alarm_time == 0) {
+ return 1;
+ }
+
+ flag = p_rtt->RTT_MR & RTT_MR_ALMIEN;
+
+ rtt_disable_interrupt(RTT, RTT_MR_ALMIEN);
+
+ /* Alarm time = ALMV + 1 */
+ p_rtt->RTT_AR = ul_alarm_time - 1;
+
+ if (flag) {
+ rtt_enable_interrupt(RTT, RTT_MR_ALMIEN);
+ }
+
+ return 0;
+}
+
+//@}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/rtt/rtt.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,80 @@
+/**
+ * \file
+ *
+ * \brief Real-time Timer (RTT) driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef RTT_H_INCLUDED
+#define RTT_H_INCLUDED
+
+#include "compiler.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ uint32_t rtt_init(Rtt *p_rtt, uint16_t us_prescaler);
+#if (SAM4N || SAM4S || SAM4E || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ void rtt_sel_source(Rtt *p_rtt, bool is_rtc_sel);
+ void rtt_enable(Rtt *p_rtt);
+ void rtt_disable(Rtt *p_rtt);
+#endif
+ void rtt_enable_interrupt(Rtt *p_rtt, uint32_t ul_sources);
+ void rtt_disable_interrupt(Rtt *p_rtt, uint32_t ul_sources);
+ uint32_t rtt_read_timer_value(Rtt *p_rtt);
+ uint32_t rtt_get_status(Rtt *p_rtt);
+ uint32_t rtt_write_alarm_time(Rtt *p_rtt, uint32_t ul_alarm_time);
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* RTT_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/spi/spi_driver.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,453 @@
+/**
+ * \file
+ *
+ * \brief Serial Peripheral Interface (SPI) driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "spi_driver.h"
+#include "sysclk.h"
+#include "flexcom.h"
+
+/**
+ * \defgroup sam_drivers_spi_group Serial Peripheral Interface (SPI)
+ *
+ * See \ref sam_spi_quickstart.
+ *
+ * The SPI circuit is a synchronous serial data link that provides communication
+ * with external devices in Master or Slave mode. Connection to Peripheral DMA
+ * Controller channel capabilities optimizes data transfers.
+ *
+ * @{
+ */
+#ifndef SPI_WPMR_WPKEY_PASSWD
+#define SPI_WPMR_WPKEY_PASSWD SPI_WPMR_WPKEY((uint32_t) 0x535049)
+#endif
+
+/**
+ * \brief Enable SPI clock.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+void spi_enable_clock(Spi *p_spi)
+{
+#if (SAM4S || SAM3S || SAM3N || SAM3U || SAM4E || SAM4N || SAMG51|| SAMG53|| SAMG54)
+ UNUSED(p_spi);
+ sysclk_enable_peripheral_clock(ID_SPI);
+#elif (SAM3XA || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ if (p_spi == SPI0) {
+ sysclk_enable_peripheral_clock(ID_SPI0);
+ }
+#ifdef SPI1
+ else if (p_spi == SPI1) {
+ sysclk_enable_peripheral_clock(ID_SPI1);
+ }
+#endif
+#elif (SAMG55)
+ if (p_spi == SPI0) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM0);
+ }
+#ifdef SPI1
+ else if (p_spi == SPI1) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM1);
+ }
+#endif
+#ifdef SPI2
+ else if (p_spi == SPI2) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM2);
+ }
+#endif
+#ifdef SPI3
+ else if (p_spi == SPI3) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM3);
+ }
+#endif
+#ifdef SPI4
+ else if (p_spi == SPI4) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM4);
+ }
+#endif
+#ifdef SPI5
+ else if (p_spi == SPI5) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM5);
+ }
+#endif
+#ifdef SPI6
+ else if (p_spi == SPI6) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM6);
+ }
+#endif
+#ifdef SPI7
+ else if (p_spi == SPI7) {
+ sysclk_enable_peripheral_clock(ID_FLEXCOM7);
+ }
+#endif
+#elif SAM4L
+ sysclk_enable_peripheral_clock(p_spi);
+#endif
+}
+
+/**
+ * \brief Disable SPI clock.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+void spi_disable_clock(Spi *p_spi)
+{
+#if (SAM4S || SAM3S || SAM3N || SAM3U || SAM4E || SAM4N || SAMG51|| SAMG53|| SAMG54)
+ UNUSED(p_spi);
+ sysclk_disable_peripheral_clock(ID_SPI);
+#elif (SAM3XA || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ if (p_spi == SPI0) {
+ sysclk_disable_peripheral_clock(ID_SPI0);
+ }
+#ifdef SPI1
+ else if (p_spi == SPI1) {
+ sysclk_disable_peripheral_clock(ID_SPI1);
+ }
+#endif
+#elif (SAMG55)
+ if (p_spi == SPI0) {
+ sysclk_disable_peripheral_clock(ID_FLEXCOM0);
+ }
+#ifdef SPI1
+ else if (p_spi == SPI1) {
+ sysclk_disable_peripheral_clock(ID_FLEXCOM1);
+ }
+#endif
+#ifdef SPI2
+ else if (p_spi == SPI2) {
+ sysclk_disable_peripheral_clock(ID_FLEXCOM2);
+ }
+#endif
+#ifdef SPI3
+ else if (p_spi == SPI3) {
+ sysclk_disable_peripheral_clock(ID_FLEXCOM3);
+ }
+#endif
+#ifdef SPI4
+ else if (p_spi == SPI4) {
+ sysclk_disable_peripheral_clock(ID_FLEXCOM4);
+ }
+#endif
+#ifdef SPI5
+ else if (p_spi == SPI5) {
+ sysclk_disable_peripheral_clock(ID_FLEXCOM5);
+ }
+#endif
+#ifdef SPI6
+ else if (p_spi == SPI6) {
+ sysclk_disable_peripheral_clock(ID_FLEXCOM6);
+ }
+#endif
+#ifdef SPI7
+ else if (p_spi == SPI7) {
+ sysclk_disable_peripheral_clock(ID_FLEXCOM7);
+ }
+#endif
+#elif SAM4L
+ sysclk_disable_peripheral_clock(p_spi);
+#endif
+}
+
+/**
+ * \brief Set Peripheral Chip Select (PCS) value.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ * \param ul_value Peripheral Chip Select value.
+ * If PCS decode mode is not used, use \ref spi_get_pcs to build
+ * the value to use.
+ * On reset the decode mode is not enabled.
+ * The decode mode can be enabled/disabled by follow functions:
+ * \ref spi_enable_peripheral_select_decode,
+ * \ref spi_disable_peripheral_select_decode.
+ */
+void spi_set_peripheral_chip_select_value(Spi *p_spi, uint32_t ul_value)
+{
+ p_spi->SPI_MR &= (~SPI_MR_PCS_Msk);
+ p_spi->SPI_MR |= SPI_MR_PCS(ul_value);
+}
+
+/**
+ * \brief Set delay between chip selects (in number of MCK clocks).
+ * If DLYBCS <= 6, 6 MCK clocks will be inserted by default.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ * \param ul_delay Delay between chip selects (in number of MCK clocks).
+ */
+void spi_set_delay_between_chip_select(Spi *p_spi, uint32_t ul_delay)
+{
+ p_spi->SPI_MR &= (~SPI_MR_DLYBCS_Msk);
+ p_spi->SPI_MR |= SPI_MR_DLYBCS(ul_delay);
+}
+
+/**
+ * \brief Read the received data and it's peripheral chip select value.
+ * While SPI works in fixed peripheral select mode, the peripheral chip select
+ * value is meaningless.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ * \param data Pointer to the location where to store the received data word.
+ * \param p_pcs Pointer to fill Peripheral Chip Select Value.
+ *
+ * \retval SPI_OK on Success.
+ * \retval SPI_ERROR_TIMEOUT on Time-out.
+ */
+spi_status_t spi_read(Spi *p_spi, uint16_t *us_data, uint8_t *p_pcs)
+{
+ uint32_t timeout = SPI_TIMEOUT;
+ static uint32_t reg_value;
+
+ while (!(p_spi->SPI_SR & SPI_SR_RDRF)) {
+ if (!timeout--) {
+ return SPI_ERROR_TIMEOUT;
+ }
+ }
+
+ reg_value = p_spi->SPI_RDR;
+ if (spi_get_peripheral_select_mode(p_spi)) {
+ *p_pcs = (uint8_t) ((reg_value & SPI_RDR_PCS_Msk) >> SPI_RDR_PCS_Pos);
+ }
+ *us_data = (uint16_t) (reg_value & SPI_RDR_RD_Msk);
+
+ return SPI_OK;
+}
+
+/**
+ * \brief Write the transmitted data with specified peripheral chip select value.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ * \param us_data The data to transmit.
+ * \param uc_pcs Peripheral Chip Select Value while SPI works in peripheral select
+ * mode, otherwise it's meaningless.
+ * \param uc_last Indicate whether this data is the last one while SPI is working
+ * in variable peripheral select mode.
+ *
+ * \retval SPI_OK on Success.
+ * \retval SPI_ERROR_TIMEOUT on Time-out.
+ */
+spi_status_t spi_write(Spi *p_spi, uint16_t us_data,
+ uint8_t uc_pcs, uint8_t uc_last)
+{
+ uint32_t timeout = SPI_TIMEOUT;
+ uint32_t value;
+
+ while (!(p_spi->SPI_SR & SPI_SR_TDRE)) {
+ if (!timeout--) {
+ return SPI_ERROR_TIMEOUT;
+ }
+ }
+
+ if (spi_get_peripheral_select_mode(p_spi)) {
+ value = SPI_TDR_TD(us_data) | SPI_TDR_PCS(uc_pcs);
+ if (uc_last) {
+ value |= SPI_TDR_LASTXFER;
+ }
+ } else {
+ value = SPI_TDR_TD(us_data);
+ }
+
+ p_spi->SPI_TDR = value;
+
+ return SPI_OK;
+}
+
+/**
+ * \brief Set clock default state.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ * \param ul_pcs_ch Peripheral Chip Select channel (0~3).
+ * \param ul_polarity Default clock state is logical one(high)/zero(low).
+ */
+void spi_set_clock_polarity(Spi *p_spi, uint32_t ul_pcs_ch,
+ uint32_t ul_polarity)
+{
+ if (ul_polarity) {
+ p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_CPOL;
+ } else {
+ p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CPOL);
+ }
+}
+
+/**
+ * \brief Set Data Capture Phase.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ * \param ul_pcs_ch Peripheral Chip Select channel (0~3).
+ * \param ul_phase Data capture on the rising/falling edge of clock.
+ */
+void spi_set_clock_phase(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_phase)
+{
+ if (ul_phase) {
+ p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_NCPHA;
+ } else {
+ p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_NCPHA);
+ }
+}
+
+/**
+ * \brief Configure CS behavior for SPI transfer (\ref spi_cs_behavior_t).
+ *
+ * \param p_spi Pointer to an SPI instance.
+ * \param ul_pcs_ch Peripheral Chip Select channel (0~3).
+ * \param ul_cs_behavior Behavior of the Chip Select after transfer.
+ */
+void spi_configure_cs_behavior(Spi *p_spi, uint32_t ul_pcs_ch,
+ uint32_t ul_cs_behavior)
+{
+ if (ul_cs_behavior == SPI_CS_RISE_FORCED) {
+ p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CSAAT);
+ p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_CSNAAT;
+ } else if (ul_cs_behavior == SPI_CS_RISE_NO_TX) {
+ p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CSAAT);
+ p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_CSNAAT);
+ } else if (ul_cs_behavior == SPI_CS_KEEP_LOW) {
+ p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_CSAAT;
+ }
+}
+
+/**
+ * \brief Set number of bits per transfer.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ * \param ul_pcs_ch Peripheral Chip Select channel (0~3).
+ * \param ul_bits Number of bits (8~16), use the pattern defined
+ * in the device header file.
+ */
+void spi_set_bits_per_transfer(Spi *p_spi, uint32_t ul_pcs_ch,
+ uint32_t ul_bits)
+{
+ p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_BITS_Msk);
+ p_spi->SPI_CSR[ul_pcs_ch] |= ul_bits;
+}
+
+/**
+ * \brief Calculate the baudrate divider.
+ *
+ * \param baudrate Baudrate value.
+ * \param mck SPI module input clock frequency (MCK clock, Hz).
+ *
+ * \return Divider or error code.
+ * \retval > 0 Success.
+ * \retval < 0 Error.
+ */
+int16_t spi_calc_baudrate_div(const uint32_t baudrate, uint32_t mck)
+{
+ int baud_div = div_ceil(mck, baudrate);
+
+ /* The value of baud_div is from 1 to 255 in the SCBR field. */
+ if (baud_div <= 0 || baud_div > 255) {
+ return -1;
+ }
+
+ return baud_div;
+}
+
+/**
+ * \brief Set Serial Clock Baud Rate divider value (SCBR).
+ *
+ * \param p_spi Pointer to an SPI instance.
+ * \param ul_pcs_ch Peripheral Chip Select channel (0~3).
+ * \param uc_baudrate_divider Baudrate divider from MCK.
+ */
+void spi_set_baudrate_div(Spi *p_spi, uint32_t ul_pcs_ch,
+ uint8_t uc_baudrate_divider)
+{
+ p_spi->SPI_CSR[ul_pcs_ch] &= (~SPI_CSR_SCBR_Msk);
+ p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_SCBR(uc_baudrate_divider);
+}
+
+/**
+ * \brief Configure timing for SPI transfer.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ * \param ul_pcs_ch Peripheral Chip Select channel (0~3).
+ * \param uc_dlybs Delay before SPCK (in number of MCK clocks).
+ * \param uc_dlybct Delay between consecutive transfers (in number of MCK clocks).
+ */
+void spi_set_transfer_delay(Spi *p_spi, uint32_t ul_pcs_ch,
+ uint8_t uc_dlybs, uint8_t uc_dlybct)
+{
+ p_spi->SPI_CSR[ul_pcs_ch] &= ~(SPI_CSR_DLYBS_Msk | SPI_CSR_DLYBCT_Msk);
+ p_spi->SPI_CSR[ul_pcs_ch] |= SPI_CSR_DLYBS(uc_dlybs)
+ | SPI_CSR_DLYBCT(uc_dlybct);
+}
+
+
+/**
+ * \brief Enable or disable write protection of SPI registers.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ * \param ul_enable 1 to enable, 0 to disable.
+ */
+void spi_set_writeprotect(Spi *p_spi, uint32_t ul_enable)
+{
+#if SAM4L
+ if (ul_enable) {
+ p_spi->SPI_WPCR = SPI_WPCR_SPIWPKEY_VALUE | SPI_WPCR_SPIWPEN;
+ } else {
+ p_spi->SPI_WPCR = SPI_WPCR_SPIWPKEY_VALUE;
+ }
+#else
+ if (ul_enable) {
+ p_spi->SPI_WPMR = SPI_WPMR_WPKEY_PASSWD | SPI_WPMR_WPEN;
+ } else {
+ p_spi->SPI_WPMR = SPI_WPMR_WPKEY_PASSWD;
+ }
+#endif
+}
+
+/**
+ * \brief Indicate write protect status.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \return SPI_WPSR value.
+ */
+uint32_t spi_get_writeprotect_status(Spi *p_spi)
+{
+ return p_spi->SPI_WPSR;
+}
+
+/**
+ * @}
+ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/spi/spi_driver.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,627 @@
+/**
+ * \file
+ *
+ * \brief Serial Peripheral Interface (SPI) driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SPI_H_INCLUDED
+#define SPI_H_INCLUDED
+
+#include "compiler.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /** Time-out value (number of attempts). */
+#define SPI_TIMEOUT 15000
+
+ /** Status codes used by the SPI driver. */
+typedef enum {
+ SPI_ERROR = -1,
+ SPI_OK = 0,
+ SPI_ERROR_TIMEOUT = 1,
+ SPI_ERROR_ARGUMENT,
+ SPI_ERROR_OVERRUN,
+ SPI_ERROR_MODE_FAULT,
+ SPI_ERROR_OVERRUN_AND_MODE_FAULT
+} spi_status_t;
+
+/** SPI Chip Select behavior modes while transferring. */
+typedef enum spi_cs_behavior {
+ /** CS does not rise until a new transfer is requested on different chip select. */
+ SPI_CS_KEEP_LOW = SPI_CSR_CSAAT,
+ /** CS rises if there is no more data to transfer. */
+ SPI_CS_RISE_NO_TX = 0,
+ /** CS is de-asserted systematically during a time DLYBCS. */
+ SPI_CS_RISE_FORCED = SPI_CSR_CSNAAT
+} spi_cs_behavior_t;
+
+/**
+ * \brief Generate Peripheral Chip Select Value from Chip Select ID
+ * \note When chip select n is working, PCS bit n is set to low level.
+ *
+ * \param chip_sel_id The chip select number used
+ */
+#define spi_get_pcs(chip_sel_id) ((~(1u<<(chip_sel_id)))&0xF)
+
+/**
+ * \brief Reset SPI and set it to Slave mode.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_reset(Spi *p_spi)
+{
+ p_spi->SPI_CR = SPI_CR_SWRST;
+}
+
+/**
+ * \brief Enable SPI.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_enable(Spi *p_spi)
+{
+ p_spi->SPI_CR = SPI_CR_SPIEN;
+}
+
+/**
+ * \brief Disable SPI.
+ *
+ * \note CS is de-asserted, which indicates that the last data is done, and user
+ * should check TX_EMPTY before disabling SPI.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_disable(Spi *p_spi)
+{
+ p_spi->SPI_CR = SPI_CR_SPIDIS;
+}
+
+/**
+ * \brief Issue a LASTXFER command.
+ * The next transfer is the last transfer and after that CS is de-asserted.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_set_lastxfer(Spi *p_spi)
+{
+ p_spi->SPI_CR = SPI_CR_LASTXFER;
+}
+
+/**
+ * \brief Set SPI to Master mode.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_set_master_mode(Spi *p_spi)
+{
+ p_spi->SPI_MR |= SPI_MR_MSTR;
+}
+
+/**
+ * \brief Set SPI to Slave mode.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_set_slave_mode(Spi *p_spi)
+{
+ p_spi->SPI_MR &= (~SPI_MR_MSTR);
+}
+
+/**
+ * \brief Get SPI work mode.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \return 1 for master mode, 0 for slave mode.
+ */
+static inline uint32_t spi_get_mode(Spi *p_spi)
+{
+ if (p_spi->SPI_MR & SPI_MR_MSTR) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Set Variable Peripheral Select.
+ * Peripheral Chip Select can be controlled by SPI_TDR.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_set_variable_peripheral_select(Spi *p_spi)
+{
+ p_spi->SPI_MR |= SPI_MR_PS;
+}
+
+/**
+ * \brief Set Fixed Peripheral Select.
+ * Peripheral Chip Select is controlled by SPI_MR.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_set_fixed_peripheral_select(Spi *p_spi)
+{
+ p_spi->SPI_MR &= (~SPI_MR_PS);
+}
+
+/**
+ * \brief Get Peripheral Select mode.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \return 1 for Variable mode, 0 for fixed mode.
+ */
+static inline uint32_t spi_get_peripheral_select_mode(Spi *p_spi)
+{
+ if (p_spi->SPI_MR & SPI_MR_PS) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Enable Peripheral Select Decode.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_enable_peripheral_select_decode(Spi *p_spi)
+{
+ p_spi->SPI_MR |= SPI_MR_PCSDEC;
+}
+
+/**
+ * \brief Disable Peripheral Select Decode.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_disable_peripheral_select_decode(Spi *p_spi)
+{
+ p_spi->SPI_MR &= (~SPI_MR_PCSDEC);
+}
+
+/**
+ * \brief Get Peripheral Select Decode mode.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \return 1 for decode mode, 0 for direct mode.
+ */
+static inline uint32_t spi_get_peripheral_select_decode_setting(Spi *p_spi)
+{
+ if (p_spi->SPI_MR & SPI_MR_PCSDEC) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Enable Mode Fault Detection.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_enable_mode_fault_detect(Spi *p_spi)
+{
+ p_spi->SPI_MR &= (~SPI_MR_MODFDIS);
+}
+
+/**
+ * \brief Disable Mode Fault Detection.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_disable_mode_fault_detect(Spi *p_spi)
+{
+ p_spi->SPI_MR |= SPI_MR_MODFDIS;
+}
+
+/**
+ * \brief Check if mode fault detection is enabled.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \return 1 for disabled, 0 for enabled.
+ */
+static inline uint32_t spi_get_mode_fault_detect_setting(Spi *p_spi)
+{
+ if (p_spi->SPI_MR & SPI_MR_MODFDIS) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Enable waiting RX_EMPTY before transfer starts.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_enable_tx_on_rx_empty(Spi *p_spi)
+{
+ p_spi->SPI_MR |= SPI_MR_WDRBT;
+}
+
+/**
+ * \brief Disable waiting RX_EMPTY before transfer starts.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_disable_tx_on_rx_empty(Spi *p_spi)
+{
+ p_spi->SPI_MR &= (~SPI_MR_WDRBT);
+}
+
+/**
+ * \brief Check if SPI waits RX_EMPTY before transfer starts.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \return 1 for SPI waits, 0 for no wait.
+ */
+static inline uint32_t spi_get_tx_on_rx_empty_setting(Spi *p_spi)
+{
+ if (p_spi->SPI_MR & SPI_MR_WDRBT) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Enable loopback mode.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_enable_loopback(Spi *p_spi)
+{
+ p_spi->SPI_MR |= SPI_MR_LLB;
+}
+
+/**
+ * \brief Disable loopback mode.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ */
+static inline void spi_disable_loopback(Spi *p_spi)
+{
+ p_spi->SPI_MR &= (~SPI_MR_LLB);
+}
+
+void spi_enable_clock(Spi *p_spi);
+void spi_disable_clock(Spi *p_spi);
+void spi_set_peripheral_chip_select_value(Spi *p_spi, uint32_t ul_value);
+void spi_set_delay_between_chip_select(Spi *p_spi, uint32_t ul_delay);
+spi_status_t spi_read(Spi *p_spi, uint16_t *us_data, uint8_t *p_pcs);
+spi_status_t spi_write(Spi *p_spi, uint16_t us_data, uint8_t uc_pcs,
+ uint8_t uc_last);
+
+/**
+ * \brief Read status register.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \return SPI status register value.
+ */
+static inline uint32_t spi_read_status(Spi *p_spi)
+{
+ return p_spi->SPI_SR;
+}
+
+/**
+ * \brief Test if the SPI is enabled.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \return 1 if the SPI is enabled, otherwise 0.
+ */
+static inline uint32_t spi_is_enabled(Spi *p_spi)
+{
+ if (p_spi->SPI_SR & SPI_SR_SPIENS) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Put one data to a SPI peripheral.
+ *
+ * \param p_spi Base address of the SPI instance.
+ * \param data The data byte to be loaded
+ *
+ */
+static inline void spi_put(Spi *p_spi, uint16_t data)
+{
+ p_spi->SPI_TDR = SPI_TDR_TD(data);
+}
+
+/** \brief Get one data to a SPI peripheral.
+ *
+ * \param p_spi Base address of the SPI instance.
+ * \return The data byte
+ *
+ */
+static inline uint16_t spi_get(Spi *p_spi)
+{
+ return (p_spi->SPI_RDR & SPI_RDR_RD_Msk);
+}
+
+/**
+ * \brief Check if all transmissions are complete.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \retval 1 if transmissions are complete.
+ * \retval 0 if transmissions are not complete.
+ */
+static inline uint32_t spi_is_tx_empty(Spi *p_spi)
+{
+ if (p_spi->SPI_SR & SPI_SR_TXEMPTY) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Check if all transmissions are ready.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \retval 1 if transmissions are complete.
+ * \retval 0 if transmissions are not complete.
+ */
+static inline uint32_t spi_is_tx_ready(Spi *p_spi)
+{
+ if (p_spi->SPI_SR & SPI_SR_TDRE) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Check if the SPI contains a received character.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \return 1 if the SPI Receive Holding Register is full, otherwise 0.
+ */
+static inline uint32_t spi_is_rx_full(Spi *p_spi)
+{
+ if (p_spi->SPI_SR & SPI_SR_RDRF) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Check if all receptions are ready.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \return 1 if the SPI Receiver is ready, otherwise 0.
+ */
+static inline uint32_t spi_is_rx_ready(Spi *p_spi)
+{
+ if ((p_spi->SPI_SR & (SPI_SR_RDRF | SPI_SR_TXEMPTY))
+ == (SPI_SR_RDRF | SPI_SR_TXEMPTY)) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Enable SPI interrupts.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ * \param ul_sources Interrupts to be enabled.
+ */
+static inline void spi_enable_interrupt(Spi *p_spi, uint32_t ul_sources)
+{
+ p_spi->SPI_IER = ul_sources;
+}
+
+/**
+ * \brief Disable SPI interrupts.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ * \param ul_sources Interrupts to be disabled.
+ */
+static inline void spi_disable_interrupt(Spi *p_spi, uint32_t ul_sources)
+{
+ p_spi->SPI_IDR = ul_sources;
+}
+
+/**
+ * \brief Read SPI interrupt mask.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \return The interrupt mask value.
+ */
+static inline uint32_t spi_read_interrupt_mask(Spi *p_spi)
+{
+ return p_spi->SPI_IMR;
+}
+
+void spi_set_clock_polarity(Spi *p_spi, uint32_t ul_pcs_ch,
+ uint32_t ul_polarity);
+void spi_set_clock_phase(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_phase);
+void spi_configure_cs_behavior(Spi *p_spi, uint32_t ul_pcs_ch,
+ uint32_t ul_cs_behavior);
+void spi_set_bits_per_transfer(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_bits);
+int16_t spi_calc_baudrate_div(const uint32_t baudrate, uint32_t mck);
+void spi_set_baudrate_div(Spi *p_spi, uint32_t ul_pcs_ch,
+ uint8_t uc_baudrate_divider);
+void spi_set_transfer_delay(Spi *p_spi, uint32_t ul_pcs_ch, uint8_t uc_dlybs,
+ uint8_t uc_dlybct);
+
+#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM)
+/**
+ * \brief Get PDC registers base address.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \return PDC registers base for PDC driver to access.
+ */
+static inline Pdc *spi_get_pdc_base(Spi *p_spi)
+{
+ return (Pdc *)&(p_spi->SPI_RPR);
+}
+#endif
+
+#if (SAM3U || SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Get transmit data register address for DMA operation.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \return Transmit address for DMA access.
+ */
+static inline void *spi_get_tx_access(Spi *p_spi)
+{
+ return (void *)&(p_spi->SPI_TDR);
+}
+
+/**
+ * \brief Get receive data register address for DMA operation.
+ *
+ * \param p_spi Pointer to an SPI instance.
+ *
+ * \return Receive address for DMA access.
+ */
+static inline void *spi_get_rx_access(Spi *p_spi)
+{
+ return (void *)&(p_spi->SPI_RDR);
+}
+#endif
+
+void spi_set_writeprotect(Spi *p_spi, uint32_t ul_enable);
+uint32_t spi_get_writeprotect_status(Spi *p_spi);
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/**
+ * \page sam_spi_quickstart Quickstart guide for SAM SPI driver
+ *
+ * This is the quickstart guide for the \ref spi_group "SAM SPI driver",
+ * with step-by-step instructions on how to configure and use the driver in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g.the main application function.
+ *
+ * \section spi_basic_use_case Basic use case
+ * In this basic use case, the SPI module are configured for:
+ * - Master mode
+ * - Interrupt-based handling
+ *
+ * \subsection sam_spi_quickstart_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (Sysclock)"
+ *
+ * \section spi_basic_use_case_setup Setup steps
+ * \subsection spi_basic_use_case_setup_code Example code
+ * Add to application C-file:
+ * \code
+ void spi_master_init(Spi *p_spi)
+ {
+ spi_enable_clock(p_spi);
+ spi_reset(p_spi);
+ spi_set_master_mode(p_spi);
+ spi_disable_mode_fault_detect(p_spi);
+ spi_disable_loopback(p_spi);
+ spi_set_peripheral_chip_select_value(p_spi,
+ spi_get_pcs(DEFAULT_CHIP_ID));
+ spi_set_fixed_peripheral_select(p_spi);
+ spi_disable_peripheral_select_decode(p_spi);
+ spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS);
+ }
+ void spi_master_setup_device(Spi *p_spi, struct spi_device *device,
+ spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id)
+ {
+ spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS,
+ CONFIG_SPI_MASTER_DELAY_BCT);
+
+ spi_set_bits_per_transfer(p_spi, device->id, CONFIG_SPI_MASTER_BITS_PER_TRANSFER);
+ spi_set_baudrate_div(p_spi, device->id,
+ spi_calc_baudrate_div(baud_rate, sysclk_get_cpu_hz()));
+
+ spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW);
+
+ spi_set_clock_polarity(p_spi, device->id, flags >> 1);
+ spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1));
+ }
+\endcode
+ *
+ * \subsection spi_basic_use_case_setup_flow Workflow
+ * -# Initialize the SPI in master mode:
+ * - \code
+ void spi_master_init(SPI_EXAMPLE);
+\endcode
+ * -# Set up an SPI device:
+ * - \code void spi_master_setup_device(SPI_EXAMPLE, &SPI_DEVICE_EXAMPLE,
+ SPI_MODE_0, SPI_EXAMPLE_BAUDRATE, 0); \endcode
+ * - \note The returned device descriptor structure must be passed to the driver
+ * whenever that device should be used as current slave device.
+ * -# Enable SPI module:
+ * - \code spi_enable(SPI_EXAMPLE); \endcode
+ */
+#endif /* SPI_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/supc/supc.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,424 @@
+/**
+ * \file
+ *
+ * \brief Supply Controller (SUPC) driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "supc.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /**
+ * \defgroup sam_drivers_supc_group Supply Controller (SUPC)
+ *
+ * Driver for the SUPC (Supply Controller). This driver provides access to the main
+ * features of the Supply Controller.
+ *
+ * @{
+ */
+
+#if (!SAMG)
+ /**
+ * \brief Switch off the voltage regulator to put the device in backup mode.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ */
+ void supc_enable_backup_mode(Supc *p_supc)
+{
+ p_supc->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF;
+ __WFE();
+ __WFI();
+}
+
+/**
+ * \brief Enable the internal voltage regulator.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ */
+void supc_enable_voltage_regulator(Supc *p_supc)
+{
+#if (SAM3U || SAM3XA)
+ uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_VDDIORDYONREG));
+ p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr | SUPC_MR_VDDIORDYONREG;
+#else
+ uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_ONREG));
+ p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr | SUPC_MR_ONREG;
+#endif
+}
+
+/**
+ * \brief Disable the internal voltage regulator to supply VDDCORE with an external supply.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ */
+void supc_disable_voltage_regulator(Supc *p_supc)
+{
+#if (SAM3U || SAM3XA)
+ uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_VDDIORDYONREG));
+#else
+ uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_ONREG));
+#endif
+ p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr;
+}
+#endif
+
+/**
+ * \brief Switch slow clock source selection to external 32k (Xtal or Bypass) oscillator.
+ * This function disables the PLLs.
+ *
+ * \note Switching sclk back to 32krc is only possible by shutting down the VDDIO power supply.
+ *
+ * \param ul_bypass 0 for Xtal, 1 for bypass.
+ */
+void supc_switch_sclk_to_32kxtal(Supc *p_supc, uint32_t ul_bypass)
+{
+ /* Set Bypass mode if required */
+ if (ul_bypass == 1) {
+ p_supc->SUPC_MR |= SUPC_MR_KEY_PASSWD | SUPC_MR_OSCBYPASS;
+ } else {
+ p_supc->SUPC_MR &= ~(SUPC_MR_KEY_PASSWD | SUPC_MR_OSCBYPASS);
+ }
+
+ p_supc->SUPC_CR |= SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL;
+}
+
+/**
+ * \brief Enable the core brownout detector.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ */
+void supc_enable_brownout_detector(Supc *p_supc)
+{
+ uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_BODDIS));
+ p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr;
+}
+
+/**
+ * \brief Disable the core brownout detector.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ */
+void supc_disable_brownout_detector(Supc *p_supc)
+{
+ uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_BODDIS));
+ p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr | SUPC_MR_BODDIS;
+}
+
+/**
+ * \brief Enable the assertion of core reset signal when a brownout detection occurs.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ */
+void supc_enable_brownout_reset(Supc *p_supc)
+{
+ uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_BODRSTEN));
+ p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr | SUPC_MR_BODRSTEN;
+}
+
+/**
+ * \brief Disable the assertion of core reset signal when a brownout detection occurs.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ */
+void supc_disable_brownout_reset(Supc *p_supc)
+{
+ uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_BODRSTEN));
+ p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr;
+}
+
+/**
+ * \brief Set Supply monitor threshold.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ * \param ul_threshold Supply monitor threshold (between 1.9V and 3.4V).
+ */
+void supc_set_monitor_threshold(Supc *p_supc, uint32_t ul_threshold)
+{
+ uint32_t ul_smmr = p_supc->SUPC_SMMR & (~SUPC_SMMR_SMTH_Msk);
+ p_supc->SUPC_SMMR = ul_smmr | (SUPC_SMMR_SMTH_Msk & ul_threshold);
+}
+
+/**
+ * \brief Set Supply monitor sampling period.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ * \param ul_period Supply monitor sampling period.
+ */
+void supc_set_monitor_sampling_period(Supc *p_supc, uint32_t ul_period)
+{
+ uint32_t ul_smmr = p_supc->SUPC_SMMR & (~SUPC_SMMR_SMSMPL_Msk);
+ p_supc->SUPC_SMMR = ul_smmr | (SUPC_SMMR_SMSMPL_Msk & ul_period);
+}
+
+/**
+ * \brief Enable the assertion of the core reset signal when a supply monitor detection occurs.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ */
+void supc_enable_monitor_reset(Supc *p_supc)
+{
+ p_supc->SUPC_SMMR |= SUPC_SMMR_SMRSTEN;
+}
+
+/**
+ * \brief Disable the assertion of core reset signal when a supply monitor detection occurs.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ */
+void supc_disable_monitor_reset(Supc *p_supc)
+{
+ p_supc->SUPC_SMMR &= ~SUPC_SMMR_SMRSTEN;
+}
+
+/**
+ * \brief Enable the assertion of SUPC interrupt signal when a supply monitor detection occurs.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ */
+void supc_enable_monitor_interrupt(Supc *p_supc)
+{
+ p_supc->SUPC_SMMR |= SUPC_SMMR_SMIEN;
+}
+
+/**
+ * \brief Disable the assertion of SUPC interrupt signal when a supply monitor detection occurs.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ */
+void supc_disable_monitor_interrupt(Supc *p_supc)
+{
+ p_supc->SUPC_SMMR &= ~SUPC_SMMR_SMIEN;
+}
+
+#if (!(SAMG51 || SAMG53 || SAMG54))
+/**
+ * \brief Set system controller wake up mode.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ * \param ul_mode Bitmask of wake up mode (please refer to datasheet for more details).
+ */
+void supc_set_wakeup_mode(Supc *p_supc, uint32_t ul_mode)
+{
+ p_supc->SUPC_WUMR = ul_mode;
+}
+
+/**
+ * \brief Set system controller wake up inputs.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ * \param ul_inputs Bitmask of wake-up inputs that can force wake up of
+ * the core power supply.
+ * \param ul_transition Bitmask of level transition of the wake-up inputs.
+ * 1 means a high-to-low level transition forces the wake up of core power supply.
+ * 0 means a low-to-high level transition forces the wake up of core power supply.
+ */
+void supc_set_wakeup_inputs(Supc *p_supc, uint32_t ul_inputs,
+ uint32_t ul_transition)
+{
+ p_supc->SUPC_WUIR = ul_inputs | ul_transition;
+}
+#endif
+
+/**
+ * \brief Get supply controller status.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ *
+ * \return The status of supply controller.
+ */
+uint32_t supc_get_status(Supc *p_supc)
+{
+ return p_supc->SUPC_SR;
+}
+
+#if (SAM4C || SAM4CP || SAM4CM)
+/**
+ * \brief Enable Backup Area Power-On Reset.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ */
+void supc_enable_backup_power_on_reset(Supc *p_supc)
+{
+ uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_BUPPOREN));
+ p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr | SUPC_MR_BUPPOREN;
+}
+
+/**
+ * \brief Disable Backup Area Power-On Reset.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ */
+void supc_disable_backup_power_on_reset(Supc *p_supc)
+{
+ uint32_t ul_mr = p_supc->SUPC_MR & (~(SUPC_MR_KEY_Msk | SUPC_MR_BUPPOREN));
+ p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr;
+}
+/**
+ * \brief Get SLCD power mode.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ *
+ * \return The mode of SLCDC.
+ */
+enum slcdc_power_mode supc_get_slcd_power_mode(Supc *p_supc)
+{
+ return (enum slcdc_power_mode)(p_supc->SUPC_MR & SUPC_MR_LCDMODE_Msk);
+}
+
+/**
+ * \brief Set SLCD power mode.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ * \param mode The mode of SLCDC.
+ */
+void supc_set_slcd_power_mode(Supc *p_supc, enum slcdc_power_mode mode)
+{
+ enum slcdc_power_mode pre_mode;
+ uint32_t tmp;
+
+ pre_mode = supc_get_slcd_power_mode(p_supc);
+
+ if ((pre_mode == SLCDC_POWER_MODE_LCDON_EXTVR) &&
+ (mode == SLCDC_POWER_MODE_LCDON_INVR)) {
+ return;
+ } else if ((pre_mode == SLCDC_POWER_MODE_LCDON_INVR) &&
+ (mode == SLCDC_POWER_MODE_LCDON_EXTVR)) {
+ return;
+ }
+ tmp = p_supc->SUPC_MR;
+ tmp &= ~SUPC_MR_LCDMODE_Msk;
+ tmp |= SUPC_MR_KEY_PASSWD | mode;
+ p_supc->SUPC_MR = tmp;
+
+ if (mode == SLCDC_POWER_MODE_LCDOFF) {
+ while(supc_get_status(p_supc) & SUPC_SR_LCDS_ENABLED);
+ } else {
+ while(!(supc_get_status(p_supc) & SUPC_SR_LCDS_ENABLED));
+ }
+}
+
+/**
+ * \brief Set LCD Voltage Regulator Output.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ * \param vol The voltage of Regulator Output.
+ */
+void supc_set_slcd_vol(Supc *p_supc, uint32_t vol)
+{
+ uint32_t tmp= p_supc->SUPC_MR;
+ tmp &= ~SUPC_MR_LCDVROUT_Msk;
+ tmp |= SUPC_MR_KEY_PASSWD | SUPC_MR_LCDVROUT(vol);
+ p_supc->SUPC_MR = tmp;
+
+}
+#endif
+
+#if SAMG54
+/**
+ * \brief Set the internal voltage regulator to use factory trim value.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ */
+void supc_set_regulator_trim_factory(Supc *p_supc)
+{
+ uint32_t ul_mr = p_supc->SUPC_MR &
+ (~(SUPC_MR_VRVDD_Msk | SUPC_MR_VDDSEL_USER_VRVDD));
+ p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr;
+}
+
+/**
+ * \brief Set the internal voltage regulator trim value.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ * \param value the trim value.
+ *
+ * \note For the trim value in 96M PLL, please read the value in flash unique identifier area.
+ */
+void supc_set_regulator_trim_user(Supc *p_supc, uint32_t value)
+{
+ uint32_t ul_mr = p_supc->SUPC_MR & (~SUPC_MR_VRVDD_Msk);
+ p_supc->SUPC_MR = SUPC_MR_KEY_PASSWD | ul_mr | SUPC_MR_VDDSEL_USER_VRVDD
+ | SUPC_MR_VRVDD(value);
+}
+
+#endif
+
+#if (SAMV70 || SAMV71 || SAME70 || SAMS70)
+/**
+ * \brief SRAM On In Backup Mode.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ *
+ */
+void supc_backup_sram_on(Supc *p_supc)
+{
+ p_supc->SUPC_MR |= (SUPC_MR_KEY_PASSWD | SUPC_MR_BKUPRETON);
+}
+
+/**
+ * \brief SRAM Off In Backup Mode.
+ *
+ * \param p_supc Pointer to a SUPC instance.
+ *
+ */
+void supc_backup_sram_off(Supc *p_supc)
+{
+ p_supc->SUPC_MR &= (~(SUPC_MR_KEY_PASSWD | SUPC_MR_BKUPRETON));
+}
+#endif
+
+//@}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/supc/supc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,127 @@
+/**
+ * \file
+ *
+ * \brief Supply Controller (SUPC) driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SUPC_H_INCLUDED
+#define SUPC_H_INCLUDED
+
+#include "compiler.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /** Key used to write SUPC registers */
+#ifndef SUPC_CR_KEY_PASSWD
+#define SUPC_CR_KEY_PASSWD SUPC_CR_KEY(0xA5U)
+#endif
+
+#ifndef SUPC_MR_KEY_PASSWD
+#define SUPC_MR_KEY_PASSWD SUPC_MR_KEY(0xA5U)
+#endif
+
+#if (SAM4C || SAM4CP || SAM4CM)
+ /** Power Mode */
+enum slcdc_power_mode {
+ /** The internal supply source and the external supply source are both deselected. */
+ SLCDC_POWER_MODE_LCDOFF = SUPC_MR_LCDMODE_LCDOFF,
+ /** The external supply source for LCD is selected */
+ SLCDC_POWER_MODE_LCDON_EXTVR = SUPC_MR_LCDMODE_LCDON_EXTVR,
+ /** The internal supply source for LCD is selected */
+ SLCDC_POWER_MODE_LCDON_INVR = SUPC_MR_LCDMODE_LCDON_INVR,
+};
+#endif
+
+#if (!SAMG)
+void supc_enable_backup_mode(Supc *p_supc);
+void supc_enable_voltage_regulator(Supc *p_supc);
+void supc_disable_voltage_regulator(Supc *p_supc);
+#endif
+void supc_switch_sclk_to_32kxtal(Supc *p_supc, uint32_t ul_bypass);
+void supc_enable_brownout_detector(Supc *p_supc);
+void supc_disable_brownout_detector(Supc *p_supc);
+void supc_enable_brownout_reset(Supc *p_supc);
+void supc_disable_brownout_reset(Supc *p_supc);
+void supc_set_monitor_threshold(Supc *p_supc, uint32_t ul_threshold);
+void supc_set_monitor_sampling_period(Supc *p_supc, uint32_t ul_period);
+void supc_enable_monitor_reset(Supc *p_supc);
+void supc_disable_monitor_reset(Supc *p_supc);
+void supc_enable_monitor_interrupt(Supc *p_supc);
+void supc_disable_monitor_interrupt(Supc *p_supc);
+#if (!(SAMG51 || SAMG53 || SAMG54))
+void supc_set_wakeup_mode(Supc *p_supc, uint32_t ul_mode);
+void supc_set_wakeup_inputs(Supc *p_supc, uint32_t ul_inputs,
+ uint32_t ul_transition);
+#endif
+uint32_t supc_get_status(Supc *p_supc);
+#if (SAM4C || SAM4CP || SAM4CM)
+void supc_enable_backup_power_on_reset(Supc *p_supc);
+void supc_disable_backup_power_on_reset(Supc *p_supc);
+enum slcdc_power_mode supc_get_slcd_power_mode(Supc *p_supc);
+void supc_set_slcd_power_mode(Supc *p_supc, enum slcdc_power_mode mode);
+void supc_set_slcd_vol(Supc *p_supc, uint32_t vol);
+#endif
+#if SAMG54
+void supc_set_regulator_trim_factory(Supc *p_supc);
+void supc_set_regulator_trim_user(Supc *p_supc, uint32_t value);
+#endif
+#if (SAMV70 || SAMV71 || SAME70 || SAMS70)
+void supc_backup_sram_on(Supc *p_supc);
+void supc_backup_sram_off(Supc *p_supc);
+#endif
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* SUPC_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/tc/tc.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,777 @@
+/**
+ * \file
+ *
+ * \brief SAM Timer Counter (TC) driver.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <assert.h>
+#include "tc.h"
+
+/// @cond
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#ifndef TC_WPMR_WPKEY_PASSWD
+#define TC_WPMR_WPKEY_PASSWD TC_WPMR_WPKEY((uint32_t)0x54494D)
+#endif
+
+ /**
+ * \brief Configure TC for timer, waveform generation, or capture.
+ *
+ * \param[in,out] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel to configure
+ * \param[in] ul_mode Control mode register bitmask value to set
+ *
+ * \note For more information regarding <i>ul_mode</i> configuration refer to
+ * the section entitled "Channel Mode Register: Capture Mode" and/or section
+ * "Waveform Operating Mode" in the device-specific datasheet.
+ *
+ * \note If the TC is configured for waveform generation then the external event
+ * selection (EEVT) should only be set to TC_CMR_EEVT_TIOB, or the
+ * equivalent value of 0, if it really is the intention to use TIOB as an
+ * external event trigger. This is because this setting forces TIOB to be
+ * an input, even if the external event trigger has not been enabled with
+ * TC_CMR_ENETRG, and thus prevents normal operation of TIOB.
+ */
+ void tc_init(
+ Tc *p_tc,
+ uint32_t ul_channel,
+ uint32_t ul_mode)
+{
+ TcChannel *tc_channel;
+
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+ tc_channel = p_tc->TC_CHANNEL + ul_channel;
+
+ /* Disable TC clock. */
+ tc_channel->TC_CCR = TC_CCR_CLKDIS;
+
+ /* Disable interrupts. */
+ tc_channel->TC_IDR = 0xFFFFFFFF;
+
+ /* Clear status register. */
+ tc_channel->TC_SR;
+
+ /* Set mode. */
+ tc_channel->TC_CMR = ul_mode;
+}
+
+/**
+ * \brief Asserts a SYNC signal to generate a software trigger on
+ * all channels.
+ *
+ * \param[out] p_tc Module hardware register base address pointer
+ *
+ */
+void tc_sync_trigger(
+ Tc *p_tc)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+
+ p_tc->TC_BCR = TC_BCR_SYNC;
+}
+
+/**
+ * \brief Configure the TC Block mode.
+ *
+ * \note The function tc_init() must be called prior to this one.
+ *
+ * \param[out] p_tc Module hardware register base address pointer
+ * \param[in] ul_blockmode Block mode register value to set
+ *
+ * \note For more information regarding <i>ul_blockmode</i> configuration refer to
+ * the section entitled "TC Block Mode Register" in the device-specific datasheet.
+ */
+void tc_set_block_mode(
+ Tc *p_tc,
+ uint32_t ul_blockmode)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+
+ p_tc->TC_BMR = ul_blockmode;
+}
+
+#if (!SAM3U) || defined(__DOXYGEN__)
+
+/**
+ * \brief Configure TC for 2-bit Gray Counter for Stepper Motor.
+ * \note The function tc_init() must be called prior to this one.
+ *
+ * \note This function is not available on SAM3U devices.
+ *
+ * \param[out] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel to configure
+ * \param[in] ul_steppermode Stepper motor mode register value to set
+ *
+ * \return 0 for OK.
+ */
+uint32_t tc_init_2bit_gray(
+ Tc *p_tc,
+ uint32_t ul_channel,
+ uint32_t ul_steppermode)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+
+ p_tc->TC_CHANNEL[ul_channel].TC_SMMR = ul_steppermode;
+ return 0;
+}
+
+#endif /* (!SAM3U) || defined(__DOXYGEN__) */
+
+/**
+ * \brief Start the TC clock on the specified channel.
+ *
+ * \param[out] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel to configure
+ */
+void tc_start(
+ Tc *p_tc,
+ uint32_t ul_channel)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+
+ p_tc->TC_CHANNEL[ul_channel].TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;
+}
+
+/**
+ * \brief Stop the TC clock on the specified channel.
+ *
+ * \param[out] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel to configure
+ */
+void tc_stop(
+ Tc *p_tc,
+ uint32_t ul_channel)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+
+ p_tc->TC_CHANNEL[ul_channel].TC_CCR = TC_CCR_CLKDIS;
+}
+
+/**
+ * \brief Read the counter value on the specified channel.
+ *
+ * \param[in] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel to read
+ *
+ * \return The counter value.
+ */
+uint32_t tc_read_cv(
+ Tc *p_tc,
+ uint32_t ul_channel)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+
+ return p_tc->TC_CHANNEL[ul_channel].TC_CV;
+}
+
+/**
+ * \brief Read TC Register A (RA) on the specified channel.
+ *
+ * \param[in] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel to read
+ *
+ * \return The TC Register A (RA) value.
+ */
+uint32_t tc_read_ra(
+ Tc *p_tc,
+ uint32_t ul_channel)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+
+ return p_tc->TC_CHANNEL[ul_channel].TC_RA;
+}
+
+/**
+ * \brief Read TC Register B (RB) on the specified channel.
+ *
+ * \param[in] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel to read
+ *
+ * \return The TC Register B (RB) value.
+ */
+uint32_t tc_read_rb(
+ Tc *p_tc,
+ uint32_t ul_channel)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+
+ return p_tc->TC_CHANNEL[ul_channel].TC_RB;
+}
+
+/**
+ * \brief Read TC Register C (RC) on the specified channel.
+ *
+ * \param[in] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel to read
+ *
+ * \return The Register C (RC) value.
+ */
+uint32_t tc_read_rc(
+ Tc *p_tc,
+ uint32_t ul_channel)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+
+ return p_tc->TC_CHANNEL[ul_channel].TC_RC;
+}
+
+/**
+ * \brief Write to TC Register A (RA) on the specified channel.
+ *
+ * \param[out] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel to write
+ * \param[in] ul_value Value to write
+ */
+void tc_write_ra(
+ Tc *p_tc,
+ uint32_t ul_channel,
+ uint32_t ul_value)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+
+ p_tc->TC_CHANNEL[ul_channel].TC_RA = ul_value;
+}
+
+/**
+ * \brief Write to TC Register B (RB) on the specified channel.
+ *
+ * \param[out] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel to write
+ * \param[in] ul_value Value to write
+ */
+void tc_write_rb(
+ Tc *p_tc,
+ uint32_t ul_channel,
+ uint32_t ul_value)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+
+ p_tc->TC_CHANNEL[ul_channel].TC_RB = ul_value;
+}
+
+/**
+ * \brief Write to TC Register C (RC) on the selected channel.
+ *
+ * \param[out] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel to write
+ * \param[in] ul_value Value to write
+ */
+void tc_write_rc(
+ Tc *p_tc,
+ uint32_t ul_channel,
+ uint32_t ul_value)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+
+ p_tc->TC_CHANNEL[ul_channel].TC_RC = ul_value;
+}
+
+/**
+ * \brief Enable the TC interrupts on the specified channel.
+ *
+ * \param[in,out] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel to configure
+ * \param[in] ul_sources Bitmask of interrupt sources
+ *
+ * Where the input parameter <i>ul_sources</i> can be one or more of the following:
+ * <table>
+ * <tr>
+ * <th>Parameter Value</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr><td>TC_IER_COVFS</td><td>Enables the Counter Overflow Interrupt</td></tr>
+ * <tr><td>TC_IER_LOVRS</td><td>Enables the Load Overrun Interrupt</td></tr>
+ * <tr><td>TC_IER_CPAS</td><td>Enables the RA Compare Interrupt</td></tr>
+ * <tr><td>TC_IER_CPBS</td><td>Enables the RB Compare Interrupt</td></tr>
+ * <tr><td>TC_IER_CPCS</td><td>Enables the RC Compare Interrupt</td></tr>
+ * <tr><td>TC_IER_LDRAS</td><td>Enables the RA Load Interrupt</td></tr>
+ * <tr><td>TC_IER_LDRBS</td><td>Enables the RB Load Interrupt</td></tr>
+ * <tr><td>TC_IER_ETRGS</td><td>Enables the External Trigger Interrupt</td></tr>
+ * </table>
+ */
+void tc_enable_interrupt(
+ Tc *p_tc,
+ uint32_t ul_channel,
+ uint32_t ul_sources)
+{
+ TcChannel *tc_channel;
+
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+ tc_channel = p_tc->TC_CHANNEL + ul_channel;
+ tc_channel->TC_IER = ul_sources;
+}
+
+/**
+ * \brief Disable TC interrupts on the specified channel.
+ *
+ * \param[in,out] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel to configure
+ * \param[in] ul_sources A bitmask of Interrupt sources
+ *
+ * Where the input parameter <i>ul_sources</i> can be one or more of the following:
+ * <table>
+ * <tr>
+ * <th>Parameter Value</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr><td>TC_IDR_COVFS</td><td>Disables the Counter Overflow Interrupt</td></tr>
+ * <tr><td>TC_IDR_LOVRS</td><td>Disables the Load Overrun Interrupt</td></tr>
+ * <tr><td>TC_IDR_CPAS</td><td>Disables the RA Compare Interrupt</td></tr>
+ * <tr><td>TC_IDR_CPBS</td><td>Disables the RB Compare Interrupt</td></tr>
+ * <tr><td>TC_IDR_CPCS</td><td>Disables the RC Compare Interrupt</td></tr>
+ * <tr><td>TC_IDR_LDRAS</td><td>Disables the RA Load Interrupt</td></tr>
+ * <tr><td>TC_IDR_LDRBS</td><td>Disables the RB Load Interrupt</td></tr>
+ * <tr><td>TC_IDR_ETRGS</td><td>Disables the External Trigger Interrupt</td></tr>
+ * </table>
+ */
+void tc_disable_interrupt(
+ Tc *p_tc,
+ uint32_t ul_channel,
+ uint32_t ul_sources)
+{
+ TcChannel *tc_channel;
+
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+ tc_channel = p_tc->TC_CHANNEL + ul_channel;
+ tc_channel->TC_IDR = ul_sources;
+}
+
+/**
+ * \brief Read the TC interrupt mask for the specified channel.
+ *
+ * \param[in] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel to read
+ *
+ * \return The TC interrupt mask value.
+ */
+uint32_t tc_get_interrupt_mask(
+ Tc *p_tc,
+ uint32_t ul_channel)
+{
+ TcChannel *tc_channel;
+
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+ tc_channel = p_tc->TC_CHANNEL + ul_channel;
+ return tc_channel->TC_IMR;
+}
+
+/**
+ * \brief Get the current status for the specified TC channel.
+ *
+ * \param[in] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel number
+ *
+ * \return The current TC status.
+ */
+uint32_t tc_get_status(
+ Tc *p_tc,
+ uint32_t ul_channel)
+{
+ TcChannel *tc_channel;
+
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+
+ tc_channel = p_tc->TC_CHANNEL + ul_channel;
+ return tc_channel->TC_SR;
+}
+
+/* TC divisor used to find the lowest acceptable timer frequency */
+#define TC_DIV_FACTOR 65536
+
+#if (!SAM4L) && !defined(__DOXYGEN__)
+
+#ifndef FREQ_SLOW_CLOCK_EXT
+#define FREQ_SLOW_CLOCK_EXT 32768 /* External slow clock frequency (hz) */
+#endif
+
+/**
+ * \brief Find the best MCK divisor.
+ *
+ * Finds the best MCK divisor given the timer frequency and MCK. The result
+ * is guaranteed to satisfy the following equation:
+ * \code (MCK / (DIV * 65536)) <= freq <= (MCK / DIV) \endcode
+ * With DIV being the lowest possible value, to maximize timing adjust resolution.
+ *
+ * \param[in] ul_freq Desired timer frequency
+ * \param[in] ul_mck Master clock frequency
+ * \param[out] p_uldiv Divisor value
+ * \param[out] p_ultcclks TCCLKS field value for divisor
+ * \param[in] ul_boardmck Board clock frequency
+ *
+ * \return The divisor found status.
+ * \retval 0 No suitable divisor was found
+ * \retval 1 A divisor was found
+ */
+uint32_t tc_find_mck_divisor(
+ uint32_t ul_freq,
+ uint32_t ul_mck,
+ uint32_t *p_uldiv,
+ uint32_t *p_ultcclks,
+ uint32_t ul_boardmck)
+{
+ const uint32_t divisors[5] = { 2, 8, 32, 128,
+ ul_boardmck / FREQ_SLOW_CLOCK_EXT
+ };
+ uint32_t ul_index;
+ uint32_t ul_high, ul_low;
+
+ /* Satisfy frequency bound. */
+ for (ul_index = 0;
+ ul_index < (sizeof(divisors) / sizeof(divisors[0]));
+ ul_index++) {
+ ul_high = ul_mck / divisors[ul_index];
+ ul_low = ul_high / TC_DIV_FACTOR;
+ if (ul_freq > ul_high) {
+ return 0;
+ } else if (ul_freq >= ul_low) {
+ break;
+ }
+ }
+ if (ul_index >= (sizeof(divisors) / sizeof(divisors[0]))) {
+ return 0;
+ }
+
+ /* Store results. */
+ if (p_uldiv) {
+ *p_uldiv = divisors[ul_index];
+ }
+
+ if (p_ultcclks) {
+ *p_ultcclks = ul_index;
+ }
+
+ return 1;
+}
+
+#endif /* (!SAM4L) */
+
+#if (SAM4L) || defined(__DOXYGEN__)
+/**
+ * \brief Find the best PBA/MCK divisor.
+ *
+ * <b>For SAM4L devices:</b> Finds the best PBA divisor given the timer
+ * frequency and PBA clock. The result is guaranteed to satisfy the following equation:
+ * \code (ul_pbaclk / (2* DIV * 65536)) <= freq <= (ul_pbaclk / (2* DIV)) \endcode
+ * with DIV being the lowest possible value, to maximize timing adjust resolution.
+ *
+ * <b>For non SAM4L devices:</b> Finds the best MCK divisor given the timer frequency
+ * and MCK. The result is guaranteed to satisfy the following equation:
+ * \code (MCK / (DIV * 65536)) <= freq <= (MCK / DIV) \endcode
+ * with DIV being the lowest possible value, to maximize timing adjust resolution.
+ *
+ * \param[in] ul_freq Desired timer frequency
+ * \param[in] ul_mck PBA clock frequency
+ * \param[out] p_uldiv Divisor value
+ * \param[out] p_ultcclks TCCLKS field value for divisor
+ * \param[in] ul_boardmck Board clock frequency (set to 0 for SAM4L devices)
+ *
+ * \return The divisor found status.
+ * \retval 0 No suitable divisor was found
+ * \retval 1 A divisor was found
+ */
+uint32_t tc_find_mck_divisor(
+ uint32_t ul_freq,
+ uint32_t ul_mck,
+ uint32_t *p_uldiv,
+ uint32_t *p_ultcclks,
+ uint32_t ul_boardmck)
+{
+ const uint32_t divisors[5] = { 0, 2, 8, 32, 128};
+ uint32_t ul_index;
+ uint32_t ul_high, ul_low;
+
+ UNUSED(ul_boardmck);
+
+ /* Satisfy frequency bound. */
+ for (ul_index = 1;
+ ul_index < (sizeof(divisors) / sizeof(divisors[0]));
+ ul_index++) {
+ ul_high = ul_mck / divisors[ul_index];
+ ul_low = ul_high / TC_DIV_FACTOR;
+ if (ul_freq > ul_high) {
+ return 0;
+ } else if (ul_freq >= ul_low) {
+ break;
+ }
+ }
+ if (ul_index >= (sizeof(divisors) / sizeof(divisors[0]))) {
+ return 0;
+ }
+
+ /* Store results. */
+ if (p_uldiv) {
+ *p_uldiv = divisors[ul_index];
+ }
+
+ if (p_ultcclks) {
+ *p_ultcclks = ul_index;
+ }
+
+ return 1;
+}
+
+#endif /* (SAM4L) || defined(__DOXYGEN__) */
+
+#if (!SAM4L && !SAMG) || defined(__DOXYGEN__)
+
+/**
+ * \brief Enable TC QDEC interrupts.
+ *
+ * \note This function is not available on SAM4L or SAMG devices.
+ *
+ * \param[out] p_tc Module hardware register base address pointer
+ * \param[in] ul_sources A bitmask of QDEC interrupts to be enabled
+ *
+ * Where the input parameter <i>ul_sources</i> can be one or more of the following:
+ * <table>
+ * <tr>
+ * <th>Parameter Value</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr><td>TC_QIER_IDX</td><td>Enable the rising edge detected on IDX input interrupt</td></tr>
+ * <tr><td>TC_QIER_DIRCHG</td><td>Enable the change in rotation direction detected interrupt</td></tr>
+ * <tr><td>TC_QIER_QERR</td><td>Enable the quadrature error detected on PHA/PHB interrupt</td></tr>
+ * </table>
+ */
+void tc_enable_qdec_interrupt(
+ Tc *p_tc,
+ uint32_t ul_sources)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+
+ p_tc->TC_QIER = ul_sources;
+}
+
+/**
+ * \brief Disable TC QDEC interrupts.
+ *
+ * \note This function is not available on SAM4L or SAMG devices.
+ *
+ * \param[out] p_tc Module hardware register base address pointer
+ * \param[in] ul_sources A bitmask of QDEC interrupts to be disabled
+ *
+ * Where the input parameter <i>ul_sources</i> can be one or more of the following:
+ * <table>
+ * <tr>
+ * <th>Parameter Value</th>
+ * <th>Description</th>
+ * </tr>
+ * <tr><td>TC_QIDR_IDX</td><td>Disable the rising edge detected on IDX input interrupt</td></tr>
+ * <tr><td>TC_QIDR_DIRCHG</td><td>Disable the change in rotation direction detected interrupt</td></tr>
+ * <tr><td>TC_QIDR_QERR</td><td>Disable the quadrature error detected on PHA/PHB interrupt</td></tr>
+ * </table>
+ */
+void tc_disable_qdec_interrupt(
+ Tc *p_tc,
+ uint32_t ul_sources)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+
+ p_tc->TC_QIDR = ul_sources;
+}
+
+/**
+ * \brief Read TC QDEC interrupt mask.
+ *
+ * \note This function is not available on SAM4L or SAMG devices.
+ *
+ * \param[in] p_tc Module hardware register base address pointer
+ *
+ * \return The QDEC interrupt mask value.
+ */
+uint32_t tc_get_qdec_interrupt_mask(
+ Tc *p_tc)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+
+ return p_tc->TC_QIMR;
+}
+
+/**
+ * \brief Get current TC QDEC interrupt status.
+ *
+ * \note This function is not available on SAM4L or SAMG devices.
+ *
+ * \param[in] p_tc Module hardware register base address pointer
+ *
+ * \return The TC QDEC interrupt status.
+ */
+uint32_t tc_get_qdec_interrupt_status(
+ Tc *p_tc)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+
+ return p_tc->TC_QISR;
+}
+
+#endif /* (!SAM4L && !SAMG) || defined(__DOXYGEN__) */
+
+#if (!SAM3U) || defined(__DOXYGEN__)
+
+/**
+ * \brief Enable or disable write protection of TC registers.
+ *
+ * \note This function is not available on SAM3U devices.
+ *
+ * \param[out] p_tc Module hardware register base address pointer
+ * \param[in] ul_enable 1 to enable, 0 to disable
+ */
+void tc_set_writeprotect(
+ Tc *p_tc,
+ uint32_t ul_enable)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+
+ if (ul_enable) {
+ p_tc->TC_WPMR = TC_WPMR_WPKEY_PASSWD | TC_WPMR_WPEN;
+ } else {
+ p_tc->TC_WPMR = TC_WPMR_WPKEY_PASSWD;
+ }
+}
+
+#endif /* (!SAM3U) || defined(__DOXYGEN__) */
+
+#if SAM4L || defined(__DOXYGEN__)
+
+/**
+ * \brief Indicate TC features.
+ *
+ * \note This function is only available on SAM4L devices.
+ *
+ * \param[in] p_tc Module hardware register base address pointer
+ *
+ * \return The TC FEATURES register contents.
+ */
+uint32_t tc_get_feature(
+ Tc *p_tc)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+
+ return p_tc->TC_FEATURES;
+}
+
+/**
+ * \brief Indicate TC version.
+ *
+ * \note This function is only available on SAM4L devices.
+ *
+ * \param[in] p_tc Module hardware register base address pointer
+ *
+ * \return The TC VERSION register contents.
+ */
+uint32_t tc_get_version(
+ Tc *p_tc)
+{
+ /* Validate inputs. */
+ Assert(p_tc);
+
+ return p_tc->TC_VERSION;
+}
+
+#endif /* SAM4L || defined(__DOXYGEN__) */
+
+/// @cond
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/tc/tc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,455 @@
+/**
+ * \file
+ *
+ * \brief SAM Timer Counter (TC) driver.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef TC_H_INCLUDED
+#define TC_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam_drivers_tc_group SAM3/4S/4L/4E/4N/4CM/4C/G Timer Counter (TC) Driver
+ *
+ * This driver for Atmel® | SMART ARM®-based microcontrollers
+ * provides an interface for the configuration and management of the
+ * device's Timer Counter functionality.
+ *
+ * The Timer Counter (TC) includes several identical 16-bit or 32-bit
+ * Timer Counter channels. Each channel can be independently programmed
+ * to perform a wide range of functions that includes frequency
+ * measurement, event counting, interval measurement, pulse generation,
+ * delay timing, and pulse width modulation.
+ *
+ * Devices from the following series can use this module:
+ * - Atmel | SMART SAM3
+ * - Atmel | SMART SAM4S
+ * - Atmel | SMART SAM4L
+ * - Atmel | SMART SAM4E
+ * - Atmel | SMART SAM4N
+ * - Atmel | SMART SAM4CM
+ * - Atmel | SMART SAM4C
+ * - Atmel | SMART SAMG
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam_drivers_tc_prerequisites
+ * - \ref asfdoc_sam_drivers_tc_module_overview
+ * - \ref asfdoc_sam_drivers_tc_special_considerations
+ * - \ref asfdoc_sam_drivers_tc_extra_info
+ * - \ref asfdoc_sam_drivers_tc_examples
+ * - \ref asfdoc_sam_drivers_tc_api_overview
+ *
+ *
+ * \section asfdoc_sam_drivers_tc_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam_drivers_tc_module_overview Module Overview
+ * The Timer Counter (TC) includes several identical 16-bit or 32-bit Timer
+ * Counter channels. The number of TC channels is device specific, refer
+ * to the device-specific datasheet for more information.
+ *
+ * Each channel can be independently programmed to perform a wide range of
+ * functions that includes frequency measurement, event counting, interval measurement,
+ * pulse generation, delay timing, and pulse width modulation.
+ *
+ * Each channel has three external clock inputs, five internal clock inputs,
+ * and two multi-purpose input/output signals which can be configured by the user.
+ * Each channel drives an internal interrupt signal which can be programmed to
+ * generate processor interrupts.
+ *
+ * The Timer Counter (TC) embeds a quadrature decoder logic connected in front of
+ * the timers. When enabled, the quadrature decoder performs the input line
+ * filtering, decoding of quadrature signals and connects to the timers/counters
+ * in order to read the position and speed of the motor.
+ *
+ *
+ * \section asfdoc_sam_drivers_tc_special_considerations Special Considerations
+ * \subsection asfdoc_sam_drivers_tc_special_considerations_clock External Clock
+ * In all cases, if an external clock is used, the duration of each of its levels
+ * must be longer than the master clock (MCLK) period. The external clock frequency
+ * must be at least 2.5 times lower than the master clock.
+ *
+ * \subsection asfdoc_sam_drivers_tc_special_considerations_trigger External Trigger
+ * If an external trigger is used, the duration of its pulses must be longer than
+ * the master clock (MCLK) period in order to be detected.
+ *
+ *
+ * \section asfdoc_sam_drivers_tc_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam_drivers_tc_extra. This includes:
+ * - \ref asfdoc_sam_drivers_tc_extra_acronyms
+ * - \ref asfdoc_sam_drivers_tc_extra_dependencies
+ * - \ref asfdoc_sam_drivers_tc_extra_errata
+ * - \ref asfdoc_sam_drivers_tc_extra_history
+ *
+ * \section asfdoc_sam_drivers_tc_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam_drivers_tc_exqsg.
+ *
+ *
+ * \section asfdoc_sam_drivers_tc_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+
+/// @cond
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ void tc_init(Tc *p_tc, uint32_t ul_Channel, uint32_t ul_Mode);
+ void tc_sync_trigger(Tc *p_tc);
+ void tc_set_block_mode(Tc *p_tc, uint32_t ul_blockmode);
+
+#if (!SAM3U) || defined(__DOXYGEN__)
+ uint32_t tc_init_2bit_gray(Tc *p_tc, uint32_t ul_channel,
+ uint32_t ul_steppermode);
+#endif /* (!SAM3U) || defined(__DOXYGEN__) */
+
+ void tc_start(Tc *p_tc, uint32_t ul_channel);
+ void tc_stop(Tc *p_tc, uint32_t ul_channel);
+
+ uint32_t tc_read_cv(Tc *p_tc, uint32_t ul_channel);
+ uint32_t tc_read_ra(Tc *p_tc, uint32_t ul_channel);
+ uint32_t tc_read_rb(Tc *p_tc, uint32_t ul_channel);
+ uint32_t tc_read_rc(Tc *p_tc, uint32_t ul_channel);
+
+ void tc_write_ra(Tc *p_tc, uint32_t ul_channel,
+ uint32_t ul_value);
+ void tc_write_rb(Tc *p_tc, uint32_t ul_channel,
+ uint32_t ul_value);
+ void tc_write_rc(Tc *p_tc, uint32_t ul_channel,
+ uint32_t ul_value);
+
+ uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck,
+ uint32_t *p_uldiv, uint32_t *ul_tcclks, uint32_t ul_boardmck);
+ void tc_enable_interrupt(Tc *p_tc, uint32_t ul_channel,
+ uint32_t ul_sources);
+ void tc_disable_interrupt(Tc *p_tc, uint32_t ul_channel,
+ uint32_t ul_sources);
+ uint32_t tc_get_interrupt_mask(Tc *p_tc, uint32_t ul_channel);
+ uint32_t tc_get_status(Tc *p_tc, uint32_t ul_channel);
+#if (!SAM4L && !SAMG) || defined(__DOXYGEN__)
+ void tc_enable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources);
+ void tc_disable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources);
+ uint32_t tc_get_qdec_interrupt_mask(Tc *p_tc);
+ uint32_t tc_get_qdec_interrupt_status(Tc *p_tc);
+#endif /* (!SAM4L && !SAMG) || defined(__DOXYGEN__) */
+
+#if (!SAM3U)
+ void tc_set_writeprotect(Tc *p_tc, uint32_t ul_enable);
+#endif /* (!SAM3U) */
+
+#if SAM4L || defined(__DOXYGEN__)
+ uint32_t tc_get_feature(Tc *p_tc);
+ uint32_t tc_get_version(Tc *p_tc);
+#endif /* SAM4L || defined(__DOXYGEN__) */
+
+/// @cond
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/** @} */
+
+/**
+ * \page asfdoc_sam_drivers_tc_extra Extra Information for Timer Counter Driver
+ *
+ * \section asfdoc_sam_drivers_tc_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ * <tr>
+ * <th>Acronym</th>
+ * <th>Definition</th>
+ * </tr>
+ * <tr>
+ * <td>MCK</td>
+ * <td>Master Clock</td>
+ * </tr>
+ * <tr>
+ * <td>PBA</td>
+ * <td>Peripheral Bus A clock</td>
+ * </tr>
+ * <tr>
+ * <td>PHA</td>
+ * <td>Quadrature Decoder input signal Phase A</td>
+ * </tr>
+ * <tr>
+ * <td>PHB</td>
+ * <td>Quadrature Decoder input signal Phase B</td>
+ * </tr>
+ * <tr>
+ * <td>QDEC</td>
+ * <td>Quadrature Decoder</td>
+ * </tr>
+ * <tr>
+ * <td>QSG</td>
+ * <td>Quick Start Guide</td>
+ * </tr>
+ * <tr>
+ * <td>RA</td>
+ * <td>Register A</td>
+ * </tr>
+ * <tr>
+ * <td>RB</td>
+ * <td>Register B</td>
+ * </tr>
+ * <tr>
+ * <td>RC</td>
+ * <td>Register C</td>
+ * </tr>
+ * <tr>
+ * <td>TIOB</td>
+ * <td>Timer Input Output B</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam_drivers_tc_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ * - \ref clk_group "System Clock Management (sysclock)"
+ * - \ref asfdoc_sam_drivers_gpio_group "General Purpose I/O (GPIO) driver"
+ * - \ref asfdoc_sam_drivers_pmc_group "Power Manager Controller (PMC) driver"
+ *
+ *
+ * \section asfdoc_sam_drivers_tc_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam_drivers_tc_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ * <tr>
+ * <th>Changelog</th>
+ * </tr>
+ * <tr>
+ * <td>Initial document release</td>
+ * </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam_drivers_tc_exqsg Examples for Timer Counter
+ *
+ * This is a list of the available Quick Start Guides (QSGs) and example
+ * applications for \ref asfdoc_sam_drivers_tc_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * - \subpage asfdoc_sam_drivers_tc_qsg
+ * - \subpage asfdoc_sam_drivers_tc_example
+ *
+ * \page asfdoc_sam_drivers_tc_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ * <th>Doc. Rev.</td>
+ * <th>Date</td>
+ * <th>Comments</td>
+ * </tr>
+ * <tr>
+ * <td>42301B</td>
+ * <td>07/2015</td>
+ * <td>Updated title of application note and added list of supported devices</td>
+ * </tr>
+ * <tr>
+ * <td>42301A</td>
+ * <td>05/2014</td>
+ * <td>Initial document release</td>
+ * </tr>
+ * </table>
+ *
+ */
+
+/**
+ * \page asfdoc_sam_drivers_tc_qsg Quick Start Guide for the TC driver
+ *
+ * This is the quick start guide for the \ref asfdoc_sam_drivers_tc_group, with
+ * step-by-step instructions on how to configure and use the driver for
+ * a specific use case. The code examples can be copied into the main
+ * application loop or any other function that will need to control the
+ * AST module.
+ *
+ * \section asfdoc_sam_drivers_tc_qsg_use_cases Use Cases
+ * - \ref asfdoc_sam_drivers_tc_qsg_basic_capture
+ * - \ref asfdoc_sam_drivers_tc_qsg_basic_waveform
+ *
+ * \section asfdoc_sam_drivers_tc_qsg_basic_capture TC Capture Mode Basic Usage
+ *
+ * This use case will demonstrate how to initialize the TC module to
+ * operate in capture mode using interrupts. Note, that the macros
+ * used to select the TC channel are device specific. Refer to the
+ * appropriate device-specific datasheet for more information.
+ *
+ *
+ * \section asfdoc_sam_drivers_tc_qsg_basic_capture_setup Setup Steps
+ *
+ * \subsection asfdoc_sam_tc_qsg_basic_capture_prereq Prerequisites
+ *
+ * This module requires the following services:
+ * - \ref clk_group "System Clock Management (sysclock)"
+ * - \ref asfdoc_sam_drivers_gpio_group "General Purpose I/O (GPIO) driver"
+ *
+ * \subsection asfdoc_sam_drivers_tc_qsg_basic_capture_setup_code Setup Code
+ *
+ * Add these macros to the top of your main application C-file:
+ * \snippet conf_board.h tc_define_peripheral
+ * \snippet conf_board.h tc_define_ch2
+ * \snippet conf_board.h tc_define_irq_handler
+ *
+ * Add this macro and functions to your main application C-file:
+ * \snippet tc_capture_waveform_example.c tc_capture_selection
+ * \snippet tc_capture_waveform_example.c tc_capture_init
+ * \snippet tc_capture_waveform_example.c tc_capture_irq_handler_start
+ * \snippet tc_capture_waveform_example.c tc_capture_irq_handler_end
+ *
+ * \subsection asfdoc_sam_drivers_tc_qsg_basic_capture_setup_workflow Workflow
+ *
+ * -# Enable the TC module's capture pin:
+ * \snippet tc_capture_waveform_example.c tc_capture_gpio
+ * -# Initialize the capture channel to the following:
+ * - Load RA on the rising edge of TIOA
+ * - Load RB on the falling edge of TIOA
+ * - Set the external trigger to TIOA
+ * - Set the external trigger to falling edge
+ * \snippet tc_capture_waveform_example.c tc_capture_init_call
+ * -# Enable the TC interrupt using NVIC:
+ * \snippet tc_capture_waveform_example.c tc_capture_init_irq
+ * -# Enable the capture channel interrupt:
+ * \snippet tc_capture_waveform_example.c tc_capture_init_module_irq
+ * -# In the \ref TC_Handler_null "TC_Handler()" function, the load.
+ * RB interrupt can be checked by:
+ * \snippet tc_capture_waveform_example.c tc_capture_irq_handler_status
+ * \code } \endcode
+ * -# In the \ref TC_Handler_null "TC_Handler()" function, the RA value.
+ * can be read by:
+ * \code uint32_t gs_ul_captured_ra; \endcode
+ * \snippet tc_capture_waveform_example.c tc_capture_irq_handler_read_ra
+ * -# In the \ref TC_Handler_null "TC_Handler()" function, the RB value.
+ * can be read by:
+ * \code uint32_t gs_ul_captured_rb; \endcode
+ * \snippet tc_capture_waveform_example.c tc_capture_irq_handler_read_rb
+ *
+ * \section asfdoc_sam_drivers_tc_qsg_basic_waveform TC Waveform Mode Basic Usage
+ *
+ * This use case will demonstrate how to initialize the TC module to
+ * operate in waveform mode. Note, that the macros used to select
+ * the TC channel are device specific. Refer to the appropriate
+ * device-specific datasheet for more information.
+ *
+ *
+ * \section asfdoc_sam_drivers_tc_qsg_basic_waveform_setup Setup Steps
+ *
+ * \subsection asfdoc_sam_tc_qsg_basic_waveform_prereq Prerequisites
+ *
+ * This module requires the following services:
+ * - \ref clk_group "System Clock Management (sysclock)"
+ * - \ref asfdoc_sam_drivers_gpio_group "General Purpose I/O (GPIO) driver"
+ *
+ * \subsection asfdoc_sam_drivers_tc_qsg_basic_waveform_setup_code Setup Code
+ *
+ * Add these macros to the top of your main application C-file:
+ * \snippet conf_board.h tc_define_peripheral
+ * \snippet conf_board.h tc_define_ch1
+ *
+ * Add these macros and function to your main application C-file:
+ * \code #define TC_WAVEFORM_TIMER_SELECTION TC_CMR_TCCLKS_TIMER_CLOCK4 \endcode
+ * \code #define TC_WAVEFORM_DIVISOR 128 \endcode
+ * \code #define TC_WAVEFORM_FREQUENCY 178 \endcode
+ * \code #define TC_WAVEFORM_DUTY_CYCLE 30 \endcode
+ * \code
+ * static void tc_waveform_initialize(void)
+ * {
+ * uint32_t ra, rc;
+ *
+ * // Configure the PMC to enable the TC module.
+ * sysclk_enable_peripheral_clock(ID_TC_WAVEFORM);
+ *
+ * // Init TC to waveform mode.
+ * tc_init(TC, TC_CHANNEL_WAVEFORM,
+ * TC_WAVEFORM_TIMER_SELECTION // Waveform Clock Selection
+ * | TC_CMR_WAVE // Waveform mode is enabled
+ * | TC_CMR_ACPA_SET // RA Compare Effect: set
+ * | TC_CMR_ACPC_CLEAR // RC Compare Effect: clear
+ * | TC_CMR_CPCTRG // UP mode with automatic trigger on RC Compare
+ * );
+ *
+ * // Configure waveform frequency and duty cycle.
+ * rc = (sysclk_get_peripheral_bus_hz(TC) /
+ * TC_WAVEFORM_DIVISOR /
+ * TC_WAVEFORM_FREQUENCY;
+ * tc_write_rc(TC, TC_CHANNEL_WAVEFORM, rc);
+ * ra = (100 - TC_WAVEFORM_FREQUENCY_DUTY_CYCLE * rc / 100;
+ * tc_write_ra(TC, TC_CHANNEL_WAVEFORM, ra);
+ *
+ * // Enable TC TC_CHANNEL_WAVEFORM.
+ * tc_start(TC, TC_CHANNEL_WAVEFORM);
+ * } \endcode
+ *
+ * \subsection asfdoc_sam_drivers_tc_qsg_basic_waveform_setup_workflow Workflow
+ *
+ * -# Enable the TC module's waveform pin:
+ * \snippet tc_capture_waveform_example.c tc_waveform_gpio
+ * -# Initialize the waveform channel to the following:
+ * - Output frequency of 178Hz, with a duty-cycle of 30%
+ * - Use TC_CMR_TCCLKS_TIMER_CLOCK4, with a divisor of 128
+ * \snippet tc_capture_waveform_example.c tc_waveform_init_call
+ */
+#endif /* TC_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/twi/twi.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,744 @@
+/**
+ * \file
+ *
+ * \brief Two-Wire Interface (TWI) driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "twi.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /**
+ * \defgroup sam_drivers_twi_group Two-Wire Interface (TWI)
+ *
+ * Driver for the TWI (Two-Wire Interface). This driver provides access to the main
+ * features of the TWI controller.
+ * The TWI interconnects components on a unique two-wire bus.
+ * The TWI is programmable as a master or a slave with sequential or single-byte access.
+ * Multiple master capability is supported.
+ *
+ * \par Usage
+ *
+ * -# Enable the TWI peripheral clock in the PMC.
+ * -# Enable the required TWI PIOs (see pio.h).
+ * -# Enable TWI master mode by calling twi_enable_master_mode if it is a master on the I2C bus.
+ * -# Configure the TWI in master mode by calling twi_master_init.
+ * -# Send data to a slave device on the I2C bus by calling twi_master_write.
+ * -# Receive data from a slave device on the I2C bus by calling the twi_master_read.
+ * -# Enable TWI slave mode by calling twi_enable_slave_mode if it is a slave on the I2C bus.
+ * -# Configure the TWI in slave mode by calling twi_slave_init.
+ *
+ * @{
+ */
+
+#define I2C_FAST_MODE_SPEED 400000
+#define TWI_CLK_DIVIDER 2
+#define TWI_CLK_CALC_ARGU 4
+#define TWI_CLK_DIV_MAX 0xFF
+#define TWI_CLK_DIV_MIN 7
+
+#define TWI_WP_KEY_VALUE TWI_WPMR_WPKEY_PASSWD
+
+ /**
+ * \brief Enable TWI master mode.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ */
+ void twi_enable_master_mode(Twi *p_twi)
+{
+ /* Set Master Disable bit and Slave Disable bit */
+ p_twi->TWI_CR = TWI_CR_MSDIS;
+ p_twi->TWI_CR = TWI_CR_SVDIS;
+
+ /* Set Master Enable bit */
+ p_twi->TWI_CR = TWI_CR_MSEN;
+}
+
+/**
+ * \brief Disable TWI master mode.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ */
+void twi_disable_master_mode(Twi *p_twi)
+{
+ /* Set Master Disable bit */
+ p_twi->TWI_CR = TWI_CR_MSDIS;
+}
+
+/**
+ * \brief Initialize TWI master mode.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ * \param p_opt Options for initializing the TWI module (see \ref twi_options_t).
+ *
+ * \return TWI_SUCCESS if initialization is complete, error code otherwise.
+ */
+uint32_t twi_master_init(Twi *p_twi, const twi_options_t *p_opt)
+{
+ uint32_t status = TWI_SUCCESS;
+
+ /* Disable TWI interrupts */
+ p_twi->TWI_IDR = ~0UL;
+
+ /* Dummy read in status register */
+ p_twi->TWI_SR;
+
+ /* Reset TWI peripheral */
+ twi_reset(p_twi);
+
+ twi_enable_master_mode(p_twi);
+
+ /* Select the speed */
+ if (twi_set_speed(p_twi, p_opt->speed, p_opt->master_clk) == FAIL) {
+ /* The desired speed setting is rejected */
+ status = TWI_INVALID_ARGUMENT;
+ }
+
+ if (p_opt->smbus == 1) {
+ p_twi->TWI_CR = TWI_CR_QUICK;
+ }
+
+ return status;
+}
+
+/**
+ * \brief Set the I2C bus speed in conjunction with the clock frequency.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ * \param ul_speed The desired I2C bus speed (in Hz).
+ * \param ul_mck Main clock of the device (in Hz).
+ *
+ * \retval PASS New speed setting is accepted.
+ * \retval FAIL New speed setting is rejected.
+ */
+uint32_t twi_set_speed(Twi *p_twi, uint32_t ul_speed, uint32_t ul_mck)
+{
+ uint32_t ckdiv = 0;
+ uint32_t c_lh_div;
+
+ if (ul_speed > I2C_FAST_MODE_SPEED) {
+ return FAIL;
+ }
+
+ c_lh_div = ul_mck / (ul_speed * TWI_CLK_DIVIDER) - TWI_CLK_CALC_ARGU;
+
+ /* cldiv must fit in 8 bits, ckdiv must fit in 3 bits */
+ while ((c_lh_div > TWI_CLK_DIV_MAX) && (ckdiv < TWI_CLK_DIV_MIN)) {
+ /* Increase clock divider */
+ ckdiv++;
+ /* Divide cldiv value */
+ c_lh_div /= TWI_CLK_DIVIDER;
+ }
+
+ /* set clock waveform generator register */
+ p_twi->TWI_CWGR =
+ TWI_CWGR_CLDIV(c_lh_div) | TWI_CWGR_CHDIV(c_lh_div) |
+ TWI_CWGR_CKDIV(ckdiv);
+
+ return PASS;
+}
+
+/**
+ * \brief Test if a chip answers a given I2C address.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ * \param uc_slave_addr Address of the remote chip to search for.
+ *
+ * \return TWI_SUCCESS if a chip was found, error code otherwise.
+ */
+uint32_t twi_probe(Twi *p_twi, uint8_t uc_slave_addr)
+{
+ twi_packet_t packet;
+ uint8_t data = 0;
+
+ /* Data to send */
+ packet.buffer = &data;
+ /* Data length */
+ packet.length = 1;
+ /* Slave chip address */
+ packet.chip = (uint32_t) uc_slave_addr;
+ /* Internal chip address */
+ packet.addr[0] = 0;
+ /* Address length */
+ packet.addr_length = 0;
+
+ /* Perform a master write access */
+ return (twi_master_write(p_twi, &packet));
+}
+
+
+/**
+ * \internal
+ * \brief Construct the TWI module address register field
+ *
+ * The TWI module address register is sent out MSB first. And the size controls
+ * which byte is the MSB to start with.
+ *
+ * Please see the device datasheet for details on this.
+ */
+static uint32_t twi_mk_addr(const uint8_t *addr, int len)
+{
+ uint32_t val;
+
+ if (len == 0)
+ return 0;
+
+ val = addr[0];
+ if (len > 1) {
+ val <<= 8;
+ val |= addr[1];
+ }
+ if (len > 2) {
+ val <<= 8;
+ val |= addr[2];
+ }
+ return val;
+}
+
+/**
+ * \brief Read multiple bytes from a TWI compatible slave device.
+ *
+ * \note This function will NOT return until all data has been read or error occurs.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ * \param p_packet Packet information and data (see \ref twi_packet_t).
+ *
+ * \return TWI_SUCCESS if all bytes were read, error code otherwise.
+ */
+uint32_t twi_master_read(Twi *p_twi, twi_packet_t *p_packet)
+{
+ uint32_t status;
+ uint32_t cnt = p_packet->length;
+ uint8_t *buffer = p_packet->buffer;
+ uint8_t stop_sent = 0;
+ uint32_t timeout = TWI_TIMEOUT;;
+
+ /* Check argument */
+ if (cnt == 0) {
+ return TWI_INVALID_ARGUMENT;
+ }
+
+ /* Set read mode, slave address and 3 internal address byte lengths */
+ p_twi->TWI_MMR = 0;
+ p_twi->TWI_MMR = TWI_MMR_MREAD | TWI_MMR_DADR(p_packet->chip) |
+ ((p_packet->addr_length << TWI_MMR_IADRSZ_Pos) &
+ TWI_MMR_IADRSZ_Msk);
+
+ /* Set internal address for remote chip */
+ p_twi->TWI_IADR = 0;
+ p_twi->TWI_IADR = twi_mk_addr(p_packet->addr, p_packet->addr_length);
+
+ /* Send a START condition */
+ if (cnt == 1) {
+ p_twi->TWI_CR = TWI_CR_START | TWI_CR_STOP;
+ stop_sent = 1;
+ } else {
+ p_twi->TWI_CR = TWI_CR_START;
+ stop_sent = 0;
+ }
+
+ while (cnt > 0) {
+ status = p_twi->TWI_SR;
+ if (status & TWI_SR_NACK) {
+ return TWI_RECEIVE_NACK;
+ }
+
+ if (!timeout--) {
+ return TWI_ERROR_TIMEOUT;
+ }
+
+ /* Last byte ? */
+ if (cnt == 1 && !stop_sent) {
+ p_twi->TWI_CR = TWI_CR_STOP;
+ stop_sent = 1;
+ }
+
+ if (!(status & TWI_SR_RXRDY)) {
+ continue;
+ }
+ *buffer++ = p_twi->TWI_RHR;
+
+ cnt--;
+ timeout = TWI_TIMEOUT;
+ }
+
+ while (!(p_twi->TWI_SR & TWI_SR_TXCOMP)) {
+ }
+
+ p_twi->TWI_SR;
+
+ return TWI_SUCCESS;
+}
+
+/**
+ * \brief Write multiple bytes to a TWI compatible slave device.
+ *
+ * \note This function will NOT return until all data has been written or error occurred.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ * \param p_packet Packet information and data (see \ref twi_packet_t).
+ *
+ * \return TWI_SUCCESS if all bytes were written, error code otherwise.
+ */
+uint32_t twi_master_write(Twi *p_twi, twi_packet_t *p_packet)
+{
+ uint32_t status;
+ uint32_t cnt = p_packet->length;
+ uint8_t *buffer = p_packet->buffer;
+
+ /* Check argument */
+ if (cnt == 0) {
+ return TWI_INVALID_ARGUMENT;
+ }
+
+ /* Set write mode, slave address and 3 internal address byte lengths */
+ p_twi->TWI_MMR = 0;
+ p_twi->TWI_MMR = TWI_MMR_DADR(p_packet->chip) |
+ ((p_packet->addr_length << TWI_MMR_IADRSZ_Pos) &
+ TWI_MMR_IADRSZ_Msk);
+
+ /* Set internal address for remote chip */
+ p_twi->TWI_IADR = 0;
+ p_twi->TWI_IADR = twi_mk_addr(p_packet->addr, p_packet->addr_length);
+
+ /* Send all bytes */
+ while (cnt > 0) {
+ status = p_twi->TWI_SR;
+ if (status & TWI_SR_NACK) {
+ return TWI_RECEIVE_NACK;
+ }
+
+ if (!(status & TWI_SR_TXRDY)) {
+ continue;
+ }
+ p_twi->TWI_THR = *buffer++;
+
+ cnt--;
+ }
+
+ while (1) {
+ status = p_twi->TWI_SR;
+ if (status & TWI_SR_NACK) {
+ return TWI_RECEIVE_NACK;
+ }
+
+ if (status & TWI_SR_TXRDY) {
+ break;
+ }
+ }
+
+ p_twi->TWI_CR = TWI_CR_STOP;
+
+ while (!(p_twi->TWI_SR & TWI_SR_TXCOMP)) {
+ }
+
+ return TWI_SUCCESS;
+}
+
+/**
+ * \brief Enable TWI interrupts.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ * \param ul_sources Interrupts to be enabled.
+ */
+void twi_enable_interrupt(Twi *p_twi, uint32_t ul_sources)
+{
+ /* Enable the specified interrupts */
+ p_twi->TWI_IER = ul_sources;
+}
+
+/**
+ * \brief Disable TWI interrupts.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ * \param ul_sources Interrupts to be disabled.
+ */
+void twi_disable_interrupt(Twi *p_twi, uint32_t ul_sources)
+{
+ /* Disable the specified interrupts */
+ p_twi->TWI_IDR = ul_sources;
+ /* Dummy read */
+ p_twi->TWI_SR;
+}
+
+/**
+ * \brief Get TWI interrupt status.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ *
+ * \retval TWI interrupt status.
+ */
+uint32_t twi_get_interrupt_status(Twi *p_twi)
+{
+ return p_twi->TWI_SR;
+}
+
+/**
+ * \brief Read TWI interrupt mask.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ *
+ * \return The interrupt mask value.
+ */
+uint32_t twi_get_interrupt_mask(Twi *p_twi)
+{
+ return p_twi->TWI_IMR;
+}
+
+/**
+ * \brief Reads a byte from the TWI bus.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ *
+ * \return The byte read.
+ */
+uint8_t twi_read_byte(Twi *p_twi)
+{
+ return p_twi->TWI_RHR;
+}
+
+/**
+ * \brief Sends a byte of data to one of the TWI slaves on the bus.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ * \param byte The byte to send.
+ */
+void twi_write_byte(Twi *p_twi, uint8_t uc_byte)
+{
+ p_twi->TWI_THR = uc_byte;
+}
+
+/**
+ * \brief Enable TWI slave mode.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ */
+void twi_enable_slave_mode(Twi *p_twi)
+{
+ /* Set Master Disable bit and Slave Disable bit */
+ p_twi->TWI_CR = TWI_CR_MSDIS;
+ p_twi->TWI_CR = TWI_CR_SVDIS;
+
+ /* Set Slave Enable bit */
+ p_twi->TWI_CR = TWI_CR_SVEN;
+}
+
+/**
+ * \brief Disable TWI slave mode.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ */
+void twi_disable_slave_mode(Twi *p_twi)
+{
+ /* Set Slave Disable bit */
+ p_twi->TWI_CR = TWI_CR_SVDIS;
+}
+
+/**
+ * \brief Initialize TWI slave mode.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ * \param ul_device_addr Device address of the SAM slave device on the I2C bus.
+ */
+void twi_slave_init(Twi *p_twi, uint32_t ul_device_addr)
+{
+ /* Disable TWI interrupts */
+ p_twi->TWI_IDR = ~0UL;
+ p_twi->TWI_SR;
+
+ /* Reset TWI */
+ twi_reset(p_twi);
+
+ /* Set slave address in slave mode */
+ p_twi->TWI_SMR = TWI_SMR_SADR(ul_device_addr);
+
+ /* Enable slave mode */
+ twi_enable_slave_mode(p_twi);
+}
+
+/**
+ * \brief Set TWI slave address.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ * \param ul_device_addr Device address of the SAM slave device on the I2C bus.
+ */
+void twi_set_slave_addr(Twi *p_twi, uint32_t ul_device_addr)
+{
+ /* Set slave address */
+ p_twi->TWI_SMR = TWI_SMR_SADR(ul_device_addr);
+}
+
+/**
+ * \brief Read data from master.
+ *
+ * \note This function will NOT return until master sends a STOP condition.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ * \param p_data Pointer to the data buffer where data received will be stored.
+ *
+ * \return Number of bytes read.
+ */
+uint32_t twi_slave_read(Twi *p_twi, uint8_t *p_data)
+{
+ uint32_t status, cnt = 0;
+
+ do {
+ status = p_twi->TWI_SR;
+ if (status & TWI_SR_SVACC) {
+ if (!(status & TWI_SR_GACC) &&
+ ((status & (TWI_SR_SVREAD | TWI_SR_RXRDY))
+ == (TWI_SR_SVREAD | TWI_SR_RXRDY))) {
+ *p_data++ = (uint8_t) p_twi->TWI_RHR;
+ cnt++;
+ }
+ } else if ((status & (TWI_SR_EOSACC | TWI_SR_TXCOMP))
+ == (TWI_SR_EOSACC | TWI_SR_TXCOMP)) {
+ break;
+ }
+ } while (1);
+
+ return cnt;
+}
+
+/**
+ * \brief Write data to TWI bus.
+ *
+ * \note This function will NOT return until master sends a STOP condition.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ * \param p_data Pointer to the data buffer to be sent.
+ *
+ * \return Number of bytes written.
+ */
+uint32_t twi_slave_write(Twi *p_twi, uint8_t *p_data)
+{
+ uint32_t status, cnt = 0;
+
+ do {
+ status = p_twi->TWI_SR;
+ if (status & TWI_SR_SVACC) {
+ if (!(status & (TWI_SR_GACC | TWI_SR_SVREAD)) &&
+ (status & TWI_SR_TXRDY)) {
+ p_twi->TWI_THR = *p_data++;
+ cnt++;
+ }
+ } else if ((status & (TWI_SR_EOSACC | TWI_SR_TXCOMP))
+ == (TWI_SR_EOSACC | TWI_SR_TXCOMP)) {
+ break;
+ }
+ } while (1);
+
+ return cnt;
+}
+
+/**
+ * \brief Reset TWI.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ */
+void twi_reset(Twi *p_twi)
+{
+ /* Set SWRST bit to reset TWI peripheral */
+ p_twi->TWI_CR = TWI_CR_SWRST;
+ p_twi->TWI_RHR;
+}
+
+/**
+ * \brief Get TWI PDC base address.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ *
+ * \return TWI PDC registers base for PDC driver to access.
+ */
+Pdc *twi_get_pdc_base(Twi *p_twi)
+{
+ Pdc *p_pdc_base = NULL;
+#if !SAMG
+ if (p_twi == TWI0) {
+ p_pdc_base = PDC_TWI0;
+ } else
+#endif
+#ifdef PDC_TWI1
+ if (p_twi == TWI1) {
+ p_pdc_base = PDC_TWI1;
+ } else
+#endif
+#ifdef PDC_TWI2
+ if (p_twi == TWI2) {
+ p_pdc_base = PDC_TWI2;
+ } else
+#endif
+ {
+ Assert(false);
+ }
+
+ return p_pdc_base;
+}
+
+#if (SAM4E || SAM4C || SAMG || SAM4CP || SAM4CM)
+/**
+ * \brief Enables/Disables write protection mode.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ * \param flag ture for enable, false for disable.
+ */
+void twi_set_write_protection(Twi *p_twi, bool flag)
+{
+
+ p_twi->TWI_WPMR = (flag ? TWI_WPMR_WPEN : 0) | TWI_WP_KEY_VALUE;
+}
+
+/**
+ * \brief Read the write protection status.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ * \param p_status Pointer to save the status.
+ */
+void twi_read_write_protection_status(Twi *p_twi, uint32_t *p_status)
+{
+
+ *p_status = p_twi->TWI_WPSR;
+}
+#endif
+
+#if SAMG55
+/**
+ * \brief Set the prescaler, TLOW:SEXT, TLOW:MEXT and clock high max cycles for SMBUS mode.
+ *
+ * \param p_twi Base address of the TWI instance.
+ * \param ul_timing Parameter for prescaler, TLOW:SEXT, TLOW:MEXT and clock high max cycles.
+ */
+void twi_smbus_set_timing(Twi *p_twi, uint32_t ul_timing)
+{
+ p_twi->TWI_SMBTR = ul_timing;;
+}
+
+/**
+ * \brief Set length/direction/PEC for alternative command mode.
+ *
+ * \param p_twi Base address of the TWI instance.
+ * \param ul_alt_cmd Alternative command parameters.
+ */
+void twi_set_alternative_command(Twi *p_twi, uint32_t ul_alt_cmd)
+{
+ p_twi->TWI_ACR = ul_alt_cmd;;
+}
+
+/**
+ * \brief Set the filter for TWI.
+ *
+ * \param p_twi Base address of the TWI instance.
+ * \param ul_filter Filter value.
+ */
+void twi_set_filter(Twi *p_twi, uint32_t ul_filter)
+{
+ p_twi->TWI_FILTR = ul_filter;;
+}
+
+/**
+ * \brief A mask can be applied on the slave device address in slave mode in order to allow multiple
+ * address answer. For each bit of the MASK field set to one the corresponding SADR bit will be masked.
+ *
+ * \param p_twi Base address of the TWI instance.
+ * \param ul_mask Mask value.
+ */
+void twi_mask_slave_addr(Twi *p_twi, uint32_t ul_mask)
+{
+ p_twi->TWI_SMR |= TWI_SMR_MASK(ul_mask);
+}
+
+/**
+ * \brief Set sleepwalking match mode.
+ *
+ * \param p_twi Pointer to a TWI instance.
+ * \param ul_matching_addr1 Address 1 value.
+ * \param ul_matching_addr2 Address 2 value.
+ * \param ul_matching_addr3 Address 3 value.
+ * \param ul_matching_data Data value.
+ * \param flag1 ture for set, false for no.
+ * \param flag2 ture for set, false for no.
+ * \param flag3 ture for set, false for no.
+ * \param flag ture for set, false for no.
+ */
+void twi_set_sleepwalking(Twi *p_twi,
+ uint32_t ul_matching_addr1, bool flag1,
+ uint32_t ul_matching_addr2, bool flag2,
+ uint32_t ul_matching_addr3, bool flag3,
+ uint32_t ul_matching_data, bool flag)
+{
+ uint32_t temp = 0;
+
+ if (flag1) {
+ temp |= TWI_SWMR_SADR1(ul_matching_addr1);
+ }
+
+ if (flag2) {
+ temp |= TWI_SWMR_SADR2(ul_matching_addr2);
+ }
+
+ if (flag3) {
+ temp |= TWI_SWMR_SADR3(ul_matching_addr3);
+ }
+
+ if (flag) {
+ temp |= TWI_SWMR_DATAM(ul_matching_data);
+ }
+
+ p_twi->TWI_SWMR = temp;
+}
+#endif
+//@}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/twi/twi.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,446 @@
+/**
+ * \file
+ *
+ * \brief Two-Wire Interface (TWI) driver for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef TWI_H_INCLUDED
+#define TWI_H_INCLUDED
+
+#include "compiler.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /** Time-out value (number of attempts). */
+#define TWI_TIMEOUT 15000
+
+ /**
+ * \brief Return codes for TWI APIs.
+ * @{
+ */
+#define TWI_SUCCESS 0
+#define TWI_INVALID_ARGUMENT 1
+#define TWI_ARBITRATION_LOST 2
+#define TWI_NO_CHIP_FOUND 3
+#define TWI_RECEIVE_OVERRUN 4
+#define TWI_RECEIVE_NACK 5
+#define TWI_SEND_OVERRUN 6
+#define TWI_SEND_NACK 7
+#define TWI_BUSY 8
+#define TWI_ERROR_TIMEOUT 9
+ /**
+ * @}
+ */
+
+ /**
+ * \brief Input parameters when initializing the TWI module mode.
+ */
+ typedef struct twi_options {
+ //! MCK for TWI.
+ uint32_t master_clk;
+ //! The baud rate of the TWI bus.
+ uint32_t speed;
+ //! The desired address.
+ uint8_t chip;
+ //! SMBUS mode (set 1 to use SMBUS quick command, otherwise don't).
+ uint8_t smbus;
+ } twi_options_t;
+
+ /**
+ * \brief Information concerning the data transmission.
+ */
+ typedef struct twi_packet {
+ //! TWI address/commands to issue to the other chip (node).
+ uint8_t addr[3];
+ //! Length of the TWI data address segment (1-3 bytes).
+ uint32_t addr_length;
+ //! Where to find the data to be transferred.
+ void *buffer;
+ //! How many bytes do we want to transfer.
+ uint32_t length;
+ //! TWI chip address to communicate with.
+ uint8_t chip;
+ } twi_packet_t;
+
+#if SAMG55
+enum twi_source_clock {
+ TWI_SOURCE_PERIPH_CLK = TWI_CWGR_BRSRCCLK_PERIPH_CLK,
+ TWI_SOURCE_PCK_CLK = TWI_CWGR_BRSRCCLK_PMC_PCK,
+};
+#endif
+
+void twi_enable_master_mode(Twi *p_twi);
+void twi_disable_master_mode(Twi *p_twi);
+uint32_t twi_master_init(Twi *p_twi, const twi_options_t *p_opt);
+uint32_t twi_set_speed(Twi *p_twi, uint32_t ul_speed, uint32_t ul_mck);
+uint32_t twi_probe(Twi *p_twi, uint8_t uc_slave_addr);
+uint32_t twi_master_read(Twi *p_twi, twi_packet_t *p_packet);
+uint32_t twi_master_write(Twi *p_twi, twi_packet_t *p_packet);
+void twi_enable_interrupt(Twi *p_twi, uint32_t ul_sources);
+void twi_disable_interrupt(Twi *p_twi, uint32_t ul_sources);
+uint32_t twi_get_interrupt_status(Twi *p_twi);
+uint32_t twi_get_interrupt_mask(Twi *p_twi);
+uint8_t twi_read_byte(Twi *p_twi);
+void twi_write_byte(Twi *p_twi, uint8_t uc_byte);
+void twi_enable_slave_mode(Twi *p_twi);
+void twi_disable_slave_mode(Twi *p_twi);
+void twi_slave_init(Twi *p_twi, uint32_t ul_device_addr);
+void twi_set_slave_addr(Twi *p_twi, uint32_t ul_device_addr);
+uint32_t twi_slave_read(Twi *p_twi, uint8_t *p_data);
+uint32_t twi_slave_write(Twi *p_twi, uint8_t *p_data);
+void twi_reset(Twi *p_twi);
+Pdc *twi_get_pdc_base(Twi *p_twi);
+#if (SAM4E || SAM4C || SAMG || SAM4CP || SAM4CM)
+void twi_set_write_protection(Twi *p_twi, bool flag);
+void twi_read_write_protection_status(Twi *p_twi, uint32_t *p_status);
+#endif
+
+#if SAMG55
+void twi_smbus_set_timing(Twi *p_twi, uint32_t ul_timing);
+void twi_set_alternative_command(Twi *p_twi, uint32_t ul_alt_cmd);
+void twi_set_filter(Twi *p_twi, uint32_t ul_filter);
+void twi_mask_slave_addr(Twi *p_twi, uint32_t ul_mask);
+void twi_set_sleepwalking(Twi *p_twi,
+ uint32_t ul_matching_addr1, bool flag1,
+ uint32_t ul_matching_addr2, bool flag2,
+ uint32_t ul_matching_addr3, bool flag3,
+ uint32_t ul_matching_data, bool flag);
+
+/**
+ * \brief Enable high speed mode.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_enable_highspeed(Twi *p_twi)
+{
+ p_twi->TWI_CR = TWI_CR_HSEN;
+}
+
+/**
+ * \brief Disable high speed mode.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_disable_highspeed(Twi *p_twi)
+{
+ p_twi->TWI_CR = TWI_CR_HSDIS;
+}
+
+/**
+ * \brief Enable SMBus mode.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_enable_smbus(Twi *p_twi)
+{
+ p_twi->TWI_CR = TWI_CR_SMBEN;
+}
+
+/**
+ * \brief Disable SMBus mode.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_disable_smbus(Twi *p_twi)
+{
+ p_twi->TWI_CR = TWI_CR_SMBDIS;
+}
+
+/**
+ * \brief Enable packet error checking.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_enable_pec(Twi *p_twi)
+{
+ p_twi->TWI_CR = TWI_CR_PECEN;
+}
+
+/**
+ * \brief Disable packet error checking.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_disable_pec(Twi *p_twi)
+{
+ p_twi->TWI_CR = TWI_CR_PECDIS;
+}
+
+/**
+ * \brief Request a packet error checking.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_request_pec(Twi *p_twi)
+{
+ p_twi->TWI_CR = TWI_CR_PECRQ;
+}
+
+/**
+ * \brief If master mode is enabled, send a bus clear command.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_send_clear(Twi *p_twi)
+{
+ p_twi->TWI_CR = TWI_CR_CLEAR;
+}
+
+/**
+ * \brief Enable alternative command mode.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_enable_alternative_command(Twi *p_twi)
+{
+ p_twi->TWI_CR = TWI_CR_ACMEN;
+}
+
+/**
+ * \brief Enable alternative command mode.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_disable_alternative_command(Twi *p_twi)
+{
+ p_twi->TWI_CR = TWI_CR_ACMDIS;
+}
+
+/**
+ * \brief Clear the Transmit Holding Register and set TXRDY, TXCOMP flags.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_thr_clear(Twi *p_twi)
+{
+ p_twi->TWI_CR = TWI_CR_THRCLR;
+}
+
+/**
+ * \brief Clear the TWI FSM lock.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_lock_clear(Twi *p_twi)
+{
+ p_twi->TWI_CR = TWI_CR_LOCKCLR;
+}
+
+/**
+ * \brief Normal value to be returned in the ACK cycle of the data phase in slave receiver mode.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_disable_slave_nack(Twi *p_twi)
+{
+ p_twi->TWI_SMR &= ~TWI_SMR_NACKEN;
+}
+
+/**
+ * \brief NACK value to be returned in the ACK cycle of the data phase in slave receiver mode.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_enable_slave_nack(Twi *p_twi)
+{
+ p_twi->TWI_SMR |= TWI_SMR_NACKEN;
+}
+
+/**
+ * \brief Acknowledge of the SMBus Default Address disabled.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_disable_slave_default_addr(Twi *p_twi)
+{
+ p_twi->TWI_SMR &= ~TWI_SMR_SMDA;
+}
+
+/**
+ * \brief Acknowledge of the SMBus Default Address enabled.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_enable_slave_default_addr(Twi *p_twi)
+{
+ p_twi->TWI_SMR |= TWI_SMR_SMDA;
+}
+
+/**
+ * \brief Acknowledge of the SMBus Host Header disabled.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_disable_smbus_host_header(Twi *p_twi)
+{
+ p_twi->TWI_SMR &= ~TWI_SMR_SMHH;
+}
+
+/**
+ * \brief Acknowledge of the SMBus Host Header enabled.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_enable_smbus_host_header(Twi *p_twi)
+{
+ p_twi->TWI_SMR |= TWI_SMR_SMHH;
+}
+
+/**
+ * \brief Clock stretching disabled in slave mode, OVRE and UNRE will indicate overrun and underrun.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_disable_clock_wait_state(Twi *p_twi)
+{
+ p_twi->TWI_SMR |= TWI_SMR_SCLWSDIS;
+}
+
+/**
+ * \brief Clear clock wait state disable mode.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_clear_disable_clock_wait_state(Twi *p_twi)
+{
+ p_twi->TWI_SMR &= ~TWI_SMR_SCLWSDIS;
+}
+
+/**
+ * \brief Slave Address 1 matching disabled.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_disable_slave_addr1_matching(Twi *p_twi)
+{
+ p_twi->TWI_SMR &= ~TWI_SMR_SADR1EN;
+}
+
+/**
+ * \brief Slave Address 1 matching enabled.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_enable_slave_addr1_matching(Twi *p_twi)
+{
+ p_twi->TWI_SMR |= TWI_SMR_SADR1EN;
+}
+
+/**
+ * \brief Slave Address 2 matching disabled.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_disable_slave_addr2_matching(Twi *p_twi)
+{
+ p_twi->TWI_SMR &= ~TWI_SMR_SADR2EN;
+}
+
+/**
+ * \brief Slave Address 2 matching enabled.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_enable_slave_addr2_matching(Twi *p_twi)
+{
+ p_twi->TWI_SMR |= TWI_SMR_SADR2EN;
+}
+
+/**
+ * \brief Slave Address 3 matching disabled.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_disable_slave_addr3_matching(Twi *p_twi)
+{
+ p_twi->TWI_SMR &= ~TWI_SMR_SADR3EN;
+}
+
+/**
+ * \brief Slave Address 3 matching enabled.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_enable_slave_addr3_matching(Twi *p_twi)
+{
+ p_twi->TWI_SMR |= TWI_SMR_SADR3EN;
+}
+
+/**
+ * \brief First received data matching disabled.
+ *
+ * \param p_twi Base address of the TWI instance.
+ */
+static inline void twi_disable_slave_data_matching(Twi *p_twi)
+{
+ p_twi->TWI_SMR &= ~TWI_SMR_DATAMEN;
+}
+
+/**
+ * \brief Select the souce clock for the bit rate generation.
+ *
+ * \param p_twi Base address of the TWI instance.
+ * \param src_clk Source clock.
+ */
+static inline void twi_select_source_clock(Twi *p_twi, enum twi_source_clock src_clk)
+{
+ p_twi->TWI_CWGR &= ~TWI_CWGR_BRSRCCLK;
+ p_twi->TWI_CWGR |= src_clk;
+}
+#endif
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* TWI_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/usart/usart.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,2102 @@
+/**
+ * \file
+ *
+ * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver
+ * for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "usart.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /**
+ * \defgroup sam_drivers_usart_group Universal Synchronous Asynchronous
+ * Receiver Transmitter (USART)
+ *
+ * The Universal Synchronous Asynchronous Receiver Transceiver (USART)
+ * provides one full duplex universal synchronous asynchronous serial link.
+ * Data frame format is widely programmable (data length, parity, number of
+ * stop bits) to support a maximum of standards. The receiver implements
+ * parity error, framing error and overrun error detection. The receiver
+ * time-out enables handling variable-length frames and the transmitter
+ * timeguard facilitates communications with slow remote devices. Multidrop
+ * communications are also supported through address bit handling in reception
+ * and transmission. The driver supports the following modes:
+ * RS232, RS485, SPI, IrDA, ISO7816, MODEM, Hardware handshaking and LIN.
+ *
+ * @{
+ */
+
+ /* The write protect key value. */
+#ifndef US_WPMR_WPKEY_PASSWD
+#define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(0x555341U)
+#endif
+
+#ifndef US_WPMR_WPKEY_PASSWD
+# define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(US_WPKEY_VALUE)
+#endif
+
+ /* The CD value scope programmed in MR register. */
+#define MIN_CD_VALUE 0x01
+#define MIN_CD_VALUE_SPI 0x04
+#define MAX_CD_VALUE US_BRGR_CD_Msk
+
+ /* The receiver sampling divide of baudrate clock. */
+#define HIGH_FRQ_SAMPLE_DIV 16
+#define LOW_FRQ_SAMPLE_DIV 8
+
+ /* Max transmitter timeguard. */
+#define MAX_TRAN_GUARD_TIME US_TTGR_TG_Msk
+
+ /* The non-existent parity error number. */
+#define USART_PARITY_ERROR 5
+
+ /* ISO7816 protocol type. */
+#define ISO7816_T_0 0
+#define ISO7816_T_1 1
+
+ /**
+ * \brief Calculate a clock divider(CD) and a fractional part (FP) for the
+ * USART asynchronous modes to generate a baudrate as close as possible to
+ * the baudrate set point.
+ *
+ * \note Baud rate calculation: Baudrate = ul_mck/(Over * (CD + FP/8))
+ * (Over being 16 or 8). The maximal oversampling is selected if it allows to
+ * generate a baudrate close to the set point.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param baudrate Baud rate set point.
+ * \param ul_mck USART module input clock frequency.
+ *
+ * \retval 0 Baud rate is successfully initialized.
+ * \retval 1 Baud rate set point is out of range for the given input clock
+ * frequency.
+ */
+ uint32_t usart_set_async_baudrate(Usart *p_usart,
+ uint32_t baudrate, uint32_t ul_mck)
+{
+ uint32_t over;
+ uint32_t cd_fp;
+ uint32_t cd;
+ uint32_t fp;
+
+ /* Calculate the receiver sampling divide of baudrate clock. */
+ if (ul_mck >= HIGH_FRQ_SAMPLE_DIV * baudrate) {
+ over = HIGH_FRQ_SAMPLE_DIV;
+ } else {
+ over = LOW_FRQ_SAMPLE_DIV;
+ }
+
+ /* Calculate clock divider according to the fraction calculated formula. */
+ cd_fp = (8 * ul_mck + (over * baudrate) / 2) / (over * baudrate);
+ cd = cd_fp >> 3;
+ fp = cd_fp & 0x07;
+ if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {
+ return 1;
+ }
+
+ /* Configure the OVER bit in MR register. */
+ if (over == 8) {
+ p_usart->US_MR |= US_MR_OVER;
+ }
+
+ /* Configure the baudrate generate register. */
+ p_usart->US_BRGR = (cd << US_BRGR_CD_Pos) | (fp << US_BRGR_FP_Pos);
+
+ return 0;
+}
+
+/**
+ * \brief Calculate a clock divider for the USART synchronous master modes
+ * to generate a baudrate as close as possible to the baudrate set point.
+ *
+ * \note Synchronous baudrate calculation: baudrate = ul_mck / cd
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param baudrate Baud rate set point.
+ * \param ul_mck USART module input clock frequency.
+ *
+ * \retval 0 Baud rate is successfully initialized.
+ * \retval 1 Baud rate set point is out of range for the given input clock
+ * frequency.
+ */
+static uint32_t usart_set_sync_master_baudrate(Usart *p_usart,
+ uint32_t baudrate, uint32_t ul_mck)
+{
+ uint32_t cd;
+
+ /* Calculate clock divider according to the formula in synchronous mode. */
+ cd = (ul_mck + baudrate / 2) / baudrate;
+
+ if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {
+ return 1;
+ }
+
+ /* Configure the baudrate generate register. */
+ p_usart->US_BRGR = cd << US_BRGR_CD_Pos;
+
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) |
+ US_MR_USCLKS_MCK | US_MR_SYNC;
+ return 0;
+}
+
+/**
+ * \brief Select the SCK pin as the source of baud rate for the USART
+ * synchronous slave modes.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+static void usart_set_sync_slave_baudrate(Usart *p_usart)
+{
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) |
+ US_MR_USCLKS_SCK | US_MR_SYNC;
+}
+
+/**
+ * \brief Calculate a clock divider (\e CD) for the USART SPI master mode to
+ * generate a baud rate as close as possible to the baud rate set point.
+ *
+ * \note Baud rate calculation:
+ * \f$ Baudrate = \frac{SelectedClock}{CD} \f$.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param baudrate Baud rate set point.
+ * \param ul_mck USART module input clock frequency.
+ *
+ * \retval 0 Baud rate is successfully initialized.
+ * \retval 1 Baud rate set point is out of range for the given input clock
+ * frequency.
+ */
+static uint32_t usart_set_spi_master_baudrate(Usart *p_usart,
+ uint32_t baudrate, uint32_t ul_mck)
+{
+ uint32_t cd;
+
+ /* Calculate the clock divider according to the formula in SPI mode. */
+ cd = (ul_mck + baudrate / 2) / baudrate;
+
+ if (cd < MIN_CD_VALUE_SPI || cd > MAX_CD_VALUE) {
+ return 1;
+ }
+
+ p_usart->US_BRGR = cd << US_BRGR_CD_Pos;
+
+ return 0;
+}
+
+/**
+ * \brief Select the SCK pin as the source of baudrate for the USART SPI slave
+ * mode.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+static void usart_set_spi_slave_baudrate(Usart *p_usart)
+{
+ p_usart->US_MR &= ~US_MR_USCLKS_Msk;
+ p_usart->US_MR |= US_MR_USCLKS_SCK;
+}
+
+/**
+ * \brief Reset the USART and disable TX and RX.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_reset(Usart *p_usart)
+{
+ /* Disable the Write Protect. */
+ usart_disable_writeprotect(p_usart);
+
+ /* Reset registers that could cause unpredictable behavior after reset. */
+ p_usart->US_MR = 0;
+ p_usart->US_RTOR = 0;
+ p_usart->US_TTGR = 0;
+
+ /* Disable TX and RX. */
+ usart_reset_tx(p_usart);
+ usart_reset_rx(p_usart);
+ /* Reset status bits. */
+ usart_reset_status(p_usart);
+ /* Turn off RTS and DTR if exist. */
+ usart_drive_RTS_pin_high(p_usart);
+#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E)
+ usart_drive_DTR_pin_high(p_usart);
+#endif
+}
+
+/**
+ * \brief Configure USART to work in RS232 mode.
+ *
+ * \note By default, the transmitter and receiver aren't enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.
+ * \param ul_mck USART module input clock frequency.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_init_rs232(Usart *p_usart,
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
+{
+ static uint32_t ul_reg_val;
+
+ /* Reset the USART and shut down TX and RX. */
+ usart_reset(p_usart);
+
+ ul_reg_val = 0;
+ /* Check whether the input values are legal. */
+ if (!p_usart_opt || usart_set_async_baudrate(p_usart,
+ p_usart_opt->baudrate, ul_mck)) {
+ return 1;
+ }
+
+ /* Configure the USART option. */
+ ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |
+ p_usart_opt->channel_mode | p_usart_opt->stop_bits;
+
+ /* Configure the USART mode as normal mode. */
+ ul_reg_val |= US_MR_USART_MODE_NORMAL;
+
+ p_usart->US_MR |= ul_reg_val;
+
+ return 0;
+}
+
+/**
+ * \brief Configure USART to work in hardware handshaking mode.
+ *
+ * \note By default, the transmitter and receiver aren't enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.
+ * \param ul_mck USART module input clock frequency.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_init_hw_handshaking(Usart *p_usart,
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
+{
+ /* Initialize the USART as standard RS232. */
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
+ return 1;
+ }
+
+ /* Set hardware handshaking mode. */
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
+ US_MR_USART_MODE_HW_HANDSHAKING;
+
+ return 0;
+}
+
+#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E)
+
+/**
+ * \brief Configure USART to work in modem mode.
+ *
+ * \note By default, the transmitter and receiver aren't enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.
+ * \param ul_mck USART module input clock frequency.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_init_modem(Usart *p_usart,
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
+{
+ /*
+ * SAM3S, SAM4S and SAM4E series support MODEM mode only on USART1,
+ * SAM3U and SAM4L series support MODEM mode only on USART0.
+ */
+#if (SAM3S || SAM4S || SAM4E)
+#ifdef USART1
+ if (p_usart != USART1) {
+ return 1;
+ }
+#endif
+#elif (SAM3U || SAM4L)
+ if (p_usart != USART0) {
+ return 1;
+ }
+#endif
+
+ /* Initialize the USART as standard RS232. */
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
+ return 1;
+ }
+
+ /* Set MODEM mode. */
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
+ US_MR_USART_MODE_MODEM;
+
+ return 0;
+}
+#endif
+
+/**
+ * \brief Configure USART to work in SYNC mode and act as a master.
+ *
+ * \note By default, the transmitter and receiver aren't enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.
+ * \param ul_mck USART module input clock frequency.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_init_sync_master(Usart *p_usart,
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
+{
+ static uint32_t ul_reg_val;
+
+ /* Reset the USART and shut down TX and RX. */
+ usart_reset(p_usart);
+
+ ul_reg_val = 0;
+ /* Check whether the input values are legal. */
+ if (!p_usart_opt || usart_set_sync_master_baudrate(p_usart,
+ p_usart_opt->baudrate, ul_mck)) {
+ return 1;
+ }
+
+ /* Configure the USART option. */
+ ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |
+ p_usart_opt->channel_mode | p_usart_opt->stop_bits;
+
+ /* Set normal mode and output clock as synchronous master. */
+ ul_reg_val |= US_MR_USART_MODE_NORMAL | US_MR_CLKO;
+ p_usart->US_MR |= ul_reg_val;
+
+ return 0;
+}
+
+/**
+ * \brief Configure USART to work in SYNC mode and act as a slave.
+ *
+ * \note By default, the transmitter and receiver aren't enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_init_sync_slave(Usart *p_usart,
+ const sam_usart_opt_t *p_usart_opt)
+{
+ static uint32_t ul_reg_val;
+
+ /* Reset the USART and shut down TX and RX. */
+ usart_reset(p_usart);
+
+ ul_reg_val = 0;
+ usart_set_sync_slave_baudrate(p_usart);
+
+ /* Check whether the input values are legal. */
+ if (!p_usart_opt) {
+ return 1;
+ }
+
+ /* Configure the USART option. */
+ ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |
+ p_usart_opt->channel_mode | p_usart_opt->stop_bits;
+
+ /* Set normal mode. */
+ ul_reg_val |= US_MR_USART_MODE_NORMAL;
+ p_usart->US_MR |= ul_reg_val;
+
+ return 0;
+}
+
+/**
+ * \brief Configure USART to work in RS485 mode.
+ *
+ * \note By default, the transmitter and receiver aren't enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.
+ * \param ul_mck USART module input clock frequency.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_init_rs485(Usart *p_usart,
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
+{
+ /* Initialize the USART as standard RS232. */
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
+ return 1;
+ }
+
+ /* Set RS485 mode. */
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
+ US_MR_USART_MODE_RS485;
+
+ return 0;
+}
+
+#if (!SAMG55 && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
+/**
+ * \brief Configure USART to work in IrDA mode.
+ *
+ * \note By default, the transmitter and receiver aren't enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.
+ * \param ul_mck USART module input clock frequency.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_init_irda(Usart *p_usart,
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)
+{
+ /* Initialize the USART as standard RS232. */
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {
+ return 1;
+ }
+
+ /* Set IrDA filter. */
+ p_usart->US_IF = p_usart_opt->irda_filter;
+
+ /* Set IrDA mode. */
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
+ US_MR_USART_MODE_IRDA;
+
+ return 0;
+}
+#endif
+
+#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
+/**
+ * \brief Calculate a clock divider (\e CD) for the USART ISO7816 mode to
+ * generate an ISO7816 clock as close as possible to the clock set point.
+ *
+ * \note ISO7816 clock calculation: Clock = ul_mck / cd
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param clock ISO7816 clock set point.
+ * \param ul_mck USART module input clock frequency.
+ *
+ * \retval 0 ISO7816 clock is successfully initialized.
+ * \retval 1 ISO7816 clock set point is out of range for the given input clock
+ * frequency.
+ */
+static uint32_t usart_set_iso7816_clock(Usart *p_usart,
+ uint32_t clock, uint32_t ul_mck)
+{
+ uint32_t cd;
+
+ /* Calculate clock divider according to the formula in ISO7816 mode. */
+ cd = (ul_mck + clock / 2) / clock;
+
+ if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {
+ return 1;
+ }
+
+ p_usart->US_MR = (p_usart->US_MR & ~(US_MR_USCLKS_Msk | US_MR_SYNC |
+ US_MR_OVER)) | US_MR_USCLKS_MCK | US_MR_CLKO;
+
+ /* Configure the baudrate generate register. */
+ p_usart->US_BRGR = cd << US_BRGR_CD_Pos;
+
+ return 0;
+}
+
+/**
+ * \brief Configure USART to work in ISO7816 mode.
+ *
+ * \note By default, the transmitter and receiver aren't enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.
+ * \param ul_mck USART module input clock frequency.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_init_iso7816(Usart *p_usart,
+ const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck)
+{
+ static uint32_t ul_reg_val;
+
+ /* Reset the USART and shut down TX and RX. */
+ usart_reset(p_usart);
+
+ ul_reg_val = 0;
+
+ /* Check whether the input values are legal. */
+ if (!p_usart_opt || ((p_usart_opt->parity_type != US_MR_PAR_EVEN) &&
+ (p_usart_opt->parity_type != US_MR_PAR_ODD))) {
+ return 1;
+ }
+
+ if (p_usart_opt->protocol_type == ISO7816_T_0) {
+ ul_reg_val |= US_MR_USART_MODE_IS07816_T_0 | US_MR_NBSTOP_2_BIT |
+ (p_usart_opt->max_iterations << US_MR_MAX_ITERATION_Pos);
+
+ if (p_usart_opt->bit_order) {
+ ul_reg_val |= US_MR_MSBF;
+ }
+ } else if (p_usart_opt->protocol_type == ISO7816_T_1) {
+ /*
+ * Only LSBF is used in the T=1 protocol, and max_iterations field
+ * is only used in T=0 mode.
+ */
+ if (p_usart_opt->bit_order || p_usart_opt->max_iterations) {
+ return 1;
+ }
+
+ /* Set USART mode to ISO7816, T=1, and always uses 1 stop bit. */
+ ul_reg_val |= US_MR_USART_MODE_IS07816_T_1 | US_MR_NBSTOP_1_BIT;
+ } else {
+ return 1;
+ }
+
+ /* Set up the baudrate. */
+ if (usart_set_iso7816_clock(p_usart, p_usart_opt->iso7816_hz, ul_mck)) {
+ return 1;
+ }
+
+ /* Set FIDI register: bit rate = iso7816_hz / fidi_ratio. */
+ p_usart->US_FIDI = p_usart_opt->fidi_ratio;
+
+ /* Set ISO7816 parity type in the MODE register. */
+ ul_reg_val |= p_usart_opt->parity_type;
+
+ if (p_usart_opt->inhibit_nack) {
+ ul_reg_val |= US_MR_INACK;
+ }
+ if (p_usart_opt->dis_suc_nack) {
+ ul_reg_val |= US_MR_DSNACK;
+ }
+
+ p_usart->US_MR |= ul_reg_val;
+
+ return 0;
+}
+
+/**
+ * \brief Reset the ITERATION in US_CSR when the ISO7816 mode is enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_reset_iterations(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_RSTIT;
+}
+
+/**
+ * \brief Reset NACK in US_CSR.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_reset_nack(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_RSTNACK;
+}
+
+/**
+ * \brief Check if one receive buffer is filled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \retval 1 Receive is complete.
+ * \retval 0 Receive is still pending.
+ */
+uint32_t usart_is_rx_buf_end(Usart *p_usart)
+{
+ return (p_usart->US_CSR & US_CSR_ENDRX) > 0;
+}
+
+/**
+ * \brief Check if one transmit buffer is empty.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \retval 1 Transmit is complete.
+ * \retval 0 Transmit is still pending.
+ */
+uint32_t usart_is_tx_buf_end(Usart *p_usart)
+{
+ return (p_usart->US_CSR & US_CSR_ENDTX) > 0;
+}
+
+/**
+ * \brief Check if both receive buffers are full.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \retval 1 Receive buffers are full.
+ * \retval 0 Receive buffers are not full.
+ */
+uint32_t usart_is_rx_buf_full(Usart *p_usart)
+{
+ return (p_usart->US_CSR & US_CSR_RXBUFF) > 0;
+}
+
+/**
+ * \brief Check if both transmit buffers are empty.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \retval 1 Transmit buffers are empty.
+ * \retval 0 Transmit buffers are not empty.
+ */
+uint32_t usart_is_tx_buf_empty(Usart *p_usart)
+{
+ return (p_usart->US_CSR & US_CSR_TXBUFE) > 0;
+}
+
+/**
+ * \brief Get the total number of errors that occur during an ISO7816 transfer.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \return The number of errors that occurred.
+ */
+uint8_t usart_get_error_number(Usart *p_usart)
+{
+ return (p_usart->US_NER & US_NER_NB_ERRORS_Msk);
+}
+
+#endif
+
+/**
+ * \brief Configure USART to work in SPI mode and act as a master.
+ *
+ * \note By default, the transmitter and receiver aren't enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.
+ * \param ul_mck USART module input clock frequency.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_init_spi_master(Usart *p_usart,
+ const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck)
+{
+ static uint32_t ul_reg_val;
+
+ /* Reset the USART and shut down TX and RX. */
+ usart_reset(p_usart);
+
+ ul_reg_val = 0;
+ /* Check whether the input values are legal. */
+ if (!p_usart_opt || (p_usart_opt->spi_mode > SPI_MODE_3) ||
+ usart_set_spi_master_baudrate(p_usart, p_usart_opt->baudrate,
+ ul_mck)) {
+ return 1;
+ }
+
+ /* Configure the character length bit in MR register. */
+ ul_reg_val |= p_usart_opt->char_length;
+
+ /* Set SPI master mode and channel mode. */
+ ul_reg_val |= US_MR_USART_MODE_SPI_MASTER | US_MR_CLKO |
+ p_usart_opt->channel_mode;
+
+ switch (p_usart_opt->spi_mode) {
+ case SPI_MODE_0:
+ ul_reg_val |= US_MR_CPHA;
+ ul_reg_val &= ~US_MR_CPOL;
+ break;
+
+ case SPI_MODE_1:
+ ul_reg_val &= ~US_MR_CPHA;
+ ul_reg_val &= ~US_MR_CPOL;
+ break;
+
+ case SPI_MODE_2:
+ ul_reg_val |= US_MR_CPHA;
+ ul_reg_val |= US_MR_CPOL;
+ break;
+
+ case SPI_MODE_3:
+ ul_reg_val &= ~US_MR_CPHA;
+ ul_reg_val |= US_MR_CPOL;
+ break;
+
+ default:
+ break;
+ }
+
+ p_usart->US_MR |= ul_reg_val;
+
+ return 0;
+}
+
+/**
+ * \brief Configure USART to work in SPI mode and act as a slave.
+ *
+ * \note By default, the transmitter and receiver aren't enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_init_spi_slave(Usart *p_usart,
+ const usart_spi_opt_t *p_usart_opt)
+{
+ static uint32_t ul_reg_val;
+
+ /* Reset the USART and shut down TX and RX. */
+ usart_reset(p_usart);
+
+ ul_reg_val = 0;
+ usart_set_spi_slave_baudrate(p_usart);
+
+ /* Check whether the input values are legal. */
+ if (!p_usart_opt || p_usart_opt->spi_mode > SPI_MODE_3) {
+ return 1;
+ }
+
+ /* Configure the character length bit in MR register. */
+ ul_reg_val |= p_usart_opt->char_length;
+
+ /* Set SPI slave mode and channel mode. */
+ ul_reg_val |= US_MR_USART_MODE_SPI_SLAVE | p_usart_opt->channel_mode;
+
+ switch (p_usart_opt->spi_mode) {
+ case SPI_MODE_0:
+ ul_reg_val |= US_MR_CPHA;
+ ul_reg_val &= ~US_MR_CPOL;
+ break;
+
+ case SPI_MODE_1:
+ ul_reg_val &= ~US_MR_CPHA;
+ ul_reg_val &= ~US_MR_CPOL;
+ break;
+
+ case SPI_MODE_2:
+ ul_reg_val |= US_MR_CPHA;
+ ul_reg_val |= US_MR_CPOL;
+ break;
+
+ case SPI_MODE_3:
+ ul_reg_val |= US_MR_CPOL;
+ ul_reg_val &= ~US_MR_CPHA;
+ break;
+
+ default:
+ break;
+ }
+
+ p_usart->US_MR |= ul_reg_val;
+
+ return 0;
+}
+
+#if (SAM3XA || SAM4L || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
+
+/**
+ * \brief Configure USART to work in LIN mode and act as a LIN master.
+ *
+ * \note By default, the transmitter and receiver aren't enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param ul_baudrate Baudrate to be used.
+ * \param ul_mck USART module input clock frequency.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_init_lin_master(Usart *p_usart,uint32_t ul_baudrate,
+ uint32_t ul_mck)
+{
+ /* Reset the USART and shut down TX and RX. */
+ usart_reset(p_usart);
+
+ /* Set up the baudrate. */
+ if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) {
+ return 1;
+ }
+
+ /* Set LIN master mode. */
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
+ US_MR_USART_MODE_LIN_MASTER;
+
+ usart_enable_rx(p_usart);
+ usart_enable_tx(p_usart);
+
+ return 0;
+}
+
+/**
+ * \brief Configure USART to work in LIN mode and act as a LIN slave.
+ *
+ * \note By default, the transmitter and receiver aren't enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param ul_baudrate Baudrate to be used.
+ * \param ul_mck USART module input clock frequency.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate,
+ uint32_t ul_mck)
+{
+ /* Reset the USART and shut down TX and RX. */
+ usart_reset(p_usart);
+
+ usart_enable_rx(p_usart);
+ usart_enable_tx(p_usart);
+
+ /* Set LIN slave mode. */
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
+ US_MR_USART_MODE_LIN_SLAVE;
+
+ /* Set up the baudrate. */
+ if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) {
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * \brief Abort the current LIN transmission.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_lin_abort_tx(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_LINABT;
+}
+
+/**
+ * \brief Send a wakeup signal on the LIN bus.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_lin_send_wakeup_signal(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_LINWKUP;
+}
+
+/**
+ * \brief Configure the LIN node action, which should be one of PUBLISH,
+ * SUBSCRIBE or IGNORE.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_action 0 for PUBLISH, 1 for SUBSCRIBE, 2 for IGNORE.
+ */
+void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action)
+{
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_NACT_Msk) |
+ (uc_action << US_LINMR_NACT_Pos);
+}
+
+/**
+ * \brief Disable the parity check during the LIN communication.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_lin_disable_parity(Usart *p_usart)
+{
+ p_usart->US_LINMR |= US_LINMR_PARDIS;
+}
+
+/**
+ * \brief Enable the parity check during the LIN communication.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_lin_enable_parity(Usart *p_usart)
+{
+ p_usart->US_LINMR &= ~US_LINMR_PARDIS;
+}
+
+/**
+ * \brief Disable the checksum during the LIN communication.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_lin_disable_checksum(Usart *p_usart)
+{
+ p_usart->US_LINMR |= US_LINMR_CHKDIS;
+}
+
+/**
+ * \brief Enable the checksum during the LIN communication.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_lin_enable_checksum(Usart *p_usart)
+{
+ p_usart->US_LINMR &= ~US_LINMR_CHKDIS;
+}
+
+/**
+ * \brief Configure the checksum type during the LIN communication.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_type 0 for LIN 2.0 Enhanced checksum or 1 for LIN 1.3 Classic
+ * checksum.
+ */
+void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type)
+{
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_CHKTYP) |
+ (uc_type << 4);
+}
+
+/**
+ * \brief Configure the data length mode during the LIN communication.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_mode Indicate the data length type: 0 if the data length is
+ * defined by the DLC of LIN mode register or 1 if the data length is defined
+ * by the bit 5 and 6 of the identifier.
+ */
+void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode)
+{
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLM) |
+ (uc_mode << 5);
+}
+
+/**
+ * \brief Disable the frame slot mode during the LIN communication.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_lin_disable_frame_slot(Usart *p_usart)
+{
+ p_usart->US_LINMR |= US_LINMR_FSDIS;
+}
+
+/**
+ * \brief Enable the frame slot mode during the LIN communication.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_lin_enable_frame_slot(Usart *p_usart)
+{
+ p_usart->US_LINMR &= ~US_LINMR_FSDIS;
+}
+
+/**
+ * \brief Configure the wakeup signal type during the LIN communication.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_type Indicate the checksum type: 0 if the wakeup signal is a
+ * LIN 2.0 wakeup signal; 1 if the wakeup signal is a LIN 1.3 wakeup signal.
+ */
+void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type)
+{
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_WKUPTYP) |
+ (uc_type << 7);
+}
+
+/**
+ * \brief Configure the response data length if the data length is defined by
+ * the DLC field during the LIN communication.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_len Indicate the response data length.
+ */
+void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len)
+{
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLC_Msk) |
+ ((uc_len - 1) << US_LINMR_DLC_Pos);
+}
+
+/**
+ * \brief The LIN mode register is not written by the PDC.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_lin_disable_pdc_mode(Usart *p_usart)
+{
+ p_usart->US_LINMR &= ~US_LINMR_PDCM;
+}
+
+/**
+ * \brief The LIN mode register (except this flag) is written by the PDC.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_lin_enable_pdc_mode(Usart *p_usart)
+{
+ p_usart->US_LINMR |= US_LINMR_PDCM;
+}
+
+/**
+ * \brief Configure the LIN identifier when USART works in LIN master mode.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_id The identifier to be transmitted.
+ */
+void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id)
+{
+ p_usart->US_LINIR = (p_usart->US_LINIR & ~US_LINIR_IDCHR_Msk) |
+ US_LINIR_IDCHR(uc_id);
+}
+
+/**
+ * \brief Read the identifier when USART works in LIN mode.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \return The last identifier received in LIN slave mode or the last
+ * identifier transmitted in LIN master mode.
+ */
+uint8_t usart_lin_read_identifier(Usart *p_usart)
+{
+ return (p_usart->US_LINIR & US_LINIR_IDCHR_Msk);
+}
+
+/**
+ * \brief Get data length.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \return Data length.
+ */
+uint8_t usart_lin_get_data_length(Usart *usart)
+{
+ if (usart->US_LINMR & US_LINMR_DLM) {
+ uint8_t data_length = 1 << ((usart->US_LINIR >>
+ (US_LINIR_IDCHR_Pos + 4)) & 0x03);
+ return data_length;
+ } else {
+ return ((usart->US_LINMR & US_LINMR_DLC_Msk) >> US_LINMR_DLC_Pos) + 1;
+ }
+}
+
+#endif
+
+#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
+/**
+ * \brief Get identifier send status.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \return
+ * 0: No LIN identifier has been sent since the last RSTSTA.
+ * 1: :At least one LIN identifier has been sent since the last RSTSTA.
+ */
+uint8_t usart_lin_identifier_send_complete(Usart *usart)
+{
+ return (usart->US_CSR & US_CSR_LINID) > 0;
+}
+
+/**
+ * \brief Get identifier received status.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \return
+ * 0: No LIN identifier has been reveived since the last RSTSTA.
+ * 1: At least one LIN identifier has been received since the last RSTSTA.
+ */
+uint8_t usart_lin_identifier_reception_complete(Usart *usart)
+{
+ return (usart->US_CSR & US_CSR_LINID) > 0;
+}
+
+/**
+ * \brief Get transmission status.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \return
+ * 0: The USART is idle or a LIN transfer is ongoing.
+ * 1: A LIN transfer has been completed since the last RSTSTA.
+ */
+uint8_t usart_lin_tx_complete(Usart *usart)
+{
+ return (usart->US_CSR & US_CSR_LINTC) > 0;
+}
+
+/**
+ * \brief Configure USART to work in LON mode.
+ *
+ * \note By default, the transmitter and receiver aren't enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param ul_baudrate Baudrate to be used.
+ * \param ul_mck USART module input clock frequency.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_init_lon(Usart *p_usart,uint32_t ul_baudrate,
+ uint32_t ul_mck)
+{
+ /* Reset the USART and shut down TX and RX. */
+ usart_reset(p_usart);
+
+ /* Set up the baudrate. */
+ if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) {
+ return 1;
+ }
+
+ /* Set LIN master mode. */
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |
+ US_MR_USART_MODE_LON;
+
+ usart_enable_rx(p_usart);
+ usart_enable_tx(p_usart);
+
+ return 0;
+}
+
+/**
+ * \brief set LON parameter value.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_type 0: LON comm_type = 1 mode,
+ * 1: LON comm_type = 2 mode
+ */
+void usart_lon_set_comm_type(Usart *p_usart, uint8_t uc_type)
+{
+ p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_COMMT) |
+ (uc_type << 0);
+}
+
+/**
+ * \brief Disable LON Collision Detection Feature.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_lon_disable_coll_detection(Usart *p_usart)
+{
+ p_usart->US_LONMR |= US_LONMR_COLDET;
+}
+
+/**
+ * \brief Enable LON Collision Detection Feature.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_lon_enable_coll_detection(Usart *p_usart)
+{
+ p_usart->US_LONMR &= ~US_LONMR_COLDET;
+}
+
+/**
+ * \brief set Terminate Frame upon Collision Notification.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_type 0: Do not terminate the frame in LON comm_type = 1 mode upon collision detection.
+ * 1:Terminate the frame in LON comm_type = 1 mode upon collision detection if possible.
+ */
+void usart_lon_set_tcol(Usart *p_usart, uint8_t uc_type)
+{
+ p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_TCOL) |
+ (uc_type << 2);
+}
+
+/**
+ * \brief set LON Collision Detection on Frame Tail.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_type 0: Detect collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode.
+ * 1: Ignore collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode.
+ */
+void usart_lon_set_cdtail(Usart *p_usart, uint8_t uc_type)
+{
+ p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_CDTAIL) |
+ (uc_type << 3);
+}
+
+/**
+ * \brief set LON DMA Mode.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_type 0: The LON data length register US_LONDL is not written by the DMA.
+ * 1: The LON data length register US_LONDL is written by the DMA.
+ */
+void usart_lon_set_dmam(Usart *p_usart, uint8_t uc_type)
+{
+ p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_DMAM) |
+ (uc_type << 4);
+}
+
+/**
+ * \brief set LON Beta1 Length after Transmission.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param ul_len 1-16777215: LON beta1 length after transmission in tbit
+ */
+void usart_lon_set_beta1_tx_len(Usart *p_usart, uint32_t ul_len)
+{
+ p_usart->US_LONB1TX = US_LONB1TX_BETA1TX(ul_len);
+}
+
+/**
+ * \brief set LON Beta1 Length after Reception.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param ul_len 1-16777215: LON beta1 length after reception in tbit.
+ */
+void usart_lon_set_beta1_rx_len(Usart *p_usart, uint32_t ul_len)
+{
+ p_usart->US_LONB1RX = US_LONB1RX_BETA1RX(ul_len);
+}
+
+/**
+ * \brief set LON Priority.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_psnb 0 -127: LON Priority Slot Number.
+ * \param uc_nps 0 -127: LON Node Priority Slot.
+ */
+void usart_lon_set_priority(Usart *p_usart, uint8_t uc_psnb, uint8_t uc_nps)
+{
+ p_usart->US_LONPRIO = US_LONPRIO_PSNB(uc_psnb) | US_LONPRIO_NPS(uc_nps);
+}
+
+/**
+ * \brief set LON Indeterminate Time after Transmission.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param ul_time 1-16777215: LON Indeterminate Time after Transmission (comm_type = 1 mode only).
+ */
+void usart_lon_set_tx_idt(Usart *p_usart, uint32_t ul_time)
+{
+ p_usart->US_IDTTX = US_IDTTX_IDTTX(ul_time);
+}
+
+/**
+ * \brief set LON Indeterminate Time after Reception.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param ul_time 1-16777215: LON Indeterminate Time after Reception (comm_type = 1 mode only).
+ */
+void usart_lon_set_rx_idt(Usart *p_usart, uint32_t ul_time)
+{
+ p_usart->US_IDTRX = US_IDTRX_IDTRX(ul_time);
+}
+
+/**
+ * \brief set LON Preamble Length.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param ul_len 1-16383: LON preamble length in tbit(without byte-sync).
+ */
+void usart_lon_set_pre_len(Usart *p_usart, uint32_t ul_len)
+{
+ p_usart->US_LONPR = US_LONPR_LONPL(ul_len);
+}
+
+/**
+ * \brief set LON Data Length.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_len 0-255: LON data length is LONDL+1 bytes.
+ */
+void usart_lon_set_data_len(Usart *p_usart, uint8_t uc_len)
+{
+ p_usart->US_LONDL = US_LONDL_LONDL(uc_len);
+}
+
+/**
+ * \brief set LON Priority.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_bli LON Backlog Increment.
+ * \param uc_altp LON Alternate Path Bit.
+ * \param uc_pb LON Priority Bit.
+ */
+void usart_lon_set_l2hdr(Usart *p_usart, uint8_t uc_bli, uint8_t uc_altp, uint8_t uc_pb)
+{
+ p_usart->US_LONL2HDR = US_LONL2HDR_BLI(uc_bli) | (uc_altp << 6) | (uc_pb << 7);
+}
+
+/**
+ * \brief Check if LON Transmission End.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \retval 1 At least one transmission has been performed since the last RSTSTA.
+ * \retval 0 Transmission on going or no transmission occurred since the last RSTSTA.
+ */
+uint32_t usart_lon_is_tx_end(Usart *p_usart)
+{
+ return (p_usart->US_CSR & US_CSR_LTXD) > 0;
+}
+
+/**
+ * \brief Check if LON Reception End.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \retval 1 At least one Reception has been performed since the last RSTSTA.
+ * \retval 0 Reception on going or no Reception occurred since the last RSTSTA.
+ */
+uint32_t usart_lon_is_rx_end(Usart *p_usart)
+{
+ return (p_usart->US_CSR & US_CSR_LRXD) > 0;
+}
+#endif
+
+/**
+ * \brief Enable USART transmitter.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_enable_tx(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_TXEN;
+}
+
+/**
+ * \brief Disable USART transmitter.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_disable_tx(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_TXDIS;
+}
+
+/**
+ * \brief Immediately stop and disable USART transmitter.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_reset_tx(Usart *p_usart)
+{
+ /* Reset transmitter */
+ p_usart->US_CR = US_CR_RSTTX | US_CR_TXDIS;
+}
+
+/**
+ * \brief Configure the transmit timeguard register.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param timeguard The value of transmit timeguard.
+ */
+void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard)
+{
+ p_usart->US_TTGR = timeguard;
+}
+
+/**
+ * \brief Enable USART receiver.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_enable_rx(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_RXEN;
+}
+
+/**
+ * \brief Disable USART receiver.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_disable_rx(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_RXDIS;
+}
+
+/**
+ * \brief Immediately stop and disable USART receiver.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_reset_rx(Usart *p_usart)
+{
+ /* Reset Receiver */
+ p_usart->US_CR = US_CR_RSTRX | US_CR_RXDIS;
+}
+
+/**
+ * \brief Configure the receive timeout register.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param timeout The value of receive timeout.
+ */
+void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout)
+{
+ p_usart->US_RTOR = timeout;
+}
+
+/**
+ * \brief Enable USART interrupts.
+ *
+ * \param p_usart Pointer to a USART peripheral.
+ * \param ul_sources Interrupt sources bit map.
+ */
+void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources)
+{
+ p_usart->US_IER = ul_sources;
+}
+
+/**
+ * \brief Disable USART interrupts.
+ *
+ * \param p_usart Pointer to a USART peripheral.
+ * \param ul_sources Interrupt sources bit map.
+ */
+void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources)
+{
+ p_usart->US_IDR = ul_sources;
+}
+
+/**
+ * \brief Read USART interrupt mask.
+ *
+ * \param p_usart Pointer to a USART peripheral.
+ *
+ * \return The interrupt mask value.
+ */
+uint32_t usart_get_interrupt_mask(Usart *p_usart)
+{
+ return p_usart->US_IMR;
+}
+
+/**
+ * \brief Get current status.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \return The current USART status.
+ */
+uint32_t usart_get_status(Usart *p_usart)
+{
+ return p_usart->US_CSR;
+}
+
+/**
+ * \brief Reset status bits (PARE, OVER, MANERR, UNRE and PXBRK in US_CSR).
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_reset_status(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_RSTSTA;
+}
+
+/**
+ * \brief Start transmission of a break.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_start_tx_break(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_STTBRK;
+}
+
+/**
+ * \brief Stop transmission of a break.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_stop_tx_break(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_STPBRK;
+}
+
+/**
+ * \brief Start waiting for a character before clocking the timeout count.
+ * Reset the status bit TIMEOUT in US_CSR.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_start_rx_timeout(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_STTTO;
+}
+
+/**
+ * \brief In Multidrop mode only, the next character written to the US_THR
+ * is sent with the address bit set.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param ul_addr The address to be sent out.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr)
+{
+ if ((p_usart->US_MR & US_MR_PAR_MULTIDROP) != US_MR_PAR_MULTIDROP) {
+ return 1;
+ }
+
+ p_usart->US_CR = US_CR_SENDA;
+
+ if (usart_write(p_usart, ul_addr)) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ * \brief Restart the receive timeout.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_restart_rx_timeout(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_RETTO;
+}
+
+#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E)
+
+/**
+ * \brief Drive the pin DTR to 0.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_drive_DTR_pin_low(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_DTREN;
+}
+
+/**
+ * \brief Drive the pin DTR to 1.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_drive_DTR_pin_high(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_DTRDIS;
+}
+
+#endif
+
+/**
+ * \brief Drive the pin RTS to 0.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_drive_RTS_pin_low(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_RTSEN;
+}
+
+/**
+ * \brief Drive the pin RTS to 1.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_drive_RTS_pin_high(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_RTSDIS;
+}
+
+/**
+ * \brief Drive the slave select line NSS (RTS pin) to 0 in SPI master mode.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_spi_force_chip_select(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_FCS;
+}
+
+/**
+ * \brief Drive the slave select line NSS (RTS pin) to 1 in SPI master mode.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_spi_release_chip_select(Usart *p_usart)
+{
+ p_usart->US_CR = US_CR_RCS;
+}
+
+/**
+ * \brief Check if Transmit is Ready.
+ * Check if data have been loaded in USART_THR and are waiting to be loaded
+ * into the Transmit Shift Register (TSR).
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \retval 1 No data is in the Transmit Holding Register.
+ * \retval 0 There is data in the Transmit Holding Register.
+ */
+uint32_t usart_is_tx_ready(Usart *p_usart)
+{
+ return (p_usart->US_CSR & US_CSR_TXRDY) > 0;
+}
+
+/**
+ * \brief Check if Transmit Holding Register is empty.
+ * Check if the last data written in USART_THR have been loaded in TSR and the
+ * last data loaded in TSR have been transmitted.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \retval 1 Transmitter is empty.
+ * \retval 0 Transmitter is not empty.
+ */
+uint32_t usart_is_tx_empty(Usart *p_usart)
+{
+ return (p_usart->US_CSR & US_CSR_TXEMPTY) > 0;
+}
+
+/**
+ * \brief Check if the received data are ready.
+ * Check if Data have been received and loaded into USART_RHR.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \retval 1 Some data has been received.
+ * \retval 0 No data has been received.
+ */
+uint32_t usart_is_rx_ready(Usart *p_usart)
+{
+ return (p_usart->US_CSR & US_CSR_RXRDY) > 0;
+}
+
+/**
+ * \brief Write to USART Transmit Holding Register.
+ *
+ * \note Before writing user should check if tx is ready (or empty).
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param c Data to be sent.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_write(Usart *p_usart, uint32_t c)
+{
+ if (!(p_usart->US_CSR & US_CSR_TXRDY)) {
+ return 1;
+ }
+
+ p_usart->US_THR = US_THR_TXCHR(c);
+ return 0;
+}
+
+/**
+ * \brief Write to USART Transmit Holding Register.
+ *
+ * \note Before writing user should check if tx is ready (or empty).
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param c Data to be sent.
+ *
+ * \retval 0 on success.
+ * \retval 1 on failure.
+ */
+uint32_t usart_putchar(Usart *p_usart, uint32_t c)
+{
+ while (!(p_usart->US_CSR & US_CSR_TXRDY)) {
+ }
+
+ p_usart->US_THR = US_THR_TXCHR(c);
+
+ return 0;
+}
+
+/**
+ * \brief Write one-line string through USART.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param string Pointer to one-line string to be sent.
+ */
+void usart_write_line(Usart *p_usart, const char *string)
+{
+ while (*string != '\0') {
+ usart_putchar(p_usart, *string++);
+ }
+}
+
+/**
+ * \brief Read from USART Receive Holding Register.
+ *
+ * \note Before reading user should check if rx is ready.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param c Pointer where the one-byte received data will be stored.
+ *
+ * \retval 0 on success.
+ * \retval 1 if no data is available or errors.
+ */
+uint32_t usart_read(Usart *p_usart, uint32_t *c)
+{
+ if (!(p_usart->US_CSR & US_CSR_RXRDY)) {
+ return 1;
+ }
+
+ /* Read character */
+ *c = p_usart->US_RHR & US_RHR_RXCHR_Msk;
+
+ return 0;
+}
+
+/**
+ * \brief Read from USART Receive Holding Register.
+ * Before reading user should check if rx is ready.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param c Pointer where the one-byte received data will be stored.
+ *
+ * \retval 0 Data has been received.
+ * \retval 1 on failure.
+ */
+uint32_t usart_getchar(Usart *p_usart, uint32_t *c)
+{
+ /* Wait until it's not empty or timeout has reached. */
+ while (!(p_usart->US_CSR & US_CSR_RXRDY)) {
+ }
+
+ /* Read character */
+ *c = p_usart->US_RHR & US_RHR_RXCHR_Msk;
+
+ return 0;
+}
+
+#if (SAM3XA || SAM3U)
+/**
+ * \brief Get Transmit address for DMA operation.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \return Transmit address for DMA access.
+ */
+uint32_t *usart_get_tx_access(Usart *p_usart)
+{
+ return (uint32_t *)&(p_usart->US_THR);
+}
+
+/**
+ * \brief Get Receive address for DMA operation.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \return Receive address for DMA access.
+ */
+uint32_t *usart_get_rx_access(Usart *p_usart)
+{
+ return (uint32_t *)&(p_usart->US_RHR);
+}
+#endif
+
+#if (!SAM4L && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
+/**
+ * \brief Get USART PDC base address.
+ *
+ * \param p_usart Pointer to a UART instance.
+ *
+ * \return USART PDC registers base for PDC driver to access.
+ */
+Pdc *usart_get_pdc_base(Usart *p_usart)
+{
+ Pdc *p_pdc_base;
+
+ p_pdc_base = (Pdc *)NULL;
+
+#ifdef PDC_USART
+ if (p_usart == USART) {
+ p_pdc_base = PDC_USART;
+ return p_pdc_base;
+ }
+#endif
+#ifdef PDC_USART0
+ if (p_usart == USART0) {
+ p_pdc_base = PDC_USART0;
+ return p_pdc_base;
+ }
+#endif
+#ifdef PDC_USART1
+ else if (p_usart == USART1) {
+ p_pdc_base = PDC_USART1;
+ return p_pdc_base;
+ }
+#endif
+#ifdef PDC_USART2
+ else if (p_usart == USART2) {
+ p_pdc_base = PDC_USART2;
+ return p_pdc_base;
+ }
+#endif
+#ifdef PDC_USART3
+ else if (p_usart == USART3) {
+ p_pdc_base = PDC_USART3;
+ return p_pdc_base;
+ }
+#endif
+#ifdef PDC_USART4
+ else if (p_usart == USART4) {
+ p_pdc_base = PDC_USART4;
+ return p_pdc_base;
+ }
+#endif
+#ifdef PDC_USART5
+ else if (p_usart == USART5) {
+ p_pdc_base = PDC_USART5;
+ return p_pdc_base;
+ }
+#endif
+#ifdef PDC_USART6
+ else if (p_usart == USART6) {
+ p_pdc_base = PDC_USART6;
+ return p_pdc_base;
+ }
+#endif
+#ifdef PDC_USART7
+ else if (p_usart == USART7) {
+ p_pdc_base = PDC_USART7;
+ return p_pdc_base;
+ }
+#endif
+
+ return p_pdc_base;
+}
+#endif
+
+/**
+ * \brief Enable write protect of USART registers.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_enable_writeprotect(Usart *p_usart)
+{
+ p_usart->US_WPMR = US_WPMR_WPEN | US_WPMR_WPKEY_PASSWD;
+}
+
+/**
+ * \brief Disable write protect of USART registers.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_disable_writeprotect(Usart *p_usart)
+{
+ p_usart->US_WPMR = US_WPMR_WPKEY_PASSWD;
+}
+
+/**
+ * \brief Get write protect status.
+ *
+ * \param p_usart Pointer to a USART instance.
+ *
+ * \return 0 if no write protect violation occurred, or 16-bit write protect
+ * violation source.
+ */
+uint32_t usart_get_writeprotect_status(Usart *p_usart)
+{
+ uint32_t reg_value;
+
+ reg_value = p_usart->US_WPSR;
+ if (reg_value & US_WPSR_WPVS) {
+ return (reg_value & US_WPSR_WPVSRC_Msk) >> US_WPSR_WPVSRC_Pos;
+ } else {
+ return 0;
+ }
+}
+
+#if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E || SAM4C || SAM4CP || SAM4CM)
+
+/**
+ * \brief Configure the transmitter preamble length when the Manchester
+ * encode/decode is enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_len The transmitter preamble length, which should be 0 ~ 15.
+ */
+void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len)
+{
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PL_Msk) |
+ US_MAN_TX_PL(uc_len);
+}
+
+/**
+ * \brief Configure the transmitter preamble pattern when the Manchester
+ * encode/decode is enabled, which should be 0 ~ 3.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_pattern 0 if the preamble is composed of '1's;
+ * 1 if the preamble is composed of '0's;
+ * 2 if the preamble is composed of '01's;
+ * 3 if the preamble is composed of '10's.
+ */
+void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern)
+{
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PP_Msk) |
+ (uc_pattern << US_MAN_TX_PP_Pos);
+}
+
+/**
+ * \brief Configure the transmitter Manchester polarity when the Manchester
+ * encode/decode is enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_polarity Indicate the transmitter Manchester polarity, which
+ * should be 0 or 1.
+ */
+void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity)
+{
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_MPOL) |
+ (uc_polarity << 12);
+}
+
+/**
+ * \brief Configure the detected receiver preamble length when the Manchester
+ * encode/decode is enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_len The detected receiver preamble length, which should be 0 ~ 15.
+ */
+void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len)
+{
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PL_Msk) |
+ US_MAN_RX_PL(uc_len);
+}
+
+/**
+ * \brief Configure the detected receiver preamble pattern when the Manchester
+ * encode/decode is enabled, which should be 0 ~ 3.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_pattern 0 if the preamble is composed of '1's;
+ * 1 if the preamble is composed of '0's;
+ * 2 if the preamble is composed of '01's;
+ * 3 if the preamble is composed of '10's.
+ */
+void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern)
+{
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PP_Msk) |
+ (uc_pattern << US_MAN_RX_PP_Pos);
+}
+
+/**
+ * \brief Configure the receiver Manchester polarity when the Manchester
+ * encode/decode is enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ * \param uc_polarity Indicate the receiver Manchester polarity, which should
+ * be 0 or 1.
+ */
+void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity)
+{
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_MPOL) |
+ (uc_polarity << 28);
+}
+
+/**
+ * \brief Enable drift compensation.
+ *
+ * \note The 16X clock mode must be enabled.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_man_enable_drift_compensation(Usart *p_usart)
+{
+ p_usart->US_MAN |= US_MAN_DRIFT;
+}
+
+/**
+ * \brief Disable drift compensation.
+ *
+ * \param p_usart Pointer to a USART instance.
+ */
+void usart_man_disable_drift_compensation(Usart *p_usart)
+{
+ p_usart->US_MAN &= ~US_MAN_DRIFT;
+}
+
+#endif
+
+#if SAM4L
+
+uint32_t usart_get_version(Usart *p_usart)
+{
+ return p_usart->US_VERSION;
+}
+
+#endif
+
+#if SAMG55
+/**
+ * \brief Set sleepwalking match mode.
+ *
+ * \param p_uart Pointer to a USART instance.
+ * \param ul_low_value First comparison value for received character.
+ * \param ul_high_value Second comparison value for received character.
+ * \param cmpmode ture for start condition, false for flag only.
+ * \param cmppar ture for parity check, false for no.
+ */
+void usart_set_sleepwalking(Usart *p_uart, uint8_t ul_low_value,
+ bool cmpmode, bool cmppar, uint8_t ul_high_value)
+{
+ Assert(ul_low_value <= ul_high_value);
+
+ uint32_t temp = 0;
+
+ if (cmpmode) {
+ temp |= US_CMPR_CMPMODE_START_CONDITION;
+ }
+
+ if (cmppar) {
+ temp |= US_CMPR_CMPPAR;
+ }
+
+ temp |= US_CMPR_VAL1(ul_low_value);
+
+ temp |= US_CMPR_VAL2(ul_high_value);
+
+ p_uart->US_CMPR= temp;
+}
+#endif
+
+//@}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/usart/usart.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,779 @@
+/**
+ * \file
+ *
+ * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver
+ * for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef USART_H_INCLUDED
+#define USART_H_INCLUDED
+
+#include "compiler.h"
+
+/**
+ * \defgroup group_sam_drivers_usart Universal Synchronous Asynchronous Receiver
+ * Transmitter (USART).
+ *
+ * See \ref sam_usart_quickstart.
+ *
+ * This is a low-level driver implementation for the SAM Universal
+ * Synchronous/Asynchronous Receiver/Transmitter.
+ *
+ * @{
+ */
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /** Clock phase. */
+#define SPI_CPHA (1 << 0)
+
+ /** Clock polarity. */
+#define SPI_CPOL (1 << 1)
+
+ /** SPI mode definition. */
+#define SPI_MODE_0 0
+#define SPI_MODE_1 (SPI_CPHA)
+#define SPI_MODE_2 (SPI_CPOL)
+#define SPI_MODE_3 (SPI_CPOL | SPI_CPHA)
+
+ /**micro definition for LIN mode of SAMV71*/
+#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
+#define US_MR_USART_MODE_LIN_MASTER 0x0A
+#define US_MR_USART_MODE_LIN_SLAVE 0x0B
+#endif
+ /* Input parameters when initializing RS232 and similar modes. */
+ typedef struct {
+ /* Set baud rate of the USART (unused in slave modes). */
+ uint32_t baudrate;
+
+ /*
+ * Number of bits, which should be one of the following: US_MR_CHRL_5_BIT,
+ * US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or
+ * US_MR_MODE9.
+ */
+ uint32_t char_length;
+
+ /*
+ * Parity type, which should be one of the following: US_MR_PAR_EVEN,
+ * US_MR_PAR_ODD, US_MR_PAR_SPACE, US_MR_PAR_MARK, US_MR_PAR_NO
+ * or US_MR_PAR_MULTIDROP.
+ */
+ uint32_t parity_type;
+
+ /*
+ * Number of stop bits between two characters: US_MR_NBSTOP_1_BIT,
+ * US_MR_NBSTOP_1_5_BIT, US_MR_NBSTOP_2_BIT.
+ * \note US_MR_NBSTOP_1_5_BIT is supported in asynchronous modes only.
+ */
+ uint32_t stop_bits;
+
+ /*
+ * Run the channel in test mode, which should be one of following:
+ * US_MR_CHMODE_NORMAL, US_MR_CHMODE_AUTOMATIC,
+ * US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK.
+ */
+ uint32_t channel_mode;
+
+ /* Filter of IrDA mode, useless in other modes. */
+ uint32_t irda_filter;
+ } sam_usart_opt_t;
+
+ /* Input parameters when initializing ISO7816 mode. */
+ typedef struct {
+ /* Set the frequency of the ISO7816 clock. */
+ uint32_t iso7816_hz;
+
+ /*
+ * The number of ISO7816 clock ticks in every bit period (1 to 2047,
+ * 0 = disable clock). Baudrate rate = iso7816_hz / fidi_ratio.
+ */
+ uint32_t fidi_ratio;
+
+ /*
+ * How to calculate the parity bit: US_MR_PAR_EVEN for normal mode or
+ * US_MR_PAR_ODD for inverse mode.
+ */
+ uint32_t parity_type;
+
+ /*
+ * Inhibit Non Acknowledge:
+ * - 0: the NACK is generated;
+ * - 1: the NACK is not generated.
+ *
+ * \note This bit will be used only in ISO7816 mode, protocol T = 0
+ * receiver.
+ */
+ uint32_t inhibit_nack;
+
+ /*
+ * Disable successive NACKs.
+ * - 0: NACK is sent on the ISO line as soon as a parity error occurs
+ * in the received character. Successive parity errors are counted up to
+ * the value in the max_iterations field. These parity errors generate
+ * a NACK on the ISO line. As soon as this value is reached, no additional
+ * NACK is sent on the ISO line. The ITERATION flag is asserted.
+ */
+ uint32_t dis_suc_nack;
+
+ /* Max number of repetitions (0 to 7). */
+ uint32_t max_iterations;
+
+ /*
+ * Bit order in transmitted characters:
+ * - 0: LSB first;
+ * - 1: MSB first.
+ */
+ uint32_t bit_order;
+
+ /*
+ * Which protocol is used:
+ * - 0: T = 0;
+ * - 1: T = 1.
+ */
+ uint32_t protocol_type;
+ } usart_iso7816_opt_t;
+
+ /* Input parameters when initializing SPI mode. */
+ typedef struct {
+ /* Set the frequency of the SPI clock (unused in slave mode). */
+ uint32_t baudrate;
+
+ /*
+ * Number of bits, which should be one of the following: US_MR_CHRL_5_BIT,
+ * US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or
+ * US_MR_MODE9.
+ */
+ uint32_t char_length;
+
+ /*
+ * Which SPI mode to use, which should be one of the following:
+ * SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3.
+ */
+ uint32_t spi_mode;
+
+ /*
+ * Run the channel in test mode, which should be one of following:
+ * US_MR_CHMODE_NORMAL, US_MR_CHMODE_AUTOMATIC,
+ * US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK.
+ */
+ uint32_t channel_mode;
+ } usart_spi_opt_t;
+
+ void usart_reset(Usart *p_usart);
+ uint32_t usart_set_async_baudrate(Usart *p_usart,
+ uint32_t baudrate, uint32_t ul_mck);
+ uint32_t usart_init_rs232(Usart *p_usart,
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);
+ uint32_t usart_init_hw_handshaking(Usart *p_usart,
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);
+#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E)
+ uint32_t usart_init_modem(Usart *p_usart,
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);
+#endif
+ uint32_t usart_init_sync_master(Usart *p_usart,
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);
+ uint32_t usart_init_sync_slave(Usart *p_usart,
+ const sam_usart_opt_t *p_usart_opt);
+ uint32_t usart_init_rs485(Usart *p_usart,
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);
+#if (!SAMG55 && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
+ uint32_t usart_init_irda(Usart *p_usart,
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);
+#endif
+#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
+ uint32_t usart_init_iso7816(Usart *p_usart,
+ const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck);
+ void usart_reset_iterations(Usart *p_usart);
+ void usart_reset_nack(Usart *p_usart);
+ uint32_t usart_is_rx_buf_end(Usart *p_usart);
+ uint32_t usart_is_tx_buf_end(Usart *p_usart);
+ uint32_t usart_is_rx_buf_full(Usart *p_usart);
+ uint32_t usart_is_tx_buf_empty(Usart *p_usart);
+ uint8_t usart_get_error_number(Usart *p_usart);
+#endif
+ uint32_t usart_init_spi_master(Usart *p_usart,
+ const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck);
+ uint32_t usart_init_spi_slave(Usart *p_usart,
+ const usart_spi_opt_t *p_usart_opt);
+#if (SAM3XA || SAM4L || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
+ uint32_t usart_init_lin_master(Usart *p_usart, uint32_t ul_baudrate,
+ uint32_t ul_mck);
+ uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate,
+ uint32_t ul_mck);
+ void usart_lin_abort_tx(Usart *p_usart);
+ void usart_lin_send_wakeup_signal(Usart *p_usart);
+ void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action);
+ void usart_lin_disable_parity(Usart *p_usart);
+ void usart_lin_enable_parity(Usart *p_usart);
+ void usart_lin_disable_checksum(Usart *p_usart);
+ void usart_lin_enable_checksum(Usart *p_usart);
+ void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type);
+ void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode);
+ void usart_lin_disable_frame_slot(Usart *p_usart);
+ void usart_lin_enable_frame_slot(Usart *p_usart);
+ void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type);
+ void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len);
+ void usart_lin_disable_pdc_mode(Usart *p_usart);
+ void usart_lin_enable_pdc_mode(Usart *p_usart);
+ void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id);
+ uint8_t usart_lin_read_identifier(Usart *p_usart);
+ uint8_t usart_lin_get_data_length(Usart *usart);
+#endif
+#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
+ uint8_t usart_lin_identifier_send_complete(Usart *usart);
+ uint8_t usart_lin_identifier_reception_complete(Usart *usart);
+ uint8_t usart_lin_tx_complete(Usart *usart);
+ uint32_t usart_init_lon(Usart *p_usart, uint32_t ul_baudrate, uint32_t ul_mck);
+ void usart_lon_set_comm_type(Usart *p_usart, uint8_t uc_type);
+ void usart_lon_disable_coll_detection(Usart *p_usart);
+ void usart_lon_enable_coll_detection(Usart *p_usart);
+ void usart_lon_set_tcol(Usart *p_usart, uint8_t uc_type);
+ void usart_lon_set_cdtail(Usart *p_usart, uint8_t uc_type);
+ void usart_lon_set_dmam(Usart *p_usart, uint8_t uc_type);
+ void usart_lon_set_beta1_tx_len(Usart *p_usart, uint32_t ul_len);
+ void usart_lon_set_beta1_rx_len(Usart *p_usart, uint32_t ul_len);
+ void usart_lon_set_priority(Usart *p_usart, uint8_t uc_psnb, uint8_t uc_nps);
+ void usart_lon_set_tx_idt(Usart *p_usart, uint32_t ul_time);
+ void usart_lon_set_rx_idt(Usart *p_usart, uint32_t ul_time);
+ void usart_lon_set_pre_len(Usart *p_usart, uint32_t ul_len);
+ void usart_lon_set_data_len(Usart *p_usart, uint8_t uc_len);
+ void usart_lon_set_l2hdr(Usart *p_usart, uint8_t uc_bli, uint8_t uc_altp, uint8_t uc_pb);
+ uint32_t usart_lon_is_tx_end(Usart *p_usart);
+ uint32_t usart_lon_is_rx_end(Usart *p_usart);
+#endif
+ void usart_enable_tx(Usart *p_usart);
+ void usart_disable_tx(Usart *p_usart);
+ void usart_reset_tx(Usart *p_usart);
+ void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard);
+ void usart_enable_rx(Usart *p_usart);
+ void usart_disable_rx(Usart *p_usart);
+ void usart_reset_rx(Usart *p_usart);
+ void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout);
+ void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources);
+ void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources);
+ uint32_t usart_get_interrupt_mask(Usart *p_usart);
+ uint32_t usart_get_status(Usart *p_usart);
+ void usart_reset_status(Usart *p_usart);
+ void usart_start_tx_break(Usart *p_usart);
+ void usart_stop_tx_break(Usart *p_usart);
+ void usart_start_rx_timeout(Usart *p_usart);
+ uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr);
+ void usart_restart_rx_timeout(Usart *p_usart);
+#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E)
+ void usart_drive_DTR_pin_low(Usart *p_usart);
+ void usart_drive_DTR_pin_high(Usart *p_usart);
+#endif
+ void usart_drive_RTS_pin_low(Usart *p_usart);
+ void usart_drive_RTS_pin_high(Usart *p_usart);
+ void usart_spi_force_chip_select(Usart *p_usart);
+ void usart_spi_release_chip_select(Usart *p_usart);
+ uint32_t usart_is_tx_ready(Usart *p_usart);
+ uint32_t usart_is_tx_empty(Usart *p_usart);
+ uint32_t usart_is_rx_ready(Usart *p_usart);
+ uint32_t usart_write(Usart *p_usart, uint32_t c);
+ uint32_t usart_putchar(Usart *p_usart, uint32_t c);
+ void usart_write_line(Usart *p_usart, const char *string);
+ uint32_t usart_read(Usart *p_usart, uint32_t *c);
+ uint32_t usart_getchar(Usart *p_usart, uint32_t *c);
+#if (SAM3XA || SAM3U)
+ uint32_t *usart_get_tx_access(Usart *p_usart);
+ uint32_t *usart_get_rx_access(Usart *p_usart);
+#endif
+#if (!SAM4L && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
+ Pdc *usart_get_pdc_base(Usart *p_usart);
+#endif
+ void usart_enable_writeprotect(Usart *p_usart);
+ void usart_disable_writeprotect(Usart *p_usart);
+ uint32_t usart_get_writeprotect_status(Usart *p_usart);
+#if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E || SAM4C || SAM4CP || SAM4CM || SAMV70 || SAMV71 || SAMS70 || SAME70)
+ void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len);
+ void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern);
+ void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity);
+ void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len);
+ void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern);
+ void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity);
+ void usart_man_enable_drift_compensation(Usart *p_usart);
+ void usart_man_disable_drift_compensation(Usart *p_usart);
+#endif
+
+#if SAM4L
+ uint32_t usart_get_version(Usart *p_usart);
+#endif
+
+#if SAMG55
+ void usart_set_sleepwalking(Usart *p_uart, uint8_t ul_low_value,
+ bool cmpmode, bool cmppar, uint8_t ul_high_value);
+#endif
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+//! @}
+
+/**
+ * \page sam_usart_quickstart Quick start guide for the SAM USART module
+ *
+ * This is the quick start guide for the \ref group_sam_drivers_usart
+ * "USART module", with step-by-step instructions on how to configure and
+ * use the driver in a selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \note Some SAM devices contain both USART and UART modules, with the latter
+ * being a subset in functionality of the former but physically separate
+ * peripherals. UART modules are compatible with the USART driver, but
+ * only for the functions and modes supported by the base UART driver.
+ *
+ * \section usart_use_cases USART use cases
+ * - \ref usart_basic_use_case
+ * - \subpage usart_use_case_1
+ * - \subpage usart_use_case_2
+ *
+ * \note The USART pins configuration are not included here. Please refer
+ * the related code in board_init() function.
+ *
+ * \section usart_basic_use_case Basic use case - transmit a character
+ * In this use case, the USART module is configured for:
+ * - Using USART0
+ * - Baudrate: 9600
+ * - Character length: 8 bit
+ * - Parity mode: Disabled
+ * - Stop bit: None
+ * - RS232 mode
+ *
+ * \section usart_basic_use_case_setup Setup steps
+ *
+ * \subsection usart_basic_use_case_setup_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (sysclock)"
+ * -# \ref ioport_group "Common IOPORT API (ioport)"
+ *
+ * \subsection usart_basic_use_case_setup_code Example code
+ * The following configuration must be added to the project (typically to a
+ * conf_usart.h file, but it can also be added to your main application file.)
+ * \code
+ #define USART_SERIAL USART0
+ #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l
+ #define USART_SERIAL_BAUDRATE 9600
+ #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT
+ #define USART_SERIAL_PARITY US_MR_PAR_NO
+ #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT
+\endcode
+ *
+ * Add to application initialization:
+ * \code
+ sysclk_init();
+
+ board_init();
+
+ const sam_usart_opt_t usart_console_settings = {
+ USART_SERIAL_BAUDRATE,
+ USART_SERIAL_CHAR_LENGTH,
+ USART_SERIAL_PARITY,
+ USART_SERIAL_STOP_BIT,
+ US_MR_CHMODE_NORMAL
+ };
+ #if SAM4L
+ sysclk_enable_peripheral_clock(USART_SERIAL);
+ #else
+ sysclk_enable_peripheral_clock(USART_SERIAL_ID);
+ #endif
+ usart_init_rs232(USART_SERIAL, &usart_console_settings,
+ sysclk_get_main_hz());
+ usart_enable_tx(USART_SERIAL);
+ usart_enable_rx(USART_SERIAL);
+\endcode
+ *
+ * \subsection usart_basic_use_case_setup_flow Workflow
+ * -# Initialize system clock:
+ * \code
+ sysclk_init();
+\endcode
+ * -# Configure the USART Tx and Rx pins by call the board init function:
+ * \code
+ board_init();
+\endcode
+ * \note Set the following define in conf_board.h file to enable COM port,it will be used in
+ * board_init() function to set up IOPorts for the USART pins.
+ * For SAM4L:
+ * \code
+ #define CONF_BOARD_COM_PORT
+\endcode
+ * For other SAM devices:
+ * \code
+ #define CONF_BOARD_UART_CONSOLE
+\endcode
+ * -# Create USART options struct:
+ * \code
+ const sam_usart_opt_t usart_console_settings = {
+ USART_SERIAL_BAUDRATE,
+ USART_SERIAL_CHAR_LENGTH,
+ USART_SERIAL_PARITY,
+ USART_SERIAL_STOP_BIT,
+ US_MR_CHMODE_NORMAL
+ };
+\endcode
+ * -# Enable the clock to the USART module:
+ * \code
+ #if SAM4L
+ sysclk_enable_peripheral_clock(USART_SERIAL);
+ #else
+ sysclk_enable_peripheral_clock(USART_SERIAL_ID);
+ #endif
+\endcode
+ * -# Initialize the USART module in RS232 mode:
+ * \code
+ usart_init_rs232(USART_SERIAL, &usart_console_settings,
+ sysclk_get_main_hz());
+\endcode
+ * -# Enable the Rx and Tx modes of the USART module:
+ * \code
+ usart_enable_tx(USART_SERIAL);
+ usart_enable_rx(USART_SERIAL);
+\endcode
+ *
+ * \section usart_basic_use_case_usage Usage steps
+ *
+ * \subsection usart_basic_use_case_usage_code Example code
+ * Add to application C-file:
+ * \code
+ usart_putchar(USART_SERIAL, 'a');
+\endcode
+ *
+ * \subsection usart_basic_use_case_usage_flow Workflow
+ * -# Send an 'a' character via USART
+ * \code usart_putchar(USART_SERIAL, 'a'); \endcode
+ */
+
+/**
+ * \page usart_use_case_1 USART receive character and echo back
+ *
+ * In this use case, the USART module is configured for:
+ * - Using USART0
+ * - Baudrate: 9600
+ * - Character length: 8 bit
+ * - Parity mode: Disabled
+ * - Stop bit: None
+ * - RS232 mode
+ *
+ * The use case waits for a received character on the configured USART and
+ * echoes the character back to the same USART.
+ *
+ * \section usart_use_case_1_setup Setup steps
+ *
+ * \subsection usart_use_case_1_setup_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (sysclock)"
+ * -# \ref ioport_group "Common IOPORT API (ioport)"
+ *
+ * \subsection usart_use_case_1_setup_code Example code
+ * The following configuration must be added to the project (typically to a
+ * conf_usart.h file, but it can also be added to your main application file.):
+ * \code
+ #define USART_SERIAL USART0
+ #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l
+ #define USART_SERIAL_BAUDRATE 9600
+ #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT
+ #define USART_SERIAL_PARITY US_MR_PAR_NO
+ #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT
+\endcode
+ *
+ * A variable for the received byte must be added:
+ * \code
+ uint32_t received_byte;
+\endcode
+ *
+ * Add to application initialization:
+ * \code
+ sysclk_init();
+
+ board_init();
+
+ const sam_usart_opt_t usart_console_settings = {
+ USART_SERIAL_BAUDRATE,
+ USART_SERIAL_CHAR_LENGTH,
+ USART_SERIAL_PARITY,
+ USART_SERIAL_STOP_BIT,
+ US_MR_CHMODE_NORMAL
+ };
+
+ #if SAM4L
+ sysclk_enable_peripheral_clock(USART_SERIAL);
+ #else
+ sysclk_enable_peripheral_clock(USART_SERIAL_ID);
+ #endif
+
+ usart_init_rs232(USART_SERIAL, &usart_console_settings,
+ sysclk_get_main_hz());
+ usart_enable_tx(USART_SERIAL);
+ usart_enable_rx(USART_SERIAL);
+\endcode
+ *
+ * \subsection usart_use_case_1_setup_flow Workflow
+ * -# Initialize system clock:
+ * \code
+ sysclk_init();
+\endcode
+ * -# Configure the USART Tx and Rx pins by call the board init function:
+ * \code
+ board_init();
+\endcode
+ * \note Set the following define in conf_board.h file to enable COM port,it will be used in
+ * board_init() function to set up IOPorts for the USART pins.
+ * For SAM4L:
+ * \code
+ #define CONF_BOARD_COM_PORT
+\endcode
+ * For other SAM devices:
+ * \code
+ #define CONF_BOARD_UART_CONSOLE
+\endcode
+ * -# Create USART options struct:
+ * \code
+ const sam_usart_opt_t usart_console_settings = {
+ USART_SERIAL_BAUDRATE,
+ USART_SERIAL_CHAR_LENGTH,
+ USART_SERIAL_PARITY,
+ USART_SERIAL_STOP_BIT,
+ US_MR_CHMODE_NORMAL
+ };
+\endcode
+ * -# Enable the clock to the USART module:
+ * \code
+ #if SAM4L
+ sysclk_enable_peripheral_clock(USART_SERIAL);
+ #else
+ sysclk_enable_peripheral_clock(USART_SERIAL_ID);
+ #endif
+\endcode
+ * -# Initialize the USART module in RS232 mode:
+ * \code
+ usart_init_rs232(USART_SERIAL, &usart_console_settings,
+ sysclk_get_main_hz());
+\endcode
+ * -# Enable the Rx and Tx modes of the USART module:
+ * \code
+ usart_enable_tx(USART_SERIAL);
+ usart_enable_rx(USART_SERIAL);
+\endcode
+ *
+ * \section usart_use_case_1_usage Usage steps
+ *
+ * \subsection usart_use_case_1_usage_code Example code
+ * Add to, e.g., main loop in application C-file:
+ * \code
+ received_byte = usart_getchar(USART_SERIAL);
+ usart_putchar(USART_SERIAL, received_byte);
+\endcode
+ *
+ * \subsection usart_use_case_1_usage_flow Workflow
+ * -# Wait for reception of a character:
+ * \code usart_getchar(USART_SERIAL, &received_byte); \endcode
+ * -# Echo the character back:
+ * \code usart_putchar(USART_SERIAL, received_byte); \endcode
+ */
+
+/**
+ * \page usart_use_case_2 USART receive character and echo back via interrupts
+ *
+ * In this use case, the USART module is configured for:
+ * - Using USART0
+ * - Baudrate: 9600
+ * - Character length: 8 bit
+ * - Parity mode: Disabled
+ * - Stop bit: None
+ * - RS232 mode
+ *
+ * The use case waits for a received character on the configured USART and
+ * echoes the character back to the same USART. The character reception is
+ * performed via an interrupt handler, rather than the polling method used
+ * in \ref usart_use_case_1.
+ *
+ * \section usart_use_case_2_setup Setup steps
+ *
+ * \subsection usart_use_case_2_setup_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (sysclock)"
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"
+ * -# \ref pmc_group "Power Management Controller (pmc)"
+ *
+ * \subsection usart_use_case_2_setup_code Example code
+ * The following configuration must be added to the project (typically to a
+ * conf_usart.h file, but it can also be added to your main application file.):
+ * \code
+ #define USART_SERIAL USART0
+ #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l
+ #define USART_SERIAL_ISR_HANDLER USART0_Handler
+ #define USART_SERIAL_BAUDRATE 9600
+ #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT
+ #define USART_SERIAL_PARITY US_MR_PAR_NO
+ #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT
+\endcode
+ *
+ * A variable for the received byte must be added:
+ * \code
+ uint32_t received_byte;
+\endcode
+ *
+ * Add to application initialization:
+ * \code
+ sysclk_init();
+
+ board_init();
+
+ const sam_usart_opt_t usart_console_settings = {
+ USART_SERIAL_BAUDRATE,
+ USART_SERIAL_CHAR_LENGTH,
+ USART_SERIAL_PARITY,
+ USART_SERIAL_STOP_BIT,
+ US_MR_CHMODE_NORMAL
+ };
+
+ #if SAM4L
+ sysclk_enable_peripheral_clock(USART_SERIAL);
+ #else
+ sysclk_enable_peripheral_clock(USART_SERIAL_ID);
+ #endif
+
+ usart_init_rs232(USART_SERIAL, &usart_console_settings,
+ sysclk_get_main_hz());
+ usart_enable_tx(USART_SERIAL);
+ usart_enable_rx(USART_SERIAL);
+
+ usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY);
+ NVIC_EnableIRQ(USART_SERIAL_IRQ);
+\endcode
+ *
+ * \subsection usart_use_case_2_setup_flow Workflow
+ * -# Initialize system clock:
+ * \code
+ sysclk_init();
+\endcode
+ * -# Configure the USART Tx and Rx pins by call the board init function:
+ * \code
+ board_init();
+\endcode
+ * \note Set the following define in conf_board.h file to enable COM port,it will be used in
+ * board_init() function to set up IOPorts for the USART pins.
+ * For SAM4L:
+ * \code
+ #define CONF_BOARD_COM_PORT
+\endcode
+ * For other SAM devices:
+ * \code
+ #define CONF_BOARD_UART_CONSOLE
+\endcode
+ * -# Create USART options struct:
+ * \code
+ const sam_usart_opt_t usart_console_settings = {
+ USART_SERIAL_BAUDRATE,
+ USART_SERIAL_CHAR_LENGTH,
+ USART_SERIAL_PARITY,
+ USART_SERIAL_STOP_BIT,
+ US_MR_CHMODE_NORMAL
+ };
+\endcode
+ * -# Enable the clock to the USART module:
+ * \code
+ #if SAM4L
+ sysclk_enable_peripheral_clock(USART_SERIAL);
+ #else
+ sysclk_enable_peripheral_clock(USART_SERIAL_ID);
+ #endif
+\endcode
+ * -# Initialize the USART module in RS232 mode:
+ * \code
+ usart_init_rs232(USART_SERIAL, &usart_console_settings,
+ sysclk_get_main_hz());
+\endcode
+ * -# Enable the Rx and Tx modes of the USART module:
+ * \code
+ usart_enable_tx(USART_SERIAL);
+ usart_enable_rx(USART_SERIAL);
+\endcode
+ * -# Enable the USART character reception interrupt, and general interrupts
+ * for the USART module.
+ * \code
+ usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY);
+ NVIC_EnableIRQ(USART_SERIAL_IRQ);
+\endcode
+ * \section usart_use_case_2_usage Usage steps
+ *
+ * \subsection usart_use_case_2_usage_code Example code
+ * Add to your main application C-file the USART interrupt handler:
+ * \code
+ void USART_SERIAL_ISR_HANDLER(void)
+ {
+ uint32_t dw_status = usart_get_status(USART_SERIAL);
+
+ if (dw_status & US_CSR_RXRDY) {
+ uint32_t received_byte;
+
+ usart_read(USART_SERIAL, &received_byte);
+ usart_write(USART_SERIAL, received_byte);
+ }
+ }
+\endcode
+ *
+ * \subsection usart_use_case_2_usage_flow Workflow
+ * -# When the USART ISR fires, retrieve the USART module interrupt flags:
+ * \code uint32_t dw_status = usart_get_status(USART_SERIAL); \endcode
+ * -# Check if the USART Receive Character interrupt has fired:
+ * \code if (dw_status & US_CSR_RXRDY) \endcode
+ * -# If a character has been received, fetch it into a temporary variable:
+ * \code usart_read(USART_SERIAL, &received_byte); \endcode
+ * -# Echo the character back:
+ * \code usart_write(USART_SERIAL, received_byte); \endcode
+ */
+
+#endif /* USART_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/gpio_api.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "PinNames.h"
+#include "gpio_object.h"
+#include "gpio_api.h"
+#include "compiler.h"
+#include "ioport.h"
+
+extern uint8_t g_sys_init;
+
+uint32_t gpio_set(PinName pin)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+ return (1UL << (pin % 32));
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+ if (g_sys_init == 0) {
+ sysclk_init();
+ system_board_init();
+ g_sys_init = 1;
+ }
+ obj->pin = pin;
+
+ ioport_set_pin_dir(pin, IOPORT_DIR_INPUT);
+ ioport_set_pin_mode(pin, IOPORT_MODE_PULLUP);
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ obj->mode = mode;
+ switch (mode) {
+ case PullNone :
+ ioport_set_pin_mode(obj->pin, IOPORT_MODE_OPEN_DRAIN);
+ break;
+ case PullUp:
+ ioport_set_pin_mode(obj->pin, IOPORT_MODE_PULLUP);
+ break;
+ case PullDown:
+ ioport_set_pin_mode(obj->pin, IOPORT_MODE_PULLDOWN);
+ break;
+ }
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ obj->direction = direction;
+ switch (direction) {
+ case PIN_INPUT :
+ ioport_set_pin_dir(obj->pin, IOPORT_DIR_INPUT);
+ break;
+ case PIN_OUTPUT:
+ ioport_set_pin_dir(obj->pin, IOPORT_DIR_OUTPUT);
+ break;
+ case PIN_INPUT_OUTPUT:
+ ioport_set_pin_dir(obj->pin, IOPORT_DIR_OUTPUT);
+ break;
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/gpio_irq_api.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,188 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "cmsis.h"
+
+#include "gpio_irq_api.h"
+#include "gpio_api.h"
+#include "ioport.h"
+
+#define IRQ_RISE_POSITION 1
+#define IRQ_FALL_POSITION 2
+#define CHANNEL_NUM 48
+#define MAX_PINS_IN_PORT 32
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler irq_handler;
+extern uint8_t g_sys_init;
+
+static IRQn_Type pin_to_irq (uint32_t pin);
+
+void gpio_irq_common_handler(uint32_t port_id)
+{
+ uint32_t i = 0, status = 0, mask = 0, temp = 0;
+ gpio_irq_event event;
+
+ Pio* pio_base = arch_ioport_port_to_base(port_id);
+ mask = pio_base->PIO_IMR;
+ status = pio_base->PIO_ISR;
+ status = status & mask;
+
+ for (i = 0; i < MAX_PINS_IN_PORT ; i++) {
+ temp = (1 << i );
+ if (status & temp ) {
+ if((pio_base->PIO_PDSR) & temp) {
+ event = IRQ_RISE;
+ } else {
+ event = IRQ_FALL;
+ }
+ if(irq_handler) {
+ irq_handler(channel_ids[(port_id * 32) + i], event);
+ }
+ }
+ }
+}
+
+void gpio_irq_porta(void)
+{
+ gpio_irq_common_handler(IOPORT_PIOA);
+}
+
+void gpio_irq_portb(void)
+{
+ gpio_irq_common_handler(IOPORT_PIOB);
+}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+ MBED_ASSERT(obj);
+ if (pin == NC)
+ return -1;
+ if (g_sys_init == 0) {
+ sysclk_init();
+ system_board_init();
+ g_sys_init = 1;
+ }
+
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t port_id;
+ uint32_t vector = 0;
+ uint8_t int_channel = 0;
+ Pio* pio_base;
+
+ irq_handler = handler; // assuming the usage of these apis in mbed layer only
+ int_channel = ((pin / 32) * 32) + (pin % 32); /*to get the channel to be used*/
+ channel_ids[int_channel] = id;
+ obj->pin = pin;
+ port_id = ioport_pin_to_port_id(pin);
+ pio_base = arch_ioport_port_to_base(port_id);
+
+ ioport_set_pin_dir(pin, IOPORT_DIR_INPUT); /*Pin to be configured input for GPIO Interrupt*/
+ ioport_set_pin_mode(pin, IOPORT_MODE_PULLUP);
+
+ irq_n = pin_to_irq(pin);
+
+ switch (port_id) {
+ /*only 2 ports for SAMG55*/ /*Setting up the vectors*/
+ case IOPORT_PIOA :
+ vector = (uint32_t)gpio_irq_porta;
+ break;
+ case IOPORT_PIOB :
+ vector = (uint32_t)gpio_irq_portb;
+ break;
+ }
+ pio_base->PIO_ISR; /*To read and clear status register*/
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+
+ return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+ MBED_ASSERT(obj);
+ channel_ids[((obj->pin / 32) * 32) + (obj->pin % 32)] = 0;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+ MBED_ASSERT(obj);
+ uint32_t mask = 0;
+
+ Pio* pio_base = arch_ioport_port_to_base(arch_ioport_pin_to_port_id(obj->pin));
+ mask = (1 << (obj->pin % 32));
+
+ if (enable) {
+ if (event == IRQ_RISE) {
+ obj->irqmask |= IRQ_RISE_POSITION;
+ } else if (event == IRQ_FALL) {
+ obj->irqmask |= IRQ_FALL_POSITION;
+ }
+ } else {
+
+ if (event == IRQ_RISE) {
+ obj->irqmask &= ~IRQ_RISE_POSITION;
+ } else if (event == IRQ_FALL) {
+ obj->irqmask &= ~IRQ_FALL_POSITION;
+ }
+ }
+ pio_base->PIO_ISR; /*To read and clear status register*/
+ if (obj->irqmask == (IRQ_RISE_POSITION | IRQ_FALL_POSITION)) { /*both edge detection*/
+ pio_base->PIO_AIMDR = mask;
+ pio_base->PIO_IER = mask;
+ } else if (obj->irqmask == IRQ_RISE_POSITION) { /*rising detection*/
+ pio_base->PIO_ESR = mask;
+ pio_base->PIO_REHLSR = mask;
+ pio_base->PIO_AIMER = mask;
+ pio_base->PIO_IER = mask;
+ } else if (obj->irqmask == IRQ_FALL_POSITION) { /*falling detection*/
+ pio_base->PIO_ESR = mask;
+ pio_base->PIO_FELLSR = mask;
+ pio_base->PIO_AIMER = mask;
+ pio_base->PIO_IER = mask;
+ } else { /*none and disable*/
+ pio_base->PIO_IDR = mask;
+ }
+}
+
+static IRQn_Type pin_to_irq (uint32_t pin)
+{
+ uint32_t port_id;
+ IRQn_Type irq_n = (IRQn_Type)0;
+ port_id = ioport_pin_to_port_id(pin);
+
+ switch (port_id) {
+ case IOPORT_PIOA :
+ irq_n = PIOA_IRQn;
+ break;
+ case IOPORT_PIOB :
+ irq_n = PIOB_IRQn;
+ break;
+ }
+ return irq_n;
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+ MBED_ASSERT(obj);
+ NVIC_EnableIRQ(pin_to_irq(obj->pin));
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+ MBED_ASSERT(obj);
+ NVIC_DisableIRQ(pin_to_irq(obj->pin));
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/gpio_object.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+#include "ioport.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint8_t mode;
+ uint8_t direction;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ if (value)
+ ioport_set_pin_level(obj->pin, IOPORT_PIN_LEVEL_HIGH);
+ else
+ ioport_set_pin_level(obj->pin, IOPORT_PIN_LEVEL_LOW);
+}
+
+static inline int gpio_read(gpio_t *obj)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ return (ioport_get_pin_level(obj->pin) ? 1 : 0);
+}
+
+static inline int gpio_is_connected(const gpio_t *obj)
+{
+ return obj->pin != (PinName)NC;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/i2c_api.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,715 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "device.h"
+#include "buffer.h"
+#include "dma_api.h"
+#include "i2c_api.h"
+#include "PeripheralPins.h"
+#include "twi.h"
+#include "pdc.h"
+#include "mbed_assert.h"
+#include "ioport.h"
+
+/**
+ * \defgroup GeneralI2C I2C Configuration Functions
+ * @{
+ */
+
+/** TWI Bus Clock 400kHz */
+extern uint8_t g_sys_init;
+
+#define TWI_CLK (400000u)
+
+#define ADDR_LENGTH 0
+
+#define MAX_I2C 8
+
+extern uint32_t twi_mk_addr(const uint8_t *addr, int len);
+
+void pinmap_find_i2c_info(Twi *sercombase, i2c_t *obj)
+{
+ if(sercombase==TWI0) {
+ obj->i2c.flexcom=FLEXCOM0;
+ obj->i2c.module_number=0;
+ obj->i2c.pdc =PDC_TWI0;
+ obj->i2c.irq_type=FLEXCOM0_IRQn;
+ } else if(sercombase==TWI1) {
+ obj->i2c.flexcom=FLEXCOM1;
+ obj->i2c.module_number=1;
+ obj->i2c.pdc =PDC_TWI1;
+ obj->i2c.irq_type=FLEXCOM1_IRQn;
+ } else if(sercombase==TWI2) {
+ obj->i2c.flexcom=FLEXCOM2;
+ obj->i2c.module_number=2;
+ obj->i2c.pdc =PDC_TWI2;
+ obj->i2c.irq_type=FLEXCOM2_IRQn;
+ } else if(sercombase==TWI3) {
+ obj->i2c.flexcom=FLEXCOM3;
+ obj->i2c.module_number=3;
+ obj->i2c.pdc =PDC_TWI3;
+ obj->i2c.irq_type=FLEXCOM3_IRQn;
+ } else if(sercombase==TWI4) {
+ obj->i2c.flexcom=FLEXCOM4;
+ obj->i2c.module_number=4;
+ obj->i2c.pdc =PDC_TWI4;
+ obj->i2c.irq_type=FLEXCOM4_IRQn;
+ } else if(sercombase==TWI5) {
+ obj->i2c.flexcom=FLEXCOM5;
+ obj->i2c.module_number=5;
+ obj->i2c.pdc =PDC_TWI5;
+ obj->i2c.irq_type=FLEXCOM5_IRQn;
+ } else if(sercombase==TWI6) {
+ obj->i2c.flexcom=FLEXCOM6;
+ obj->i2c.module_number=6;
+ obj->i2c.pdc =PDC_TWI6;
+ obj->i2c.irq_type=FLEXCOM6_IRQn;
+ } else if(sercombase==TWI7) {
+ obj->i2c.flexcom=FLEXCOM7;
+ obj->i2c.module_number=7;
+ obj->i2c.pdc =PDC_TWI7;
+ obj->i2c.irq_type=FLEXCOM7_IRQn;
+ } else {
+ obj->i2c.flexcom=(Flexcom *)NC;
+ obj->i2c.module_number=0;
+ obj->i2c.pdc =(Pdc *) NC;
+ }
+}
+
+
+/** Initialize the I2C peripheral. It sets the default parameters for I2C
+ * peripheral, and configure its specifieds pins.
+ * @param obj The i2c object
+ * @param sda The sda pin
+ * @param scl The scl pin
+ */
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+ MBED_ASSERT(obj);
+ MBED_ASSERT(sda !=NC && scl!=NC );
+
+ if (g_sys_init == 0) {
+ sysclk_init();
+ board_init();
+ g_sys_init = 1;
+ }
+
+
+ Twi* sda_base = (Twi*)pinmap_peripheral(sda, PinMap_I2C_SDA);
+ Twi* scl_base = (Twi*)pinmap_peripheral(scl, PinMap_I2C_SCL);
+ Twi* I2cBase = (Twi*)pinmap_merge((uint32_t)sda_base, (uint32_t)scl_base);
+
+ MBED_ASSERT(I2cBase !=NC );
+
+ obj->i2c.i2c_base=I2cBase;
+ pinmap_find_i2c_info(I2cBase,obj);
+
+ /* Configure I2C pins */
+ pin_function(sda, pinmap_find_function(sda, PinMap_I2C_SDA));
+ ioport_disable_pin(sda);
+
+ pin_function(scl, pinmap_find_function(scl, PinMap_I2C_SCL));
+ ioport_disable_pin(scl);
+
+#if (SAMG55)
+ /* Enable the peripheral and set TWI mode. */
+ MBED_ASSERT((int)obj->i2c.flexcom!=NC);
+ flexcom_enable(obj->i2c.flexcom);
+ flexcom_set_opmode(obj->i2c.flexcom, FLEXCOM_TWI);
+#else
+ /* Enable the peripheral clock for TWI */
+ pmc_enable_periph_clk(obj->i2c.i2c_base);
+#endif
+
+ twi_options_t twi_options;
+ twi_options.master_clk=sysclk_get_cpu_hz();
+ twi_options.speed=TWI_CLK;
+ twi_options.smbus = 0;
+
+ twi_master_init(obj->i2c.i2c_base,&twi_options);
+
+ obj->i2c.is_slave=false;
+ obj->i2c.speed=TWI_CLK;
+ obj->i2c.master_clk=twi_options.master_clk;
+}
+
+/** Configure the I2C frequency.
+ * @param obj The i2c object
+ * @param hz Frequency in Hz
+ */
+void i2c_frequency(i2c_t *obj, int hz)
+{
+ MBED_ASSERT(obj);
+ if(obj->i2c.is_slave)
+ twi_disable_slave_mode(obj->i2c.i2c_base);
+ else
+ twi_disable_master_mode(obj->i2c.i2c_base);
+
+ twi_set_speed(obj->i2c.i2c_base,hz,obj->i2c.master_clk);
+
+ if(obj->i2c.is_slave)
+ twi_enable_slave_mode(obj->i2c.i2c_base);
+ else
+ twi_enable_master_mode(obj->i2c.i2c_base);
+}
+
+/** Send START command.
+ * @param obj The i2c object
+ */
+int i2c_start(i2c_t *obj)
+{
+ MBED_ASSERT(obj);
+ obj->i2c.i2c_base->TWI_CR = TWI_CR_START;
+ return 0;
+}
+
+/** Send STOP command.
+ * @param obj The i2c object
+ */
+int i2c_stop(i2c_t *obj)
+{
+ MBED_ASSERT(obj);
+ obj->i2c.i2c_base->TWI_CR = TWI_CR_STOP;
+ return 0;
+}
+
+
+uint32_t twi_master_read_no_stop(Twi *p_twi, twi_packet_t *p_packet, uint8_t stopena)
+{
+ uint32_t status;
+ uint32_t cnt = p_packet->length;
+ uint8_t *buffer = p_packet->buffer;
+ uint8_t stop_sent = 0;
+ uint32_t timeout = TWI_TIMEOUT;;
+
+ /* Check argument */
+ if (cnt == 0) {
+ return TWI_INVALID_ARGUMENT;
+ }
+
+ /* Set read mode, slave address and 3 internal address byte lengths */
+ p_twi->TWI_MMR = 0;
+ p_twi->TWI_MMR = TWI_MMR_MREAD | TWI_MMR_DADR(p_packet->chip) |
+ ((p_packet->addr_length << TWI_MMR_IADRSZ_Pos) &
+ TWI_MMR_IADRSZ_Msk);
+
+ /* Send a START condition */
+ if ((cnt == 1) && (stopena == 1)) {
+ p_twi->TWI_CR = TWI_CR_START | TWI_CR_STOP;
+ stop_sent = 1;
+ } else {
+ p_twi->TWI_CR = TWI_CR_START;
+ stop_sent = 0;
+ }
+
+ while (cnt > 0) {
+ status = p_twi->TWI_SR;
+ if (status & TWI_SR_NACK) {
+ return TWI_RECEIVE_NACK;
+ }
+
+ if (!timeout--) {
+ return TWI_ERROR_TIMEOUT;
+ }
+
+ /* Last byte ? */
+ if ((cnt == 1) && (!stop_sent) && (stopena == 1)) {
+ p_twi->TWI_CR = TWI_CR_STOP;
+ stop_sent = 1;
+ }
+
+ if (!(status & TWI_SR_RXRDY)) {
+ continue;
+ }
+ *buffer++ = p_twi->TWI_RHR;
+
+ cnt--;
+ timeout = TWI_TIMEOUT;
+ }
+ if(stopena) {
+ while (!(p_twi->TWI_SR & TWI_SR_TXCOMP)) {
+ }
+ }
+
+ p_twi->TWI_SR;
+
+ return TWI_SUCCESS;
+
+}
+
+
+
+
+
+/** Blocking reading data.
+ * @param obj The i2c object
+ * @param address 7-bit address (last bit is 1)
+ * @param data The buffer for receiving
+ * @param length Number of bytes to read
+ * @param stop Stop to be generated after the transfer is done
+ * @return Number of read bytes
+ */
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+ MBED_ASSERT(obj);
+
+ twi_packet_t packet;
+ packet.chip= (address>>1) & 0x7F;
+ packet.addr_length=ADDR_LENGTH;
+ packet.buffer=data;
+ packet.length=length;
+
+ uint8_t status;
+ status= twi_master_read_no_stop(obj->i2c.i2c_base, &packet, stop);
+
+ if(TWI_SUCCESS==status)
+ return length;
+
+ return 0;
+}
+
+
+uint32_t twi_master_write_no_stop(Twi *p_twi, twi_packet_t *p_packet, uint8_t stopena)
+{
+ uint32_t status;
+ uint32_t cnt = p_packet->length;
+ uint8_t *buffer = p_packet->buffer;
+
+ /* Check argument */
+ if (cnt == 0) {
+ return TWI_INVALID_ARGUMENT;
+ }
+
+ /* Set write mode, slave address and 3 internal address byte lengths */
+ p_twi->TWI_MMR = 0;
+ p_twi->TWI_MMR = TWI_MMR_DADR(p_packet->chip) |
+ ((p_packet->addr_length << TWI_MMR_IADRSZ_Pos) &
+ TWI_MMR_IADRSZ_Msk);
+
+ /* Send a START condition */
+ if ((cnt == 1) && (stopena == 1)) {
+ p_twi->TWI_CR = TWI_CR_START | TWI_CR_STOP;
+ } else {
+ p_twi->TWI_CR = TWI_CR_START;
+ }
+
+ /* Send all bytes */
+ while (cnt > 0) {
+ status = p_twi->TWI_SR;
+ if (status & TWI_SR_NACK) {
+ return TWI_RECEIVE_NACK;
+ }
+
+ if (!(status & TWI_SR_TXRDY)) {
+ continue;
+ }
+ p_twi->TWI_THR = *buffer++;
+
+ cnt--;
+ }
+
+ while (1) {
+ status = p_twi->TWI_SR;
+ if (status & TWI_SR_NACK) {
+ return TWI_RECEIVE_NACK;
+ }
+
+ if (status & TWI_SR_TXRDY) {
+ break;
+ }
+ }
+
+ if (stopena) {
+ p_twi->TWI_CR = TWI_CR_STOP;
+ while (!(p_twi->TWI_SR & TWI_SR_TXCOMP));
+ }
+
+ return TWI_SUCCESS;
+}
+
+
+
+/** Blocking sending data.
+ * @param obj The i2c object
+ * @param address 7-bit address (last bit is 0)
+ * @param data The buffer for sending
+ * @param length Number of bytes to wrte
+ * @param stop Stop to be generated after the transfer is done
+ * @return Number of written bytes
+ */
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+ MBED_ASSERT(obj);
+
+ twi_packet_t packet;
+ packet.chip= (address>>1) & 0x7F;
+ packet.addr_length=ADDR_LENGTH;
+ packet.buffer= (void *)data;
+ packet.length=length;
+
+ uint8_t status;
+ status= twi_master_write_no_stop(obj->i2c.i2c_base,&packet, stop);
+
+ if(TWI_SUCCESS==status)
+ return length;
+
+ return 0;
+}
+
+/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop().
+ * @param obj The i2c object
+ */
+void i2c_reset(i2c_t *obj)
+{
+ MBED_ASSERT(obj);
+ twi_reset(obj->i2c.i2c_base);
+}
+
+/** Read one byte.
+ * @param obj The i2c object
+ * @param last Acknoledge
+ * @return The read byte
+ */
+int i2c_byte_read(i2c_t *obj, int last)
+{
+ MBED_ASSERT(obj);
+ if(!last)
+ twi_enable_slave_nack(obj->i2c.i2c_base);
+
+ return twi_read_byte(obj->i2c.i2c_base);
+}
+
+/** Write one byte.
+ * @param obj The i2c object
+ * @param data Byte to be written
+ * @return 1 if NAK was received, 0 if ACK was received, 2 for timeout.
+ */
+#define ACK 0
+#define NAK 1
+#define TIMEOUT 2
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+ MBED_ASSERT(obj);
+ twi_write_byte(obj->i2c.i2c_base,data);
+
+ uint32_t timeout = TWI_TIMEOUT;
+ while (timeout--) {
+ uint32_t status = obj->i2c.i2c_base->TWI_SR;
+ if (status & TWI_SR_NACK) {
+ return NAK;
+ }
+
+ if (status & TWI_SR_TXRDY) {
+ return ACK;
+ }
+
+ if (timeout<1) {
+ return TIMEOUT;
+ }
+ }
+
+ return ACK;
+}
+
+/**@}*/
+
+#if DEVICE_I2CSLAVE
+
+/**
+ * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave
+ * @{
+ */
+
+/** Configure I2C as slave or master.
+ * @param obj The I2C object
+ * @return non-zero if a value is available
+ */
+void i2c_slave_mode(i2c_t *obj, int enable_slave)
+{
+ MBED_ASSERT(obj);
+ /* Disable TWI interrupts */
+ obj->i2c.i2c_base->TWI_IDR = ~0UL;
+ obj->i2c.i2c_base->TWI_SR;
+
+ /* Reset TWI */
+ twi_reset(obj->i2c.i2c_base);
+
+ MBED_ASSERT(obj);
+ if(enable_slave)
+ twi_enable_slave_mode(obj->i2c.i2c_base);
+ else
+ twi_enable_master_mode(obj->i2c.i2c_base);
+}
+
+/** Check to see if the I2C slave has been addressed.
+ * @param obj The I2C object
+ * @return The status - 1 - read addresses, 2 - write to all slaves,
+ * 3 write addressed, 0 - the slave has not been addressed
+ */
+int i2c_slave_receive(i2c_t *obj)
+{
+ uint32_t status = obj->i2c.i2c_base->TWI_SR;
+ if((status & TWI_SR_SVACC)) {
+ if(status & TWI_SR_SVREAD)
+ return 1;
+ else
+ return 3;
+ }
+ return 0;
+}
+
+
+uint32_t twi_slave_read_n(Twi *p_twi, uint8_t *p_data, int length)
+{
+ uint32_t status, cnt = 0;
+
+ do {
+ status = p_twi->TWI_SR;
+ if (status & TWI_SR_SVACC) {
+ if (!(status & (TWI_SR_GACC| TWI_SR_SVREAD )) &&
+ (status & TWI_SR_RXRDY)
+ ) {
+ *p_data++ = (uint8_t) p_twi->TWI_RHR;
+ cnt++;
+ if(cnt>=length) break;
+ }
+ } else if ((status & (TWI_SR_EOSACC | TWI_SR_TXCOMP))
+ == (TWI_SR_EOSACC | TWI_SR_TXCOMP)) {
+ break;
+ }
+ } while (1);
+
+ return cnt;
+}
+
+/** Read I2C slave.
+ * @param obj The I2C object
+ * @return non-zero if a value is available
+ */
+int i2c_slave_read(i2c_t *obj, char *data, int length)
+{
+ MBED_ASSERT(obj);
+ int read= twi_slave_read_n(obj->i2c.i2c_base,(uint8_t *) data,length);
+ return read;
+}
+
+
+uint32_t twi_slave_write_n(Twi *p_twi, uint8_t *p_data, int length)
+{
+ uint32_t status, cnt = 0;
+
+ do {
+ status = p_twi->TWI_SR;
+ if (status & TWI_SR_SVACC) {
+ if ((status & TWI_SR_SVREAD) && !(status & TWI_SR_GACC) &&
+ (status & TWI_SR_TXRDY)) {
+ p_twi->TWI_THR = *p_data++;
+ cnt++;
+ if(cnt>=length) break;
+ }
+ } else if ((status & (TWI_SR_EOSACC | TWI_SR_TXCOMP))
+ == (TWI_SR_EOSACC | TWI_SR_TXCOMP)) {
+ break;
+ }
+ } while (1);
+
+ return cnt;
+}
+
+
+/** Write I2C as slave.
+ * @param obj The I2C object
+ * @return non-zero if a value is available
+ */
+int i2c_slave_write(i2c_t *obj, const char *data, int length)
+{
+ MBED_ASSERT(obj);
+ int write= twi_slave_write_n(obj->i2c.i2c_base, (uint8_t *) data,length);
+ return write;
+}
+
+/** Configure I2C address.
+ * @param obj The I2C object
+ * @param idx Currently not used
+ * @param address The address to be set
+ * @param mask Currently not used
+ */
+void i2c_slave_address(i2c_t *obj, int idx/*not used*/, uint32_t address, uint32_t mask)
+{
+ MBED_ASSERT(obj);
+ twi_set_slave_addr(obj->i2c.i2c_base, (address>>1));
+}
+
+#endif
+
+/**@}*/
+
+#if DEVICE_I2C_ASYNCH
+
+/**
+ * \defgroup AsynchI2C Asynchronous I2C Hardware Abstraction Layer
+ * @{
+ */
+
+/** Start i2c asynchronous transfer.
+ * @param obj The I2C object
+ * @param tx The buffer to send
+ * @param tx_length The number of words to transmit
+ * @param rx The buffer to receive
+ * @param rx_length The number of words to receive
+ * @param address The address to be set - 7bit or 9 bit
+ * @param stop If true, stop will be generated after the transfer is done
+ * @param handler The I2C IRQ handler to be set
+ * @param hint DMA hint usage
+ */
+#warning "Only DMA async supported by I2C master transfer"
+
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint /*Not Used*/)
+{
+ uint32_t pdcenable=0;
+
+ if(address) {
+ twi_packet_t pdc_packet;
+ pdc_packet.chip=(address>>1) & 0x7F;
+ pdc_packet.addr_length=ADDR_LENGTH;
+
+ /* Set write mode, slave address and 3 internal address byte lengths */
+ obj->i2c.i2c_base->TWI_MMR = 0;
+ obj->i2c.i2c_base->TWI_MMR = TWI_MMR_DADR(pdc_packet.chip) |
+ ((pdc_packet.addr_length << TWI_MMR_IADRSZ_Pos) &
+ TWI_MMR_IADRSZ_Msk);
+ }
+
+ if(tx) {
+ pdc_packet_t pdc_packet_tx;
+ pdc_packet_tx.ul_addr=(uint32_t)tx;
+ pdc_packet_tx.ul_size=tx_length;
+
+ pdcenable|=PERIPH_PTCR_TXTEN;
+ /* Configure PDC for data send */
+ pdc_tx_init(obj->i2c.pdc, &pdc_packet_tx, NULL);
+ }
+
+ if(rx) {
+ obj->i2c.i2c_base->TWI_MMR |= TWI_MMR_MREAD;
+ pdc_rx_clear_cnt(obj->i2c.pdc);
+ pdc_packet_t pdc_packet_rx;
+ pdc_packet_rx.ul_addr=(uint32_t)rx;
+ pdc_packet_rx.ul_size=rx_length;
+ pdcenable|=PERIPH_PTCR_RXTEN;
+
+ /* Configure PDC for data receive */
+ pdc_rx_init(obj->i2c.pdc, &pdc_packet_rx, NULL);
+ }
+
+ obj->i2c.dma_usage=hint;
+ obj->i2c.event=event;
+ obj->i2c.stop=stop;
+ obj->i2c.address=address;
+
+ NVIC_ClearPendingIRQ(obj->i2c.irq_type);
+ NVIC_DisableIRQ(obj->i2c.irq_type);
+ NVIC_SetVector(obj->i2c.irq_type,handler);
+ NVIC_EnableIRQ(obj->i2c.irq_type);
+
+ /* Enable TWI IRQ */
+ twi_enable_interrupt(obj->i2c.i2c_base, TWI_IER_RXBUFF| TWI_IER_TXBUFE | TWI_IER_UNRE | TWI_IER_OVRE | TWI_IER_PECERR);
+
+ /* Enable PDC transfers */
+ pdc_enable_transfer(obj->i2c.pdc, pdcenable );
+
+}
+
+/** The asynchronous IRQ handler
+ * @param obj The I2C object which holds the transfer information
+ * @return event flags if a transfer termination condition was met or 0 otherwise.
+ */
+uint32_t i2c_irq_handler_asynch(i2c_t *obj)
+{
+ uint32_t event=0;
+
+ if(obj->i2c.stop) {
+ i2c_stop(obj);
+ }
+
+ // Data transferred via DMA
+ if((obj->i2c.i2c_base->TWI_SR & TWI_IER_TXBUFE)) {
+ twi_disable_interrupt(obj->i2c.i2c_base, TWI_IDR_TXBUFE | TWI_IDR_UNRE | TWI_IDR_OVRE | TWI_IDR_PECERR);
+ if(obj->i2c.event | I2C_EVENT_TRANSFER_COMPLETE)
+ event |=I2C_EVENT_TRANSFER_COMPLETE;
+ }
+
+ if((obj->i2c.i2c_base->TWI_SR & TWI_IER_RXBUFF)) {
+ twi_disable_interrupt(obj->i2c.i2c_base, TWI_IDR_RXBUFF | TWI_IDR_UNRE | TWI_IDR_OVRE | TWI_IDR_PECERR);
+ if(obj->i2c.event | I2C_EVENT_TRANSFER_COMPLETE)
+ event |=I2C_EVENT_TRANSFER_COMPLETE;
+ }
+
+ if(obj->i2c.i2c_base->TWI_SR & TWI_IER_NACK) {
+ if(obj->i2c.event | I2C_EVENT_TRANSFER_EARLY_NACK)
+ event |=I2C_EVENT_TRANSFER_EARLY_NACK;
+ }
+
+
+ if((obj->i2c.i2c_base->TWI_SR & TWI_IER_UNRE) || (obj->i2c.i2c_base->TWI_SR & TWI_IER_OVRE) || (obj->i2c.i2c_base->TWI_SR & TWI_IER_PECERR) || (obj->i2c.i2c_base->TWI_SR & TWI_SR_TOUT) ) {
+ if((obj->i2c.event | I2C_EVENT_ERROR))
+ event |=I2C_EVENT_ERROR;
+
+ if(obj->i2c.address) {
+ uint8_t status= twi_probe(obj->i2c.i2c_base,obj->i2c.address);
+ if((obj->i2c.event | I2C_EVENT_ERROR_NO_SLAVE) && (status!=TWI_SUCCESS) )
+ event |=I2C_EVENT_ERROR_NO_SLAVE;
+ }
+ }
+
+ return event;
+}
+
+/** Attempts to determine if I2C peripheral is already in use.
+ * @param obj The I2C object
+ * @return non-zero if the I2C module is active or zero if it is not
+ */
+uint8_t i2c_active(i2c_t *obj)
+{
+
+ if(obj->i2c.i2c_base->TWI_SR & TWI_SR_ENDTX && obj->i2c.i2c_base->TWI_SR & TWI_SR_ENDRX)
+ return 0;
+
+ return 1;
+
+}
+
+/** Abort ongoing asynchronous transaction.
+ * @param obj The I2C object
+ */
+void i2c_abort_asynch(i2c_t *obj)
+{
+ /* Disable PDC transfers */
+ pdc_disable_transfer(obj->i2c.pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);
+
+ /* Clear PDC buffer receive counter */
+ pdc_rx_clear_cnt(obj->i2c.pdc);
+
+ /* Disable I2C IRQ */
+ twi_disable_interrupt(obj->i2c.i2c_base, TWI_IDR_TXBUFE);
+ twi_disable_interrupt(obj->i2c.i2c_base, TWI_IDR_RXBUFF);
+
+ /* Disable I2C interrupt */
+ NVIC_DisableIRQ(obj->i2c.irq_type);
+}
+
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/lp_ticker.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,133 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis.h"
+#include <stddef.h>
+#include "lp_ticker_api.h"
+#include "mbed_assert.h"
+#include "sleep_api.h"
+#include "compiler.h"
+#include "sysclk.h"
+#include "tc.h"
+#include "us_ticker_api.h"
+
+uint8_t lp_ticker_inited = 0;
+extern volatile uint8_t us_ticker_inited;
+extern uint8_t g_sys_init;
+extern volatile uint32_t overflow32bitcounter;
+volatile uint16_t lp_ticker_16bit_counter;
+volatile uint16_t lp_ticker_interrupt_counter;
+volatile uint16_t lp_ticker_interrupt_offset;
+volatile uint32_t lpoverflow32bitcounter = 0;
+
+#define TICKER_COUNTER_lp TC0
+
+#define TICKER_COUNTER_CLK2 ID_TC2
+
+#define TICKER_COUNTER_CHANNEL2 2
+#define TICKER_COUNTER_IRQn2 TC2_IRQn
+#define TICKER_COUNTER_Handlr2 TC2_Handler
+
+#define OVERFLOW_16bit_VALUE 0xFFFF
+
+
+void TICKER_COUNTER_Handlr2(void)
+{
+ uint32_t status=tc_get_status(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2);
+ uint32_t interrupmask=tc_get_interrupt_mask(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2);
+
+ if (((status & interrupmask) & TC_IER_CPCS)) {
+ if(lp_ticker_interrupt_counter) {
+ lp_ticker_interrupt_counter--;
+ } else {
+ if(lp_ticker_interrupt_offset) {
+ tc_stop(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2);
+ tc_write_rc(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2, (uint32_t)lp_ticker_interrupt_offset);
+ tc_start(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2);
+ lp_ticker_interrupt_offset=0;
+ } else {
+ lp_ticker_irq_handler();
+ }
+ }
+ }
+}
+
+void lp_ticker_init(void)
+{
+ if(lp_ticker_inited)
+ return;
+ if (!us_ticker_inited)
+ us_ticker_init();
+ sysclk_enable_peripheral_clock(TICKER_COUNTER_CLK2);
+ tc_init(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2, TC_CMR_TCCLKS_TIMER_CLOCK4);
+ lp_ticker_inited = 1;
+}
+
+uint32_t lp_ticker_read()
+{
+ if (!lp_ticker_inited)
+ lp_ticker_init();
+ return us_ticker_read();
+}
+
+void lp_ticker_set_interrupt(timestamp_t timestamp)
+{
+ uint32_t cur_time;
+ int32_t delta;
+
+ cur_time = lp_ticker_read();
+ delta = (int32_t)((uint32_t)timestamp - cur_time);
+ if (delta < 0) {
+ /* Event already occurred in past */
+ lp_ticker_irq_handler();
+ return;
+ }
+
+ uint16_t interruptat=0;
+
+ if(delta > OVERFLOW_16bit_VALUE) {
+ lp_ticker_interrupt_counter= (delta/OVERFLOW_16bit_VALUE) -1;
+ lp_ticker_interrupt_offset=delta%OVERFLOW_16bit_VALUE;
+ interruptat=OVERFLOW_16bit_VALUE;
+ } else {
+ lp_ticker_interrupt_counter=0;
+ lp_ticker_interrupt_offset=0;
+ interruptat=delta;
+ }
+
+ NVIC_DisableIRQ(TICKER_COUNTER_IRQn2);
+
+ tc_write_rc(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2, (uint32_t)interruptat);
+
+ NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn2);
+ NVIC_SetPriority(TICKER_COUNTER_IRQn2, 0);
+ NVIC_EnableIRQ(TICKER_COUNTER_IRQn2);
+ tc_enable_interrupt(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2, TC_IDR_CPCS );
+
+ tc_start(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2);
+}
+
+void lp_ticker_disable_interrupt(void)
+{
+ tc_stop(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2);
+ tc_disable_interrupt(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2, TC_IDR_CPCS);
+ NVIC_DisableIRQ(TICKER_COUNTER_IRQn2);
+}
+
+void lp_ticker_clear_interrupt(void)
+{
+ NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn2);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/objects.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,110 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "gpio_object.h"
+#include "serial_platform.h"
+#include "adc2.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct waveconfig_t {
+ /** Internal clock signals selection. */
+ uint32_t ul_intclock;
+ /** Waveform frequency (in Hz). */
+ uint16_t us_frequency;
+ /** Duty cycle in percent (positive).*/
+ uint16_t us_dutycycle;
+};
+
+struct gpio_irq_s {
+ uint32_t pin;
+ uint32_t irqmask;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ uint8_t mode;
+ uint8_t direction;
+};
+
+struct serial_s {
+ UARTName uart;
+ usart_serial_options_t uart_serial_options;
+#if DEVICE_SERIAL_ASYNCH
+ uint8_t actrec;
+ uint8_t acttra;
+ uint32_t events;
+#endif
+};
+
+struct analogin_s {
+ enum adc_channel_num channel;
+};
+
+struct pwmout_s {
+ uint32_t channel;
+ uint32_t ioline;
+ uint32_t pin;
+ uint32_t prescalarindex;
+ struct waveconfig_t waveconfig;
+};
+
+struct i2c_s {
+ Twi * i2c_base;
+ Flexcom * flexcom;
+ uint8_t is_slave;
+ uint8_t module_number;
+ uint32_t speed;
+ uint32_t master_clk;
+ uint32_t address;
+#if DEVICE_I2C_ASYNCH
+ Pdc * pdc;
+ uint8_t dma_usage;
+ IRQn_Type irq_type;
+ uint32_t event;
+ uint32_t stop;
+#endif
+};
+struct spi_s {
+ Spi * spi_base;
+ Flexcom * flexcom;
+ uint8_t cs;
+ uint8_t polarity;
+ uint8_t phase;
+ uint32_t transferrate;
+ uint8_t is_slave;
+ uint8_t module_number;
+#if DEVICE_SPI_ASYNCH
+ Pdc * pdc;
+ uint8_t dma_usage;
+ IRQn_Type irq_type;
+ uint32_t event;
+#endif
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/pinmap.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+
+#include "cmsis.h"
+#include "mbed_assert.h"
+#include "compiler.h"
+
+#include "pinmap.h"
+#include "ioport.h"
+
+/** Change the MUX padding of input pin
+ *
+ * Configure the pin for specific module
+ * @param[in] pin Pin name whose MUX padding is to be changed
+ * @param[in] function The MUX mode to be selected
+ * @return void
+ */
+void pin_function(PinName pin, int function)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+ ioport_set_pin_mode(pin, function);
+}
+
+/** Change the pin pull mode
+ *
+ * Configure the pin pull mode
+ * @param[in] pin Pin name whose MUX padding is to be changed
+ * @param[in] mode Pin pull mode to be set
+ * @return void
+ */
+void pin_mode(PinName pin, PinMode mode)
+{
+ MBED_ASSERT(pin != (PinName)NC);
+ if (mode == PullUp) {
+ ioport_set_pin_mode(pin, IOPORT_MODE_PULLUP);
+ } else if (mode == PullDown) {
+ ioport_set_pin_mode(pin, IOPORT_MODE_PULLDOWN);
+ } else {
+ ioport_set_pin_mode(pin, IOPORT_MODE_OPEN_DRAIN);
+ }
+}
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/port_api.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,92 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+#include "ioport.h"
+
+extern uint8_t g_sys_init;
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+ MBED_ASSERT(obj);
+ if (g_sys_init == 0) {
+ sysclk_init();
+ system_board_init();
+ g_sys_init = 1;
+ }
+ obj->port = port;
+ obj->mask = mask;
+
+ switch (dir) {
+ case PIN_INPUT :
+ ioport_set_port_dir(port, mask, IOPORT_DIR_INPUT);
+ break;
+ case PIN_OUTPUT:
+ ioport_set_port_dir(port, mask, IOPORT_DIR_OUTPUT);
+ break;
+ case PIN_INPUT_OUTPUT:
+ ioport_set_port_dir(port, mask, IOPORT_DIR_OUTPUT);
+ break;
+ }
+ ioport_set_port_mode(port, mask, IOPORT_MODE_PULLUP);
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+ MBED_ASSERT(obj);
+ obj->mode = mode;
+ switch (mode) {
+ case PullNone :
+ ioport_set_port_mode(obj->port, obj->mask, IOPORT_MODE_OPEN_DRAIN);
+ break;
+ case PullUp:
+ ioport_set_port_mode(obj->port, obj->mask, IOPORT_MODE_PULLUP);
+ break;
+ case PullDown:
+ ioport_set_port_mode(obj->port, obj->mask, IOPORT_MODE_PULLDOWN);
+ break;
+ }
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+ MBED_ASSERT(obj);
+ obj->direction = dir;
+ switch (dir) {
+ case PIN_INPUT :
+ ioport_set_port_dir(obj->port, obj->mask, IOPORT_DIR_INPUT);
+ break;
+ case PIN_OUTPUT:
+ ioport_set_port_dir(obj->port, obj->mask, IOPORT_DIR_OUTPUT);
+ break;
+ case PIN_INPUT_OUTPUT:
+ ioport_set_port_dir(obj->port, obj->mask, IOPORT_DIR_OUTPUT);
+ break;
+ }
+}
+
+void port_write(port_t *obj, int value)
+{
+ MBED_ASSERT(obj);
+ ioport_set_port_level(obj->port, obj->mask, value);
+}
+
+int port_read(port_t *obj)
+{
+ MBED_ASSERT(obj);
+ return ioport_get_port_level(obj->port, obj->mask);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/pwmout_api.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,307 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pwmout_api.h"
+
+#include "cmsis.h"
+#include "tc.h"
+#include "sysclk.h"
+#include "PeripheralPins.h"
+
+extern uint8_t g_sys_init;
+
+/** Use TC Peripheral 0 **/
+#define TC TC0
+
+static const uint32_t tc_prescalar[] = {
+ TC_CMR_TCCLKS_TIMER_CLOCK1, // MCK/2
+ TC_CMR_TCCLKS_TIMER_CLOCK2, // MCK/8
+ TC_CMR_TCCLKS_TIMER_CLOCK3, // MCK/32
+ TC_CMR_TCCLKS_TIMER_CLOCK4, // MCK/128
+};
+static const uint32_t tc_prescalar_divider[] = {
+ 2, // MCK/2
+ 8, // MCK/8
+ 32, // MCK/32
+ 128 // MCK/128
+};
+
+uint32_t getpwmchannelid (uint32_t channel)
+{
+ switch (channel) {
+ case 0 :
+ return ID_TC0;
+ case 1 :
+ return ID_TC1;
+ case 2 :
+ return ID_TC2;
+ default :
+ MBED_ASSERT(false);
+ break;
+ }
+}
+
+uint32_t getprescalarindex (uint16_t frequency)
+{
+ float time_period_ms;
+ time_period_ms = (1.0 / (float)frequency) * 1000.0;
+ if (time_period_ms <= 1.0) {
+ return 0;
+ } else if ((time_period_ms > 1.0) && (time_period_ms <= 4.0)) {
+ return 1;
+ } else if ((time_period_ms > 4.0) && (time_period_ms <= 16.0)) {
+ return 2;
+ } else {
+ return 3;
+ }
+}
+
+static void setregisterabc (pwmout_t* obj)
+{
+ uint32_t ra, rb, rc;
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ /* Configure waveform frequency and duty cycle. */
+ rc = (sysclk_get_peripheral_bus_hz(TC) /
+ tc_prescalar_divider[obj->prescalarindex] )/
+ obj->waveconfig.us_frequency;
+ tc_write_rc(TC, obj->channel, rc);
+ switch (obj->ioline) {
+ case 0 :
+ ra = (100 - obj->waveconfig.us_dutycycle) * rc / 100;
+ if(ra <= 0) ra = 1; /*non zero value only*/
+ tc_write_ra(TC, obj->channel, ra);
+ break;
+ case 1 :
+ rb = (100 - obj->waveconfig.us_dutycycle) * rc / 100;
+ if(rb <= 0) rb = 1; /*non zero value only*/
+ tc_write_rb(TC, obj->channel, rb);
+ break;
+ default :
+ MBED_ASSERT(false);
+ break;
+ }
+}
+
+void pwmout_inithw(pwmout_t* obj)
+{
+ uint32_t mode = 0;
+ /* Configure the PMC to enable the TC module. */
+ sysclk_enable_peripheral_clock(getpwmchannelid(obj->channel));
+#if SAMG55
+ /* Enable PCK output */
+ pmc_disable_pck(PMC_PCK_3);
+ pmc_switch_pck_to_mck(PMC_PCK_3, PMC_PCK_PRES_CLK_1);
+ pmc_enable_pck(PMC_PCK_3);
+#endif
+ switch (obj->ioline) {
+ case 0 :
+ mode = TC_CMR_ACPA_SET | TC_CMR_ACPC_CLEAR; /* RA Compare Effect: set */ /* RC Compare Effect: clear */
+ break;
+ case 1 :
+ mode = TC_CMR_BCPB_SET | TC_CMR_BCPC_CLEAR | TC_CMR_ABETRG; /* RB Compare Effect: set */ /* RC Compare Effect: clear */ /*Change external event selection from TIOB*/
+ break;
+ default :
+ MBED_ASSERT(false);
+ break;
+ }
+ /* Disable TC TC_CHANNEL_WAVEFORM. */
+ tc_stop(TC, obj->channel);
+ /* Init TC to waveform mode. */
+ tc_init(TC, obj->channel,
+ /* Waveform Clock Selection */
+ obj->waveconfig.ul_intclock
+ | TC_CMR_WAVE /* Waveform mode is enabled */
+ | TC_CMR_CPCTRG /* UP mode with automatic trigger on RC Compare */
+ | mode
+ );
+}
+
+/** Initialize PWM Module
+ *
+ * @param[in][out] obj The PWM object to initialize
+ * @return void
+ */
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ uint32_t ioline = NC;
+ uint32_t channel = NC;
+
+ if (g_sys_init == 0) {
+ sysclk_init();
+ system_board_init();
+ g_sys_init = 1;
+ }
+ if(pin != NC) {
+ pin_function(pin, pinmap_find_function(pin, PinMap_PWM));
+ ioport_disable_pin(pin);
+ }
+ obj->pin = pin;
+
+ ioline = pinmap_find_function(pin, PinMap_PWM_IO_Line); /*To find out which IO Line is associated with the pin and initialise accordingly*/ /*pinmap_find_function reused to find out iolin used*/
+ MBED_ASSERT(ioline != NC);
+ obj->ioline = ioline;
+
+ channel = pinmap_find_peripheral(pin, PinMap_PWM_IO_Line); /* PinMap_PWM_IO_Line contains channel number and ioline to be used*/ /*pinmap_find_peripheral function reused to find out channel number*/
+ MBED_ASSERT(channel != NC);
+ obj->channel = channel;
+ obj->waveconfig.us_frequency = 500;
+ obj->waveconfig.us_dutycycle = 50;
+
+ obj->prescalarindex = getprescalarindex(obj->waveconfig.us_frequency);
+ obj->waveconfig.ul_intclock = tc_prescalar[obj->prescalarindex];
+ pwmout_inithw(obj);
+
+ /*Set the registers a,b,c*/
+ setregisterabc(obj);
+
+ /* Enable TC TC_CHANNEL_WAVEFORM. */
+ tc_start(TC, channel);
+}
+
+/** Free the PWM Module
+ *
+ * @param[in] obj The PWM object to free
+ * @return void
+ */
+void pwmout_free(pwmout_t* obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ tc_stop(TC, obj->channel);
+}
+
+/** Set the duty cycle of PWM Waveform
+ *
+ * @param[in] obj The PWM object
+ * @param[in] value New duty cycle to be set
+ * @return void
+ */
+void pwmout_write(pwmout_t* obj, float value)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ if (value < 0.0f) {
+ value = 0;
+ } else if (value > 1.0f) {
+ value = 1;
+ }
+ obj->waveconfig.us_dutycycle = (uint16_t)(value * 100);
+ tc_stop(TC, obj->channel);
+
+ /*Set the registers a,b,c*/
+ setregisterabc(obj);
+
+ /* Enable TC TC_CHANNEL_WAVEFORM. */
+ tc_start(TC, obj->channel);
+}
+
+/** Get the duty cycle of PWM Waveform
+ *
+ * @param[in] obj The PWM object
+ * @return Current duty cycle
+ */
+float pwmout_read(pwmout_t* obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ return (obj->waveconfig.us_dutycycle / 100.0);
+}
+
+/** Set the period of PWM Waveform
+ *
+ * @param[in] obj The PWM object
+ * @param[in] seconds New period in seconds
+ * @return void
+ */
+void pwmout_period(pwmout_t* obj, float seconds)
+{
+ pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+/** Set the period of PWM Waveform
+ *
+ * @param[in] obj The PWM object
+ * @param[in] value New period in milliseconds
+ * @return void
+ */
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
+ pwmout_period_us(obj, ms * 1000);
+}
+
+/** Set the period of PWM Waveform
+ *
+ * @param[in] obj The PWM object
+ * @param[in] us New period in microseconds
+ * @return void
+ */
+void pwmout_period_us(pwmout_t* obj, int us)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ float freq = ( 1.0 / us ) * 1000000.0;
+
+ obj->waveconfig.us_frequency = (uint16_t) freq;
+ obj->prescalarindex = getprescalarindex(obj->waveconfig.us_frequency);
+ obj->waveconfig.ul_intclock = tc_prescalar[obj->prescalarindex];
+ pwmout_inithw(obj);
+
+ /*Set the registers a,b,c*/
+ setregisterabc(obj);
+
+ /* Enable TC TC_CHANNEL_WAVEFORM. */
+ tc_start(TC, obj->channel);
+}
+
+/** Set the pulse width of PWM Waveform
+ *
+ * @param[in] obj The PWM object
+ * @param[in] seconds New pulse width in seconds
+ * @return void
+ */
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
+ pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+/** Set the pulse width of PWM Waveform
+ *
+ * @param[in] obj The PWM object
+ * @param[in] ms New pulse width in milliseconds
+ * @return void
+ */
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
+ pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+/** Set the pulse width of PWM Waveform
+ *
+ * @param[in] obj The PWM object
+ * @param[in] us New pulse width in microseconds
+ * @return void
+ */
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ float new_duty = (us / 1000000.0) * (float)obj->waveconfig.us_frequency;
+ pwmout_write(obj, new_duty);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/rtc_api.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "rtc_api.h"
+#include "cmsis.h"
+#include "sysclk.h"
+#include "rtc.h"
+
+static int rtc_inited = 0;
+
+extern uint8_t g_sys_init;
+
+void rtc_init(void)
+{
+ if (g_sys_init == 0) {
+ sysclk_init();
+ system_board_init();
+ g_sys_init = 1;
+ }
+ /* Default RTC configuration, 24-hour mode */
+ rtc_set_hour_mode(RTC, 0);
+ rtc_inited = 1;
+}
+
+void rtc_free(void)
+{
+ /*This is a free running peripheral and cannot be disabled*/
+ rtc_inited = 0;
+}
+
+
+int rtc_isenabled(void)
+{
+ return rtc_inited;
+}
+
+
+time_t rtc_read(void)
+{
+ if (!rtc_inited) {
+ /* Return invalid time for now! */
+ return 0;
+ }
+ struct tm timeinfo;
+ uint32_t ul_hour, ul_minute, ul_second;
+ uint32_t ul_year, ul_month, ul_day, ul_week;
+
+ rtc_get_time(RTC, &ul_hour, &ul_minute, &ul_second);
+ rtc_get_date(RTC, &ul_year, &ul_month, &ul_day, &ul_week);
+
+ timeinfo.tm_sec = ul_second;
+ timeinfo.tm_min = ul_minute;
+ timeinfo.tm_hour = ul_hour;
+ timeinfo.tm_mday = ul_day;
+ timeinfo.tm_wday = ul_week;
+ timeinfo.tm_mon = ul_month;
+ timeinfo.tm_year = (ul_year - 1900);
+
+ /* Convert to timestamp */
+ time_t t = mktime(&timeinfo);
+ return t;
+}
+
+void rtc_write(time_t t)
+{
+ if (!rtc_inited) {
+ /* Initialize the RTC is not yet initialized */
+ rtc_init();
+ }
+ struct tm *timeinfo = localtime(&t);
+ uint32_t ul_hour, ul_minute, ul_second;
+ uint32_t ul_year, ul_month, ul_day, ul_week;
+
+ ul_second = timeinfo->tm_sec;
+ ul_minute = timeinfo->tm_min;
+ ul_hour = timeinfo->tm_hour;
+ ul_day = timeinfo->tm_mday;
+ ul_week = timeinfo->tm_wday;
+ ul_month = timeinfo->tm_mon;
+ ul_year = timeinfo->tm_year;
+
+ /* Set the RTC */
+ rtc_set_time(RTC, ul_hour, ul_minute, ul_second);
+ rtc_set_date(RTC, ul_year, ul_month, ul_day, ul_week);
+}
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/serial_api.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,786 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "serial_api.h"
+#include "sysclk.h"
+#include "serial_platform.h"
+#include "ioport.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "pdc.h"
+
+#if DEVICE_SERIAL_ASYNCH
+#define pUSART_S(obj) obj->serial.uart
+#define pSERIAL_S(obj) ((struct serial_s*)&(obj->serial))
+#else
+#define pUSART_S(obj) obj->uart
+#define pSERIAL_S(obj) ((struct serial_s*)obj)
+#endif
+#define _USART(obj) ((Usart*)pUSART_S(obj))
+#define USART_NUM 8
+
+static uint8_t serial_get_index(serial_t *obj);
+static IRQn_Type get_serial_irq_num (serial_t *obj);
+static uint32_t get_serial_vector (serial_t *obj);
+static uint32_t serial_irq_ids[USART_NUM] = {0};
+static uart_irq_handler irq_handler;
+static void uart0_irq(void);
+static void uart1_irq(void);
+static void uart2_irq(void);
+static void uart3_irq(void);
+static void uart4_irq(void);
+static void uart5_irq(void);
+static void uart6_irq(void);
+static void uart7_irq(void);
+
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+extern uint8_t g_sys_init;
+
+static int get_usart_clock_id(UARTName peripheral)
+{
+ int cid;
+ switch (peripheral) {
+ case UART_0:
+ cid = ID_FLEXCOM0;
+ break;
+ case UART_1:
+ cid = ID_FLEXCOM1;
+ break;
+ case UART_2:
+ cid = ID_FLEXCOM2;
+ break;
+ case UART_3:
+ cid = ID_FLEXCOM3;
+ break;
+ case UART_4:
+ cid = ID_FLEXCOM4;
+ break;
+ case UART_5:
+ cid = ID_FLEXCOM5;
+ break;
+ case UART_6:
+ cid = ID_FLEXCOM6;
+ break;
+ case UART_7:
+ cid = ID_FLEXCOM7;
+ break;
+ default :
+ cid = NC;
+ break;
+ }
+ return cid;
+}
+
+static int get_flexcom_id(UARTName peripheral)
+{
+ int fid;
+ switch (peripheral) {
+ case UART_0:
+ fid = (int)FLEXCOM0;
+ break;
+ case UART_1:
+ fid = (int)FLEXCOM1;
+ break;
+ case UART_2:
+ fid = (int)FLEXCOM2;
+ break;
+ case UART_3:
+ fid = (int)FLEXCOM3;
+ break;
+ case UART_4:
+ fid = (int)FLEXCOM4;
+ break;
+ case UART_5:
+ fid = (int)FLEXCOM5;
+ break;
+ case UART_6:
+ fid = (int)FLEXCOM6;
+ break;
+ case UART_7:
+ fid = (int)FLEXCOM7;
+ break;
+ default :
+ fid = NC;
+ break;
+ }
+ return fid;
+}
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ int clockid = NC, flexcom = NC;
+
+ /*To determine the uart peripheral associated with pins*/
+ UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+ UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+ UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+
+ MBED_ASSERT(uart != (UARTName)NC);
+
+ if (g_sys_init == 0) {
+ sysclk_init();
+ system_board_init();
+ g_sys_init = 1;
+ }
+ pUSART_S(obj) = uart;
+ pSERIAL_S(obj)->uart_serial_options.baudrate = (9600UL);
+ pSERIAL_S(obj)->uart_serial_options.charlength = US_MR_CHRL_8_BIT;
+ pSERIAL_S(obj)->uart_serial_options.paritytype = US_MR_PAR_NO;
+ pSERIAL_S(obj)->uart_serial_options.stopbits = US_MR_NBSTOP_1_BIT;
+ pSERIAL_S(obj)->actrec = false;
+ pSERIAL_S(obj)->acttra = false;
+
+ /* Configure UART pins */
+ if(tx != NC) {
+ pin_function(tx, pinmap_find_function(tx, PinMap_UART_TX));
+ ioport_disable_pin(tx);
+ }
+ if(rx != NC) {
+ pin_function(rx, pinmap_find_function(rx, PinMap_UART_RX));
+ ioport_disable_pin(rx);
+ }
+ clockid = get_usart_clock_id(uart);
+ if (clockid != NC) {
+ sysclk_enable_peripheral_clock(clockid);
+ }
+
+ flexcom = (int)get_flexcom_id(uart);
+#if (!SAM4L)
+#if (SAMG55)
+ /* Configure flexcom for usart */
+ flexcom_enable((Flexcom* )flexcom);
+ flexcom_set_opmode((Flexcom* )flexcom, FLEXCOM_USART);
+#else
+ sysclk_enable_peripheral_clock(clockid);
+#endif
+ /* Configure USART */
+ usart_init_rs232((Usart*)uart, (sam_usart_opt_t*)&(pSERIAL_S(obj)->uart_serial_options),
+ sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+ sysclk_enable_peripheral_clock(clockid);
+ /* Configure USART */
+ usart_init_rs232((Usart*)uart, (sam_usart_opt_t*)&(pSERIAL_S(obj)->uart_serial_options, sysclk_get_peripheral_bus_hz((Usart*)uart));
+#endif
+ /* Disable rx and tx in case 1 line only required to be configured for usart */
+ usart_disable_tx((Usart*)uart);
+ usart_disable_rx((Usart*)uart);
+ /* Enable the receiver and transmitter. */
+ if(tx != NC) {
+ usart_enable_tx((Usart*)uart);
+ }
+ if(rx != NC) {
+ usart_enable_rx((Usart*)uart);
+ }
+
+ if(uart == STDIO_UART) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+}
+
+void serial_free(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ usart_reset(_USART(obj));
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ MBED_ASSERT((baudrate == 110) || (baudrate == 150) || (baudrate == 300) || (baudrate == 1200) ||
+ (baudrate == 2400) || (baudrate == 4800) || (baudrate == 9600) || (baudrate == 19200) || (baudrate == 38400) ||
+ (baudrate == 57600) || (baudrate == 115200) || (baudrate == 230400) || (baudrate == 460800) || (baudrate == 921600) );
+ uint32_t clockid = 0;
+ clockid = get_usart_clock_id(pUSART_S(obj));
+ if (clockid != (uint32_t)NC) {
+ sysclk_disable_peripheral_clock(clockid);
+ }
+ pSERIAL_S(obj)->uart_serial_options.baudrate = baudrate;
+ usart_serial_init(_USART(obj), &(pSERIAL_S(obj)->uart_serial_options));
+ sysclk_enable_peripheral_clock(clockid);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
+ MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven));
+ MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8));
+
+ uint32_t clockid = 0;
+ clockid = get_usart_clock_id(pUSART_S(obj));
+ if (clockid != (uint32_t)NC) {
+ sysclk_disable_peripheral_clock(clockid);
+ }
+
+ switch(stop_bits) { /*selecting the stop bits*/
+ case 1:
+ pSERIAL_S(obj)->uart_serial_options.stopbits = US_MR_NBSTOP_1_BIT;
+ break;
+ case 2:
+ pSERIAL_S(obj)->uart_serial_options.stopbits = US_MR_NBSTOP_2_BIT;
+ break;
+ }
+
+ switch(parity) { /*selecting the parity bits*/
+ case ParityNone:
+ pSERIAL_S(obj)->uart_serial_options.paritytype = US_MR_PAR_NO;
+ break;
+ case ParityOdd:
+ pSERIAL_S(obj)->uart_serial_options.paritytype = US_MR_PAR_ODD;
+ break;
+ case ParityEven:
+ pSERIAL_S(obj)->uart_serial_options.paritytype = US_MR_PAR_EVEN;
+ break;
+ case ParityForced1: /*No Hardware Support*/
+ MBED_ASSERT(0);
+ break;
+ case ParityForced0: /*No Hardware Support*/
+ MBED_ASSERT(0);
+ break;
+ }
+
+ switch(data_bits) { /*selecting the data bits*/
+ case 5:
+ pSERIAL_S(obj)->uart_serial_options.charlength = US_MR_CHRL_5_BIT;
+ break;
+ case 6:
+ pSERIAL_S(obj)->uart_serial_options.charlength = US_MR_CHRL_6_BIT;
+ break;
+ case 7:
+ pSERIAL_S(obj)->uart_serial_options.charlength = US_MR_CHRL_7_BIT;
+ break;
+ case 8:
+ pSERIAL_S(obj)->uart_serial_options.charlength = US_MR_CHRL_8_BIT;
+ break;
+ }
+
+ usart_serial_init(_USART(obj), &(pSERIAL_S(obj)->uart_serial_options));
+ sysclk_enable_peripheral_clock(clockid);
+}
+
+#ifdef DEVICE_SERIAL_FC
+
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+
+ if(FlowControlNone == type) {
+ /* Disable Hardware Handshaking. */
+ _USART(obj)->US_MR = (_USART(obj)->US_MR & ~US_MR_USART_MODE_Msk) | US_MR_USART_MODE_NORMAL;
+ return;
+ }
+
+ /*To determine the uart peripheral associated with pins*/
+ UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
+ UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
+ UARTName uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
+ MBED_ASSERT(uart != (UARTName)NC);
+
+ if((FlowControlCTS == type) || (FlowControlRTSCTS== type)) {
+ /* Configure CTS pin. */
+ pin_function(txflow, pinmap_find_function(txflow, PinMap_UART_CTS));
+ ioport_disable_pin(txflow);
+ }
+
+ if((FlowControlRTS == type) || (FlowControlRTSCTS== type)) {
+ /* Configure CTS pin. */
+ pin_function(rxflow, pinmap_find_function(rxflow, PinMap_UART_RTS));
+ ioport_disable_pin(rxflow);
+ }
+
+ /* Set hardware handshaking mode. */
+ _USART(obj)->US_MR = (_USART(obj)->US_MR & ~US_MR_USART_MODE_Msk) | US_MR_USART_MODE_HW_HANDSHAKING;
+}
+
+#endif //DEVICE_SERIAL_FC
+
+void serial_break_set(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ _USART(obj)->US_CR = US_CR_STTBRK;
+
+}
+
+void serial_break_clear(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ _USART(obj)->US_CR = US_CR_STPBRK;
+
+}
+
+void serial_pinout_tx(PinName tx)
+{
+ pin_function(tx, pinmap_find_function(tx, PinMap_UART_TX));
+ ioport_disable_pin(tx);
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ irq_handler = handler;
+ serial_irq_ids[serial_get_index(obj)] = id;
+}
+
+#warning "Interrupt only available for Serial Receive complete. Transmit complete not supported by Controller"
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+
+ vector = get_serial_vector(obj);
+ irq_n = get_serial_irq_num(obj);
+
+ if (enable) {
+ switch (irq) {
+ case RxIrq:
+ usart_enable_interrupt(_USART(obj), US_IER_RXRDY);
+ break;
+ case TxIrq:
+ break;
+ }
+ NVIC_ClearPendingIRQ(irq_n);
+ NVIC_DisableIRQ(irq_n);
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+ } else {
+ switch (irq) {
+ case RxIrq:
+ usart_disable_interrupt(_USART(obj), US_IER_RXRDY);
+ break;
+ case TxIrq:
+ break;
+ }
+ NVIC_DisableIRQ(irq_n);
+ }
+}
+
+static inline void uart_irq(Usart *const usart, uint32_t index)
+{
+ MBED_ASSERT(usart != (void*)0);
+ uint32_t mask, status;
+ /* Read and clear mask. */
+ status = usart_get_status(usart);
+ mask = usart_get_interrupt_mask(usart);
+ status &= mask;
+
+ if (serial_irq_ids[index] != 0) {
+ if (status & US_IER_RXRDY) { /*For Receive Complete*/
+ if (irq_handler) {
+ irq_handler(serial_irq_ids[index], RxIrq);
+ }
+ }
+ }
+}
+
+void uart0_irq(void)
+{
+ uart_irq(USART0, 0);
+}
+
+void uart1_irq(void)
+{
+ uart_irq(USART1, 1);
+}
+
+void uart2_irq(void)
+{
+ uart_irq(USART2, 2);
+}
+
+void uart3_irq(void)
+{
+ uart_irq(USART3, 3);
+}
+
+void uart4_irq(void)
+{
+ uart_irq(USART4, 4);
+}
+
+void uart5_irq(void)
+{
+ uart_irq(USART5, 5);
+}
+
+void uart6_irq(void)
+{
+ uart_irq(USART6, 6);
+}
+
+void uart7_irq(void)
+{
+ uart_irq(USART7, 7);
+}
+
+static uint8_t serial_get_index(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ switch ((int)pUSART_S(obj)) {
+ case UART_0:
+ return 0;
+ case UART_1:
+ return 1;
+ case UART_2:
+ return 2;
+ case UART_3:
+ return 3;
+ case UART_4:
+ return 4;
+ case UART_5:
+ return 5;
+ case UART_6:
+ return 6;
+ case UART_7:
+ return 7;
+ }
+ return 0;
+}
+
+static uint32_t get_serial_vector (serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ uint32_t vector = 0;
+ switch ((int)pUSART_S(obj)) {
+ case UART_0:
+ vector = (uint32_t)uart0_irq;
+ break;
+ case UART_1:
+ vector = (uint32_t)uart1_irq;
+ break;
+ case UART_2:
+ vector = (uint32_t)uart2_irq;
+ break;
+ case UART_3:
+ vector = (uint32_t)uart3_irq;
+ break;
+ case UART_4:
+ vector = (uint32_t)uart4_irq;
+ break;
+ case UART_5:
+ vector = (uint32_t)uart5_irq;
+ break;
+ case UART_6:
+ vector = (uint32_t)uart6_irq;
+ break;
+ case UART_7:
+ vector = (uint32_t)uart7_irq;
+ break;
+ }
+ return vector;
+}
+
+IRQn_Type get_serial_irq_num (serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ switch ((int)pUSART_S(obj)) {
+ case UART_0:
+ return FLEXCOM0_IRQn;
+ case UART_1:
+ return FLEXCOM1_IRQn;
+ case UART_2:
+ return FLEXCOM2_IRQn;
+ case UART_3:
+ return FLEXCOM3_IRQn;
+ case UART_4:
+ return FLEXCOM4_IRQn;
+ case UART_5:
+ return FLEXCOM5_IRQn;
+ case UART_6:
+ return FLEXCOM6_IRQn;
+ case UART_7:
+ return FLEXCOM7_IRQn;
+ default:
+ MBED_ASSERT(0);
+ }
+ return 0; /*Warning Suppression*/
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ while (!serial_readable(obj));
+ return (int)((_USART(obj)->US_RHR & US_RHR_RXCHR_Msk) & 0xFF);
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ while (!serial_writable(obj));
+ _USART(obj)->US_THR = US_THR_TXCHR(c);
+}
+
+int serial_readable(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ uint32_t status = 1;
+ if (!(_USART(obj)->US_CSR & US_CSR_RXRDY)) {
+ status = 0;
+ } else {
+ status = 1;
+ }
+ return status;
+}
+
+int serial_writable(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ uint32_t status = 1;
+ if (!(_USART(obj)->US_CSR & US_CSR_TXRDY)) {
+ status = 0;
+ } else {
+ status = 1;
+ }
+ return status;
+}
+
+/************************************************************************************
+ * ASYNCHRONOUS HAL *
+ ************************************************************************************/
+
+
+#if DEVICE_SERIAL_ASYNCH
+/************************************
+ * HELPER FUNCTIONS *
+ ***********************************/
+
+void serial_set_char_match(serial_t *obj, uint8_t char_match)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ if (char_match != SERIAL_RESERVED_CHAR_MATCH) {
+ obj->char_match = char_match;
+ _USART(obj)->US_CMPR = (char_match & 0xFF);
+ usart_enable_interrupt(_USART(obj), US_IER_CMP);
+ }
+}
+
+/************************************
+ * TRANSFER FUNCTIONS *
+ ***********************************/
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ MBED_ASSERT(tx != (void*)0);
+ if(tx_length == 0) return 0;
+ Pdc *pdc_base;
+ IRQn_Type irq_n = (IRQn_Type)0;
+ pdc_packet_t packet;
+
+ pSERIAL_S(obj)->acttra = true; /* flag for active transmit transfer */
+
+ irq_n = get_serial_irq_num(obj);
+
+ /* Get board USART PDC base address and enable transmitter. */
+ pdc_base = usart_get_pdc_base(_USART(obj));
+ pdc_enable_transfer(pdc_base, PERIPH_PTCR_TXTEN);
+
+ packet.ul_addr = (uint32_t)tx;
+ packet.ul_size = (uint32_t)tx_length;
+
+ pdc_tx_init(pdc_base, &packet, NULL);
+ usart_enable_interrupt(_USART(obj), US_IER_TXBUFE);
+
+ NVIC_ClearPendingIRQ(irq_n);
+ NVIC_DisableIRQ(irq_n);
+ NVIC_SetVector(irq_n, (uint32_t)handler);
+ NVIC_EnableIRQ(irq_n);
+
+ return 0;
+}
+
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ MBED_ASSERT(rx != (void*)0);
+ if(rx_length == 0) return 0;
+ Pdc *pdc_base;
+ IRQn_Type irq_n = (IRQn_Type)0;
+ pdc_packet_t packet;
+
+ pSERIAL_S(obj)->actrec = true; /* flag for active receive transfer */
+ if (event == SERIAL_EVENT_RX_CHARACTER_MATCH) { /* if event is character match alone */
+ pSERIAL_S(obj)->events = SERIAL_EVENT_RX_CHARACTER_MATCH;
+ }
+
+ irq_n = get_serial_irq_num(obj);
+
+ serial_set_char_match(obj, char_match);
+
+ /* Get board USART PDC base address and enable transmitter. */
+ pdc_base = usart_get_pdc_base(_USART(obj));
+ pdc_enable_transfer(pdc_base, PERIPH_PTCR_RXTEN);
+ packet.ul_addr = (uint32_t)rx;
+ packet.ul_size = (uint32_t)rx_length;
+ pdc_rx_init(pdc_base, &packet, NULL);
+
+ usart_enable_interrupt(_USART(obj), (US_IER_RXBUFF | US_IER_OVRE | US_IER_FRAME | US_IER_PARE));
+
+ NVIC_ClearPendingIRQ(irq_n);
+ NVIC_DisableIRQ(irq_n);
+ NVIC_SetVector(irq_n, (uint32_t)handler);
+ NVIC_EnableIRQ(irq_n);
+
+}
+
+uint8_t serial_tx_active(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ return pSERIAL_S(obj)->acttra;
+}
+
+uint8_t serial_rx_active(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ return pSERIAL_S(obj)->actrec;
+}
+
+int serial_tx_irq_handler_asynch(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ serial_tx_abort_asynch(obj);
+ return SERIAL_EVENT_TX_COMPLETE;
+}
+int serial_rx_irq_handler_asynch(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ uint32_t ul_status, ulmask;
+
+ /* Read USART Status. */
+ ul_status = usart_get_status(_USART(obj));
+ ulmask = usart_get_interrupt_mask(_USART(obj));
+ ul_status &= ulmask;
+
+ if (ul_status & US_CSR_OVRE) { /* Overrun Error */
+ usart_disable_interrupt(_USART(obj), US_IDR_OVRE);
+ serial_rx_abort_asynch(obj);
+ return SERIAL_EVENT_RX_OVERFLOW;
+ }
+ if (ul_status & US_CSR_FRAME) { /* Framing Error */
+ usart_disable_interrupt(_USART(obj), US_IDR_FRAME);
+ serial_rx_abort_asynch(obj);
+ return SERIAL_EVENT_RX_FRAMING_ERROR;
+ }
+ if (ul_status & US_CSR_PARE) { /* Parity Error */
+ usart_disable_interrupt(_USART(obj), US_IDR_PARE);
+ serial_rx_abort_asynch(obj);
+ return SERIAL_EVENT_RX_PARITY_ERROR;
+ }
+ if ((ul_status & (US_IER_RXBUFF | US_IER_CMP)) == (US_IER_RXBUFF | US_IER_CMP)) { /* Character match in last character in transfer*/
+ usart_disable_interrupt(_USART(obj), US_IDR_CMP);
+ serial_rx_abort_asynch(obj);
+ return SERIAL_EVENT_RX_COMPLETE|SERIAL_EVENT_RX_CHARACTER_MATCH;
+ }
+ if (ul_status & US_IER_CMP) { /* Character match */
+ usart_disable_interrupt(_USART(obj), US_IDR_CMP);
+ if (pSERIAL_S(obj)->events == SERIAL_EVENT_RX_CHARACTER_MATCH) { /*if character match is the only event abort transfer */
+ serial_rx_abort_asynch(obj);
+ }
+ return SERIAL_EVENT_RX_CHARACTER_MATCH;
+ }
+ if (ul_status & US_IER_RXBUFF) { /* Reception Complete */
+ serial_rx_abort_asynch(obj);
+ return SERIAL_EVENT_RX_COMPLETE;
+ }
+ return 0;
+}
+
+int serial_irq_handler_asynch(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ uint32_t ul_status, ulmask;
+
+ /* Read USART Status. */
+ ul_status = usart_get_status(_USART(obj));
+ ulmask = usart_get_interrupt_mask(_USART(obj));
+
+ ul_status &= ulmask;
+
+ if (ul_status & (US_CSR_RXBUFF | US_CSR_OVRE | US_CSR_FRAME | US_CSR_PARE | US_IER_CMP)) {
+ return serial_rx_irq_handler_asynch(obj);
+ }
+ if (ul_status & US_CSR_TXBUFE) {
+ return serial_tx_irq_handler_asynch(obj);
+ }
+ return 0;
+}
+
+void serial_tx_abort_asynch(serial_t *obj)
+{
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ Pdc *pdc_base;
+ usart_disable_interrupt(_USART(obj), US_IER_TXBUFE);
+ pdc_base = usart_get_pdc_base(_USART(obj));
+ pdc_disable_transfer(pdc_base, PERIPH_PTCR_TXTEN);
+ pSERIAL_S(obj)->acttra = false;
+}
+
+void serial_rx_abort_asynch(serial_t *obj)
+{
+ IRQn_Type irq_n = (IRQn_Type)0;
+ /* Sanity check arguments */
+ MBED_ASSERT(obj);
+ Pdc *pdc_base;
+ usart_disable_interrupt(_USART(obj), US_IER_RXBUFF);
+ pdc_base = usart_get_pdc_base(_USART(obj));
+ pdc_disable_transfer(pdc_base, PERIPH_PTCR_RXTEN);
+ irq_n = get_serial_irq_num(obj);
+ NVIC_ClearPendingIRQ(irq_n);
+ NVIC_DisableIRQ(irq_n);
+ pSERIAL_S(obj)->actrec = false;
+}
+
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/dfll.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,402 @@
+/**
+ * \file
+ *
+ * \brief DFLL management
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CLK_DFLL_H_INCLUDED
+#define CLK_DFLL_H_INCLUDED
+
+#include <parts.h>
+#include "conf_clock.h"
+
+#if UC3L
+# include "uc3l/dfll.h"
+#elif SAM4L
+# include "sam4l/dfll.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ * \ingroup clk_group
+ * \defgroup dfll_group DFLL Management
+ *
+ * A Digital Frequency Locked Loop can be used to generate a highly
+ * accurate frequency from a slower-running reference clock, in much the
+ * same way as a PLL. DFLLs typically have shorter startup times and
+ * less jitter. They can also be used in open-loop mode to generate a
+ * less accurate frequency without the use of a reference clock.
+ *
+ * There may be significant variations between platforms in the support
+ * for certain features.
+ *
+ * \par Example: Setting up DFLL0 with default parameters and dithering enabled
+ *
+ * The following example shows how to configure and enable DFLL0 in
+ * closed-loop mode using the default parameters specified through
+ * configuration symbols.
+ * \code
+ dfll_enable_config_defaults(0); \endcode
+ *
+ * To configure and enable DFLL0 in closed-loop mode using the default
+ * parameters and to enable specific feature like dithering for better accuracy,
+ * you can use this initialization process.
+ * \code
+ struct dfll_config dfllcfg;
+
+ dfll_enable_source(CONFIG_DFLL0_SOURCE);
+ dfll_config_defaults(&dfllcfg, 0);
+ dfll_config_enable_dithering(&dfllcfg);
+ dfll_enable(&dfllcfg, 0);
+ dfll_wait_for_accurate_lock(0); \endcode
+ *
+ * When the last function call returns, DFLL0 is running at a frequency
+ * which matches the default configuration as accurately as possible.
+ * Any additional alterations to the default configuration can be added
+ * at the same place as the call to dfll_config_enable_dithering(), but
+ * note that the DFLL will never achieve "accurate" lock if dithering is
+ * disabled.
+ *
+ * @{
+ */
+
+//! \name Chip-specific DFLL characteristics
+//@{
+/**
+ * \def NR_DFLLS
+ * \brief Number of on-chip DFLLs.
+ */
+/**
+ * \def DFLL_MIN_HZ
+ * \brief Minimum frequency that the DFLL can generate.
+ */
+/**
+ * \def DFLL_MAX_HZ
+ * \brief Maximum frequency that the DFLL can generate.
+ */
+//@}
+
+/**
+ * \typedef dfll_refclk_t
+ * \brief Type used for identifying a reference clock source for the DFLL.
+ */
+
+//! \name DFLL Configuration
+//@{
+
+/**
+ * \struct dfll_config
+ * \brief Hardware-specific representation of DFLL configuration.
+ *
+ * This structure contains one or more device-specific values
+ * representing the current DFLL configuration. The contents of this
+ * structure is typically different from platform to platform, and the
+ * user should not access any fields except through the DFLL
+ * configuration API.
+ */
+
+/**
+ * \fn void dfll_config_init_open_loop_mode(struct dfll_config *cfg)
+ * \brief Configure the DFLL configuration \a cfg for open-loop mode.
+ *
+ * \param cfg The DFLL configuration to be initialized.
+ */
+/**
+ * \fn void dfll_config_init_closed_loop_mode(struct dfll_config *cfg,
+ * dfll_refclk_t refclk, uint16_t div, uint16_t mul)
+ * \brief Configure the DFLL configuration \a cfg for closed-loop mode.
+ *
+ * \param cfg The DFLL configuration to be initialized.
+ * \param refclk The reference clock source.
+ * \param div Reference clock divider.
+ * \param mul Multiplier (integer part only).
+ */
+/**
+ * \def dfll_config_defaults(cfg, dfll_id)
+ * \brief Initialize DFLL configuration using default parameters.
+ *
+ * After this function returns, \a cfg will contain a configuration
+ * which will make the DFLL run at (CONFIG_DFLLx_MUL / CONFIG_DFLLx_DIV)
+ * times the frequency of CONFIG_DFLLx_SOURCE. The default configuration
+ * will always use closed-loop mode with no fractional multiplier.
+ *
+ * \param cfg The DFLL configuration to be initialized.
+ * \param dfll_id Use defaults for this DFLL.
+ */
+/**
+ * \def dfll_get_default_rate(dfll_id)
+ * \brief Return the default rate in Hz of \a dfll_id.
+ */
+
+/**
+ * \fn void dfll_config_set_fractional_multiplier(struct dfll_config *cfg,
+ * uint16_t mul_i, uint16_t mul_f)
+ * \brief Set a fractional multiplier.
+ *
+ * This function has no effect in open-loop mode, and is only available
+ * on devices which support fractional multipliers.
+ *
+ * The fractional part of the multiplier is assumed to be 16 bits. The
+ * low-level driver will make sure to shift this value to match the
+ * hardware if necessary.
+ *
+ * \param cfg The DFLL configuration to be modified.
+ * \param mul_i Integer part of multiplier.
+ * \param mul_f Fractional part of multiplier.
+ */
+/**
+ * \fn void dfll_config_enable_dithering(struct dfll_config *cfg)
+ * \brief Enable dithering for more accurate frequency generation.
+ *
+ * The fine LSB input to the VCO is dithered to achieve fractional
+ * approximation to the correct multiplication ratio.
+ *
+ * \param cfg The DFLL configuration to be modified.
+ */
+/**
+ * \fn void dfll_config_disable_dithering(struct dfll_config *cfg)
+ * \brief Disable dithering.
+ *
+ * \see dfll_config_enable_dithering()
+ *
+ * \param cfg The DFLL configuration to be modified.
+ */
+/**
+ * \fn void dfll_config_set_initial_tuning(struct dfll_config *cfg,
+ * uint16_t coarse, uint16_t fine)
+ * \brief Set initial VCO tuning.
+ *
+ * In open loop mode, this will determine the frequency of the output.
+ *
+ * In closed loop mode, this will provide an initial estimate of the VCO
+ * tuning. While the DFLL will automatically adjust these values to
+ * match the desired output frequency, careful selection of initial
+ * values might reduce the time to achieve coarse and fine lock.
+ *
+ * \param cfg The DFLL configuration to be modified.
+ * \param coarse Coarse tuning of the frequency generator.
+ * \param fine Fine tuning of the frequency generator.
+ */
+/**
+ * \fn void dfll_config_set_max_step(struct dfll_config *cfg,
+ * uint16_t coarse, uint16_t fine)
+ * \brief Set the maximum VCO tuning step size.
+ *
+ * This function has no effect in open-loop mode.
+ *
+ * By default, both of these values are set to 50% of their respective
+ * maximums. It is not recommended to set the values any higher than
+ * this, but setting them lower might reduce the frequency overshoot at
+ * the expense of longer time to achieve coarse and/or fine lock.
+ *
+ * \param cfg The DFLL configuration to be modified
+ * \param coarse The maximum step size of the coarse VCO tuning.
+ * \param fine The maximum step size of the fine VCO tuning.
+ */
+/**
+ * \fn void dfll_config_enable_ssg(struct dfll_config *cfg,
+ * uint16_t amplitude, uint16_t step_size)
+ * \brief Enable Spread Spectrum Generator.
+ *
+ * \param cfg The DFLL configuration to be modified.
+ * \param amplitude The amplitude of the spread spectrum.
+ * \param step_size The step size of the spread spectrum.
+ */
+/**
+ * \fn void dfll_config_disable_ssg(struct dfll_config *cfg)
+ * \brief Disable Spread Spectrum Generator.
+ *
+ * \param cfg The DFLL configuration to be modified.
+ */
+//@}
+
+//! \name Interaction with the DFLL hardware
+//@{
+/**
+ * \fn void dfll_enable_open_loop(const struct dfll_config *cfg,
+ * unsigned int dfll_id)
+ * \brief Activate the configuration \a cfg and enable DFLL \a dfll_id
+ * in open-loop mode.
+ *
+ * \pre The configuration in \a cfg must represent an open-loop
+ * configuration.
+ *
+ * \param cfg The configuration to be activated.
+ * \param dfll_id The ID of the DFLL to be enabled.
+ */
+/**
+ * \fn void dfll_enable_closed_loop(const struct dfll_config *cfg,
+ * unsigned int dfll_id)
+ * \brief Activate the configuration \a cfg and enable DFLL \a dfll_id
+ * in closed-loop mode.
+ *
+ * \pre The configuration in \a cfg must represent a closed-loop
+ * configuration.
+ *
+ * \param cfg The configuration to be activated.
+ * \param dfll_id The ID of the DFLL to be enabled.
+ */
+/**
+ * \fn void dfll_disable_open_loop(unsigned int dfll_id)
+ * \brief Disable the DFLL identified by \a dfll_id.
+ *
+ * \pre The DFLL must have been enabled in open loop mode.
+ *
+ * \param dfll_id The ID of the DFLL to be disabled.
+ */
+/**
+ * \fn void dfll_disable_closed_loop(unsigned int dfll_id)
+ * \brief Disable the DFLL identified by \a dfll_id.
+ *
+ * \pre The DFLL must have been enabled in closed loop mode.
+ *
+ * \param dfll_id The ID of the DFLL to be disabled.
+ */
+/**
+ * \fn bool dfll_is_coarse_locked(unsigned int dfll_id)
+ * \brief Determine whether or not a DFLL has achieved coarse lock.
+ *
+ * \param dfll_id The ID of the DFLL to check.
+ *
+ * \retval true The DFLL has determined the final value of the coarse
+ * VCO tuning value.
+ * \retval false The DFLL has not yet determined the coarse VCO tuning
+ * value, or has not been enabled.
+ */
+/**
+ * \fn bool dfll_is_fine_locked(unsigned int dfll_id)
+ * \brief Determine whether or not a DFLL has achieved fine lock.
+ *
+ * \param dfll_id The ID of the DFLL to check.
+ *
+ * \retval true The DFLL has determined the final value of the fine VCO
+ * tuning value.
+ * \retval false The DFLL has not yet determined the fine VCO tuning
+ * value, or has not been enabled.
+ */
+/**
+ * \fn bool dfll_is_accurate_locked(unsigned int dfll_id)
+ * \brief Determine whether or not a DFLL has achieved accurate lock.
+ *
+ * \param dfll_id The ID of the DFLL to check.
+ *
+ * \retval true The DFLL has determined the final dithering duty cycle.
+ * \retval false The DFLL has not yet determined the dithering duty
+ * cycle, or has not been enabled with dithering enabled.
+ */
+/**
+ * \fn void dfll_enable_source(enum dfll_refclk_t src)
+ * \brief Enable the source of the dfll.
+ * The source is enabled, if the source is not already running.
+ *
+ * \param dfll_source src The ID of the DFLL source to enable.
+ */
+/**
+ * \fn void dfll_enable_config_defaults(unsigned int dfll_id)
+ * \brief Enable the dfll with the default configuration.
+ * DFLL is enabled, if the DFLL is not already locked.
+ *
+ * \param dfll_id The ID of the DFLL to enable.
+ */
+
+/**
+ * \brief Wait for the DFLL identified by \a dfll_id to achieve coarse
+ * lock.
+ *
+ * \param dfll_id The ID of the DFLL to wait for.
+ *
+ * \retval STATUS_OK The DFLL has achieved coarse lock.
+ * \retval ERR_TIMEOUT Timed out waiting for lock.
+ */
+static inline int dfll_wait_for_coarse_lock(unsigned int dfll_id)
+{
+ /* TODO: Add timeout mechanism */
+ while (!dfll_is_coarse_locked(dfll_id)) {
+ /* Do nothing */
+ }
+
+ return 0;
+}
+
+/**
+ * \brief Wait for the DFLL identified by \a dfll_id to achieve fine
+ * lock.
+ *
+ * \param dfll_id The ID of the DFLL to wait for.
+ *
+ * \retval STATUS_OK The DFLL has achieved fine lock.
+ * \retval ERR_TIMEOUT Timed out waiting for lock.
+ */
+static inline int dfll_wait_for_fine_lock(unsigned int dfll_id)
+{
+ /* TODO: Add timeout mechanism */
+ while (!dfll_is_fine_locked(dfll_id)) {
+ /* Do nothing */
+ }
+
+ return 0;
+}
+
+/**
+ * \brief Wait for the DFLL identified by \a dfll_id to achieve accurate
+ * lock.
+ *
+ * \param dfll_id The ID of the DFLL to wait for.
+ *
+ * \retval STATUS_OK The DFLL has achieved accurate lock.
+ * \retval ERR_TIMEOUT Timed out waiting for lock.
+ */
+static inline int dfll_wait_for_accurate_lock(unsigned int dfll_id)
+{
+ /* TODO: Add timeout mechanism */
+ while (!dfll_is_accurate_locked(dfll_id)) {
+ /* Do nothing */
+ }
+
+ return 0;
+}
+
+//@}
+//! @}
+
+#endif /* CLK_DFLL_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/genclk.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,199 @@
+/**
+ * \file
+ *
+ * \brief Generic clock management
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CLK_GENCLK_H_INCLUDED
+#define CLK_GENCLK_H_INCLUDED
+
+#include "parts.h"
+
+#if SAM3S
+# include "sam3s/genclk.h"
+#elif SAM3U
+# include "sam3u/genclk.h"
+#elif SAM3N
+# include "sam3n/genclk.h"
+#elif SAM3XA
+# include "sam3x/genclk.h"
+#elif SAM4S
+# include "sam4s/genclk.h"
+#elif SAM4L
+# include "sam4l/genclk.h"
+#elif SAM4E
+# include "sam4e/genclk.h"
+#elif SAM4N
+# include "sam4n/genclk.h"
+#elif SAM4C
+# include "sam4c/genclk.h"
+#elif SAM4CM
+# include "sam4cm/genclk.h"
+#elif SAM4CP
+# include "sam4cp/genclk.h"
+#elif SAMG
+# include "samg/genclk.h"
+#elif SAMV71
+# include "samv71/genclk.h"
+#elif SAMV70
+# include "samv70/genclk.h"
+#elif SAME70
+# include "same70/genclk.h"
+#elif SAMS70
+# include "sams70/genclk.h"
+#elif (UC3A0 || UC3A1)
+# include "uc3a0_a1/genclk.h"
+#elif UC3A3
+# include "uc3a3_a4/genclk.h"
+#elif UC3B
+# include "uc3b0_b1/genclk.h"
+#elif UC3C
+# include "uc3c/genclk.h"
+#elif UC3D
+# include "uc3d/genclk.h"
+#elif UC3L
+# include "uc3l/genclk.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ * \ingroup clk_group
+ * \defgroup genclk_group Generic Clock Management
+ *
+ * Generic clocks are configurable clocks which run outside the system
+ * clock domain. They are often connected to peripherals which have an
+ * asynchronous component running independently of the bus clock, e.g.
+ * USB controllers, low-power timers and RTCs, etc.
+ *
+ * Note that not all platforms have support for generic clocks; on such
+ * platforms, this API will not be available.
+ *
+ * @{
+ */
+
+/**
+ * \def GENCLK_DIV_MAX
+ * \brief Maximum divider supported by the generic clock implementation
+ */
+/**
+ * \enum genclk_source
+ * \brief Generic clock source ID
+ *
+ * Each generic clock may be generated from a different clock source.
+ * These are the available alternatives provided by the chip.
+ */
+
+//! \name Generic clock configuration
+//@{
+/**
+ * \struct genclk_config
+ * \brief Hardware representation of a set of generic clock parameters
+ */
+/**
+ * \fn void genclk_config_defaults(struct genclk_config *cfg,
+ * unsigned int id)
+ * \brief Initialize \a cfg to the default configuration for the clock
+ * identified by \a id.
+ */
+/**
+ * \fn void genclk_config_read(struct genclk_config *cfg, unsigned int id)
+ * \brief Read the currently active configuration of the clock
+ * identified by \a id into \a cfg.
+ */
+/**
+ * \fn void genclk_config_write(const struct genclk_config *cfg,
+ * unsigned int id)
+ * \brief Activate the configuration \a cfg on the clock identified by
+ * \a id.
+ */
+/**
+ * \fn void genclk_config_set_source(struct genclk_config *cfg,
+ * enum genclk_source src)
+ * \brief Select a new source clock \a src in configuration \a cfg.
+ */
+/**
+ * \fn void genclk_config_set_divider(struct genclk_config *cfg,
+ * unsigned int divider)
+ * \brief Set a new \a divider in configuration \a cfg.
+ */
+/**
+ * \fn void genclk_enable_source(enum genclk_source src)
+ * \brief Enable the source clock \a src used by a generic clock.
+ */
+//@}
+
+//! \name Enabling and disabling Generic Clocks
+//@{
+/**
+ * \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id)
+ * \brief Activate the configuration \a cfg on the clock identified by
+ * \a id and enable it.
+ */
+/**
+ * \fn void genclk_disable(unsigned int id)
+ * \brief Disable the generic clock identified by \a id.
+ */
+//@}
+
+/**
+ * \brief Enable the configuration defined by \a src and \a divider
+ * for the generic clock identified by \a id.
+ *
+ * \param id The ID of the generic clock.
+ * \param src The source clock of the generic clock.
+ * \param divider The divider used to generate the generic clock.
+ */
+static inline void genclk_enable_config(unsigned int id, enum genclk_source src, unsigned int divider)
+{
+ struct genclk_config gcfg;
+
+ genclk_config_defaults(&gcfg, id);
+ genclk_enable_source(src);
+ genclk_config_set_source(&gcfg, src);
+ genclk_config_set_divider(&gcfg, divider);
+ genclk_enable(&gcfg, id);
+}
+
+//! @}
+
+#endif /* CLK_GENCLK_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/osc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,185 @@
+/**
+ * \file
+ *
+ * \brief Oscillator management
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef OSC_H_INCLUDED
+#define OSC_H_INCLUDED
+
+#include "parts.h"
+#include "conf_clock.h"
+
+#if SAM3S
+# include "sam3s/osc.h"
+#elif SAM3XA
+# include "sam3x/osc.h"
+#elif SAM3U
+# include "sam3u/osc.h"
+#elif SAM3N
+# include "sam3n/osc.h"
+#elif SAM4S
+# include "sam4s/osc.h"
+#elif SAM4E
+# include "sam4e/osc.h"
+#elif SAM4C
+# include "sam4c/osc.h"
+#elif SAM4CM
+# include "sam4cm/osc.h"
+#elif SAM4CP
+# include "sam4cp/osc.h"
+#elif SAM4L
+# include "sam4l/osc.h"
+#elif SAM4N
+# include "sam4n/osc.h"
+#elif SAMG
+# include "samg/osc.h"
+#elif SAMV71
+# include "samv71/osc.h"
+#elif SAMV70
+# include "samv70/osc.h"
+#elif SAME70
+# include "same70/osc.h"
+#elif SAMS70
+# include "sams70/osc.h"
+#elif (UC3A0 || UC3A1)
+# include "uc3a0_a1/osc.h"
+#elif UC3A3
+# include "uc3a3_a4/osc.h"
+#elif UC3B
+# include "uc3b0_b1/osc.h"
+#elif UC3C
+# include "uc3c/osc.h"
+#elif UC3D
+# include "uc3d/osc.h"
+#elif UC3L
+# include "uc3l/osc.h"
+#elif XMEGA
+# include "xmega/osc.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ * \ingroup clk_group
+ * \defgroup osc_group Oscillator Management
+ *
+ * This group contains functions and definitions related to configuring
+ * and enabling/disabling on-chip oscillators. Internal RC-oscillators,
+ * external crystal oscillators and external clock generators are
+ * supported by this module. What all of these have in common is that
+ * they swing at a fixed, nominal frequency which is normally not
+ * adjustable.
+ *
+ * \par Example: Enabling an oscillator
+ *
+ * The following example demonstrates how to enable the external
+ * oscillator on XMEGA A and wait for it to be ready to use. The
+ * oscillator identifiers are platform-specific, so while the same
+ * procedure is used on all platforms, the parameter to osc_enable()
+ * will be different from device to device.
+ * \code
+ osc_enable(OSC_ID_XOSC);
+ osc_wait_ready(OSC_ID_XOSC); \endcode
+ *
+ * \section osc_group_board Board-specific Definitions
+ * If external oscillators are used, the board code must provide the
+ * following definitions for each of those:
+ * - \b BOARD_<osc name>_HZ: The nominal frequency of the oscillator.
+ * - \b BOARD_<osc name>_STARTUP_US: The startup time of the
+ * oscillator in microseconds.
+ * - \b BOARD_<osc name>_TYPE: The type of oscillator connected, i.e.
+ * whether it's a crystal or external clock, and sometimes what kind
+ * of crystal it is. The meaning of this value is platform-specific.
+ *
+ * @{
+ */
+
+//! \name Oscillator Management
+//@{
+/**
+ * \fn void osc_enable(uint8_t id)
+ * \brief Enable oscillator \a id
+ *
+ * The startup time and mode value is automatically determined based on
+ * definitions in the board code.
+ */
+/**
+ * \fn void osc_disable(uint8_t id)
+ * \brief Disable oscillator \a id
+ */
+/**
+ * \fn osc_is_ready(uint8_t id)
+ * \brief Determine whether oscillator \a id is ready.
+ * \retval true Oscillator \a id is running and ready to use as a clock
+ * source.
+ * \retval false Oscillator \a id is not running.
+ */
+/**
+ * \fn uint32_t osc_get_rate(uint8_t id)
+ * \brief Return the frequency of oscillator \a id in Hz
+ */
+
+#ifndef __ASSEMBLY__
+
+/**
+ * \brief Wait until the oscillator identified by \a id is ready
+ *
+ * This function will busy-wait for the oscillator identified by \a id
+ * to become stable and ready to use as a clock source.
+ *
+ * \param id A number identifying the oscillator to wait for.
+ */
+static inline void osc_wait_ready(uint8_t id)
+{
+ while (!osc_is_ready(id)) {
+ /* Do nothing */
+ }
+}
+
+#endif /* __ASSEMBLY__ */
+
+//@}
+
+//! @}
+
+#endif /* OSC_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/pll.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,341 @@
+/**
+ * \file
+ *
+ * \brief PLL management
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CLK_PLL_H_INCLUDED
+#define CLK_PLL_H_INCLUDED
+
+#include "parts.h"
+#include "conf_clock.h"
+
+#if SAM3S
+# include "sam3s/pll.h"
+#elif SAM3XA
+# include "sam3x/pll.h"
+#elif SAM3U
+# include "sam3u/pll.h"
+#elif SAM3N
+# include "sam3n/pll.h"
+#elif SAM4S
+# include "sam4s/pll.h"
+#elif SAM4E
+# include "sam4e/pll.h"
+#elif SAM4C
+# include "sam4c/pll.h"
+#elif SAM4CM
+# include "sam4cm/pll.h"
+#elif SAM4CP
+# include "sam4cp/pll.h"
+#elif SAM4L
+# include "sam4l/pll.h"
+#elif SAM4N
+# include "sam4n/pll.h"
+#elif SAMG
+# include "samg/pll.h"
+#elif SAMV71
+# include "samv71/pll.h"
+#elif SAMV70
+# include "samv70/pll.h"
+#elif SAME70
+# include "same70/pll.h"
+#elif SAMS70
+# include "sams70/pll.h"
+#elif (UC3A0 || UC3A1)
+# include "uc3a0_a1/pll.h"
+#elif UC3A3
+# include "uc3a3_a4/pll.h"
+#elif UC3B
+# include "uc3b0_b1/pll.h"
+#elif UC3C
+# include "uc3c/pll.h"
+#elif UC3D
+# include "uc3d/pll.h"
+#elif (UC3L0128 || UC3L0256 || UC3L3_L4)
+# include "uc3l/pll.h"
+#elif XMEGA
+# include "xmega/pll.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ * \ingroup clk_group
+ * \defgroup pll_group PLL Management
+ *
+ * This group contains functions and definitions related to configuring
+ * and enabling/disabling on-chip PLLs. A PLL will take an input signal
+ * (the \em source), optionally divide the frequency by a configurable
+ * \em divider, and then multiply the frequency by a configurable \em
+ * multiplier.
+ *
+ * Some devices don't support input dividers; specifying any other
+ * divisor than 1 on these devices will result in an assertion failure.
+ * Other devices may have various restrictions to the frequency range of
+ * the input and output signals.
+ *
+ * \par Example: Setting up PLL0 with default parameters
+ *
+ * The following example shows how to configure and enable PLL0 using
+ * the default parameters specified using the configuration symbols
+ * listed above.
+ * \code
+ pll_enable_config_defaults(0); \endcode
+ *
+ * To configure, enable PLL0 using the default parameters and to disable
+ * a specific feature like Wide Bandwidth Mode (a UC3A3-specific
+ * PLL option.), you can use this initialization process.
+ * \code
+ struct pll_config pllcfg;
+ if (pll_is_locked(pll_id)) {
+ return; // Pll already running
+ }
+ pll_enable_source(CONFIG_PLL0_SOURCE);
+ pll_config_defaults(&pllcfg, 0);
+ pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);
+ pll_enable(&pllcfg, 0);
+ pll_wait_for_lock(0); \endcode
+ *
+ * When the last function call returns, PLL0 is ready to be used as the
+ * main system clock source.
+ *
+ * \section pll_group_config Configuration Symbols
+ *
+ * Each PLL has a set of default parameters determined by the following
+ * configuration symbols in the application's configuration file:
+ * - \b CONFIG_PLLn_SOURCE: The default clock source connected to the
+ * input of PLL \a n. Must be one of the values defined by the
+ * #pll_source enum.
+ * - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL
+ * \a n.
+ * - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n.
+ *
+ * These configuration symbols determine the result of calling
+ * pll_config_defaults() and pll_get_default_rate().
+ *
+ * @{
+ */
+
+//! \name Chip-specific PLL characteristics
+//@{
+/**
+ * \def PLL_MAX_STARTUP_CYCLES
+ * \brief Maximum PLL startup time in number of slow clock cycles
+ */
+/**
+ * \def NR_PLLS
+ * \brief Number of on-chip PLLs
+ */
+
+/**
+ * \def PLL_MIN_HZ
+ * \brief Minimum frequency that the PLL can generate
+ */
+/**
+ * \def PLL_MAX_HZ
+ * \brief Maximum frequency that the PLL can generate
+ */
+/**
+ * \def PLL_NR_OPTIONS
+ * \brief Number of PLL option bits
+ */
+//@}
+
+/**
+ * \enum pll_source
+ * \brief PLL clock source
+ */
+
+//! \name PLL configuration
+//@{
+
+/**
+ * \struct pll_config
+ * \brief Hardware-specific representation of PLL configuration.
+ *
+ * This structure contains one or more device-specific values
+ * representing the current PLL configuration. The contents of this
+ * structure is typically different from platform to platform, and the
+ * user should not access any fields except through the PLL
+ * configuration API.
+ */
+
+/**
+ * \fn void pll_config_init(struct pll_config *cfg,
+ * enum pll_source src, unsigned int div, unsigned int mul)
+ * \brief Initialize PLL configuration from standard parameters.
+ *
+ * \note This function may be defined inline because it is assumed to be
+ * called very few times, and usually with constant parameters. Inlining
+ * it will in such cases reduce the code size significantly.
+ *
+ * \param cfg The PLL configuration to be initialized.
+ * \param src The oscillator to be used as input to the PLL.
+ * \param div PLL input divider.
+ * \param mul PLL loop divider (i.e. multiplier).
+ *
+ * \return A configuration which will make the PLL run at
+ * (\a mul / \a div) times the frequency of \a src
+ */
+/**
+ * \def pll_config_defaults(cfg, pll_id)
+ * \brief Initialize PLL configuration using default parameters.
+ *
+ * After this function returns, \a cfg will contain a configuration
+ * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV)
+ * times the frequency of CONFIG_PLLx_SOURCE.
+ *
+ * \param cfg The PLL configuration to be initialized.
+ * \param pll_id Use defaults for this PLL.
+ */
+/**
+ * \def pll_get_default_rate(pll_id)
+ * \brief Get the default rate in Hz of \a pll_id
+ */
+/**
+ * \fn void pll_config_set_option(struct pll_config *cfg,
+ * unsigned int option)
+ * \brief Set the PLL option bit \a option in the configuration \a cfg.
+ *
+ * \param cfg The PLL configuration to be changed.
+ * \param option The PLL option bit to be set.
+ */
+/**
+ * \fn void pll_config_clear_option(struct pll_config *cfg,
+ * unsigned int option)
+ * \brief Clear the PLL option bit \a option in the configuration \a cfg.
+ *
+ * \param cfg The PLL configuration to be changed.
+ * \param option The PLL option bit to be cleared.
+ */
+/**
+ * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id)
+ * \brief Read the currently active configuration of \a pll_id.
+ *
+ * \param cfg The configuration object into which to store the currently
+ * active configuration.
+ * \param pll_id The ID of the PLL to be accessed.
+ */
+/**
+ * \fn void pll_config_write(const struct pll_config *cfg,
+ * unsigned int pll_id)
+ * \brief Activate the configuration \a cfg on \a pll_id
+ *
+ * \param cfg The configuration object representing the PLL
+ * configuration to be activated.
+ * \param pll_id The ID of the PLL to be updated.
+ */
+
+//@}
+
+//! \name Interaction with the PLL hardware
+//@{
+/**
+ * \fn void pll_enable(const struct pll_config *cfg,
+ * unsigned int pll_id)
+ * \brief Activate the configuration \a cfg and enable PLL \a pll_id.
+ *
+ * \param cfg The PLL configuration to be activated.
+ * \param pll_id The ID of the PLL to be enabled.
+ */
+/**
+ * \fn void pll_disable(unsigned int pll_id)
+ * \brief Disable the PLL identified by \a pll_id.
+ *
+ * After this function is called, the PLL identified by \a pll_id will
+ * be disabled. The PLL configuration stored in hardware may be affected
+ * by this, so if the caller needs to restore the same configuration
+ * later, it should either do a pll_config_read() before disabling the
+ * PLL, or remember the last configuration written to the PLL.
+ *
+ * \param pll_id The ID of the PLL to be disabled.
+ */
+/**
+ * \fn bool pll_is_locked(unsigned int pll_id)
+ * \brief Determine whether the PLL is locked or not.
+ *
+ * \param pll_id The ID of the PLL to check.
+ *
+ * \retval true The PLL is locked and ready to use as a clock source
+ * \retval false The PLL is not yet locked, or has not been enabled.
+ */
+/**
+ * \fn void pll_enable_source(enum pll_source src)
+ * \brief Enable the source of the pll.
+ * The source is enabled, if the source is not already running.
+ *
+ * \param src The ID of the PLL source to enable.
+ */
+/**
+ * \fn void pll_enable_config_defaults(unsigned int pll_id)
+ * \brief Enable the pll with the default configuration.
+ * PLL is enabled, if the PLL is not already locked.
+ *
+ * \param pll_id The ID of the PLL to enable.
+ */
+
+/**
+ * \brief Wait for PLL \a pll_id to become locked
+ *
+ * \todo Use a timeout to avoid waiting forever and hanging the system
+ *
+ * \param pll_id The ID of the PLL to wait for.
+ *
+ * \retval STATUS_OK The PLL is now locked.
+ * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked.
+ */
+static inline int pll_wait_for_lock(unsigned int pll_id)
+{
+ Assert(pll_id < NR_PLLS);
+
+ while (!pll_is_locked(pll_id)) {
+ /* Do nothing */
+ }
+
+ return 0;
+}
+
+//@}
+//! @}
+
+#endif /* CLK_PLL_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/genclk.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,292 @@
+/**
+ * \file
+ *
+ * \brief Chip-specific generic clock management.
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CHIP_GENCLK_H_INCLUDED
+#define CHIP_GENCLK_H_INCLUDED
+
+#include <osc.h>
+#include <pll.h>
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /**
+ * \weakgroup genclk_group
+ * @{
+ */
+
+//! \name Programmable Clock Identifiers (PCK)
+//@{
+#define GENCLK_PCK_0 0 //!< PCK0 ID
+#define GENCLK_PCK_1 1 //!< PCK1 ID
+#define GENCLK_PCK_2 2 //!< PCK2 ID
+#if SAMG55
+#define GENCLK_PCK_3 3 //!< PCK3 ID
+#define GENCLK_PCK_4 4 //!< PCK4 ID
+#define GENCLK_PCK_5 5 //!< PCK5 ID
+#define GENCLK_PCK_6 6 //!< PCK6 ID
+#define GENCLK_PCK_7 7 //!< PCK7 ID
+#endif
+//@}
+
+//! \name Programmable Clock Sources (PCK)
+//@{
+
+enum genclk_source {
+ GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32kHz RC oscillator as PCK source clock
+ GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32kHz crystal oscillator as PCK source clock
+ GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32kHz bypass oscillator as PCK source clock
+ GENCLK_PCK_SRC_MAINCK_8M_RC = 3, //!< Internal 8MHz RC oscillator as PCK source clock
+ GENCLK_PCK_SRC_MAINCK_16M_RC = 4, //!< Internal 16MHz RC oscillator as PCK source clock
+ GENCLK_PCK_SRC_MAINCK_24M_RC = 5, //!< Internal 24MHz RC oscillator as PCK source clock
+ GENCLK_PCK_SRC_MAINCK_XTAL = 6, //!< External crystal oscillator as PCK source clock
+ GENCLK_PCK_SRC_MAINCK_BYPASS = 7, //!< External bypass oscillator as PCK source clock
+ GENCLK_PCK_SRC_PLLACK = 8, //!< Use PLLACK as PCK source clock
+#if SAMG55
+ GENCLK_PCK_SRC_PLLBCK = 9, //!< Use PLLBCK as PCK source clock
+ GENCLK_PCK_SRC_MCK = 10, //!< Use Master Clk as PCK source clock
+#else
+ GENCLK_PCK_SRC_MCK = 9, //!< Use Master Clk as PCK source clock
+#endif
+};
+
+//@}
+
+//! \name Programmable Clock Prescalers (PCK)
+//@{
+
+enum genclk_divider {
+ GENCLK_PCK_PRES_1 = PMC_PCK_PRES_CLK_1, //!< Set PCK clock prescaler to 1
+ GENCLK_PCK_PRES_2 = PMC_PCK_PRES_CLK_2, //!< Set PCK clock prescaler to 2
+ GENCLK_PCK_PRES_4 = PMC_PCK_PRES_CLK_4, //!< Set PCK clock prescaler to 4
+ GENCLK_PCK_PRES_8 = PMC_PCK_PRES_CLK_8, //!< Set PCK clock prescaler to 8
+ GENCLK_PCK_PRES_16 = PMC_PCK_PRES_CLK_16, //!< Set PCK clock prescaler to 16
+ GENCLK_PCK_PRES_32 = PMC_PCK_PRES_CLK_32, //!< Set PCK clock prescaler to 32
+ GENCLK_PCK_PRES_64 = PMC_PCK_PRES_CLK_64, //!< Set PCK clock prescaler to 64
+};
+
+//@}
+
+struct genclk_config {
+ uint32_t ctrl;
+};
+
+static inline void genclk_config_defaults(struct genclk_config *p_cfg,
+ uint32_t ul_id)
+{
+ ul_id = ul_id;
+ p_cfg->ctrl = 0;
+}
+
+static inline void genclk_config_read(struct genclk_config *p_cfg,
+ uint32_t ul_id)
+{
+ p_cfg->ctrl = PMC->PMC_PCK[ul_id];
+}
+
+static inline void genclk_config_write(const struct genclk_config *p_cfg,
+ uint32_t ul_id)
+{
+ PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
+}
+
+//! \name Programmable Clock Source and Prescaler configuration
+//@{
+
+static inline void genclk_config_set_source(struct genclk_config *p_cfg,
+ enum genclk_source e_src)
+{
+ p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);
+
+ switch (e_src) {
+ case GENCLK_PCK_SRC_SLCK_RC:
+ case GENCLK_PCK_SRC_SLCK_XTAL:
+ case GENCLK_PCK_SRC_SLCK_BYPASS:
+ p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK);
+ break;
+
+ case GENCLK_PCK_SRC_MAINCK_8M_RC:
+ case GENCLK_PCK_SRC_MAINCK_16M_RC:
+ case GENCLK_PCK_SRC_MAINCK_24M_RC:
+ case GENCLK_PCK_SRC_MAINCK_XTAL:
+ case GENCLK_PCK_SRC_MAINCK_BYPASS:
+ p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK);
+ break;
+
+ case GENCLK_PCK_SRC_PLLACK:
+ p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK);
+ break;
+
+#if SAMG55
+ case GENCLK_PCK_SRC_PLLBCK:
+ p_cfg->ctrl |= (PMC_PCK_CSS_PLLB_CLK);
+ break;
+#endif
+
+ case GENCLK_PCK_SRC_MCK:
+ p_cfg->ctrl |= (PMC_PCK_CSS_MCK);
+ break;
+ }
+}
+
+static inline void genclk_config_set_divider(struct genclk_config *p_cfg,
+ uint32_t e_divider)
+{
+ p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;
+ p_cfg->ctrl |= e_divider;
+}
+
+//@}
+
+static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id)
+{
+ PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
+ pmc_enable_pck(ul_id);
+}
+
+static inline void genclk_disable(uint32_t ul_id)
+{
+ pmc_disable_pck(ul_id);
+}
+
+static inline void genclk_enable_source(enum genclk_source e_src)
+{
+ switch (e_src) {
+ case GENCLK_PCK_SRC_SLCK_RC:
+ if (!osc_is_ready(OSC_SLCK_32K_RC)) {
+ osc_enable(OSC_SLCK_32K_RC);
+ osc_wait_ready(OSC_SLCK_32K_RC);
+ }
+ break;
+
+ case GENCLK_PCK_SRC_SLCK_XTAL:
+ if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {
+ osc_enable(OSC_SLCK_32K_XTAL);
+ osc_wait_ready(OSC_SLCK_32K_XTAL);
+ }
+ break;
+
+ case GENCLK_PCK_SRC_SLCK_BYPASS:
+ if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {
+ osc_enable(OSC_SLCK_32K_BYPASS);
+ osc_wait_ready(OSC_SLCK_32K_BYPASS);
+ }
+ break;
+
+ case GENCLK_PCK_SRC_MAINCK_8M_RC:
+ if (!osc_is_ready(OSC_MAINCK_8M_RC)) {
+ osc_enable(OSC_MAINCK_8M_RC);
+ osc_wait_ready(OSC_MAINCK_8M_RC);
+ }
+ break;
+
+ case GENCLK_PCK_SRC_MAINCK_16M_RC:
+ if (!osc_is_ready(OSC_MAINCK_16M_RC)) {
+ osc_enable(OSC_MAINCK_16M_RC);
+ osc_wait_ready(OSC_MAINCK_16M_RC);
+ }
+ break;
+
+ case GENCLK_PCK_SRC_MAINCK_24M_RC:
+ if (!osc_is_ready(OSC_MAINCK_24M_RC)) {
+ osc_enable(OSC_MAINCK_24M_RC);
+ osc_wait_ready(OSC_MAINCK_24M_RC);
+ }
+ break;
+
+ case GENCLK_PCK_SRC_MAINCK_XTAL:
+ if (!osc_is_ready(OSC_MAINCK_XTAL)) {
+ osc_enable(OSC_MAINCK_XTAL);
+ osc_wait_ready(OSC_MAINCK_XTAL);
+ }
+ break;
+
+ case GENCLK_PCK_SRC_MAINCK_BYPASS:
+ if (!osc_is_ready(OSC_MAINCK_BYPASS)) {
+ osc_enable(OSC_MAINCK_BYPASS);
+ osc_wait_ready(OSC_MAINCK_BYPASS);
+ }
+ break;
+
+#ifdef CONFIG_PLL0_SOURCE
+ case GENCLK_PCK_SRC_PLLACK:
+ pll_enable_config_defaults(0);
+ break;
+#endif
+
+#if SAMG55
+#ifdef CONFIG_PLL1_SOURCE
+ case GENCLK_PCK_SRC_PLLBCK:
+ pll_enable_config_defaults(1);
+ break;
+#endif
+#endif
+
+ case GENCLK_PCK_SRC_MCK:
+ break;
+
+ default:
+ Assert(false);
+ break;
+ }
+}
+
+//! @}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* CHIP_GENCLK_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/osc.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,226 @@
+/**
+ * \file
+ *
+ * \brief Chip-specific oscillator management functions.
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CHIP_OSC_H_INCLUDED
+#define CHIP_OSC_H_INCLUDED
+
+#include "board.h"
+#include "pmc.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /**
+ * \weakgroup osc_group
+ * @{
+ */
+
+//! \name Oscillator identifiers
+//@{
+#define OSC_SLCK_32K_RC 0 //!< Internal 32kHz RC oscillator.
+#define OSC_SLCK_32K_XTAL 1 //!< External 32kHz crystal oscillator.
+#define OSC_SLCK_32K_BYPASS 2 //!< External 32kHz bypass oscillator.
+#define OSC_MAINCK_8M_RC 3 //!< Internal 8MHz RC oscillator.
+#define OSC_MAINCK_16M_RC 4 //!< Internal 16MHz RC oscillator.
+#define OSC_MAINCK_24M_RC 5 //!< Internal 24MHz RC oscillator.
+#define OSC_MAINCK_XTAL 6 //!< External crystal oscillator.
+#define OSC_MAINCK_BYPASS 7 //!< External bypass oscillator.
+//@}
+
+//! \name Oscillator clock speed in hertz
+//@{
+#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32kHz RC oscillator.
+#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32kHz crystal oscillator.
+#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32kHz bypass oscillator.
+#define OSC_MAINCK_8M_RC_HZ CHIP_FREQ_MAINCK_RC_8MHZ //!< Internal 8MHz RC oscillator.
+#define OSC_MAINCK_16M_RC_HZ CHIP_FREQ_MAINCK_RC_16MHZ //!< Internal 16MHz RC oscillator.
+#define OSC_MAINCK_24M_RC_HZ CHIP_FREQ_MAINCK_RC_24MHZ //!< Internal 24MHz RC oscillator.
+#define OSC_MAINCK_XTAL_HZ BOARD_FREQ_MAINCK_XTAL //!< External crystal oscillator.
+#define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator.
+//@}
+
+ static inline void osc_enable(uint32_t ul_id)
+{
+ switch (ul_id) {
+ case OSC_SLCK_32K_RC:
+ break;
+
+ case OSC_SLCK_32K_XTAL:
+ pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);
+ break;
+
+ case OSC_SLCK_32K_BYPASS:
+ pmc_switch_sclk_to_32kxtal(PMC_OSC_BYPASS);
+ break;
+
+
+ case OSC_MAINCK_8M_RC:
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);
+ break;
+
+ case OSC_MAINCK_16M_RC:
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_16_MHz);
+ break;
+
+ case OSC_MAINCK_24M_RC:
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_24_MHz);
+ break;
+
+
+ case OSC_MAINCK_XTAL:
+ pmc_switch_mainck_to_xtal(PMC_OSC_XTAL,
+ pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US,
+ OSC_SLCK_32K_RC_HZ));
+ break;
+
+ case OSC_MAINCK_BYPASS:
+ pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS,
+ pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US,
+ OSC_SLCK_32K_RC_HZ));
+ break;
+ }
+}
+
+static inline void osc_disable(uint32_t ul_id)
+{
+ switch (ul_id) {
+ case OSC_SLCK_32K_RC:
+ case OSC_SLCK_32K_XTAL:
+ case OSC_SLCK_32K_BYPASS:
+ break;
+
+ case OSC_MAINCK_8M_RC:
+ case OSC_MAINCK_16M_RC:
+ case OSC_MAINCK_24M_RC:
+ pmc_osc_disable_fastrc();
+ break;
+
+ case OSC_MAINCK_XTAL:
+ pmc_osc_disable_xtal(PMC_OSC_XTAL);
+ break;
+
+ case OSC_MAINCK_BYPASS:
+ pmc_osc_disable_xtal(PMC_OSC_BYPASS);
+ break;
+ }
+}
+
+static inline bool osc_is_ready(uint32_t ul_id)
+{
+ switch (ul_id) {
+ case OSC_SLCK_32K_RC:
+ return 1;
+
+ case OSC_SLCK_32K_XTAL:
+ case OSC_SLCK_32K_BYPASS:
+ return pmc_osc_is_ready_32kxtal();
+
+ case OSC_MAINCK_8M_RC:
+ case OSC_MAINCK_16M_RC:
+ case OSC_MAINCK_24M_RC:
+ case OSC_MAINCK_XTAL:
+ case OSC_MAINCK_BYPASS:
+ return pmc_osc_is_ready_mainck();
+ }
+
+ return 0;
+}
+
+static inline uint32_t osc_get_rate(uint32_t ul_id)
+{
+ switch (ul_id) {
+ case OSC_SLCK_32K_RC:
+ return OSC_SLCK_32K_RC_HZ;
+
+#ifdef BOARD_FREQ_SLCK_XTAL
+ case OSC_SLCK_32K_XTAL:
+ return BOARD_FREQ_SLCK_XTAL;
+#endif
+
+#ifdef BOARD_FREQ_SLCK_BYPASS
+ case OSC_SLCK_32K_BYPASS:
+ return BOARD_FREQ_SLCK_BYPASS;
+#endif
+
+ case OSC_MAINCK_8M_RC:
+ return OSC_MAINCK_8M_RC_HZ;
+
+ case OSC_MAINCK_16M_RC:
+ return OSC_MAINCK_16M_RC_HZ;
+
+ case OSC_MAINCK_24M_RC:
+ return OSC_MAINCK_24M_RC_HZ;
+
+#ifdef BOARD_FREQ_MAINCK_XTAL
+ case OSC_MAINCK_XTAL:
+ return BOARD_FREQ_MAINCK_XTAL;
+#endif
+
+#ifdef BOARD_FREQ_MAINCK_BYPASS
+ case OSC_MAINCK_BYPASS:
+ return BOARD_FREQ_MAINCK_BYPASS;
+#endif
+ }
+
+ return 0;
+}
+
+//! @}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* CHIP_OSC_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/pll.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,266 @@
+/**
+ * \file
+ *
+ * \brief Chip-specific PLL definitions.
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CHIP_PLL_H_INCLUDED
+#define CHIP_PLL_H_INCLUDED
+
+#include <osc.h>
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /**
+ * \weakgroup pll_group
+ * @{
+ */
+
+#define PLL_OUTPUT_MIN_HZ 24000000
+#if (SAMG51 || SAMG53)
+#define PLL_OUTPUT_MAX_HZ 48000000
+#endif
+#if (SAMG54)
+#define PLL_OUTPUT_MAX_HZ 96000000
+#endif
+#if (SAMG55)
+#define PLL_OUTPUT_MAX_HZ 120000000
+#endif
+
+#define PLL_INPUT_HZ 32768
+
+#define NR_PLLS 2
+#define PLLA_ID 0
+#define PLLB_ID 1
+
+#define PLL_COUNT 0x3fU
+
+enum pll_source {
+ PLL_SRC_SLCK_RC = OSC_SLCK_32K_RC, //!< Internal 32KHz RC oscillator.
+ PLL_SRC_SLCK_XTAL = OSC_SLCK_32K_XTAL, //!< External 32kHz crystal oscillator.
+ PLL_NR_SOURCES, //!< Number of PLL sources.
+};
+
+struct pll_config {
+ uint32_t ctrl;
+};
+
+#define pll_get_default_rate(pll_id) \
+ ((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE) \
+ * CONFIG_PLL##pll_id##_MUL) \
+ / CONFIG_PLL##pll_id##_DIV)
+
+/**
+ * \note The SAMG PLL hardware interprets mul as mul+1. For readability the hardware mul+1
+ * is hidden in this implementation. Use mul as mul effective value.
+ */
+static inline void pll_config_init(struct pll_config *p_cfg,
+ enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul)
+{
+ uint32_t vco_hz;
+
+ Assert(e_src < PLL_NR_SOURCES);
+ Assert(ul_div < 2);
+
+ /* Calculate internal VCO frequency */
+ vco_hz = osc_get_rate(e_src) / ul_div;
+
+ vco_hz *= ul_mul;
+ Assert(vco_hz >= (PLL_OUTPUT_MIN_HZ - (PLL_OUTPUT_MIN_HZ >> 6)));
+ Assert(vco_hz <= (PLL_OUTPUT_MAX_HZ + (PLL_OUTPUT_MAX_HZ >> 6)));
+
+ /* PMC hardware will automatically make it mul+1 */
+ p_cfg->ctrl = CKGR_PLLAR_MULA(ul_mul - 1) | CKGR_PLLAR_PLLAEN(ul_div) | CKGR_PLLAR_PLLACOUNT(PLL_COUNT);
+}
+
+#define pll_config_defaults(cfg, pll_id) \
+ pll_config_init(cfg, \
+ CONFIG_PLL##pll_id##_SOURCE, \
+ CONFIG_PLL##pll_id##_DIV, \
+ CONFIG_PLL##pll_id##_MUL)
+
+static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id)
+{
+ Assert(ul_pll_id < NR_PLLS);
+
+ if (ul_pll_id == PLLA_ID) {
+ p_cfg->ctrl = PMC->CKGR_PLLAR;
+#if SAMG55
+ } else {
+ p_cfg->ctrl = PMC->CKGR_PLLBR;
+#endif
+ }
+}
+
+static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id)
+{
+ Assert(ul_pll_id < NR_PLLS);
+
+ if (ul_pll_id == PLLA_ID) {
+ pmc_disable_pllack(); // Always stop PLL first!
+ PMC->CKGR_PLLAR = p_cfg->ctrl;
+#if SAMG55
+ } else {
+ pmc_disable_pllbck(); // Always stop PLL first!
+ PMC->CKGR_PLLBR = p_cfg->ctrl;
+#endif
+ }
+}
+
+static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id)
+{
+ Assert(ul_pll_id < NR_PLLS);
+
+ if (ul_pll_id == PLLA_ID) {
+ pmc_disable_pllack(); // Always stop PLL first!
+ PMC->CKGR_PLLAR = p_cfg->ctrl;
+#if SAMG55
+ } else {
+ pmc_disable_pllbck(); // Always stop PLL first!
+ PMC->CKGR_PLLBR = p_cfg->ctrl;
+#endif
+ }
+}
+
+/**
+ * \note This will only disable the selected PLL, not the underlying oscillator (mainck).
+ */
+static inline void pll_disable(uint32_t ul_pll_id)
+{
+ Assert(ul_pll_id < NR_PLLS);
+
+ if (ul_pll_id == PLLA_ID) {
+ pmc_disable_pllack();
+#if SAMG55
+ } else {
+ pmc_disable_pllbck();
+#endif
+ }
+}
+
+static inline uint32_t pll_is_locked(uint32_t ul_pll_id)
+{
+ Assert(ul_pll_id < NR_PLLS);
+
+ if (ul_pll_id == PLLA_ID) {
+ return pmc_is_locked_pllack();
+#if SAMG55
+ } else if (ul_pll_id == PLLB_ID) {
+ return pmc_is_locked_pllbck();
+#endif
+ } else {
+ return 0;
+ }
+}
+
+static inline void pll_enable_source(enum pll_source e_src)
+{
+ switch (e_src) {
+ case PLL_SRC_SLCK_RC:
+ case PLL_SRC_SLCK_XTAL:
+ osc_enable(e_src);
+ osc_wait_ready(e_src);
+ break;
+
+ default:
+ Assert(false);
+ break;
+ }
+}
+
+static inline void pll_enable_config_defaults(unsigned int ul_pll_id)
+{
+ struct pll_config pllcfg;
+
+ if (pll_is_locked(ul_pll_id)) {
+ return; // Pll already running
+ }
+
+ switch (ul_pll_id) {
+#ifdef CONFIG_PLL0_SOURCE
+ case 0:
+ pll_enable_source(CONFIG_PLL0_SOURCE);
+ pll_config_init(&pllcfg,
+ CONFIG_PLL0_SOURCE,
+ CONFIG_PLL0_DIV,
+ CONFIG_PLL0_MUL);
+ break;
+#endif
+
+#if SAMG55
+#ifdef CONFIG_PLL1_SOURCE
+ case 1:
+ pll_enable_source(CONFIG_PLL1_SOURCE);
+ pll_config_init(&pllcfg,
+ CONFIG_PLL1_SOURCE,
+ CONFIG_PLL1_DIV,
+ CONFIG_PLL1_MUL);
+ break;
+#endif
+#endif
+
+ default:
+ Assert(false);
+ break;
+ }
+ pll_enable(&pllcfg, ul_pll_id);
+ while (!pll_is_locked(ul_pll_id));
+}
+
+//! @}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* CHIP_PLL_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/sysclk.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,307 @@
+/**
+ * \file
+ *
+ * \brief Chip-specific system clock management functions.
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <sysclk.h>
+#include <supc.h>
+#include <efc.h>
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /**
+ * \weakgroup sysclk_group
+ * @{
+ */
+
+#if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
+ /**
+ * \brief boolean signalling that the sysclk_init is done.
+ */
+ uint32_t sysclk_initialized = 0;
+#endif
+
+ /**
+ * \brief Set system clock prescaler configuration
+ *
+ * This function will change the system clock prescaler configuration to
+ * match the parameters.
+ *
+ * \note The parameters to this function are device-specific.
+ *
+ * \param cpu_shift The CPU clock will be divided by \f$2^{mck\_pres}\f$
+ */
+ void sysclk_set_prescalers(uint32_t ul_pres)
+{
+ pmc_mck_set_prescaler(ul_pres);
+ SystemCoreClockUpdate();
+}
+
+/**
+ * \brief Change the source of the main system clock.
+ *
+ * \param src The new system clock source. Must be one of the constants
+ * from the <em>System Clock Sources</em> section.
+ */
+void sysclk_set_source(uint32_t ul_src)
+{
+ switch (ul_src) {
+ case SYSCLK_SRC_SLCK_RC:
+ case SYSCLK_SRC_SLCK_XTAL:
+ case SYSCLK_SRC_SLCK_BYPASS:
+ pmc_mck_set_source(PMC_MCKR_CSS_SLOW_CLK);
+ break;
+
+ case SYSCLK_SRC_MAINCK_8M_RC:
+ case SYSCLK_SRC_MAINCK_16M_RC:
+ case SYSCLK_SRC_MAINCK_24M_RC:
+ case SYSCLK_SRC_MAINCK_XTAL:
+ case SYSCLK_SRC_MAINCK_BYPASS:
+ pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK);
+ break;
+
+ case SYSCLK_SRC_PLLACK:
+ pmc_mck_set_source(PMC_MCKR_CSS_PLLA_CLK);
+ break;
+
+#if SAMG55
+ case SYSCLK_SRC_PLLBCK:
+ pmc_mck_set_source(PMC_MCKR_CSS_PLLB_CLK);
+ break;
+#endif
+ }
+ SystemCoreClockUpdate();
+}
+
+#if SAMG55
+#if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__)
+/**
+ * \brief Enable USB clock.
+ *
+ *
+ * \param pll_id Source of the USB clock.
+ * \param div Actual clock divisor. Must be superior to 0.
+ */
+void sysclk_enable_usb(void)
+{
+ Assert(CONFIG_USBCLK_DIV > 0);
+
+#ifdef CONFIG_PLL0_SOURCE
+ if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL0) {
+ struct pll_config pllcfg;
+
+ pll_enable_source(CONFIG_PLL0_SOURCE);
+ pll_config_defaults(&pllcfg, 0);
+ pll_enable(&pllcfg, 0);
+ pll_wait_for_lock(0);
+#ifdef UHD_ENABLE
+ pmc_switch_uhpck_to_pllack(CONFIG_USBCLK_DIV - 1);
+ pmc_enable_uhpck();
+#else
+ pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1);
+ pmc_enable_udpck();
+#endif
+ return;
+ }
+#endif
+
+#ifdef CONFIG_PLL1_SOURCE
+ if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL1) {
+ struct pll_config pllcfg;
+
+ pll_enable_source(CONFIG_PLL1_SOURCE);
+ pll_config_defaults(&pllcfg, 1);
+ pll_enable(&pllcfg, 1);
+ pll_wait_for_lock(1);
+#ifdef UHD_ENABLE
+ pmc_switch_uhpck_to_pllbck(CONFIG_USBCLK_DIV - 1);
+ pmc_enable_uhpck();
+#else
+ pmc_switch_udpck_to_pllbck(CONFIG_USBCLK_DIV - 1);
+ pmc_enable_udpck();
+#endif
+ return;
+ }
+#endif
+}
+
+/**
+ * \brief Disable the USB clock.
+ *
+ * \note This implementation does not switch off the PLL, it just turns off the USB clock.
+ */
+void sysclk_disable_usb(void)
+{
+ pmc_disable_udpck();
+}
+#endif // CONFIG_USBCLK_SOURCE
+#endif
+
+void sysclk_init(void)
+{
+#if SAMG54
+ uint32_t unique_id[32];
+ uint32_t trim_value;
+#endif
+
+ /* Set flash wait state to max in case the below clock switching. */
+ system_init_flash(CHIP_FREQ_CPU_MAX);
+
+ /* Config system clock setting */
+ if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) {
+ osc_enable(OSC_SLCK_32K_RC);
+ osc_wait_ready(OSC_SLCK_32K_RC);
+ pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
+ }
+
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) {
+ osc_enable(OSC_SLCK_32K_XTAL);
+ osc_wait_ready(OSC_SLCK_32K_XTAL);
+ pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
+ }
+
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) {
+ osc_enable(OSC_SLCK_32K_BYPASS);
+ osc_wait_ready(OSC_SLCK_32K_BYPASS);
+ pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
+ }
+
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) {
+ /* Already running from SYSCLK_SRC_MAINCK_8M_RC */
+ }
+
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_16M_RC) {
+ osc_enable(OSC_MAINCK_16M_RC);
+ osc_wait_ready(OSC_MAINCK_16M_RC);
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
+ }
+
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_24M_RC) {
+ osc_enable(OSC_MAINCK_24M_RC);
+ osc_wait_ready(OSC_MAINCK_24M_RC);
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
+ }
+
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) {
+ osc_enable(OSC_MAINCK_XTAL);
+ osc_wait_ready(OSC_MAINCK_XTAL);
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
+ }
+
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) {
+ osc_enable(OSC_MAINCK_BYPASS);
+ osc_wait_ready(OSC_MAINCK_BYPASS);
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
+ }
+
+#ifdef CONFIG_PLL0_SOURCE
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) {
+ struct pll_config pllcfg;
+
+ pll_enable_source(CONFIG_PLL0_SOURCE);
+ pll_config_defaults(&pllcfg, 0);
+ pll_enable(&pllcfg, 0);
+ pll_wait_for_lock(0);
+ pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES);
+ }
+#endif
+
+#if SAMG55
+#ifdef CONFIG_PLL1_SOURCE
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLBCK) {
+ struct pll_config pllcfg;
+
+ pll_enable_source(CONFIG_PLL1_SOURCE);
+ pll_config_defaults(&pllcfg, 1);
+ pll_enable(&pllcfg, 1);
+ pll_wait_for_lock(1);
+ pmc_switch_mck_to_pllbck(CONFIG_SYSCLK_PRES);
+ }
+#endif
+#endif
+
+ /* Update the SystemFrequency variable */
+ SystemCoreClockUpdate();
+
+ /* Set a flash wait state depending on the new cpu frequency */
+ system_init_flash(sysclk_get_cpu_hz());
+
+#if SAMG54
+ /* Set the trim value when system run near 96M */
+ if ((SystemCoreClock <= (CHIP_FREQ_CPU_MAX + (CHIP_FREQ_CPU_MAX >> 3))) &&
+ (SystemCoreClock >= (CHIP_FREQ_CPU_MAX - (CHIP_FREQ_CPU_MAX >> 3)))) {
+ /* Get the trim value from unique ID area */
+ efc_perform_read_sequence(EFC, EFC_FCMD_STUI, EFC_FCMD_SPUI,
+ unique_id, 32);
+#ifdef BOARD_VDDIO_18
+ trim_value = unique_id[0x10] & 0x000000FF;
+ supc_set_regulator_trim_user(SUPC, trim_value);
+#else
+ trim_value = unique_id[0x14] & 0x000000FF;
+ supc_set_regulator_trim_user(SUPC, trim_value);
+#endif
+ }
+#endif
+
+#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
+ /* Signal that the internal frequencies are setup */
+ sysclk_initialized = 1;
+#endif
+}
+
+//! @}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/samg/sysclk.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,385 @@
+/**
+ * \file
+ *
+ * \brief Chip-specific system clock management functions.
+ *
+ * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CHIP_SYSCLK_H_INCLUDED
+#define CHIP_SYSCLK_H_INCLUDED
+
+#include <osc.h>
+#include <pll.h>
+
+/**
+ * \page sysclk_quickstart Quick Start Guide for the System Clock Management service (SAMG51)
+ *
+ * This is the quick start guide for the \ref sysclk_group "System Clock Management"
+ * service, with step-by-step instructions on how to configure and use the service for
+ * specific use cases.
+ *
+ * \section sysclk_quickstart_usecases System Clock Management use cases
+ * - \ref sysclk_quickstart_basic
+ *
+ * \section sysclk_quickstart_basic Basic usage of the System Clock Management service
+ * This section will present a basic use case for the System Clock Management service.
+ * This use case will configure the main system clock to 100Hz, using an internal PLL
+ * module to multiply the frequency of a crystal attached to the microcontroller.
+ *
+ * \subsection sysclk_quickstart_use_case_1_prereq Prerequisites
+ * - None
+ *
+ * \subsection sysclk_quickstart_use_case_1_setup_steps Initialization code
+ * Add to the application initialization code:
+ * \code
+ sysclk_init();
+\endcode
+ *
+ * \subsection sysclk_quickstart_use_case_1_setup_steps_workflow Workflow
+ * -# Configure the system clocks according to the settings in conf_clock.h:
+ * \code sysclk_init(); \endcode
+ *
+ * \subsection sysclk_quickstart_use_case_1_example_code Example code
+ * Add or uncomment the following in your conf_clock.h header file, commenting out all other
+ * definitions of the same symbol(s):
+ * \code
+ #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
+
+ // Fpll0 = (Fclk * PLL_mul) / PLL_div
+ #define CONFIG_PLL0_SOURCE PLL_SRC_SCLK_RC
+ #define CONFIG_PLL0_MUL (1500)
+ #define CONFIG_PLL0_DIV 1
+
+ // Fbus = Fsys / BUS_div
+ #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
+\endcode
+ *
+ * \subsection sysclk_quickstart_use_case_1_example_workflow Workflow
+ * -# Configure the main system clock to use the output of the PLL module as its source:
+ * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode
+ * -# Configure the PLL module to use the fast external fast crystal oscillator as its source:
+ * \code #define CONFIG_PLL0_SOURCE PLL_SRC_SCLK_RC \endcode
+ * -# Configure the PLL module to multiply the internal 32K RC frequency up to 48MHz:
+ * \code
+ #define CONFIG_PLL0_MUL (1500)
+ #define CONFIG_PLL0_DIV 1
+\endcode
+ * -# Configure the main clock to run at the full 48MHz, disable scaling of the main system clock speed:
+ * \code
+ #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
+\endcode
+ * \note Some dividers are powers of two, while others are integer division factors. Refer to the
+ * formulas in the conf_clock.h template commented above each division define.
+ */
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+ /**
+ * \weakgroup sysclk_group
+ * @{
+ */
+
+//! \name Configuration Symbols
+//@{
+ /**
+ * \def CONFIG_SYSCLK_SOURCE
+ * \brief Initial/static main system clock source
+ *
+ * The main system clock will be configured to use this clock during
+ * initialization.
+ */
+#ifndef CONFIG_SYSCLK_SOURCE
+# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC
+#endif
+ /**
+ * \def CONFIG_SYSCLK_PRES
+ * \brief Initial CPU clock divider (mck)
+ *
+ * The MCK will run at
+ * \f[
+ * f_{MCK} = \frac{f_{sys}}{\mathrm{CONFIG\_SYSCLK\_PRES}}\,\mbox{Hz}
+ * \f]
+ * after initialization.
+ */
+#ifndef CONFIG_SYSCLK_PRES
+# define CONFIG_SYSCLK_PRES 0
+#endif
+
+//@}
+
+//! \name Master Clock Sources (MCK)
+//@{
+#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock
+#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock
+#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock
+#define SYSCLK_SRC_MAINCK_8M_RC 3 //!< Internal 8MHz RC oscillator as master source clock
+#define SYSCLK_SRC_MAINCK_16M_RC 4 //!< Internal 16MHz RC oscillator as master source clock
+#define SYSCLK_SRC_MAINCK_24M_RC 5 //!< Internal 24MHz RC oscillator as master source clock
+#define SYSCLK_SRC_MAINCK_XTAL 6 //!< External crystal oscillator as master source clock
+#define SYSCLK_SRC_MAINCK_BYPASS 7 //!< External bypass oscillator as master source clock
+#define SYSCLK_SRC_PLLACK 8 //!< Use PLLACK as master source clock
+#if SAMG55
+#define SYSCLK_SRC_PLLBCK 9 //!< Use PLLBCK as master source clock
+#endif
+//@}
+
+//! \name Master Clock Prescalers (MCK)
+//@{
+#define SYSCLK_PRES_1 PMC_MCKR_PRES_CLK_1 //!< Set master clock prescaler to 1
+#define SYSCLK_PRES_2 PMC_MCKR_PRES_CLK_2 //!< Set master clock prescaler to 2
+#define SYSCLK_PRES_4 PMC_MCKR_PRES_CLK_4 //!< Set master clock prescaler to 4
+#define SYSCLK_PRES_8 PMC_MCKR_PRES_CLK_8 //!< Set master clock prescaler to 8
+#define SYSCLK_PRES_16 PMC_MCKR_PRES_CLK_16 //!< Set master clock prescaler to 16
+#define SYSCLK_PRES_32 PMC_MCKR_PRES_CLK_32 //!< Set master clock prescaler to 32
+#define SYSCLK_PRES_64 PMC_MCKR_PRES_CLK_64 //!< Set master clock prescaler to 64
+#define SYSCLK_PRES_3 PMC_MCKR_PRES_CLK_3 //!< Set master clock prescaler to 3
+//@}
+
+#if SAMG55
+//! \name USB Clock Sources
+//@{
+#define USBCLK_SRC_PLL0 0 //!< Use PLLA
+#define USBCLK_SRC_PLL1 1 //!< Use PLLB
+//@}
+
+ /**
+ * \def CONFIG_USBCLK_SOURCE
+ * \brief Configuration symbol for the USB generic clock source
+ *
+ * Sets the clock source to use for the USB. The source must also be properly
+ * configured.
+ *
+ * Define this to one of the \c USBCLK_SRC_xxx settings. Leave it undefined if
+ * USB is not required.
+ */
+#ifdef __DOXYGEN__
+# define CONFIG_USBCLK_SOURCE
+#endif
+
+ /**
+ * \def CONFIG_USBCLK_DIV
+ * \brief Configuration symbol for the USB generic clock divider setting
+ *
+ * Sets the clock division for the USB generic clock. If a USB clock source is
+ * selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be
+ * defined.
+ */
+#ifdef __DOXYGEN__
+# define CONFIG_USBCLK_DIV
+#endif
+#endif
+
+ /**
+ * \name Querying the system clock
+ *
+ * The following functions may be used to query the current frequency of
+ * the system clock and the CPU and bus clocks derived from it.
+ * sysclk_get_main_hz() and sysclk_get_cpu_hz() can be assumed to be
+ * available on all platforms, although some platforms may define
+ * additional accessors for various chip-internal bus clocks. These are
+ * usually not intended to be queried directly by generic code.
+ */
+//@{
+
+ /**
+ * \brief Return the current rate in Hz of the main system clock
+ *
+ * \todo This function assumes that the main clock source never changes
+ * once it's been set up, and that PLL0 always runs at the compile-time
+ * configured default rate. While this is probably the most common
+ * configuration, which we want to support as a special case for
+ * performance reasons, we will at some point need to support more
+ * dynamic setups as well.
+ */
+#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
+ extern uint32_t sysclk_initialized;
+#endif
+ static inline uint32_t sysclk_get_main_hz(void)
+{
+#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
+ if (!sysclk_initialized ) {
+ return OSC_MAINCK_8M_RC_HZ;
+ }
+#endif
+
+ /* Config system clock setting */
+ if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) {
+ return OSC_SLCK_32K_RC_HZ;
+ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) {
+ return OSC_SLCK_32K_XTAL_HZ;
+ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) {
+ return OSC_SLCK_32K_BYPASS_HZ;
+ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) {
+ return OSC_MAINCK_8M_RC_HZ;
+ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_16M_RC) {
+ return OSC_MAINCK_16M_RC_HZ;
+ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_24M_RC) {
+ return OSC_MAINCK_24M_RC_HZ;
+ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) {
+ return OSC_MAINCK_XTAL_HZ;
+ } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) {
+ return OSC_MAINCK_BYPASS_HZ;
+ }
+#ifdef CONFIG_PLL0_SOURCE
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) {
+ return pll_get_default_rate(0);
+ }
+#endif
+
+#if SAMG55
+#ifdef CONFIG_PLL1_SOURCE
+ else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLBCK) {
+ return pll_get_default_rate(1);
+ }
+#endif
+#endif
+
+ else {
+ /* unhandled_case(CONFIG_SYSCLK_SOURCE); */
+ return 0;
+ }
+}
+
+/**
+ * \brief Return the current rate in Hz of the CPU clock
+ *
+ * \todo This function assumes that the CPU always runs at the system
+ * clock frequency. We want to support at least two more scenarios:
+ * Fixed CPU/bus clock dividers (config symbols) and dynamic CPU/bus
+ * clock dividers (which may change at run time). Ditto for all the bus
+ * clocks.
+ *
+ * \return Frequency of the CPU clock, in Hz.
+ */
+static inline uint32_t sysclk_get_cpu_hz(void)
+{
+ /* CONFIG_SYSCLK_PRES is the register value for setting the expected */
+ /* prescaler, not an immediate value. */
+ return sysclk_get_main_hz() /
+ ((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 :
+ (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos)));
+}
+
+/**
+ * \brief Retrieves the current rate in Hz of the peripheral clocks.
+ *
+ * \return Frequency of the peripheral clocks, in Hz.
+ */
+static inline uint32_t sysclk_get_peripheral_hz(void)
+{
+ /* CONFIG_SYSCLK_PRES is the register value for setting the expected */
+ /* prescaler, not an immediate value. */
+ return sysclk_get_main_hz() /
+ ((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 :
+ (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos)));
+}
+
+/**
+ * \brief Retrieves the current rate in Hz of the Peripheral Bus clock attached
+ * to the specified peripheral.
+ *
+ * \param module Pointer to the module's base address.
+ *
+ * \return Frequency of the bus attached to the specified peripheral, in Hz.
+ */
+static inline uint32_t sysclk_get_peripheral_bus_hz(const volatile void *module)
+{
+ UNUSED(module);
+ return sysclk_get_peripheral_hz();
+}
+//@}
+
+//! \name Enabling and disabling synchronous clocks
+//@{
+
+/**
+ * \brief Enable a peripheral's clock.
+ *
+ * \param ul_id Id (number) of the peripheral clock.
+ */
+static inline void sysclk_enable_peripheral_clock(uint32_t ul_id)
+{
+ pmc_enable_periph_clk(ul_id);
+}
+
+/**
+ * \brief Disable a peripheral's clock.
+ *
+ * \param ul_id Id (number) of the peripheral clock.
+ */
+static inline void sysclk_disable_peripheral_clock(uint32_t ul_id)
+{
+ pmc_disable_periph_clk(ul_id);
+}
+
+//@}
+
+//! \name System Clock Source and Prescaler configuration
+//@{
+
+extern void sysclk_set_prescalers(uint32_t ul_pres);
+extern void sysclk_set_source(uint32_t ul_src);
+
+//@}
+
+extern void sysclk_enable_usb(void);
+extern void sysclk_disable_usb(void);
+
+extern void sysclk_init(void);
+
+//! @}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* CHIP_SYSCLK_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/clock/sysclk.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,194 @@
+/**
+ * \file
+ *
+ * \brief System clock management
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SYSCLK_H_INCLUDED
+#define SYSCLK_H_INCLUDED
+
+#include "parts.h"
+#include "conf_clock.h"
+
+#if SAM3S
+# include "sam3s/sysclk.h"
+#elif SAM3U
+# include "sam3u/sysclk.h"
+#elif SAM3N
+# include "sam3n/sysclk.h"
+#elif SAM3XA
+# include "sam3x/sysclk.h"
+#elif SAM4S
+# include "sam4s/sysclk.h"
+#elif SAM4E
+# include "sam4e/sysclk.h"
+#elif SAM4C
+# include "sam4c/sysclk.h"
+#elif SAM4CM
+# include "sam4cm/sysclk.h"
+#elif SAM4CP
+# include "sam4cp/sysclk.h"
+#elif SAM4L
+# include "sam4l/sysclk.h"
+#elif SAM4N
+# include "sam4n/sysclk.h"
+#elif SAMG
+# include "samg/sysclk.h"
+#elif SAMV71
+# include "samv71/sysclk.h"
+#elif SAMV70
+# include "samv70/sysclk.h"
+#elif SAME70
+# include "same70/sysclk.h"
+#elif SAMS70
+# include "sams70/sysclk.h"
+#elif (UC3A0 || UC3A1)
+# include "uc3a0_a1/sysclk.h"
+#elif UC3A3
+# include "uc3a3_a4/sysclk.h"
+#elif UC3B
+# include "uc3b0_b1/sysclk.h"
+#elif UC3C
+# include "uc3c/sysclk.h"
+#elif UC3D
+# include "uc3d/sysclk.h"
+#elif UC3L
+# include "uc3l/sysclk.h"
+#elif XMEGA
+# include "xmega/sysclk.h"
+#elif MEGA
+# include "mega/sysclk.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ * \defgroup clk_group Clock Management
+ */
+
+/**
+ * \ingroup clk_group
+ * \defgroup sysclk_group System Clock Management
+ *
+ * See \ref sysclk_quickstart.
+ *
+ * The <em>sysclk</em> API covers the <em>system clock</em> and all
+ * clocks derived from it. The system clock is a chip-internal clock on
+ * which all <em>synchronous clocks</em>, i.e. CPU and bus/peripheral
+ * clocks, are based. The system clock is typically generated from one
+ * of a variety of sources, which may include crystal and RC oscillators
+ * as well as PLLs. The clocks derived from the system clock are
+ * sometimes also known as <em>synchronous clocks</em>, since they
+ * always run synchronously with respect to each other, as opposed to
+ * <em>generic clocks</em> which may run from different oscillators or
+ * PLLs.
+ *
+ * Most applications should simply call sysclk_init() to initialize
+ * everything related to the system clock and its source (oscillator,
+ * PLL or DFLL), and leave it at that. More advanced applications, and
+ * platform-specific drivers, may require additional services from the
+ * clock system, some of which may be platform-specific.
+ *
+ * \section sysclk_group_platform Platform Dependencies
+ *
+ * The sysclk API is partially chip- or platform-specific. While all
+ * platforms provide mostly the same functionality, there are some
+ * variations around how different bus types and clock tree structures
+ * are handled.
+ *
+ * The following functions are available on all platforms with the same
+ * parameters and functionality. These functions may be called freely by
+ * portable applications, drivers and services:
+ * - sysclk_init()
+ * - sysclk_set_source()
+ * - sysclk_get_main_hz()
+ * - sysclk_get_cpu_hz()
+ * - sysclk_get_peripheral_bus_hz()
+ *
+ * The following functions are available on all platforms, but there may
+ * be variations in the function signature (i.e. parameters) and
+ * behavior. These functions are typically called by platform-specific
+ * parts of drivers, and applications that aren't intended to be
+ * portable:
+ * - sysclk_enable_peripheral_clock()
+ * - sysclk_disable_peripheral_clock()
+ * - sysclk_enable_module()
+ * - sysclk_disable_module()
+ * - sysclk_module_is_enabled()
+ * - sysclk_set_prescalers()
+ *
+ * All other functions should be considered platform-specific.
+ * Enabling/disabling clocks to specific peripherals as well as
+ * determining the speed of these clocks should be done by calling
+ * functions provided by the driver for that peripheral.
+ *
+ * @{
+ */
+
+//! \name System Clock Initialization
+//@{
+/**
+ * \fn void sysclk_init(void)
+ * \brief Initialize the synchronous clock system.
+ *
+ * This function will initialize the system clock and its source. This
+ * includes:
+ * - Mask all synchronous clocks except for any clocks which are
+ * essential for normal operation (for example internal memory
+ * clocks).
+ * - Set up the system clock prescalers as specified by the
+ * application's configuration file.
+ * - Enable the clock source specified by the application's
+ * configuration file (oscillator or PLL) and wait for it to become
+ * stable.
+ * - Set the main system clock source to the clock specified by the
+ * application's configuration file.
+ *
+ * Since all non-essential peripheral clocks are initially disabled, it
+ * is the responsibility of the peripheral driver to re-enable any
+ * clocks that are needed for normal operation.
+ */
+//@}
+
+//! @}
+
+#endif /* SYSCLK_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/delay/delay.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,139 @@
+/**
+ * \file
+ *
+ * \brief Common Delay Service
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef _DELAY_H_
+#define _DELAY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <sysclk.h>
+
+#if UC3
+# include <cycle_counter.h>
+#elif XMEGA
+# include "xmega/cycle_counter.h"
+#elif MEGA
+# include "mega/cycle_counter.h"
+#elif SAM
+# include "sam/cycle_counter.h"
+#endif
+
+/**
+ * @defgroup group_common_services_delay Busy-Wait Delay Routines
+ *
+ * This module provides simple loop-based delay routines for those
+ * applications requiring a brief wait during execution. Common API
+ * for UC3, XMEGA, and AVR MEGA.
+ *
+ * @{
+ */
+
+/**
+ * @def F_CPU
+ * @brief MCU Clock Frequency (Hertz)
+ *
+ * @deprecated
+ * The \ref F_CPU configuration constant is used for compatibility with the
+ * \ref group_common_services_delay routines. The common loop-based delay
+ * routines are designed to use the \ref clk_group modules while anticipating
+ * support for legacy applications assuming a statically defined clock
+ * frequency. Applications using a statically configured MCU clock frequency
+ * can define \ref F_CPU (Hertz), in which case the common delay routines will
+ * use this value rather than calling sysclk_get_cpu_hz() to get the current
+ * MCU clock frequency.
+ */
+#ifndef F_CPU
+# define F_CPU sysclk_get_cpu_hz()
+#endif
+
+/**
+ * @def delay_init
+ *
+ * @brief Initialize the delay driver.
+ * @param fcpu_hz CPU frequency in Hz
+ *
+ * @deprecated
+ * This function is provided for compatibility with ASF applications that
+ * may not have been updated to configure the system clock via the common
+ * clock service; e.g. sysclk_init() and a configuration header file are
+ * used to configure clocks.
+ *
+ * The functions in this module call \ref sysclk_get_cpu_hz() function to
+ * obtain the system clock frequency.
+ */
+#define delay_init(fcpu_hz)
+
+/**
+ * @def delay_s
+ * @brief Delay in seconds.
+ * @param delay Delay in seconds
+ */
+#define delay_s(delay) cpu_delay_ms(1000 * delay, F_CPU)
+
+/**
+ * @def delay_ms
+ * @brief Delay in milliseconds.
+ * @param delay Delay in milliseconds
+ */
+#define delay_ms(delay) cpu_delay_ms(delay, F_CPU)
+
+/**
+ * @def delay_us
+ * @brief Delay in microseconds.
+ * @param delay Delay in microseconds
+ */
+#define delay_us(delay) cpu_delay_us(delay, F_CPU)
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* _DELAY_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/delay/sam/cycle_counter.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,61 @@
+/**
+ * \file
+ *
+ * \brief ARM functions for busy-wait delay loops
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "cycle_counter.h"
+
+// Delay loop is put to SRAM so that FWS will not affect delay time
+OPTIMIZE_HIGH
+RAMFUNC
+void portable_delay_cycles(unsigned long n)
+{
+ UNUSED(n);
+
+ __asm (
+ "loop: DMB \n"
+ "SUBS R0, R0, #1 \n"
+ "BNE.N loop "
+ );
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/delay/sam/cycle_counter.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,126 @@
+/**
+ * \file
+ *
+ * \brief ARM functions for busy-wait delay loops
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef _cycle_counter_h_
+#define _cycle_counter_h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include <compiler.h>
+
+/**
+ * @name Convenience functions for busy-wait delay loops
+ *
+ * @def delay_cycles
+ * @brief Delay program execution for a specified number of CPU cycles.
+ * @param n number of CPU cycles to wait
+ *
+ * @def cpu_delay_ms
+ * @brief Delay program execution for a specified number of milliseconds.
+ * @param delay number of milliseconds to wait
+ * @param f_cpu CPU frequency in Hertz
+ *
+ * @def cpu_delay_us
+ * @brief Delay program execution for a specified number of microseconds.
+ * @param delay number of microseconds to wait
+ * @param f_cpu CPU frequency in Hertz
+ *
+ * @def cpu_ms_2_cy
+ * @brief Convert milli-seconds into CPU cycles.
+ * @param ms number of milliseconds
+ * @param f_cpu CPU frequency in Hertz
+ * @return the converted number of CPU cycles
+ *
+ * @def cpu_us_2_cy
+ * @brief Convert micro-seconds into CPU cycles.
+ * @param ms number of microseconds
+ * @param f_cpu CPU frequency in Hertz
+ * @return the converted number of CPU cycles
+ *
+ * @{
+ */
+
+/**
+ * \brief Delay loop to delay n number of cycles
+ *
+ * \note The function runs in internal RAM so that flash wait states
+ * will not affect the delay time.
+ *
+ * \param n Number of cycles
+ */
+void portable_delay_cycles(unsigned long n);
+
+/* Cortex-M7 is faster than Cortex-M3/M4/M0+ */
+#ifdef __CM7_REV
+
+# define cpu_ms_2_cy(ms, f_cpu) \
+ (((uint64_t)(ms) * (f_cpu) + (uint64_t)(5.932e3 - 1ul)) / (uint64_t)5.932e3)
+# define cpu_us_2_cy(us, f_cpu) \
+ (((uint64_t)(us) * (f_cpu) + (uint64_t)(5.932e6 - 1ul)) / (uint64_t)5.932e6)
+
+#else
+
+# define cpu_ms_2_cy(ms, f_cpu) \
+ (((uint64_t)(ms) * (f_cpu) + (uint64_t)(14e3 - 1ul)) / (uint64_t)14e3)
+# define cpu_us_2_cy(us, f_cpu) \
+ (((uint64_t)(us) * (f_cpu) + (uint64_t)(14e6 - 1ul)) / (uint64_t)14e6)
+
+#endif
+
+#define delay_cycles portable_delay_cycles
+
+#define cpu_delay_ms(delay, f_cpu) delay_cycles(cpu_ms_2_cy(delay, f_cpu))
+#define cpu_delay_us(delay, f_cpu) delay_cycles(cpu_us_2_cy(delay, f_cpu))
+//! @}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _cycle_counter_h_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/gpio/gpio.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,86 @@ +/** + * \file + * + * \brief Common GPIO API. + * + * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ +#ifndef _GPIO_H_ +#define _GPIO_H_ + +#include <parts.h> + +#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +# include "sam_gpio/sam_gpio.h" +#elif XMEGA +# include "xmega_gpio/xmega_gpio.h" +#elif MEGA || MEGA_RF +# include "mega_gpio/mega_gpio.h" +#else +# error Unsupported chip type +#endif + +/** + * \defgroup gpio_group General Purpose Input/Output + * + * This is the common API for GPIO. Additional features are available + * in the documentation of the specific modules. + * + * \section io_group_platform Platform Dependencies + * + * The following functions are available on all platforms, but there may + * be variations in the function signature (i.e. parameters) and + * behaviour. These functions are typically called by platform-specific + * parts of drivers, and applications that aren't intended to be + * portable: + * - gpio_pin_is_low() + * - gpio_pin_is_high() + * - gpio_set_pin_high() + * - gpio_set_pin_group_high() + * - gpio_set_pin_low() + * - gpio_set_pin_group_low() + * - gpio_toggle_pin() + * - gpio_toggle_pin_group() + * - gpio_configure_pin() + * - gpio_configure_group() + */ + +#endif /* _GPIO_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/gpio/sam_gpio/sam_gpio.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,83 @@ +/** + * \file + * + * \brief GPIO service for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#ifndef SAM_GPIO_H_INCLUDED +#define SAM_GPIO_H_INCLUDED + +#include "compiler.h" +#include "pio.h" + +#define gpio_pin_is_low(io_id) \ + (pio_get_pin_value(io_id) ? 0 : 1) + +#define gpio_pin_is_high(io_id) \ + (pio_get_pin_value(io_id) ? 1 : 0) + +#define gpio_set_pin_high(io_id) \ + pio_set_pin_high(io_id) + +#define gpio_set_pin_low(io_id) \ + pio_set_pin_low(io_id) + +#define gpio_toggle_pin(io_id) \ + pio_toggle_pin(io_id) + +#define gpio_configure_pin(io_id,io_flags) \ + pio_configure_pin(io_id,io_flags) + +#define gpio_configure_group(port_id,port_mask,io_flags) \ + pio_configure_pin_group(port_id,port_mask,io_flags) + +#define gpio_set_pin_group_high(port_id,mask) \ + pio_set_pin_group_high(port_id,mask) + +#define gpio_set_pin_group_low(port_id,mask) \ + pio_set_pin_group_low(port_id,mask) + +#define gpio_toggle_pin_group(port_id,mask) \ + pio_toggle_pin_group(port_id,mask) + +#endif /* SAM_GPIO_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/ioport/ioport.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,541 @@
+/**
+ * \file
+ *
+ * \brief Common IOPORT service main header file for AVR, UC3 and ARM
+ * architectures.
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef IOPORT_H
+#define IOPORT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <parts.h>
+#include <compiler.h>
+
+/**
+ * \defgroup ioport_group Common IOPORT API
+ *
+ * See \ref ioport_quickstart.
+ *
+ * This is common IOPORT service for GPIO pin configuration and control in a
+ * standardized manner across the MEGA, MEGA_RF, XMEGA, UC3 and ARM devices.
+ *
+ * Port pin control code is optimized for each platform, and should produce
+ * both compact and fast execution times when used with constant values.
+ *
+ * \section dependencies Dependencies
+ * This driver depends on the following modules:
+ * - \ref sysclk_group for clock speed and functions.
+ * @{
+ */
+
+/**
+ * \def IOPORT_CREATE_PIN(port, pin)
+ * \brief Create IOPORT pin number
+ *
+ * Create a IOPORT pin number for use with the IOPORT functions.
+ *
+ * \param port IOPORT port (e.g. PORTA, PA or PIOA depending on chosen
+ * architecture)
+ * \param pin IOPORT zero-based index of the I/O pin
+ */
+
+/** \brief IOPORT pin directions */
+enum ioport_direction {
+ IOPORT_DIR_INPUT, /*!< IOPORT input direction */
+ IOPORT_DIR_OUTPUT, /*!< IOPORT output direction */
+};
+
+/** \brief IOPORT levels */
+enum ioport_value {
+ IOPORT_PIN_LEVEL_LOW, /*!< IOPORT pin value low */
+ IOPORT_PIN_LEVEL_HIGH, /*!< IOPORT pin value high */
+};
+
+#if MEGA_RF
+/** \brief IOPORT edge sense modes */
+enum ioport_sense {
+ IOPORT_SENSE_LEVEL, /*!< IOPORT sense low level */
+ IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
+ IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */
+ IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */
+};
+#elif SAM && !SAM4L
+/** \brief IOPORT edge sense modes */
+enum ioport_sense {
+ IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
+ IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */
+ IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */
+ IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level */
+ IOPORT_SENSE_LEVEL_HIGH,/*!< IOPORT sense High level */
+};
+#else
+enum ioport_sense {
+ IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
+ IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */
+ IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */
+};
+#endif
+
+
+#if XMEGA
+# include "xmega/ioport.h"
+# if defined(IOPORT_XMEGA_COMPAT)
+# include "xmega/ioport_compat.h"
+# endif
+#elif MEGA
+# include "mega/ioport.h"
+#elif UC3
+# include "uc3/ioport.h"
+#elif SAM
+# if SAM4L
+# include "sam/ioport_gpio.h"
+# elif (SAMD20 | SAMD21)
+# include "sam0/ioport.h"
+# else
+# include "sam/ioport_pio.h"
+# endif
+#endif
+
+/**
+ * \brief Initializes the IOPORT service, ready for use.
+ *
+ * This function must be called before using any other functions in the IOPORT
+ * service.
+ */
+static inline void ioport_init(void)
+{
+ arch_ioport_init();
+}
+
+/**
+ * \brief Enable an IOPORT pin, based on a pin created with \ref
+ * IOPORT_CREATE_PIN().
+ *
+ * \param pin IOPORT pin to enable
+ */
+static inline void ioport_enable_pin(ioport_pin_t pin)
+{
+ arch_ioport_enable_pin(pin);
+}
+
+/**
+ * \brief Enable multiple pins in a single IOPORT port.
+ *
+ * \param port IOPORT port to enable
+ * \param mask Mask of pins within the port to enable
+ */
+static inline void ioport_enable_port(ioport_port_t port,
+ ioport_port_mask_t mask)
+{
+ arch_ioport_enable_port(port, mask);
+}
+
+/**
+ * \brief Disable IOPORT pin, based on a pin created with \ref
+ * IOPORT_CREATE_PIN().
+ *
+ * \param pin IOPORT pin to disable
+ */
+static inline void ioport_disable_pin(ioport_pin_t pin)
+{
+ arch_ioport_disable_pin(pin);
+}
+
+/**
+ * \brief Disable multiple pins in a single IOPORT port.
+ *
+ * \param port IOPORT port to disable
+ * \param mask Pin mask of pins to disable
+ */
+static inline void ioport_disable_port(ioport_port_t port,
+ ioport_port_mask_t mask)
+{
+ arch_ioport_disable_port(port, mask);
+}
+
+/**
+ * \brief Set multiple pin modes in a single IOPORT port, such as pull-up,
+ * pull-down, etc. configuration.
+ *
+ * \param port IOPORT port to configure
+ * \param mask Pin mask of pins to configure
+ * \param mode Mode masks to configure for the specified pins (\ref
+ * ioport_modes)
+ */
+static inline void ioport_set_port_mode(ioport_port_t port,
+ ioport_port_mask_t mask, ioport_mode_t mode)
+{
+ arch_ioport_set_port_mode(port, mask, mode);
+}
+
+/**
+ * \brief Set pin mode for one single IOPORT pin.
+ *
+ * \param pin IOPORT pin to configure
+ * \param mode Mode masks to configure for the specified pin (\ref ioport_modes)
+ */
+static inline void ioport_set_pin_mode(ioport_pin_t pin, ioport_mode_t mode)
+{
+ arch_ioport_set_pin_mode(pin, mode);
+}
+
+/**
+ * \brief Reset multiple pin modes in a specified IOPORT port to defaults.
+ *
+ * \param port IOPORT port to configure
+ * \param mask Mask of pins whose mode configuration is to be reset
+ */
+static inline void ioport_reset_port_mode(ioport_port_t port,
+ ioport_port_mask_t mask)
+{
+ arch_ioport_set_port_mode(port, mask, 0);
+}
+
+/**
+ * \brief Reset pin mode configuration for a single IOPORT pin
+ *
+ * \param pin IOPORT pin to configure
+ */
+static inline void ioport_reset_pin_mode(ioport_pin_t pin)
+{
+ arch_ioport_set_pin_mode(pin, 0);
+}
+
+/**
+ * \brief Set I/O direction for a group of pins in a single IOPORT.
+ *
+ * \param port IOPORT port to configure
+ * \param mask Pin mask of pins to configure
+ * \param dir Direction to set for the specified pins (\ref ioport_direction)
+ */
+static inline void ioport_set_port_dir(ioport_port_t port,
+ ioport_port_mask_t mask, enum ioport_direction dir)
+{
+ arch_ioport_set_port_dir(port, mask, dir);
+}
+
+/**
+ * \brief Set direction for a single IOPORT pin.
+ *
+ * \param pin IOPORT pin to configure
+ * \param dir Direction to set for the specified pin (\ref ioport_direction)
+ */
+static inline void ioport_set_pin_dir(ioport_pin_t pin,
+ enum ioport_direction dir)
+{
+ arch_ioport_set_pin_dir(pin, dir);
+}
+
+/**
+ * \brief Set an IOPORT pin to a specified logical value.
+ *
+ * \param pin IOPORT pin to configure
+ * \param level Logical value of the pin
+ */
+static inline void ioport_set_pin_level(ioport_pin_t pin, bool level)
+{
+ arch_ioport_set_pin_level(pin, level);
+}
+
+/**
+ * \brief Set a group of IOPORT pins in a single port to a specified logical
+ * value.
+ *
+ * \param port IOPORT port to write to
+ * \param mask Pin mask of pins to modify
+ * \param level Level of the pins to be modified
+ */
+static inline void ioport_set_port_level(ioport_port_t port,
+ ioport_port_mask_t mask, ioport_port_mask_t level)
+{
+ arch_ioport_set_port_level(port, mask, level);
+}
+
+/**
+ * \brief Get current value of an IOPORT pin, which has been configured as an
+ * input.
+ *
+ * \param pin IOPORT pin to read
+ * \return Current logical value of the specified pin
+ */
+static inline bool ioport_get_pin_level(ioport_pin_t pin)
+{
+ return arch_ioport_get_pin_level(pin);
+}
+
+/**
+ * \brief Get current value of several IOPORT pins in a single port, which have
+ * been configured as an inputs.
+ *
+ * \param port IOPORT port to read
+ * \param mask Pin mask of pins to read
+ * \return Logical levels of the specified pins from the read port, returned as
+ * a mask.
+ */
+static inline ioport_port_mask_t ioport_get_port_level(ioport_pin_t port,
+ ioport_port_mask_t mask)
+{
+ return arch_ioport_get_port_level(port, mask);
+}
+
+/**
+ * \brief Toggle the value of an IOPORT pin, which has previously configured as
+ * an output.
+ *
+ * \param pin IOPORT pin to toggle
+ */
+static inline void ioport_toggle_pin_level(ioport_pin_t pin)
+{
+ arch_ioport_toggle_pin_level(pin);
+}
+
+/**
+ * \brief Toggle the values of several IOPORT pins located in a single port.
+ *
+ * \param port IOPORT port to modify
+ * \param mask Pin mask of pins to toggle
+ */
+static inline void ioport_toggle_port_level(ioport_port_t port,
+ ioport_port_mask_t mask)
+{
+ arch_ioport_toggle_port_level(port, mask);
+}
+
+/**
+ * \brief Set the pin sense mode of a single IOPORT pin.
+ *
+ * \param pin IOPORT pin to configure
+ * \param pin_sense Edge to sense for the pin (\ref ioport_sense)
+ */
+static inline void ioport_set_pin_sense_mode(ioport_pin_t pin,
+ enum ioport_sense pin_sense)
+{
+ arch_ioport_set_pin_sense_mode(pin, pin_sense);
+}
+
+/**
+ * \brief Set the pin sense mode of a multiple IOPORT pins on a single port.
+ *
+ * \param port IOPORT port to configure
+ * \param mask Bitmask if pins whose edge sense is to be configured
+ * \param pin_sense Edge to sense for the pins (\ref ioport_sense)
+ */
+static inline void ioport_set_port_sense_mode(ioport_port_t port,
+ ioport_port_mask_t mask,
+ enum ioport_sense pin_sense)
+{
+ arch_ioport_set_port_sense_mode(port, mask, pin_sense);
+}
+
+/**
+ * \brief Convert a pin ID into a its port ID.
+ *
+ * \param pin IOPORT pin ID to convert
+ * \retval Port ID for the given pin ID
+ */
+static inline ioport_port_t ioport_pin_to_port_id(ioport_pin_t pin)
+{
+ return arch_ioport_pin_to_port_id(pin);
+}
+
+/**
+ * \brief Convert a pin ID into a bitmask mask for the given pin on its port.
+ *
+ * \param pin IOPORT pin ID to convert
+ * \retval Bitmask with a bit set that corresponds to the given pin ID in its port
+ */
+static inline ioport_port_mask_t ioport_pin_to_mask(ioport_pin_t pin)
+{
+ return arch_ioport_pin_to_mask(pin);
+}
+
+/** @} */
+
+/**
+ * \page ioport_quickstart Quick start guide for the common IOPORT service
+ *
+ * This is the quick start guide for the \ref ioport_group, with
+ * step-by-step instructions on how to configure and use the service in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section ioport_quickstart_basic Basic use case
+ * In this use case we will configure one IO pin for button input and one for
+ * LED control. Then it will read the button state and output it on the LED.
+ *
+ * \section ioport_quickstart_basic_setup Setup steps
+ *
+ * \subsection ioport_quickstart_basic_setup_code Example code
+ * \code
+ #define MY_LED IOPORT_CREATE_PIN(PORTA, 5)
+ #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6)
+
+ ioport_init();
+
+ ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT);
+ ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT);
+ ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP);
+\endcode
+ *
+ * \subsection ioport_quickstart_basic_setup_flow Workflow
+ * -# It's useful to give the GPIOs symbolic names and this can be done with
+ * the \ref IOPORT_CREATE_PIN macro. We define one for a LED and one for a
+ * button.
+ * - \code
+ #define MY_LED IOPORT_CREATE_PIN(PORTA, 5)
+ #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6)
+\endcode
+ * - \note The usefulness of the \ref IOPORT_CREATE_PIN macro and port names
+ * differ between architectures:
+ * - MEGA, MEGA_RF and XMEGA: Use \ref IOPORT_CREATE_PIN macro with port definitions
+ * PORTA, PORTB ...
+ * - UC3: Most convenient to pick up the device header file pin definition
+ * and us it directly. E.g.: AVR32_PIN_PB06
+ * - SAM: Most convenient to pick up the device header file pin definition
+ * and us it directly. E.g.: PIO_PA5_IDX<br>
+ * \ref IOPORT_CREATE_PIN can also be used with port definitions
+ * PIOA, PIOB ...
+ * -# Initialize the ioport service. This typically enables the IO module if
+ * needed.
+ * - \code ioport_init(); \endcode
+ * -# Set the LED GPIO as output:
+ * - \code ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT); \endcode
+ * -# Set the button GPIO as input:
+ * - \code ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT); \endcode
+ * -# Enable pull-up for the button GPIO:
+ * - \code ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP); \endcode
+ *
+ * \section ioport_quickstart_basic_usage Usage steps
+ *
+ * \subsection ioport_quickstart_basic_usage_code Example code
+ * \code
+ bool value;
+
+ value = ioport_get_pin_level(MY_BUTTON);
+ ioport_set_pin_level(MY_LED, value);
+\endcode
+ *
+ * \subsection ioport_quickstart_basic_usage_flow Workflow
+ * -# Define a boolean variable for state storage:
+ * - \code bool value; \endcode
+ * -# Read out the button level into variable value:
+ * - \code value = ioport_get_pin_level(MY_BUTTON); \endcode
+ * -# Set the LED to read out value from the button:
+ * - \code ioport_set_pin_level(MY_LED, value); \endcode
+ *
+ * \section ioport_quickstart_advanced Advanced use cases
+ * - \subpage ioport_quickstart_use_case_1 : Port access
+ */
+
+/**
+ * \page ioport_quickstart_use_case_1 Advanced use case doing port access
+ *
+ * In this case we will read out the pins from one whole port and write the
+ * read value to another port.
+ *
+ * \section ioport_quickstart_use_case_1_setup Setup steps
+ *
+ * \subsection ioport_quickstart_use_case_1_setup_code Example code
+ * \code
+ #define IN_PORT IOPORT_PORTA
+ #define OUT_PORT IOPORT_PORTB
+ #define MASK 0x00000060
+
+ ioport_init();
+
+ ioport_set_port_dir(IN_PORT, MASK, IOPORT_DIR_INPUT);
+ ioport_set_port_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT);
+\endcode
+ *
+ * \subsection ioport_quickstart_basic_setup_flow Workflow
+ * -# It's useful to give the ports symbolic names:
+ * - \code
+ #define IN_PORT IOPORT_PORTA
+ #define OUT_PORT IOPORT_PORTB
+\endcode
+ * - \note The port names differ between architectures:
+ * - MEGA_RF, MEGA and XMEGA: There are predefined names for ports: IOPORT_PORTA,
+ * IOPORT_PORTB ...
+ * - UC3: Use the index value of the different IO blocks: 0, 1 ...
+ * - SAM: There are predefined names for ports: IOPORT_PIOA, IOPORT_PIOB
+ * ...
+ * -# Also useful to define a mask for the bits to work with:
+ * - \code #define MASK 0x00000060 \endcode
+ * -# Initialize the ioport service. This typically enables the IO module if
+ * needed.
+ * - \code ioport_init(); \endcode
+ * -# Set one of the ports as input:
+ * - \code ioport_set_pin_dir(IN_PORT, MASK, IOPORT_DIR_INPUT); \endcode
+ * -# Set the other port as output:
+ * - \code ioport_set_pin_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT); \endcode
+ *
+ * \section ioport_quickstart_basic_usage Usage steps
+ *
+ * \subsection ioport_quickstart_basic_usage_code Example code
+ * \code
+ ioport_port_mask_t value;
+
+ value = ioport_get_port_level(IN_PORT, MASK);
+ ioport_set_port_level(OUT_PORT, MASK, value);
+\endcode
+ *
+ * \subsection ioport_quickstart_basic_usage_flow Workflow
+ * -# Define a variable for port date storage:
+ * - \code ioport_port_mask_t value; \endcode
+ * -# Read out from one port:
+ * - \code value = ioport_get_port_level(IN_PORT, MASK); \endcode
+ * -# Put the read data out on the other port:
+ * - \code ioport_set_port_level(OUT_PORT, MASK, value); \endcode
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* IOPORT_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/ioport/sam/ioport_gpio.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,307 @@
+/**
+ * \file
+ *
+ * \brief SAM architecture specific IOPORT service implementation header file.
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef IOPORT_SAM_H
+#define IOPORT_SAM_H
+
+#include <sysclk.h>
+
+#define IOPORT_CREATE_PIN(port, pin) ((port) * 32 + (pin))
+
+// Aliases
+#define IOPORT_GPIOA 0
+#define IOPORT_GPIOB 1
+#define IOPORT_GPIOC 2
+#define IOPORT_GPIOD 3
+#define IOPORT_GPIOE 4
+#define IOPORT_GPIOF 5
+
+/**
+ * \weakgroup ioport_group
+ * \section ioport_modes IOPORT Modes
+ *
+ * For details on these please see the device datasheet.
+ *
+ * @{
+ */
+
+/** \name IOPORT Mode bit definitions */
+/** @{ */
+#define IOPORT_MODE_MUX_MASK (7 << 0) /*!< MUX bits mask */
+#define IOPORT_MODE_MUX_BIT0 (1 << 0) /*!< MUX BIT0 mask */
+#define IOPORT_MODE_MUX_BIT1 (1 << 1) /*!< MUX BIT1 mask */
+#define IOPORT_MODE_MUX_A (0 << 0) /*!< MUX function A */
+#define IOPORT_MODE_MUX_B (1 << 0) /*!< MUX function B */
+#define IOPORT_MODE_MUX_C (2 << 0) /*!< MUX function C */
+#define IOPORT_MODE_MUX_D (3 << 0) /*!< MUX function D */
+
+#define IOPORT_MODE_MUX_BIT2 (1 << 2) /*!< MUX BIT2 mask */
+#define IOPORT_MODE_MUX_E (4 << 0) /*!< MUX function E */
+#define IOPORT_MODE_MUX_F (5 << 0) /*!< MUX function F */
+#define IOPORT_MODE_MUX_G (6 << 0) /*!< MUX function G */
+#define IOPORT_MODE_MUX_H (7 << 0) /*!< MUX function H */
+
+#define IOPORT_MODE_PULLUP (1 << 3) /*!< Pull-up */
+#define IOPORT_MODE_PULLDOWN (1 << 4) /*!< Pull-down */
+#define IOPORT_MODE_GLITCH_FILTER (1 << 6) /*!< Glitch filter */
+#define IOPORT_MODE_DRIVE_STRENGTH (1 << 7) /*!< Extra drive strength */
+/** @} */
+
+/** @} */
+
+typedef uint32_t ioport_mode_t;
+typedef uint32_t ioport_pin_t;
+typedef uint32_t ioport_port_t;
+typedef uint32_t ioport_port_mask_t;
+
+__always_inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin)
+{
+ return pin >> 5;
+}
+
+__always_inline static volatile GpioPort *arch_ioport_port_to_base(
+ ioport_port_t port)
+{
+ return (volatile GpioPort *)(GPIO_ADDR
+ + port * sizeof(GpioPort));
+}
+
+__always_inline static volatile GpioPort *arch_ioport_pin_to_base(ioport_pin_t pin)
+{
+ return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin));
+}
+
+__always_inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin)
+{
+ return 1U << (pin & 0x1F);
+}
+
+__always_inline static void arch_ioport_init(void)
+{
+ sysclk_enable_peripheral_clock(GPIO);
+}
+
+__always_inline static void arch_ioport_enable_port(ioport_port_t port,
+ ioport_port_mask_t mask)
+{
+ arch_ioport_port_to_base(port)->GPIO_GPERS = mask;
+}
+
+__always_inline static void arch_ioport_disable_port(ioport_port_t port,
+ ioport_port_mask_t mask)
+{
+ arch_ioport_port_to_base(port)->GPIO_GPERC = mask;
+}
+
+__always_inline static void arch_ioport_enable_pin(ioport_pin_t pin)
+{
+ arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin),
+ arch_ioport_pin_to_mask(pin));
+}
+
+__always_inline static void arch_ioport_disable_pin(ioport_pin_t pin)
+{
+ arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin),
+ arch_ioport_pin_to_mask(pin));
+}
+
+__always_inline static void arch_ioport_set_port_mode(ioport_port_t port,
+ ioport_port_mask_t mask, ioport_mode_t mode)
+{
+ volatile GpioPort *base = arch_ioport_port_to_base(port);
+
+ if (mode & IOPORT_MODE_PULLUP) {
+ base->GPIO_PUERS = mask;
+ } else {
+ base->GPIO_PUERC = mask;
+ }
+
+#ifdef IOPORT_MODE_PULLDOWN
+ if (mode & IOPORT_MODE_PULLDOWN) {
+ base->GPIO_PDERS = mask;
+ } else {
+ base->GPIO_PDERC = mask;
+ }
+#endif
+
+ if (mode & IOPORT_MODE_GLITCH_FILTER) {
+ base->GPIO_GFERS = mask;
+ } else {
+ base->GPIO_GFERC = mask;
+ }
+
+#ifdef IOPORT_MODE_DRIVE_STRENGTH
+ if (mode & IOPORT_MODE_DRIVE_STRENGTH) {
+ base->GPIO_ODCR0S = mask;
+ } else {
+ base->GPIO_ODCR0C = mask;
+ }
+#endif
+
+ if (mode & IOPORT_MODE_MUX_BIT0) {
+ base->GPIO_PMR0S = mask;
+ } else {
+ base->GPIO_PMR0C = mask;
+ }
+
+ if (mode & IOPORT_MODE_MUX_BIT1) {
+ base->GPIO_PMR1S = mask;
+ } else {
+ base->GPIO_PMR1C = mask;
+ }
+
+#ifdef IOPORT_MODE_MUX_BIT2
+ if (mode & IOPORT_MODE_MUX_BIT2) {
+ base->GPIO_PMR2S = mask;
+ } else {
+ base->GPIO_PMR2C = mask;
+ }
+#endif
+}
+
+__always_inline static void arch_ioport_set_pin_mode(ioport_pin_t pin,
+ ioport_mode_t mode)
+{
+ arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin),
+ arch_ioport_pin_to_mask(pin), mode);
+}
+
+__always_inline static void arch_ioport_set_port_dir(ioport_port_t port,
+ ioport_port_mask_t mask, unsigned char group_direction)
+{
+ if (group_direction == IOPORT_DIR_OUTPUT) {
+ arch_ioport_port_to_base(port)->GPIO_ODERS = mask;
+ // Always disable the Schmitt trigger for output pins.
+ arch_ioport_port_to_base(port)->GPIO_STERC = mask;
+ } else if (group_direction == IOPORT_DIR_INPUT) {
+ arch_ioport_port_to_base(port)->GPIO_ODERC = mask;
+ // Always enable the Schmitt trigger for input pins.
+ arch_ioport_port_to_base(port)->GPIO_STERS = mask;
+ }
+}
+
+__always_inline static void arch_ioport_set_pin_dir(ioport_pin_t pin,
+ enum ioport_direction dir)
+{
+ if (dir == IOPORT_DIR_OUTPUT) {
+ arch_ioport_pin_to_base(pin)->GPIO_ODERS = arch_ioport_pin_to_mask(pin);
+ // Always disable the Schmitt trigger for output pins.
+ arch_ioport_pin_to_base(pin)->GPIO_STERC = arch_ioport_pin_to_mask(pin);
+ } else if (dir == IOPORT_DIR_INPUT) {
+ arch_ioport_pin_to_base(pin)->GPIO_ODERC = arch_ioport_pin_to_mask(pin);
+ // Always enable the Schmitt trigger for input pins.
+ arch_ioport_pin_to_base(pin)->GPIO_STERS = arch_ioport_pin_to_mask(pin);
+ }
+}
+
+__always_inline static void arch_ioport_set_pin_level(ioport_pin_t pin,
+ bool level)
+{
+ if (level) {
+ arch_ioport_pin_to_base(pin)->GPIO_OVRS = arch_ioport_pin_to_mask(pin);
+ } else {
+ arch_ioport_pin_to_base(pin)->GPIO_OVRC = arch_ioport_pin_to_mask(pin);
+ }
+}
+
+__always_inline static void arch_ioport_set_port_level(ioport_port_t port,
+ ioport_port_mask_t mask, ioport_port_mask_t level)
+{
+ volatile GpioPort *base = arch_ioport_port_to_base(port);
+ if (level) {
+ base->GPIO_OVRS = mask;
+ } else {
+ base->GPIO_OVRC = mask;
+ }
+}
+
+__always_inline static bool arch_ioport_get_pin_level(ioport_pin_t pin)
+{
+ return arch_ioport_pin_to_base(pin)->GPIO_PVR & arch_ioport_pin_to_mask(pin);
+}
+
+__always_inline static ioport_port_mask_t arch_ioport_get_port_level(
+ ioport_port_t port, ioport_port_mask_t mask)
+{
+ return arch_ioport_port_to_base(port)->GPIO_PVR & mask;
+}
+
+__always_inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin)
+{
+ arch_ioport_pin_to_base(pin)->GPIO_OVRT = arch_ioport_pin_to_mask(pin);
+}
+
+__always_inline static void arch_ioport_toggle_port_level(ioport_port_t port,
+ ioport_port_mask_t mask)
+{
+ arch_ioport_port_to_base(port)->GPIO_OVRT = mask;
+}
+
+__always_inline static void arch_ioport_set_port_sense_mode(ioport_port_t port,
+ ioport_port_mask_t mask, enum ioport_sense pin_sense)
+{
+ volatile GpioPort *base = arch_ioport_port_to_base(port);
+
+ if (pin_sense & 0x01) {
+ base->GPIO_IMR0S = mask;
+ } else {
+ base->GPIO_IMR0C = mask;
+ }
+
+ if (pin_sense & 0x02) {
+ base->GPIO_IMR1S = mask;
+ } else {
+ base->GPIO_IMR1C = mask;
+ }
+}
+
+__always_inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin,
+ enum ioport_sense pin_sense)
+{
+ arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin),
+ arch_ioport_pin_to_mask(pin), pin_sense);
+}
+
+#endif /* IOPORT_SAM_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/ioport/sam/ioport_pio.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,380 @@
+/**
+ * \file
+ *
+ * \brief SAM architecture specific IOPORT service implementation header file.
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef IOPORT_SAM_H
+#define IOPORT_SAM_H
+
+#include <sysclk.h>
+
+#define IOPORT_CREATE_PIN(port, pin) ((IOPORT_ ## port) * 32 + (pin))
+#define IOPORT_BASE_ADDRESS (uintptr_t)PIOA
+#define IOPORT_PIO_OFFSET ((uintptr_t)PIOB - (uintptr_t)PIOA)
+
+#define IOPORT_PIOA 0
+#define IOPORT_PIOB 1
+#define IOPORT_PIOC 2
+#define IOPORT_PIOD 3
+#define IOPORT_PIOE 4
+#define IOPORT_PIOF 5
+
+/**
+ * \weakgroup ioport_group
+ * \section ioport_modes IOPORT Modes
+ *
+ * For details on these please see the SAM Manual.
+ *
+ * @{
+ */
+
+/** \name IOPORT Mode bit definitions */
+/** @{ */
+#define IOPORT_MODE_MUX_MASK (0x7 << 0) /*!< MUX bits mask */
+#define IOPORT_MODE_MUX_BIT0 ( 1 << 0) /*!< MUX BIT0 mask */
+
+#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70
+#define IOPORT_MODE_MUX_BIT1 ( 1 << 1) /*!< MUX BIT1 mask */
+#endif
+
+#define IOPORT_MODE_MUX_A ( 0 << 0) /*!< MUX function A */
+#define IOPORT_MODE_MUX_B ( 1 << 0) /*!< MUX function B */
+
+#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70
+#define IOPORT_MODE_MUX_C ( 2 << 0) /*!< MUX function C */
+#define IOPORT_MODE_MUX_D ( 3 << 0) /*!< MUX function D */
+#endif
+
+#define IOPORT_MODE_PULLUP ( 1 << 3) /*!< Pull-up */
+
+#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70
+#define IOPORT_MODE_PULLDOWN ( 1 << 4) /*!< Pull-down */
+#endif
+
+#define IOPORT_MODE_OPEN_DRAIN ( 1 << 5) /*!< Open drain */
+
+#define IOPORT_MODE_GLITCH_FILTER ( 1 << 6) /*!< Glitch filter */
+#define IOPORT_MODE_DEBOUNCE ( 1 << 7) /*!< Input debounce */
+/** @} */
+
+/** @} */
+
+typedef uint32_t ioport_mode_t;
+typedef uint32_t ioport_pin_t;
+typedef uint32_t ioport_port_t;
+typedef uint32_t ioport_port_mask_t;
+
+__always_inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin)
+{
+ return pin >> 5;
+}
+
+__always_inline static Pio *arch_ioport_port_to_base(ioport_port_t port)
+{
+#if (SAM4C || SAM4CM || SAM4CP)
+ if (port == IOPORT_PIOC) {
+ return (Pio *)(uintptr_t)PIOC;
+# ifdef ID_PIOD
+ } else if (port == IOPORT_PIOD) {
+ return (Pio *)(uintptr_t)PIOD;
+# endif
+ } else {
+ return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS +
+ (IOPORT_PIO_OFFSET * port));
+ }
+#else
+ return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS +
+ (IOPORT_PIO_OFFSET * port));
+#endif
+}
+
+__always_inline static Pio *arch_ioport_pin_to_base(ioport_pin_t pin)
+{
+ return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin));
+}
+
+__always_inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin)
+{
+ return 1U << (pin & 0x1F);
+}
+
+__always_inline static void arch_ioport_init(void)
+{
+#ifdef ID_PIOA
+ sysclk_enable_peripheral_clock(ID_PIOA);
+#endif
+#ifdef ID_PIOB
+ sysclk_enable_peripheral_clock(ID_PIOB);
+#endif
+#ifdef ID_PIOC
+ sysclk_enable_peripheral_clock(ID_PIOC);
+#endif
+#ifdef ID_PIOD
+ sysclk_enable_peripheral_clock(ID_PIOD);
+#endif
+#ifdef ID_PIOE
+ sysclk_enable_peripheral_clock(ID_PIOE);
+#endif
+#ifdef ID_PIOF
+ sysclk_enable_peripheral_clock(ID_PIOF);
+#endif
+}
+
+__always_inline static void arch_ioport_enable_port(ioport_port_t port,
+ ioport_port_mask_t mask)
+{
+ arch_ioport_port_to_base(port)->PIO_PER = mask;
+}
+
+__always_inline static void arch_ioport_disable_port(ioport_port_t port,
+ ioport_port_mask_t mask)
+{
+ arch_ioport_port_to_base(port)->PIO_PDR = mask;
+}
+
+__always_inline static void arch_ioport_enable_pin(ioport_pin_t pin)
+{
+ arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin),
+ arch_ioport_pin_to_mask(pin));
+}
+
+__always_inline static void arch_ioport_disable_pin(ioport_pin_t pin)
+{
+ arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin),
+ arch_ioport_pin_to_mask(pin));
+}
+
+__always_inline static void arch_ioport_set_port_mode(ioport_port_t port,
+ ioport_port_mask_t mask, ioport_mode_t mode)
+{
+ Pio *base = arch_ioport_port_to_base(port);
+
+ if (mode & IOPORT_MODE_PULLUP) {
+ base->PIO_PUER = mask;
+ } else {
+ base->PIO_PUDR = mask;
+ }
+
+#if defined(IOPORT_MODE_PULLDOWN)
+ if (mode & IOPORT_MODE_PULLDOWN) {
+ base->PIO_PPDER = mask;
+ } else {
+ base->PIO_PPDDR = mask;
+ }
+#endif
+
+ if (mode & IOPORT_MODE_OPEN_DRAIN) {
+ base->PIO_MDER = mask;
+ } else {
+ base->PIO_MDDR = mask;
+ }
+
+ if (mode & (IOPORT_MODE_GLITCH_FILTER | IOPORT_MODE_DEBOUNCE)) {
+ base->PIO_IFER = mask;
+ } else {
+ base->PIO_IFDR = mask;
+ }
+
+ if (mode & IOPORT_MODE_DEBOUNCE) {
+#if SAM3U || SAM3XA
+ base->PIO_DIFSR = mask;
+#else
+ base->PIO_IFSCER = mask;
+#endif
+ } else {
+#if SAM3U || SAM3XA
+ base->PIO_SCIFSR = mask;
+#else
+ base->PIO_IFSCDR = mask;
+#endif
+ }
+
+#if !defined(IOPORT_MODE_MUX_BIT1)
+ if (mode & IOPORT_MODE_MUX_BIT0) {
+ base->PIO_ABSR |= mask;
+ } else {
+ base->PIO_ABSR &= ~mask;
+ }
+#else
+ if (mode & IOPORT_MODE_MUX_BIT0) {
+ base->PIO_ABCDSR[0] |= mask;
+ } else {
+ base->PIO_ABCDSR[0] &= ~mask;
+ }
+
+ if (mode & IOPORT_MODE_MUX_BIT1) {
+ base->PIO_ABCDSR[1] |= mask;
+ } else {
+ base->PIO_ABCDSR[1] &= ~mask;
+ }
+#endif
+}
+
+__always_inline static void arch_ioport_set_pin_mode(ioport_pin_t pin,
+ ioport_mode_t mode)
+{
+ arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin),
+ arch_ioport_pin_to_mask(pin), mode);
+}
+
+__always_inline static void arch_ioport_set_port_dir(ioport_port_t port,
+ ioport_port_mask_t mask, enum ioport_direction group_direction)
+{
+ Pio *base = arch_ioport_port_to_base(port);
+
+ if (group_direction == IOPORT_DIR_OUTPUT) {
+ base->PIO_OER = mask;
+ } else if (group_direction == IOPORT_DIR_INPUT) {
+ base->PIO_ODR = mask;
+ }
+
+ base->PIO_OWER = mask;
+}
+
+__always_inline static void arch_ioport_set_pin_dir(ioport_pin_t pin,
+ enum ioport_direction dir)
+{
+ Pio *base = arch_ioport_pin_to_base(pin);
+
+ if (dir == IOPORT_DIR_OUTPUT) {
+ base->PIO_OER = arch_ioport_pin_to_mask(pin);
+ } else if (dir == IOPORT_DIR_INPUT) {
+ base->PIO_ODR = arch_ioport_pin_to_mask(pin);
+ }
+
+ base->PIO_OWER = arch_ioport_pin_to_mask(pin);
+}
+
+__always_inline static void arch_ioport_set_pin_level(ioport_pin_t pin,
+ bool level)
+{
+ Pio *base = arch_ioport_pin_to_base(pin);
+
+ if (level) {
+ base->PIO_SODR = arch_ioport_pin_to_mask(pin);
+ } else {
+ base->PIO_CODR = arch_ioport_pin_to_mask(pin);
+ }
+}
+
+__always_inline static void arch_ioport_set_port_level(ioport_port_t port,
+ ioport_port_mask_t mask, ioport_port_mask_t level)
+{
+ Pio *base = arch_ioport_port_to_base(port);
+
+ base->PIO_SODR = mask & level;
+ base->PIO_CODR = mask & ~level;
+}
+
+__always_inline static bool arch_ioport_get_pin_level(ioport_pin_t pin)
+{
+ return arch_ioport_pin_to_base(pin)->PIO_PDSR & arch_ioport_pin_to_mask(pin);
+}
+
+__always_inline static ioport_port_mask_t arch_ioport_get_port_level(
+ ioport_port_t port, ioport_port_mask_t mask)
+{
+ return arch_ioport_port_to_base(port)->PIO_PDSR & mask;
+}
+
+__always_inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin)
+{
+ Pio *port = arch_ioport_pin_to_base(pin);
+ ioport_port_mask_t mask = arch_ioport_pin_to_mask(pin);
+
+ if (port->PIO_PDSR & arch_ioport_pin_to_mask(pin)) {
+ port->PIO_CODR = mask;
+ } else {
+ port->PIO_SODR = mask;
+ }
+}
+
+__always_inline static void arch_ioport_toggle_port_level(ioport_port_t port,
+ ioport_port_mask_t mask)
+{
+ arch_ioport_port_to_base(port)->PIO_ODSR ^= mask;
+}
+
+__always_inline static void arch_ioport_set_port_sense_mode(ioport_port_t port,
+ ioport_port_mask_t mask, enum ioport_sense pin_sense)
+{
+ Pio *base = arch_ioport_port_to_base(port);
+ /* AIMMR ELSR FRLHSR
+ * 0 X X IOPORT_SENSE_BOTHEDGES (Default)
+ * 1 0 0 IOPORT_SENSE_FALLING
+ * 1 0 1 IOPORT_SENSE_RISING
+ * 1 1 0 IOPORT_SENSE_LEVEL_LOW
+ * 1 1 1 IOPORT_SENSE_LEVEL_HIGH
+ */
+ switch(pin_sense) {
+ case IOPORT_SENSE_LEVEL_LOW:
+ base->PIO_LSR = mask;
+ base->PIO_FELLSR = mask;
+ break;
+ case IOPORT_SENSE_LEVEL_HIGH:
+ base->PIO_LSR = mask;
+ base->PIO_REHLSR = mask;
+ break;
+ case IOPORT_SENSE_FALLING:
+ base->PIO_ESR = mask;
+ base->PIO_FELLSR = mask;
+ break;
+ case IOPORT_SENSE_RISING:
+ base->PIO_ESR = mask;
+ base->PIO_REHLSR = mask;
+ break;
+ default:
+ base->PIO_AIMDR = mask;
+ return;
+ }
+ base->PIO_AIMER = mask;
+}
+
+__always_inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin,
+ enum ioport_sense pin_sense)
+{
+ arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin),
+ arch_ioport_pin_to_mask(pin), pin_sense);
+}
+
+#endif /* IOPORT_SAM_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/serial/sam_uart/uart_serial.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,682 @@
+/**
+ * \file
+ *
+ * \brief Uart Serial for SAM.
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef _UART_SERIAL_H_
+#define _UART_SERIAL_H_
+
+#include "compiler.h"
+#include "sysclk.h"
+#if (SAMG55)
+#include "flexcom.h"
+#endif
+#if ((!SAM4L) && (!SAMG55))
+#include "uart.h"
+#endif
+#include "usart.h"
+
+/**
+ * \name Serial Management Configuration
+ */
+//! @{
+#include "conf_uart_serial.h"
+
+//! @}
+
+/** Input parameters when initializing RS232 and similar modes. */
+typedef struct uart_rs232_options {
+ /** Set baud rate of the USART (unused in slave modes). */
+ uint32_t baudrate;
+
+ /** Number of bits to transmit as a character (5-bit to 9-bit). */
+ uint32_t charlength;
+
+ /**
+ * Parity type: USART_PMODE_DISABLED_gc, USART_PMODE_EVEN_gc,
+ * USART_PMODE_ODD_gc.
+ */
+ uint32_t paritytype;
+
+ /** 1, 1.5 or 2 stop bits. */
+ uint32_t stopbits;
+
+} usart_rs232_options_t;
+
+typedef usart_rs232_options_t usart_serial_options_t;
+
+typedef Usart *usart_if;
+
+/**
+ * \brief Initializes the Usart in master mode.
+ *
+ * \param p_usart Base address of the USART instance.
+ * \param opt Options needed to set up RS232 communication (see
+ * \ref usart_options_t).
+ */
+static inline void usart_serial_init(usart_if p_usart,
+ usart_serial_options_t *opt)
+{
+#if ((!SAM4L) && (!SAMG55))
+ sam_uart_opt_t uart_settings;
+ uart_settings.ul_mck = sysclk_get_peripheral_hz();
+ uart_settings.ul_baudrate = opt->baudrate;
+ uart_settings.ul_mode = opt->paritytype;
+#endif
+
+ sam_usart_opt_t usart_settings;
+ usart_settings.baudrate = opt->baudrate;
+ usart_settings.char_length = opt->charlength;
+ usart_settings.parity_type = opt->paritytype;
+ usart_settings.stop_bits= opt->stopbits;
+ usart_settings.channel_mode= US_MR_CHMODE_NORMAL;
+
+#ifdef UART
+ if (UART == (Uart*)p_usart) {
+ sysclk_enable_peripheral_clock(ID_UART);
+ /* Configure UART */
+ uart_init((Uart*)p_usart, &uart_settings);
+ }
+#else
+# ifdef UART0
+ if (UART0 == (Uart*)p_usart) {
+ sysclk_enable_peripheral_clock(ID_UART0);
+ /* Configure UART */
+ uart_init((Uart*)p_usart, &uart_settings);
+ }
+# endif
+# ifdef UART1
+ if (UART1 == (Uart*)p_usart) {
+ sysclk_enable_peripheral_clock(ID_UART1);
+ /* Configure UART */
+ uart_init((Uart*)p_usart, &uart_settings);
+ }
+# endif
+# ifdef UART2
+ if (UART2 == (Uart*)p_usart) {
+ sysclk_enable_peripheral_clock(ID_UART2);
+ /* Configure UART */
+ uart_init((Uart*)p_usart, &uart_settings);
+ }
+# endif
+# ifdef UART3
+ if (UART3 == (Uart*)p_usart) {
+ sysclk_enable_peripheral_clock(ID_UART3);
+ /* Configure UART */
+ uart_init((Uart*)p_usart, &uart_settings);
+ }
+# endif
+#endif /* ifdef UART */
+
+
+#ifdef USART
+ if (USART == p_usart) {
+#if (!SAM4L)
+ sysclk_enable_peripheral_clock(ID_USART);
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+ sysclk_enable_peripheral_clock(p_usart);
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+ /* Enable the receiver and transmitter. */
+ usart_enable_tx(p_usart);
+ usart_enable_rx(p_usart);
+ }
+#else
+# ifdef USART0
+ if (USART0 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+ flexcom_enable(FLEXCOM0);
+ flexcom_set_opmode(FLEXCOM0, FLEXCOM_USART);
+#else
+ sysclk_enable_peripheral_clock(ID_USART0);
+#endif
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+ sysclk_enable_peripheral_clock(p_usart);
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+ /* Enable the receiver and transmitter. */
+ usart_enable_tx(p_usart);
+ usart_enable_rx(p_usart);
+ }
+# endif
+# ifdef USART1
+ if (USART1 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+ flexcom_enable(FLEXCOM1);
+ flexcom_set_opmode(FLEXCOM1, FLEXCOM_USART);
+#else
+ sysclk_enable_peripheral_clock(ID_USART1);
+#endif
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+ sysclk_enable_peripheral_clock(p_usart);
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+ /* Enable the receiver and transmitter. */
+ usart_enable_tx(p_usart);
+ usart_enable_rx(p_usart);
+ }
+# endif
+# ifdef USART2
+ if (USART2 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+ flexcom_enable(FLEXCOM2);
+ flexcom_set_opmode(FLEXCOM2, FLEXCOM_USART);
+#else
+ sysclk_enable_peripheral_clock(ID_USART2);
+#endif
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+ sysclk_enable_peripheral_clock(p_usart);
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+ /* Enable the receiver and transmitter. */
+ usart_enable_tx(p_usart);
+ usart_enable_rx(p_usart);
+ }
+# endif
+# ifdef USART3
+ if (USART3 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+ flexcom_enable(FLEXCOM3);
+ flexcom_set_opmode(FLEXCOM3, FLEXCOM_USART);
+#else
+ sysclk_enable_peripheral_clock(ID_USART3);
+#endif
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+ sysclk_enable_peripheral_clock(p_usart);
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+ /* Enable the receiver and transmitter. */
+ usart_enable_tx(p_usart);
+ usart_enable_rx(p_usart);
+ }
+# endif
+# ifdef USART4
+ if (USART4 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+ flexcom_enable(FLEXCOM4);
+ flexcom_set_opmode(FLEXCOM4, FLEXCOM_USART);
+#else
+ sysclk_enable_peripheral_clock(ID_USART4);
+#endif
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+ sysclk_enable_peripheral_clock(p_usart);
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+ /* Enable the receiver and transmitter. */
+ usart_enable_tx(p_usart);
+ usart_enable_rx(p_usart);
+ }
+# endif
+# ifdef USART5
+ if (USART5 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+ flexcom_enable(FLEXCOM5);
+ flexcom_set_opmode(FLEXCOM5, FLEXCOM_USART);
+#else
+ sysclk_enable_peripheral_clock(ID_USART5);
+#endif
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+ sysclk_enable_peripheral_clock(p_usart);
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+ /* Enable the receiver and transmitter. */
+ usart_enable_tx(p_usart);
+ usart_enable_rx(p_usart);
+ }
+# endif
+# ifdef USART6
+ if (USART6 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+ flexcom_enable(FLEXCOM6);
+ flexcom_set_opmode(FLEXCOM6, FLEXCOM_USART);
+#else
+ sysclk_enable_peripheral_clock(ID_USART6);
+#endif
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+ sysclk_enable_peripheral_clock(p_usart);
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+ /* Enable the receiver and transmitter. */
+ usart_enable_tx(p_usart);
+ usart_enable_rx(p_usart);
+ }
+# endif
+# ifdef USART7
+ if (USART7 == p_usart) {
+#if (!SAM4L)
+#if (SAMG55)
+ flexcom_enable(FLEXCOM7);
+ flexcom_set_opmode(FLEXCOM7, FLEXCOM_USART);
+#else
+ sysclk_enable_peripheral_clock(ID_USART7);
+#endif
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_hz());
+#endif
+#if (SAM4L)
+ sysclk_enable_peripheral_clock(p_usart);
+ /* Configure USART */
+ usart_init_rs232(p_usart, &usart_settings,
+ sysclk_get_peripheral_bus_hz(p_usart));
+#endif
+ /* Enable the receiver and transmitter. */
+ usart_enable_tx(p_usart);
+ usart_enable_rx(p_usart);
+ }
+# endif
+
+#endif /* ifdef USART */
+
+}
+
+/**
+ * \brief Sends a character with the USART.
+ *
+ * \param p_usart Base address of the USART instance.
+ * \param c Character to write.
+ *
+ * \return Status.
+ * \retval 1 The character was written.
+ * \retval 0 The function timed out before the USART transmitter became
+ * ready to send.
+ */
+static inline int usart_serial_putchar(usart_if p_usart, const uint8_t c)
+{
+#ifdef UART
+ if (UART == (Uart*)p_usart) {
+ while (uart_write((Uart*)p_usart, c)!=0);
+ return 1;
+ }
+#else
+# ifdef UART0
+ if (UART0 == (Uart*)p_usart) {
+ while (uart_write((Uart*)p_usart, c)!=0);
+ return 1;
+ }
+# endif
+# ifdef UART1
+ if (UART1 == (Uart*)p_usart) {
+ while (uart_write((Uart*)p_usart, c)!=0);
+ return 1;
+ }
+# endif
+# ifdef UART2
+ if (UART2 == (Uart*)p_usart) {
+ while (uart_write((Uart*)p_usart, c)!=0);
+ return 1;
+ }
+# endif
+# ifdef UART3
+ if (UART3 == (Uart*)p_usart) {
+ while (uart_write((Uart*)p_usart, c)!=0);
+ return 1;
+ }
+# endif
+#endif /* ifdef UART */
+
+
+#ifdef USART
+ if (USART == p_usart) {
+ while (usart_write(p_usart, c)!=0);
+ return 1;
+ }
+#else
+# ifdef USART0
+ if (USART0 == p_usart) {
+ while (usart_write(p_usart, c)!=0);
+ return 1;
+ }
+# endif
+# ifdef USART1
+ if (USART1 == p_usart) {
+ while (usart_write(p_usart, c)!=0);
+ return 1;
+ }
+# endif
+# ifdef USART2
+ if (USART2 == p_usart) {
+ while (usart_write(p_usart, c)!=0);
+ return 1;
+ }
+# endif
+# ifdef USART3
+ if (USART3 == p_usart) {
+ while (usart_write(p_usart, c)!=0);
+ return 1;
+ }
+# endif
+# ifdef USART4
+ if (USART4 == p_usart) {
+ while (usart_write(p_usart, c)!=0);
+ return 1;
+ }
+# endif
+# ifdef USART5
+ if (USART5 == p_usart) {
+ while (usart_write(p_usart, c)!=0);
+ return 1;
+ }
+# endif
+# ifdef USART6
+ if (USART6 == p_usart) {
+ while (usart_write(p_usart, c)!=0);
+ return 1;
+ }
+# endif
+# ifdef USART7
+ if (USART7 == p_usart) {
+ while (usart_write(p_usart, c)!=0);
+ return 1;
+ }
+# endif
+#endif /* ifdef USART */
+
+ return 0;
+}
+/**
+ * \brief Waits until a character is received, and returns it.
+ *
+ * \param p_usart Base address of the USART instance.
+ * \param data Data to read
+ *
+ */
+static inline void usart_serial_getchar(usart_if p_usart, uint8_t *data)
+{
+ uint32_t val = 0;
+
+ /* Avoid Cppcheck Warning */
+ UNUSED(val);
+
+#ifdef UART
+ if (UART == (Uart*)p_usart) {
+ while (uart_read((Uart*)p_usart, data));
+ }
+#else
+# ifdef UART0
+ if (UART0 == (Uart*)p_usart) {
+ while (uart_read((Uart*)p_usart, data));
+ }
+# endif
+# ifdef UART1
+ if (UART1 == (Uart*)p_usart) {
+ while (uart_read((Uart*)p_usart, data));
+ }
+# endif
+# ifdef UART2
+ if (UART2 == (Uart*)p_usart) {
+ while (uart_read((Uart*)p_usart, data));
+ }
+# endif
+# ifdef UART3
+ if (UART3 == (Uart*)p_usart) {
+ while (uart_read((Uart*)p_usart, data));
+ }
+# endif
+#endif /* ifdef UART */
+
+
+#ifdef USART
+ if (USART == p_usart) {
+ while (usart_read(p_usart, &val));
+ *data = (uint8_t)(val & 0xFF);
+ }
+#else
+# ifdef USART0
+ if (USART0 == p_usart) {
+ while (usart_read(p_usart, &val));
+ *data = (uint8_t)(val & 0xFF);
+ }
+# endif
+# ifdef USART1
+ if (USART1 == p_usart) {
+ while (usart_read(p_usart, &val));
+ *data = (uint8_t)(val & 0xFF);
+ }
+# endif
+# ifdef USART2
+ if (USART2 == p_usart) {
+ while (usart_read(p_usart, &val));
+ *data = (uint8_t)(val & 0xFF);
+ }
+# endif
+# ifdef USART3
+ if (USART3 == p_usart) {
+ while (usart_read(p_usart, &val));
+ *data = (uint8_t)(val & 0xFF);
+ }
+# endif
+# ifdef USART4
+ if (USART4 == p_usart) {
+ while (usart_read(p_usart, &val));
+ *data = (uint8_t)(val & 0xFF);
+ }
+# endif
+# ifdef USART5
+ if (USART5 == p_usart) {
+ while (usart_read(p_usart, &val));
+ *data = (uint8_t)(val & 0xFF);
+ }
+# endif
+# ifdef USART6
+ if (USART6 == p_usart) {
+ while (usart_read(p_usart, &val));
+ *data = (uint8_t)(val & 0xFF);
+ }
+# endif
+# ifdef USART7
+ if (USART7 == p_usart) {
+ while (usart_read(p_usart, &val));
+ *data = (uint8_t)(val & 0xFF);
+ }
+# endif
+#endif /* ifdef USART */
+
+}
+
+/**
+ * \brief Check if Received data is ready.
+ *
+ * \param p_usart Base address of the USART instance.
+ *
+ * \retval 1 One data has been received.
+ * \retval 0 No data has been received.
+ */
+static inline uint32_t usart_serial_is_rx_ready(usart_if p_usart)
+{
+#ifdef UART
+ if (UART == (Uart*)p_usart) {
+ return uart_is_rx_ready((Uart*)p_usart);
+ }
+#else
+# ifdef UART0
+ if (UART0 == (Uart*)p_usart) {
+ return uart_is_rx_ready((Uart*)p_usart);
+ }
+# endif
+# ifdef UART1
+ if (UART1 == (Uart*)p_usart) {
+ return uart_is_rx_ready((Uart*)p_usart);
+ }
+# endif
+# ifdef UART2
+ if (UART2 == (Uart*)p_usart) {
+ return uart_is_rx_ready((Uart*)p_usart);
+ }
+# endif
+# ifdef UART3
+ if (UART3 == (Uart*)p_usart) {
+ return uart_is_rx_ready((Uart*)p_usart);
+ }
+# endif
+#endif /* ifdef UART */
+
+
+#ifdef USART
+ if (USART == p_usart) {
+ return usart_is_rx_ready(p_usart);
+ }
+#else
+# ifdef USART0
+ if (USART0 == p_usart) {
+ return usart_is_rx_ready(p_usart);
+ }
+# endif
+# ifdef USART1
+ if (USART1 == p_usart) {
+ return usart_is_rx_ready(p_usart);
+ }
+# endif
+# ifdef USART2
+ if (USART2 == p_usart) {
+ return usart_is_rx_ready(p_usart);
+ }
+# endif
+# ifdef USART3
+ if (USART3 == p_usart) {
+ return usart_is_rx_ready(p_usart);
+ }
+# endif
+# ifdef USART4
+ if (USART4 == p_usart) {
+ return usart_is_rx_ready(p_usart);
+ }
+# endif
+# ifdef USART5
+ if (USART5 == p_usart) {
+ return usart_is_rx_ready(p_usart);
+ }
+# endif
+# ifdef USART6
+ if (USART6 == p_usart) {
+ return usart_is_rx_ready(p_usart);
+ }
+# endif
+# ifdef USART7
+ if (USART7 == p_usart) {
+ return usart_is_rx_ready(p_usart);
+ }
+# endif
+#endif /* ifdef USART */
+
+ return 0;
+}
+
+/**
+ * \brief Send a sequence of bytes to a USART device
+ *
+ * \param usart Base address of the USART instance.
+ * \param data data buffer to write
+ * \param len Length of data
+ *
+ */
+status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data,
+ size_t len);
+
+/**
+ * \brief Receive a sequence of bytes to a USART device
+ *
+ * \param usart Base address of the USART instance.
+ * \param data data buffer to write
+ * \param len Length of data
+ *
+ */
+status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data,
+ size_t len);
+
+#endif /* _UART_SERIAL_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/serial/serial_platform.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,279 @@
+/**
+ * \file
+ *
+ * \brief Serial Mode management
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SERIAL_PLATFORM_H_INCLUDED
+#define SERIAL_PLATFORM_H_INCLUDED
+
+#include <parts.h>
+#include "status_codes.h"
+
+/**
+ * \typedef usart_if
+ *
+ * This type can be used independently to refer to USART module for the
+ * architecture used. It refers to the correct type definition for the
+ * architecture, ie. USART_t* for XMEGA or avr32_usart_t* for UC3.
+ */
+
+#if XMEGA
+# include "xmega_usart/usart_serial.h"
+#elif MEGA_RF
+# include "megarf_usart/usart_serial.h"
+#elif UC3
+# include "uc3_usart/usart_serial.h"
+#elif (SAMB)
+#include "samb_uart/uart_serial.h"
+#elif (SAM0)
+#include "sam0_usart/usart_serial.h"
+#elif SAM
+# include "sam_uart/uart_serial.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ *
+ * \defgroup serial_group Serial Interface (Serial)
+ *
+ * See \ref serial_quickstart.
+ *
+ * This is the common API for serial interface. Additional features are available
+ * in the documentation of the specific modules.
+ *
+ * \section serial_group_platform Platform Dependencies
+ *
+ * The serial API is partially chip- or platform-specific. While all
+ * platforms provide mostly the same functionality, there are some
+ * variations around how different bus types and clock tree structures
+ * are handled.
+ *
+ * The following functions are available on all platforms, but there may
+ * be variations in the function signature (i.e. parameters) and
+ * behaviour. These functions are typically called by platform-specific
+ * parts of drivers, and applications that aren't intended to be
+ * portable:
+ * - usart_serial_init()
+ * - usart_serial_putchar()
+ * - usart_serial_getchar()
+ * - usart_serial_write_packet()
+ * - usart_serial_read_packet()
+ *
+ *
+ * @{
+ */
+
+//! @}
+
+/**
+ * \page serial_quickstart Quick start guide for Serial Interface service
+ *
+ * This is the quick start guide for the \ref serial_group "Serial Interface module", with
+ * step-by-step instructions on how to configure and use the serial in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section serial_use_cases Serial use cases
+ * - \ref serial_basic_use_case
+ * - \subpage serial_use_case_1
+ *
+ * \section serial_basic_use_case Basic use case - transmit a character
+ * In this use case, the serial module is configured for:
+ * - Using USARTD0
+ * - Baudrate: 9600
+ * - Character length: 8 bit
+ * - Parity mode: Disabled
+ * - Stop bit: None
+ * - RS232 mode
+ *
+ * The use case waits for a received character on the configured USART and
+ * echoes the character back to the same USART.
+ *
+ * \section serial_basic_use_case_setup Setup steps
+ *
+ * \subsection serial_basic_use_case_setup_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (sysclk)"
+ *
+ * \subsection serial_basic_use_case_setup_code Example code
+ * The following configuration must be added to the project (typically to a
+ * conf_uart_serial.h file, but it can also be added to your main application file.)
+ *
+ * \note The following takes SAM3X configuration for example, other devices have similar
+ * configuration, but their parameters may be different, refer to corresponding header files.
+ *
+ * \code
+ #define USART_SERIAL &USARTD0
+ #define USART_SERIAL_BAUDRATE 9600
+ #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT
+ #define USART_SERIAL_PARITY US_MR_PAR_NO
+ #define USART_SERIAL_STOP_BIT false
+\endcode
+ *
+ * A variable for the received byte must be added:
+ * \code uint8_t received_byte; \endcode
+ *
+ * Add to application initialization:
+ * \code
+ sysclk_init();
+
+ static usart_serial_options_t usart_options = {
+ .baudrate = USART_SERIAL_BAUDRATE,
+ .charlength = USART_SERIAL_CHAR_LENGTH,
+ .paritytype = USART_SERIAL_PARITY,
+ .stopbits = USART_SERIAL_STOP_BIT
+ };
+
+ usart_serial_init(USART_SERIAL, &usart_options);
+\endcode
+ *
+ * \subsection serial_basic_use_case_setup_flow Workflow
+ * -# Initialize system clock:
+ * - \code sysclk_init(); \endcode
+ * -# Create serial USART options struct:
+ * - \code
+ static usart_serial_options_t usart_options = {
+ .baudrate = USART_SERIAL_BAUDRATE,
+ .charlength = USART_SERIAL_CHAR_LENGTH,
+ .paritytype = USART_SERIAL_PARITY,
+ .stopbits = USART_SERIAL_STOP_BIT
+ };
+\endcode
+ * -# Initialize the serial service:
+ * - \code usart_serial_init(USART_SERIAL, &usart_options);\endcode
+ *
+ * \section serial_basic_use_case_usage Usage steps
+ *
+ * \subsection serial_basic_use_case_usage_code Example code
+ * Add to application C-file:
+ * \code
+ usart_serial_getchar(USART_SERIAL, &received_byte);
+ usart_serial_putchar(USART_SERIAL, received_byte);
+\endcode
+ *
+ * \subsection serial_basic_use_case_usage_flow Workflow
+ * -# Wait for reception of a character:
+ * - \code usart_serial_getchar(USART_SERIAL, &received_byte); \endcode
+ * -# Echo the character back:
+ * - \code usart_serial_putchar(USART_SERIAL, received_byte); \endcode
+ */
+
+/**
+ * \page serial_use_case_1 Advanced use case - Send a packet of serial data
+ *
+ * In this use case, the USART module is configured for:
+ * - Using USARTD0
+ * - Baudrate: 9600
+ * - Character length: 8 bit
+ * - Parity mode: Disabled
+ * - Stop bit: None
+ * - RS232 mode
+ *
+ * The use case sends a string of text through the USART.
+ *
+ * \section serial_use_case_1_setup Setup steps
+ *
+ * \subsection serial_use_case_1_setup_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (sysclk)"
+ *
+ * \subsection serial_use_case_1_setup_code Example code
+ * The following configuration must be added to the project (typically to a
+ * conf_uart_serial.h file, but it can also be added to your main application file.):
+ *
+ * \note The following takes SAM3X configuration for example, other devices have similar
+ * configuration, but their parameters may be different, refer to corresponding header files.
+ *
+ * \code
+ #define USART_SERIAL &USARTD0
+ #define USART_SERIAL_BAUDRATE 9600
+ #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT
+ #define USART_SERIAL_PARITY US_MR_PAR_NO
+ #define USART_SERIAL_STOP_BIT false
+\endcode
+ *
+ * Add to application initialization:
+ * \code
+ sysclk_init();
+
+ static usart_serial_options_t usart_options = {
+ .baudrate = USART_SERIAL_BAUDRATE,
+ .charlength = USART_SERIAL_CHAR_LENGTH,
+ .paritytype = USART_SERIAL_PARITY,
+ .stopbits = USART_SERIAL_STOP_BIT
+ };
+
+ usart_serial_init(USART_SERIAL, &usart_options);
+\endcode
+ *
+ * \subsection serial_use_case_1_setup_flow Workflow
+ * -# Initialize system clock:
+ * - \code sysclk_init(); \endcode
+ * -# Create USART options struct:
+ * - \code
+ static usart_serial_options_t usart_options = {
+ .baudrate = USART_SERIAL_BAUDRATE,
+ .charlength = USART_SERIAL_CHAR_LENGTH,
+ .paritytype = USART_SERIAL_PARITY,
+ .stopbits = USART_SERIAL_STOP_BIT
+ };
+\endcode
+ * -# Initialize in RS232 mode:
+ * - \code usart_serial_init(USART_SERIAL_EXAMPLE, &usart_options); \endcode
+ *
+ * \section serial_use_case_1_usage Usage steps
+ *
+ * \subsection serial_use_case_1_usage_code Example code
+ * Add to, e.g., main loop in application C-file:
+ * \code
+ usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String"));
+\endcode
+ *
+ * \subsection serial_use_case_1_usage_flow Workflow
+ * -# Write a string of text to the USART:
+ * - \code usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String")); \endcode
+ */
+
+#endif /* SERIAL_PLATFORM_H_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/serial/usart_serial.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,87 @@
+/**
+ *
+ * \file
+ *
+ * \brief USART Serial driver functions.
+ *
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include "serial_platform.h"
+
+/**
+ * \brief Send a sequence of bytes to USART device
+ *
+ * \param usart Base address of the USART instance.
+ * \param data Data buffer to read
+ * \param len Length of data
+ *
+ */
+status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data,
+ size_t len)
+{
+ while (len) {
+ usart_serial_putchar(usart, *data);
+ len--;
+ data++;
+ }
+ return STATUS_OK;
+}
+
+
+/**
+ * \brief Receive a sequence of bytes from USART device
+ *
+ * \param usart Base address of the USART instance.
+ * \param data Data buffer to write
+ * \param len Length of data
+ *
+ */
+status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data,
+ size_t len)
+{
+ while (len) {
+ usart_serial_getchar(usart, data);
+ len--;
+ data++;
+ }
+ return STATUS_OK;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sam/module_config/conf_sleepmgr.h Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,52 @@ +/** + * \file + * + * \brief Chip-specific sleep manager configuration + * + * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ +#ifndef CONF_SLEEPMGR_H +#define CONF_SLEEPMGR_H + +// Sleep manager options +#define CONFIG_SLEEPMGR_ENABLE + +#endif /* CONF_SLEEPMGR_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sam/sleepmgr.c Tue Apr 05 18:15:12 2016 +0100 @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief SAM3/SAM4 Sleep manager implementation. + * + * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> + */ + +#include <compiler.h> +#include <sleepmgr.h> + +#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) + +uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES]; + +#endif /* CONFIG_SLEEPMGR_ENABLE */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sam/sleepmgr.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,136 @@
+/**
+ * \file
+ *
+ * \brief SAM3/SAM4 Sleep manager implementation.
+ *
+ * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef SAM_SLEEPMGR_INCLUDED
+#define SAM_SLEEPMGR_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <conf_sleepmgr.h>
+#include <sleep.h>
+#include <interrupt.h>
+
+/**
+ * \weakgroup sleepmgr_group
+ * @{
+ */
+#if (SAMG51 || SAMG53 || SAMG54)
+enum sleepmgr_mode {
+ //! Active mode.
+ SLEEPMGR_ACTIVE = 0,
+ /*! Wait mode, wakeup fast (in 3ms).
+ * Potential Wake Up sources: fast startup events */
+ SLEEPMGR_WAIT_FAST,
+ /*! Wait mode.
+ * Potential Wake Up sources: fast startup events */
+ SLEEPMGR_WAIT,
+
+ SLEEPMGR_NR_OF_MODES,
+};
+
+#else
+enum sleepmgr_mode {
+ //! Active mode.
+ SLEEPMGR_ACTIVE = 0,
+ /*! WFE sleep mode.
+ * Potential Wake Up sources:
+ * fast startup events (USB, RTC, RTT, WKUPs),
+ * interrupt, and events. */
+ SLEEPMGR_SLEEP_WFE,
+ /*! WFI sleep mode.
+ * Potential Wake Up sources: fast startup events and interrupt. */
+ SLEEPMGR_SLEEP_WFI,
+ /*! Wait mode, wakeup fast (in 3ms).
+ * XTAL is not disabled when sleep.
+ * Potential Wake Up sources: fast startup events */
+ SLEEPMGR_WAIT_FAST,
+ /*! Wait mode.
+ * Potential Wake Up sources: fast startup events */
+ SLEEPMGR_WAIT,
+ //! Backup mode. Potential Wake Up sources: WKUPs, SM, RTT, RTC.
+ SLEEPMGR_BACKUP,
+
+ SLEEPMGR_NR_OF_MODES,
+};
+#endif
+
+/**
+ * \internal
+ * \name Internal arrays
+ * @{
+ */
+#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__)
+//! Sleep mode lock counters
+extern uint8_t sleepmgr_locks[];
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+//! @}
+
+
+static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode)
+{
+ Assert(sleep_mode != SLEEPMGR_ACTIVE);
+#ifdef CONFIG_SLEEPMGR_ENABLE
+ cpu_irq_disable();
+
+ // Atomically enable the global interrupts and enter the sleep mode.
+ pmc_sleep(sleep_mode);
+#else
+ UNUSED(sleep_mode);
+ cpu_irq_enable();
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+
+}
+
+//! @}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SAM_SLEEPMGR_INCLUDED */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/services/sleepmgr/sleepmgr.h Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,273 @@
+/**
+ * \file
+ *
+ * \brief Sleep manager
+ *
+ * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SLEEPMGR_H
+#define SLEEPMGR_H
+
+#include <compiler.h>
+#include <parts.h>
+
+#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAMS70 || SAME70)
+# include "sam/sleepmgr.h"
+#elif XMEGA
+# include "xmega/sleepmgr.h"
+#elif UC3
+# include "uc3/sleepmgr.h"
+#elif SAM4L
+# include "sam4l/sleepmgr.h"
+#elif MEGA
+# include "mega/sleepmgr.h"
+#elif (SAMD20 || SAMD21 || SAMR21 || SAMD11 || SAMDA1)
+# include "samd/sleepmgr.h"
+#elif (SAML21 || SAML22)
+# include "saml/sleepmgr.h"
+#elif (SAMC21)
+# include "samc/sleepmgr.h"
+#else
+# error Unsupported device.
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup sleepmgr_group Sleep manager
+ *
+ * The sleep manager is a service for ensuring that the device is not put to
+ * sleep in deeper sleep modes than the system (e.g., peripheral drivers,
+ * services or the application) allows at any given time.
+ *
+ * It is based on the use of lock counting for the individual sleep modes, and
+ * will put the device to sleep in the shallowest sleep mode that has a non-zero
+ * lock count. The drivers/services/application can change these counts by use
+ * of \ref sleepmgr_lock_mode and \ref sleepmgr_unlock_mode.
+ * Refer to \ref sleepmgr_mode for a list of the sleep modes available for
+ * locking, and the device datasheet for information on their effect.
+ *
+ * The application must supply the file \ref conf_sleepmgr.h.
+ *
+ * For the sleep manager to be enabled, the symbol \ref CONFIG_SLEEPMGR_ENABLE
+ * must be defined, e.g., in \ref conf_sleepmgr.h. If this symbol is not
+ * defined, the functions are replaced with dummy functions and no RAM is used.
+ *
+ * @{
+ */
+
+/**
+ * \def CONFIG_SLEEPMGR_ENABLE
+ * \brief Configuration symbol for enabling the sleep manager
+ *
+ * If this symbol is not defined, the functions of this service are replaced
+ * with dummy functions. This is useful for reducing code size and execution
+ * time if the sleep manager is not needed in the application.
+ *
+ * This symbol may be defined in \ref conf_sleepmgr.h.
+ */
+#if defined(__DOXYGEN__) && !defined(CONFIG_SLEEPMGR_ENABLE)
+# define CONFIG_SLEEPMGR_ENABLE
+#endif
+
+/**
+ * \enum sleepmgr_mode
+ * \brief Sleep mode locks
+ *
+ * Identifiers for the different sleep mode locks.
+ */
+
+/**
+ * \brief Initialize the lock counts
+ *
+ * Sets all lock counts to 0, except the very last one, which is set to 1. This
+ * is done to simplify the algorithm for finding the deepest allowable sleep
+ * mode in \ref sleepmgr_enter_sleep.
+ */
+static inline void sleepmgr_init(void)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+ uint8_t i;
+
+ for (i = 0; i < SLEEPMGR_NR_OF_MODES - 1; i++) {
+ sleepmgr_locks[i] = 0;
+ }
+ sleepmgr_locks[SLEEPMGR_NR_OF_MODES - 1] = 1;
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+/**
+ * \brief Increase lock count for a sleep mode
+ *
+ * Increases the lock count for \a mode to ensure that the sleep manager does
+ * not put the device to sleep in the deeper sleep modes.
+ *
+ * \param mode Sleep mode to lock.
+ */
+static inline void sleepmgr_lock_mode(enum sleepmgr_mode mode)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+ irqflags_t flags;
+
+ if(sleepmgr_locks[mode] >= 0xff) {
+ while (true) {
+ // Warning: maximum value of sleepmgr_locks buffer is no more than 255.
+ // Check APP or change the data type to uint16_t.
+ }
+ }
+
+ // Enter a critical section
+ flags = cpu_irq_save();
+
+ ++sleepmgr_locks[mode];
+
+ // Leave the critical section
+ cpu_irq_restore(flags);
+#else
+ UNUSED(mode);
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+/**
+ * \brief Decrease lock count for a sleep mode
+ *
+ * Decreases the lock count for \a mode. If the lock count reaches 0, the sleep
+ * manager can put the device to sleep in the deeper sleep modes.
+ *
+ * \param mode Sleep mode to unlock.
+ */
+static inline void sleepmgr_unlock_mode(enum sleepmgr_mode mode)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+ irqflags_t flags;
+
+ if(sleepmgr_locks[mode] == 0) {
+ while (true) {
+ // Warning: minimum value of sleepmgr_locks buffer is no less than 0.
+ // Check APP.
+ }
+ }
+
+ // Enter a critical section
+ flags = cpu_irq_save();
+
+ --sleepmgr_locks[mode];
+
+ // Leave the critical section
+ cpu_irq_restore(flags);
+#else
+ UNUSED(mode);
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+/**
+* \brief Retrieves the deepest allowable sleep mode
+*
+* Searches through the sleep mode lock counts, starting at the shallowest sleep
+* mode, until the first non-zero lock count is found. The deepest allowable
+* sleep mode is then returned.
+*/
+static inline enum sleepmgr_mode sleepmgr_get_sleep_mode(void)
+{
+ enum sleepmgr_mode sleep_mode = SLEEPMGR_ACTIVE;
+
+#ifdef CONFIG_SLEEPMGR_ENABLE
+ uint8_t *lock_ptr = sleepmgr_locks;
+
+ // Find first non-zero lock count, starting with the shallowest modes.
+ while (!(*lock_ptr)) {
+ lock_ptr++;
+ sleep_mode = (enum sleepmgr_mode)(sleep_mode + 1);
+ }
+
+ // Catch the case where one too many sleepmgr_unlock_mode() call has been
+ // performed on the deepest sleep mode.
+ Assert((uintptr_t)(lock_ptr - sleepmgr_locks) < SLEEPMGR_NR_OF_MODES);
+
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+
+ return sleep_mode;
+}
+
+/**
+ * \fn sleepmgr_enter_sleep
+ * \brief Go to sleep in the deepest allowed mode
+ *
+ * Searches through the sleep mode lock counts, starting at the shallowest sleep
+ * mode, until the first non-zero lock count is found. The device is then put to
+ * sleep in the sleep mode that corresponds to the lock.
+ *
+ * \note This function enables interrupts before going to sleep, and will leave
+ * them enabled upon return. This also applies if sleep is skipped due to ACTIVE
+ * mode being locked.
+ */
+
+static inline void sleepmgr_enter_sleep(void)
+{
+#ifdef CONFIG_SLEEPMGR_ENABLE
+ enum sleepmgr_mode sleep_mode;
+
+ cpu_irq_disable();
+
+ // Find the deepest allowable sleep mode
+ sleep_mode = sleepmgr_get_sleep_mode();
+ // Return right away if first mode (ACTIVE) is locked.
+ if (sleep_mode==SLEEPMGR_ACTIVE) {
+ cpu_irq_enable();
+ return;
+ }
+ // Enter the deepest allowable sleep mode with interrupts enabled
+ sleepmgr_sleep(sleep_mode);
+#else
+ cpu_irq_enable();
+#endif /* CONFIG_SLEEPMGR_ENABLE */
+}
+
+
+//! @}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SLEEPMGR_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/sleep_api.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "sleep_api.h"
+#include "sleepmgr.h"
+
+/** Send the device to sleep
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs.
+ * @param[void] void
+ * @return void
+ */
+void sleep(void)
+{
+ enum sleepmgr_mode sleep_mode;
+
+ sleep_mode = SLEEPMGR_SLEEP_WFI;
+ sleepmgr_sleep(sleep_mode);
+
+}
+/** Send the device to deep sleep
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ * @param[void] void
+ * @return void
+ */
+void deepsleep(void)
+{
+ enum sleepmgr_mode sleep_mode;
+
+ sleep_mode = SLEEPMGR_SLEEP_WFE;
+ sleepmgr_sleep(sleep_mode);
+}
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/spi_api.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,506 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "device.h"
+#include "dma_api.h"
+#include "buffer.h"
+#include "spi_api.h"
+#include "pinmap.h"
+#include "spi_driver.h"
+#include "PeripheralPins.h"
+#include "pdc.h"
+
+
+/* Chip select. */
+#define SPI_CHIP_SEL 0
+
+/* Clock polarity. */
+#define SPI_CLK_POLARITY 0
+
+/* Clock phase. */
+#define SPI_CLK_PHASE 0
+
+/* Last data */
+#define SPI_LAST 0
+
+
+/* Delay before SPCK. */
+#define SPI_DLYBS 0x40
+
+/* Delay between consecutive transfers. */
+#define SPI_DLYBCT 0x10
+
+#define MAX_SPI 8
+
+/* SPI clock setting (Hz). */
+uint32_t gSPI_clock=500000;
+
+extern uint8_t g_sys_init;
+
+
+
+void pinmap_find_spi_info(Spi *sercombase, spi_t *obj)
+{
+ if(sercombase==SPI0) {
+ obj->spi.flexcom=FLEXCOM0;
+ obj->spi.module_number=0;
+ obj->spi.pdc =PDC_SPI0;
+ obj->spi.irq_type=FLEXCOM0_IRQn;
+ } else if(sercombase==SPI1) {
+ obj->spi.flexcom=FLEXCOM1;
+ obj->spi.module_number=1;
+ obj->spi.pdc =PDC_SPI1;
+ obj->spi.irq_type=FLEXCOM1_IRQn;
+ } else if(sercombase==SPI2) {
+ obj->spi.flexcom=FLEXCOM2;
+ obj->spi.module_number=2;
+ obj->spi.pdc =PDC_SPI2;
+ obj->spi.irq_type=FLEXCOM2_IRQn;
+ } else if(sercombase==SPI3) {
+ obj->spi.flexcom=FLEXCOM3;
+ obj->spi.module_number=3;
+ obj->spi.pdc =PDC_SPI3;
+ obj->spi.irq_type=FLEXCOM3_IRQn;
+ } else if(sercombase==SPI4) {
+ obj->spi.flexcom=FLEXCOM4;
+ obj->spi.module_number=4;
+ obj->spi.pdc =PDC_SPI4;
+ obj->spi.irq_type=FLEXCOM4_IRQn;
+ } else if(sercombase==SPI5) {
+ obj->spi.flexcom=FLEXCOM5;
+ obj->spi.module_number=5;
+ obj->spi.pdc =PDC_SPI5;
+ obj->spi.irq_type=FLEXCOM5_IRQn;
+ } else if(sercombase==SPI6) {
+ obj->spi.flexcom=FLEXCOM6;
+ obj->spi.module_number=6;
+ obj->spi.pdc =PDC_SPI6;
+ obj->spi.irq_type=FLEXCOM6_IRQn;
+ } else if(sercombase==SPI7) {
+ obj->spi.flexcom=FLEXCOM7;
+ obj->spi.module_number=7;
+ obj->spi.pdc =PDC_SPI7;
+ obj->spi.irq_type=FLEXCOM7_IRQn;
+ } else {
+ obj->spi.flexcom=(Flexcom *)NC;
+ obj->spi.module_number=0;
+ obj->spi.pdc =(Pdc *) NC;
+ }
+}
+
+Spi* pinmap_find_sercom(PinName mosi, PinName miso, PinName sclk)
+{
+ Spi* sercomIndex=(Spi*)pinmap_peripheral (mosi,PinMap_SPI_MOSI);
+ if(sercomIndex== (Spi*)pinmap_peripheral (miso, PinMap_SPI_MISO) &&
+ sercomIndex == (Spi*)pinmap_peripheral (sclk, PinMap_SPI_SCLK))
+ return sercomIndex;
+
+ return (Spi*)NC;
+}
+
+
+/** Initialize the SPI peripheral
+ *
+ * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
+ * @param[out] obj The SPI object to initialize
+ * @param[in] mosi The pin to use for MOSI
+ * @param[in] miso The pin to use for MISO
+ * @param[in] sclk The pin to use for SCLK
+ * @param[in] ssel The pin to use for SSEL <Not Used>
+ */
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel /*Not Used*/)
+{
+ MBED_ASSERT(obj);
+ MBED_ASSERT(mosi !=NC && miso!=NC && sclk !=NC );
+
+ if (g_sys_init == 0) {
+ sysclk_init();
+ system_board_init();
+ g_sys_init = 1;
+ }
+
+ Spi *sercombase = pinmap_find_sercom(mosi,miso,sclk);
+ MBED_ASSERT(sercombase!=NC);
+
+ pinmap_find_spi_info(sercombase, obj);
+ MBED_ASSERT(obj->spi.flexcom!=NC);
+ MBED_ASSERT(obj->spi.pdc!=NC);
+
+ /* Configure SPI pins */
+ pin_function(mosi, pinmap_find_function(mosi, PinMap_SPI_MOSI));
+ ioport_disable_pin(mosi);
+
+ pin_function(miso, pinmap_find_function(miso, PinMap_SPI_MISO));
+ ioport_disable_pin(miso);
+
+ pin_function(sclk, pinmap_find_function(sclk, PinMap_SPI_SCLK));
+ ioport_disable_pin(sclk);
+
+#if (SAMG55)
+ /* Enable the peripheral and set SPI mode. */
+ flexcom_enable(obj->spi.flexcom);
+ flexcom_set_opmode(obj->spi.flexcom, FLEXCOM_SPI);
+#else
+ /* Configure an SPI peripheral. */
+ spi_enable_clock(sercombase);
+#endif
+ spi_disable(sercombase);
+ spi_reset(sercombase);
+ spi_set_lastxfer(sercombase);
+ spi_set_master_mode(sercombase);
+ spi_disable_mode_fault_detect(sercombase);
+ spi_set_peripheral_chip_select_value(sercombase, SPI_CHIP_SEL);
+ spi_set_clock_polarity(sercombase, SPI_CHIP_SEL, SPI_CLK_POLARITY);
+ spi_set_clock_phase(sercombase, SPI_CHIP_SEL, SPI_CLK_PHASE);
+ spi_set_bits_per_transfer(sercombase, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
+ spi_set_baudrate_div(sercombase, SPI_CHIP_SEL,(sysclk_get_cpu_hz() / gSPI_clock));
+ spi_set_transfer_delay(sercombase, SPI_CHIP_SEL, SPI_DLYBS,SPI_DLYBCT);
+
+ spi_enable(sercombase);
+
+ pdc_disable_transfer(obj->spi.pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);
+
+ obj->spi.spi_base=sercombase;
+ obj->spi.cs= SPI_CHIP_SEL;
+ obj->spi.polarity=SPI_CLK_POLARITY;
+ obj->spi.phase=SPI_CLK_PHASE;
+ obj->spi.transferrate=SPI_CSR_BITS_8_BIT;
+ obj->spi.is_slave=0;
+}
+
+/** Release a SPI object
+ *
+ * TODO: spi_free is currently unimplemented
+ * This will require reference counting at the C++ level to be safe
+ *
+ * Return the pins owned by the SPI object to their reset state
+ * Disable the SPI peripheral
+ * Disable the SPI clock
+ * @param[in] obj The SPI object to deinitialize
+ */
+void spi_free(spi_t *obj)
+{
+ MBED_ASSERT(obj);
+ spi_disable(obj->spi.spi_base);
+ spi_reset(obj->spi.spi_base);
+ flexcom_disable((Flexcom *)obj->spi.flexcom);
+}
+
+uint32_t get_transfer_rate(int bits)
+{
+ switch(bits) {
+ case 8:
+ return SPI_CSR_BITS_8_BIT;
+ case 9:
+ return SPI_CSR_BITS_9_BIT;
+ case 10:
+ return SPI_CSR_BITS_10_BIT;
+ case 11:
+ return SPI_CSR_BITS_11_BIT;
+ case 12:
+ return SPI_CSR_BITS_12_BIT;
+ case 13:
+ return SPI_CSR_BITS_13_BIT;
+ case 14:
+ return SPI_CSR_BITS_14_BIT;
+ case 15:
+ return SPI_CSR_BITS_15_BIT;
+ case 16:
+ return SPI_CSR_BITS_16_BIT;
+ default:
+ return NC;
+ }
+}
+
+/** Configure the SPI format
+ *
+ * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode
+ * @param[in,out] obj The SPI object to configure
+ * @param[in] bits The number of bits per frame
+ * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
+ * @param[in] slave Zero for master mode or non-zero for slave mode
+ */
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+ uint32_t transferrate= get_transfer_rate(bits);
+ MBED_ASSERT(transferrate!=NC);
+
+ spi_disable(obj->spi.spi_base);
+ obj->spi.transferrate=transferrate;
+ if(slave) {
+ spi_set_slave_mode(obj->spi.spi_base);
+ obj->spi.is_slave=1;
+ } else {
+ spi_set_master_mode(obj->spi.spi_base);
+ obj->spi.is_slave=0;
+ }
+ spi_set_bits_per_transfer(obj->spi.spi_base, obj->spi.cs, obj->spi.transferrate);
+ spi_set_clock_phase(obj->spi.spi_base, SPI_CHIP_SEL, (mode & 0x01));
+ spi_set_clock_polarity(obj->spi.spi_base, SPI_CHIP_SEL, (mode & 0x02));
+
+ obj->spi.phase=(mode & 0x01);
+ obj->spi.polarity=(mode & 0x02);
+ spi_enable(obj->spi.spi_base);
+}
+
+/** Set the SPI baud rate
+ *
+ * Actual frequency may differ from the desired frequency due to available dividers and bus clock
+ * Configures the SPI peripheral's baud rate
+ * @param[in,out] obj The SPI object to configure
+ * @param[in] hz The baud rate in Hz
+ */
+
+void spi_frequency(spi_t *obj, int hz)
+{
+ spi_disable(obj->spi.spi_base);
+ int16_t baudrate_div=spi_calc_baudrate_div(hz, sysclk_get_cpu_hz());
+ spi_set_baudrate_div(obj->spi.spi_base,obj->spi.cs,(uint8_t)baudrate_div);
+ spi_enable(obj->spi.spi_base);
+}
+
+/**@}*/
+/**
+ * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
+ * @{
+ */
+
+/** Write a byte out in master mode and receive a value
+ *
+ * @param[in] obj The SPI peripheral to use for sending
+ * @param[in] value The value to send
+ * @return Returns the value received during send
+ */
+int spi_master_write(spi_t *obj, int value)
+{
+ spi_status_t status=spi_write(obj->spi.spi_base,(uint16_t)value,obj->spi.cs,SPI_LAST);
+ if(status ==SPI_OK) {
+ uint16_t data;
+ status =spi_read(obj->spi.spi_base,&data,&obj->spi.cs);
+ if(status == SPI_OK)
+ return data;
+ }
+ return 0;
+}
+
+/** Check if a value is available to read
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return non-zero if a value is available
+ */
+int spi_slave_receive(spi_t *obj)
+{
+ if(obj->spi.spi_base->SPI_SR & SPI_SR_RDRF)
+ return 1;
+ return 0;
+}
+
+/** Get a received value out of the SPI receive buffer in slave mode
+ *
+ * Blocks until a value is available
+ * @param[in] obj The SPI peripheral to read
+ * @return The value received
+ */
+int spi_slave_read(spi_t *obj)
+{
+ uint16_t data;
+ spi_status_t status =spi_read(obj->spi.spi_base, &data, &obj->spi.cs);
+ if(status == SPI_OK)
+ return data;
+ return 0;
+}
+
+/** Write a value to the SPI peripheral in slave mode
+ *
+ * Blocks until the SPI peripheral can be written to
+ * @param[in] obj The SPI peripheral to write
+ * @param[in] value The value to write
+ */
+void spi_slave_write(spi_t *obj, int value)
+{
+ spi_write(obj->spi.spi_base,(uint16_t)value,obj->spi.cs,SPI_LAST);
+}
+
+/** Checks if the specified SPI peripheral is in use
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return non-zero if the peripheral is currently transmitting
+ */
+int spi_busy(spi_t *obj)
+{
+ if(obj->spi.spi_base->SPI_SR & SPI_SR_TDRE) //Transmit Data Register Empty
+ return 0;
+ return 1;
+}
+
+/** Get the module number
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return The module number
+ */
+uint8_t spi_get_module(spi_t *obj)
+{
+ return obj->spi.module_number;
+}
+
+
+/**@}*/
+#if DEVICE_SPI_ASYNCH
+/**
+ * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
+ * @{
+ */
+
+/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
+ *
+ * @param[in] obj The SPI object which holds the transfer information
+ * @param[in] tx The buffer to send
+ * @param[in] tx_length The number of words to transmit
+ * @param[in] rx The buffer to receive
+ * @param[in] rx_length The number of words to receive
+ * @param[in] bit_width The bit width of buffer words
+ * @param[in] event The logical OR of events to be registered
+ * @param[in] handler SPI interrupt handler
+ * @param[in] hint A suggestion for how to use DMA with this transfer
+ */
+#warning "Only DMA async supported by SPI master transfer"
+
+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
+{
+ uint32_t pdcenable=0;
+
+ if(bit_width) {
+ uint32_t transferrate= get_transfer_rate(bit_width);
+ spi_set_bits_per_transfer(obj->spi.spi_base, obj->spi.cs, transferrate);
+ }
+
+ if(tx) {
+ pdc_packet_t pdc_packet_tx;
+ pdc_packet_tx.ul_addr=(uint32_t)tx;
+ pdc_packet_tx.ul_size=tx_length;
+
+ pdcenable|=PERIPH_PTCR_TXTEN;
+ /* Configure PDC for data send */
+ pdc_tx_init(obj->spi.pdc, &pdc_packet_tx, NULL);
+ }
+
+ if(rx) {
+ pdc_rx_clear_cnt(obj->spi.pdc);
+ pdc_packet_t pdc_packet_rx;
+ pdc_packet_rx.ul_addr=(uint32_t)rx;
+ pdc_packet_rx.ul_size=rx_length;
+ pdcenable|=PERIPH_PTCR_RXTEN;
+ char *rxbuffer=(char *)rx;
+ for(uint8_t index=0; index<rx_length; index++, rxbuffer++)
+ *rxbuffer=SPI_FILL_WORD;
+
+ /* Configure PDC for data receive */
+ pdc_rx_init(obj->spi.pdc, &pdc_packet_rx, NULL);
+ }
+
+ obj->spi.dma_usage=hint;
+ obj->spi.event=event;
+
+ NVIC_ClearPendingIRQ(obj->spi.irq_type);
+ NVIC_DisableIRQ(obj->spi.irq_type);
+ NVIC_SetVector(obj->spi.irq_type,handler);
+ NVIC_EnableIRQ(obj->spi.irq_type);
+
+ /* Enable SPI IRQ */
+ spi_enable_interrupt(obj->spi.spi_base, SPI_IER_RXBUFF| SPI_IER_TXBUFE | SPI_IER_MODF | SPI_IER_OVRES);
+
+ /* Enable PDC transfers */
+ pdc_enable_transfer(obj->spi.pdc, pdcenable );
+
+}
+
+/** The asynchronous IRQ handler
+ *
+ * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
+ * conditions, such as buffer overflows or transfer complete.
+ * @param[in] obj The SPI object which holds the transfer information
+ * @return event flags if a transfer termination condition was met or 0 otherwise.
+ */
+uint32_t spi_irq_handler_asynch(spi_t *obj)
+{
+ uint32_t event=0;
+
+ // Data transferred via DMA
+ if((obj->spi.spi_base->SPI_SR & SPI_IER_TXBUFE)) {
+ spi_disable_interrupt(obj->spi.spi_base, SPI_IDR_TXBUFE | SPI_IDR_MODF | SPI_IDR_OVRES);
+ if(obj->spi.event | SPI_EVENT_COMPLETE)
+ event |=SPI_EVENT_COMPLETE;
+ }
+
+ if((obj->spi.spi_base->SPI_SR & SPI_IER_RXBUFF)) {
+ spi_disable_interrupt(obj->spi.spi_base, SPI_IDR_RXBUFF | SPI_IDR_MODF | SPI_IDR_OVRES);
+ if(obj->spi.event | SPI_EVENT_COMPLETE)
+ event |=SPI_EVENT_COMPLETE;
+ }
+
+ if(obj->spi.spi_base->SPI_SR & SPI_SR_MODF) {
+ if(obj->spi.event | SPI_EVENT_ERROR)
+ event |=SPI_EVENT_ERROR;
+ }
+
+ if(obj->spi.spi_base->SPI_SR & SPI_SR_OVRES) {
+ if(obj->spi.event | SPI_EVENT_RX_OVERFLOW)
+ event |=SPI_EVENT_RX_OVERFLOW;
+ }
+
+ return event;
+}
+
+/** Attempts to determine if the SPI peripheral is already in use.
+ *
+ * If a temporary DMA channel has been allocated, peripheral is in use.
+ * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
+ * channel were allocated.
+ * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
+ * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
+ * there are any bytes in the FIFOs.
+ * @param[in] obj The SPI object to check for activity
+ * @return non-zero if the SPI port is active or zero if it is not.
+ */
+
+uint8_t spi_active(spi_t *obj)
+{
+ if(obj->spi.spi_base->SPI_SR & SPI_SR_ENDTX && obj->spi.spi_base->SPI_SR & SPI_SR_ENDRX)
+ return 0;
+ return 1;
+}
+
+/** Abort an SPI transfer
+ *
+ * @param obj The SPI peripheral to stop
+ */
+void spi_abort_asynch(spi_t *obj)
+{
+ /* Disable PDC transfers */
+ pdc_disable_transfer(obj->spi.pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);
+
+ /* Clear PDC buffer receive counter */
+ pdc_rx_clear_cnt(obj->spi.pdc);
+
+ /* Disable SPI IRQ */
+ spi_disable_interrupt(obj->spi.spi_base, SPI_IDR_TXBUFE);
+ spi_disable_interrupt(obj->spi.spi_base, SPI_IDR_RXBUFF);
+
+ /* Disable SPI interrupt */
+ NVIC_DisableIRQ(obj->spi.irq_type);
+}
+
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/us_ticker.c Tue Apr 05 18:15:12 2016 +0100
@@ -0,0 +1,183 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "cmsis.h"
+#include "mbed_assert.h"
+#include "compiler.h"
+#include "sysclk.h"
+#include "tc.h"
+
+uint8_t us_ticker_inited = 0;
+extern uint8_t g_sys_init;
+volatile uint16_t us_ticker_16bit_counter;
+volatile uint16_t us_ticker_interrupt_counter;
+volatile uint16_t us_ticker_interrupt_offset;
+volatile uint32_t overflow32bitcounter = 0;
+
+#define TICKER_COUNTER_uS TC1
+
+#define TICKER_COUNTER_CLK0 ID_TC3
+#define TICKER_COUNTER_CLK1 ID_TC4
+
+#define TICKER_COUNTER_CHANNEL0 0
+#define TICKER_COUNTER_IRQn0 TC3_IRQn
+#define TICKER_COUNTER_Handlr0 TC3_Handler
+
+#define TICKER_COUNTER_CHANNEL1 1
+#define TICKER_COUNTER_IRQn1 TC4_IRQn
+#define TICKER_COUNTER_Handlr1 TC4_Handler
+
+#define OVERFLOW_16bit_VALUE 0xFFFF
+
+
+void TICKER_COUNTER_Handlr1(void)
+{
+ uint32_t status=tc_get_status(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
+ uint32_t interrupmask=tc_get_interrupt_mask(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
+
+ if (((status & interrupmask) & TC_IER_CPCS)) {
+ if(us_ticker_interrupt_counter) {
+ us_ticker_interrupt_counter--;
+ } else {
+ if(us_ticker_interrupt_offset) {
+ us_ticker_interrupt_offset=0;
+ tc_stop(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
+ tc_write_rc(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, (uint32_t)us_ticker_interrupt_offset);
+ tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
+ } else
+ us_ticker_irq_handler();
+ }
+ }
+}
+
+void TICKER_COUNTER_Handlr0(void)
+{
+ uint32_t status=tc_get_status(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0);
+ uint32_t interrupmask=tc_get_interrupt_mask(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0);
+
+ if (((status & interrupmask) & TC_IER_COVFS)) {
+ us_ticker_16bit_counter++;
+ if(us_ticker_16bit_counter == 0xFFFF)
+ overflow32bitcounter++;
+ }
+}
+
+void us_ticker_init(void)
+{
+ if (us_ticker_inited) return;
+ us_ticker_inited = 1;
+
+ us_ticker_16bit_counter=0;
+ us_ticker_interrupt_counter=0;
+ us_ticker_interrupt_offset=0;
+
+ if (g_sys_init == 0) {
+ sysclk_init();
+ system_board_init();
+ g_sys_init = 1;
+ }
+
+ /* Configure the PMC to enable the TC module. */
+ sysclk_enable_peripheral_clock(TICKER_COUNTER_CLK0);
+ sysclk_enable_peripheral_clock(TICKER_COUNTER_CLK1);
+
+#if SAMG55
+ /* Enable PCK output */
+ pmc_disable_pck(PMC_PCK_3);
+ pmc_switch_pck_to_mck(PMC_PCK_3, PMC_PCK_PRES_CLK_1);
+ pmc_enable_pck(PMC_PCK_3);
+#endif
+
+ /* Init TC to Counter mode. */
+ tc_init(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0, TC_CMR_TCCLKS_TIMER_CLOCK4);
+ tc_init(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, TC_CMR_TCCLKS_TIMER_CLOCK4);
+
+
+ NVIC_DisableIRQ(TICKER_COUNTER_IRQn0);
+
+ NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn0);
+ NVIC_SetPriority(TICKER_COUNTER_IRQn0, 0);
+ NVIC_EnableIRQ(TICKER_COUNTER_IRQn0);
+ tc_enable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0, TC_IER_COVFS);
+
+ tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0);
+}
+
+
+uint32_t us_ticker_read()
+{
+ if (!us_ticker_inited)
+ us_ticker_init();
+
+ uint32_t counter_value=0;
+ uint16_t tickerbefore=0;
+ do {
+ tickerbefore=us_ticker_16bit_counter;
+ counter_value=tc_read_cv(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0);
+ } while(tickerbefore!=us_ticker_16bit_counter);
+
+ return counter_value+(OVERFLOW_16bit_VALUE*us_ticker_16bit_counter);
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+ uint32_t cur_time;
+ int32_t delta;
+
+ cur_time = us_ticker_read();
+ delta = (int32_t)((uint32_t)timestamp - cur_time);
+ if (delta < 0) {
+ /* Event already occurred in past */
+ us_ticker_irq_handler();
+ return;
+ }
+
+ uint16_t interruptat=0;
+
+ if(delta > OVERFLOW_16bit_VALUE) {
+ us_ticker_interrupt_counter= (delta/OVERFLOW_16bit_VALUE) -1;
+ us_ticker_interrupt_offset=delta%OVERFLOW_16bit_VALUE;
+ interruptat=OVERFLOW_16bit_VALUE;
+ } else {
+ us_ticker_interrupt_counter=0;
+ us_ticker_interrupt_offset=0;
+ interruptat=delta;
+ }
+
+ NVIC_DisableIRQ(TICKER_COUNTER_IRQn1);
+
+ tc_write_rc(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, (uint32_t)interruptat);
+
+ NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn1);
+ NVIC_SetPriority(TICKER_COUNTER_IRQn1, 0);
+ NVIC_EnableIRQ(TICKER_COUNTER_IRQn1);
+ tc_enable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, TC_IDR_CPCS );
+
+ tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
+}
+
+void us_ticker_disable_interrupt(void)
+{
+ tc_stop(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
+ tc_disable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, TC_IDR_CPCS);
+ NVIC_DisableIRQ(TICKER_COUNTER_IRQn1);
+}
+
+void us_ticker_clear_interrupt(void)
+{
+ NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn1);
+}