Frank Vannieuwkerke
LPC1768 Mini-DK EasyWeb application with SPI TFT output. Started from EasyWebCR and modified for DM9161 PHY support.
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ethmac.h
00001 /****************************************************************** 00002 ***** ***** 00003 ***** Name: ethmac.h ***** 00004 ***** Ver.: 1.0 ***** 00005 ***** Date: 17/12/2012 ***** 00006 ***** Auth: Frank Vannieuwkerke ***** 00007 ***** Func: header-file for ethmac.c ***** 00008 ***** Rewrite from Andreas Dannenberg ***** 00009 ***** HTWK Leipzig ***** 00010 ***** university of applied sciences ***** 00011 ***** Germany ***** 00012 ***** adannenb@et.htwk-leipzig.de ***** 00013 ***** ***** 00014 ******************************************************************/ 00015 00016 #ifndef __ETHMAC_H 00017 #define __ETHMAC_H 00018 00019 // Ethernet power/clock control bit in PCONP register 00020 #define PCENET 0x40000000 00021 // Ethernet configuration for PINSEL2, as per user guide section 5.3 00022 #define ENET_PINSEL2_CONFIG 0x50150105 00023 // Ethernet configuration for PINSEL3, as per user guide section 5.4 00024 #define ENET_PINSEL3_CONFIG 0x00000005 00025 // Only bottom byte of PINSEL3 relevant to Ethernet 00026 #define ENET_PINSEL3_MASK 0x0000000F 00027 00028 #define MYMAC_1 1 // our ethernet (MAC) address 00029 #define MYMAC_2 2 // (MUST be unique in LAN!) 00030 #define MYMAC_3 3 00031 #define MYMAC_4 4 00032 #define MYMAC_5 5 00033 #define MYMAC_6 6 00034 00035 // ******* 00036 // defines for LPC1768 ethernet 00037 // ******* 00038 00039 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ 00040 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ 00041 #define NUM_TX_FRAG 2 /* Num.of TX Fragments 3*1536= 4.6kB */ 00042 #define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ 00043 00044 #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ 00045 00046 /* EMAC variables located in AHB SRAM bank 1*/ 00047 #define RX_DESC_BASE 0x20080000 00048 #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) 00049 #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) 00050 #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) 00051 #define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4) 00052 #define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE) 00053 00054 /* RX and TX descriptor and status definitions. */ 00055 #define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i)) 00056 #define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i)) 00057 #define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i)) 00058 #define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i)) 00059 #define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i)) 00060 #define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i)) 00061 #define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i)) 00062 #define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) 00063 #define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) 00064 00065 /* MAC Configuration Register 1 */ 00066 #define MAC1_REC_EN 0x00000001 /* Receive Enable */ 00067 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ 00068 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ 00069 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ 00070 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ 00071 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ 00072 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ 00073 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ 00074 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ 00075 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ 00076 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ 00077 00078 /* MAC Configuration Register 2 */ 00079 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ 00080 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ 00081 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ 00082 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ 00083 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ 00084 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ 00085 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ 00086 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ 00087 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ 00088 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ 00089 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ 00090 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ 00091 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ 00092 00093 /* Back-to-Back Inter-Packet-Gap Register */ 00094 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ 00095 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ 00096 00097 /* Non Back-to-Back Inter-Packet-Gap Register */ 00098 #define IPGR_DEF 0x00000012 /* Recommended value */ 00099 00100 /* Collision Window/Retry Register */ 00101 #define CLRT_DEF 0x0000370F /* Default value */ 00102 00103 /* PHY Support Register */ 00104 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ 00105 #define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ 00106 00107 /* Test Register */ 00108 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ 00109 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */ 00110 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ 00111 00112 /* MII Management Configuration Register */ 00113 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ 00114 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ 00115 #define MCFG_CLK_SEL(n) ((n&0x0F)<<2)/* Clock Select Mask */ 00116 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ 00117 #define MCFG_MII_MAXCLK 2500000UL /* MII Clock max */ 00118 00119 /* MII Management Command Register */ 00120 #define MCMD_READ 0x00000001 /* MII Read */ 00121 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */ 00122 00123 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ 00124 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ 00125 00126 /* MII Management Address Register */ 00127 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ 00128 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ 00129 00130 /* MII Management Indicators Register */ 00131 #define MIND_BUSY 0x00000001 /* MII is Busy */ 00132 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ 00133 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ 00134 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ 00135 00136 /* Command Register */ 00137 #define CR_RX_EN 0x00000001 /* Enable Receive */ 00138 #define CR_TX_EN 0x00000002 /* Enable Transmit */ 00139 #define CR_REG_RES 0x00000008 /* Reset Host Registers */ 00140 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ 00141 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ 00142 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ 00143 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ 00144 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ 00145 #define CR_RMII 0x00000200 /* Reduced MII Interface */ 00146 #define CR_FULL_DUP 0x00000400 /* Full Duplex */ 00147 00148 /* Status Register */ 00149 #define SR_RX_EN 0x00000001 /* Enable Receive */ 00150 #define SR_TX_EN 0x00000002 /* Enable Transmit */ 00151 00152 /* Transmit Status Vector 0 Register */ 00153 #define TSV0_CRC_ERR 0x00000001 /* CRC error */ 00154 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ 00155 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ 00156 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */ 00157 #define TSV0_MCAST 0x00000010 /* Multicast Destination */ 00158 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */ 00159 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ 00160 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ 00161 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ 00162 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ 00163 #define TSV0_GIANT 0x00000400 /* Giant Frame */ 00164 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ 00165 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ 00166 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ 00167 #define TSV0_PAUSE 0x20000000 /* Pause Frame */ 00168 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ 00169 #define TSV0_VLAN 0x80000000 /* VLAN Frame */ 00170 00171 /* Transmit Status Vector 1 Register */ 00172 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ 00173 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ 00174 00175 /* Receive Status Vector Register */ 00176 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ 00177 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ 00178 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ 00179 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ 00180 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ 00181 #define RSV_CRC_ERR 0x00100000 /* CRC Error */ 00182 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ 00183 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ 00184 #define RSV_REC_OK 0x00800000 /* Frame Received OK */ 00185 #define RSV_MCAST 0x01000000 /* Multicast Frame */ 00186 #define RSV_BCAST 0x02000000 /* Broadcast Frame */ 00187 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ 00188 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ 00189 #define RSV_PAUSE 0x10000000 /* Pause Frame */ 00190 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ 00191 #define RSV_VLAN 0x40000000 /* VLAN Frame */ 00192 00193 /* Flow Control Counter Register */ 00194 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ 00195 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ 00196 00197 /* Flow Control Status Register */ 00198 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ 00199 00200 /* Receive Filter Control Register */ 00201 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ 00202 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ 00203 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ 00204 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ 00205 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ 00206 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ 00207 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ 00208 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ 00209 00210 /* Receive Filter WoL Status/Clear Registers */ 00211 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ 00212 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ 00213 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ 00214 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ 00215 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ 00216 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ 00217 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ 00218 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ 00219 00220 /* Interrupt Status/Enable/Clear/Set Registers */ 00221 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ 00222 #define INT_RX_ERR 0x00000002 /* Receive Error */ 00223 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ 00224 #define INT_RX_DONE 0x00000008 /* Receive Done */ 00225 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ 00226 #define INT_TX_ERR 0x00000020 /* Transmit Error */ 00227 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ 00228 #define INT_TX_DONE 0x00000080 /* Transmit Done */ 00229 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ 00230 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ 00231 00232 /* Power Down Register */ 00233 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ 00234 00235 /* RX Descriptor Control Word */ 00236 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */ 00237 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ 00238 00239 /* RX Status Hash CRC Word */ 00240 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ 00241 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ 00242 00243 /* RX Status Information Word */ 00244 #define RINFO_SIZE 0x000007FF /* Data size in bytes */ 00245 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ 00246 #define RINFO_VLAN 0x00080000 /* VLAN Frame */ 00247 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ 00248 #define RINFO_MCAST 0x00200000 /* Multicast Frame */ 00249 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */ 00250 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ 00251 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ 00252 #define RINFO_LEN_ERR 0x02000000 /* Length Error */ 00253 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ 00254 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ 00255 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */ 00256 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ 00257 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ 00258 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ 00259 00260 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ 00261 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) 00262 00263 /* TX Descriptor Control Word */ 00264 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ 00265 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ 00266 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ 00267 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ 00268 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ 00269 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ 00270 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ 00271 00272 /* TX Status Information Word */ 00273 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */ 00274 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ 00275 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ 00276 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ 00277 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ 00278 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ 00279 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ 00280 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ 00281 00282 /* ENET Device Revision ID */ 00283 #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ 00284 00285 /** PHY device reset time out definition */ 00286 #define PHY_RESP_TOUT 0x100000UL 00287 00288 /* DM9161 PHY Registers */ 00289 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ 00290 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ 00291 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ 00292 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ 00293 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ 00294 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ 00295 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ 00296 00297 /* PHY Extended Registers */ 00298 #define PHY_REG_DSCR 0x10 /* Specified Configuration Register */ 00299 #define PHY_REG_DSCSR 0x11 /* Specified Configuration and Status Register */ 00300 #define PHY_REG_10BTCSR 0x12 /* 10BASE-T Configuration and Satus Register */ 00301 #define PHY_REG_MDINTR 0x15 /* Specified Interrupt Register */ 00302 #define PHY_REG_RECR 0x16 /* Specified Receive Error Counter Register */ 00303 #define PHY_REG_DISCR 0x17 /* Specified Disconnect Counter Register */ 00304 #define PHY_REG_RLSR 0x18 /* Hardware Reset Latch State Register */ 00305 00306 //--Bit definitions: DM9161_BMCR 00307 #define DM9161_RESET (1 << 15) // 1=Software Reset; 0=Normal Operation 00308 #define DM9161_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation 00309 #define DM9161_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps 00310 #define DM9161_AUTONEG (1 << 12) // 1=Auto negotiation enabled. Bit8 and bit13 will be in auto negotiation Status. 00311 #define DM9161_POWER_DOWN (1 << 11) 00312 #define DM9161_ISOLATE (1 << 10) 00313 #define DM9161_RESTART_AUTONEG (1 << 9 ) 00314 #define DM9161_DUPLEX_MODE (1 << 8 ) 00315 #define DM9161_COLLISION_TEST (1 << 7 ) 00316 00317 //--Bit definitions: DM9161_BMSR 00318 #define DM9161_100BASE_T4 (1 << 15) 00319 #define DM9161_100BASE_TX_FD (1 << 14) 00320 #define DM9161_100BASE_TX_HD (1 << 13) 00321 #define DM9161_10BASE_T_FD (1 << 12) 00322 #define DM9161_10BASE_T_HD (1 << 11) 00323 #define DM9161_MF_PREAMB_SUPPR (1 << 6 ) 00324 #define DM9161_AUTONEG_COMP (1 << 5 ) 00325 #define DM9161_REMOTE_FAULT (1 << 4 ) 00326 #define DM9161_AUTONEG_ABILITY (1 << 3 ) 00327 #define DM9161_LINK_STATUS (1 << 2 ) 00328 #define DM9161_JABBER_DETECT (1 << 1 ) 00329 #define DM9161_EXTEND_CAPAB (1 << 0 ) 00330 00331 //--Bit definitions: DM9161_ANAR, DM9161_ANLPAR 00332 #define DM9161_NP (1 << 15) 00333 #define DM9161_ACK (1 << 14) 00334 #define DM9161_RF (1 << 13) 00335 #define DM9161_FCS (1 << 10) 00336 #define DM9161_T4 (1 << 9 ) 00337 #define DM9161_TX_FDX (1 << 8 ) 00338 #define DM9161_TX_HDX (1 << 7 ) 00339 #define DM9161_10_FDX (1 << 6 ) 00340 #define DM9161_10_HDX (1 << 5 ) 00341 #define DM9161_AN_IEEE_802_3 0x0001 00342 00343 //--Bit definitions: DM9161_ANER 00344 #define DM9161_PDF (1 << 4 ) 00345 #define DM9161_LP_NP_ABLE (1 << 3 ) 00346 #define DM9161_NP_ABLE (1 << 2 ) 00347 #define DM9161_PAGE_RX (1 << 1 ) 00348 #define DM9161_LP_AN_ABLE (1 << 0 ) 00349 00350 //--Bit definitions: DM9161_DSCR 00351 #define DM9161_BP4B5B (1 << 15) 00352 #define DM9161_BP_SCR (1 << 14) 00353 #define DM9161_BP_ALIGN (1 << 13) 00354 #define DM9161_BP_ADPOK (1 << 12) 00355 #define DM9161_REPEATER (1 << 11) 00356 #define DM9161_TX (1 << 10) 00357 #define DM9161_RMII_ENABLE (1 << 8 ) 00358 #define DM9161_F_LINK_100 (1 << 7 ) 00359 #define DM9161_SPLED_CTL (1 << 6 ) 00360 #define DM9161_COLLED_CTL (1 << 5 ) 00361 #define DM9161_RPDCTR_EN (1 << 4 ) 00362 #define DM9161_SM_RST (1 << 3 ) 00363 #define DM9161_MFP SC (1 << 2 ) 00364 #define DM9161_SLEEP (1 << 1 ) 00365 #define DM9161_RLOUT (1 << 0 ) 00366 00367 //--Bit definitions: DM9161_DSCSR 00368 #define DM9161_100FDX (1 << 15) 00369 #define DM9161_100HDX (1 << 14) 00370 #define DM9161_10FDX (1 << 13) 00371 #define DM9161_10HDX (1 << 12) 00372 00373 //--Bit definitions: DM9161_10BTCSR 00374 #define DM9161_LP_EN (1 << 14) 00375 #define DM9161_HBE (1 << 13) 00376 #define DM9161_SQUELCH (1 << 12) 00377 #define DM9161_JABEN (1 << 11) 00378 #define DM9161_10BT_SER (1 << 10) 00379 #define DM9161_POLR (1 << 0 ) 00380 00381 //--Bit definitions: DM9161_MDINTR 00382 #define DM9161_INTR_PEND (1 << 15) 00383 #define DM9161_FDX_MASK (1 << 11) 00384 #define DM9161_SPD_MASK (1 << 10) 00385 #define DM9161_LINK_MASK (1 << 9 ) 00386 #define DM9161_INTR_MASK (1 << 8 ) 00387 #define DM9161_FDX_CHANGE (1 << 4 ) 00388 #define DM9161_SPD_CHANGE (1 << 3 ) 00389 #define DM9161_LINK_CHANGE (1 << 2 ) 00390 #define DM9161_INTR_STATUS (1 << 0 ) 00391 00392 00393 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ 00394 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ 00395 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ 00396 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ 00397 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ 00398 00399 #define DM9161_DEF_ADR 0x1300 /* Default PHY device address DM9161 */ 00400 #define DM9161_ID 0x0181B8A0 /* DM9161 PHY Identifier */ 00401 00402 00403 00404 void Init_EthMAC(void); 00405 unsigned short ReadFrameBE_EthMAC(void); 00406 void CopyToFrame_EthMAC(void *Source, unsigned int Size); 00407 void CopyFromFrame_EthMAC(void *Dest, unsigned short Size); 00408 void DummyReadFrame_EthMAC(unsigned short Size); 00409 void RequestSend(unsigned short FrameSize); 00410 unsigned int Rdy4Tx(void); 00411 unsigned short StartReadingFrame(void); 00412 void StopReadingFrame(void); 00413 unsigned int CheckIfFrameReceived(void); 00414 00415 #endif 00416
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