Device Driver for RAMTRON FM25W256 SPI-driven FRAM Uses SPI peripheral at 10MHz Based on fast SPI routines
fm25w256.h
00001 #include "mbed.h" 00002 00003 //Shortcuts 00004 #define SSL1 LPC_GPIO0->FIOSET = BIT6 00005 #define SSL0 LPC_GPIO0->FIOCLR = BIT6 00006 00007 // Aliases for code readability 00008 #define BIT31 0x80000000 00009 #define BIT30 0x40000000 00010 #define BIT29 0x20000000 00011 #define BIT28 0x10000000 00012 #define BIT27 0x08000000 00013 #define BIT26 0x04000000 00014 #define BIT25 0x02000000 00015 #define BIT24 0x01000000 00016 #define BIT23 0x00800000 00017 #define BIT22 0x00400000 00018 #define BIT21 0x00200000 00019 #define BIT20 0x00100000 00020 #define BIT19 0x00080000 00021 #define BIT18 0x00040000 00022 #define BIT17 0x00020000 00023 #define BIT16 0x00010000 00024 #define BIT15 0x00008000 00025 #define BIT14 0x00004000 00026 #define BIT13 0x00002000 00027 #define BIT12 0x00001000 00028 #define BIT11 0x00000800 00029 #define BIT10 0x00000400 00030 #define BIT9 0x00000200 00031 #define BIT8 0x00000100 00032 #define BIT7 0x00000080 00033 #define BIT6 0x00000040 00034 #define BIT5 0x00000020 00035 #define BIT4 0x00000010 00036 #define BIT3 0x00000008 00037 #define BIT2 0x00000004 00038 #define BIT1 0x00000002 00039 #define BIT0 0x00000001 00040 00041 // FeRAM command defines 00042 #define WREN 0x06 // Write enable 00043 #define WRITE 0x02 // Write command 00044 #define READ 0x03 // Read command 00045 #define RDSR 0x05 // Read Status Register 00046 00047 00048 void FM25W_SSP1_Init (void); 00049 unsigned char FM25W_ReadByte (unsigned int iAddress); 00050 void FM25W_WriteByte (unsigned int iAddress, unsigned char cByte); 00051 void FM25W_WriteBlock(unsigned int iAddress, unsigned char *ptrBlock, unsigned int iCount); 00052 void FM25W_ReadBlock (unsigned int iAddress, unsigned char *ptrBlock, unsigned int iCount);
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