CDMS code for testing sbc

Dependencies:   FreescaleIAP SimpleDMA mbed-rtos mbed

Fork of CDMS_CODE by shubham c

Files at this revision

API Documentation at this revision

Comitter:
ee12b079
Date:
Sun Jul 10 13:47:26 2016 +0000
Parent:
243:29625f5fc745
Child:
246:565458eefd94
Commit message:
Making integrated code of CDMS

Changed in this revision

CDMS_HK.h Show annotated file Show diff for this revision Revisions of this file
CDMS_PL.h Show annotated file Show diff for this revision Revisions of this file
COM_MNG_TMTC.h Show annotated file Show diff for this revision Revisions of this file
DefinitionsAndGlobals.h Show annotated file Show diff for this revision Revisions of this file
FMS_all.h Show annotated file Show diff for this revision Revisions of this file
RESET_functions.h Show annotated file Show diff for this revision Revisions of this file
TEST_PL.h Show annotated file Show diff for this revision Revisions of this file
ThreadsAndFunctions.h Show annotated file Show diff for this revision Revisions of this file
adf.h Show annotated file Show diff for this revision Revisions of this file
cdms_rtc.h Show annotated file Show diff for this revision Revisions of this file
dmaSPIslave.h Show annotated file Show diff for this revision Revisions of this file
main.cpp Show annotated file Show diff for this revision Revisions of this file
--- a/CDMS_HK.h	Sat Jul 09 13:11:25 2016 +0000
+++ b/CDMS_HK.h	Sun Jul 10 13:47:26 2016 +0000
@@ -25,9 +25,12 @@
 
 void FCTN_CDMS_HK_MAIN(void const *args)
 {
+    while(1)
+    {
     gPC.printf("Entering HK thread");
+    gHK_THREAD->signal_wait(HK_SIGNAL);
     unsigned char CDMS_HK_FRAME[134] = {0};
-    char BAE_HK[128] = {0};
+    char BAE_HK[134] = {0};
     uint8_t convoluted_CDMS_HK[270];
     uint8_t interleave_CDMS_HK[288];
     uint8_t CDMS_HEALTH_FINAL[512] = {0};
@@ -92,38 +95,45 @@
         CDMS_HEALTH_FINAL[i] = interleave_CDMS_HK[i];
 
     SD_WRITE(CDMS_HEALTH_FINAL,FSC_CURRENT[4]+1,4);
-    gPC.printf("Completed CDMS HK\n");
+    gPC.printf("\rCompleted CDMS HK\n");
 
     /*---------------------------------- BAE HK --------------------------------------------*/
 
 
     BAE_HK_I2C = FCTN_I2C_READ(BAE_HK,134);
-    gPC.printf("Entering BAE thread\n");
+    gPC.printf("\rEntering BAE HK\n");
     if(BAE_HK_I2C == 0) {
-        TIME_LATEST_I2C_BAE = FCTN_CDMS_RD_RTC() >> 7;
+        crc = crc16_gen((unsigned char *)BAE_HK,132);
+        if(crc == ((uint16_t)BAE_HK[132] << 8) | (uint16_t)BAE_HK[133]){
+            TIME_LATEST_I2C_BAE = FCTN_CDMS_RD_RTC() >> 7;
+            for(int i = 0; i<15; i++)
+                gPC.printf("\r 0x%02X\n",BAE_HK[i]);
+            for(int i = 0; i<4; i++)
+            BAE_HK[i] = HK_time >> i;
+            BAE_HK_FRAME[0] = 0x28;
+            BAE_HK_FRAME[1] = FSC_CURRENT[5]+1;
+            BAE_HK_FRAME[2] = (FSC_CURRENT[5]+1) >> 8;
+            BAE_HK_FRAME[3] = (FSC_CURRENT[5]+1) >> 16;
+            for(int i = 0; i<128; i++)                       /*Adding actual CDMS Health data to TM frame*/
+                BAE_HK_FRAME[4+i] = BAE_HK[i];
+            crc = crc16_gen(BAE_HK_FRAME,132);               /*Adding CRC to TM frame*/
+            BAE_HK_FRAME[133] = crc;
+            BAE_HK_FRAME[132] = crc >> 8;
+            BAE_HEALTH.convolutionEncode(BAE_HK_FRAME , convoluted_BAE_HK);
+            BAE_HEALTH.convolutionEncode(BAE_HK_FRAME + 67, convoluted_BAE_HK + 135);
+            interleave(convoluted_BAE_HK ,  interleave_BAE_HK);
+            interleave(convoluted_BAE_HK +135, interleave_BAE_HK + 144);
+            for(int i=0; i<288; i++)
+                BAE_HEALTH_FINAL[i] = interleave_BAE_HK[i];
+            SD_WRITE(BAE_HEALTH_FINAL,FSC_CURRENT[5]+1,5);
+        }
+        
     } else {
-        for(int i = 0; i<128; i++)
+        gPC.printf("\rBAE HK data not recieved through I2C\n");
+        for(int i = 0; i<134; i++)
             BAE_HK[i] = 0;
     }
-    for(int i = 0; i<4; i++)
-        BAE_HK[i] = HK_time >> i;
-    BAE_HK_FRAME[0] = 0x28;
-    BAE_HK_FRAME[1] = FSC_CURRENT[5]+1;
-    BAE_HK_FRAME[2] = (FSC_CURRENT[5]+1) >> 8;
-    BAE_HK_FRAME[3] = (FSC_CURRENT[5]+1) >> 16;
-    for(int i = 0; i<128; i++)                       /*Adding actual CDMS Health data to TM frame*/
-        BAE_HK_FRAME[4+i] = BAE_HK[i];
-    crc = crc16_gen(BAE_HK_FRAME,132);               /*Adding CRC to TM frame*/
-    BAE_HK_FRAME[133] = crc;
-    BAE_HK_FRAME[132] = crc >> 8;
-    BAE_HEALTH.convolutionEncode(BAE_HK_FRAME , convoluted_BAE_HK);
-    BAE_HEALTH.convolutionEncode(BAE_HK_FRAME + 67, convoluted_BAE_HK + 135);
-    interleave(convoluted_BAE_HK ,  interleave_BAE_HK);
-    interleave(convoluted_BAE_HK +135, interleave_BAE_HK + 144);
-    for(int i=0; i<288; i++)
-        BAE_HEALTH_FINAL[i] = interleave_BAE_HK[i];
-    SD_WRITE(BAE_HEALTH_FINAL,FSC_CURRENT[5]+1,5);
-    gPC.printf("Completed BAE HK\n");
+    gPC.printf("\rCompleted BAE HK\n");
 
     /*----------------------------------Beacon message--------------------------------------*/
     unsigned char SC_HK_LBM_0[135];
@@ -135,7 +145,8 @@
     SC_HK_LBM_0[132] = crc;
     SC_HK_LBM_0[133] = crc >> 8;
     FCTN_I2C_WRITE((char *)SC_HK_LBM_0,135);
-    gPC.printf("Completed Beacon\n");
+    gPC.printf("\rCompleted Beacon\n");
+    }
 }
 
 int quantiz(float start,float step,float x)
@@ -261,7 +272,7 @@
     GPIO_STATUS=(PL_BEE_SW_OC_FAULT)?(GPIO_STATUS)||((uint16_t)(0x1<<5)):(GPIO_STATUS)&(~((uint16_t)(0x1<<5)));
     //PL_EPS_LATCH_SW_OC_FAULT // to be verified
     GPIO_STATUS=(PL_EPS_LATCH_SW_OC_FAULT)?(GPIO_STATUS)||((uint16_t)(0x1<<4)):(GPIO_STATUS)&(~((uint16_t)(0x1<<4)));
-
+    
 }
 
 void VERIFY_COMRX()
@@ -342,16 +353,35 @@
 void HANDLE_HW_FAULT_PL()
 {
     if(PL_STATUS != DEVICE_DISABLED) {
-        if(PL_STATUS == DEVICE_OC_FAULT)
-            PL_SW_EN_DS = 0; //Power ON PL
-
+        if(PL_STATUS == DEVICE_OC_FAULT){
+            PYLD_DFF_CLK = 0;
+            PYLD_DFF = 1;           // Switching ON PL
+            wait_us(1);
+            PYLD_DFF_CLK = 1;
+            wait_us(1);
+            PYLD_DFF_CLK = 0;
+            wait_us(1);         
+        }
         if(PL_BEE_SW_OC_FAULT == 0) { // if OC Fault
-            PL_SW_EN_DS = 1;  // switching OFF PL
+            PYLD_DFF_CLK = 0;     
+            PYLD_DFF = 0;             //Switching OFF PL
+            wait_us(1);
+            PYLD_DFF_CLK = 1;
+            wait_us(1);
+            PYLD_DFF_CLK = 0;
+            wait_us(1);
             PL_FAULTCOUNT++;
             PL_STATUS = (PL_FAULTCOUNT == 3)?DEVICE_DISABLED:DEVICE_OC_FAULT;
         } else {
-            if(PL_STATUS == DEVICE_OC_FAULT)
-                PL_SW_EN_DS = 0; //Switching OFF PL
+            if(PL_STATUS == DEVICE_OC_FAULT){
+                PYLD_DFF_CLK = 0;     
+                PYLD_DFF = 0;             //Switching OFF PL
+                wait_us(1);
+                PYLD_DFF_CLK = 1;
+                wait_us(1);
+                PYLD_DFF_CLK = 0;
+                wait_us(1);
+            }
             PL_STATUS = DEVICE_ENABLED;
             PL_FAULTCOUNT = 0;
         }
--- a/CDMS_PL.h	Sat Jul 09 13:11:25 2016 +0000
+++ b/CDMS_PL.h	Sun Jul 10 13:47:26 2016 +0000
@@ -29,10 +29,6 @@
 #define UNEXECUTED                  0x00000003      //also used as mask for EXEC_STATUS
 
 
-DigitalOut PYLD_DFF(PIN73);
-DigitalOut PYLD_DFF_CLK(PIN65);
-DigitalOut PYLD_EPS_DFF_PWR(PIN64);
-DigitalOut PYLD_EPS_DFF_PWR_CLK(PIN40);
 Base_tm* FCTN_CDMS_RLY_TMTC(Base_tc *tc_ptr);
 
 // waiting 1us for setup time,hold time and propagation delay
@@ -78,7 +74,14 @@
     tm_ptr_standby =  FCTN_CDMS_RLY_TMTC(pl_tc_standby);\
     VERIFY_TM(tm_ptr_standby);\
     delete pl_tc_standby;\
-    delete tm_ptr_standby;\
+    Base_tm *temp;\
+    temp = tm_ptr_standby;\
+    while(tm_ptr_standby!=NULL)\
+    {\
+        temp = temp->next_TM;\
+        delete tm_ptr_standby;\
+        tm_ptr_standby = temp;\        
+    }\
 }
 
 //TC_string[0] should not be 0x00
@@ -104,7 +107,14 @@
     tm_ptr_hibernate =  FCTN_CDMS_RLY_TMTC(pl_tc_hibernate);\
     VERIFY_TM(tm_ptr_hibernate);\
     delete pl_tc_hibernate;\
-    delete tm_ptr_hibernate;\
+    Base_tm *temp;\
+    temp = tm_ptr_hibernate;\
+    while(tm_ptr_hibernate!=NULL)\
+    {\
+        temp = temp->next_TM;\
+        delete tm_ptr_hibernate;\
+        tm_ptr_hibernate = temp;\        
+    }\
 }
 
 //TC_string[0] should not be 0x00
@@ -131,7 +141,14 @@
     tm_ptr_science =  FCTN_CDMS_RLY_TMTC(pl_tc_science);\
     VERIFY_TM(tm_ptr_science);\
     delete pl_tc_science;\
-    delete tm_ptr_science;\
+    Base_tm *temp;\
+    temp = tm_ptr_science;\
+    while(tm_ptr_science!=NULL)\
+    {\
+        temp = temp->next_TM;\
+        delete tm_ptr_science;\
+        tm_ptr_science = temp;\        
+    }\
 }
 void print_processed_block(uint8_t index)
 {
--- a/COM_MNG_TMTC.h	Sat Jul 09 13:11:25 2016 +0000
+++ b/COM_MNG_TMTC.h	Sun Jul 10 13:47:26 2016 +0000
@@ -1493,6 +1493,7 @@
         /*COM_POWER_OFF_TX;*/\
         reset_all;\
         /*PENDING : ENABLE THREADS*/\
+        gPAY_SPI->bulkRead_resume(&payload_isr_fun);\
         gSESSION_TIMEOUT.detach();\
         gFLAGS = gFLAGS & (~COM_MNG_TMTC_RUNNING_FLAG);\
         gFLAGS = gFLAGS & (~COM_SESSION_FLAG);\
--- a/DefinitionsAndGlobals.h	Sat Jul 09 13:11:25 2016 +0000
+++ b/DefinitionsAndGlobals.h	Sun Jul 10 13:47:26 2016 +0000
@@ -1,6 +1,6 @@
 // **************DEFINITIONS*********************
 
-#define bypass_adf 1
+#define bypass_adf 0
 
 // COM_RX
     #define RX_TIMEOUT_LIMIT 0.5
@@ -31,8 +31,8 @@
     DigitalOut PL_I2C_GPIO(PTC1);
             
 //I2C - CDMS to BAE
-    DigitalIn BAE_I2C_GPIO(PIN67);
-    DigitalOut CDMS_I2C_GPIO(PIN39);
+    DigitalIn BAE_I2C_GPIO(PIN67);//PTB21 from bae to cdms
+    DigitalOut CDMS_I2C_GPIO(PIN39);//PTA5 from cdms to bae 
 
 // TC LIST
     #define TCL_STATE_INCOMPLETE 0x00
@@ -67,7 +67,7 @@
     #define COM_MNG_TMTC_SIGNAL_UART_INT 0x01
     #define COM_MNG_TMTC_SIGNAL_ADF_NSD 0x02
     #define COM_MNG_TMTC_SIGNAL_ADF_SD 0x03
-    #define SCIENCE_SIGNAL 0x04
+    
 // COM_MNG_TMTC
     #define COM_PA_COOLING_TIME_LIMIT 20
     #define COM_MAX_TC_LIMIT 200
@@ -126,6 +126,7 @@
     #define PAY_SPI_MISO PTE19
     #define PAY_SPI_CLK PTE17
     #define PAY_SPI_CS PTE16
+    #define SCIENCE_SIGNAL 0x04
 
 //BEACON
     #define BCN_APID_SOURCE 0x41
@@ -143,6 +144,7 @@
     #define RF_RELAY_CNTRL_BCN PTA12 
     
 //CDMS HK
+#define HK_SIGNAL 0x04
 #define COMRX_ALIVE 0x01
 #define COMRX_DEAD 0x00
 #define DEVICE_ENABLED 0x00
@@ -214,14 +216,17 @@
 
 // PAYLOAD OR SCIENCE_THREAD
 Thread* gSCIENCE_THREAD = NULL;
-dmaSPISlave gPAY_SPI(PAY_SPI_MOSI, PAY_SPI_MISO, PAY_SPI_CLK, PAY_SPI_CS);
+dmaSPISlave *gPAY_SPI;
 uint8_t gPAYLOAD_BUFFER[PAYLOAD_BUFFER_LENGTH] = {0x00,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41,0x00,0x00,0x00,0x41};
-RtosTimer *PL_wo_dma;
 
 
 // CALL SIGN TM
 const uint8_t gCALL_SIGN_STRING[TM_SHORT_SIZE] = {0xE0, 0x00, 0x00, 0x00, 0x56, 0x55, 0x32, 0x4E, 0x43, 0x46, 0x00, 0xAC, 0x11};
 
+//HK Thread
+Thread* gHK_THREAD = NULL;
+RtosTimer *HK_counter;
+
 // CDMS HK
 uint8_t CDMS_STANDBY;
 uint8_t CDMS_HEALTH_DATA[128];
@@ -258,14 +263,22 @@
 DigitalIn PL_GPIO_3_STATUS (PIN80);
 DigitalIn PL_BEE_SW_OC_FAULT (PIN91);
 DigitalIn PL_EPS_LATCH_SW_OC_FAULT (PIN5);
-DigitalIn V_C_EN_STATUS (PIN72);
 DigitalIn V_D_EN_STATUS (PIN56);
 
 
 DigitalIn SD_OC_FAULT (PIN90);
 DigitalOut SD_SW_EN_DS (PIN97);
 DigitalOut BAE_SW_EN_DS (PIN47);
-DigitalOut PL_SW_EN_DS (PIN73);
+DigitalOut TRXY_PWR_CNTRL (PIN84);
+DigitalOut TRZ_PWR_CNTRL (PIN88);
+
+DigitalOut PYLD_DFF (PIN73);
+DigitalOut PYLD_DFF_CLK (PIN65);
+DigitalOut PYLD_EPS_DFF_PWR (PIN64);
+DigitalOut PYLD_EPS_DFF_PWR_CLK (PIN40);
+
+DigitalOut RESET_TO_BAE(PIN93,1);
+DigitalOut RESET_TO_PYLD(PIN21);
 
 //SD HK
 uint32_t FSC_CURRENT[6];
--- a/FMS_all.h	Sat Jul 09 13:11:25 2016 +0000
+++ b/FMS_all.h	Sun Jul 10 13:47:26 2016 +0000
@@ -1,12 +1,17 @@
 
+//Run processes
 void P_PL_INIT();
 void P_PL_MAIN();
 void P_COM_INIT();
 void P_CDMS_HK_MAIN();
 void P_PL_RCV_SC_DATA();
 void P_CDMS_INIT_SD();
+
+// Switch ON/OFF functions
 void CDMS_SD_SW_ON();
 void CDMS_SD_SW_OFF();
+void CDMS_RTC_ON();
+void CDMS_RTC_OFF();
 void SW_ON_BAE();
 void SW_OFF_BAE();
 void SW_ON_PL_BEE();
@@ -15,13 +20,24 @@
 void SW_OFF_PL_EPS();
 void SW_ON_V_A_EN();
 void SW_OFF_V_A_EN();
+
+// RST functions
 void RST_SD();
+void SW_RST_BAE();
+void SW_RST_PL_BEE();
 void RST_BAE();
 void RST_PL_BEE();
+void CDMS_INTERNAL_RESET();
+void SYS_PWR_RESET();  // Have to be decided with EPS team.
+void EPS_V_A_EN();
+void EPS_V_C_EN();
+
 void RST_HK_COUNTER();
 uint8_t CDMS_RD_SD_HK(uint8_t *);
+void CDMS_RD_RTC(uint64_t *);
+void CDMS_CALIB_RTC();
 void CDMS_RESET();
-void CDMS_INTERNAL_RESET();
+
 
 void P_PL_INIT()
 {
@@ -30,22 +46,22 @@
 
 void P_PL_MAIN()
 {
-    
+   // FCTN_CDMS_PL_MAIN((void *)NULL);
 }
 
 void P_COM_INIT()
 {
-    
+    P_COM_INIT;
 }
 
 void P_CDMS_HK_MAIN()
 {
-    //FCTN_CDMS_HK_MAIN();
+    FCTN_CDMS_HK_MAIN((void *)NULL);
 }
 
 void P_PL_RCV_SC_DATA()
 {
-
+    
 }
 
 void P_CDMS_INIT_SD()
@@ -55,74 +71,149 @@
 
 void CDMS_SD_SW_ON()
 {
-    SD_SW_EN_DS = 0; //powering on SD
+    SD_SW_EN_DS = 0;
 }
 
 void CDMS_SD_SW_OFF()
 {
-    SD_SW_EN_DS = 0; //powering on SD
-}
-
-void SW_ON_BAE()
-{
-    BAE_SW_EN_DS = 0; //Power ON BAE
+    SD_SW_EN_DS = 1;
 }
 
-void SW_OFF_BAE()
+void CDMS_RTC_ON()
 {
-    BAE_SW_EN_DS = 1; //Switch OFF BAE
+    
 }
 
-void SW_ON_PL_BEE()
-{
-    PL_SW_EN_DS = 0; //Power ON PL
-}
-
-void SW_OFF_PL_BEE()
-{
-      PL_SW_EN_DS = 1;  // switching OFF PL    
-}
-
-void SW_ON_PL_EPS()
+void CDMS_RTC_OFF()
 {
     
 }
 
+void SW_ON_BAE()
+{
+    BAE_SW_EN_DS = 0;
+}
+
+void SW_OFF_BAE()
+{
+    BAE_SW_EN_DS = 1;
+}
+
+void SW_ON_PL_BEE()
+{
+    PYLD_DFF_CLK = 0;\
+    PYLD_DFF = 1;\
+    wait_us(1);\
+    PYLD_DFF_CLK = 1;\
+    wait_us(1);\
+    PYLD_DFF_CLK = 0;\
+    wait_us(1);\
+}
+
+void SW_OFF_PL_BEE()
+{
+    PYLD_DFF_CLK = 0;
+    PYLD_DFF = 0;
+    wait_us(1);
+    PYLD_DFF_CLK = 1;
+    wait_us(1);
+    PYLD_DFF_CLK = 0;
+    wait_us(1);
+}
+
+void SW_ON_PL_EPS()
+{
+    PYLD_EPS_DFF_PWR_CLK = 0;\
+    PYLD_EPS_DFF_PWR = 1;\
+    wait_us(1);\
+    PYLD_EPS_DFF_PWR_CLK = 1;\
+    wait_us(1);\
+    PYLD_EPS_DFF_PWR_CLK = 0;\
+    wait_us(1);\
+}
+
 void SW_OFF_PL_EPS()
 {
-
+    PYLD_EPS_DFF_PWR_CLK = 0;\
+    PYLD_EPS_DFF_PWR = 0;\
+    wait_us(1);\
+    PYLD_EPS_DFF_PWR_CLK = 1;\
+    wait_us(1);\
+    PYLD_EPS_DFF_PWR_CLK = 0;\
+    wait_us(1);\
 }
 
 void SW_ON_V_A_EN()
 {
-    
+    TRXY_PWR_CNTRL = 1;
+    TRZ_PWR_CNTRL = 1;
 }
 
 void SW_OFF_V_A_EN()
 {
-
+    TRXY_PWR_CNTRL = 0;
+    TRZ_PWR_CNTRL = 0;    
 }
 
 void RST_SD()
 {
-    SD_SW_EN_DS = 1; //switching off SD card
+    SD_SW_EN_DS = 1;
     wait_ms(10);
     SD_SW_EN_DS = 0;
-    FCTN_CDMS_SD_INIT();
+}
+
+void SW_RST_BAE()
+{
+    BAE_SW_EN_DS = 1;
+    wait_ms(10);
+    BAE_SW_EN_DS = 0;
+}
+
+void SW_RST_PL_BEE()
+{
+    PYLD_DFF = 1;
+    wait_ms(10);
+    PYLD_DFF = 0;
 }
 
 void RST_BAE()
 {
-    BAE_SW_EN_DS = 1; //Switch OFF BAE
+    RESET_TO_BAE = 1;
     wait_ms(10);
-    BAE_SW_EN_DS = 0; //Switch ON BAE
+    RESET_TO_BAE = 0;
 }
 
 void RST_PL_BEE()
 {
-    PL_SW_EN_DS = 1;  // switching OFF PL
+    RESET_TO_PYLD = 1;
     wait_ms(10);
-    PL_SW_EN_DS = 0;  // Switch ON PL
+    RESET_TO_PYLD = 0;
+}
+
+void CDMS_INTERNAL_RESET()
+{
+    NVIC_SystemReset();
+}
+
+void SYS_PWR_RESET()  // Have to be decided with EPS team.
+{
+    
+}
+
+void EPS_V_A_EN()     // This is a reset function
+{
+    TRXY_PWR_CNTRL = 0;
+    TRZ_PWR_CNTRL = 0;
+    wait_ms(10);
+    TRXY_PWR_CNTRL = 1;
+    TRZ_PWR_CNTRL = 1;
+}
+
+void EPS_V_C_EN()     // This is a reset function
+{
+    COM_RX_CNTRL = 0;
+    wait_ms(10);
+    COM_RX_CNTRL = 1;
 }
 
 void RST_HK_COUNTER()
@@ -151,12 +242,24 @@
     return ACK;
 }
 
+void CDMS_RD_RTC(uint64_t *time)
+{
+    *time = FCTN_CDMS_RD_RTC();
+}
+
+void CDMS_CALIB_RTC()
+{
+    
+}
+
 void CDMS_RESET()
 {
     NVIC_SystemReset();    
 }
 
-void CDMS_INTERNAL_RESET()
+/*
+//void CDMS_INTERNAL_RESET()
 {
     
-}
\ No newline at end of file
+}
+*/
\ No newline at end of file
--- a/RESET_functions.h	Sat Jul 09 13:11:25 2016 +0000
+++ b/RESET_functions.h	Sun Jul 10 13:47:26 2016 +0000
@@ -1,13 +1,12 @@
-DigitalOut pwr_comrx (PIN72);
 
 void RESET_COMRX();
 void RESET_RTC();
 
 void RESET_COMRX()
 {
-    pwr_comrx = 0;
+    COM_RX_CNTRL = 0;
     wait_ms(10);
-    pwr_comrx =1;
+    COM_RX_CNTRL =1;
 }
 
 void RESET_RTC()
--- a/TEST_PL.h	Sat Jul 09 13:11:25 2016 +0000
+++ b/TEST_PL.h	Sun Jul 10 13:47:26 2016 +0000
@@ -12,34 +12,34 @@
                         {
                             {0,1,1,0,0,15,3,3},
                             {0,1,1,0,0,45,2,3},
-                            {0,1,1,0,1,00,1,3},
+                            {0,1,1,0,1,0,1,3},
                             {0,1,1,0,1,25,0,3},     
-                            {0,1,1,0,2,10,3,3},
-                            {0,1,1,0,1,50,2,3},
-                            {0,1,1,0,2, 0,2,3},
+                            {0,1,1,0,1,50,3,3},
                             {0,1,1,0,2,10,2,3},
-                            {0,1,1,0,2,20,2,0},
-                            {0,1,1,0,2,30,2,3},
+                            {0,1,1,0,1,40,2,3},
+                            {0,1,1,0,1,10,2,3},
+                            {0,1,1,0,3,40,2,0},
+                            {0,1,1,0,4,10,2,3},
                             
-                            {0,1,1,0,2,50,0,1},
-                            {0,1,1,0,4,10,3,3},
-                            {0,1,1,0,5,30,3,3},
-                            {0,1,1,0,4,15,2,3},
-                            {0,1,1,0,4,10,1,0},
-                            {0,1,1,0,3,10,2,3},
-                            {0,1,1,0,4,10,3,3},
-                            {0,1,1,0,5,10,0,3},
-                            {0,1,1,0,6,10,1,3},
-                            {0,1,1,0,6,20,1,2},                           
+                            {0,1,1,0,4,40,0,1},
+                            {0,1,1,0,5,10,3,3},
+                            {0,1,1,0,5,40,3,3},
+                            {0,1,1,0,6,10,2,3},
+                            {0,1,1,0,6,40,1,0},
+                            {0,1,1,0,7,10,2,3},
+                            {0,1,1,0,7,40,3,3},
+                            {0,1,1,0,8,10,0,3},
+                            {0,1,1,0,8,40,1,3},
+                            {0,1,1,0,9,10,1,2},                           
 
-                            {0,1,1,0,1,40,2,3},
-                            {0,1,1,0,1,20,3,1},
-                            {0,1,1,0,1,30,3,3},                         
-                            {0,1,1,0,1,10,2,1},
-                            {0,1,1,0,0, 0,0,0},
-                            {0,1,1,0,0, 0,0,0},
-                            {0,1,1,0,0, 0,0,0},
-                            {0,1,1,0,0, 0,0,0},
+                            {0,1,1,0,9,40,2,3},
+                            {0,1,1,0,10,10,3,1},
+                            {0,1,1,0,10,40,3,3},                         
+                            {0,1,1,0,11,10,2,1},
+                            {0,0,0,0,11,40,0,0},
+                            {0,1,1,0,12,10,0,0},
+                            {0,1,1,0,12,40,0,0},
+                            {0,1,1,0,13, 0,0,0},
                             {0,1,1,0,0, 0,0,0},
                             {0,1,1,0,0, 0,0,0},
 
@@ -233,6 +233,15 @@
     test_tc->TC_string[133] = (uint8_t)(crc16 & 0xFF00)>>8;\
     test_tc->TC_string[134] = (uint8_t)(crc16 & 0x00FF);\
     test_tm_ptr =  FCTN_CDMS_RLY_TMTC(test_tc);\
+    delete test_tc;\
+    Base_tm *temp;\
+    temp = test_tm_ptr;\
+    while(test_tm_ptr!=NULL)\
+    {\
+        temp = temp->next_TM;\
+        delete test_tm_ptr;\
+        test_tm_ptr = temp;\        
+    }\
 }
 #define test_schedule_2(test_tm_ptr) {\
     Base_tc *test_tc = new Long_tc;\
@@ -247,6 +256,15 @@
     test_tc->TC_string[133] = (uint8_t)(crc16 & 0xFF00)>>8;\
     test_tc->TC_string[134] = (uint8_t)(crc16 & 0x00FF);\
     test_tm_ptr =  FCTN_CDMS_RLY_TMTC(test_tc);\
+    delete test_tc;\
+    Base_tm *temp;\
+    temp = test_tm_ptr;\
+    while(test_tm_ptr!=NULL)\
+    {\
+        temp = temp->next_TM;\
+        delete test_tm_ptr;\
+        test_tm_ptr = temp;\        
+    }\
 }
 #define test_schedule_3(test_tm_ptr) {\
     Base_tc *test_tc = new Long_tc;\
@@ -261,6 +279,15 @@
     test_tc->TC_string[133] = (uint8_t)(crc16 & 0xFF00)>>8;\
     test_tc->TC_string[134] = (uint8_t)(crc16 & 0x00FF);\
     test_tm_ptr =  FCTN_CDMS_RLY_TMTC(test_tc);\
+    delete test_tc;\
+    Base_tm *temp;\
+    temp = test_tm_ptr;\
+    while(test_tm_ptr!=NULL)\
+    {\
+        temp = temp->next_TM;\
+        delete test_tm_ptr;\
+        test_tm_ptr = temp;\        
+    }\
 }
 #define test_schedule_4(test_tm_ptr) {\
     Base_tc *test_tc = new Long_tc;\
@@ -275,6 +302,15 @@
     test_tc->TC_string[133] = (uint8_t)(crc16 & 0xFF00)>>8;\
     test_tc->TC_string[134] = (uint8_t)(crc16 & 0x00FF);\
     test_tm_ptr =  FCTN_CDMS_RLY_TMTC(test_tc);\
+    delete test_tc;\
+    Base_tm *temp;\
+    temp = test_tm_ptr;\
+    while(test_tm_ptr!=NULL)\
+    {\
+        temp = temp->next_TM;\
+        delete test_tm_ptr;\
+        test_tm_ptr = temp;\        
+    }\
 }
 #define test_schedule_5(test_tm_ptr) {\
     Base_tc *test_tc = new Long_tc;\
@@ -289,6 +325,15 @@
     test_tc->TC_string[133] = (uint8_t)(crc16 & 0xFF00)>>8;\
     test_tc->TC_string[134] = (uint8_t)(crc16 & 0x00FF);\
     test_tm_ptr =  FCTN_CDMS_RLY_TMTC(test_tc);\
+    delete test_tc;\
+    Base_tm *temp;\
+    temp = test_tm_ptr;\
+    while(test_tm_ptr!=NULL)\
+    {\
+        temp = temp->next_TM;\
+        delete test_tm_ptr;\
+        test_tm_ptr = temp;\        
+    }\
 }
 #define test_schedule_6(test_tm_ptr) {\
     Base_tc *test_tc = new Long_tc;\
@@ -303,6 +348,15 @@
     test_tc->TC_string[133] = (uint8_t)(crc16 & 0xFF00)>>8;\
     test_tc->TC_string[134] = (uint8_t)(crc16 & 0x00FF);\
     test_tm_ptr =  FCTN_CDMS_RLY_TMTC(test_tc);\
+    delete test_tc;\
+    Base_tm *temp;\
+    temp = test_tm_ptr;\
+    while(test_tm_ptr!=NULL)\
+    {\
+        temp = temp->next_TM;\
+        delete test_tm_ptr;\
+        test_tm_ptr = temp;\        
+    }\
 }
 #define test_schedule_F(test_tm_ptr) {\
     Base_tc *test_tc = NULL;\
@@ -323,6 +377,7 @@
     test_tc->TC_string[133] = (uint8_t)(crc16 & 0xFF00)>>8;\
     test_tc->TC_string[134] = (uint8_t)(crc16 & 0x00FF);\
     test_tm_ptr =  FCTN_CDMS_RLY_TMTC(test_tc);\
+    delete test_tc;\
 }
 void send_verify_0xF(Base_tm* test_tm_ptr)
 {
@@ -330,8 +385,8 @@
     uint8_t j=0,tm_data_err_count=0;
     Base_tm* temp_ptr;
     test_schedule_F(test_tm_ptr);
-    //gPC.printf("\n\r----------------------------------------------------------------------------------");
-    //gPC.printf("\n\rTC_Schedule_Report(0xF):\n");
+    gPC.printf("\n\r----------------------------------------------------------------------------------");
+    gPC.printf("\n\rTC_Schedule_Report(0xF):\n");
     temp_ptr=test_tm_ptr;
     while(temp_ptr!=NULL)
     {
@@ -389,7 +444,15 @@
     {
         gPC.printf("\n\rNo errors in TM Data(0xF)");
     }
-    //gPC.printf("\n\r----------------------------------------------------------------------------------");
+    gPC.printf("\n\r----------------------------------------------------------------------------------");
+    Base_tm *temp;\
+    temp = test_tm_ptr;\
+    while(test_tm_ptr!=NULL)\
+    {\
+        temp = temp->next_TM;\
+        delete test_tm_ptr;\
+        test_tm_ptr = temp;\        
+    }\
 }
 void verify_extracted(uint8_t c)
 {
@@ -423,20 +486,19 @@
 }
 void test_pl_main()
 {
-    //uint32_t temp_pl_block[192] = {0};
+    uint32_t temp_pl_block[192] = {0};
     uint8_t wrong_modify=0,z;
     Base_tm* test_tm_ptr;    
-    //Base_tm* temp;
-    //for(z=0;z<192;z++)
-    //    pl_block[z] = 0xFFFFFFFF;
-    //testing 0xF
+    for(z=0;z<192;z++)
+        pl_block[z] = 0xFFFFFFFF;
+   // testing 0xF
     send_verify_0xF(test_tm_ptr);
-    //for(z=0;z<192;z++)  
-    //    temp_pl_block[z] = pl_block[z];
+    for(z=0;z<192;z++)  
+        temp_pl_block[z] = pl_block[z];
         
     //testing TC = 0x1,0x2...0x6
-    uint8_t w =1;
-    for(uint8_t v=1;w<7;w++)
+    int w =1;
+    for(uint8_t v=1;w<1000;w++)
     {        
         /*switch(v)
         {
@@ -453,6 +515,7 @@
             case 6: test_schedule_6(test_tm_ptr);
                     break;
         }*/
+        gPC.printf("\n\rIndex:%d",w);
         if(v==1)
         {
             test_schedule_1(test_tm_ptr);
@@ -477,7 +540,7 @@
         {
             test_schedule_6(test_tm_ptr);
         }
-        /*for(z=0;z<192;z++)
+        for(z=0;z<192;z++)
         {
             if((z>=((v-1)*32)) && (z<=((v*32)-1)))
                 z++;
@@ -501,12 +564,12 @@
                 //gPC.printf("\n\r%03d-0x%08X\t%03d-0x%08X",(i),pl_block[i],(i)+1,pl_block[(i)+1]);
                 //gPC.printf("\t%03d-0x%08X\t%03d-0x%08X\n",(i)+2,pl_block[(i)+2],(i)+3,pl_block[(i)+3]);
             }
-        }*/
+        }
         send_verify_0xF(test_tm_ptr);
         verify_extracted(v);
-        //for(z=0;z<192;z++)
-        //    temp_pl_block[z] = pl_block[z];
-        wait(1);
+        for(z=0;z<192;z++)
+            temp_pl_block[z] = pl_block[z];
+        //wait(1);
     }
     gPC.printf("\n\rTesting TC_TM block processing complete");
 }
\ No newline at end of file
--- a/ThreadsAndFunctions.h	Sat Jul 09 13:11:25 2016 +0000
+++ b/ThreadsAndFunctions.h	Sun Jul 10 13:47:26 2016 +0000
@@ -9,25 +9,29 @@
 }
 
 void SCIENCE_FUN(void const *args){
-    
-    // initialisation of payload spi
-    gPAY_SPI.frequency(1000000);
-    gPAY_SPI.format(8,0);
-    gPAY_SPI.bulkRead_init(gPAYLOAD_BUFFER, PAYLOAD_BUFFER_LENGTH, &payload_isr_fun);
-    gPAY_SPI.bulkRead_start();
-    
+    gPAY_SPI = new dmaSPISlave(PAY_SPI_MOSI, PAY_SPI_MISO, PAY_SPI_CLK, PAY_SPI_CS);
+    gPAY_SPI->frequency(1000000);
+    gPAY_SPI->format(8,0);
+    gPAY_SPI->bulkRead_init(gPAYLOAD_BUFFER, PAYLOAD_BUFFER_LENGTH, &payload_isr_fun);
+    gPAY_SPI->bulkRead_start();
     while(true){
         gPC.puts("entering sci\r\n");
         gSCIENCE_THREAD->signal_wait(SCIENCE_SIGNAL);
-        PL_wo_dma->stop();//
         gPC.puts("sig_set\r\n");
         srp(gPAYLOAD_BUFFER);
         gPC.puts("exit_srp\r\n");
-        //gPAY_SPI.bulkRead_start();
-        
+        wait(2);/*timeout to be decided*/
+        gPAY_SPI->bulkRead_start();
     }
 }
 
+//HK Thread(Contains HK_main() and PL_main())
+//RTOS timer calllback func
+void hk_isr(void const *args){
+    gSCIENCE_THREAD->signal_set(SCIENCE_SIGNAL);
+}
+
+
 //COM THREAD
 // UART ISR
 void rx_read(){
@@ -110,7 +114,7 @@
             gFLAGS = gFLAGS & (~UART_INT_FLAG);
             if( !(gFLAGS & COM_SESSION_FLAG) ){
                 // PENDING : DISABLE THREADS
-                PL_wo_dma->stop();
+                gPAY_SPI->bulkRead_pause();
                 gFLAGS = gFLAGS | COM_SESSION_FLAG;
                 gSESSION_TIMEOUT.attach(&after_session, SESSION_TIME_LIMIT);
                 gFLAGS = gFLAGS | COM_RX_FLAG;
@@ -194,7 +198,7 @@
                             reset_all;
                             gFLAGS = gFLAGS & (~COM_SESSION_VALIDITY);
                             // PENDING : ENABLE THREADS
-                            /*PL_wo_dma->start(6000);*/
+                            gPAY_SPI->bulkRead_resume(&payload_isr_fun);
                             gSESSION_TIMEOUT.detach();
                             gFLAGS = gFLAGS & (~COM_SESSION_FLAG);
                             // WARNING: clear COM_MNG_TMTC ?
@@ -247,7 +251,7 @@
                 gFLAGS = gFLAGS & (~COM_MNG_TMTC_RUNNING_FLAG);
                 reset_all;
                 // PENDING : ENABLE THREADS
-                /*PL_wo_dma->start(6000);*/
+                gPAY_SPI->bulkRead_resume(&payload_isr_fun);
                 gSESSION_TIMEOUT.detach();
                 gFLAGS = gFLAGS & (~COM_SESSION_FLAG);
             }
@@ -287,7 +291,7 @@
             /*gPC.puts("session timeout: resetting in main\r\n");*/
             COM_POWER_OFF_TX;
             /*PENDING : ENABLE THREADS*/
-            
+            gPAY_SPI->bulkRead_resume(&payload_isr_fun);
             gSESSION_TIMEOUT.detach();
             gFLAGS = gFLAGS & (~COM_MNG_TMTC_RUNNING_FLAG);
             gFLAGS = gFLAGS & (~COM_SESSION_FLAG);
@@ -299,7 +303,7 @@
             COM_POWER_OFF_TX;
             reset_all;
             // PENDING : ENABLE THREADS
-            /*PL_wo_dma->start(6000);*/
+            gPAY_SPI->bulkRead_resume(&payload_isr_fun);
             gSESSION_TIMEOUT.detach();
             gFLAGS = gFLAGS & (~COM_SESSION_FLAG);
         }
--- a/adf.h	Sat Jul 09 13:11:25 2016 +0000
+++ b/adf.h	Sun Jul 10 13:47:26 2016 +0000
@@ -7,29 +7,38 @@
 bool buffer_state;
 bool finish_write_data;
 uint8_t signal = 0x00;
-unsigned char bbram_buffer[66]={0x19,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0xF4,0xC2,0x10,0xC0,0x00,0x30,0x31,0x07,0x00,0x01,0x00,0x7F,0x00,0x0B,0x37,0x00,0x00,0x40,0x0C,0x00,0x05,0x00,0x00,0x18,0x12,0x34,0x56,0x10,0x10,0xC4,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00};
+unsigned char bbram_buffer[66]={0x19,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0xF4,0xC2,0x10,0xC0,0x00,0x30,0x31,0x07,0x00,0x01,0x00,0x7F,0x00,0x0B,0x37,0x00,0x00,0x40,0x0C,0x00,0x05,0x00,0x00,0x18,0x12,0x34,0x56,0x20,0x10,0xC4,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0xE0,0x00,0x10,0x04,0x00,0x00,0x00,0x00,0x00};
+bool data_irq_err=0;
+bool data_err= false;
+unsigned char temp_byte=0x00;
+unsigned char data_err1[112];
+unsigned char data_err_cnt=0;
+unsigned int byte_count =0;
+#define DATA_ERR_THRS 20
+bool rolling_buffer_settings_error=true;
+bool bbram_write_success=true;
+int bbram_err_cnt=0;
+int rbp_err_cnt=0;
+bool reset_flag=false;
+#define RBP_THRS 4
+bool quit_configuration=false;
+bool power_reset_flag=false;
+unsigned int power_reset_count=0;
+bool Configuration_done=false;
+#define HW_THRS 2
  
 //int initialise_card();
 //int disk_initialize();
- 
-#define bbram_write {\
-     SPI_mutex.lock();\
-    gCS_ADF=0;\
-    spi.write(0xB0);\
-    wait_us(300);\
-    gCS_ADF=1;\
-    gCS_ADF=0;\
-    for(int i=0;i<66;i++){\
-        spi.write(bbram_buffer[i]);\
-    }\
-    gCS_ADF=1;\
-    SPI_mutex.unlock();\
-}
 //------------------------------------------------------------------------
 // state checking functions
 //bool assrt_phy_off( int, int, int);
 //bool assrt_phy_on( int,int,int);
 //bool assrt_phy_tx(int,int,int);
+
+#define TRANSMIT_LEN_1 0xFF
+#define TRANSMIT_LEN_2 0xFF
+/***/
+Timer T;
  
 #define START_ADDRESS 0x020;
 #define MISO_PIN PTE3
@@ -45,7 +54,105 @@
 #define CMD_PHY_OFF 0xB0
 #define CMD_PHY_TX 0xB5
 #define CMD_CONFIG_DEV 0xBB
+/**STATES**/
+//=======================
+#define PHY_OFF 0xB1
+#define PHY_ON 0xB2
+#define PHY_TX 0xB4
+#define BUSY 0x00
+//===================================================
+
+unsigned int Adf_data_counter=0;
+unsigned char status =0;
+unsigned int cmd_err_cnt=0;
+unsigned int data_length;
+unsigned int state_err_cnt=0;
+unsigned int miso_err_cnt=0;
+unsigned int hw_reset_err_cnt=0;
+unsigned int counter =0;
+bool temp_return = 0;
+bool bcn_flag=0;
+bool bbram_flag=0;
+
+bool stop_transmission=false;
+
+#define reset_flags {\
+finish_write_data = false;\
+buffer_state = true;\
+last_buffer = false;\
+loop_on = true;\
+ADF_off = false;\
+buffer_state = true;\
+loop_on = true;\
+ADF_off = false;\
+sent_tmfrom_SDcard = false;\
+Adf_data_counter=0;\
+status =0;\
+cmd_err_cnt=0;\
+data_length;\
+state_err_cnt=0;\
+miso_err_cnt=0;\
+hw_reset_err_cnt=0;\
+counter =0;\
+bcn_flag=0;\
+bbram_flag=0;\
+stop_transmission=false;\
+    }
+
+
+int err_arr[64];
+bool bbram_err=false;
+int err_idx=-1;
+int err[64];
+#define bbram_check gCS_ADF=0;\
+    for(int i=0;i<64;i++){\
+        err_arr[i]=0;\
+        }\
+    for(int i=0;i<64;i++){\
+        err[i]=0;\
+        }\
+    bbram_err=false;\
+    gCS_ADF=0;\
+    spi.write(0x39);\
+    spi.write(0x00);\
+    spi.write(0xFF);\
+    for(int i=0;i<64;i++){\
+        err_arr[i]=spi.write(0xFF);\
+        if(err_arr[i]!=bbram_buffer[i+2]){\
+            err[i]=1;\
+            bbram_err=true;\
+            }\
+    }\
+    gCS_ADF=1;\
+    if(!bbram_err)\
+        gPC.printf("BBRAM verified \r\n");\
+    else\
+        gPC.printf("BBRAM error \r\n");\
  
+
+bool tx_loop=1;
+
+#define PRNT_ONCE {\
+    gPC.printf("%d %d lol_ what?\r\n",segment_len,EOS_len);\
+    }
+ 
+#define bbram_write {\
+    gCS_ADF=0;\
+    spi.write(0xB0);\
+    wait_us(300);\
+    gCS_ADF=1;\
+    gCS_ADF=0;\
+    for(int i=0;i<66;i++){\
+        spi.write(bbram_buffer[i]);\
+    }\
+    gCS_ADF=1;\
+}
+//------------------------------------------------------------------------
+// state checking functions
+//bool assrt_phy_off( int, int, int);
+//bool assrt_phy_on( int,int,int);
+//bool assrt_phy_tx(int,int,int);
+
 #define check_status {\
     unsigned char stat=0;\
     gCS_ADF=0;\
@@ -54,97 +161,106 @@
     gCS_ADF=1;\
     status = stat;\
 }
- 
-// all three arguments are int
-#define assrt_phy_off(return_this) {\
-    int cmd_err_cnt = 0;\
-    int spi_err_cnt = 0;\
-    int state_err_cnt = 0;\
-    for(int i = 0 ; i < 40 ;i++){\
+
+/*CMD_VAR*/
+bool cmd_bit=true;
+bool cmd_err_flag=false;
+unsigned char command = 0x00;
+#define CMD(command) {\
+    cmd_err_cnt=0;\
+    cmd_err_flag=false;\
+    while(cmd_err_cnt<3) {\
         check_status;\
-        if(status == 0xB1){\
-            return_this = 0;\
+        cmd_bit=status&0x20;\
+        if(cmd_bit) {\
+            gCS_ADF=0;\
+            spi.write(command);\
+            gCS_ADF=1;\
             break;\
-        }\
-        else if(cmd_err_cnt>THRS||spi_err_cnt>THRS){\
-            return_this = 1;\
-            break;\
+        } else {\
+            wait_us(5);\
+            cmd_err_cnt++;\
         }\
-        else if(state_err_cnt>STATE_ERR_THRS){\
-            return_this = 1;\
-            break;\
+    }\
+    if(cmd_err_cnt==3) {\
+        cmd_err_flag=true;\
+    }\
+}
+// all three arguments are int\
+#define assrt_phy_off {\
+    int state_err_cnt = 0;\
+    CMD(CMD_PHY_OFF);\
+    if(cmd_err_flag){\
+        temp_return=1;\
         }\
-        else if( (status & 0xA0) == 0xA0 ){\
-            gCS_ADF=0;\
-            spi.write(CMD_PHY_OFF);\
-            gCS_ADF=1;\
-            wait_us(PHY_OFF_EXEC_TIME);\
-            state_err_cnt++;\
-        }\
-        else if(status&0x80==0x00){\
-            wait_ms(5);\
-            spi_err_cnt++;\
-        }\
-        else {\
-            wait_ms(1);\
-            cmd_err_cnt++;\
+    else{\
+        for(int i = 0 ; i < 40 ;i++){\
+            CMD(CMD_PHY_OFF);\
+            check_status;\
+            if(status == PHY_OFF){\
+                temp_return = 0;\
+            break;\
+            }\
+            else if(state_err_cnt>THRS){\
+                temp_return = 1;\
+            break;\
+            }\
+            else {\
+                wait_ms(1);\
+            }\
         }\
     }\
 }
- 
- 
-#define initial_adf_check {\
-    spi.write(CMD_PHY_OFF);\
-    int tempReturn = 0;\
-    bool flag = false;\
-    while( hw_reset_err_cnt < 2 ){\
-        assrt_phy_off( tempReturn);\
-        if( !tempReturn ){\
-            bbram_write;\
-            bbram_flag=1;\
-            flag = true;\
-            break;\
-        }\
-        else{\
-            hardware_reset(0);\
-            hw_reset_err_cnt++;\
-            gPC.puts("Resetting hardware\r\n");\
-        }\
-    }\
-    if( flag == false ){\
-        gPC.puts("Seems to be SPI problem\r\n");\
-    }\
-    assrt_phy_off(tempReturn);\
-    if(!bbram_flag){\
-        bcn_flag=1;\
-     }\
-}
- 
-unsigned char status =0;
-unsigned int cmd_err_cnt=0;
-unsigned int state_err_cnt=0;
-unsigned int miso_err_cnt=0;
-unsigned int hw_reset_err_cnt=0;
-bool bcn_flag=0;
-bool bbram_flag=0;
- 
-bool hardware_reset(int bcn_call){
-    for(int i= 0; i < 20 ; i++){
+
+
+bool hardware_reset(int bcn_call)
+{
+    for(int i= 0; i < 2 ; i++) {
         gCS_ADF=0;
         spi.write(CMD_HW_RESET);
         gCS_ADF=1;
         wait_ms(2);// Typically 1 ms
         int count=0;
-        int temp_return = 0;
-        while(count<10 && miso_err_cnt<10){      
-            if(MISO_PIN){
-                assrt_phy_off(temp_return);
+        temp_return = 0;
+        while(count<10 && miso_err_cnt<10) {
+            if(MISO_PIN) {
+//                assrt_phy_off;
+/*asseert_phyoff Starts**/
+{\
+    int state_err_cnt = 0;\
+    CMD(CMD_PHY_OFF);\
+    if(cmd_err_flag){\
+        temp_return=1;\
+        }\
+    else{\
+        for(int i = 0 ; i < 40 ;i++){\
+            CMD(CMD_PHY_OFF);\
+            check_status;\
+            if(status == PHY_OFF){\
+                temp_return = 0;\
+            break;\
+            }\
+            else if(state_err_cnt>THRS){\
+                temp_return = 1;\
+            break;\
+            }\
+            else {\
+                wait_ms(1);\
+            }\
+        }\
+    }\
+}\
+/*Assert_phy_off_ends*/
+
+
+
+
+
                 if(!temp_return){
                     return 0;
                 }
                 count++;
-            }
-            else{
+            } else {
                 wait_us(50);
                 miso_err_cnt++;
             }
@@ -152,46 +268,158 @@
     }
     return 1;
 }
- 
-//for reseting the transmission call assert function after b5 and b1. after b1 assert_phi_on and after b5 assert_phi_tx. 
+//for reseting the transmission call assert function after b5 and b1. after b1 assert_phi_on and after b5 assert_phi_tx.
 //----------------------------------------------------------------------------
- 
-# define initiate {\
-    SPI_mutex.lock();\
+unsigned char temp;
+bool reg_err;
+int reg_err_cnt;
+#define REG_ERR_THRS 5
+#define reg_check(addr1,addr2,reg_val){\
+ gCS_ADF=0;\
+        reg_err=false;\
+        spi.write(addr1);\
+        spi.write(addr2);\
+        spi.write(0xFF);\
+        temp = spi.write(0xFF);\
+        if(temp==reg_val)\
+            reg_err = false;\
+        else\
+            reg_err=true;\
+    gCS_ADF=1;\
+}
+
+#define initiate {\
     gCS_ADF=0;\
     spi.write(0xFF);\
     spi.write(0xFF);\
     gCS_ADF=1;\
-    gCS_ADF=0;\
-    spi.write(0x08);\
-    spi.write(0x14);\
-    spi.write(0xFF);\
-    gCS_ADF=1;\
+    reg_err=true;\
+    for(reg_err_cnt=0;reg_err_cnt<REG_ERR_THRS && reg_err;reg_err_cnt++){\
+        gCS_ADF=0;\
+        spi.write(0x08);\
+        spi.write(0x14);\
+        spi.write(TRANSMIT_LEN_1);\
+        gCS_ADF=1;\
+        reg_check(0x28,0x14,TRANSMIT_LEN_1);\
+    }\
+    if(reg_err)\
+        gPC.printf("Reg_err_ignored %x \r\n",(int)temp);\
+    else\
+        gPC.printf("reg written successful %x \r\n",(int)temp);\
+    reg_err=true;\
+    for(reg_err_cnt=0;reg_err_cnt<REG_ERR_THRS && reg_err;reg_err_cnt++){\
+        gCS_ADF=0;\
+        spi.write(0x08);\
+        spi.write(0x15);\
+        spi.write(TRANSMIT_LEN_2);\
+        gCS_ADF=1;\
+        reg_check(0x28,0x15,TRANSMIT_LEN_2);\
+    }\
+    if(reg_err)\
+        gPC.printf("Reg_err_ignored %x \r\n",(int)temp);\
+    else\
+        gPC.printf("reg written successful %x \r\n",(int)temp);\
+}
+
+#define write_data {\
+    counter++;\
     gCS_ADF=0;\
-    spi.write(0x08);\
-    spi.write(0x15);\
-    spi.write(0xFF);\
-    gCS_ADF=1;\
-    gCS_ADF=0;\
-    spi.write(0x09);\
-    spi.write(0x24);\
-    spi.write(0x20);\
+        spi.write(0x0B);\
+        spi.write(0x36);\
+        spi.write(0xFF);\
     gCS_ADF=1;\
-    gCS_ADF=0;\
-    spi.write(0x09);\
-    spi.write(0x37);\
-    spi.write(0xE0);\
+    data_err_cnt=0;\
+    data_err=true;\
+    while(data_err && (data_err_cnt<DATA_ERR_THRS)){\
+        gCS_ADF=0;\
+        if(buffer_state){\
+            spi.write(0x18);\
+            spi.write(0x20);\
+            for(unsigned char i=0; i<112;i++){\
+                if(bypass_adf)\
+                    gPC.putc(buffer_112[i]);\
+                else\
+                    spi.write(buffer_112[i]);\
+                    /*gPC.printf("0x%X,",spi.write(buffer_112[i]));*/\
+            }\
+        }\
+        else{\
+            spi.write(0x18);\
+            spi.write(0x90);\
+            for(unsigned char i=0; i<112;i++){\
+                if(bypass_adf)\
+                    gPC.putc(buffer_112[i]);\
+                else\
+                    spi.write(buffer_112[i]);\
+                /*gPC.printf("0x%X,",spi.write(buffer_112[i]));*/\
+            }\
+        }\
+        gCS_ADF=1;\
+        wait_us(5);\
+        data_err=false;\
+        gCS_ADF=0;\
+        spi.write(0x38);\
+        if(buffer_state){\
+            spi.write(0x20);\
+            }\
+        else{\
+            spi.write(0x90);\
+            }\
+        spi.write(0xFF);\
+        for(unsigned char i=0; i<112;i++){\
+            temp_byte=spi.write(0xFF);\
+            if(buffer_112[i]!=temp_byte){\
+                data_err1[i]=1;\
+                data_err=true;\
+                }\
+        }\
     gCS_ADF=1;\
-    gCS_ADF=0;\
-    spi.write(0x09);\
-    spi.write(0x36);\
-    spi.write(0x70);\
-    gCS_ADF=1;\
-    gCS_ADF=0;\
-    spi.write(0x09);\
-    spi.write(0x39);\
-    spi.write(0x10);\
-    gCS_ADF=1;\
+    /*SPI_mutex.unlock();*/\
+    if(data_err==false){\
+    buffer_state = !buffer_state;\
+    }\
+    data_err_cnt++;\
+    if(last_buffer){\
+        finish_write_data = true;\
+           /*gPC.puts("adf_off\r\n");*/\
+        }\
+    }\
+}
+
+#define check {\
+    check_status;\
+    /*gPC.printf("I 0x%X\r\n",(int)status);*/\
+    if(IRQ || bypass_adf){\
+        /*gPC.printf("det\r\n");*/\
+        if(!ADF_off) {\
+            if(finish_write_data) {\
+                write_data;\
+                ADF_off=true;\
+            } else {\
+                write_data;\
+                if(sent_tmfrom_SDcard)\
+                send_tm_from_SD_card_fun();\
+                else snd_tm.transmit_data(buffer_112,&last_buffer);\
+            }\
+        } else {\
+            wait_ms(20);\
+            gCS_ADF=0;\
+            spi.write(0xB1);\
+            gCS_ADF=1;\
+            gPC.puts("transmission done\r\n");\
+            loop_on=false;\
+        }\
+    }\
+    else{\
+        if(T.read_us()>98000){\
+                data_irq_err=true;\
+                CMD(CMD_PHY_ON);\
+                gPC.printf("Data_error_detected");\
+                }\        
+        }\
+}
+
+#define send_data {\
     gCS_ADF=0;\
     spi.write(0xBB);\
     gCS_ADF=1;\
@@ -199,58 +427,7 @@
     spi.write(0xFF);\
     spi.write(0xFF);\
     gCS_ADF=1;\
-    SPI_mutex.unlock();\
-}
- 
-#define write_data {\
-    SPI_mutex.lock();\
-    gCS_ADF=0;\
-    spi.write(0x0B);\
-    spi.write(0x36);\
-    spi.write(0xFF);\
-    gCS_ADF=1;\
-    gCS_ADF=0;\
-    if(buffer_state){\
-        spi.write(0x18);\
-        spi.write(0x20);\
-        for(unsigned char i=0; i<112;i++){\
-            if(bypass_adf)\
-                gPC.putc(buffer_112[i]);\
-            else\
-                spi.write(buffer_112[i]);\
-            /*gPC.printf("%02X",buffer_112[i])*/;\
-        }\
-    }\
-    else{\
-        spi.write(0x18);\
-        spi.write(0x90);\
-        for(unsigned char i=0; i<112;i++){\
-            if(bypass_adf)\
-                gPC.putc(buffer_112[i]);\
-            else\
-                spi.write(buffer_112[i]);\
-            /*gPC.printf("%02X",buffer_112[i])*/;\
-        }\
-    }\
-    gCS_ADF=1;\
-    SPI_mutex.unlock();\
-    buffer_state = !buffer_state;\
-    if(last_buffer){\
-        finish_write_data = true;\
-        /*gPC.puts("adf_off\r\n");*/\
-    }\
-}
- 
-/* 
-void check(){   
-    if(IRQ){
-        gCOM_MNG_TMTC_THREAD->signal_set(signal);
-    }
-}*/
-  
- 
-#define send_data {\
-if(sent_tmfrom_SDcard){\
+    if(sent_tmfrom_SDcard){\
         send_tm_from_SD_card_fun();\
     }else{\
         snd_tm.transmit_data(buffer_112,&last_buffer);\
@@ -267,7 +444,6 @@
     }else{\
         snd_tm.transmit_data(buffer_112,&last_buffer);\
     }\
-    SPI_mutex.lock();\
     gCS_ADF=0;\
     spi.write(0xB1);\
     gCS_ADF=1;\
@@ -284,53 +460,112 @@
     spi.write(0xFF);\
     spi.write(0xFF);\
     gCS_ADF=1;\
-    SPI_mutex.unlock();\
-    /*ticker.attach_us(&check,32000);*/\
 }
- 
+  
+#define initial_adf_check {\
+    bool Configuration_Done=false;\
+    quit_configuration=false;\
+    bool reset_flag1 = 0;\
+    bool flag = false;\
+    while((hw_reset_err_cnt<HW_THRS)&&(quit_configuration==false)){\
+        while((bbram_err_cnt<2)&&(quit_configuration==false)){\
+            /*assrt_phy_off;*/\
+            /*Assrt_phy_off Begin*/\
+            {\
+    int state_err_cnt = 0;\
+    CMD(CMD_PHY_OFF);\
+    if(cmd_err_flag){\
+        temp_return=1;\
+        }\
+    else{\
+        for(int i = 0 ; i < 40 ;i++){\
+            CMD(CMD_PHY_OFF);\
+            check_status;\
+            if(status == PHY_OFF){\
+                temp_return = 0;\
+            break;\
+            }\
+            else if(state_err_cnt>THRS){\
+                temp_return = 1;\
+            break;\
+            }\
+            else {\
+                wait_ms(1);\
+            }\
+        }\
+    }\
+}\
+            /*Assrt_phy_off end*/\
+            reset_flag1=temp_return;\
+            if(!reset_flag1){\
+                bbram_write;\
+                while((rbp_err_cnt<RBP_THRS)&&(quit_configuration==false)){\
+                    bbram_check;\
+                    if(bbram_err==0){\
+                        bbram_write_success=true;\
+                        bbram_err_cnt=0;\
+                        initiate;\
+                        if(reg_err){\
+                            rbp_err_cnt++;\
+                            }\
+                        else{\
+                            rbp_err_cnt=0;\
+                            gPC.printf("NO Reg err\r\n");\
+                            CMD(CMD_CONFIG_DEV);\
+                            if(cmd_err_flag){\
+                                reset_flag=1;\
+                                gPC.printf("CMD ERR\r\n");\
+                            }\
+                            else{\
+                                reset_flag=0;\
+                                gPC.printf("NO CMD ERR CONFIG_DONE\r\n");\
+                                quit_configuration=true;\
+                            }\
+                        }\
+                    }\
+                    else{\
+                        bbram_write_success=false;\
+                        bbram_err_cnt++;\
+                        break;\
+                    }\
+                }\
+            }\
+            else{\
+                break;\
+            }\
+        }\
+        if(reset_flag1){\
+            hardware_reset(0);\
+            hw_reset_err_cnt++;\
+            gPC.puts("Resetting hardware\r\n");\
+        }\
+    }\
+    if(hw_reset_err_cnt==HW_THRS){\
+        power_reset_flag=1;\
+        power_reset_count++;\
+        }\
+    else{\
+        Configuration_Done=true;\
+        gPC.printf("Configuration_Done\n");\
+        }\
+}
+
 #define configure_adf {\
-    finish_write_data = false;\
-    buffer_state = true;\
-    last_buffer = false;\
-    loop_on = true;\
-    ADF_off = false;\
+    reset_flags;\
     initial_adf_check;\
-    gPC.puts("initial adf check\r\n");\
-    initiate;\
-    gPC.puts("adf configured\r\n");\
-    /*gLEDR = !gLEDR;*/\
+    gPC.puts("Config_part done\r\n");\
 }
  
 #define transmit_adf {\
     configure_adf;\
-    if(sent_tmfrom_SDcard)\
-    signal = COM_MNG_TMTC_SIGNAL_ADF_SD;\
-    else signal = COM_MNG_TMTC_SIGNAL_ADF_NSD;\
     send_data;\
+    CMD(CMD_PHY_TX);\
+    wait_us(2000);\
     while(loop_on){\
-        wait_ms(COM_TX_TICKER_LIMIT);\
-        if(IRQ || bypass_adf){\
-            if(finish_write_data){\
-                if(ADF_off){\
-                    SPI_mutex.lock();\ 
-                    gCS_ADF=0;\
-                    spi.write(0xB1);\
-                    gCS_ADF=1;\
-                    SPI_mutex.unlock();\
-                    loop_on = false;\
-                    gPC.puts("Transmission done\r\n");\
-                    gLEDR = 1;\
-                }\
-                else{\
-                    ADF_off = true;\
-                }\
-            }else{\ 
-                gLEDG = !gLEDG;\  
-                write_data;\
-                if(sent_tmfrom_SDcard)\
-                send_tm_from_SD_card_fun();\
-                else snd_tm.transmit_data(buffer_112,&last_buffer);\ 
-            }\
+        wait_us(20);\
+        check;\
+        if(data_irq_err){\
+        break;\
         }\
     }\
     /*gPC.puts("after while loop\r\n");*/\
--- a/cdms_rtc.h	Sat Jul 09 13:11:25 2016 +0000
+++ b/cdms_rtc.h	Sun Jul 10 13:47:26 2016 +0000
@@ -40,22 +40,22 @@
     
     gCS_RTC=0;
     spi.write(0x80); 
-    spi.write(0x01); // set milliseconds value to 00
+    spi.write(0x00); // set milliseconds value to 00
     gCS_RTC=1;
  
     gCS_RTC=0;
     spi.write(0x81); 
-    spi.write(0x01); //set seconds value to 00
+    spi.write(0x00); //set seconds value to 00
     gCS_RTC=1;
  
     gCS_RTC=0;
     spi.write(0x82); 
-    spi.write(0x01);//set minutes value to 00
+    spi.write(0x00);//set minutes value to 00
     gCS_RTC=1;
  
     gCS_RTC=0;
     spi.write(0x83); 
-    spi.write(0x23); //set the hours to 01
+    spi.write(0x00); //set the hours to 01
     gCS_RTC=1;
     
     gCS_RTC=0;
@@ -65,17 +65,17 @@
     
     gCS_RTC=0;
     spi.write(0x85); 
-    spi.write(0x31); //set date of the month to 01
+    spi.write(0x01); //set date of the month to 01
     gCS_RTC=1;
     
     gCS_RTC=0;
     spi.write(0x86); 
-    spi.write(0x12); //set month to 01
+    spi.write(0x01); //set month to 01
     gCS_RTC=1;
     
     gCS_RTC=0;
     spi.write(0x87); 
-    spi.write(0x01); //set year to 00(2000)
+    spi.write(0x00); //set year to 00(2000)
     gCS_RTC=1;
     gPC.puts("\n\r rtc initalised \n");
     SPI_mutex.unlock();
--- a/dmaSPIslave.h	Sat Jul 09 13:11:25 2016 +0000
+++ b/dmaSPIslave.h	Sun Jul 10 13:47:26 2016 +0000
@@ -41,6 +41,13 @@
 
         }
         
+        void bulkRead_pause(){
+            read_dma.attach(NULL);
+            }
+            
+        void bulkRead_resume(void (*fun)(void)){
+            read_dma.attach(fun);
+            }
 /*
 @brief:     start the dma read process : has to be done everytime the buffer gets filled, can be used repeatedly
 @param:     none
@@ -73,4 +80,4 @@
         int length;
         SimpleDMA read_dma;
 };
-#endif
\ No newline at end of file
+#endif
--- a/main.cpp	Sat Jul 09 13:11:25 2016 +0000
+++ b/main.cpp	Sun Jul 10 13:47:26 2016 +0000
@@ -118,7 +118,7 @@
     gCS_RTC = 1;
     gCS_ADF = 1;
     
-    //FCTN_CDMS_INIT_RTC();/* rtc initialization*/
+    FCTN_CDMS_INIT_RTC();/* rtc initialization*/
     FCTN_CDMS_SD_INIT();/* sd card initialization*/
     
     
@@ -146,7 +146,7 @@
     
     
     master.frequency(400000);
-    PL_wo_dma = new RtosTimer(payload_isr_fun_dma, osTimerPeriodic,(void * )NULL);
+    //PL_wo_dma = new RtosTimer(payload_isr_fun_dma, osTimerPeriodic,(void * )NULL);
     //PL_wo_dma->start(6000);//
     //gSCIENCE_THREAD->signal_set(SCIENCE_SIGNAL);
     
@@ -167,6 +167,11 @@
     //RtosTimer gCDMS_HK_TIMER(FCTN_CDMS_HK_MAIN, osTimerPeriodic);
     //gCDMS_HK_TIMER.start(5000);
     
+    /*test_pl_main();
+    
+    RtosTimer gCDMS_PL_TIMER(FCTN_CDMS_PL_MAIN, osTimerPeriodic);
+    gCDMS_PL_TIMER.start(10000);
+    */
     /*starting the thread with signal*/
     //set_sig();
     //payload_isr_fun();