Peter Drescher
mbed library with additional peripherals for ST F401 board
Fork of
mbed-src
by 
mbed official
This mbed LIB has additional peripherals for ST F401 board
- UART2 : PA_3 rx, PA_2 tx
- UART3 : PC_7 rx, PC_6 tx
- I2C2 : PB_3 SDA, PB_10 SCL
- I2C3 : PB_4 SDA, PA_8 SCL
Revision 69:49e45cb70de1, committed 2013-12-31
- Comitter:
- mbed_official
- Date:
- Tue Dec 31 15:30:05 2013 +0000
- Parent:
- 68:41613245dfd7
- Child:
- 70:c1fbde68b492
- Commit message:
- Synchronized with git revision b311c56b44e2f3d58c5a425453fba9dfaa0b13e3
Full URL: https://github.com/mbedmicro/mbed/commit/b311c56b44e2f3d58c5a425453fba9dfaa0b13e3/
[LPC812] Add SPISlave function
Changed in this revision
--- a/api/InterruptIn.h Thu Dec 26 13:00:06 2013 +0000
+++ b/api/InterruptIn.h Tue Dec 31 15:30:05 2013 +0000
@@ -108,11 +108,13 @@
*/
void mode(PinMode pull);
- /** Enable IRQ
+ /** Enable IRQ. This method depends on hw implementation, might enable one
+ * port interrupts. For further information, check gpio_irq_enable().
*/
void enable_irq();
- /** Disable IRQ
+ /** Disable IRQ. This method depends on hw implementation, might disable one
+ * port interrupts. For further information, check gpio_irq_disable().
*/
void disable_irq();
--- a/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/MKL46Z4.h Thu Dec 26 13:00:06 2013 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL46Z/MKL46Z4.h Tue Dec 31 15:30:05 2013 +0000
@@ -12,13 +12,13 @@
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
-** Reference manual: KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
-** Version: rev. 2.0, 2012-12-12
+** Reference manual: KL46P121M48SF4RM, Rev.2, Dec 2012
+** Version: rev. 2.2, 2013-04-12
**
** Abstract:
** CMSIS Peripheral Access Layer for MKL46Z4
**
-** Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved.
+** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
@@ -28,14 +28,19 @@
** Initial version.
** - rev. 2.0 (2012-12-12)
** Update to reference manual rev. 1.
+** - rev. 2.1 (2013-04-05)
+** Changed start of doxygen comment.
+** - rev. 2.2 (2013-04-12)
+** SystemInit function fixed for clock configuration 1.
+** Name of the interrupt num. 31 updated to reflect proper function.
**
** ###################################################################
*/
-/**
+/*!
* @file MKL46Z4.h
- * @version 2.0
- * @date 2012-12-12
+ * @version 2.2
+ * @date 2013-04-12
* @brief CMSIS Peripheral Access Layer for MKL46Z4
*
* CMSIS Peripheral Access Layer for MKL46Z4
@@ -48,14 +53,14 @@
* compatible) */
#define MCU_MEM_MAP_VERSION 0x0200u
/** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0000u
+#define MCU_MEM_MAP_VERSION_MINOR 0x0002u
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
@@ -101,10 +106,10 @@
LPTimer_IRQn = 28, /**< LPTimer interrupt */
LCD_IRQn = 29, /**< Segment LCD Interrupt */
PORTA_IRQn = 30, /**< Port A interrupt */
- PORTD_IRQn = 31 /**< Port D interrupt */
+ PORTC_PORTD_IRQn = 31 /**< Port C and port D interrupt */
} IRQn_Type;
-/**
+/*!
* @}
*/ /* end of group Interrupt_vector_numbers */
@@ -113,7 +118,7 @@
-- Cortex M0 Core Configuration
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
* @{
*/
@@ -127,7 +132,7 @@
#include "core_cm0plus.h" /* Core Peripheral Access Layer */
#include "system_MKL46Z4.h" /* Device specific configuration file */
-/**
+/*!
* @}
*/ /* end of group Cortex_Core_Configuration */
@@ -136,7 +141,7 @@
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
* @{
*/
@@ -164,7 +169,7 @@
-- ADC Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
* @{
*/
@@ -203,7 +208,7 @@
-- ADC Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup ADC_Register_Masks ADC Register Masks
* @{
*/
@@ -351,7 +356,7 @@
#define ADC_CLM0_CLM0_SHIFT 0
#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
-/**
+/*!
* @}
*/ /* end of group ADC_Register_Masks */
@@ -364,7 +369,7 @@
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASES { ADC0 }
-/**
+/*!
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
@@ -373,7 +378,7 @@
-- CMP Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
* @{
*/
@@ -392,7 +397,7 @@
-- CMP Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup CMP_Register_Masks CMP Register Masks
* @{
*/
@@ -456,7 +461,7 @@
#define CMP_MUXCR_PSTM_MASK 0x80u
#define CMP_MUXCR_PSTM_SHIFT 7
-/**
+/*!
* @}
*/ /* end of group CMP_Register_Masks */
@@ -469,7 +474,7 @@
/** Array initializer of CMP peripheral base pointers */
#define CMP_BASES { CMP0 }
-/**
+/*!
* @}
*/ /* end of group CMP_Peripheral_Access_Layer */
@@ -478,7 +483,7 @@
-- DAC Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
* @{
*/
@@ -500,7 +505,7 @@
-- DAC Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup DAC_Register_Masks DAC Register Masks
* @{
*/
@@ -546,7 +551,7 @@
#define DAC_C2_DACBFRP_MASK 0x10u
#define DAC_C2_DACBFRP_SHIFT 4
-/**
+/*!
* @}
*/ /* end of group DAC_Register_Masks */
@@ -559,7 +564,7 @@
/** Array initializer of DAC peripheral base pointers */
#define DAC_BASES { DAC0 }
-/**
+/*!
* @}
*/ /* end of group DAC_Peripheral_Access_Layer */
@@ -568,7 +573,7 @@
-- DMA Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
* @{
*/
@@ -594,7 +599,7 @@
-- DMA Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup DMA_Register_Masks DMA Register Masks
* @{
*/
@@ -664,7 +669,7 @@
#define DMA_DCR_EINT_MASK 0x80000000u
#define DMA_DCR_EINT_SHIFT 31
-/**
+/*!
* @}
*/ /* end of group DMA_Register_Masks */
@@ -677,7 +682,7 @@
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASES { DMA0 }
-/**
+/*!
* @}
*/ /* end of group DMA_Peripheral_Access_Layer */
@@ -686,7 +691,7 @@
-- DMAMUX Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
* @{
*/
@@ -700,7 +705,7 @@
-- DMAMUX Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
* @{
*/
@@ -714,7 +719,7 @@
#define DMAMUX_CHCFG_ENBL_MASK 0x80u
#define DMAMUX_CHCFG_ENBL_SHIFT 7
-/**
+/*!
* @}
*/ /* end of group DMAMUX_Register_Masks */
@@ -727,7 +732,7 @@
/** Array initializer of DMAMUX peripheral base pointers */
#define DMAMUX_BASES { DMAMUX0 }
-/**
+/*!
* @}
*/ /* end of group DMAMUX_Peripheral_Access_Layer */
@@ -736,7 +741,7 @@
-- FGPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
* @{
*/
@@ -755,7 +760,7 @@
-- FGPIO Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup FGPIO_Register_Masks FGPIO Register Masks
* @{
*/
@@ -785,7 +790,7 @@
#define FGPIO_PDDR_PDD_SHIFT 0
#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
-/**
+/*!
* @}
*/ /* end of group FGPIO_Register_Masks */
@@ -814,7 +819,7 @@
/** Array initializer of FGPIO peripheral base pointers */
#define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
-/**
+/*!
* @}
*/ /* end of group FGPIO_Peripheral_Access_Layer */
@@ -823,7 +828,7 @@
-- FTFA Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
* @{
*/
@@ -856,7 +861,7 @@
-- FTFA Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup FTFA_Register_Masks FTFA Register Masks
* @{
*/
@@ -963,7 +968,7 @@
#define FTFA_FPROT0_PROT_SHIFT 0
#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
-/**
+/*!
* @}
*/ /* end of group FTFA_Register_Masks */
@@ -976,7 +981,7 @@
/** Array initializer of FTFA peripheral base pointers */
#define FTFA_BASES { FTFA }
-/**
+/*!
* @}
*/ /* end of group FTFA_Peripheral_Access_Layer */
@@ -985,7 +990,7 @@
-- GPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
* @{
*/
@@ -1004,7 +1009,7 @@
-- GPIO Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup GPIO_Register_Masks GPIO Register Masks
* @{
*/
@@ -1034,7 +1039,7 @@
#define GPIO_PDDR_PDD_SHIFT 0
#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
-/**
+/*!
* @}
*/ /* end of group GPIO_Register_Masks */
@@ -1063,7 +1068,7 @@
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
-/**
+/*!
* @}
*/ /* end of group GPIO_Peripheral_Access_Layer */
@@ -1072,7 +1077,7 @@
-- I2C Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
* @{
*/
@@ -1097,7 +1102,7 @@
-- I2C Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup I2C_Register_Masks I2C Register Masks
* @{
*/
@@ -1209,7 +1214,7 @@
#define I2C_SLTL_SSLT_SHIFT 0
#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
-/**
+/*!
* @}
*/ /* end of group I2C_Register_Masks */
@@ -1226,7 +1231,7 @@
/** Array initializer of I2C peripheral base pointers */
#define I2C_BASES { I2C0, I2C1 }
-/**
+/*!
* @}
*/ /* end of group I2C_Peripheral_Access_Layer */
@@ -1235,7 +1240,7 @@
-- I2S Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
* @{
*/
@@ -1272,7 +1277,7 @@
-- I2S Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup I2S_Register_Masks I2S Register Masks
* @{
*/
@@ -1451,7 +1456,7 @@
#define I2S_MDR_FRACT_SHIFT 12
#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
-/**
+/*!
* @}
*/ /* end of group I2S_Register_Masks */
@@ -1464,7 +1469,7 @@
/** Array initializer of I2S peripheral base pointers */
#define I2S_BASES { I2S0 }
-/**
+/*!
* @}
*/ /* end of group I2S_Peripheral_Access_Layer */
@@ -1473,7 +1478,7 @@
-- LCD Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
* @{
*/
@@ -1496,7 +1501,7 @@
-- LCD Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup LCD_Register_Masks LCD Register Masks
* @{
*/
@@ -2798,7 +2803,7 @@
#define LCD_WF8B_BPHLCD7_MASK 0x80u
#define LCD_WF8B_BPHLCD7_SHIFT 7
-/**
+/*!
* @}
*/ /* end of group LCD_Register_Masks */
@@ -2811,7 +2816,7 @@
/** Array initializer of LCD peripheral base pointers */
#define LCD_BASES { LCD }
-/**
+/*!
* @}
*/ /* end of group LCD_Peripheral_Access_Layer */
@@ -2820,7 +2825,7 @@
-- LLWU Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
* @{
*/
@@ -2843,7 +2848,7 @@
-- LLWU Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup LLWU_Register_Masks LLWU Register Masks
* @{
*/
@@ -2987,7 +2992,7 @@
#define LLWU_FILT2_FILTF_MASK 0x80u
#define LLWU_FILT2_FILTF_SHIFT 7
-/**
+/*!
* @}
*/ /* end of group LLWU_Register_Masks */
@@ -3000,7 +3005,7 @@
/** Array initializer of LLWU peripheral base pointers */
#define LLWU_BASES { LLWU }
-/**
+/*!
* @}
*/ /* end of group LLWU_Peripheral_Access_Layer */
@@ -3009,7 +3014,7 @@
-- LPTMR Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
* @{
*/
@@ -3026,7 +3031,7 @@
-- LPTMR Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
* @{
*/
@@ -3065,7 +3070,7 @@
#define LPTMR_CNR_COUNTER_SHIFT 0
#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
-/**
+/*!
* @}
*/ /* end of group LPTMR_Register_Masks */
@@ -3078,7 +3083,7 @@
/** Array initializer of LPTMR peripheral base pointers */
#define LPTMR_BASES { LPTMR0 }
-/**
+/*!
* @}
*/ /* end of group LPTMR_Peripheral_Access_Layer */
@@ -3087,7 +3092,7 @@
-- MCG Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
* @{
*/
@@ -3116,7 +3121,7 @@
-- MCG Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup MCG_Register_Masks MCG Register Masks
* @{
*/
@@ -3225,7 +3230,7 @@
#define MCG_C8_LOLRE_MASK 0x40u
#define MCG_C8_LOLRE_SHIFT 6
-/**
+/*!
* @}
*/ /* end of group MCG_Register_Masks */
@@ -3238,7 +3243,7 @@
/** Array initializer of MCG peripheral base pointers */
#define MCG_BASES { MCG }
-/**
+/*!
* @}
*/ /* end of group MCG_Peripheral_Access_Layer */
@@ -3247,7 +3252,7 @@
-- MCM Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
* @{
*/
@@ -3266,7 +3271,7 @@
-- MCM Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup MCM_Register_Masks MCM Register Masks
* @{
*/
@@ -3304,7 +3309,7 @@
#define MCM_CPO_CPOWOI_MASK 0x4u
#define MCM_CPO_CPOWOI_SHIFT 2
-/**
+/*!
* @}
*/ /* end of group MCM_Register_Masks */
@@ -3317,7 +3322,7 @@
/** Array initializer of MCM peripheral base pointers */
#define MCM_BASES { MCM }
-/**
+/*!
* @}
*/ /* end of group MCM_Peripheral_Access_Layer */
@@ -3326,7 +3331,7 @@
-- MTB Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
* @{
*/
@@ -3358,7 +3363,7 @@
-- MTB Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup MTB_Register_Masks MTB Register Masks
* @{
*/
@@ -3447,7 +3452,7 @@
#define MTB_COMPID_COMPID_SHIFT 0
#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
-/**
+/*!
* @}
*/ /* end of group MTB_Register_Masks */
@@ -3460,7 +3465,7 @@
/** Array initializer of MTB peripheral base pointers */
#define MTB_BASES { MTB }
-/**
+/*!
* @}
*/ /* end of group MTB_Peripheral_Access_Layer */
@@ -3469,7 +3474,7 @@
-- MTBDWT Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
* @{
*/
@@ -3497,7 +3502,7 @@
-- MTBDWT Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
* @{
*/
@@ -3556,7 +3561,7 @@
#define MTBDWT_COMPID_COMPID_SHIFT 0
#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
-/**
+/*!
* @}
*/ /* end of group MTBDWT_Register_Masks */
@@ -3569,7 +3574,7 @@
/** Array initializer of MTBDWT peripheral base pointers */
#define MTBDWT_BASES { MTBDWT }
-/**
+/*!
* @}
*/ /* end of group MTBDWT_Peripheral_Access_Layer */
@@ -3578,7 +3583,7 @@
-- NV Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
* @{
*/
@@ -3605,7 +3610,7 @@
-- NV Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup NV_Register_Masks NV Register Masks
* @{
*/
@@ -3683,7 +3688,7 @@
#define NV_FOPT_FAST_INIT_MASK 0x20u
#define NV_FOPT_FAST_INIT_SHIFT 5
-/**
+/*!
* @}
*/ /* end of group NV_Register_Masks */
@@ -3696,7 +3701,7 @@
/** Array initializer of NV peripheral base pointers */
#define NV_BASES { FTFA_FlashConfig }
-/**
+/*!
* @}
*/ /* end of group NV_Peripheral_Access_Layer */
@@ -3705,7 +3710,7 @@
-- OSC Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
* @{
*/
@@ -3719,7 +3724,7 @@
-- OSC Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup OSC_Register_Masks OSC Register Masks
* @{
*/
@@ -3738,7 +3743,7 @@
#define OSC_CR_ERCLKEN_MASK 0x80u
#define OSC_CR_ERCLKEN_SHIFT 7
-/**
+/*!
* @}
*/ /* end of group OSC_Register_Masks */
@@ -3751,7 +3756,7 @@
/** Array initializer of OSC peripheral base pointers */
#define OSC_BASES { OSC0 }
-/**
+/*!
* @}
*/ /* end of group OSC_Peripheral_Access_Layer */
@@ -3760,7 +3765,7 @@
-- PIT Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
* @{
*/
@@ -3784,7 +3789,7 @@
-- PIT Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup PIT_Register_Masks PIT Register Masks
* @{
*/
@@ -3821,7 +3826,7 @@
#define PIT_TFLG_TIF_MASK 0x1u
#define PIT_TFLG_TIF_SHIFT 0
-/**
+/*!
* @}
*/ /* end of group PIT_Register_Masks */
@@ -3834,7 +3839,7 @@
/** Array initializer of PIT peripheral base pointers */
#define PIT_BASES { PIT }
-/**
+/*!
* @}
*/ /* end of group PIT_Peripheral_Access_Layer */
@@ -3843,7 +3848,7 @@
-- PMC Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
* @{
*/
@@ -3859,7 +3864,7 @@
-- PMC Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup PMC_Register_Masks PMC Register Masks
* @{
*/
@@ -3896,7 +3901,7 @@
#define PMC_REGSC_BGEN_MASK 0x10u
#define PMC_REGSC_BGEN_SHIFT 4
-/**
+/*!
* @}
*/ /* end of group PMC_Register_Masks */
@@ -3909,7 +3914,7 @@
/** Array initializer of PMC peripheral base pointers */
#define PMC_BASES { PMC }
-/**
+/*!
* @}
*/ /* end of group PMC_Peripheral_Access_Layer */
@@ -3918,7 +3923,7 @@
-- PORT Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
* @{
*/
@@ -3936,7 +3941,7 @@
-- PORT Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup PORT_Register_Masks PORT Register Masks
* @{
*/
@@ -3979,7 +3984,7 @@
#define PORT_ISFR_ISF_SHIFT 0
#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
-/**
+/*!
* @}
*/ /* end of group PORT_Register_Masks */
@@ -4008,7 +4013,7 @@
/** Array initializer of PORT peripheral base pointers */
#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
-/**
+/*!
* @}
*/ /* end of group PORT_Peripheral_Access_Layer */
@@ -4017,7 +4022,7 @@
-- RCM Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
* @{
*/
@@ -4035,7 +4040,7 @@
-- RCM Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup RCM_Register_Masks RCM Register Masks
* @{
*/
@@ -4075,7 +4080,7 @@
#define RCM_RPFW_RSTFLTSEL_SHIFT 0
#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
-/**
+/*!
* @}
*/ /* end of group RCM_Register_Masks */
@@ -4088,7 +4093,7 @@
/** Array initializer of RCM peripheral base pointers */
#define RCM_BASES { RCM }
-/**
+/*!
* @}
*/ /* end of group RCM_Peripheral_Access_Layer */
@@ -4097,7 +4102,7 @@
-- ROM Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
* @{
*/
@@ -4123,7 +4128,7 @@
-- ROM Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup ROM_Register_Masks ROM Register Masks
* @{
*/
@@ -4177,7 +4182,7 @@
#define ROM_COMPID_COMPID_SHIFT 0
#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
-/**
+/*!
* @}
*/ /* end of group ROM_Register_Masks */
@@ -4190,7 +4195,7 @@
/** Array initializer of ROM peripheral base pointers */
#define ROM_BASES { ROM }
-/**
+/*!
* @}
*/ /* end of group ROM_Peripheral_Access_Layer */
@@ -4199,7 +4204,7 @@
-- RTC Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
* @{
*/
@@ -4220,7 +4225,7 @@
-- RTC Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup RTC_Register_Masks RTC Register Masks
* @{
*/
@@ -4301,7 +4306,7 @@
#define RTC_IER_WPON_MASK 0x80u
#define RTC_IER_WPON_SHIFT 7
-/**
+/*!
* @}
*/ /* end of group RTC_Register_Masks */
@@ -4314,7 +4319,7 @@
/** Array initializer of RTC peripheral base pointers */
#define RTC_BASES { RTC }
-/**
+/*!
* @}
*/ /* end of group RTC_Peripheral_Access_Layer */
@@ -4323,7 +4328,7 @@
-- SIM Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
* @{
*/
@@ -4363,7 +4368,7 @@
-- SIM Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup SIM_Register_Masks SIM Register Masks
* @{
*/
@@ -4567,7 +4572,7 @@
#define SIM_SRVCOP_SRVCOP_SHIFT 0
#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
-/**
+/*!
* @}
*/ /* end of group SIM_Register_Masks */
@@ -4580,7 +4585,7 @@
/** Array initializer of SIM peripheral base pointers */
#define SIM_BASES { SIM }
-/**
+/*!
* @}
*/ /* end of group SIM_Peripheral_Access_Layer */
@@ -4589,7 +4594,7 @@
-- SMC Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
* @{
*/
@@ -4606,7 +4611,7 @@
-- SMC Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup SMC_Register_Masks SMC Register Masks
* @{
*/
@@ -4641,7 +4646,7 @@
#define SMC_PMSTAT_PMSTAT_SHIFT 0
#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
-/**
+/*!
* @}
*/ /* end of group SMC_Register_Masks */
@@ -4654,7 +4659,7 @@
/** Array initializer of SMC peripheral base pointers */
#define SMC_BASES { SMC }
-/**
+/*!
* @}
*/ /* end of group SMC_Peripheral_Access_Layer */
@@ -4663,7 +4668,7 @@
-- SPI Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
* @{
*/
@@ -4687,7 +4692,7 @@
-- SPI Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup SPI_Register_Masks SPI Register Masks
* @{
*/
@@ -4797,7 +4802,7 @@
#define SPI_C3_TNEAREF_MARK_MASK 0x20u
#define SPI_C3_TNEAREF_MARK_SHIFT 5
-/**
+/*!
* @}
*/ /* end of group SPI_Register_Masks */
@@ -4814,7 +4819,7 @@
/** Array initializer of SPI peripheral base pointers */
#define SPI_BASES { SPI0, SPI1 }
-/**
+/*!
* @}
*/ /* end of group SPI_Peripheral_Access_Layer */
@@ -4823,7 +4828,7 @@
-- TPM Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
* @{
*/
@@ -4847,7 +4852,7 @@
-- TPM Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup TPM_Register_Masks TPM Register Masks
* @{
*/
@@ -4927,7 +4932,7 @@
#define TPM_CONF_TRGSEL_SHIFT 24
#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
-/**
+/*!
* @}
*/ /* end of group TPM_Register_Masks */
@@ -4948,7 +4953,7 @@
/** Array initializer of TPM peripheral base pointers */
#define TPM_BASES { TPM0, TPM1, TPM2 }
-/**
+/*!
* @}
*/ /* end of group TPM_Peripheral_Access_Layer */
@@ -4957,7 +4962,7 @@
-- TSI Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
* @{
*/
@@ -4973,7 +4978,7 @@
-- TSI Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup TSI_Register_Masks TSI Register Masks
* @{
*/
@@ -5034,7 +5039,7 @@
#define TSI_TSHD_THRESH_SHIFT 16
#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
-/**
+/*!
* @}
*/ /* end of group TSI_Register_Masks */
@@ -5047,7 +5052,7 @@
/** Array initializer of TSI peripheral base pointers */
#define TSI_BASES { TSI0 }
-/**
+/*!
* @}
*/ /* end of group TSI_Peripheral_Access_Layer */
@@ -5056,7 +5061,7 @@
-- UART Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
* @{
*/
@@ -5078,7 +5083,7 @@
-- UART Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup UART_Register_Masks UART Register Masks
* @{
*/
@@ -5203,7 +5208,7 @@
#define UART_C4_TDMAS_MASK 0x80u
#define UART_C4_TDMAS_SHIFT 7
-/**
+/*!
* @}
*/ /* end of group UART_Register_Masks */
@@ -5220,7 +5225,7 @@
/** Array initializer of UART peripheral base pointers */
#define UART_BASES { UART1, UART2 }
-/**
+/*!
* @}
*/ /* end of group UART_Peripheral_Access_Layer */
@@ -5229,7 +5234,7 @@
-- UART0 Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
* @{
*/
@@ -5254,7 +5259,7 @@
-- UART0 Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup UART0_Register_Masks UART0 Register Masks
* @{
*/
@@ -5403,7 +5408,7 @@
#define UART0_C5_TDMAE_MASK 0x80u
#define UART0_C5_TDMAE_SHIFT 7
-/**
+/*!
* @}
*/ /* end of group UART0_Register_Masks */
@@ -5416,7 +5421,7 @@
/** Array initializer of UART0 peripheral base pointers */
#define UART0_BASES { UART0 }
-/**
+/*!
* @}
*/ /* end of group UART0_Peripheral_Access_Layer */
@@ -5425,7 +5430,7 @@
-- USB Peripheral Access Layer
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
* @{
*/
@@ -5495,7 +5500,7 @@
-- USB Register Masks
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup USB_Register_Masks USB Register Masks
* @{
*/
@@ -5736,7 +5741,7 @@
#define USB_USBFRMADJUST_ADJ_SHIFT 0
#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
-/**
+/*!
* @}
*/ /* end of group USB_Register_Masks */
@@ -5749,7 +5754,7 @@
/** Array initializer of USB peripheral base pointers */
#define USB_BASES { USB0 }
-/**
+/*!
* @}
*/ /* end of group USB_Peripheral_Access_Layer */
@@ -5770,7 +5775,7 @@
#error Not supported compiler type
#endif
-/**
+/*!
* @}
*/ /* end of group Peripheral_access_layer */
@@ -5779,14 +5784,14 @@
-- Backward Compatibility
---------------------------------------------------------------------------- */
-/**
+/*!
* @addtogroup Backward_Compatibility_Symbols Backward Compatibility
* @{
*/
/* No backward compatibility issues. */
-/**
+/*!
* @}
*/ /* end of group Backward_Compatibility_Symbols */
--- a/targets/hal/TARGET_Freescale/TARGET_KL46Z/gpio_irq_api.c Thu Dec 26 13:00:06 2013 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL46Z/gpio_irq_api.c Tue Dec 31 15:30:05 2013 +0000
@@ -19,7 +19,7 @@
#include "gpio_irq_api.h"
#include "error.h"
-#define CHANNEL_NUM 64
+#define CHANNEL_NUM 96
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler;
@@ -37,7 +37,8 @@
if (port->ISFR & pmask) {
mask |= pmask;
uint32_t id = channel_ids[ch_base + i];
- if (id == 0) continue;
+ if (id == 0)
+ continue;
FGPIO_Type *gpio;
gpio_irq_event event = IRQ_NONE;
@@ -51,7 +52,13 @@
break;
case IRQ_EITHER_EDGE:
- gpio = (port == PORTA) ? (FPTA) : (FPTD);
+ if (port == PORTA) {
+ gpio = FPTA;
+ } else if (port == PORTC) {
+ gpio = FPTC;
+ } else {
+ gpio = FPTD;
+ }
event = (gpio->PDIR & pmask) ? (IRQ_RISE) : (IRQ_FALL);
break;
}
@@ -62,11 +69,22 @@
port->ISFR = mask;
}
-void gpio_irqA(void) {handle_interrupt_in(PORTA, 0);}
-void gpio_irqD(void) {handle_interrupt_in(PORTD, 32);}
+void gpio_irqA(void) {
+ handle_interrupt_in(PORTA, 0);
+}
+
+/* PORTC and PORTD share same vector */
+void gpio_irqCD(void) {
+ if ((SIM->SCGC5 & SIM_SCGC5_PORTC_MASK) && (PORTC->ISFR)) {
+ handle_interrupt_in(PORTC, 32);
+ } else if ((SIM->SCGC5 & SIM_SCGC5_PORTD_MASK) && (PORTD->ISFR)) {
+ handle_interrupt_in(PORTD, 64);
+ }
+}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
- if (pin == NC) return -1;
+ if (pin == NC)
+ return -1;
irq_handler = handler;
@@ -80,12 +98,16 @@
ch_base = 0; irq_n = PORTA_IRQn; vector = (uint32_t)gpio_irqA;
break;
+ case PortC:
+ ch_base = 32; irq_n = PORTC_PORTD_IRQn; vector = (uint32_t)gpio_irqCD;
+ break;
+
case PortD:
- ch_base = 32; irq_n = PORTD_IRQn; vector = (uint32_t)gpio_irqD;
+ ch_base = 64; irq_n = PORTC_PORTD_IRQn; vector = (uint32_t)gpio_irqCD;
break;
default:
- error("gpio_irq only supported on port A and D\n");
+ error("gpio_irq only supported on port A,C and D\n");
break;
}
NVIC_SetVector(irq_n, vector);
@@ -147,15 +169,15 @@
void gpio_irq_enable(gpio_irq_t *obj) {
if (obj->port == PortA) {
NVIC_EnableIRQ(PORTA_IRQn);
- } else if (obj->port == PortD) {
- NVIC_EnableIRQ(PORTD_IRQn);
+ } else {
+ NVIC_EnableIRQ(PORTC_PORTD_IRQn);
}
}
void gpio_irq_disable(gpio_irq_t *obj) {
if (obj->port == PortA) {
NVIC_DisableIRQ(PORTA_IRQn);
- } else if (obj->port == PortD) {
- NVIC_DisableIRQ(PORTD_IRQn);
+ } else {
+ NVIC_DisableIRQ(PORTC_PORTD_IRQn);
}
}
--- a/targets/hal/TARGET_NXP/TARGET_LPC81X/device.h Thu Dec 26 13:00:06 2013 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/device.h Tue Dec 31 15:30:05 2013 +0000 @@ -32,7 +32,7 @@ #define DEVICE_I2CSLAVE 0 #define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 0 +#define DEVICE_SPISLAVE 1 #define DEVICE_CAN 0
--- a/targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c Thu Dec 26 13:00:06 2013 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c Tue Dec 31 15:30:05 2013 +0000
@@ -183,9 +183,9 @@
}
static inline int ssp_busy(spi_t *obj) {
- // TODO
- return 0;
-}
+ // checking RXOV(Receiver Overrun interrupt flag)
+ return obj->spi->STAT & (1 << 2);
+ }
int spi_master_write(spi_t *obj, int value) {
ssp_write(obj, value);